#include "main.h"
#include "sysdeps.h"
#include "hatari-glue.h"
#include "maccess.h"
#include "memory.h"
#include "custom.h"
#include "newcpu.h"
#include "cpu_prefetch.h"
#include "cputbl.h"
#include "debugmem.h"
#define SET_ALWAYS_CFLG(x) SET_CFLG(x)
#define SET_ALWAYS_NFLG(x) SET_NFLG(x)
/* OR.B #<data>.B,Dn */
uae_u32 REGPARAM2 op_0000_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 8;  
	uae_s8 src = (uae_u8)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = m68k_dreg(regs, dstreg);
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8 (2/0) */
/* 4 0,0   */

/* OR.B #<data>.B,(An) */
uae_u32 REGPARAM2 op_0010_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 16; 
	uae_s8 src = (uae_u8)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_byte_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 4 0,0   */

/* OR.B #<data>.B,(An)+ */
uae_u32 REGPARAM2 op_0018_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 16; 
	uae_s8 src = (uae_u8)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_byte_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 4 0,0   */

/* OR.B #<data>.B,-(An) */
uae_u32 REGPARAM2 op_0020_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 18; 
	uae_s8 src = (uae_u8)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, dstreg) = dsta;
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) = dsta;
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_byte_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (3/1) */
/* 4 0,0   */

/* OR.B #<data>.B,(d16,An) */
uae_u32 REGPARAM2 op_0028_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 20; 
	uae_s8 src = (uae_u8)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_byte_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (4/1) */
/* 6 0,0   */

/* OR.B #<data>.B,(d8,An,Xn) */
uae_u32 REGPARAM2 op_0030_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 22; 
	uae_s8 src = (uae_u8)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	BusCyclePenalty += 2;
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_000_prefetch(6));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_byte_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return 22 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 22 * CYCLE_UNIT / 2 + count_cycles;
}
/* 22 (4/1) */
/* 6 4,0   */

/* OR.B #<data>.B,(xxx).W */
uae_u32 REGPARAM2 op_0038_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 1;
	CurrentInstrCycles = 20; 
	uae_s8 src = (uae_u8)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, 0);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_byte_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (4/1) */
/* 6 0,0   */

/* OR.B #<data>.B,(xxx).L */
uae_u32 REGPARAM2 op_0039_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 1;
	CurrentInstrCycles = 24; 
	uae_s8 src = (uae_u8)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = get_word_000_prefetch(6) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	dsta |= get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 8, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(10);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 10, pcoffset);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_byte_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(10);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(8);
	return 24 * CYCLE_UNIT / 2 + count_cycles;
}
/* 24 (5/1) */
/* 8 0,0   */

/* ORSR.B #<data>.W */
uae_u32 REGPARAM2 op_003c_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 4;
	CurrentInstrCycles = 16; 
	MakeSR();
	uae_s16 src = regs.irc;
	src &= 0xFF;
	regs.sr |= src;
	MakeFromSR();
	m68k_incpci(4);
	get_word_000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, 0);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (2/0) */
/* 4 0,0   */

/* OR.W #<data>.W,Dn */
uae_u32 REGPARAM2 op_0040_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 8;  
	uae_s16 src = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8 (2/0) */
/* 4 0,0   */

/* OR.W #<data>.W,(An) */
uae_u32 REGPARAM2 op_0050_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 16; 
	uae_s16 src = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	if (dsta & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, dsta, 1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = get_word_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_word_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 4 0,0   */

/* OR.W #<data>.W,(An)+ */
uae_u32 REGPARAM2 op_0058_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 16; 
	uae_s16 src = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	if (dsta & 1) {
		m68k_areg(regs, dstreg) += 2 + 0;
		m68k_incpci(4);
		exception3_read_access(opcode, dsta, 1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = get_word_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, dstreg) += 2 + 0;
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) += 2;
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_word_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 4 0,0   */

/* OR.W #<data>.W,-(An) */
uae_u32 REGPARAM2 op_0060_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 18; 
	uae_s16 src = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - 2;
	if (dsta & 1) {
		m68k_areg(regs, dstreg) = dsta;
		m68k_incpci(4);
		exception3_read_access(opcode, dsta, 1, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = get_word_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, dstreg) = dsta;
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) = dsta;
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_word_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (3/1) */
/* 4 0,0   */

/* OR.W #<data>.W,(d16,An) */
uae_u32 REGPARAM2 op_0068_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 20; 
	uae_s16 src = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, dsta, 1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = get_word_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_word_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (4/1) */
/* 6 0,0   */

/* OR.W #<data>.W,(d8,An,Xn) */
uae_u32 REGPARAM2 op_0070_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 22; 
	uae_s16 src = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	BusCyclePenalty += 2;
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_000_prefetch(6));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, dsta, 1, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = get_word_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_word_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return 22 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 22 * CYCLE_UNIT / 2 + count_cycles;
}
/* 22 (4/1) */
/* 6 4,0   */

/* OR.W #<data>.W,(xxx).W */
uae_u32 REGPARAM2 op_0078_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 1;
	CurrentInstrCycles = 20; 
	uae_s16 src = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, 0);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, dsta, 1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = get_word_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_word_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (4/1) */
/* 6 0,0   */

/* OR.W #<data>.W,(xxx).L */
uae_u32 REGPARAM2 op_0079_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 1;
	CurrentInstrCycles = 24; 
	uae_s16 src = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = get_word_000_prefetch(6) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	dsta |= get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 8, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(8);
		exception3_read_access(opcode, dsta, 1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = get_word_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(10);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 10, pcoffset);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_word_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(10);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(8);
	return 24 * CYCLE_UNIT / 2 + count_cycles;
}
/* 24 (5/1) */
/* 8 0,0   */

/* ORSR.W #<data>.W */
uae_u32 REGPARAM2 op_007c_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 4;
	CurrentInstrCycles = 16; 
	if (!regs.s) {
		Exception(8);
		return 0;
	}
	MakeSR();
	uae_s16 src = regs.irc;
	regs.sr |= src;
	MakeFromSR();
	m68k_incpci(4);
	get_word_000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, 0);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (2/0) */
/* 4 0,0   */

/* OR.L #<data>.L,Dn */
uae_u32 REGPARAM2 op_0080_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 16; 
	uae_s32 src;
	src = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		m68k_dreg(regs, dstreg) = (src);
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_dreg(regs, dstreg) = (src);
	m68k_incpci(6);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/0) */
/* 6 0,0   */

/* OR.L #<data>.L,(An) */
uae_u32 REGPARAM2 op_0090_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 28; 
	uae_s32 src;
	src = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	if (dsta & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, dsta, 2, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = get_word_000(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	dst |= get_word_000(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src >> 16); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return 28 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 28 * CYCLE_UNIT / 2 + count_cycles;
}
/* 28 (5/2) */
/* 6 0,0   */

/* OR.L #<data>.L,(An)+ */
uae_u32 REGPARAM2 op_0098_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 28; 
	uae_s32 src;
	src = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	if (dsta & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, dsta, 2, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = get_word_000(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	dst |= get_word_000(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) += 4;
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src >> 16); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return 28 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 28 * CYCLE_UNIT / 2 + count_cycles;
}
/* 28 (5/2) */
/* 6 0,0   */

/* OR.L #<data>.L,-(An) */
uae_u32 REGPARAM2 op_00a0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 30; 
	uae_s32 src;
	src = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - 4;
	if (dsta & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, dsta, 2, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = get_word_000(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	dst |= get_word_000(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		m68k_areg(regs, dstreg) = dsta;
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) = dsta;
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 22 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return 26 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src >> 16); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return 30 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 30 * CYCLE_UNIT / 2 + count_cycles;
}
/* 30 (5/2) */
/* 6 0,0   */

/* OR.L #<data>.L,(d16,An) */
uae_u32 REGPARAM2 op_00a8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 32; 
	uae_s32 src;
	src = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 8, -2);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, dsta, 2, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = get_word_000(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	dst |= get_word_000(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(10);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch_opcode(opcode, 10, pcoffset);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(10);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return 28 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src >> 16); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(10);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return 32 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(8);
	return 32 * CYCLE_UNIT / 2 + count_cycles;
}
/* 32 (6/2) */
/* 8 0,0   */

/* OR.L #<data>.L,(d8,An,Xn) */
uae_u32 REGPARAM2 op_00b0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 34; 
	uae_s32 src;
	src = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	BusCyclePenalty += 2;
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_000_prefetch(8));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 8, -2);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, dsta, 2, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = get_word_000(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	dst |= get_word_000(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return 22 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(10);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch_opcode(opcode, 10, pcoffset);
		return 26 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(10);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return 30 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src >> 16); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(10);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return 34 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(8);
	return 34 * CYCLE_UNIT / 2 + count_cycles;
}
/* 34 (6/2) */
/* 8 4,0   */

/* OR.L #<data>.L,(xxx).W */
uae_u32 REGPARAM2 op_00b8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 1;
	CurrentInstrCycles = 32; 
	uae_s32 src;
	src = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 8, 0);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(8);
		exception3_read_access(opcode, dsta, 2, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = get_word_000(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	dst |= get_word_000(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(10);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch_opcode(opcode, 10, pcoffset);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(10);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return 28 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src >> 16); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(10);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return 32 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(8);
	return 32 * CYCLE_UNIT / 2 + count_cycles;
}
/* 32 (6/2) */
/* 8 0,0   */

/* OR.L #<data>.L,(xxx).L */
uae_u32 REGPARAM2 op_00b9_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 1;
	CurrentInstrCycles = 36; 
	uae_s32 src;
	src = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = get_word_000_prefetch(8) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 8, -2);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	dsta |= get_word_000_prefetch(10);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 10, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(10);
		exception3_read_access(opcode, dsta, 2, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = get_word_000(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(10);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	dst |= get_word_000(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(10);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(12);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch_opcode(opcode, 12, pcoffset);
		return 28 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(12);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return 32 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src >> 16); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(12);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return 36 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(10);
	return 36 * CYCLE_UNIT / 2 + count_cycles;
}
/* 36 (7/2) */
/* 10 0,0   */

/* BTST.L Dn,Dn */
uae_u32 REGPARAM2 op_0100_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 21;
	CurrentInstrCycles = 6;  
	uae_s32 src = m68k_dreg(regs, srcreg);
	uae_s32 dst = m68k_dreg(regs, dstreg);
	regs.ir = regs.irc;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	src &= 31;
	SET_ZFLG(1 ^ ((dst >> src) & 1));
	m68k_incpci(2);
	return 6 * CYCLE_UNIT / 2 + count_cycles;
}
/* 6 (1/0) */
/* 2 0,0   */

/* MVPMR.W (d16,An),Dn */
uae_u32 REGPARAM2 op_0108_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 29;
	CurrentInstrCycles = 16; 
	uaecptr mempa = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u16 val  = (get_byte_000(mempa) & 0xff) << 8;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		opcode |= 0x10000;
		exception2_read(opcode, mempa + 0, 0x0, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	val |= (get_byte_000(mempa + 2) & 0xff);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, mempa + 2, 0x0, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((val) & 0xffff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (4/0) */
/* 4 0,0   */

/* BTST.B Dn,(An) */
uae_u32 REGPARAM2 op_0110_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 21;
	CurrentInstrCycles = 8;  
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	src &= 7;
	SET_ZFLG(1 ^ ((dst >> src) & 1));
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8 (2/0) */
/* 2 0,0   */

/* BTST.B Dn,(An)+ */
uae_u32 REGPARAM2 op_0118_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 21;
	CurrentInstrCycles = 8;  
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
	src &= 7;
	SET_ZFLG(1 ^ ((dst >> src) & 1));
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8 (2/0) */
/* 2 0,0   */

/* BTST.B Dn,-(An) */
uae_u32 REGPARAM2 op_0120_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 21;
	CurrentInstrCycles = 10; 
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, dstreg) = dsta;
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) = dsta;
	src &= 7;
	SET_ZFLG(1 ^ ((dst >> src) & 1));
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 10 * CYCLE_UNIT / 2 + count_cycles;
}
/* 10 (2/0) */
/* 2 0,0   */

/* BTST.B Dn,(d16,An) */
uae_u32 REGPARAM2 op_0128_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 21;
	CurrentInstrCycles = 12; 
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	src &= 7;
	SET_ZFLG(1 ^ ((dst >> src) & 1));
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (3/0) */
/* 4 0,0   */

/* BTST.B Dn,(d8,An,Xn) */
uae_u32 REGPARAM2 op_0130_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 21;
	CurrentInstrCycles = 14; 
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	BusCyclePenalty += 2;
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	src &= 7;
	SET_ZFLG(1 ^ ((dst >> src) & 1));
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 14 * CYCLE_UNIT / 2 + count_cycles;
}
/* 14 (3/0) */
/* 4 4,0   */

/* BTST.B Dn,(xxx).W */
uae_u32 REGPARAM2 op_0138_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	OpcodeFamily = 21;
	CurrentInstrCycles = 12; 
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	src &= 7;
	SET_ZFLG(1 ^ ((dst >> src) & 1));
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (3/0) */
/* 4 0,0   */

/* BTST.B Dn,(xxx).L */
uae_u32 REGPARAM2 op_0139_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	OpcodeFamily = 21;
	CurrentInstrCycles = 16; 
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	dsta |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	src &= 7;
	SET_ZFLG(1 ^ ((dst >> src) & 1));
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (4/0) */
/* 6 0,0   */

/* BTST.B Dn,(d16,PC) */
uae_u32 REGPARAM2 op_013a_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = 2;
	OpcodeFamily = 21;
	CurrentInstrCycles = 12; 
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_getpci() + 2;
	dsta += (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x0, 2);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	src &= 7;
	SET_ZFLG(1 ^ ((dst >> src) & 1));
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (3/0) */
/* 4 0,0   */

/* BTST.B Dn,(d8,PC,Xn) */
uae_u32 REGPARAM2 op_013b_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = 3;
	OpcodeFamily = 21;
	CurrentInstrCycles = 14; 
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	uaecptr tmppc = m68k_getpci() + 2;
	BusCyclePenalty += 2;
	dsta = get_disp_ea_000(tmppc, get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x0, 2);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	src &= 7;
	SET_ZFLG(1 ^ ((dst >> src) & 1));
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 14 * CYCLE_UNIT / 2 + count_cycles;
}
/* 14 (3/0) */
/* 4 4,0   */

/* BTST.B Dn,#<data>.B */
uae_u32 REGPARAM2 op_013c_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	OpcodeFamily = 21;
	CurrentInstrCycles = 10; 
	uae_s8 src = m68k_dreg(regs, srcreg);
	uae_s8 dst = (uae_u8)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	src &= 7;
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	SET_ZFLG(1 ^ ((dst >> src) & 1));
	m68k_incpci(4);
	return 10 * CYCLE_UNIT / 2 + count_cycles;
}
/* 10 (2/0) */
/* 4 0,0   */

/* BCHG.L Dn,Dn */
uae_u32 REGPARAM2 op_0140_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 22;
	CurrentInstrCycles = 6;  
	uae_s32 src = m68k_dreg(regs, srcreg);
	uae_s32 dst = m68k_dreg(regs, dstreg);
	regs.ir = regs.irc;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	src &= 31;
	if (src > 15) {
		count_cycles +=  2 * CYCLE_UNIT / 2;
	}
	dst ^= (1 << src);
	SET_ZFLG(((uae_u32)dst & (1 << src)) >> src);
	m68k_dreg(regs, dstreg) = (dst);
	m68k_incpci(2);
	return 6 * CYCLE_UNIT / 2 + count_cycles;
}
/* 6+ (1/0) */
/* 2 0,0   */

/* MVPMR.L (d16,An),Dn */
uae_u32 REGPARAM2 op_0148_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 29;
	CurrentInstrCycles = 24; 
	uaecptr mempa = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 val  = (get_byte_000(mempa) & 0xff) << 24;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		opcode |= 0x10000;
		exception2_read(opcode, mempa + 0, 0x0, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	val |= (get_byte_000(mempa + 2) & 0xff) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, mempa + 2, 0x0, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & 0x0000ffff) | val;
	val |= (get_byte_000(mempa + 4) & 0xff) << 8;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		opcode |= 0x10000;
		exception2_read(opcode, mempa + 4, 0x0, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	val |= (get_byte_000(mempa + 6) & 0xff);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, mempa + 6, 0x0, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_dreg(regs, dstreg) = (val);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 24 * CYCLE_UNIT / 2 + count_cycles;
}
/* 24 (6/0) */
/* 4 0,0   */

/* BCHG.B Dn,(An) */
uae_u32 REGPARAM2 op_0150_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 22;
	CurrentInstrCycles = 12; 
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	src &= 7;
	dst ^= (1 << src);
	SET_ZFLG(((uae_u32)dst & (1 << src)) >> src);
	put_byte_000(dsta, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x0, dst, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (2/1) */
/* 2 0,0   */

/* BCHG.B Dn,(An)+ */
uae_u32 REGPARAM2 op_0158_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 22;
	CurrentInstrCycles = 12; 
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
	regs.ir = regs.irc;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	src &= 7;
	dst ^= (1 << src);
	SET_ZFLG(((uae_u32)dst & (1 << src)) >> src);
	put_byte_000(dsta, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x0, dst, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (2/1) */
/* 2 0,0   */

/* BCHG.B Dn,-(An) */
uae_u32 REGPARAM2 op_0160_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 22;
	CurrentInstrCycles = 14; 
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, dstreg) = dsta;
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) = dsta;
	regs.ir = regs.irc;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	src &= 7;
	dst ^= (1 << src);
	SET_ZFLG(((uae_u32)dst & (1 << src)) >> src);
	put_byte_000(dsta, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x0, dst, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 14 * CYCLE_UNIT / 2 + count_cycles;
}
/* 14 (2/1) */
/* 2 0,0   */

/* BCHG.B Dn,(d16,An) */
uae_u32 REGPARAM2 op_0168_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 22;
	CurrentInstrCycles = 16; 
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	src &= 7;
	dst ^= (1 << src);
	SET_ZFLG(((uae_u32)dst & (1 << src)) >> src);
	put_byte_000(dsta, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x0, dst, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 4 0,0   */

/* BCHG.B Dn,(d8,An,Xn) */
uae_u32 REGPARAM2 op_0170_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 22;
	CurrentInstrCycles = 18; 
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	BusCyclePenalty += 2;
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	src &= 7;
	dst ^= (1 << src);
	SET_ZFLG(((uae_u32)dst & (1 << src)) >> src);
	put_byte_000(dsta, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x0, dst, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (3/1) */
/* 4 4,0   */

/* BCHG.B Dn,(xxx).W */
uae_u32 REGPARAM2 op_0178_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	OpcodeFamily = 22;
	CurrentInstrCycles = 16; 
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	src &= 7;
	dst ^= (1 << src);
	SET_ZFLG(((uae_u32)dst & (1 << src)) >> src);
	put_byte_000(dsta, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x0, dst, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 4 0,0   */

/* BCHG.B Dn,(xxx).L */
uae_u32 REGPARAM2 op_0179_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	OpcodeFamily = 22;
	CurrentInstrCycles = 20; 
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	dsta |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	src &= 7;
	dst ^= (1 << src);
	SET_ZFLG(((uae_u32)dst & (1 << src)) >> src);
	put_byte_000(dsta, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 0, 0x0, dst, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (4/1) */
/* 6 0,0   */

/* BCLR.L Dn,Dn */
uae_u32 REGPARAM2 op_0180_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 23;
	CurrentInstrCycles = 8;  
	uae_s32 src = m68k_dreg(regs, srcreg);
	uae_s32 dst = m68k_dreg(regs, dstreg);
	regs.ir = regs.irc;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	src &= 31;
	if (src > 15) {
		count_cycles +=  2 * CYCLE_UNIT / 2;
	}
	SET_ZFLG(1 ^ ((dst >> src) & 1));
	dst &= ~(1 << src);
	m68k_dreg(regs, dstreg) = (dst);
	m68k_incpci(2);
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8+ (1/0) */
/* 2 0,0   */

/* MVPRM.W Dn,(d16,An) */
uae_u32 REGPARAM2 op_0188_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 28;
	CurrentInstrCycles = 16; 
	uae_s16 src = m68k_dreg(regs, srcreg);
	uaecptr mempa = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_byte_000(mempa, src >> 8);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		opcode |= 0x10000;
		uae_u16 val = src;
		exception2_write(opcode, mempa + 0, 0x100, val, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_byte_000(mempa + 2, src); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		uae_u16 val = src;
		exception2_write(opcode, mempa + 2, 0x100, val, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (2/2) */
/* 4 0,0   */

/* BCLR.B Dn,(An) */
uae_u32 REGPARAM2 op_0190_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 23;
	CurrentInstrCycles = 14; 
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	src &= 7;
	SET_ZFLG(1 ^ ((dst >> src) & 1));
	dst &= ~(1 << src);
	put_byte_000(dsta, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x0, dst, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 14 * CYCLE_UNIT / 2 + count_cycles;
}
/* 14 (2/1) */
/* 2 0,0   */

/* BCLR.B Dn,(An)+ */
uae_u32 REGPARAM2 op_0198_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 23;
	CurrentInstrCycles = 14; 
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
	regs.ir = regs.irc;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	src &= 7;
	SET_ZFLG(1 ^ ((dst >> src) & 1));
	dst &= ~(1 << src);
	put_byte_000(dsta, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x0, dst, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 14 * CYCLE_UNIT / 2 + count_cycles;
}
/* 14 (2/1) */
/* 2 0,0   */

/* BCLR.B Dn,-(An) */
uae_u32 REGPARAM2 op_01a0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 23;
	CurrentInstrCycles = 16; 
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, dstreg) = dsta;
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) = dsta;
	regs.ir = regs.irc;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	src &= 7;
	SET_ZFLG(1 ^ ((dst >> src) & 1));
	dst &= ~(1 << src);
	put_byte_000(dsta, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x0, dst, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (2/1) */
/* 2 0,0   */

/* BCLR.B Dn,(d16,An) */
uae_u32 REGPARAM2 op_01a8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 23;
	CurrentInstrCycles = 18; 
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	src &= 7;
	SET_ZFLG(1 ^ ((dst >> src) & 1));
	dst &= ~(1 << src);
	put_byte_000(dsta, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x0, dst, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (3/1) */
/* 4 0,0   */

/* BCLR.B Dn,(d8,An,Xn) */
uae_u32 REGPARAM2 op_01b0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 23;
	CurrentInstrCycles = 20; 
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	BusCyclePenalty += 2;
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	src &= 7;
	SET_ZFLG(1 ^ ((dst >> src) & 1));
	dst &= ~(1 << src);
	put_byte_000(dsta, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x0, dst, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (3/1) */
/* 4 4,0   */

/* BCLR.B Dn,(xxx).W */
uae_u32 REGPARAM2 op_01b8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	OpcodeFamily = 23;
	CurrentInstrCycles = 18; 
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	src &= 7;
	SET_ZFLG(1 ^ ((dst >> src) & 1));
	dst &= ~(1 << src);
	put_byte_000(dsta, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x0, dst, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (3/1) */
/* 4 0,0   */

/* BCLR.B Dn,(xxx).L */
uae_u32 REGPARAM2 op_01b9_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	OpcodeFamily = 23;
	CurrentInstrCycles = 22; 
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	dsta |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	src &= 7;
	SET_ZFLG(1 ^ ((dst >> src) & 1));
	dst &= ~(1 << src);
	put_byte_000(dsta, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 0, 0x0, dst, 1);
		return 22 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 22 * CYCLE_UNIT / 2 + count_cycles;
}
/* 22 (4/1) */
/* 6 0,0   */

/* BSET.L Dn,Dn */
uae_u32 REGPARAM2 op_01c0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 24;
	CurrentInstrCycles = 6;  
	uae_s32 src = m68k_dreg(regs, srcreg);
	uae_s32 dst = m68k_dreg(regs, dstreg);
	regs.ir = regs.irc;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	src &= 31;
	if (src > 15) {
		count_cycles +=  2 * CYCLE_UNIT / 2;
	}
	SET_ZFLG(1 ^ ((dst >> src) & 1));
	dst |= (1 << src);
	m68k_dreg(regs, dstreg) = (dst);
	m68k_incpci(2);
	return 6 * CYCLE_UNIT / 2 + count_cycles;
}
/* 6+ (1/0) */
/* 2 0,0   */

/* MVPRM.L Dn,(d16,An) */
uae_u32 REGPARAM2 op_01c8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 28;
	CurrentInstrCycles = 24; 
	uae_s32 src = m68k_dreg(regs, srcreg);
	uaecptr mempa = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_byte_000(mempa, src >> 24);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		opcode |= 0x10000;
		uae_u16 val = src >> 16;
		exception2_write(opcode, mempa + 0, 0x100, val, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_byte_000(mempa + 2, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		uae_u16 val = src >> 16;
		exception2_write(opcode, mempa + 2, 0x100, val, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_byte_000(mempa + 4, src >> 8);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		opcode |= 0x10000;
		uae_u16 val = src >> 0;
		exception2_write(opcode, mempa + 4, 0x100, val, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_byte_000(mempa + 6, src); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		uae_u16 val = src >> 0;
		exception2_write(opcode, mempa + 6, 0x100, val, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 24 * CYCLE_UNIT / 2 + count_cycles;
}
/* 24 (2/4) */
/* 4 0,0   */

/* BSET.B Dn,(An) */
uae_u32 REGPARAM2 op_01d0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 24;
	CurrentInstrCycles = 12; 
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	src &= 7;
	SET_ZFLG(1 ^ ((dst >> src) & 1));
	dst |= (1 << src);
	put_byte_000(dsta, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x0, dst, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (2/1) */
/* 2 0,0   */

/* BSET.B Dn,(An)+ */
uae_u32 REGPARAM2 op_01d8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 24;
	CurrentInstrCycles = 12; 
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
	regs.ir = regs.irc;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	src &= 7;
	SET_ZFLG(1 ^ ((dst >> src) & 1));
	dst |= (1 << src);
	put_byte_000(dsta, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x0, dst, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (2/1) */
/* 2 0,0   */

/* BSET.B Dn,-(An) */
uae_u32 REGPARAM2 op_01e0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 24;
	CurrentInstrCycles = 14; 
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, dstreg) = dsta;
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) = dsta;
	regs.ir = regs.irc;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	src &= 7;
	SET_ZFLG(1 ^ ((dst >> src) & 1));
	dst |= (1 << src);
	put_byte_000(dsta, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x0, dst, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 14 * CYCLE_UNIT / 2 + count_cycles;
}
/* 14 (2/1) */
/* 2 0,0   */

/* BSET.B Dn,(d16,An) */
uae_u32 REGPARAM2 op_01e8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 24;
	CurrentInstrCycles = 16; 
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	src &= 7;
	SET_ZFLG(1 ^ ((dst >> src) & 1));
	dst |= (1 << src);
	put_byte_000(dsta, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x0, dst, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 4 0,0   */

/* BSET.B Dn,(d8,An,Xn) */
uae_u32 REGPARAM2 op_01f0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 24;
	CurrentInstrCycles = 18; 
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	BusCyclePenalty += 2;
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	src &= 7;
	SET_ZFLG(1 ^ ((dst >> src) & 1));
	dst |= (1 << src);
	put_byte_000(dsta, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x0, dst, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (3/1) */
/* 4 4,0   */

/* BSET.B Dn,(xxx).W */
uae_u32 REGPARAM2 op_01f8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	OpcodeFamily = 24;
	CurrentInstrCycles = 16; 
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	src &= 7;
	SET_ZFLG(1 ^ ((dst >> src) & 1));
	dst |= (1 << src);
	put_byte_000(dsta, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x0, dst, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 4 0,0   */

/* BSET.B Dn,(xxx).L */
uae_u32 REGPARAM2 op_01f9_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	OpcodeFamily = 24;
	CurrentInstrCycles = 20; 
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	dsta |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	src &= 7;
	SET_ZFLG(1 ^ ((dst >> src) & 1));
	dst |= (1 << src);
	put_byte_000(dsta, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 0, 0x0, dst, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (4/1) */
/* 6 0,0   */

/* AND.B #<data>.B,Dn */
uae_u32 REGPARAM2 op_0200_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 8;  
	uae_s8 src = (uae_u8)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = m68k_dreg(regs, dstreg);
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8 (2/0) */
/* 4 0,0   */

/* AND.B #<data>.B,(An) */
uae_u32 REGPARAM2 op_0210_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 16; 
	uae_s8 src = (uae_u8)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_byte_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 4 0,0   */

/* AND.B #<data>.B,(An)+ */
uae_u32 REGPARAM2 op_0218_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 16; 
	uae_s8 src = (uae_u8)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_byte_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 4 0,0   */

/* AND.B #<data>.B,-(An) */
uae_u32 REGPARAM2 op_0220_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 18; 
	uae_s8 src = (uae_u8)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, dstreg) = dsta;
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) = dsta;
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_byte_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (3/1) */
/* 4 0,0   */

/* AND.B #<data>.B,(d16,An) */
uae_u32 REGPARAM2 op_0228_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 20; 
	uae_s8 src = (uae_u8)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_byte_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (4/1) */
/* 6 0,0   */

/* AND.B #<data>.B,(d8,An,Xn) */
uae_u32 REGPARAM2 op_0230_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 22; 
	uae_s8 src = (uae_u8)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	BusCyclePenalty += 2;
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_000_prefetch(6));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_byte_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return 22 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 22 * CYCLE_UNIT / 2 + count_cycles;
}
/* 22 (4/1) */
/* 6 4,0   */

/* AND.B #<data>.B,(xxx).W */
uae_u32 REGPARAM2 op_0238_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 2;
	CurrentInstrCycles = 20; 
	uae_s8 src = (uae_u8)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, 0);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_byte_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (4/1) */
/* 6 0,0   */

/* AND.B #<data>.B,(xxx).L */
uae_u32 REGPARAM2 op_0239_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 2;
	CurrentInstrCycles = 24; 
	uae_s8 src = (uae_u8)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = get_word_000_prefetch(6) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	dsta |= get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 8, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(10);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 10, pcoffset);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_byte_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(10);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(8);
	return 24 * CYCLE_UNIT / 2 + count_cycles;
}
/* 24 (5/1) */
/* 8 0,0   */

/* ANDSR.B #<data>.W */
uae_u32 REGPARAM2 op_023c_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 5;
	CurrentInstrCycles = 16; 
	MakeSR();
	uae_s16 src = regs.irc;
	src &= 0xFF;
	src |= 0xff00;
	regs.sr &= src;
	MakeFromSR();
	m68k_incpci(4);
	get_word_000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, 0);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (2/0) */
/* 4 0,0   */

/* AND.W #<data>.W,Dn */
uae_u32 REGPARAM2 op_0240_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 8;  
	uae_s16 src = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8 (2/0) */
/* 4 0,0   */

/* AND.W #<data>.W,(An) */
uae_u32 REGPARAM2 op_0250_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 16; 
	uae_s16 src = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	if (dsta & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, dsta, 1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = get_word_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_word_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 4 0,0   */

/* AND.W #<data>.W,(An)+ */
uae_u32 REGPARAM2 op_0258_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 16; 
	uae_s16 src = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	if (dsta & 1) {
		m68k_areg(regs, dstreg) += 2 + 0;
		m68k_incpci(4);
		exception3_read_access(opcode, dsta, 1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = get_word_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, dstreg) += 2 + 0;
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) += 2;
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_word_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 4 0,0   */

/* AND.W #<data>.W,-(An) */
uae_u32 REGPARAM2 op_0260_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 18; 
	uae_s16 src = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - 2;
	if (dsta & 1) {
		m68k_areg(regs, dstreg) = dsta;
		m68k_incpci(4);
		exception3_read_access(opcode, dsta, 1, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = get_word_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, dstreg) = dsta;
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) = dsta;
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_word_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (3/1) */
/* 4 0,0   */

/* AND.W #<data>.W,(d16,An) */
uae_u32 REGPARAM2 op_0268_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 20; 
	uae_s16 src = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, dsta, 1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = get_word_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_word_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (4/1) */
/* 6 0,0   */

/* AND.W #<data>.W,(d8,An,Xn) */
uae_u32 REGPARAM2 op_0270_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 22; 
	uae_s16 src = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	BusCyclePenalty += 2;
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_000_prefetch(6));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, dsta, 1, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = get_word_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_word_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return 22 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 22 * CYCLE_UNIT / 2 + count_cycles;
}
/* 22 (4/1) */
/* 6 4,0   */

/* AND.W #<data>.W,(xxx).W */
uae_u32 REGPARAM2 op_0278_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 2;
	CurrentInstrCycles = 20; 
	uae_s16 src = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, 0);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, dsta, 1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = get_word_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_word_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (4/1) */
/* 6 0,0   */

/* AND.W #<data>.W,(xxx).L */
uae_u32 REGPARAM2 op_0279_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 2;
	CurrentInstrCycles = 24; 
	uae_s16 src = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = get_word_000_prefetch(6) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	dsta |= get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 8, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(8);
		exception3_read_access(opcode, dsta, 1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = get_word_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(10);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 10, pcoffset);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_word_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(10);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(8);
	return 24 * CYCLE_UNIT / 2 + count_cycles;
}
/* 24 (5/1) */
/* 8 0,0   */

/* ANDSR.W #<data>.W */
uae_u32 REGPARAM2 op_027c_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 5;
	CurrentInstrCycles = 16; 
	if (!regs.s) {
		Exception(8);
		return 0;
	}
	MakeSR();
	uae_s16 src = regs.irc;
	regs.sr &= src;
	MakeFromSR();
	m68k_incpci(4);
	get_word_000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, 0);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (2/0) */
/* 4 0,0   */

/* AND.L #<data>.L,Dn */
uae_u32 REGPARAM2 op_0280_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 16; 
	uae_s32 src;
	src = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		m68k_dreg(regs, dstreg) = (src);
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_dreg(regs, dstreg) = (src);
	m68k_incpci(6);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/0) */
/* 6 0,0   */

/* AND.L #<data>.L,(An) */
uae_u32 REGPARAM2 op_0290_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 28; 
	uae_s32 src;
	src = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	if (dsta & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, dsta, 2, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = get_word_000(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	dst |= get_word_000(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src >> 16); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return 28 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 28 * CYCLE_UNIT / 2 + count_cycles;
}
/* 28 (5/2) */
/* 6 0,0   */

/* AND.L #<data>.L,(An)+ */
uae_u32 REGPARAM2 op_0298_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 28; 
	uae_s32 src;
	src = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	if (dsta & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, dsta, 2, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = get_word_000(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	dst |= get_word_000(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) += 4;
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src >> 16); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return 28 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 28 * CYCLE_UNIT / 2 + count_cycles;
}
/* 28 (5/2) */
/* 6 0,0   */

/* AND.L #<data>.L,-(An) */
uae_u32 REGPARAM2 op_02a0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 30; 
	uae_s32 src;
	src = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - 4;
	if (dsta & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, dsta, 2, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = get_word_000(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	dst |= get_word_000(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		m68k_areg(regs, dstreg) = dsta;
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) = dsta;
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 22 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return 26 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src >> 16); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return 30 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 30 * CYCLE_UNIT / 2 + count_cycles;
}
/* 30 (5/2) */
/* 6 0,0   */

/* AND.L #<data>.L,(d16,An) */
uae_u32 REGPARAM2 op_02a8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 32; 
	uae_s32 src;
	src = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 8, -2);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, dsta, 2, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = get_word_000(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	dst |= get_word_000(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(10);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch_opcode(opcode, 10, pcoffset);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(10);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return 28 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src >> 16); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(10);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return 32 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(8);
	return 32 * CYCLE_UNIT / 2 + count_cycles;
}
/* 32 (6/2) */
/* 8 0,0   */

/* AND.L #<data>.L,(d8,An,Xn) */
uae_u32 REGPARAM2 op_02b0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 34; 
	uae_s32 src;
	src = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	BusCyclePenalty += 2;
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_000_prefetch(8));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 8, -2);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, dsta, 2, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = get_word_000(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	dst |= get_word_000(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return 22 * CYCLE_UNIT / 2 + count_cycles;
	}
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(10);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch_opcode(opcode, 10, pcoffset);
		return 26 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(10);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return 30 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src >> 16); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(10);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return 34 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(8);
	return 34 * CYCLE_UNIT / 2 + count_cycles;
}
/* 34 (6/2) */
/* 8 4,0   */

/* AND.L #<data>.L,(xxx).W */
uae_u32 REGPARAM2 op_02b8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 2;
	CurrentInstrCycles = 32; 
	uae_s32 src;
	src = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 8, 0);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(8);
		exception3_read_access(opcode, dsta, 2, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = get_word_000(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	dst |= get_word_000(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(10);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch_opcode(opcode, 10, pcoffset);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(10);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return 28 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src >> 16); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(10);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return 32 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(8);
	return 32 * CYCLE_UNIT / 2 + count_cycles;
}
/* 32 (6/2) */
/* 8 0,0   */

/* AND.L #<data>.L,(xxx).L */
uae_u32 REGPARAM2 op_02b9_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 2;
	CurrentInstrCycles = 36; 
	uae_s32 src;
	src = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = get_word_000_prefetch(8) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 8, -2);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	dsta |= get_word_000_prefetch(10);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 10, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(10);
		exception3_read_access(opcode, dsta, 2, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = get_word_000(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(10);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	dst |= get_word_000(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(10);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(12);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch_opcode(opcode, 12, pcoffset);
		return 28 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(12);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return 32 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src >> 16); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(12);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return 36 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(10);
	return 36 * CYCLE_UNIT / 2 + count_cycles;
}
/* 36 (7/2) */
/* 10 0,0   */

/* SUB.B #<data>.B,Dn */
uae_u32 REGPARAM2 op_0400_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 8;  
	uae_s8 src = (uae_u8)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8 (2/0) */
/* 4 0,0   */

/* SUB.B #<data>.B,(An) */
uae_u32 REGPARAM2 op_0410_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 16; 
	uae_s8 src = (uae_u8)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_byte_000(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x0, newv, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 4 0,0   */

/* SUB.B #<data>.B,(An)+ */
uae_u32 REGPARAM2 op_0418_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 16; 
	uae_s8 src = (uae_u8)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
	uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_byte_000(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x0, newv, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 4 0,0   */

/* SUB.B #<data>.B,-(An) */
uae_u32 REGPARAM2 op_0420_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 18; 
	uae_s8 src = (uae_u8)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, dstreg) = dsta;
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) = dsta;
	uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_byte_000(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x0, newv, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (3/1) */
/* 4 0,0   */

/* SUB.B #<data>.B,(d16,An) */
uae_u32 REGPARAM2 op_0428_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 20; 
	uae_s8 src = (uae_u8)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_byte_000(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 0, 0x0, newv, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (4/1) */
/* 6 0,0   */

/* SUB.B #<data>.B,(d8,An,Xn) */
uae_u32 REGPARAM2 op_0430_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 22; 
	uae_s8 src = (uae_u8)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	BusCyclePenalty += 2;
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_000_prefetch(6));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_byte_000(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 0, 0x0, newv, 1);
		return 22 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 22 * CYCLE_UNIT / 2 + count_cycles;
}
/* 22 (4/1) */
/* 6 4,0   */

/* SUB.B #<data>.B,(xxx).W */
uae_u32 REGPARAM2 op_0438_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 7;
	CurrentInstrCycles = 20; 
	uae_s8 src = (uae_u8)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, 0);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_byte_000(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 0, 0x0, newv, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (4/1) */
/* 6 0,0   */

/* SUB.B #<data>.B,(xxx).L */
uae_u32 REGPARAM2 op_0439_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 7;
	CurrentInstrCycles = 24; 
	uae_s8 src = (uae_u8)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = get_word_000_prefetch(6) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	dsta |= get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 8, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(10);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 10, pcoffset);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_byte_000(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(10);
		exception2_write(opcode, dsta + 0, 0x0, newv, 1);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(8);
	return 24 * CYCLE_UNIT / 2 + count_cycles;
}
/* 24 (5/1) */
/* 8 0,0   */

/* SUB.W #<data>.W,Dn */
uae_u32 REGPARAM2 op_0440_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 8;  
	uae_s16 src = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8 (2/0) */
/* 4 0,0   */

/* SUB.W #<data>.W,(An) */
uae_u32 REGPARAM2 op_0450_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 16; 
	uae_s16 src = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	if (dsta & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, dsta, 1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = get_word_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_word_000(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, newv, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 4 0,0   */

/* SUB.W #<data>.W,(An)+ */
uae_u32 REGPARAM2 op_0458_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 16; 
	uae_s16 src = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	if (dsta & 1) {
		m68k_areg(regs, dstreg) += 2 + 0;
		m68k_incpci(4);
		exception3_read_access(opcode, dsta, 1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = get_word_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, dstreg) += 2 + 0;
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) += 2;
	uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_word_000(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, newv, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 4 0,0   */

/* SUB.W #<data>.W,-(An) */
uae_u32 REGPARAM2 op_0460_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 18; 
	uae_s16 src = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - 2;
	if (dsta & 1) {
		m68k_areg(regs, dstreg) = dsta;
		m68k_incpci(4);
		exception3_read_access(opcode, dsta, 1, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = get_word_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, dstreg) = dsta;
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) = dsta;
	uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_word_000(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, newv, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (3/1) */
/* 4 0,0   */

/* SUB.W #<data>.W,(d16,An) */
uae_u32 REGPARAM2 op_0468_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 20; 
	uae_s16 src = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, dsta, 1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = get_word_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_word_000(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 0, 0x1, newv, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (4/1) */
/* 6 0,0   */

/* SUB.W #<data>.W,(d8,An,Xn) */
uae_u32 REGPARAM2 op_0470_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 22; 
	uae_s16 src = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	BusCyclePenalty += 2;
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_000_prefetch(6));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, dsta, 1, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = get_word_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_word_000(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 0, 0x1, newv, 1);
		return 22 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 22 * CYCLE_UNIT / 2 + count_cycles;
}
/* 22 (4/1) */
/* 6 4,0   */

/* SUB.W #<data>.W,(xxx).W */
uae_u32 REGPARAM2 op_0478_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 7;
	CurrentInstrCycles = 20; 
	uae_s16 src = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, 0);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, dsta, 1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = get_word_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_word_000(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 0, 0x1, newv, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (4/1) */
/* 6 0,0   */

/* SUB.W #<data>.W,(xxx).L */
uae_u32 REGPARAM2 op_0479_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 7;
	CurrentInstrCycles = 24; 
	uae_s16 src = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = get_word_000_prefetch(6) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	dsta |= get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 8, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(8);
		exception3_read_access(opcode, dsta, 1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = get_word_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(10);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 10, pcoffset);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_word_000(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(10);
		exception2_write(opcode, dsta + 0, 0x1, newv, 1);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(8);
	return 24 * CYCLE_UNIT / 2 + count_cycles;
}
/* 24 (5/1) */
/* 8 0,0   */

/* SUB.L #<data>.L,Dn */
uae_u32 REGPARAM2 op_0480_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 14; 
	uae_s32 src;
	src = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		uae_s16 bnewv = (uae_s16)dst - (uae_s16)src;
		int bflgs = ((uae_s16)(src)) < 0;
		int bflgo = ((uae_s16)(dst)) < 0;
		int bflgn = bnewv < 0;
		ccr_68000_long_move_ae_LZN(bnewv);
		SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
		SET_XFLG(GET_CFLG());
		SET_VFLG((bflgs ^ bflgo) & (bflgn ^ bflgo));
		dreg_68000_long_replace_low(dstreg, bnewv);
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	m68k_dreg(regs, dstreg) = (newv);
	m68k_incpci(6);
	return 14 * CYCLE_UNIT / 2 + count_cycles;
}
/* 14 (3/0) */
/* 6 0,0   */

/* SUB.L #<data>.L,(An) */
uae_u32 REGPARAM2 op_0490_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 28; 
	uae_s32 src;
	src = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	if (dsta & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, dsta, 2, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = get_word_000(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	dst |= get_word_000(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		uae_s16 bnewv = (uae_s16)dst - (uae_s16)src;
		int bflgs = ((uae_s16)(src)) < 0;
		int bflgo = ((uae_s16)(dst)) < 0;
		int bflgn = bnewv < 0;
		ccr_68000_long_move_ae_LZN(bnewv);
		SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
		SET_XFLG(GET_CFLG());
		SET_VFLG((bflgs ^ bflgo) & (bflgn ^ bflgo));
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta + 2, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 2, 0x1, newv, 1);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, newv >> 16); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 0, 0x1, newv >> 16, 1);
		return 28 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 28 * CYCLE_UNIT / 2 + count_cycles;
}
/* 28 (5/2) */
/* 6 0,0   */

/* SUB.L #<data>.L,(An)+ */
uae_u32 REGPARAM2 op_0498_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 28; 
	uae_s32 src;
	src = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	if (dsta & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, dsta, 2, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = get_word_000(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	dst |= get_word_000(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) += 4;
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		uae_s16 bnewv = (uae_s16)dst - (uae_s16)src;
		int bflgs = ((uae_s16)(src)) < 0;
		int bflgo = ((uae_s16)(dst)) < 0;
		int bflgn = bnewv < 0;
		ccr_68000_long_move_ae_LZN(bnewv);
		SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
		SET_XFLG(GET_CFLG());
		SET_VFLG((bflgs ^ bflgo) & (bflgn ^ bflgo));
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta + 2, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 2, 0x1, newv, 1);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, newv >> 16); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 0, 0x1, newv >> 16, 1);
		return 28 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 28 * CYCLE_UNIT / 2 + count_cycles;
}
/* 28 (5/2) */
/* 6 0,0   */

/* SUB.L #<data>.L,-(An) */
uae_u32 REGPARAM2 op_04a0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 30; 
	uae_s32 src;
	src = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - 4;
	if (dsta & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, dsta, 2, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = get_word_000(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	dst |= get_word_000(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		m68k_areg(regs, dstreg) = dsta;
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) = dsta;
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		uae_s16 bnewv = (uae_s16)dst - (uae_s16)src;
		int bflgs = ((uae_s16)(src)) < 0;
		int bflgo = ((uae_s16)(dst)) < 0;
		int bflgn = bnewv < 0;
		ccr_68000_long_move_ae_LZN(bnewv);
		SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
		SET_XFLG(GET_CFLG());
		SET_VFLG((bflgs ^ bflgo) & (bflgn ^ bflgo));
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 22 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta + 2, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 2, 0x1, newv, 1);
		return 26 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, newv >> 16); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 0, 0x1, newv >> 16, 1);
		return 30 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 30 * CYCLE_UNIT / 2 + count_cycles;
}
/* 30 (5/2) */
/* 6 0,0   */

/* SUB.L #<data>.L,(d16,An) */
uae_u32 REGPARAM2 op_04a8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 32; 
	uae_s32 src;
	src = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 8, -2);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, dsta, 2, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = get_word_000(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	dst |= get_word_000(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(10);
	if(hardware_bus_error) {
		int pcoffset = 0;
		uae_s16 bnewv = (uae_s16)dst - (uae_s16)src;
		int bflgs = ((uae_s16)(src)) < 0;
		int bflgo = ((uae_s16)(dst)) < 0;
		int bflgn = bnewv < 0;
		ccr_68000_long_move_ae_LZN(bnewv);
		SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
		SET_XFLG(GET_CFLG());
		SET_VFLG((bflgs ^ bflgo) & (bflgn ^ bflgo));
		exception2_fetch_opcode(opcode, 10, pcoffset);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta + 2, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(10);
		exception2_write(opcode, dsta + 2, 0x1, newv, 1);
		return 28 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, newv >> 16); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(10);
		exception2_write(opcode, dsta + 0, 0x1, newv >> 16, 1);
		return 32 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(8);
	return 32 * CYCLE_UNIT / 2 + count_cycles;
}
/* 32 (6/2) */
/* 8 0,0   */

/* SUB.L #<data>.L,(d8,An,Xn) */
uae_u32 REGPARAM2 op_04b0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 34; 
	uae_s32 src;
	src = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	BusCyclePenalty += 2;
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_000_prefetch(8));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 8, -2);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, dsta, 2, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = get_word_000(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	dst |= get_word_000(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return 22 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(10);
	if(hardware_bus_error) {
		int pcoffset = 0;
		uae_s16 bnewv = (uae_s16)dst - (uae_s16)src;
		int bflgs = ((uae_s16)(src)) < 0;
		int bflgo = ((uae_s16)(dst)) < 0;
		int bflgn = bnewv < 0;
		ccr_68000_long_move_ae_LZN(bnewv);
		SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
		SET_XFLG(GET_CFLG());
		SET_VFLG((bflgs ^ bflgo) & (bflgn ^ bflgo));
		exception2_fetch_opcode(opcode, 10, pcoffset);
		return 26 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta + 2, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(10);
		exception2_write(opcode, dsta + 2, 0x1, newv, 1);
		return 30 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, newv >> 16); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(10);
		exception2_write(opcode, dsta + 0, 0x1, newv >> 16, 1);
		return 34 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(8);
	return 34 * CYCLE_UNIT / 2 + count_cycles;
}
/* 34 (6/2) */
/* 8 4,0   */

/* SUB.L #<data>.L,(xxx).W */
uae_u32 REGPARAM2 op_04b8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 7;
	CurrentInstrCycles = 32; 
	uae_s32 src;
	src = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 8, 0);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(8);
		exception3_read_access(opcode, dsta, 2, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = get_word_000(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	dst |= get_word_000(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(10);
	if(hardware_bus_error) {
		int pcoffset = 0;
		uae_s16 bnewv = (uae_s16)dst - (uae_s16)src;
		int bflgs = ((uae_s16)(src)) < 0;
		int bflgo = ((uae_s16)(dst)) < 0;
		int bflgn = bnewv < 0;
		ccr_68000_long_move_ae_LZN(bnewv);
		SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
		SET_XFLG(GET_CFLG());
		SET_VFLG((bflgs ^ bflgo) & (bflgn ^ bflgo));
		exception2_fetch_opcode(opcode, 10, pcoffset);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta + 2, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(10);
		exception2_write(opcode, dsta + 2, 0x1, newv, 1);
		return 28 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, newv >> 16); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(10);
		exception2_write(opcode, dsta + 0, 0x1, newv >> 16, 1);
		return 32 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(8);
	return 32 * CYCLE_UNIT / 2 + count_cycles;
}
/* 32 (6/2) */
/* 8 0,0   */

/* SUB.L #<data>.L,(xxx).L */
uae_u32 REGPARAM2 op_04b9_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 7;
	CurrentInstrCycles = 36; 
	uae_s32 src;
	src = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = get_word_000_prefetch(8) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 8, -2);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	dsta |= get_word_000_prefetch(10);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 10, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(10);
		exception3_read_access(opcode, dsta, 2, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = get_word_000(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(10);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	dst |= get_word_000(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(10);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(12);
	if(hardware_bus_error) {
		int pcoffset = 0;
		uae_s16 bnewv = (uae_s16)dst - (uae_s16)src;
		int bflgs = ((uae_s16)(src)) < 0;
		int bflgo = ((uae_s16)(dst)) < 0;
		int bflgn = bnewv < 0;
		ccr_68000_long_move_ae_LZN(bnewv);
		SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
		SET_XFLG(GET_CFLG());
		SET_VFLG((bflgs ^ bflgo) & (bflgn ^ bflgo));
		exception2_fetch_opcode(opcode, 12, pcoffset);
		return 28 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta + 2, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(12);
		exception2_write(opcode, dsta + 2, 0x1, newv, 1);
		return 32 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, newv >> 16); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(12);
		exception2_write(opcode, dsta + 0, 0x1, newv >> 16, 1);
		return 36 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(10);
	return 36 * CYCLE_UNIT / 2 + count_cycles;
}
/* 36 (7/2) */
/* 10 0,0   */

/* ADD.B #<data>.B,Dn */
uae_u32 REGPARAM2 op_0600_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 8;  
	uae_s8 src = (uae_u8)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u8)(~dst)) < ((uae_u8)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8 (2/0) */
/* 4 0,0   */

/* ADD.B #<data>.B,(An) */
uae_u32 REGPARAM2 op_0610_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 16; 
	uae_s8 src = (uae_u8)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u8)(~dst)) < ((uae_u8)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_byte_000(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x0, newv, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 4 0,0   */

/* ADD.B #<data>.B,(An)+ */
uae_u32 REGPARAM2 op_0618_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 16; 
	uae_s8 src = (uae_u8)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
	uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u8)(~dst)) < ((uae_u8)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_byte_000(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x0, newv, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 4 0,0   */

/* ADD.B #<data>.B,-(An) */
uae_u32 REGPARAM2 op_0620_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 18; 
	uae_s8 src = (uae_u8)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, dstreg) = dsta;
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) = dsta;
	uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u8)(~dst)) < ((uae_u8)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_byte_000(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x0, newv, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (3/1) */
/* 4 0,0   */

/* ADD.B #<data>.B,(d16,An) */
uae_u32 REGPARAM2 op_0628_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 20; 
	uae_s8 src = (uae_u8)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u8)(~dst)) < ((uae_u8)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_byte_000(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 0, 0x0, newv, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (4/1) */
/* 6 0,0   */

/* ADD.B #<data>.B,(d8,An,Xn) */
uae_u32 REGPARAM2 op_0630_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 22; 
	uae_s8 src = (uae_u8)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	BusCyclePenalty += 2;
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_000_prefetch(6));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u8)(~dst)) < ((uae_u8)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_byte_000(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 0, 0x0, newv, 1);
		return 22 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 22 * CYCLE_UNIT / 2 + count_cycles;
}
/* 22 (4/1) */
/* 6 4,0   */

/* ADD.B #<data>.B,(xxx).W */
uae_u32 REGPARAM2 op_0638_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 11;
	CurrentInstrCycles = 20; 
	uae_s8 src = (uae_u8)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, 0);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u8)(~dst)) < ((uae_u8)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_byte_000(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 0, 0x0, newv, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (4/1) */
/* 6 0,0   */

/* ADD.B #<data>.B,(xxx).L */
uae_u32 REGPARAM2 op_0639_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 11;
	CurrentInstrCycles = 24; 
	uae_s8 src = (uae_u8)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = get_word_000_prefetch(6) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	dsta |= get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 8, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u8)(~dst)) < ((uae_u8)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(10);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 10, pcoffset);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_byte_000(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(10);
		exception2_write(opcode, dsta + 0, 0x0, newv, 1);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(8);
	return 24 * CYCLE_UNIT / 2 + count_cycles;
}
/* 24 (5/1) */
/* 8 0,0   */

/* ADD.W #<data>.W,Dn */
uae_u32 REGPARAM2 op_0640_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 8;  
	uae_s16 src = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8 (2/0) */
/* 4 0,0   */

/* ADD.W #<data>.W,(An) */
uae_u32 REGPARAM2 op_0650_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 16; 
	uae_s16 src = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	if (dsta & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, dsta, 1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = get_word_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_word_000(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, newv, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 4 0,0   */

/* ADD.W #<data>.W,(An)+ */
uae_u32 REGPARAM2 op_0658_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 16; 
	uae_s16 src = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	if (dsta & 1) {
		m68k_areg(regs, dstreg) += 2 + 0;
		m68k_incpci(4);
		exception3_read_access(opcode, dsta, 1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = get_word_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, dstreg) += 2 + 0;
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) += 2;
	uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_word_000(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, newv, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 4 0,0   */

/* ADD.W #<data>.W,-(An) */
uae_u32 REGPARAM2 op_0660_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 18; 
	uae_s16 src = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - 2;
	if (dsta & 1) {
		m68k_areg(regs, dstreg) = dsta;
		m68k_incpci(4);
		exception3_read_access(opcode, dsta, 1, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = get_word_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, dstreg) = dsta;
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) = dsta;
	uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_word_000(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, newv, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (3/1) */
/* 4 0,0   */

/* ADD.W #<data>.W,(d16,An) */
uae_u32 REGPARAM2 op_0668_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 20; 
	uae_s16 src = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, dsta, 1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = get_word_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_word_000(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 0, 0x1, newv, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (4/1) */
/* 6 0,0   */

/* ADD.W #<data>.W,(d8,An,Xn) */
uae_u32 REGPARAM2 op_0670_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 22; 
	uae_s16 src = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	BusCyclePenalty += 2;
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_000_prefetch(6));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, dsta, 1, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = get_word_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_word_000(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 0, 0x1, newv, 1);
		return 22 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 22 * CYCLE_UNIT / 2 + count_cycles;
}
/* 22 (4/1) */
/* 6 4,0   */

/* ADD.W #<data>.W,(xxx).W */
uae_u32 REGPARAM2 op_0678_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 11;
	CurrentInstrCycles = 20; 
	uae_s16 src = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, 0);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, dsta, 1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = get_word_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_word_000(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 0, 0x1, newv, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (4/1) */
/* 6 0,0   */

/* ADD.W #<data>.W,(xxx).L */
uae_u32 REGPARAM2 op_0679_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 11;
	CurrentInstrCycles = 24; 
	uae_s16 src = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = get_word_000_prefetch(6) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	dsta |= get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 8, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(8);
		exception3_read_access(opcode, dsta, 1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = get_word_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(10);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 10, pcoffset);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_word_000(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(10);
		exception2_write(opcode, dsta + 0, 0x1, newv, 1);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(8);
	return 24 * CYCLE_UNIT / 2 + count_cycles;
}
/* 24 (5/1) */
/* 8 0,0   */

/* ADD.L #<data>.L,Dn */
uae_u32 REGPARAM2 op_0680_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 14; 
	uae_s32 src;
	src = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u32)(~dst)) < ((uae_u32)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		uae_s16 bnewv = (uae_s16)dst + (uae_s16)src;
		int bflgs = ((uae_s16)(src)) < 0;
		int bflgo = ((uae_s16)(dst)) < 0;
		int bflgn = bnewv < 0;
		ccr_68000_long_move_ae_LZN(bnewv);
		SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
		SET_XFLG(GET_CFLG());
		SET_VFLG((bflgs ^ bflgn) & (bflgo ^ bflgn));
		dreg_68000_long_replace_low(dstreg, bnewv);
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	m68k_dreg(regs, dstreg) = (newv);
	m68k_incpci(6);
	return 14 * CYCLE_UNIT / 2 + count_cycles;
}
/* 14 (3/0) */
/* 6 0,0   */

/* ADD.L #<data>.L,(An) */
uae_u32 REGPARAM2 op_0690_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 28; 
	uae_s32 src;
	src = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	if (dsta & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, dsta, 2, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = get_word_000(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	dst |= get_word_000(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u32)(~dst)) < ((uae_u32)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		uae_s16 bnewv = (uae_s16)dst + (uae_s16)src;
		int bflgs = ((uae_s16)(src)) < 0;
		int bflgo = ((uae_s16)(dst)) < 0;
		int bflgn = bnewv < 0;
		ccr_68000_long_move_ae_LZN(bnewv);
		SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
		SET_XFLG(GET_CFLG());
		SET_VFLG((bflgs ^ bflgn) & (bflgo ^ bflgn));
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta + 2, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 2, 0x1, newv, 1);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, newv >> 16); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 0, 0x1, newv >> 16, 1);
		return 28 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 28 * CYCLE_UNIT / 2 + count_cycles;
}
/* 28 (5/2) */
/* 6 0,0   */

/* ADD.L #<data>.L,(An)+ */
uae_u32 REGPARAM2 op_0698_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 28; 
	uae_s32 src;
	src = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	if (dsta & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, dsta, 2, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = get_word_000(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	dst |= get_word_000(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) += 4;
	uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u32)(~dst)) < ((uae_u32)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		uae_s16 bnewv = (uae_s16)dst + (uae_s16)src;
		int bflgs = ((uae_s16)(src)) < 0;
		int bflgo = ((uae_s16)(dst)) < 0;
		int bflgn = bnewv < 0;
		ccr_68000_long_move_ae_LZN(bnewv);
		SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
		SET_XFLG(GET_CFLG());
		SET_VFLG((bflgs ^ bflgn) & (bflgo ^ bflgn));
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta + 2, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 2, 0x1, newv, 1);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, newv >> 16); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 0, 0x1, newv >> 16, 1);
		return 28 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 28 * CYCLE_UNIT / 2 + count_cycles;
}
/* 28 (5/2) */
/* 6 0,0   */

/* ADD.L #<data>.L,-(An) */
uae_u32 REGPARAM2 op_06a0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 30; 
	uae_s32 src;
	src = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - 4;
	if (dsta & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, dsta, 2, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = get_word_000(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	dst |= get_word_000(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		m68k_areg(regs, dstreg) = dsta;
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) = dsta;
	uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u32)(~dst)) < ((uae_u32)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		uae_s16 bnewv = (uae_s16)dst + (uae_s16)src;
		int bflgs = ((uae_s16)(src)) < 0;
		int bflgo = ((uae_s16)(dst)) < 0;
		int bflgn = bnewv < 0;
		ccr_68000_long_move_ae_LZN(bnewv);
		SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
		SET_XFLG(GET_CFLG());
		SET_VFLG((bflgs ^ bflgn) & (bflgo ^ bflgn));
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 22 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta + 2, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 2, 0x1, newv, 1);
		return 26 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, newv >> 16); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 0, 0x1, newv >> 16, 1);
		return 30 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 30 * CYCLE_UNIT / 2 + count_cycles;
}
/* 30 (5/2) */
/* 6 0,0   */

/* ADD.L #<data>.L,(d16,An) */
uae_u32 REGPARAM2 op_06a8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 32; 
	uae_s32 src;
	src = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 8, -2);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, dsta, 2, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = get_word_000(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	dst |= get_word_000(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u32)(~dst)) < ((uae_u32)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(10);
	if(hardware_bus_error) {
		int pcoffset = 0;
		uae_s16 bnewv = (uae_s16)dst + (uae_s16)src;
		int bflgs = ((uae_s16)(src)) < 0;
		int bflgo = ((uae_s16)(dst)) < 0;
		int bflgn = bnewv < 0;
		ccr_68000_long_move_ae_LZN(bnewv);
		SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
		SET_XFLG(GET_CFLG());
		SET_VFLG((bflgs ^ bflgn) & (bflgo ^ bflgn));
		exception2_fetch_opcode(opcode, 10, pcoffset);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta + 2, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(10);
		exception2_write(opcode, dsta + 2, 0x1, newv, 1);
		return 28 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, newv >> 16); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(10);
		exception2_write(opcode, dsta + 0, 0x1, newv >> 16, 1);
		return 32 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(8);
	return 32 * CYCLE_UNIT / 2 + count_cycles;
}
/* 32 (6/2) */
/* 8 0,0   */

/* ADD.L #<data>.L,(d8,An,Xn) */
uae_u32 REGPARAM2 op_06b0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 34; 
	uae_s32 src;
	src = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	BusCyclePenalty += 2;
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_000_prefetch(8));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 8, -2);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, dsta, 2, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = get_word_000(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	dst |= get_word_000(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return 22 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u32)(~dst)) < ((uae_u32)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(10);
	if(hardware_bus_error) {
		int pcoffset = 0;
		uae_s16 bnewv = (uae_s16)dst + (uae_s16)src;
		int bflgs = ((uae_s16)(src)) < 0;
		int bflgo = ((uae_s16)(dst)) < 0;
		int bflgn = bnewv < 0;
		ccr_68000_long_move_ae_LZN(bnewv);
		SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
		SET_XFLG(GET_CFLG());
		SET_VFLG((bflgs ^ bflgn) & (bflgo ^ bflgn));
		exception2_fetch_opcode(opcode, 10, pcoffset);
		return 26 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta + 2, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(10);
		exception2_write(opcode, dsta + 2, 0x1, newv, 1);
		return 30 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, newv >> 16); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(10);
		exception2_write(opcode, dsta + 0, 0x1, newv >> 16, 1);
		return 34 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(8);
	return 34 * CYCLE_UNIT / 2 + count_cycles;
}
/* 34 (6/2) */
/* 8 4,0   */

/* ADD.L #<data>.L,(xxx).W */
uae_u32 REGPARAM2 op_06b8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 11;
	CurrentInstrCycles = 32; 
	uae_s32 src;
	src = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 8, 0);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(8);
		exception3_read_access(opcode, dsta, 2, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = get_word_000(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	dst |= get_word_000(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u32)(~dst)) < ((uae_u32)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(10);
	if(hardware_bus_error) {
		int pcoffset = 0;
		uae_s16 bnewv = (uae_s16)dst + (uae_s16)src;
		int bflgs = ((uae_s16)(src)) < 0;
		int bflgo = ((uae_s16)(dst)) < 0;
		int bflgn = bnewv < 0;
		ccr_68000_long_move_ae_LZN(bnewv);
		SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
		SET_XFLG(GET_CFLG());
		SET_VFLG((bflgs ^ bflgn) & (bflgo ^ bflgn));
		exception2_fetch_opcode(opcode, 10, pcoffset);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta + 2, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(10);
		exception2_write(opcode, dsta + 2, 0x1, newv, 1);
		return 28 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, newv >> 16); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(10);
		exception2_write(opcode, dsta + 0, 0x1, newv >> 16, 1);
		return 32 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(8);
	return 32 * CYCLE_UNIT / 2 + count_cycles;
}
/* 32 (6/2) */
/* 8 0,0   */

/* ADD.L #<data>.L,(xxx).L */
uae_u32 REGPARAM2 op_06b9_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 11;
	CurrentInstrCycles = 36; 
	uae_s32 src;
	src = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = get_word_000_prefetch(8) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 8, -2);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	dsta |= get_word_000_prefetch(10);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 10, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(10);
		exception3_read_access(opcode, dsta, 2, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = get_word_000(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(10);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	dst |= get_word_000(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(10);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u32)(~dst)) < ((uae_u32)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(12);
	if(hardware_bus_error) {
		int pcoffset = 0;
		uae_s16 bnewv = (uae_s16)dst + (uae_s16)src;
		int bflgs = ((uae_s16)(src)) < 0;
		int bflgo = ((uae_s16)(dst)) < 0;
		int bflgn = bnewv < 0;
		ccr_68000_long_move_ae_LZN(bnewv);
		SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
		SET_XFLG(GET_CFLG());
		SET_VFLG((bflgs ^ bflgn) & (bflgo ^ bflgn));
		exception2_fetch_opcode(opcode, 12, pcoffset);
		return 28 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta + 2, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(12);
		exception2_write(opcode, dsta + 2, 0x1, newv, 1);
		return 32 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, newv >> 16); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(12);
		exception2_write(opcode, dsta + 0, 0x1, newv >> 16, 1);
		return 36 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(10);
	return 36 * CYCLE_UNIT / 2 + count_cycles;
}
/* 36 (7/2) */
/* 10 0,0   */

/* BTST.L #<data>.W,Dn */
uae_u32 REGPARAM2 op_0800_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 21;
	CurrentInstrCycles = 10; 
	uae_s16 src = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	src &= 31;
	SET_ZFLG(1 ^ ((dst >> src) & 1));
	m68k_incpci(4);
	return 10 * CYCLE_UNIT / 2 + count_cycles;
}
/* 10 (2/0) */
/* 4 0,0   */

/* BTST.B #<data>.W,(An) */
uae_u32 REGPARAM2 op_0810_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 21;
	CurrentInstrCycles = 12; 
	uae_s16 src = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	src &= 7;
	SET_ZFLG(1 ^ ((dst >> src) & 1));
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (3/0) */
/* 4 0,0   */

/* BTST.B #<data>.W,(An)+ */
uae_u32 REGPARAM2 op_0818_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 21;
	CurrentInstrCycles = 12; 
	uae_s16 src = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
	src &= 7;
	SET_ZFLG(1 ^ ((dst >> src) & 1));
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (3/0) */
/* 4 0,0   */

/* BTST.B #<data>.W,-(An) */
uae_u32 REGPARAM2 op_0820_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 21;
	CurrentInstrCycles = 14; 
	uae_s16 src = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, dstreg) = dsta;
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) = dsta;
	src &= 7;
	SET_ZFLG(1 ^ ((dst >> src) & 1));
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 14 * CYCLE_UNIT / 2 + count_cycles;
}
/* 14 (3/0) */
/* 4 0,0   */

/* BTST.B #<data>.W,(d16,An) */
uae_u32 REGPARAM2 op_0828_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 21;
	CurrentInstrCycles = 16; 
	uae_s16 src = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	src &= 7;
	SET_ZFLG(1 ^ ((dst >> src) & 1));
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (4/0) */
/* 6 0,0   */

/* BTST.B #<data>.W,(d8,An,Xn) */
uae_u32 REGPARAM2 op_0830_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 21;
	CurrentInstrCycles = 18; 
	uae_s16 src = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	BusCyclePenalty += 2;
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_000_prefetch(6));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	src &= 7;
	SET_ZFLG(1 ^ ((dst >> src) & 1));
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (4/0) */
/* 6 4,0   */

/* BTST.B #<data>.W,(xxx).W */
uae_u32 REGPARAM2 op_0838_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 21;
	CurrentInstrCycles = 16; 
	uae_s16 src = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, 0);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	src &= 7;
	SET_ZFLG(1 ^ ((dst >> src) & 1));
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (4/0) */
/* 6 0,0   */

/* BTST.B #<data>.W,(xxx).L */
uae_u32 REGPARAM2 op_0839_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 21;
	CurrentInstrCycles = 20; 
	uae_s16 src = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = get_word_000_prefetch(6) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	dsta |= get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 8, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	src &= 7;
	SET_ZFLG(1 ^ ((dst >> src) & 1));
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(10);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 10, pcoffset);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(8);
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (5/0) */
/* 8 0,0   */

/* BTST.B #<data>.W,(d16,PC) */
uae_u32 REGPARAM2 op_083a_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 dstreg = 2;
	OpcodeFamily = 21;
	CurrentInstrCycles = 16; 
	uae_s16 src = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_getpci() + 4;
	dsta += (uae_s32)(uae_s16)get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x0, 2);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	src &= 7;
	SET_ZFLG(1 ^ ((dst >> src) & 1));
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (4/0) */
/* 6 0,0   */

/* BTST.B #<data>.W,(d8,PC,Xn) */
uae_u32 REGPARAM2 op_083b_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 dstreg = 3;
	OpcodeFamily = 21;
	CurrentInstrCycles = 18; 
	uae_s16 src = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	uaecptr tmppc = m68k_getpci() + 4;
	BusCyclePenalty += 2;
	dsta = get_disp_ea_000(tmppc, get_word_000_prefetch(6));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x0, 2);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	src &= 7;
	SET_ZFLG(1 ^ ((dst >> src) & 1));
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (4/0) */
/* 6 4,0   */

/* BCHG.L #<data>.W,Dn */
uae_u32 REGPARAM2 op_0840_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 22;
	CurrentInstrCycles = 10; 
	uae_s16 src = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	src &= 31;
	if (src > 15) {
		count_cycles +=  2 * CYCLE_UNIT / 2;
	}
	dst ^= (1 << src);
	SET_ZFLG(((uae_u32)dst & (1 << src)) >> src);
	m68k_dreg(regs, dstreg) = (dst);
	m68k_incpci(4);
	return 10 * CYCLE_UNIT / 2 + count_cycles;
}
/* 10+ (2/0) */
/* 4 0,0   */

/* BCHG.B #<data>.W,(An) */
uae_u32 REGPARAM2 op_0850_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 22;
	CurrentInstrCycles = 16; 
	uae_s16 src = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	src &= 7;
	dst ^= (1 << src);
	SET_ZFLG(((uae_u32)dst & (1 << src)) >> src);
	put_byte_000(dsta, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x0, dst, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 4 0,0   */

/* BCHG.B #<data>.W,(An)+ */
uae_u32 REGPARAM2 op_0858_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 22;
	CurrentInstrCycles = 16; 
	uae_s16 src = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	src &= 7;
	dst ^= (1 << src);
	SET_ZFLG(((uae_u32)dst & (1 << src)) >> src);
	put_byte_000(dsta, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x0, dst, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 4 0,0   */

/* BCHG.B #<data>.W,-(An) */
uae_u32 REGPARAM2 op_0860_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 22;
	CurrentInstrCycles = 18; 
	uae_s16 src = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, dstreg) = dsta;
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) = dsta;
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	src &= 7;
	dst ^= (1 << src);
	SET_ZFLG(((uae_u32)dst & (1 << src)) >> src);
	put_byte_000(dsta, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x0, dst, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (3/1) */
/* 4 0,0   */

/* BCHG.B #<data>.W,(d16,An) */
uae_u32 REGPARAM2 op_0868_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 22;
	CurrentInstrCycles = 20; 
	uae_s16 src = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	src &= 7;
	dst ^= (1 << src);
	SET_ZFLG(((uae_u32)dst & (1 << src)) >> src);
	put_byte_000(dsta, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 0, 0x0, dst, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (4/1) */
/* 6 0,0   */

/* BCHG.B #<data>.W,(d8,An,Xn) */
uae_u32 REGPARAM2 op_0870_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 22;
	CurrentInstrCycles = 22; 
	uae_s16 src = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	BusCyclePenalty += 2;
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_000_prefetch(6));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	src &= 7;
	dst ^= (1 << src);
	SET_ZFLG(((uae_u32)dst & (1 << src)) >> src);
	put_byte_000(dsta, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 0, 0x0, dst, 1);
		return 22 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 22 * CYCLE_UNIT / 2 + count_cycles;
}
/* 22 (4/1) */
/* 6 4,0   */

/* BCHG.B #<data>.W,(xxx).W */
uae_u32 REGPARAM2 op_0878_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 22;
	CurrentInstrCycles = 20; 
	uae_s16 src = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, 0);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	src &= 7;
	dst ^= (1 << src);
	SET_ZFLG(((uae_u32)dst & (1 << src)) >> src);
	put_byte_000(dsta, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 0, 0x0, dst, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (4/1) */
/* 6 0,0   */

/* BCHG.B #<data>.W,(xxx).L */
uae_u32 REGPARAM2 op_0879_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 22;
	CurrentInstrCycles = 24; 
	uae_s16 src = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = get_word_000_prefetch(6) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	dsta |= get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 8, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	get_word_000_prefetch(10);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 10, pcoffset);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	src &= 7;
	dst ^= (1 << src);
	SET_ZFLG(((uae_u32)dst & (1 << src)) >> src);
	put_byte_000(dsta, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(10);
		exception2_write(opcode, dsta + 0, 0x0, dst, 1);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(8);
	return 24 * CYCLE_UNIT / 2 + count_cycles;
}
/* 24 (5/1) */
/* 8 0,0   */

/* BCLR.L #<data>.W,Dn */
uae_u32 REGPARAM2 op_0880_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 23;
	CurrentInstrCycles = 12; 
	uae_s16 src = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	src &= 31;
	if (src > 15) {
		count_cycles +=  2 * CYCLE_UNIT / 2;
	}
	SET_ZFLG(1 ^ ((dst >> src) & 1));
	dst &= ~(1 << src);
	m68k_dreg(regs, dstreg) = (dst);
	m68k_incpci(4);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12+ (2/0) */
/* 4 0,0   */

/* BCLR.B #<data>.W,(An) */
uae_u32 REGPARAM2 op_0890_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 23;
	CurrentInstrCycles = 18; 
	uae_s16 src = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	src &= 7;
	SET_ZFLG(1 ^ ((dst >> src) & 1));
	dst &= ~(1 << src);
	put_byte_000(dsta, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x0, dst, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (3/1) */
/* 4 0,0   */

/* BCLR.B #<data>.W,(An)+ */
uae_u32 REGPARAM2 op_0898_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 23;
	CurrentInstrCycles = 18; 
	uae_s16 src = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	src &= 7;
	SET_ZFLG(1 ^ ((dst >> src) & 1));
	dst &= ~(1 << src);
	put_byte_000(dsta, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x0, dst, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (3/1) */
/* 4 0,0   */

/* BCLR.B #<data>.W,-(An) */
uae_u32 REGPARAM2 op_08a0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 23;
	CurrentInstrCycles = 20; 
	uae_s16 src = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, dstreg) = dsta;
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) = dsta;
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	src &= 7;
	SET_ZFLG(1 ^ ((dst >> src) & 1));
	dst &= ~(1 << src);
	put_byte_000(dsta, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x0, dst, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (3/1) */
/* 4 0,0   */

/* BCLR.B #<data>.W,(d16,An) */
uae_u32 REGPARAM2 op_08a8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 23;
	CurrentInstrCycles = 22; 
	uae_s16 src = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	src &= 7;
	SET_ZFLG(1 ^ ((dst >> src) & 1));
	dst &= ~(1 << src);
	put_byte_000(dsta, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 0, 0x0, dst, 1);
		return 22 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 22 * CYCLE_UNIT / 2 + count_cycles;
}
/* 22 (4/1) */
/* 6 0,0   */

/* BCLR.B #<data>.W,(d8,An,Xn) */
uae_u32 REGPARAM2 op_08b0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 23;
	CurrentInstrCycles = 24; 
	uae_s16 src = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	BusCyclePenalty += 2;
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_000_prefetch(6));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	src &= 7;
	SET_ZFLG(1 ^ ((dst >> src) & 1));
	dst &= ~(1 << src);
	put_byte_000(dsta, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 0, 0x0, dst, 1);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 24 * CYCLE_UNIT / 2 + count_cycles;
}
/* 24 (4/1) */
/* 6 4,0   */

/* BCLR.B #<data>.W,(xxx).W */
uae_u32 REGPARAM2 op_08b8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 23;
	CurrentInstrCycles = 22; 
	uae_s16 src = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, 0);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	src &= 7;
	SET_ZFLG(1 ^ ((dst >> src) & 1));
	dst &= ~(1 << src);
	put_byte_000(dsta, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 0, 0x0, dst, 1);
		return 22 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 22 * CYCLE_UNIT / 2 + count_cycles;
}
/* 22 (4/1) */
/* 6 0,0   */

/* BCLR.B #<data>.W,(xxx).L */
uae_u32 REGPARAM2 op_08b9_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 23;
	CurrentInstrCycles = 26; 
	uae_s16 src = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = get_word_000_prefetch(6) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	dsta |= get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 8, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	get_word_000_prefetch(10);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 10, pcoffset);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	src &= 7;
	SET_ZFLG(1 ^ ((dst >> src) & 1));
	dst &= ~(1 << src);
	put_byte_000(dsta, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(10);
		exception2_write(opcode, dsta + 0, 0x0, dst, 1);
		return 26 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(8);
	return 26 * CYCLE_UNIT / 2 + count_cycles;
}
/* 26 (5/1) */
/* 8 0,0   */

/* BSET.L #<data>.W,Dn */
uae_u32 REGPARAM2 op_08c0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 24;
	CurrentInstrCycles = 10; 
	uae_s16 src = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	src &= 31;
	if (src > 15) {
		count_cycles +=  2 * CYCLE_UNIT / 2;
	}
	SET_ZFLG(1 ^ ((dst >> src) & 1));
	dst |= (1 << src);
	m68k_dreg(regs, dstreg) = (dst);
	m68k_incpci(4);
	return 10 * CYCLE_UNIT / 2 + count_cycles;
}
/* 10+ (2/0) */
/* 4 0,0   */

/* BSET.B #<data>.W,(An) */
uae_u32 REGPARAM2 op_08d0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 24;
	CurrentInstrCycles = 16; 
	uae_s16 src = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	src &= 7;
	SET_ZFLG(1 ^ ((dst >> src) & 1));
	dst |= (1 << src);
	put_byte_000(dsta, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x0, dst, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 4 0,0   */

/* BSET.B #<data>.W,(An)+ */
uae_u32 REGPARAM2 op_08d8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 24;
	CurrentInstrCycles = 16; 
	uae_s16 src = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	src &= 7;
	SET_ZFLG(1 ^ ((dst >> src) & 1));
	dst |= (1 << src);
	put_byte_000(dsta, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x0, dst, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 4 0,0   */

/* BSET.B #<data>.W,-(An) */
uae_u32 REGPARAM2 op_08e0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 24;
	CurrentInstrCycles = 18; 
	uae_s16 src = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, dstreg) = dsta;
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) = dsta;
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	src &= 7;
	SET_ZFLG(1 ^ ((dst >> src) & 1));
	dst |= (1 << src);
	put_byte_000(dsta, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x0, dst, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (3/1) */
/* 4 0,0   */

/* BSET.B #<data>.W,(d16,An) */
uae_u32 REGPARAM2 op_08e8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 24;
	CurrentInstrCycles = 20; 
	uae_s16 src = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	src &= 7;
	SET_ZFLG(1 ^ ((dst >> src) & 1));
	dst |= (1 << src);
	put_byte_000(dsta, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 0, 0x0, dst, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (4/1) */
/* 6 0,0   */

/* BSET.B #<data>.W,(d8,An,Xn) */
uae_u32 REGPARAM2 op_08f0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 24;
	CurrentInstrCycles = 22; 
	uae_s16 src = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	BusCyclePenalty += 2;
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_000_prefetch(6));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	src &= 7;
	SET_ZFLG(1 ^ ((dst >> src) & 1));
	dst |= (1 << src);
	put_byte_000(dsta, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 0, 0x0, dst, 1);
		return 22 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 22 * CYCLE_UNIT / 2 + count_cycles;
}
/* 22 (4/1) */
/* 6 4,0   */

/* BSET.B #<data>.W,(xxx).W */
uae_u32 REGPARAM2 op_08f8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 24;
	CurrentInstrCycles = 20; 
	uae_s16 src = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, 0);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	src &= 7;
	SET_ZFLG(1 ^ ((dst >> src) & 1));
	dst |= (1 << src);
	put_byte_000(dsta, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 0, 0x0, dst, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (4/1) */
/* 6 0,0   */

/* BSET.B #<data>.W,(xxx).L */
uae_u32 REGPARAM2 op_08f9_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 24;
	CurrentInstrCycles = 24; 
	uae_s16 src = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = get_word_000_prefetch(6) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	dsta |= get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 8, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	get_word_000_prefetch(10);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 10, pcoffset);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	src &= 7;
	SET_ZFLG(1 ^ ((dst >> src) & 1));
	dst |= (1 << src);
	put_byte_000(dsta, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(10);
		exception2_write(opcode, dsta + 0, 0x0, dst, 1);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(8);
	return 24 * CYCLE_UNIT / 2 + count_cycles;
}
/* 24 (5/1) */
/* 8 0,0   */

/* EOR.B #<data>.B,Dn */
uae_u32 REGPARAM2 op_0a00_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 3;
	CurrentInstrCycles = 8;  
	uae_s8 src = (uae_u8)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = m68k_dreg(regs, dstreg);
	src ^= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8 (2/0) */
/* 4 0,0   */

/* EOR.B #<data>.B,(An) */
uae_u32 REGPARAM2 op_0a10_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 3;
	CurrentInstrCycles = 16; 
	uae_s8 src = (uae_u8)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	src ^= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_byte_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 4 0,0   */

/* EOR.B #<data>.B,(An)+ */
uae_u32 REGPARAM2 op_0a18_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 3;
	CurrentInstrCycles = 16; 
	uae_s8 src = (uae_u8)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
	src ^= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_byte_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 4 0,0   */

/* EOR.B #<data>.B,-(An) */
uae_u32 REGPARAM2 op_0a20_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 3;
	CurrentInstrCycles = 18; 
	uae_s8 src = (uae_u8)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, dstreg) = dsta;
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) = dsta;
	src ^= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_byte_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (3/1) */
/* 4 0,0   */

/* EOR.B #<data>.B,(d16,An) */
uae_u32 REGPARAM2 op_0a28_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 3;
	CurrentInstrCycles = 20; 
	uae_s8 src = (uae_u8)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	src ^= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_byte_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (4/1) */
/* 6 0,0   */

/* EOR.B #<data>.B,(d8,An,Xn) */
uae_u32 REGPARAM2 op_0a30_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 3;
	CurrentInstrCycles = 22; 
	uae_s8 src = (uae_u8)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	BusCyclePenalty += 2;
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_000_prefetch(6));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	src ^= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_byte_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return 22 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 22 * CYCLE_UNIT / 2 + count_cycles;
}
/* 22 (4/1) */
/* 6 4,0   */

/* EOR.B #<data>.B,(xxx).W */
uae_u32 REGPARAM2 op_0a38_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 3;
	CurrentInstrCycles = 20; 
	uae_s8 src = (uae_u8)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, 0);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	src ^= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_byte_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (4/1) */
/* 6 0,0   */

/* EOR.B #<data>.B,(xxx).L */
uae_u32 REGPARAM2 op_0a39_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 3;
	CurrentInstrCycles = 24; 
	uae_s8 src = (uae_u8)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = get_word_000_prefetch(6) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	dsta |= get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 8, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	src ^= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(10);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 10, pcoffset);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_byte_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(10);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(8);
	return 24 * CYCLE_UNIT / 2 + count_cycles;
}
/* 24 (5/1) */
/* 8 0,0   */

/* EORSR.B #<data>.W */
uae_u32 REGPARAM2 op_0a3c_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 6;
	CurrentInstrCycles = 16; 
	MakeSR();
	uae_s16 src = regs.irc;
	src &= 0xFF;
	regs.sr ^= src;
	MakeFromSR();
	m68k_incpci(4);
	get_word_000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, 0);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (2/0) */
/* 4 0,0   */

/* EOR.W #<data>.W,Dn */
uae_u32 REGPARAM2 op_0a40_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 3;
	CurrentInstrCycles = 8;  
	uae_s16 src = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	src ^= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8 (2/0) */
/* 4 0,0   */

/* EOR.W #<data>.W,(An) */
uae_u32 REGPARAM2 op_0a50_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 3;
	CurrentInstrCycles = 16; 
	uae_s16 src = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	if (dsta & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, dsta, 1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = get_word_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	src ^= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_word_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 4 0,0   */

/* EOR.W #<data>.W,(An)+ */
uae_u32 REGPARAM2 op_0a58_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 3;
	CurrentInstrCycles = 16; 
	uae_s16 src = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	if (dsta & 1) {
		m68k_areg(regs, dstreg) += 2 + 0;
		m68k_incpci(4);
		exception3_read_access(opcode, dsta, 1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = get_word_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, dstreg) += 2 + 0;
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) += 2;
	src ^= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_word_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 4 0,0   */

/* EOR.W #<data>.W,-(An) */
uae_u32 REGPARAM2 op_0a60_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 3;
	CurrentInstrCycles = 18; 
	uae_s16 src = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - 2;
	if (dsta & 1) {
		m68k_areg(regs, dstreg) = dsta;
		m68k_incpci(4);
		exception3_read_access(opcode, dsta, 1, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = get_word_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, dstreg) = dsta;
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) = dsta;
	src ^= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_word_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (3/1) */
/* 4 0,0   */

/* EOR.W #<data>.W,(d16,An) */
uae_u32 REGPARAM2 op_0a68_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 3;
	CurrentInstrCycles = 20; 
	uae_s16 src = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, dsta, 1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = get_word_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	src ^= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_word_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (4/1) */
/* 6 0,0   */

/* EOR.W #<data>.W,(d8,An,Xn) */
uae_u32 REGPARAM2 op_0a70_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 3;
	CurrentInstrCycles = 22; 
	uae_s16 src = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	BusCyclePenalty += 2;
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_000_prefetch(6));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, dsta, 1, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = get_word_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	src ^= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_word_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return 22 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 22 * CYCLE_UNIT / 2 + count_cycles;
}
/* 22 (4/1) */
/* 6 4,0   */

/* EOR.W #<data>.W,(xxx).W */
uae_u32 REGPARAM2 op_0a78_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 3;
	CurrentInstrCycles = 20; 
	uae_s16 src = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, 0);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, dsta, 1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = get_word_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	src ^= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_word_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (4/1) */
/* 6 0,0   */

/* EOR.W #<data>.W,(xxx).L */
uae_u32 REGPARAM2 op_0a79_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 3;
	CurrentInstrCycles = 24; 
	uae_s16 src = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = get_word_000_prefetch(6) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	dsta |= get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 8, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(8);
		exception3_read_access(opcode, dsta, 1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = get_word_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	src ^= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(10);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 10, pcoffset);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_word_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(10);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(8);
	return 24 * CYCLE_UNIT / 2 + count_cycles;
}
/* 24 (5/1) */
/* 8 0,0   */

/* EORSR.W #<data>.W */
uae_u32 REGPARAM2 op_0a7c_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 6;
	CurrentInstrCycles = 16; 
	if (!regs.s) {
		Exception(8);
		return 0;
	}
	MakeSR();
	uae_s16 src = regs.irc;
	regs.sr ^= src;
	MakeFromSR();
	m68k_incpci(4);
	get_word_000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, 0);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (2/0) */
/* 4 0,0   */

/* EOR.L #<data>.L,Dn */
uae_u32 REGPARAM2 op_0a80_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 3;
	CurrentInstrCycles = 16; 
	uae_s32 src;
	src = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	src ^= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		m68k_dreg(regs, dstreg) = (src);
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_dreg(regs, dstreg) = (src);
	m68k_incpci(6);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/0) */
/* 6 0,0   */

/* EOR.L #<data>.L,(An) */
uae_u32 REGPARAM2 op_0a90_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 3;
	CurrentInstrCycles = 28; 
	uae_s32 src;
	src = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	if (dsta & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, dsta, 2, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = get_word_000(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	dst |= get_word_000(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	src ^= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src >> 16); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return 28 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 28 * CYCLE_UNIT / 2 + count_cycles;
}
/* 28 (5/2) */
/* 6 0,0   */

/* EOR.L #<data>.L,(An)+ */
uae_u32 REGPARAM2 op_0a98_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 3;
	CurrentInstrCycles = 28; 
	uae_s32 src;
	src = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	if (dsta & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, dsta, 2, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = get_word_000(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	dst |= get_word_000(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) += 4;
	src ^= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src >> 16); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return 28 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 28 * CYCLE_UNIT / 2 + count_cycles;
}
/* 28 (5/2) */
/* 6 0,0   */

/* EOR.L #<data>.L,-(An) */
uae_u32 REGPARAM2 op_0aa0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 3;
	CurrentInstrCycles = 30; 
	uae_s32 src;
	src = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - 4;
	if (dsta & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, dsta, 2, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = get_word_000(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	dst |= get_word_000(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		m68k_areg(regs, dstreg) = dsta;
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) = dsta;
	src ^= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 22 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return 26 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src >> 16); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return 30 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 30 * CYCLE_UNIT / 2 + count_cycles;
}
/* 30 (5/2) */
/* 6 0,0   */

/* EOR.L #<data>.L,(d16,An) */
uae_u32 REGPARAM2 op_0aa8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 3;
	CurrentInstrCycles = 32; 
	uae_s32 src;
	src = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 8, -2);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, dsta, 2, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = get_word_000(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	dst |= get_word_000(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	src ^= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(10);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch_opcode(opcode, 10, pcoffset);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(10);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return 28 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src >> 16); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(10);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return 32 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(8);
	return 32 * CYCLE_UNIT / 2 + count_cycles;
}
/* 32 (6/2) */
/* 8 0,0   */

/* EOR.L #<data>.L,(d8,An,Xn) */
uae_u32 REGPARAM2 op_0ab0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 3;
	CurrentInstrCycles = 34; 
	uae_s32 src;
	src = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	BusCyclePenalty += 2;
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_000_prefetch(8));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 8, -2);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, dsta, 2, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = get_word_000(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	dst |= get_word_000(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return 22 * CYCLE_UNIT / 2 + count_cycles;
	}
	src ^= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(10);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch_opcode(opcode, 10, pcoffset);
		return 26 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(10);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return 30 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src >> 16); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(10);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return 34 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(8);
	return 34 * CYCLE_UNIT / 2 + count_cycles;
}
/* 34 (6/2) */
/* 8 4,0   */

/* EOR.L #<data>.L,(xxx).W */
uae_u32 REGPARAM2 op_0ab8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 3;
	CurrentInstrCycles = 32; 
	uae_s32 src;
	src = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 8, 0);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(8);
		exception3_read_access(opcode, dsta, 2, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = get_word_000(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	dst |= get_word_000(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	src ^= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(10);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch_opcode(opcode, 10, pcoffset);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(10);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return 28 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src >> 16); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(10);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return 32 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(8);
	return 32 * CYCLE_UNIT / 2 + count_cycles;
}
/* 32 (6/2) */
/* 8 0,0   */

/* EOR.L #<data>.L,(xxx).L */
uae_u32 REGPARAM2 op_0ab9_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 3;
	CurrentInstrCycles = 36; 
	uae_s32 src;
	src = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = get_word_000_prefetch(8) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 8, -2);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	dsta |= get_word_000_prefetch(10);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 10, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(10);
		exception3_read_access(opcode, dsta, 2, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = get_word_000(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(10);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	dst |= get_word_000(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(10);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	src ^= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(12);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch_opcode(opcode, 12, pcoffset);
		return 28 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(12);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return 32 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src >> 16); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(12);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return 36 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(10);
	return 36 * CYCLE_UNIT / 2 + count_cycles;
}
/* 36 (7/2) */
/* 10 0,0   */

/* CMP.B #<data>.B,Dn */
uae_u32 REGPARAM2 op_0c00_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 25;
	CurrentInstrCycles = 8;  
	uae_s8 src = (uae_u8)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8 (2/0) */
/* 4 0,0   */

/* CMP.B #<data>.B,(An) */
uae_u32 REGPARAM2 op_0c10_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 25;
	CurrentInstrCycles = 12; 
	uae_s8 src = (uae_u8)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (3/0) */
/* 4 0,0   */

/* CMP.B #<data>.B,(An)+ */
uae_u32 REGPARAM2 op_0c18_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 25;
	CurrentInstrCycles = 12; 
	uae_s8 src = (uae_u8)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
	uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (3/0) */
/* 4 0,0   */

/* CMP.B #<data>.B,-(An) */
uae_u32 REGPARAM2 op_0c20_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 25;
	CurrentInstrCycles = 14; 
	uae_s8 src = (uae_u8)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, dstreg) = dsta;
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) = dsta;
	uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 14 * CYCLE_UNIT / 2 + count_cycles;
}
/* 14 (3/0) */
/* 4 0,0   */

/* CMP.B #<data>.B,(d16,An) */
uae_u32 REGPARAM2 op_0c28_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 25;
	CurrentInstrCycles = 16; 
	uae_s8 src = (uae_u8)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (4/0) */
/* 6 0,0   */

/* CMP.B #<data>.B,(d8,An,Xn) */
uae_u32 REGPARAM2 op_0c30_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 25;
	CurrentInstrCycles = 18; 
	uae_s8 src = (uae_u8)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	BusCyclePenalty += 2;
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_000_prefetch(6));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (4/0) */
/* 6 4,0   */

/* CMP.B #<data>.B,(xxx).W */
uae_u32 REGPARAM2 op_0c38_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 25;
	CurrentInstrCycles = 16; 
	uae_s8 src = (uae_u8)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, 0);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (4/0) */
/* 6 0,0   */

/* CMP.B #<data>.B,(xxx).L */
uae_u32 REGPARAM2 op_0c39_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 25;
	CurrentInstrCycles = 20; 
	uae_s8 src = (uae_u8)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = get_word_000_prefetch(6) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	dsta |= get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 8, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(10);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 10, pcoffset);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(8);
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (5/0) */
/* 8 0,0   */

/* CMP.W #<data>.W,Dn */
uae_u32 REGPARAM2 op_0c40_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 25;
	CurrentInstrCycles = 8;  
	uae_s16 src = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8 (2/0) */
/* 4 0,0   */

/* CMP.W #<data>.W,(An) */
uae_u32 REGPARAM2 op_0c50_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 25;
	CurrentInstrCycles = 12; 
	uae_s16 src = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	if (dsta & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, dsta, 1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = get_word_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (3/0) */
/* 4 0,0   */

/* CMP.W #<data>.W,(An)+ */
uae_u32 REGPARAM2 op_0c58_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 25;
	CurrentInstrCycles = 12; 
	uae_s16 src = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	if (dsta & 1) {
		m68k_areg(regs, dstreg) += 2 + 0;
		m68k_incpci(4);
		exception3_read_access(opcode, dsta, 1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = get_word_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, dstreg) += 2 + 0;
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) += 2;
	uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (3/0) */
/* 4 0,0   */

/* CMP.W #<data>.W,-(An) */
uae_u32 REGPARAM2 op_0c60_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 25;
	CurrentInstrCycles = 14; 
	uae_s16 src = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - 2;
	if (dsta & 1) {
		m68k_areg(regs, dstreg) = dsta;
		m68k_incpci(4);
		exception3_read_access(opcode, dsta, 1, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = get_word_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, dstreg) = dsta;
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) = dsta;
	uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 14 * CYCLE_UNIT / 2 + count_cycles;
}
/* 14 (3/0) */
/* 4 0,0   */

/* CMP.W #<data>.W,(d16,An) */
uae_u32 REGPARAM2 op_0c68_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 25;
	CurrentInstrCycles = 16; 
	uae_s16 src = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, dsta, 1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = get_word_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (4/0) */
/* 6 0,0   */

/* CMP.W #<data>.W,(d8,An,Xn) */
uae_u32 REGPARAM2 op_0c70_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 25;
	CurrentInstrCycles = 18; 
	uae_s16 src = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	BusCyclePenalty += 2;
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_000_prefetch(6));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, dsta, 1, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = get_word_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (4/0) */
/* 6 4,0   */

/* CMP.W #<data>.W,(xxx).W */
uae_u32 REGPARAM2 op_0c78_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 25;
	CurrentInstrCycles = 16; 
	uae_s16 src = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, 0);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, dsta, 1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = get_word_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (4/0) */
/* 6 0,0   */

/* CMP.W #<data>.W,(xxx).L */
uae_u32 REGPARAM2 op_0c79_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 25;
	CurrentInstrCycles = 20; 
	uae_s16 src = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = get_word_000_prefetch(6) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	dsta |= get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 8, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(8);
		exception3_read_access(opcode, dsta, 1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = get_word_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(10);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 10, pcoffset);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(8);
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (5/0) */
/* 8 0,0   */

/* CMP.L #<data>.L,Dn */
uae_u32 REGPARAM2 op_0c80_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 25;
	CurrentInstrCycles = 14; 
	uae_s32 src;
	src = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	m68k_incpci(6);
	return 14 * CYCLE_UNIT / 2 + count_cycles;
}
/* 14 (3/0) */
/* 6 0,0   */

/* CMP.L #<data>.L,(An) */
uae_u32 REGPARAM2 op_0c90_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 25;
	CurrentInstrCycles = 20; 
	uae_s32 src;
	src = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	if (dsta & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, dsta, 2, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = get_word_000(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	dst |= get_word_000(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (5/0) */
/* 6 0,0   */

/* CMP.L #<data>.L,(An)+ */
uae_u32 REGPARAM2 op_0c98_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 25;
	CurrentInstrCycles = 20; 
	uae_s32 src;
	src = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	if (dsta & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, dsta, 2, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = get_word_000(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	dst |= get_word_000(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) += 4;
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (5/0) */
/* 6 0,0   */

/* CMP.L #<data>.L,-(An) */
uae_u32 REGPARAM2 op_0ca0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 25;
	CurrentInstrCycles = 22; 
	uae_s32 src;
	src = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - 4;
	if (dsta & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, dsta, 2, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = get_word_000(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	dst |= get_word_000(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		m68k_areg(regs, dstreg) = dsta;
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) = dsta;
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 22 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 22 * CYCLE_UNIT / 2 + count_cycles;
}
/* 22 (5/0) */
/* 6 0,0   */

/* CMP.L #<data>.L,(d16,An) */
uae_u32 REGPARAM2 op_0ca8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 25;
	CurrentInstrCycles = 24; 
	uae_s32 src;
	src = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 8, -2);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, dsta, 2, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = get_word_000(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	dst |= get_word_000(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(10);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 10, pcoffset);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(8);
	return 24 * CYCLE_UNIT / 2 + count_cycles;
}
/* 24 (6/0) */
/* 8 0,0   */

/* CMP.L #<data>.L,(d8,An,Xn) */
uae_u32 REGPARAM2 op_0cb0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 25;
	CurrentInstrCycles = 26; 
	uae_s32 src;
	src = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	BusCyclePenalty += 2;
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_000_prefetch(8));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 8, -2);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, dsta, 2, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = get_word_000(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	dst |= get_word_000(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return 22 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(10);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 10, pcoffset);
		return 26 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(8);
	return 26 * CYCLE_UNIT / 2 + count_cycles;
}
/* 26 (6/0) */
/* 8 4,0   */

/* CMP.L #<data>.L,(xxx).W */
uae_u32 REGPARAM2 op_0cb8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 25;
	CurrentInstrCycles = 24; 
	uae_s32 src;
	src = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 8, 0);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(8);
		exception3_read_access(opcode, dsta, 2, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = get_word_000(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	dst |= get_word_000(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(10);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 10, pcoffset);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(8);
	return 24 * CYCLE_UNIT / 2 + count_cycles;
}
/* 24 (6/0) */
/* 8 0,0   */

/* CMP.L #<data>.L,(xxx).L */
uae_u32 REGPARAM2 op_0cb9_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 25;
	CurrentInstrCycles = 28; 
	uae_s32 src;
	src = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = get_word_000_prefetch(8) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 8, -2);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	dsta |= get_word_000_prefetch(10);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 10, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(10);
		exception3_read_access(opcode, dsta, 2, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = get_word_000(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(10);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	dst |= get_word_000(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(10);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(12);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 12, pcoffset);
		return 28 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(10);
	return 28 * CYCLE_UNIT / 2 + count_cycles;
}
/* 28 (7/0) */
/* 10 0,0   */

/* MOVES.B #<data>.W,(An) */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_0e10_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 103;
	CurrentInstrCycles = 18; 
	if (!regs.s) {
		Exception(8);
		return 0;
	}
	uae_s16 extra = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (extra & 0x800) {
		uae_u32 src = regs.regs[(extra >> 12) & 15];
		uaecptr dsta;
		dsta = m68k_areg(regs, dstreg);
		dfc_nommu_put_byte(dsta, src);
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(6);
			regs.irc = extra;
			exception2_write(opcode, dsta + 0, 0x0, src, 1);
			return 14 * CYCLE_UNIT / 2 + count_cycles;
		}
		m68k_incpci(4);
	} else {
		uaecptr srca;
		srca = m68k_areg(regs, dstreg);
		uae_s8 src = sfc_nommu_get_byte(srca);
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(4);
			regs.irc = extra;
			regs.write_buffer = extra;
			exception2_read(opcode, srca + 0, 0x0, 1);
			return 14 * CYCLE_UNIT / 2 + count_cycles;
		}
		if (extra & 0x8000) {
			m68k_areg(regs, (extra >> 12) & 7) = (uae_s32)(uae_s8)src;
		} else {
			m68k_dreg(regs, (extra >> 12) & 7) = (m68k_dreg(regs, (extra >> 12) & 7) & ~0xff) | ((src) & 0xff);
		}
		m68k_incpci(4);
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (3/0) */
/* 4 0,0   */

#endif
/* MOVES.B #<data>.W,(An)+ */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_0e18_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 103;
	CurrentInstrCycles = 20; 
	if (!regs.s) {
		Exception(8);
		return 0;
	}
	uae_s16 extra = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (extra & 0x800) {
		uae_u32 src = regs.regs[(extra >> 12) & 15];
		uaecptr dsta;
		dsta = m68k_areg(regs, dstreg);
		m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
		src = regs.regs[(extra >> 12) & 15];
		dfc_nommu_put_byte(dsta, src);
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(6);
			regs.irc = extra;
			exception2_write(opcode, dsta + 0, 0x0, src, 1);
			return 16 * CYCLE_UNIT / 2 + count_cycles;
		}
		m68k_incpci(4);
	} else {
		uaecptr srca;
		srca = m68k_areg(regs, dstreg);
		uae_s8 src = sfc_nommu_get_byte(srca);
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(4);
			regs.irc = extra;
			regs.write_buffer = extra;
			exception2_read(opcode, srca + 0, 0x0, 1);
			return 16 * CYCLE_UNIT / 2 + count_cycles;
		}
		m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
		if (extra & 0x8000) {
			m68k_areg(regs, (extra >> 12) & 7) = (uae_s32)(uae_s8)src;
		} else {
			m68k_dreg(regs, (extra >> 12) & 7) = (m68k_dreg(regs, (extra >> 12) & 7) & ~0xff) | ((src) & 0xff);
		}
		m68k_incpci(4);
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (3/0) */
/* 4 0,0   */

#endif
/* MOVES.B #<data>.W,-(An) */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_0e20_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 103;
	CurrentInstrCycles = 20; 
	if (!regs.s) {
		Exception(8);
		return 0;
	}
	uae_s16 extra = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (extra & 0x800) {
		uae_u32 src = regs.regs[(extra >> 12) & 15];
		uaecptr dsta;
		dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
		m68k_areg(regs, dstreg) = dsta;
		src = regs.regs[(extra >> 12) & 15];
		dfc_nommu_put_byte(dsta, src);
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(6);
			regs.irc = extra;
			exception2_write(opcode, dsta + 0, 0x0, src, 1);
			return 16 * CYCLE_UNIT / 2 + count_cycles;
		}
		m68k_incpci(4);
	} else {
		uaecptr srca;
		srca = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
		uae_s8 src = sfc_nommu_get_byte(srca);
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(4);
			m68k_areg(regs, dstreg) = srca;
			regs.irc = extra;
			regs.write_buffer = extra;
			m68k_incpci(2);
			exception2_read(opcode, srca + 0, 0x0, 1);
			return 16 * CYCLE_UNIT / 2 + count_cycles;
		}
		m68k_areg(regs, dstreg) = srca;
		if (extra & 0x8000) {
			m68k_areg(regs, (extra >> 12) & 7) = (uae_s32)(uae_s8)src;
		} else {
			m68k_dreg(regs, (extra >> 12) & 7) = (m68k_dreg(regs, (extra >> 12) & 7) & ~0xff) | ((src) & 0xff);
		}
		m68k_incpci(4);
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (3/0) */
/* 4 0,0   */

#endif
/* MOVES.B #<data>.W,(d16,An) */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_0e28_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 103;
	CurrentInstrCycles = 20; 
	if (!regs.s) {
		Exception(8);
		return 0;
	}
	uae_s16 extra = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (extra & 0x800) {
		uae_u32 src = regs.regs[(extra >> 12) & 15];
		uaecptr dsta;
		dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_000_prefetch(6);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch(opcode, 6, -2);
			return 12 * CYCLE_UNIT / 2 + count_cycles;
		}
		dfc_nommu_put_byte(dsta, src);
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(8);
			regs.irc = extra;
			exception2_write(opcode, dsta + 0, 0x0, src, 1);
			return 16 * CYCLE_UNIT / 2 + count_cycles;
		}
		m68k_incpci(6);
	} else {
		uaecptr srca;
		srca = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_000_prefetch(6);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch(opcode, 6, -2);
			return 12 * CYCLE_UNIT / 2 + count_cycles;
		}
		uae_s8 src = sfc_nommu_get_byte(srca);
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(4);
			regs.irc = extra;
			regs.write_buffer = extra;
			m68k_incpci(4);
			exception2_read(opcode, srca + 0, 0x0, 1);
			return 16 * CYCLE_UNIT / 2 + count_cycles;
		}
		if (extra & 0x8000) {
			m68k_areg(regs, (extra >> 12) & 7) = (uae_s32)(uae_s8)src;
		} else {
			m68k_dreg(regs, (extra >> 12) & 7) = (m68k_dreg(regs, (extra >> 12) & 7) & ~0xff) | ((src) & 0xff);
		}
		m68k_incpci(6);
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (4/0) */
/* 6 0,0   */

#endif
/* MOVES.B #<data>.W,(d8,An,Xn) */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_0e30_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 103;
	CurrentInstrCycles = 24; 
	if (!regs.s) {
		Exception(8);
		return 0;
	}
	uae_s16 extra = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (extra & 0x800) {
		uae_u32 src = regs.regs[(extra >> 12) & 15];
		uaecptr dsta;
		dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_000_prefetch(6));
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch(opcode, 6, -2);
			return 16 * CYCLE_UNIT / 2 + count_cycles;
		}
		dfc_nommu_put_byte(dsta, src);
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(8);
			regs.irc = extra;
			exception2_write(opcode, dsta + 0, 0x0, src, 1);
			return 20 * CYCLE_UNIT / 2 + count_cycles;
		}
		m68k_incpci(6);
	} else {
		uaecptr srca;
		srca = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_000_prefetch(6));
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch(opcode, 6, -2);
			return 16 * CYCLE_UNIT / 2 + count_cycles;
		}
		uae_s8 src = sfc_nommu_get_byte(srca);
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(4);
			regs.irc = extra;
			regs.write_buffer = extra;
			m68k_incpci(4);
			exception2_read(opcode, srca + 0, 0x0, 1);
			return 20 * CYCLE_UNIT / 2 + count_cycles;
		}
		if (extra & 0x8000) {
			m68k_areg(regs, (extra >> 12) & 7) = (uae_s32)(uae_s8)src;
		} else {
			m68k_dreg(regs, (extra >> 12) & 7) = (m68k_dreg(regs, (extra >> 12) & 7) & ~0xff) | ((src) & 0xff);
		}
		m68k_incpci(6);
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 24 * CYCLE_UNIT / 2 + count_cycles;
}
/* 24 (4/0) */
/* 6 4,4   */

#endif
/* MOVES.B #<data>.W,(xxx).W */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_0e38_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 103;
	CurrentInstrCycles = 20; 
	if (!regs.s) {
		Exception(8);
		return 0;
	}
	uae_s16 extra = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (extra & 0x800) {
		uae_u32 src = regs.regs[(extra >> 12) & 15];
		uaecptr dsta;
		dsta = (uae_s32)(uae_s16)get_word_000_prefetch(6);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch(opcode, 6, 0);
			return 12 * CYCLE_UNIT / 2 + count_cycles;
		}
		dfc_nommu_put_byte(dsta, src);
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(8);
			regs.irc = extra;
			exception2_write(opcode, dsta + 0, 0x0, src, 1);
			return 16 * CYCLE_UNIT / 2 + count_cycles;
		}
		m68k_incpci(6);
	} else {
		uaecptr srca;
		srca = (uae_s32)(uae_s16)get_word_000_prefetch(6);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch(opcode, 6, 0);
			return 12 * CYCLE_UNIT / 2 + count_cycles;
		}
		uae_s8 src = sfc_nommu_get_byte(srca);
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(6);
			regs.irc = extra;
			regs.write_buffer = extra;
			m68k_incpci(4);
			exception2_read(opcode, srca + 0, 0x0, 1);
			return 16 * CYCLE_UNIT / 2 + count_cycles;
		}
		if (extra & 0x8000) {
			m68k_areg(regs, (extra >> 12) & 7) = (uae_s32)(uae_s8)src;
		} else {
			m68k_dreg(regs, (extra >> 12) & 7) = (m68k_dreg(regs, (extra >> 12) & 7) & ~0xff) | ((src) & 0xff);
		}
		m68k_incpci(6);
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (4/0) */
/* 6 0,0   */

#endif
/* MOVES.B #<data>.W,(xxx).L */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_0e39_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 103;
	CurrentInstrCycles = 24; 
	if (!regs.s) {
		Exception(8);
		return 0;
	}
	uae_s16 extra = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (extra & 0x800) {
		uae_u32 src = regs.regs[(extra >> 12) & 15];
		uaecptr dsta;
		dsta = get_word_000_prefetch(6) << 16;
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch(opcode, 6, -2);
			return 12 * CYCLE_UNIT / 2 + count_cycles;
		}
		dsta |= get_word_000_prefetch(8);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch(opcode, 8, pcoffset);
			return 16 * CYCLE_UNIT / 2 + count_cycles;
		}
		dfc_nommu_put_byte(dsta, src);
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(10);
			regs.irc = extra;
			exception2_write(opcode, dsta + 0, 0x0, src, 1);
			return 20 * CYCLE_UNIT / 2 + count_cycles;
		}
		m68k_incpci(8);
	} else {
		uaecptr srca;
		srca = get_word_000_prefetch(6) << 16;
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch(opcode, 6, -2);
			return 12 * CYCLE_UNIT / 2 + count_cycles;
		}
		srca |= get_word_000_prefetch(8);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch(opcode, 8, pcoffset);
			return 16 * CYCLE_UNIT / 2 + count_cycles;
		}
		uae_s8 src = sfc_nommu_get_byte(srca);
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(8);
			regs.irc = extra;
			regs.write_buffer = extra;
			m68k_incpci(2);
			exception2_read(opcode, srca + 0, 0x0, 1);
			return 20 * CYCLE_UNIT / 2 + count_cycles;
		}
		if (extra & 0x8000) {
			m68k_areg(regs, (extra >> 12) & 7) = (uae_s32)(uae_s8)src;
		} else {
			m68k_dreg(regs, (extra >> 12) & 7) = (m68k_dreg(regs, (extra >> 12) & 7) & ~0xff) | ((src) & 0xff);
		}
		m68k_incpci(8);
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 24 * CYCLE_UNIT / 2 + count_cycles;
}
/* 24 (5/0) */
/* 8 0,0   */

#endif
/* MOVES.W #<data>.W,(An) */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_0e50_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 103;
	CurrentInstrCycles = 18; 
	if (!regs.s) {
		Exception(8);
		return 0;
	}
	uae_s16 extra = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (extra & 0x800) {
		uae_u32 src = regs.regs[(extra >> 12) & 15];
		uaecptr dsta;
		dsta = m68k_areg(regs, dstreg);
		if (dsta & 1) {
			regs.irc = extra;
			m68k_incpci(6);
			exception3_write_access(opcode, dsta, 1, src, 1);
			return 10 * CYCLE_UNIT / 2 + count_cycles;
		}
		dfc_nommu_put_word(dsta, src);
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(6);
			regs.irc = extra;
			exception2_write(opcode, dsta + 0, 0x1, src, 1);
			return 14 * CYCLE_UNIT / 2 + count_cycles;
		}
		m68k_incpci(4);
	} else {
		uaecptr srca;
		srca = m68k_areg(regs, dstreg);
		if (srca & 1) {
			regs.irc = extra;
			regs.write_buffer = extra;
			m68k_incpci(6);
			exception3_read_access(opcode, srca, 1, 1);
			return 10 * CYCLE_UNIT / 2 + count_cycles;
		}
		uae_s16 src = sfc_nommu_get_word(srca);
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(4);
			regs.irc = extra;
			regs.write_buffer = extra;
			exception2_read(opcode, srca + 0, 0x1, 1);
			return 14 * CYCLE_UNIT / 2 + count_cycles;
		}
		if (extra & 0x8000) {
			m68k_areg(regs, (extra >> 12) & 7) = (uae_s32)(uae_s16)src;
		} else {
			m68k_dreg(regs, (extra >> 12) & 7) = (m68k_dreg(regs, (extra >> 12) & 7) & ~0xffff) | ((src) & 0xffff);
		}
		m68k_incpci(4);
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (3/0) */
/* 4 0,0   */

#endif
/* MOVES.W #<data>.W,(An)+ */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_0e58_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 103;
	CurrentInstrCycles = 20; 
	if (!regs.s) {
		Exception(8);
		return 0;
	}
	uae_s16 extra = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (extra & 0x800) {
		uae_u32 src = regs.regs[(extra >> 12) & 15];
		uaecptr dsta;
		dsta = m68k_areg(regs, dstreg);
		if (dsta & 1) {
			m68k_areg(regs, dstreg) += 2 + 0;
			regs.irc = extra;
			if (dstreg + 8 == ((extra >> 12) & 15)) {
				src += 2;
			}
			m68k_incpci(6);
			exception3_write_access(opcode, dsta, 1, src, 1);
			return 12 * CYCLE_UNIT / 2 + count_cycles;
		}
		m68k_areg(regs, dstreg) += 2;
		src = regs.regs[(extra >> 12) & 15];
		dfc_nommu_put_word(dsta, src);
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(6);
			regs.irc = extra;
			exception2_write(opcode, dsta + 0, 0x1, src, 1);
			return 16 * CYCLE_UNIT / 2 + count_cycles;
		}
		m68k_incpci(4);
	} else {
		uaecptr srca;
		srca = m68k_areg(regs, dstreg);
		if (srca & 1) {
			m68k_areg(regs, dstreg) += 2 + 0;
			regs.irc = extra;
			regs.write_buffer = extra;
			m68k_incpci(6);
			exception3_read_access(opcode, srca, 1, 1);
			return 12 * CYCLE_UNIT / 2 + count_cycles;
		}
		uae_s16 src = sfc_nommu_get_word(srca);
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(4);
			m68k_areg(regs, dstreg) += 2 + 0;
			regs.irc = extra;
			regs.write_buffer = extra;
			exception2_read(opcode, srca + 0, 0x1, 1);
			return 16 * CYCLE_UNIT / 2 + count_cycles;
		}
		m68k_areg(regs, dstreg) += 2;
		if (extra & 0x8000) {
			m68k_areg(regs, (extra >> 12) & 7) = (uae_s32)(uae_s16)src;
		} else {
			m68k_dreg(regs, (extra >> 12) & 7) = (m68k_dreg(regs, (extra >> 12) & 7) & ~0xffff) | ((src) & 0xffff);
		}
		m68k_incpci(4);
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (3/0) */
/* 4 0,0   */

#endif
/* MOVES.W #<data>.W,-(An) */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_0e60_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 103;
	CurrentInstrCycles = 20; 
	if (!regs.s) {
		Exception(8);
		return 0;
	}
	uae_s16 extra = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (extra & 0x800) {
		uae_u32 src = regs.regs[(extra >> 12) & 15];
		uaecptr dsta;
		dsta = m68k_areg(regs, dstreg) - 2;
		if (dsta & 1) {
			regs.irc = extra;
			if (dstreg + 8 == ((extra >> 12) & 15)) {
				src += -2;
			}
			m68k_areg(regs, dstreg) = dsta;
			m68k_incpci(6);
			exception3_write_access(opcode, dsta, 1, src, 1);
			return 12 * CYCLE_UNIT / 2 + count_cycles;
		}
		m68k_areg(regs, dstreg) = dsta;
		src = regs.regs[(extra >> 12) & 15];
		dfc_nommu_put_word(dsta, src);
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(6);
			regs.irc = extra;
			exception2_write(opcode, dsta + 0, 0x1, src, 1);
			return 16 * CYCLE_UNIT / 2 + count_cycles;
		}
		m68k_incpci(4);
	} else {
		uaecptr srca;
		srca = m68k_areg(regs, dstreg) - 2;
		if (srca & 1) {
			regs.irc = extra;
			regs.write_buffer = extra;
			m68k_areg(regs, dstreg) = srca;
			m68k_incpci(6);
			exception3_read_access(opcode, srca, 1, 1);
			return 12 * CYCLE_UNIT / 2 + count_cycles;
		}
		uae_s16 src = sfc_nommu_get_word(srca);
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(4);
			m68k_areg(regs, dstreg) = srca;
			regs.irc = extra;
			regs.write_buffer = extra;
			m68k_incpci(2);
			exception2_read(opcode, srca + 0, 0x1, 1);
			return 16 * CYCLE_UNIT / 2 + count_cycles;
		}
		m68k_areg(regs, dstreg) = srca;
		if (extra & 0x8000) {
			m68k_areg(regs, (extra >> 12) & 7) = (uae_s32)(uae_s16)src;
		} else {
			m68k_dreg(regs, (extra >> 12) & 7) = (m68k_dreg(regs, (extra >> 12) & 7) & ~0xffff) | ((src) & 0xffff);
		}
		m68k_incpci(4);
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (3/0) */
/* 4 0,0   */

#endif
/* MOVES.W #<data>.W,(d16,An) */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_0e68_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 103;
	CurrentInstrCycles = 20; 
	if (!regs.s) {
		Exception(8);
		return 0;
	}
	uae_s16 extra = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (extra & 0x800) {
		uae_u32 src = regs.regs[(extra >> 12) & 15];
		uaecptr dsta;
		dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_000_prefetch(6);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch(opcode, 6, -2);
			return 12 * CYCLE_UNIT / 2 + count_cycles;
		}
		if (dsta & 1) {
			regs.irc = extra;
			m68k_incpci(8);
			exception3_write_access(opcode, dsta, 1, src, 1);
			return 12 * CYCLE_UNIT / 2 + count_cycles;
		}
		dfc_nommu_put_word(dsta, src);
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(8);
			regs.irc = extra;
			exception2_write(opcode, dsta + 0, 0x1, src, 1);
			return 16 * CYCLE_UNIT / 2 + count_cycles;
		}
		m68k_incpci(6);
	} else {
		uaecptr srca;
		srca = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_000_prefetch(6);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch(opcode, 6, -2);
			return 12 * CYCLE_UNIT / 2 + count_cycles;
		}
		if (srca & 1) {
			regs.irc = extra;
			regs.write_buffer = extra;
			m68k_incpci(6);
			exception3_read_access(opcode, srca, 1, 1);
			return 12 * CYCLE_UNIT / 2 + count_cycles;
		}
		uae_s16 src = sfc_nommu_get_word(srca);
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(4);
			regs.irc = extra;
			regs.write_buffer = extra;
			m68k_incpci(4);
			exception2_read(opcode, srca + 0, 0x1, 1);
			return 16 * CYCLE_UNIT / 2 + count_cycles;
		}
		if (extra & 0x8000) {
			m68k_areg(regs, (extra >> 12) & 7) = (uae_s32)(uae_s16)src;
		} else {
			m68k_dreg(regs, (extra >> 12) & 7) = (m68k_dreg(regs, (extra >> 12) & 7) & ~0xffff) | ((src) & 0xffff);
		}
		m68k_incpci(6);
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (4/0) */
/* 6 0,0   */

#endif
/* MOVES.W #<data>.W,(d8,An,Xn) */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_0e70_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 103;
	CurrentInstrCycles = 24; 
	if (!regs.s) {
		Exception(8);
		return 0;
	}
	uae_s16 extra = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (extra & 0x800) {
		uae_u32 src = regs.regs[(extra >> 12) & 15];
		uaecptr dsta;
		dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_000_prefetch(6));
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch(opcode, 6, -2);
			return 16 * CYCLE_UNIT / 2 + count_cycles;
		}
		if (dsta & 1) {
			regs.irc = extra;
			m68k_incpci(8);
			exception3_write_access(opcode, dsta, 1, src, 1);
			return 16 * CYCLE_UNIT / 2 + count_cycles;
		}
		dfc_nommu_put_word(dsta, src);
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(8);
			regs.irc = extra;
			exception2_write(opcode, dsta + 0, 0x1, src, 1);
			return 20 * CYCLE_UNIT / 2 + count_cycles;
		}
		m68k_incpci(6);
	} else {
		uaecptr srca;
		srca = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_000_prefetch(6));
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch(opcode, 6, -2);
			return 16 * CYCLE_UNIT / 2 + count_cycles;
		}
		if (srca & 1) {
			regs.irc = extra;
			regs.write_buffer = extra;
			m68k_incpci(8);
			exception3_read_access(opcode, srca, 1, 1);
			return 16 * CYCLE_UNIT / 2 + count_cycles;
		}
		uae_s16 src = sfc_nommu_get_word(srca);
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(4);
			regs.irc = extra;
			regs.write_buffer = extra;
			m68k_incpci(4);
			exception2_read(opcode, srca + 0, 0x1, 1);
			return 20 * CYCLE_UNIT / 2 + count_cycles;
		}
		if (extra & 0x8000) {
			m68k_areg(regs, (extra >> 12) & 7) = (uae_s32)(uae_s16)src;
		} else {
			m68k_dreg(regs, (extra >> 12) & 7) = (m68k_dreg(regs, (extra >> 12) & 7) & ~0xffff) | ((src) & 0xffff);
		}
		m68k_incpci(6);
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 24 * CYCLE_UNIT / 2 + count_cycles;
}
/* 24 (4/0) */
/* 6 4,4   */

#endif
/* MOVES.W #<data>.W,(xxx).W */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_0e78_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 103;
	CurrentInstrCycles = 20; 
	if (!regs.s) {
		Exception(8);
		return 0;
	}
	uae_s16 extra = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (extra & 0x800) {
		uae_u32 src = regs.regs[(extra >> 12) & 15];
		uaecptr dsta;
		dsta = (uae_s32)(uae_s16)get_word_000_prefetch(6);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch(opcode, 6, 0);
			return 12 * CYCLE_UNIT / 2 + count_cycles;
		}
		if (dsta & 1) {
			regs.irc = extra;
			m68k_incpci(8);
			exception3_write_access(opcode, dsta, 1, src, 1);
			return 12 * CYCLE_UNIT / 2 + count_cycles;
		}
		dfc_nommu_put_word(dsta, src);
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(8);
			regs.irc = extra;
			exception2_write(opcode, dsta + 0, 0x1, src, 1);
			return 16 * CYCLE_UNIT / 2 + count_cycles;
		}
		m68k_incpci(6);
	} else {
		uaecptr srca;
		srca = (uae_s32)(uae_s16)get_word_000_prefetch(6);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch(opcode, 6, 0);
			return 12 * CYCLE_UNIT / 2 + count_cycles;
		}
		if (srca & 1) {
			regs.irc = extra;
			regs.write_buffer = extra;
			m68k_incpci(8);
			exception3_read_access(opcode, srca, 1, 1);
			return 12 * CYCLE_UNIT / 2 + count_cycles;
		}
		uae_s16 src = sfc_nommu_get_word(srca);
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(6);
			regs.irc = extra;
			regs.write_buffer = extra;
			m68k_incpci(4);
			exception2_read(opcode, srca + 0, 0x1, 1);
			return 16 * CYCLE_UNIT / 2 + count_cycles;
		}
		if (extra & 0x8000) {
			m68k_areg(regs, (extra >> 12) & 7) = (uae_s32)(uae_s16)src;
		} else {
			m68k_dreg(regs, (extra >> 12) & 7) = (m68k_dreg(regs, (extra >> 12) & 7) & ~0xffff) | ((src) & 0xffff);
		}
		m68k_incpci(6);
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (4/0) */
/* 6 0,0   */

#endif
/* MOVES.W #<data>.W,(xxx).L */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_0e79_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 103;
	CurrentInstrCycles = 24; 
	if (!regs.s) {
		Exception(8);
		return 0;
	}
	uae_s16 extra = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (extra & 0x800) {
		uae_u32 src = regs.regs[(extra >> 12) & 15];
		uaecptr dsta;
		dsta = get_word_000_prefetch(6) << 16;
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch(opcode, 6, -2);
			return 12 * CYCLE_UNIT / 2 + count_cycles;
		}
		dsta |= get_word_000_prefetch(8);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch(opcode, 8, pcoffset);
			return 16 * CYCLE_UNIT / 2 + count_cycles;
		}
		if (dsta & 1) {
			regs.irc = extra;
			m68k_incpci(10);
			exception3_write_access(opcode, dsta, 1, src, 1);
			return 16 * CYCLE_UNIT / 2 + count_cycles;
		}
		dfc_nommu_put_word(dsta, src);
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(10);
			regs.irc = extra;
			exception2_write(opcode, dsta + 0, 0x1, src, 1);
			return 20 * CYCLE_UNIT / 2 + count_cycles;
		}
		m68k_incpci(8);
	} else {
		uaecptr srca;
		srca = get_word_000_prefetch(6) << 16;
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch(opcode, 6, -2);
			return 12 * CYCLE_UNIT / 2 + count_cycles;
		}
		srca |= get_word_000_prefetch(8);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch(opcode, 8, pcoffset);
			return 16 * CYCLE_UNIT / 2 + count_cycles;
		}
		if (srca & 1) {
			regs.irc = extra;
			regs.write_buffer = extra;
			m68k_incpci(10);
			exception3_read_access(opcode, srca, 1, 1);
			return 16 * CYCLE_UNIT / 2 + count_cycles;
		}
		uae_s16 src = sfc_nommu_get_word(srca);
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(8);
			regs.irc = extra;
			regs.write_buffer = extra;
			m68k_incpci(2);
			exception2_read(opcode, srca + 0, 0x1, 1);
			return 20 * CYCLE_UNIT / 2 + count_cycles;
		}
		if (extra & 0x8000) {
			m68k_areg(regs, (extra >> 12) & 7) = (uae_s32)(uae_s16)src;
		} else {
			m68k_dreg(regs, (extra >> 12) & 7) = (m68k_dreg(regs, (extra >> 12) & 7) & ~0xffff) | ((src) & 0xffff);
		}
		m68k_incpci(8);
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 24 * CYCLE_UNIT / 2 + count_cycles;
}
/* 24 (5/0) */
/* 8 0,0   */

#endif
/* MOVES.L #<data>.W,(An) */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_0e90_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 103;
	CurrentInstrCycles = 22; 
	if (!regs.s) {
		Exception(8);
		return 0;
	}
	uae_s16 extra = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (extra & 0x800) {
		uae_u32 src = regs.regs[(extra >> 12) & 15];
		uaecptr dsta;
		dsta = m68k_areg(regs, dstreg);
		if (dsta & 1) {
			regs.irc = extra;
			m68k_incpci(6);
			exception3_write_access(opcode, dsta, 2, src >> 16, 1);
			return 10 * CYCLE_UNIT / 2 + count_cycles;
		}
		src = regs.regs[(extra >> 12) & 15];
		dfc_nommu_put_word(dsta, src >> 16);
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(6);
			regs.irc = extra;
			exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
			return 14 * CYCLE_UNIT / 2 + count_cycles;
		}
		dfc_nommu_put_word(dsta + 2, src); 
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(6);
			regs.irc = extra;
			exception2_write(opcode, dsta + 2, 0x1, src, 1);
			return 18 * CYCLE_UNIT / 2 + count_cycles;
		}
		m68k_incpci(4);
	} else {
		uaecptr srca;
		srca = m68k_areg(regs, dstreg);
		if (srca & 1) {
			regs.irc = extra;
			regs.write_buffer = extra;
			m68k_incpci(6);
			exception3_read_access(opcode, srca, 2, 1);
			return 10 * CYCLE_UNIT / 2 + count_cycles;
		}
		uae_s32 src = sfc_nommu_get_word(srca) << 16;
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(4);
			regs.irc = extra;
			regs.write_buffer = extra;
			exception2_read(opcode, srca + 0, 0x1, 1);
			return 14 * CYCLE_UNIT / 2 + count_cycles;
		}
		src |= sfc_nommu_get_word(srca + 2);
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(4);
			regs.irc = extra;
			regs.write_buffer = extra;
			exception2_read(opcode, srca + 2, 0x1, 1);
			return 18 * CYCLE_UNIT / 2 + count_cycles;
		}
		if (extra & 0x8000) {
			m68k_areg(regs, (extra >> 12) & 7) = src;
		} else {
			m68k_dreg(regs, (extra >> 12) & 7) = (src);
		}
		m68k_incpci(4);
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 22 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 22 * CYCLE_UNIT / 2 + count_cycles;
}
/* 22 (4/0) */
/* 4 0,0   */

#endif
/* MOVES.L #<data>.W,(An)+ */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_0e98_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 103;
	CurrentInstrCycles = 24; 
	if (!regs.s) {
		Exception(8);
		return 0;
	}
	uae_s16 extra = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (extra & 0x800) {
		uae_u32 src = regs.regs[(extra >> 12) & 15];
		uaecptr dsta;
		dsta = m68k_areg(regs, dstreg);
		if (dsta & 1) {
			regs.irc = extra;
			if (dstreg + 8 == ((extra >> 12) & 15)) {
				src += 2;
			}
			m68k_areg(regs, dstreg) += 4;
			m68k_incpci(6);
			exception3_write_access(opcode, dsta, 2, src >> 16, 1);
			return 12 * CYCLE_UNIT / 2 + count_cycles;
		}
		m68k_areg(regs, dstreg) += 4;
		src = regs.regs[(extra >> 12) & 15];
		dfc_nommu_put_word(dsta, src >> 16);
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(6);
			regs.irc = extra;
			m68k_areg(regs, dstreg) += 4;
			exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
			return 16 * CYCLE_UNIT / 2 + count_cycles;
		}
		dfc_nommu_put_word(dsta + 2, src); 
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(6);
			regs.irc = extra;
			m68k_areg(regs, dstreg) += 4;
			exception2_write(opcode, dsta + 2, 0x1, src, 1);
			return 20 * CYCLE_UNIT / 2 + count_cycles;
		}
		m68k_incpci(4);
	} else {
		uaecptr srca;
		srca = m68k_areg(regs, dstreg);
		if (srca & 1) {
			regs.irc = extra;
			regs.write_buffer = extra;
			m68k_areg(regs, dstreg) += 4;
			m68k_incpci(6);
			exception3_read_access(opcode, srca, 2, 1);
			return 12 * CYCLE_UNIT / 2 + count_cycles;
		}
		uae_s32 src = sfc_nommu_get_word(srca) << 16;
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(4);
			regs.irc = extra;
			regs.write_buffer = extra;
			m68k_areg(regs, dstreg) += 4;
			exception2_read(opcode, srca + 0, 0x1, 1);
			return 16 * CYCLE_UNIT / 2 + count_cycles;
		}
		src |= sfc_nommu_get_word(srca + 2);
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(4);
			regs.irc = extra;
			regs.write_buffer = extra;
			m68k_areg(regs, dstreg) += 4;
			exception2_read(opcode, srca + 2, 0x1, 1);
			return 20 * CYCLE_UNIT / 2 + count_cycles;
		}
		m68k_areg(regs, dstreg) += 4;
		if (extra & 0x8000) {
			m68k_areg(regs, (extra >> 12) & 7) = src;
		} else {
			m68k_dreg(regs, (extra >> 12) & 7) = (src);
		}
		m68k_incpci(4);
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 24 * CYCLE_UNIT / 2 + count_cycles;
}
/* 24 (4/0) */
/* 4 0,0   */

#endif
/* MOVES.L #<data>.W,-(An) */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_0ea0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 103;
	CurrentInstrCycles = 24; 
	if (!regs.s) {
		Exception(8);
		return 0;
	}
	uae_s16 extra = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (extra & 0x800) {
		uae_u32 src = regs.regs[(extra >> 12) & 15];
		uaecptr dsta;
		dsta = m68k_areg(regs, dstreg) - 4;
		if (dsta & 1) {
			regs.irc = extra;
			if (dstreg + 8 == ((extra >> 12) & 15)) {
				src += -2;
			}
			m68k_incpci(6);
			m68k_areg(regs, dstreg) = dsta;
			exception3_write_access(opcode, dsta, 2, src >> 16, 1);
			return 12 * CYCLE_UNIT / 2 + count_cycles;
		}
		m68k_areg(regs, dstreg) = dsta;
		src = regs.regs[(extra >> 12) & 15];
		dfc_nommu_put_word(dsta, src >> 16);
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(6);
			regs.irc = extra;
			exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
			return 16 * CYCLE_UNIT / 2 + count_cycles;
		}
		dfc_nommu_put_word(dsta + 2, src); 
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(6);
			regs.irc = extra;
			exception2_write(opcode, dsta + 2, 0x1, src, 1);
			return 20 * CYCLE_UNIT / 2 + count_cycles;
		}
		m68k_incpci(4);
	} else {
		uaecptr srca;
		srca = m68k_areg(regs, dstreg) - 4;
		if (srca & 1) {
			regs.irc = extra;
			regs.write_buffer = extra;
			m68k_incpci(6);
			m68k_areg(regs, dstreg) = srca;
			exception3_read_access(opcode, srca, 2, 1);
			return 12 * CYCLE_UNIT / 2 + count_cycles;
		}
		uae_s32 src = sfc_nommu_get_word(srca) << 16;
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(4);
			regs.irc = extra;
			regs.write_buffer = extra;
			m68k_areg(regs, dstreg) = srca;
			m68k_incpci(2);
			exception2_read(opcode, srca + 0, 0x1, 1);
			return 16 * CYCLE_UNIT / 2 + count_cycles;
		}
		src |= sfc_nommu_get_word(srca + 2);
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(4);
			m68k_areg(regs, dstreg) = srca;
			regs.irc = extra;
			regs.write_buffer = extra;
			m68k_areg(regs, dstreg) = srca;
			m68k_incpci(2);
			exception2_read(opcode, srca + 2, 0x1, 1);
			return 20 * CYCLE_UNIT / 2 + count_cycles;
		}
		m68k_areg(regs, dstreg) = srca;
		if (extra & 0x8000) {
			m68k_areg(regs, (extra >> 12) & 7) = src;
		} else {
			m68k_dreg(regs, (extra >> 12) & 7) = (src);
		}
		m68k_incpci(4);
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 24 * CYCLE_UNIT / 2 + count_cycles;
}
/* 24 (4/0) */
/* 4 0,0   */

#endif
/* MOVES.L #<data>.W,(d16,An) */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_0ea8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 103;
	CurrentInstrCycles = 24; 
	if (!regs.s) {
		Exception(8);
		return 0;
	}
	uae_s16 extra = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (extra & 0x800) {
		uae_u32 src = regs.regs[(extra >> 12) & 15];
		uaecptr dsta;
		dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_000_prefetch(6);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch(opcode, 6, -2);
			return 12 * CYCLE_UNIT / 2 + count_cycles;
		}
		if (dsta & 1) {
			regs.irc = extra;
			m68k_incpci(8);
			exception3_write_access(opcode, dsta, 2, src >> 16, 1);
			return 12 * CYCLE_UNIT / 2 + count_cycles;
		}
		src = regs.regs[(extra >> 12) & 15];
		dfc_nommu_put_word(dsta, src >> 16);
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(8);
			regs.irc = extra;
			exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
			return 16 * CYCLE_UNIT / 2 + count_cycles;
		}
		dfc_nommu_put_word(dsta + 2, src); 
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(8);
			regs.irc = extra;
			exception2_write(opcode, dsta + 2, 0x1, src, 1);
			return 20 * CYCLE_UNIT / 2 + count_cycles;
		}
		m68k_incpci(6);
	} else {
		uaecptr srca;
		srca = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_000_prefetch(6);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch(opcode, 6, -2);
			return 12 * CYCLE_UNIT / 2 + count_cycles;
		}
		if (srca & 1) {
			regs.irc = extra;
			regs.write_buffer = extra;
			m68k_incpci(6);
			exception3_read_access(opcode, srca, 2, 1);
			return 12 * CYCLE_UNIT / 2 + count_cycles;
		}
		uae_s32 src = sfc_nommu_get_word(srca) << 16;
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(4);
			regs.irc = extra;
			regs.write_buffer = extra;
			m68k_incpci(4);
			exception2_read(opcode, srca + 0, 0x1, 1);
			return 16 * CYCLE_UNIT / 2 + count_cycles;
		}
		src |= sfc_nommu_get_word(srca + 2);
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(4);
			regs.irc = extra;
			regs.write_buffer = extra;
			m68k_incpci(4);
			exception2_read(opcode, srca + 2, 0x1, 1);
			return 20 * CYCLE_UNIT / 2 + count_cycles;
		}
		if (extra & 0x8000) {
			m68k_areg(regs, (extra >> 12) & 7) = src;
		} else {
			m68k_dreg(regs, (extra >> 12) & 7) = (src);
		}
		m68k_incpci(6);
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 24 * CYCLE_UNIT / 2 + count_cycles;
}
/* 24 (5/0) */
/* 6 0,0   */

#endif
/* MOVES.L #<data>.W,(d8,An,Xn) */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_0eb0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 103;
	CurrentInstrCycles = 28; 
	if (!regs.s) {
		Exception(8);
		return 0;
	}
	uae_s16 extra = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (extra & 0x800) {
		uae_u32 src = regs.regs[(extra >> 12) & 15];
		uaecptr dsta;
		dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_000_prefetch(6));
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch(opcode, 6, -2);
			return 16 * CYCLE_UNIT / 2 + count_cycles;
		}
		if (dsta & 1) {
			regs.irc = extra;
			m68k_incpci(8);
			exception3_write_access(opcode, dsta, 2, src >> 16, 1);
			return 16 * CYCLE_UNIT / 2 + count_cycles;
		}
		src = regs.regs[(extra >> 12) & 15];
		dfc_nommu_put_word(dsta, src >> 16);
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(8);
			regs.irc = extra;
			exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
			return 20 * CYCLE_UNIT / 2 + count_cycles;
		}
		dfc_nommu_put_word(dsta + 2, src); 
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(8);
			regs.irc = extra;
			exception2_write(opcode, dsta + 2, 0x1, src, 1);
			return 24 * CYCLE_UNIT / 2 + count_cycles;
		}
		m68k_incpci(6);
	} else {
		uaecptr srca;
		srca = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_000_prefetch(6));
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch(opcode, 6, -2);
			return 16 * CYCLE_UNIT / 2 + count_cycles;
		}
		if (srca & 1) {
			regs.irc = extra;
			regs.write_buffer = extra;
			m68k_incpci(8);
			exception3_read_access(opcode, srca, 2, 1);
			return 16 * CYCLE_UNIT / 2 + count_cycles;
		}
		uae_s32 src = sfc_nommu_get_word(srca) << 16;
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(4);
			regs.irc = extra;
			regs.write_buffer = extra;
			m68k_incpci(4);
			exception2_read(opcode, srca + 0, 0x1, 1);
			return 20 * CYCLE_UNIT / 2 + count_cycles;
		}
		src |= sfc_nommu_get_word(srca + 2);
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(4);
			regs.irc = extra;
			regs.write_buffer = extra;
			m68k_incpci(4);
			exception2_read(opcode, srca + 2, 0x1, 1);
			return 24 * CYCLE_UNIT / 2 + count_cycles;
		}
		if (extra & 0x8000) {
			m68k_areg(regs, (extra >> 12) & 7) = src;
		} else {
			m68k_dreg(regs, (extra >> 12) & 7) = (src);
		}
		m68k_incpci(6);
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 28 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 28 * CYCLE_UNIT / 2 + count_cycles;
}
/* 28 (5/0) */
/* 6 4,4   */

#endif
/* MOVES.L #<data>.W,(xxx).W */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_0eb8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 103;
	CurrentInstrCycles = 24; 
	if (!regs.s) {
		Exception(8);
		return 0;
	}
	uae_s16 extra = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (extra & 0x800) {
		uae_u32 src = regs.regs[(extra >> 12) & 15];
		uaecptr dsta;
		dsta = (uae_s32)(uae_s16)get_word_000_prefetch(6);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch(opcode, 6, 0);
			return 12 * CYCLE_UNIT / 2 + count_cycles;
		}
		if (dsta & 1) {
			regs.irc = extra;
			m68k_incpci(8);
			exception3_write_access(opcode, dsta, 2, src >> 16, 1);
			return 12 * CYCLE_UNIT / 2 + count_cycles;
		}
		src = regs.regs[(extra >> 12) & 15];
		dfc_nommu_put_word(dsta, src >> 16);
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(8);
			regs.irc = extra;
			exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
			return 16 * CYCLE_UNIT / 2 + count_cycles;
		}
		dfc_nommu_put_word(dsta + 2, src); 
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(8);
			regs.irc = extra;
			exception2_write(opcode, dsta + 2, 0x1, src, 1);
			return 20 * CYCLE_UNIT / 2 + count_cycles;
		}
		m68k_incpci(6);
	} else {
		uaecptr srca;
		srca = (uae_s32)(uae_s16)get_word_000_prefetch(6);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch(opcode, 6, 0);
			return 12 * CYCLE_UNIT / 2 + count_cycles;
		}
		if (srca & 1) {
			regs.irc = extra;
			regs.write_buffer = extra;
			m68k_incpci(8);
			exception3_read_access(opcode, srca, 2, 1);
			return 12 * CYCLE_UNIT / 2 + count_cycles;
		}
		uae_s32 src = sfc_nommu_get_word(srca) << 16;
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(6);
			regs.irc = extra;
			regs.write_buffer = extra;
			m68k_incpci(4);
			exception2_read(opcode, srca + 0, 0x1, 1);
			return 16 * CYCLE_UNIT / 2 + count_cycles;
		}
		src |= sfc_nommu_get_word(srca + 2);
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(6);
			regs.irc = extra;
			regs.write_buffer = extra;
			m68k_incpci(4);
			exception2_read(opcode, srca + 2, 0x1, 1);
			return 20 * CYCLE_UNIT / 2 + count_cycles;
		}
		if (extra & 0x8000) {
			m68k_areg(regs, (extra >> 12) & 7) = src;
		} else {
			m68k_dreg(regs, (extra >> 12) & 7) = (src);
		}
		m68k_incpci(6);
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 24 * CYCLE_UNIT / 2 + count_cycles;
}
/* 24 (5/0) */
/* 6 0,0   */

#endif
/* MOVES.L #<data>.W,(xxx).L */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_0eb9_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 103;
	CurrentInstrCycles = 28; 
	if (!regs.s) {
		Exception(8);
		return 0;
	}
	uae_s16 extra = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (extra & 0x800) {
		uae_u32 src = regs.regs[(extra >> 12) & 15];
		uaecptr dsta;
		dsta = get_word_000_prefetch(6) << 16;
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch(opcode, 6, -2);
			return 12 * CYCLE_UNIT / 2 + count_cycles;
		}
		dsta |= get_word_000_prefetch(8);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch(opcode, 8, pcoffset);
			return 16 * CYCLE_UNIT / 2 + count_cycles;
		}
		if (dsta & 1) {
			regs.irc = extra;
			m68k_incpci(10);
			exception3_write_access(opcode, dsta, 2, src >> 16, 1);
			return 16 * CYCLE_UNIT / 2 + count_cycles;
		}
		src = regs.regs[(extra >> 12) & 15];
		dfc_nommu_put_word(dsta, src >> 16);
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(10);
			regs.irc = extra;
			exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
			return 20 * CYCLE_UNIT / 2 + count_cycles;
		}
		dfc_nommu_put_word(dsta + 2, src); 
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(10);
			regs.irc = extra;
			exception2_write(opcode, dsta + 2, 0x1, src, 1);
			return 24 * CYCLE_UNIT / 2 + count_cycles;
		}
		m68k_incpci(8);
	} else {
		uaecptr srca;
		srca = get_word_000_prefetch(6) << 16;
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch(opcode, 6, -2);
			return 12 * CYCLE_UNIT / 2 + count_cycles;
		}
		srca |= get_word_000_prefetch(8);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch(opcode, 8, pcoffset);
			return 16 * CYCLE_UNIT / 2 + count_cycles;
		}
		if (srca & 1) {
			regs.irc = extra;
			regs.write_buffer = extra;
			m68k_incpci(10);
			exception3_read_access(opcode, srca, 2, 1);
			return 16 * CYCLE_UNIT / 2 + count_cycles;
		}
		uae_s32 src = sfc_nommu_get_word(srca) << 16;
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(8);
			regs.irc = extra;
			regs.write_buffer = extra;
			m68k_incpci(2);
			exception2_read(opcode, srca + 0, 0x1, 1);
			return 20 * CYCLE_UNIT / 2 + count_cycles;
		}
		src |= sfc_nommu_get_word(srca + 2);
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(8);
			regs.irc = extra;
			regs.write_buffer = extra;
			m68k_incpci(2);
			exception2_read(opcode, srca + 2, 0x1, 1);
			return 24 * CYCLE_UNIT / 2 + count_cycles;
		}
		if (extra & 0x8000) {
			m68k_areg(regs, (extra >> 12) & 7) = src;
		} else {
			m68k_dreg(regs, (extra >> 12) & 7) = (src);
		}
		m68k_incpci(8);
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 28 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 28 * CYCLE_UNIT / 2 + count_cycles;
}
/* 28 (6/0) */
/* 8 0,0   */

#endif
/* MOVE.B Dn,Dn */
uae_u32 REGPARAM2 op_1000_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 4;  
	uae_s8 src = m68k_dreg(regs, srcreg);
	struct flag_struct oldflags;
	oldflags.cznv = regflags.cznv;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
	m68k_incpci(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 4 * CYCLE_UNIT / 2 + count_cycles;
}
/* 4 (1/0) */
/* 2 0,0   */

/* MOVE.B (An),Dn */
uae_u32 REGPARAM2 op_1010_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 8;  
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
	m68k_incpci(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8 (2/0) */
/* 2 0,0   */

/* MOVE.B (An)+,Dn */
uae_u32 REGPARAM2 op_1018_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 8;  
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
	m68k_incpci(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8 (2/0) */
/* 2 0,0   */

/* MOVE.B -(An),Dn */
uae_u32 REGPARAM2 op_1020_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 10; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) = srca;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
	m68k_incpci(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 10 * CYCLE_UNIT / 2 + count_cycles;
}
/* 10 (2/0) */
/* 2 0,0   */

/* MOVE.B (d16,An),Dn */
uae_u32 REGPARAM2 op_1028_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (3/0) */
/* 4 0,0   */

/* MOVE.B (d8,An,Xn),Dn */
uae_u32 REGPARAM2 op_1030_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	BusCyclePenalty += 2;
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 14 * CYCLE_UNIT / 2 + count_cycles;
}
/* 14 (3/0) */
/* 4 4,0   */

/* MOVE.B (xxx).W,Dn */
uae_u32 REGPARAM2 op_1038_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (3/0) */
/* 4 0,0   */

/* MOVE.B (xxx).L,Dn */
uae_u32 REGPARAM2 op_1039_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	srca |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (4/0) */
/* 6 0,0   */

/* MOVE.B (d16,PC),Dn */
uae_u32 REGPARAM2 op_103a_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_getpci() + 2;
	srca += (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 2);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (3/0) */
/* 4 0,0   */

/* MOVE.B (d8,PC,Xn),Dn */
uae_u32 REGPARAM2 op_103b_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	uaecptr tmppc = m68k_getpci() + 2;
	BusCyclePenalty += 2;
	srca = get_disp_ea_000(tmppc, get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 2);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 14 * CYCLE_UNIT / 2 + count_cycles;
}
/* 14 (3/0) */
/* 4 4,0   */

/* MOVE.B #<data>.B,Dn */
uae_u32 REGPARAM2 op_103c_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 8;  
	uae_s8 src = (uae_u8)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	struct flag_struct oldflags;
	oldflags.cznv = regflags.cznv;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8 (2/0) */
/* 4 0,0   */

/* MOVE.B Dn,(An) */
uae_u32 REGPARAM2 op_1080_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 4;  
	int loop_mode = regs.loop_mode;
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	struct flag_struct oldflags;
	oldflags.cznv = regflags.cznv;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	put_byte_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	if(!loop_mode) {
		regs.ir = regs.irc;
		opcode = regs.ir;
		get_word_000_prefetch(2);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 2, pcoffset);
			return 4 * CYCLE_UNIT / 2 + count_cycles;
		}
	} else {
		loop_mode = 0;
		loop_mode |= 2;
		loop_mode |= 4 << 16;
	}
	regs.loop_mode = loop_mode;
	return 4 * CYCLE_UNIT / 2 + count_cycles;
}
/* 4+ (0/1) */
/* 2 0,0   */

/* MOVE.B (An),(An) */
uae_u32 REGPARAM2 op_1090_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 8;  
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	put_byte_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	if(!loop_mode) {
		regs.ir = regs.irc;
		opcode = regs.ir;
		get_word_000_prefetch(2);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 2, pcoffset);
			return 8 * CYCLE_UNIT / 2 + count_cycles;
		}
	} else {
		loop_mode = 0;
		loop_mode |= 2;
		loop_mode |= 2 << 16;
	}
	regs.loop_mode = loop_mode;
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8+ (1/1) */
/* 2 0,0   */

/* MOVE.B (An)+,(An) */
uae_u32 REGPARAM2 op_1098_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 8;  
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	put_byte_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	if(!loop_mode) {
		regs.ir = regs.irc;
		opcode = regs.ir;
		get_word_000_prefetch(2);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 2, pcoffset);
			return 8 * CYCLE_UNIT / 2 + count_cycles;
		}
	} else {
		loop_mode = 0;
		loop_mode |= 2;
		loop_mode |= 2 << 16;
	}
	regs.loop_mode = loop_mode;
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8+ (1/1) */
/* 2 0,0   */

/* MOVE.B -(An),(An) */
uae_u32 REGPARAM2 op_10a0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 10; 
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) = srca;
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	put_byte_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	if(!loop_mode) {
		regs.ir = regs.irc;
		opcode = regs.ir;
		get_word_000_prefetch(2);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 2, pcoffset);
			return 10 * CYCLE_UNIT / 2 + count_cycles;
		}
	} else {
		loop_mode = 0;
		loop_mode |= 2;
		loop_mode |= 2 << 16;
	}
	regs.loop_mode = loop_mode;
	return 10 * CYCLE_UNIT / 2 + count_cycles;
}
/* 10+ (1/1) */
/* 2 0,0   */

/* MOVE.B (d16,An),(An) */
uae_u32 REGPARAM2 op_10a8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	put_byte_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 4 0,0   */

/* MOVE.B (d8,An,Xn),(An) */
uae_u32 REGPARAM2 op_10b0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	BusCyclePenalty += 2;
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	put_byte_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (3/1) */
/* 4 4,0   */

/* MOVE.B (xxx).W,(An) */
uae_u32 REGPARAM2 op_10b8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	put_byte_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 4 0,0   */

/* MOVE.B (xxx).L,(An) */
uae_u32 REGPARAM2 op_10b9_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	srca = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	srca |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	put_byte_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (4/1) */
/* 6 0,0   */

/* MOVE.B (d16,PC),(An) */
uae_u32 REGPARAM2 op_10ba_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = m68k_getpci() + 2;
	srca += (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 2);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	put_byte_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 4 0,0   */

/* MOVE.B (d8,PC,Xn),(An) */
uae_u32 REGPARAM2 op_10bb_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	uaecptr tmppc = m68k_getpci() + 2;
	BusCyclePenalty += 2;
	srca = get_disp_ea_000(tmppc, get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 2);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	put_byte_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (3/1) */
/* 4 4,0   */

/* MOVE.B #<data>.B,(An) */
uae_u32 REGPARAM2 op_10bc_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 12; 
	uae_s8 src = (uae_u8)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	struct flag_struct oldflags;
	oldflags.cznv = regflags.cznv;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	put_byte_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (2/1) */
/* 4 0,0   */

/* MOVE.B Dn,(An)+ */
uae_u32 REGPARAM2 op_10c0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 4;  
	int loop_mode = regs.loop_mode;
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
	struct flag_struct oldflags;
	oldflags.cznv = regflags.cznv;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	put_byte_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, dstreg) -= areg_byteinc[dstreg];
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	if(!loop_mode) {
		regs.ir = regs.irc;
		opcode = regs.ir;
		get_word_000_prefetch(2);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 2, pcoffset);
			return 4 * CYCLE_UNIT / 2 + count_cycles;
		}
	} else {
		loop_mode = 0;
		loop_mode |= 2;
		loop_mode |= 4 << 16;
	}
	regs.loop_mode = loop_mode;
	return 4 * CYCLE_UNIT / 2 + count_cycles;
}
/* 4+ (0/1) */
/* 2 0,0   */

/* MOVE.B (An),(An)+ */
uae_u32 REGPARAM2 op_10d0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 8;  
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	put_byte_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, dstreg) -= areg_byteinc[dstreg];
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	if(!loop_mode) {
		regs.ir = regs.irc;
		opcode = regs.ir;
		get_word_000_prefetch(2);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 2, pcoffset);
			return 8 * CYCLE_UNIT / 2 + count_cycles;
		}
	} else {
		loop_mode = 0;
		loop_mode |= 2;
		loop_mode |= 2 << 16;
	}
	regs.loop_mode = loop_mode;
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8+ (1/1) */
/* 2 0,0   */

/* MOVE.B (An)+,(An)+ */
uae_u32 REGPARAM2 op_10d8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 8;  
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	put_byte_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, dstreg) -= areg_byteinc[dstreg];
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	if(!loop_mode) {
		regs.ir = regs.irc;
		opcode = regs.ir;
		get_word_000_prefetch(2);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 2, pcoffset);
			return 8 * CYCLE_UNIT / 2 + count_cycles;
		}
	} else {
		loop_mode = 0;
		loop_mode |= 2;
		loop_mode |= 2 << 16;
	}
	regs.loop_mode = loop_mode;
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8+ (1/1) */
/* 2 0,0   */

/* MOVE.B -(An),(An)+ */
uae_u32 REGPARAM2 op_10e0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 10; 
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) = srca;
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	put_byte_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, dstreg) -= areg_byteinc[dstreg];
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	if(!loop_mode) {
		regs.ir = regs.irc;
		opcode = regs.ir;
		get_word_000_prefetch(2);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 2, pcoffset);
			return 10 * CYCLE_UNIT / 2 + count_cycles;
		}
	} else {
		loop_mode = 0;
		loop_mode |= 2;
		loop_mode |= 2 << 16;
	}
	regs.loop_mode = loop_mode;
	return 10 * CYCLE_UNIT / 2 + count_cycles;
}
/* 10+ (1/1) */
/* 2 0,0   */

/* MOVE.B (d16,An),(An)+ */
uae_u32 REGPARAM2 op_10e8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	put_byte_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, dstreg) -= areg_byteinc[dstreg];
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 4 0,0   */

/* MOVE.B (d8,An,Xn),(An)+ */
uae_u32 REGPARAM2 op_10f0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	BusCyclePenalty += 2;
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	put_byte_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, dstreg) -= areg_byteinc[dstreg];
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (3/1) */
/* 4 4,0   */

/* MOVE.B (xxx).W,(An)+ */
uae_u32 REGPARAM2 op_10f8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	put_byte_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, dstreg) -= areg_byteinc[dstreg];
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 4 0,0   */

/* MOVE.B (xxx).L,(An)+ */
uae_u32 REGPARAM2 op_10f9_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	srca = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	srca |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	put_byte_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		m68k_areg(regs, dstreg) -= areg_byteinc[dstreg];
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (4/1) */
/* 6 0,0   */

/* MOVE.B (d16,PC),(An)+ */
uae_u32 REGPARAM2 op_10fa_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = m68k_getpci() + 2;
	srca += (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 2);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	put_byte_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, dstreg) -= areg_byteinc[dstreg];
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 4 0,0   */

/* MOVE.B (d8,PC,Xn),(An)+ */
uae_u32 REGPARAM2 op_10fb_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	uaecptr tmppc = m68k_getpci() + 2;
	BusCyclePenalty += 2;
	srca = get_disp_ea_000(tmppc, get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 2);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	put_byte_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, dstreg) -= areg_byteinc[dstreg];
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (3/1) */
/* 4 4,0   */

/* MOVE.B #<data>.B,(An)+ */
uae_u32 REGPARAM2 op_10fc_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 12; 
	uae_s8 src = (uae_u8)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
	struct flag_struct oldflags;
	oldflags.cznv = regflags.cznv;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	put_byte_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, dstreg) -= areg_byteinc[dstreg];
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (2/1) */
/* 4 0,0   */

/* MOVE.B Dn,-(An) */
uae_u32 REGPARAM2 op_1100_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 8;  
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
	m68k_areg(regs, dstreg) = dsta;
	regs.ir = regs.irc;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	struct flag_struct oldflags;
	oldflags.cznv = regflags.cznv;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	put_byte_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8 (1/1) */
/* 2 0,0   */

/* MOVE.B (An),-(An) */
uae_u32 REGPARAM2 op_1110_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 8;  
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
	m68k_areg(regs, dstreg) = dsta;
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_000_prefetch(4);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			int pcoffset = 0;
			m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
			ccr_68000_word_move_ae_normal((uae_s16)src);
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return 4 * CYCLE_UNIT / 2 + count_cycles;
		}
		opcode = regs.ir;
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	if(loop_mode & 0xfffe) {
		count_cycles += (loop_mode & 0xfffe) * CYCLE_UNIT / 2;
		loop_mode = 1;
	}
	put_byte_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	regs.loop_mode = loop_mode;
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8+ (1/1) */
/* 2 0,0   */

/* MOVE.B (An)+,-(An) */
uae_u32 REGPARAM2 op_1118_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 8;  
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
	m68k_areg(regs, dstreg) = dsta;
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_000_prefetch(4);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			int pcoffset = 0;
			m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
			ccr_68000_word_move_ae_normal((uae_s16)src);
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return 4 * CYCLE_UNIT / 2 + count_cycles;
		}
		opcode = regs.ir;
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	if(loop_mode & 0xfffe) {
		count_cycles += (loop_mode & 0xfffe) * CYCLE_UNIT / 2;
		loop_mode = 1;
	}
	put_byte_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	regs.loop_mode = loop_mode;
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8+ (1/1) */
/* 2 0,0   */

/* MOVE.B -(An),-(An) */
uae_u32 REGPARAM2 op_1120_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 10; 
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) = srca;
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
	m68k_areg(regs, dstreg) = dsta;
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_000_prefetch(4);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			int pcoffset = 0;
			m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
			ccr_68000_word_move_ae_normal((uae_s16)src);
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return 6 * CYCLE_UNIT / 2 + count_cycles;
		}
		opcode = regs.ir;
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	if(loop_mode & 0xfffe) {
		count_cycles += (loop_mode & 0xfffe) * CYCLE_UNIT / 2;
		loop_mode = 1;
	}
	put_byte_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	regs.loop_mode = loop_mode;
	return 10 * CYCLE_UNIT / 2 + count_cycles;
}
/* 10+ (1/1) */
/* 2 0,0   */

/* MOVE.B (d16,An),-(An) */
uae_u32 REGPARAM2 op_1128_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
	m68k_areg(regs, dstreg) = dsta;
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	put_byte_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 4 0,0   */

/* MOVE.B (d8,An,Xn),-(An) */
uae_u32 REGPARAM2 op_1130_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	BusCyclePenalty += 2;
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
	m68k_areg(regs, dstreg) = dsta;
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	put_byte_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (3/1) */
/* 4 4,0   */

/* MOVE.B (xxx).W,-(An) */
uae_u32 REGPARAM2 op_1138_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
	m68k_areg(regs, dstreg) = dsta;
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	put_byte_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 4 0,0   */

/* MOVE.B (xxx).L,-(An) */
uae_u32 REGPARAM2 op_1139_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	srca = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	srca |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
	m68k_areg(regs, dstreg) = dsta;
	regs.ir = regs.irc;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	put_byte_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (4/1) */
/* 6 0,0   */

/* MOVE.B (d16,PC),-(An) */
uae_u32 REGPARAM2 op_113a_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = m68k_getpci() + 2;
	srca += (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 2);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
	m68k_areg(regs, dstreg) = dsta;
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	put_byte_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 4 0,0   */

/* MOVE.B (d8,PC,Xn),-(An) */
uae_u32 REGPARAM2 op_113b_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	uaecptr tmppc = m68k_getpci() + 2;
	BusCyclePenalty += 2;
	srca = get_disp_ea_000(tmppc, get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 2);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
	m68k_areg(regs, dstreg) = dsta;
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	put_byte_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (3/1) */
/* 4 4,0   */

/* MOVE.B #<data>.B,-(An) */
uae_u32 REGPARAM2 op_113c_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 12; 
	uae_s8 src = (uae_u8)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
	m68k_areg(regs, dstreg) = dsta;
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	struct flag_struct oldflags;
	oldflags.cznv = regflags.cznv;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	put_byte_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (2/1) */
/* 4 0,0   */

/* MOVE.B Dn,(d16,An) */
uae_u32 REGPARAM2 op_1140_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 12; 
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	struct flag_struct oldflags;
	oldflags.cznv = regflags.cznv;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	put_byte_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (2/1) */
/* 4 0,0   */

/* MOVE.B (An),(d16,An) */
uae_u32 REGPARAM2 op_1150_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 4, 0);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	put_byte_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 4 0,0   */

/* MOVE.B (An)+,(d16,An) */
uae_u32 REGPARAM2 op_1158_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 4, 0);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	put_byte_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 4 0,0   */

/* MOVE.B -(An),(d16,An) */
uae_u32 REGPARAM2 op_1160_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) = srca;
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 4, 0);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	put_byte_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (3/1) */
/* 4 0,0   */

/* MOVE.B (d16,An),(d16,An) */
uae_u32 REGPARAM2 op_1168_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 6, 0);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	put_byte_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (4/1) */
/* 6 0,0   */

/* MOVE.B (d8,An,Xn),(d16,An) */
uae_u32 REGPARAM2 op_1170_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 22; 
	uaecptr srca;
	BusCyclePenalty += 2;
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 6, 0);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	put_byte_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 22 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 22 * CYCLE_UNIT / 2 + count_cycles;
}
/* 22 (4/1) */
/* 6 6,0   */

/* MOVE.B (xxx).W,(d16,An) */
uae_u32 REGPARAM2 op_1178_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 6, 0);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	put_byte_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (4/1) */
/* 6 0,0   */

/* MOVE.B (xxx).L,(d16,An) */
uae_u32 REGPARAM2 op_1179_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 24; 
	uaecptr srca;
	srca = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	srca |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 8, 0);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	put_byte_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(8);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 24 * CYCLE_UNIT / 2 + count_cycles;
}
/* 24 (5/1) */
/* 8 0,0   */

/* MOVE.B (d16,PC),(d16,An) */
uae_u32 REGPARAM2 op_117a_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	srca = m68k_getpci() + 2;
	srca += (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 2);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 6, 0);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	put_byte_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (4/1) */
/* 6 0,0   */

/* MOVE.B (d8,PC,Xn),(d16,An) */
uae_u32 REGPARAM2 op_117b_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 22; 
	uaecptr srca;
	uaecptr tmppc = m68k_getpci() + 2;
	BusCyclePenalty += 2;
	srca = get_disp_ea_000(tmppc, get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 2);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 6, 0);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	put_byte_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 22 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 22 * CYCLE_UNIT / 2 + count_cycles;
}
/* 22 (4/1) */
/* 6 6,0   */

/* MOVE.B #<data>.B,(d16,An) */
uae_u32 REGPARAM2 op_117c_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 16; 
	uae_s8 src = (uae_u8)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, 0);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	struct flag_struct oldflags;
	oldflags.cznv = regflags.cznv;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	put_byte_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 6 0,0   */

/* MOVE.B Dn,(d8,An,Xn) */
uae_u32 REGPARAM2 op_1180_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 14; 
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	BusCyclePenalty += 2;
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	struct flag_struct oldflags;
	oldflags.cznv = regflags.cznv;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	put_byte_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 14 * CYCLE_UNIT / 2 + count_cycles;
}
/* 14 (2/1) */
/* 4 4,0   */

/* MOVE.B (An),(d8,An,Xn) */
uae_u32 REGPARAM2 op_1190_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	BusCyclePenalty += 2;
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 4, 0);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	put_byte_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (3/1) */
/* 4 4,0   */

/* MOVE.B (An)+,(d8,An,Xn) */
uae_u32 REGPARAM2 op_1198_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
	uaecptr dsta;
	BusCyclePenalty += 2;
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 4, 0);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	put_byte_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (3/1) */
/* 4 4,0   */

/* MOVE.B -(An),(d8,An,Xn) */
uae_u32 REGPARAM2 op_11a0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) = srca;
	uaecptr dsta;
	BusCyclePenalty += 2;
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 4, 0);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	put_byte_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (3/1) */
/* 4 4,0   */

/* MOVE.B (d16,An),(d8,An,Xn) */
uae_u32 REGPARAM2 op_11a8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 22; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	BusCyclePenalty += 2;
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_000_prefetch(6));
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 6, 0);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	put_byte_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 22 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 22 * CYCLE_UNIT / 2 + count_cycles;
}
/* 22 (4/1) */
/* 6 4,0   */

/* MOVE.B (d8,An,Xn),(d8,An,Xn) */
uae_u32 REGPARAM2 op_11b0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 24; 
	uaecptr srca;
	BusCyclePenalty += 2;
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	BusCyclePenalty += 2;
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_000_prefetch(6));
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 6, 0);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	put_byte_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 24 * CYCLE_UNIT / 2 + count_cycles;
}
/* 24 (4/1) */
/* 6 6,4   */

/* MOVE.B (xxx).W,(d8,An,Xn) */
uae_u32 REGPARAM2 op_11b8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 22; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	BusCyclePenalty += 2;
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_000_prefetch(6));
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 6, 0);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	put_byte_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 22 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 22 * CYCLE_UNIT / 2 + count_cycles;
}
/* 22 (4/1) */
/* 6 4,0   */

/* MOVE.B (xxx).L,(d8,An,Xn) */
uae_u32 REGPARAM2 op_11b9_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 26; 
	uaecptr srca;
	srca = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	srca |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	BusCyclePenalty += 2;
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_000_prefetch(8));
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 8, 0);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	put_byte_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return 22 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(8);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 26 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 26 * CYCLE_UNIT / 2 + count_cycles;
}
/* 26 (5/1) */
/* 8 4,0   */

/* MOVE.B (d16,PC),(d8,An,Xn) */
uae_u32 REGPARAM2 op_11ba_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 22; 
	uaecptr srca;
	srca = m68k_getpci() + 2;
	srca += (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 2);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	BusCyclePenalty += 2;
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_000_prefetch(6));
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 6, 0);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	put_byte_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 22 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 22 * CYCLE_UNIT / 2 + count_cycles;
}
/* 22 (4/1) */
/* 6 4,0   */

/* MOVE.B (d8,PC,Xn),(d8,An,Xn) */
uae_u32 REGPARAM2 op_11bb_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 24; 
	uaecptr srca;
	uaecptr tmppc = m68k_getpci() + 2;
	BusCyclePenalty += 2;
	srca = get_disp_ea_000(tmppc, get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 2);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	BusCyclePenalty += 2;
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_000_prefetch(6));
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 6, 0);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	put_byte_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 24 * CYCLE_UNIT / 2 + count_cycles;
}
/* 24 (4/1) */
/* 6 6,4   */

/* MOVE.B #<data>.B,(d8,An,Xn) */
uae_u32 REGPARAM2 op_11bc_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 18; 
	uae_s8 src = (uae_u8)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	BusCyclePenalty += 2;
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_000_prefetch(6));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, 0);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	struct flag_struct oldflags;
	oldflags.cznv = regflags.cznv;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	put_byte_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (3/1) */
/* 6 4,0   */

/* MOVE.B Dn,(xxx).W */
uae_u32 REGPARAM2 op_11c0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 30;
	CurrentInstrCycles = 12; 
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	struct flag_struct oldflags;
	oldflags.cznv = regflags.cznv;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	put_byte_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (2/1) */
/* 4 0,0   */

/* MOVE.B (An),(xxx).W */
uae_u32 REGPARAM2 op_11d0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 30;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 4, 0);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	put_byte_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 4 0,0   */

/* MOVE.B (An)+,(xxx).W */
uae_u32 REGPARAM2 op_11d8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 30;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 4, 0);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	put_byte_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 4 0,0   */

/* MOVE.B -(An),(xxx).W */
uae_u32 REGPARAM2 op_11e0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 30;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) = srca;
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 4, 0);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	put_byte_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (3/1) */
/* 4 0,0   */

/* MOVE.B (d16,An),(xxx).W */
uae_u32 REGPARAM2 op_11e8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 30;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 6, 0);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	put_byte_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (4/1) */
/* 6 0,0   */

/* MOVE.B (d8,An,Xn),(xxx).W */
uae_u32 REGPARAM2 op_11f0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 30;
	CurrentInstrCycles = 22; 
	uaecptr srca;
	BusCyclePenalty += 2;
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 6, 0);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	put_byte_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 22 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 22 * CYCLE_UNIT / 2 + count_cycles;
}
/* 22 (4/1) */
/* 6 6,0   */

/* MOVE.B (xxx).W,(xxx).W */
uae_u32 REGPARAM2 op_11f8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 30;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 6, 0);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	put_byte_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (4/1) */
/* 6 0,0   */

/* MOVE.B (xxx).L,(xxx).W */
uae_u32 REGPARAM2 op_11f9_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 30;
	CurrentInstrCycles = 24; 
	uaecptr srca;
	srca = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	srca |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 8, 0);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	put_byte_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(8);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 24 * CYCLE_UNIT / 2 + count_cycles;
}
/* 24 (5/1) */
/* 8 0,0   */

/* MOVE.B (d16,PC),(xxx).W */
uae_u32 REGPARAM2 op_11fa_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 30;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	srca = m68k_getpci() + 2;
	srca += (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 2);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 6, 0);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	put_byte_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (4/1) */
/* 6 0,0   */

/* MOVE.B (d8,PC,Xn),(xxx).W */
uae_u32 REGPARAM2 op_11fb_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 30;
	CurrentInstrCycles = 22; 
	uaecptr srca;
	uaecptr tmppc = m68k_getpci() + 2;
	BusCyclePenalty += 2;
	srca = get_disp_ea_000(tmppc, get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 2);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 6, 0);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	put_byte_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 22 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 22 * CYCLE_UNIT / 2 + count_cycles;
}
/* 22 (4/1) */
/* 6 6,0   */

/* MOVE.B #<data>.B,(xxx).W */
uae_u32 REGPARAM2 op_11fc_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 30;
	CurrentInstrCycles = 16; 
	uae_s8 src = (uae_u8)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 6, 0);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	struct flag_struct oldflags;
	oldflags.cznv = regflags.cznv;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	put_byte_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 6 0,0   */

/* MOVE.B Dn,(xxx).L */
uae_u32 REGPARAM2 op_13c0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 30;
	CurrentInstrCycles = 16; 
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	dsta |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	struct flag_struct oldflags;
	oldflags.cznv = regflags.cznv;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	put_byte_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 6 0,0   */

/* MOVE.B (An),(xxx).L */
uae_u32 REGPARAM2 op_13d0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 30;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = get_word_000_prefetch(4) << 16;
	dsta |= regs.irc;
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 4, 0);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	put_byte_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		regs.irc = dsta >> 16;
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	get_word_000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, 0);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (4/1) */
/* 6 0,0   */

/* MOVE.B (An)+,(xxx).L */
uae_u32 REGPARAM2 op_13d8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 30;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
	uaecptr dsta;
	dsta = get_word_000_prefetch(4) << 16;
	dsta |= regs.irc;
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 4, 0);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	put_byte_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		regs.irc = dsta >> 16;
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	get_word_000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, 0);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (4/1) */
/* 6 0,0   */

/* MOVE.B -(An),(xxx).L */
uae_u32 REGPARAM2 op_13e0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 30;
	CurrentInstrCycles = 22; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) = srca;
	uaecptr dsta;
	dsta = get_word_000_prefetch(4) << 16;
	dsta |= regs.irc;
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 4, 0);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	put_byte_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		regs.irc = dsta >> 16;
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	get_word_000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, 0);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 22 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 22 * CYCLE_UNIT / 2 + count_cycles;
}
/* 22 (4/1) */
/* 6 0,0   */

/* MOVE.B (d16,An),(xxx).L */
uae_u32 REGPARAM2 op_13e8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 30;
	CurrentInstrCycles = 24; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = get_word_000_prefetch(6) << 16;
	dsta |= regs.irc;
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 6, 0);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	put_byte_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		regs.irc = dsta >> 16;
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(8);
	get_word_000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, 0);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 24 * CYCLE_UNIT / 2 + count_cycles;
}
/* 24 (5/1) */
/* 8 0,0   */

/* MOVE.B (d8,An,Xn),(xxx).L */
uae_u32 REGPARAM2 op_13f0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 30;
	CurrentInstrCycles = 26; 
	uaecptr srca;
	BusCyclePenalty += 2;
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = get_word_000_prefetch(6) << 16;
	dsta |= regs.irc;
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 6, 0);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	put_byte_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		regs.irc = dsta >> 16;
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(8);
	get_word_000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, 0);
		return 22 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 26 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 26 * CYCLE_UNIT / 2 + count_cycles;
}
/* 26 (5/1) */
/* 8 8,0   */

/* MOVE.B (xxx).W,(xxx).L */
uae_u32 REGPARAM2 op_13f8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 30;
	CurrentInstrCycles = 24; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = get_word_000_prefetch(6) << 16;
	dsta |= regs.irc;
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 6, 0);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	put_byte_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		regs.irc = dsta >> 16;
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(8);
	get_word_000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, 0);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 24 * CYCLE_UNIT / 2 + count_cycles;
}
/* 24 (5/1) */
/* 8 0,0   */

/* MOVE.B (xxx).L,(xxx).L */
uae_u32 REGPARAM2 op_13f9_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 30;
	CurrentInstrCycles = 28; 
	uaecptr srca;
	srca = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	srca |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = get_word_000_prefetch(8) << 16;
	dsta |= regs.irc;
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 8, 0);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	put_byte_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		regs.irc = dsta >> 16;
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(10);
	get_word_000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, 0);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 28 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 28 * CYCLE_UNIT / 2 + count_cycles;
}
/* 28 (6/1) */
/* 10 0,0   */

/* MOVE.B (d16,PC),(xxx).L */
uae_u32 REGPARAM2 op_13fa_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 30;
	CurrentInstrCycles = 24; 
	uaecptr srca;
	srca = m68k_getpci() + 2;
	srca += (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 2);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = get_word_000_prefetch(6) << 16;
	dsta |= regs.irc;
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 6, 0);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	put_byte_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		regs.irc = dsta >> 16;
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(8);
	get_word_000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, 0);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 24 * CYCLE_UNIT / 2 + count_cycles;
}
/* 24 (5/1) */
/* 8 0,0   */

/* MOVE.B (d8,PC,Xn),(xxx).L */
uae_u32 REGPARAM2 op_13fb_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 30;
	CurrentInstrCycles = 26; 
	uaecptr srca;
	uaecptr tmppc = m68k_getpci() + 2;
	BusCyclePenalty += 2;
	srca = get_disp_ea_000(tmppc, get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 2);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = get_word_000_prefetch(6) << 16;
	dsta |= regs.irc;
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 6, 0);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	put_byte_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		regs.irc = dsta >> 16;
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(8);
	get_word_000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, 0);
		return 22 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 26 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 26 * CYCLE_UNIT / 2 + count_cycles;
}
/* 26 (5/1) */
/* 8 8,0   */

/* MOVE.B #<data>.B,(xxx).L */
uae_u32 REGPARAM2 op_13fc_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 30;
	CurrentInstrCycles = 20; 
	uae_s8 src = (uae_u8)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = get_word_000_prefetch(6) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	dsta |= get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 8, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	struct flag_struct oldflags;
	oldflags.cznv = regflags.cznv;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	put_byte_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(8);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (4/1) */
/* 8 0,0   */

/* MOVE.L Dn,Dn */
uae_u32 REGPARAM2 op_2000_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 4;  
	uae_s32 src = m68k_dreg(regs, srcreg);
	struct flag_struct oldflags;
	oldflags.cznv = regflags.cznv;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	m68k_dreg(regs, dstreg) = (src);
	m68k_incpci(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 4 * CYCLE_UNIT / 2 + count_cycles;
}
/* 4 (1/0) */
/* 2 0,0   */

/* MOVE.L An,Dn */
uae_u32 REGPARAM2 op_2008_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 4;  
	uae_s32 src = m68k_areg(regs, srcreg);
	struct flag_struct oldflags;
	oldflags.cznv = regflags.cznv;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	m68k_dreg(regs, dstreg) = (src);
	m68k_incpci(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 4 * CYCLE_UNIT / 2 + count_cycles;
}
/* 4 (1/0) */
/* 2 0,0   */

/* MOVE.L (An),Dn */
uae_u32 REGPARAM2 op_2010_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	m68k_dreg(regs, dstreg) = (src);
	m68k_incpci(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (3/0) */
/* 2 0,0   */

/* MOVE.L (An)+,Dn */
uae_u32 REGPARAM2 op_2018_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) += 4;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	m68k_dreg(regs, dstreg) = (src);
	m68k_incpci(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (3/0) */
/* 2 0,0   */

/* MOVE.L -(An),Dn */
uae_u32 REGPARAM2 op_2020_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - 4;
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return 2 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) = srca;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	m68k_dreg(regs, dstreg) = (src);
	m68k_incpci(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 14 * CYCLE_UNIT / 2 + count_cycles;
}
/* 14 (3/0) */
/* 2 0,0   */

/* MOVE.L (d16,An),Dn */
uae_u32 REGPARAM2 op_2028_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	m68k_dreg(regs, dstreg) = (src);
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (4/0) */
/* 4 0,0   */

/* MOVE.L (d8,An,Xn),Dn */
uae_u32 REGPARAM2 op_2030_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	BusCyclePenalty += 2;
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	m68k_dreg(regs, dstreg) = (src);
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (4/0) */
/* 4 4,0   */

/* MOVE.L (xxx).W,Dn */
uae_u32 REGPARAM2 op_2038_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, srca, 2, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	m68k_dreg(regs, dstreg) = (src);
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (4/0) */
/* 4 0,0   */

/* MOVE.L (xxx).L,Dn */
uae_u32 REGPARAM2 op_2039_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	srca = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	srca |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, srca, 2, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	m68k_dreg(regs, dstreg) = (src);
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (5/0) */
/* 6 0,0   */

/* MOVE.L (d16,PC),Dn */
uae_u32 REGPARAM2 op_203a_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = m68k_getpci() + 2;
	srca += (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 2);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	m68k_dreg(regs, dstreg) = (src);
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (4/0) */
/* 4 0,0   */

/* MOVE.L (d8,PC,Xn),Dn */
uae_u32 REGPARAM2 op_203b_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	uaecptr tmppc = m68k_getpci() + 2;
	BusCyclePenalty += 2;
	srca = get_disp_ea_000(tmppc, get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 2);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	m68k_dreg(regs, dstreg) = (src);
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (4/0) */
/* 4 4,0   */

/* MOVE.L #<data>.L,Dn */
uae_u32 REGPARAM2 op_203c_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 12; 
	uae_s32 src;
	src = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	struct flag_struct oldflags;
	oldflags.cznv = regflags.cznv;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	m68k_dreg(regs, dstreg) = (src);
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (3/0) */
/* 6 0,0   */

/* MOVEA.L Dn,An */
uae_u32 REGPARAM2 op_2040_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 31;
	CurrentInstrCycles = 4;  
	uae_s32 src = m68k_dreg(regs, srcreg);
	m68k_areg(regs, dstreg) = (src);
	m68k_incpci(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 4 * CYCLE_UNIT / 2 + count_cycles;
}
/* 4 (1/0) */
/* 2 0,0   */

/* MOVEA.L An,An */
uae_u32 REGPARAM2 op_2048_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 31;
	CurrentInstrCycles = 4;  
	uae_s32 src = m68k_areg(regs, srcreg);
	m68k_areg(regs, dstreg) = (src);
	m68k_incpci(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 4 * CYCLE_UNIT / 2 + count_cycles;
}
/* 4 (1/0) */
/* 2 0,0   */

/* MOVEA.L (An),An */
uae_u32 REGPARAM2 op_2050_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 31;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) = (src);
	m68k_incpci(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (3/0) */
/* 2 0,0   */

/* MOVEA.L (An)+,An */
uae_u32 REGPARAM2 op_2058_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 31;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) += 4;
	m68k_areg(regs, dstreg) = (src);
	m68k_incpci(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (3/0) */
/* 2 0,0   */

/* MOVEA.L -(An),An */
uae_u32 REGPARAM2 op_2060_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 31;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - 4;
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return 2 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) = srca;
	m68k_areg(regs, dstreg) = (src);
	m68k_incpci(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 14 * CYCLE_UNIT / 2 + count_cycles;
}
/* 14 (3/0) */
/* 2 0,0   */

/* MOVEA.L (d16,An),An */
uae_u32 REGPARAM2 op_2068_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 31;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) = (src);
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (4/0) */
/* 4 0,0   */

/* MOVEA.L (d8,An,Xn),An */
uae_u32 REGPARAM2 op_2070_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 31;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	BusCyclePenalty += 2;
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) = (src);
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (4/0) */
/* 4 4,0   */

/* MOVEA.L (xxx).W,An */
uae_u32 REGPARAM2 op_2078_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 31;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, srca, 2, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) = (src);
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (4/0) */
/* 4 0,0   */

/* MOVEA.L (xxx).L,An */
uae_u32 REGPARAM2 op_2079_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 31;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	srca = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	srca |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, srca, 2, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) = (src);
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (5/0) */
/* 6 0,0   */

/* MOVEA.L (d16,PC),An */
uae_u32 REGPARAM2 op_207a_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 31;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = m68k_getpci() + 2;
	srca += (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 2);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) = (src);
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (4/0) */
/* 4 0,0   */

/* MOVEA.L (d8,PC,Xn),An */
uae_u32 REGPARAM2 op_207b_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 31;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	uaecptr tmppc = m68k_getpci() + 2;
	BusCyclePenalty += 2;
	srca = get_disp_ea_000(tmppc, get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 2);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) = (src);
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (4/0) */
/* 4 4,0   */

/* MOVEA.L #<data>.L,An */
uae_u32 REGPARAM2 op_207c_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 31;
	CurrentInstrCycles = 12; 
	uae_s32 src;
	src = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) = (src);
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (3/0) */
/* 6 0,0   */

/* MOVE.L Dn,(An) */
uae_u32 REGPARAM2 op_2080_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 8;  
	int loop_mode = regs.loop_mode;
	uae_s32 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	struct flag_struct oldflags;
	oldflags.cznv = regflags.cznv;
	if (dsta & 1) {
		m68k_incpci(4);
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	put_word_000(dsta + 2, src); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		ccr_68000_long_move_ae_LZN(src);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	if(!loop_mode) {
		regs.ir = regs.irc;
		opcode = regs.ir;
		get_word_000_prefetch(2);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 2, pcoffset);
			return 8 * CYCLE_UNIT / 2 + count_cycles;
		}
	} else {
		loop_mode = 0;
		loop_mode |= 2;
		loop_mode |= 4 << 16;
	}
	regs.loop_mode = loop_mode;
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8+ (0/2) */
/* 2 0,0   */

/* MOVE.L An,(An) */
uae_u32 REGPARAM2 op_2088_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 8;  
	int loop_mode = regs.loop_mode;
	uae_s32 src = m68k_areg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	struct flag_struct oldflags;
	oldflags.cznv = regflags.cznv;
	if (dsta & 1) {
		m68k_incpci(4);
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	put_word_000(dsta + 2, src); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		ccr_68000_long_move_ae_LZN(src);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	if(!loop_mode) {
		regs.ir = regs.irc;
		opcode = regs.ir;
		get_word_000_prefetch(2);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 2, pcoffset);
			return 8 * CYCLE_UNIT / 2 + count_cycles;
		}
	} else {
		loop_mode = 0;
		loop_mode |= 2;
		loop_mode |= 4 << 16;
	}
	regs.loop_mode = loop_mode;
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8+ (0/2) */
/* 2 0,0   */

/* MOVE.L (An),(An) */
uae_u32 REGPARAM2 op_2090_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 16; 
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	if (dsta & 1) {
		m68k_incpci(4);
		ccr_68000_long_move_ae_LZN(src);
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		ccr_68000_long_move_ae_LZN(src);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	put_word_000(dsta + 2, src); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	if(!loop_mode) {
		regs.ir = regs.irc;
		opcode = regs.ir;
		get_word_000_prefetch(2);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 2, pcoffset);
			return 16 * CYCLE_UNIT / 2 + count_cycles;
		}
	} else {
		loop_mode = 0;
		loop_mode |= 2;
		loop_mode |= 2 << 16;
	}
	regs.loop_mode = loop_mode;
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16+ (2/2) */
/* 2 0,0   */

/* MOVE.L (An)+,(An) */
uae_u32 REGPARAM2 op_2098_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 16; 
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) += 4;
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	if (dsta & 1) {
		m68k_incpci(4);
		ccr_68000_long_move_ae_LZN(src);
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		ccr_68000_long_move_ae_LZN(src);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	put_word_000(dsta + 2, src); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	if(!loop_mode) {
		regs.ir = regs.irc;
		opcode = regs.ir;
		get_word_000_prefetch(2);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 2, pcoffset);
			return 16 * CYCLE_UNIT / 2 + count_cycles;
		}
	} else {
		loop_mode = 0;
		loop_mode |= 2;
		loop_mode |= 2 << 16;
	}
	regs.loop_mode = loop_mode;
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16+ (2/2) */
/* 2 0,0   */

/* MOVE.L -(An),(An) */
uae_u32 REGPARAM2 op_20a0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 18; 
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - 4;
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return 2 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) = srca;
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	if (dsta & 1) {
		m68k_incpci(4);
		ccr_68000_long_move_ae_LZN(src);
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		ccr_68000_long_move_ae_LZN(src);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	put_word_000(dsta + 2, src); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	if(!loop_mode) {
		regs.ir = regs.irc;
		opcode = regs.ir;
		get_word_000_prefetch(2);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 2, pcoffset);
			return 18 * CYCLE_UNIT / 2 + count_cycles;
		}
	} else {
		loop_mode = 0;
		loop_mode |= 2;
		loop_mode |= 2 << 16;
	}
	regs.loop_mode = loop_mode;
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18+ (2/2) */
/* 2 0,0   */

/* MOVE.L (d16,An),(An) */
uae_u32 REGPARAM2 op_20a8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 24; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	if (dsta & 1) {
		m68k_incpci(6);
		ccr_68000_long_move_ae_LZN(src);
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		ccr_68000_long_move_ae_LZN(src);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	put_word_000(dsta + 2, src); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 24 * CYCLE_UNIT / 2 + count_cycles;
}
/* 24 (4/2) */
/* 4 0,0   */

/* MOVE.L (d8,An,Xn),(An) */
uae_u32 REGPARAM2 op_20b0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 26; 
	uaecptr srca;
	BusCyclePenalty += 2;
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	if (dsta & 1) {
		m68k_incpci(6);
		ccr_68000_long_move_ae_LZN(src);
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		ccr_68000_long_move_ae_LZN(src);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	put_word_000(dsta + 2, src); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return 22 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 26 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 26 * CYCLE_UNIT / 2 + count_cycles;
}
/* 26 (4/2) */
/* 4 4,0   */

/* MOVE.L (xxx).W,(An) */
uae_u32 REGPARAM2 op_20b8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 24; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, srca, 2, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	if (dsta & 1) {
		m68k_incpci(6);
		ccr_68000_long_move_ae_LZN(src);
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		ccr_68000_long_move_ae_LZN(src);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	put_word_000(dsta + 2, src); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 24 * CYCLE_UNIT / 2 + count_cycles;
}
/* 24 (4/2) */
/* 4 0,0   */

/* MOVE.L (xxx).L,(An) */
uae_u32 REGPARAM2 op_20b9_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 28; 
	uaecptr srca;
	srca = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	srca |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, srca, 2, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	if (dsta & 1) {
		m68k_incpci(8);
		ccr_68000_long_move_ae_LZN(src);
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		ccr_68000_long_move_ae_LZN(src);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	put_word_000(dsta + 2, src); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 28 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 28 * CYCLE_UNIT / 2 + count_cycles;
}
/* 28 (5/2) */
/* 6 0,0   */

/* MOVE.L (d16,PC),(An) */
uae_u32 REGPARAM2 op_20ba_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 24; 
	uaecptr srca;
	srca = m68k_getpci() + 2;
	srca += (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 2);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	if (dsta & 1) {
		m68k_incpci(6);
		ccr_68000_long_move_ae_LZN(src);
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		ccr_68000_long_move_ae_LZN(src);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	put_word_000(dsta + 2, src); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 24 * CYCLE_UNIT / 2 + count_cycles;
}
/* 24 (4/2) */
/* 4 0,0   */

/* MOVE.L (d8,PC,Xn),(An) */
uae_u32 REGPARAM2 op_20bb_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 26; 
	uaecptr srca;
	uaecptr tmppc = m68k_getpci() + 2;
	BusCyclePenalty += 2;
	srca = get_disp_ea_000(tmppc, get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 2);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	if (dsta & 1) {
		m68k_incpci(6);
		ccr_68000_long_move_ae_LZN(src);
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		ccr_68000_long_move_ae_LZN(src);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	put_word_000(dsta + 2, src); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return 22 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 26 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 26 * CYCLE_UNIT / 2 + count_cycles;
}
/* 26 (4/2) */
/* 4 4,0   */

/* MOVE.L #<data>.L,(An) */
uae_u32 REGPARAM2 op_20bc_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 20; 
	uae_s32 src;
	src = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	struct flag_struct oldflags;
	oldflags.cznv = regflags.cznv;
	if (dsta & 1) {
		m68k_incpci(8);
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	put_word_000(dsta + 2, src); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		ccr_68000_long_move_ae_LZN(src);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (3/2) */
/* 6 0,0   */

/* MOVE.L Dn,(An)+ */
uae_u32 REGPARAM2 op_20c0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 8;  
	int loop_mode = regs.loop_mode;
	uae_s32 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	m68k_areg(regs, dstreg) += 4;
	struct flag_struct oldflags;
	oldflags.cznv = regflags.cznv;
	if (dsta & 1) {
		m68k_incpci(4);
		m68k_areg(regs, dstreg) = dsta;
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, dstreg) -= 4;
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	put_word_000(dsta + 2, src); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		ccr_68000_long_move_ae_LZN(src);
		m68k_areg(regs, dstreg) -= 4;
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	if(!loop_mode) {
		regs.ir = regs.irc;
		opcode = regs.ir;
		get_word_000_prefetch(2);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 2, pcoffset);
			return 8 * CYCLE_UNIT / 2 + count_cycles;
		}
	} else {
		loop_mode = 0;
		loop_mode |= 2;
		loop_mode |= 4 << 16;
	}
	regs.loop_mode = loop_mode;
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8+ (0/2) */
/* 2 0,0   */

/* MOVE.L An,(An)+ */
uae_u32 REGPARAM2 op_20c8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 8;  
	int loop_mode = regs.loop_mode;
	uae_s32 src = m68k_areg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	m68k_areg(regs, dstreg) += 4;
	struct flag_struct oldflags;
	oldflags.cznv = regflags.cznv;
	if (dsta & 1) {
		m68k_incpci(4);
		m68k_areg(regs, dstreg) = dsta;
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, dstreg) -= 4;
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	put_word_000(dsta + 2, src); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		ccr_68000_long_move_ae_LZN(src);
		m68k_areg(regs, dstreg) -= 4;
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	if(!loop_mode) {
		regs.ir = regs.irc;
		opcode = regs.ir;
		get_word_000_prefetch(2);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 2, pcoffset);
			return 8 * CYCLE_UNIT / 2 + count_cycles;
		}
	} else {
		loop_mode = 0;
		loop_mode |= 2;
		loop_mode |= 4 << 16;
	}
	regs.loop_mode = loop_mode;
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8+ (0/2) */
/* 2 0,0   */

/* MOVE.L (An),(An)+ */
uae_u32 REGPARAM2 op_20d0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 16; 
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	m68k_areg(regs, dstreg) += 4;
	if (dsta & 1) {
		m68k_incpci(4);
		ccr_68000_long_move_ae_LZN(src);
		m68k_areg(regs, dstreg) = dsta;
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		ccr_68000_long_move_ae_LZN(src);
		m68k_areg(regs, dstreg) -= 4;
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	put_word_000(dsta + 2, src); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		ccr_68000_long_move_ae_normal(src);
		m68k_areg(regs, dstreg) -= 4;
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	if(!loop_mode) {
		regs.ir = regs.irc;
		opcode = regs.ir;
		get_word_000_prefetch(2);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 2, pcoffset);
			return 16 * CYCLE_UNIT / 2 + count_cycles;
		}
	} else {
		loop_mode = 0;
		loop_mode |= 2;
		loop_mode |= 2 << 16;
	}
	regs.loop_mode = loop_mode;
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16+ (2/2) */
/* 2 0,0   */

/* MOVE.L (An)+,(An)+ */
uae_u32 REGPARAM2 op_20d8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 16; 
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) += 4;
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	m68k_areg(regs, dstreg) += 4;
	if (dsta & 1) {
		m68k_incpci(4);
		ccr_68000_long_move_ae_LZN(src);
		m68k_areg(regs, dstreg) = dsta;
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		ccr_68000_long_move_ae_LZN(src);
		m68k_areg(regs, dstreg) -= 4;
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	put_word_000(dsta + 2, src); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		ccr_68000_long_move_ae_normal(src);
		m68k_areg(regs, dstreg) -= 4;
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	if(!loop_mode) {
		regs.ir = regs.irc;
		opcode = regs.ir;
		get_word_000_prefetch(2);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 2, pcoffset);
			return 16 * CYCLE_UNIT / 2 + count_cycles;
		}
	} else {
		loop_mode = 0;
		loop_mode |= 2;
		loop_mode |= 2 << 16;
	}
	regs.loop_mode = loop_mode;
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16+ (2/2) */
/* 2 0,0   */

/* MOVE.L -(An),(An)+ */
uae_u32 REGPARAM2 op_20e0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 18; 
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - 4;
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return 2 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) = srca;
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	m68k_areg(regs, dstreg) += 4;
	if (dsta & 1) {
		m68k_incpci(4);
		ccr_68000_long_move_ae_LZN(src);
		m68k_areg(regs, dstreg) = dsta;
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		ccr_68000_long_move_ae_LZN(src);
		m68k_areg(regs, dstreg) -= 4;
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	put_word_000(dsta + 2, src); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		ccr_68000_long_move_ae_normal(src);
		m68k_areg(regs, dstreg) -= 4;
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	if(!loop_mode) {
		regs.ir = regs.irc;
		opcode = regs.ir;
		get_word_000_prefetch(2);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 2, pcoffset);
			return 18 * CYCLE_UNIT / 2 + count_cycles;
		}
	} else {
		loop_mode = 0;
		loop_mode |= 2;
		loop_mode |= 2 << 16;
	}
	regs.loop_mode = loop_mode;
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18+ (2/2) */
/* 2 0,0   */

/* MOVE.L (d16,An),(An)+ */
uae_u32 REGPARAM2 op_20e8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 24; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	m68k_areg(regs, dstreg) += 4;
	if (dsta & 1) {
		m68k_incpci(6);
		ccr_68000_long_move_ae_LZN(src);
		m68k_areg(regs, dstreg) = dsta;
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		ccr_68000_long_move_ae_LZN(src);
		m68k_areg(regs, dstreg) -= 4;
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	put_word_000(dsta + 2, src); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		ccr_68000_long_move_ae_normal(src);
		m68k_areg(regs, dstreg) -= 4;
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 24 * CYCLE_UNIT / 2 + count_cycles;
}
/* 24 (4/2) */
/* 4 0,0   */

/* MOVE.L (d8,An,Xn),(An)+ */
uae_u32 REGPARAM2 op_20f0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 26; 
	uaecptr srca;
	BusCyclePenalty += 2;
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	m68k_areg(regs, dstreg) += 4;
	if (dsta & 1) {
		m68k_incpci(6);
		ccr_68000_long_move_ae_LZN(src);
		m68k_areg(regs, dstreg) = dsta;
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		ccr_68000_long_move_ae_LZN(src);
		m68k_areg(regs, dstreg) -= 4;
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	put_word_000(dsta + 2, src); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		ccr_68000_long_move_ae_normal(src);
		m68k_areg(regs, dstreg) -= 4;
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return 22 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 26 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 26 * CYCLE_UNIT / 2 + count_cycles;
}
/* 26 (4/2) */
/* 4 4,0   */

/* MOVE.L (xxx).W,(An)+ */
uae_u32 REGPARAM2 op_20f8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 24; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, srca, 2, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	m68k_areg(regs, dstreg) += 4;
	if (dsta & 1) {
		m68k_incpci(6);
		ccr_68000_long_move_ae_LZN(src);
		m68k_areg(regs, dstreg) = dsta;
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		ccr_68000_long_move_ae_LZN(src);
		m68k_areg(regs, dstreg) -= 4;
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	put_word_000(dsta + 2, src); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		ccr_68000_long_move_ae_normal(src);
		m68k_areg(regs, dstreg) -= 4;
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 24 * CYCLE_UNIT / 2 + count_cycles;
}
/* 24 (4/2) */
/* 4 0,0   */

/* MOVE.L (xxx).L,(An)+ */
uae_u32 REGPARAM2 op_20f9_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 28; 
	uaecptr srca;
	srca = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	srca |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, srca, 2, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	m68k_areg(regs, dstreg) += 4;
	if (dsta & 1) {
		m68k_incpci(8);
		ccr_68000_long_move_ae_LZN(src);
		m68k_areg(regs, dstreg) = dsta;
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		ccr_68000_long_move_ae_LZN(src);
		m68k_areg(regs, dstreg) -= 4;
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	put_word_000(dsta + 2, src); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		ccr_68000_long_move_ae_normal(src);
		m68k_areg(regs, dstreg) -= 4;
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 28 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 28 * CYCLE_UNIT / 2 + count_cycles;
}
/* 28 (5/2) */
/* 6 0,0   */

/* MOVE.L (d16,PC),(An)+ */
uae_u32 REGPARAM2 op_20fa_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 24; 
	uaecptr srca;
	srca = m68k_getpci() + 2;
	srca += (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 2);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	m68k_areg(regs, dstreg) += 4;
	if (dsta & 1) {
		m68k_incpci(6);
		ccr_68000_long_move_ae_LZN(src);
		m68k_areg(regs, dstreg) = dsta;
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		ccr_68000_long_move_ae_LZN(src);
		m68k_areg(regs, dstreg) -= 4;
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	put_word_000(dsta + 2, src); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		ccr_68000_long_move_ae_normal(src);
		m68k_areg(regs, dstreg) -= 4;
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 24 * CYCLE_UNIT / 2 + count_cycles;
}
/* 24 (4/2) */
/* 4 0,0   */

/* MOVE.L (d8,PC,Xn),(An)+ */
uae_u32 REGPARAM2 op_20fb_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 26; 
	uaecptr srca;
	uaecptr tmppc = m68k_getpci() + 2;
	BusCyclePenalty += 2;
	srca = get_disp_ea_000(tmppc, get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 2);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	m68k_areg(regs, dstreg) += 4;
	if (dsta & 1) {
		m68k_incpci(6);
		ccr_68000_long_move_ae_LZN(src);
		m68k_areg(regs, dstreg) = dsta;
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		ccr_68000_long_move_ae_LZN(src);
		m68k_areg(regs, dstreg) -= 4;
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	put_word_000(dsta + 2, src); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		ccr_68000_long_move_ae_normal(src);
		m68k_areg(regs, dstreg) -= 4;
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return 22 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 26 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 26 * CYCLE_UNIT / 2 + count_cycles;
}
/* 26 (4/2) */
/* 4 4,0   */

/* MOVE.L #<data>.L,(An)+ */
uae_u32 REGPARAM2 op_20fc_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 20; 
	uae_s32 src;
	src = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	m68k_areg(regs, dstreg) += 4;
	struct flag_struct oldflags;
	oldflags.cznv = regflags.cznv;
	if (dsta & 1) {
		m68k_incpci(8);
		m68k_areg(regs, dstreg) = dsta;
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		m68k_areg(regs, dstreg) -= 4;
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	put_word_000(dsta + 2, src); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		ccr_68000_long_move_ae_LZN(src);
		m68k_areg(regs, dstreg) -= 4;
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (3/2) */
/* 6 0,0   */

/* MOVE.L Dn,-(An) */
uae_u32 REGPARAM2 op_2100_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 14; 
	uae_s32 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - 4;
	m68k_areg(regs, dstreg) = dsta;
	regs.ir = regs.irc;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		m68k_areg(regs, dstreg) += 4;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	struct flag_struct oldflags;
	oldflags.cznv = regflags.cznv;
	if (dsta & 1) {
		m68k_incpci(4);
		ccr_68000_long_move_ae_normal(src);
		m68k_areg(regs, dstreg) = dsta + 4;
		dsta += 2;
		exception3_write_access(opcode, dsta, 2, src, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		ccr_68000_long_move_ae_normal(src);
		m68k_areg(regs, dstreg) += 4;
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	put_word_000(dsta, src >> 16); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		ccr_68000_long_move_ae_normal(src);
		m68k_areg(regs, dstreg) += 4;
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 14 * CYCLE_UNIT / 2 + count_cycles;
}
/* 14 (1/2) */
/* 2 0,0   */

/* MOVE.L An,-(An) */
uae_u32 REGPARAM2 op_2108_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 14; 
	uae_s32 src = m68k_areg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - 4;
	m68k_areg(regs, dstreg) = dsta;
	regs.ir = regs.irc;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		m68k_areg(regs, dstreg) += 4;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	struct flag_struct oldflags;
	oldflags.cznv = regflags.cznv;
	if (dsta & 1) {
		m68k_incpci(4);
		ccr_68000_long_move_ae_normal(src);
		m68k_areg(regs, dstreg) = dsta + 4;
		dsta += 2;
		exception3_write_access(opcode, dsta, 2, src, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		ccr_68000_long_move_ae_normal(src);
		m68k_areg(regs, dstreg) += 4;
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	put_word_000(dsta, src >> 16); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		ccr_68000_long_move_ae_normal(src);
		m68k_areg(regs, dstreg) += 4;
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 14 * CYCLE_UNIT / 2 + count_cycles;
}
/* 14 (1/2) */
/* 2 0,0   */

/* MOVE.L (An),-(An) */
uae_u32 REGPARAM2 op_2110_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 16; 
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - 4;
	m68k_areg(regs, dstreg) = dsta;
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_000_prefetch(4);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			int pcoffset = 0;
			m68k_areg(regs, dstreg) += 4;
			ccr_68000_long_move_ae_LZN(src);
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return 8 * CYCLE_UNIT / 2 + count_cycles;
		}
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	if(loop_mode & 0xfffe) {
		count_cycles += (loop_mode & 0xfffe) * CYCLE_UNIT / 2;
		loop_mode = 1;
	}
	if (dsta & 1) {
		m68k_incpci(4);
		ccr_68000_long_move_ae_normal(src);
		m68k_areg(regs, dstreg) = dsta + 4;
		dsta += 2;
		exception3_write_access(opcode, dsta, 2, src, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		ccr_68000_long_move_ae_normal(src);
		m68k_areg(regs, dstreg) += 4;
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	put_word_000(dsta, src >> 16); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		ccr_68000_long_move_ae_normal(src);
		m68k_areg(regs, dstreg) += 4;
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	regs.loop_mode = loop_mode;
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16+ (2/2) */
/* 2 0,0   */

/* MOVE.L (An)+,-(An) */
uae_u32 REGPARAM2 op_2118_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 16; 
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) += 4;
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - 4;
	m68k_areg(regs, dstreg) = dsta;
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_000_prefetch(4);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			int pcoffset = 0;
			m68k_areg(regs, dstreg) += 4;
			ccr_68000_long_move_ae_LZN(src);
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return 8 * CYCLE_UNIT / 2 + count_cycles;
		}
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	if(loop_mode & 0xfffe) {
		count_cycles += (loop_mode & 0xfffe) * CYCLE_UNIT / 2;
		loop_mode = 1;
	}
	if (dsta & 1) {
		m68k_incpci(4);
		ccr_68000_long_move_ae_normal(src);
		m68k_areg(regs, dstreg) = dsta + 4;
		dsta += 2;
		exception3_write_access(opcode, dsta, 2, src, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		ccr_68000_long_move_ae_normal(src);
		m68k_areg(regs, dstreg) += 4;
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	put_word_000(dsta, src >> 16); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		ccr_68000_long_move_ae_normal(src);
		m68k_areg(regs, dstreg) += 4;
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	regs.loop_mode = loop_mode;
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16+ (2/2) */
/* 2 0,0   */

/* MOVE.L -(An),-(An) */
uae_u32 REGPARAM2 op_2120_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 18; 
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - 4;
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return 2 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) = srca;
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - 4;
	m68k_areg(regs, dstreg) = dsta;
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_000_prefetch(4);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			int pcoffset = 0;
			m68k_areg(regs, dstreg) += 4;
			ccr_68000_long_move_ae_LZN(src);
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return 10 * CYCLE_UNIT / 2 + count_cycles;
		}
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	if(loop_mode & 0xfffe) {
		count_cycles += (loop_mode & 0xfffe) * CYCLE_UNIT / 2;
		loop_mode = 1;
	}
	if (dsta & 1) {
		m68k_incpci(4);
		ccr_68000_long_move_ae_normal(src);
		m68k_areg(regs, dstreg) = dsta + 4;
		dsta += 2;
		exception3_write_access(opcode, dsta, 2, src, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		ccr_68000_long_move_ae_normal(src);
		m68k_areg(regs, dstreg) += 4;
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	put_word_000(dsta, src >> 16); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		ccr_68000_long_move_ae_normal(src);
		m68k_areg(regs, dstreg) += 4;
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	regs.loop_mode = loop_mode;
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18+ (2/2) */
/* 2 0,0   */

/* MOVE.L (d16,An),-(An) */
uae_u32 REGPARAM2 op_2128_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 24; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - 4;
	m68k_areg(regs, dstreg) = dsta;
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		m68k_areg(regs, dstreg) += 4;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(6);
		ccr_68000_long_move_ae_normal(src);
		m68k_areg(regs, dstreg) = dsta + 4;
		dsta += 2;
		exception3_write_access(opcode, dsta, 2, src, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		ccr_68000_long_move_ae_normal(src);
		m68k_areg(regs, dstreg) += 4;
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	put_word_000(dsta, src >> 16); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		ccr_68000_long_move_ae_normal(src);
		m68k_areg(regs, dstreg) += 4;
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 24 * CYCLE_UNIT / 2 + count_cycles;
}
/* 24 (4/2) */
/* 4 0,0   */

/* MOVE.L (d8,An,Xn),-(An) */
uae_u32 REGPARAM2 op_2130_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 26; 
	uaecptr srca;
	BusCyclePenalty += 2;
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - 4;
	m68k_areg(regs, dstreg) = dsta;
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		m68k_areg(regs, dstreg) += 4;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(6);
		ccr_68000_long_move_ae_normal(src);
		m68k_areg(regs, dstreg) = dsta + 4;
		dsta += 2;
		exception3_write_access(opcode, dsta, 2, src, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		ccr_68000_long_move_ae_normal(src);
		m68k_areg(regs, dstreg) += 4;
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return 22 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	put_word_000(dsta, src >> 16); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		ccr_68000_long_move_ae_normal(src);
		m68k_areg(regs, dstreg) += 4;
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return 26 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 26 * CYCLE_UNIT / 2 + count_cycles;
}
/* 26 (4/2) */
/* 4 4,0   */

/* MOVE.L (xxx).W,-(An) */
uae_u32 REGPARAM2 op_2138_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 24; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, srca, 2, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - 4;
	m68k_areg(regs, dstreg) = dsta;
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		m68k_areg(regs, dstreg) += 4;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(6);
		ccr_68000_long_move_ae_normal(src);
		m68k_areg(regs, dstreg) = dsta + 4;
		dsta += 2;
		exception3_write_access(opcode, dsta, 2, src, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		ccr_68000_long_move_ae_normal(src);
		m68k_areg(regs, dstreg) += 4;
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	put_word_000(dsta, src >> 16); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		ccr_68000_long_move_ae_normal(src);
		m68k_areg(regs, dstreg) += 4;
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 24 * CYCLE_UNIT / 2 + count_cycles;
}
/* 24 (4/2) */
/* 4 0,0   */

/* MOVE.L (xxx).L,-(An) */
uae_u32 REGPARAM2 op_2139_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 28; 
	uaecptr srca;
	srca = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	srca |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, srca, 2, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - 4;
	m68k_areg(regs, dstreg) = dsta;
	regs.ir = regs.irc;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		m68k_areg(regs, dstreg) += 4;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(8);
		ccr_68000_long_move_ae_normal(src);
		m68k_areg(regs, dstreg) = dsta + 4;
		dsta += 2;
		exception3_write_access(opcode, dsta, 2, src, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		ccr_68000_long_move_ae_normal(src);
		m68k_areg(regs, dstreg) += 4;
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	put_word_000(dsta, src >> 16); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		ccr_68000_long_move_ae_normal(src);
		m68k_areg(regs, dstreg) += 4;
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return 28 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 28 * CYCLE_UNIT / 2 + count_cycles;
}
/* 28 (5/2) */
/* 6 0,0   */

/* MOVE.L (d16,PC),-(An) */
uae_u32 REGPARAM2 op_213a_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 24; 
	uaecptr srca;
	srca = m68k_getpci() + 2;
	srca += (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 2);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - 4;
	m68k_areg(regs, dstreg) = dsta;
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		m68k_areg(regs, dstreg) += 4;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(6);
		ccr_68000_long_move_ae_normal(src);
		m68k_areg(regs, dstreg) = dsta + 4;
		dsta += 2;
		exception3_write_access(opcode, dsta, 2, src, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		ccr_68000_long_move_ae_normal(src);
		m68k_areg(regs, dstreg) += 4;
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	put_word_000(dsta, src >> 16); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		ccr_68000_long_move_ae_normal(src);
		m68k_areg(regs, dstreg) += 4;
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 24 * CYCLE_UNIT / 2 + count_cycles;
}
/* 24 (4/2) */
/* 4 0,0   */

/* MOVE.L (d8,PC,Xn),-(An) */
uae_u32 REGPARAM2 op_213b_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 26; 
	uaecptr srca;
	uaecptr tmppc = m68k_getpci() + 2;
	BusCyclePenalty += 2;
	srca = get_disp_ea_000(tmppc, get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 2);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - 4;
	m68k_areg(regs, dstreg) = dsta;
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		m68k_areg(regs, dstreg) += 4;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(6);
		ccr_68000_long_move_ae_normal(src);
		m68k_areg(regs, dstreg) = dsta + 4;
		dsta += 2;
		exception3_write_access(opcode, dsta, 2, src, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		ccr_68000_long_move_ae_normal(src);
		m68k_areg(regs, dstreg) += 4;
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return 22 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	put_word_000(dsta, src >> 16); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		ccr_68000_long_move_ae_normal(src);
		m68k_areg(regs, dstreg) += 4;
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return 26 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 26 * CYCLE_UNIT / 2 + count_cycles;
}
/* 26 (4/2) */
/* 4 4,0   */

/* MOVE.L #<data>.L,-(An) */
uae_u32 REGPARAM2 op_213c_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 20; 
	uae_s32 src;
	src = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - 4;
	m68k_areg(regs, dstreg) = dsta;
	regs.ir = regs.irc;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		m68k_areg(regs, dstreg) += 4;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	struct flag_struct oldflags;
	oldflags.cznv = regflags.cznv;
	if (dsta & 1) {
		m68k_incpci(8);
		ccr_68000_long_move_ae_normal(src);
		m68k_areg(regs, dstreg) = dsta + 4;
		dsta += 2;
		exception3_write_access(opcode, dsta, 2, src, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		ccr_68000_long_move_ae_normal(src);
		m68k_areg(regs, dstreg) += 4;
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	put_word_000(dsta, src >> 16); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		ccr_68000_long_move_ae_normal(src);
		m68k_areg(regs, dstreg) += 4;
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (3/2) */
/* 6 0,0   */

/* MOVE.L Dn,(d16,An) */
uae_u32 REGPARAM2 op_2140_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 16; 
	uae_s32 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	struct flag_struct oldflags;
	oldflags.cznv = regflags.cznv;
	if (dsta & 1) {
		m68k_incpci(4);
		ccr_68000_long_move_ae_HNZ(src);
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		SET_NFLG(src < 0);
		if((src & 0xffff0000)) SET_ZFLG(0);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	put_word_000(dsta + 2, src); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		ccr_68000_long_move_ae_LZN(src);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (2/2) */
/* 4 0,0   */

/* MOVE.L An,(d16,An) */
uae_u32 REGPARAM2 op_2148_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 16; 
	uae_s32 src = m68k_areg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	struct flag_struct oldflags;
	oldflags.cznv = regflags.cznv;
	if (dsta & 1) {
		m68k_incpci(4);
		ccr_68000_long_move_ae_HNZ(src);
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		SET_NFLG(src < 0);
		if((src & 0xffff0000)) SET_ZFLG(0);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	put_word_000(dsta + 2, src); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		ccr_68000_long_move_ae_LZN(src);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (2/2) */
/* 4 0,0   */

/* MOVE.L (An),(d16,An) */
uae_u32 REGPARAM2 op_2150_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 24; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch(opcode, 4, 0);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(4);
		ccr_68000_long_move_ae_normal(src);
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	put_word_000(dsta + 2, src); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 24 * CYCLE_UNIT / 2 + count_cycles;
}
/* 24 (4/2) */
/* 4 0,0   */

/* MOVE.L (An)+,(d16,An) */
uae_u32 REGPARAM2 op_2158_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 24; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) += 4;
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch(opcode, 4, 0);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(4);
		ccr_68000_long_move_ae_normal(src);
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	put_word_000(dsta + 2, src); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 24 * CYCLE_UNIT / 2 + count_cycles;
}
/* 24 (4/2) */
/* 4 0,0   */

/* MOVE.L -(An),(d16,An) */
uae_u32 REGPARAM2 op_2160_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 26; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - 4;
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return 2 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) = srca;
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch(opcode, 4, 0);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(4);
		ccr_68000_long_move_ae_normal(src);
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	put_word_000(dsta + 2, src); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return 22 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 26 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 26 * CYCLE_UNIT / 2 + count_cycles;
}
/* 26 (4/2) */
/* 4 0,0   */

/* MOVE.L (d16,An),(d16,An) */
uae_u32 REGPARAM2 op_2168_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 28; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch(opcode, 6, 0);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(6);
		ccr_68000_long_move_ae_normal(src);
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	put_word_000(dsta + 2, src); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 28 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 28 * CYCLE_UNIT / 2 + count_cycles;
}
/* 28 (5/2) */
/* 6 0,0   */

/* MOVE.L (d8,An,Xn),(d16,An) */
uae_u32 REGPARAM2 op_2170_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 30; 
	uaecptr srca;
	BusCyclePenalty += 2;
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch(opcode, 6, 0);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(6);
		ccr_68000_long_move_ae_normal(src);
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return 22 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	put_word_000(dsta + 2, src); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return 26 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 30 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 30 * CYCLE_UNIT / 2 + count_cycles;
}
/* 30 (5/2) */
/* 6 6,0   */

/* MOVE.L (xxx).W,(d16,An) */
uae_u32 REGPARAM2 op_2178_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 28; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, srca, 2, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch(opcode, 6, 0);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(6);
		ccr_68000_long_move_ae_normal(src);
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	put_word_000(dsta + 2, src); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 28 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 28 * CYCLE_UNIT / 2 + count_cycles;
}
/* 28 (5/2) */
/* 6 0,0   */

/* MOVE.L (xxx).L,(d16,An) */
uae_u32 REGPARAM2 op_2179_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 32; 
	uaecptr srca;
	srca = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	srca |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, srca, 2, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch(opcode, 8, 0);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(8);
		ccr_68000_long_move_ae_normal(src);
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	put_word_000(dsta + 2, src); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return 28 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(8);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 32 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 32 * CYCLE_UNIT / 2 + count_cycles;
}
/* 32 (6/2) */
/* 8 0,0   */

/* MOVE.L (d16,PC),(d16,An) */
uae_u32 REGPARAM2 op_217a_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 28; 
	uaecptr srca;
	srca = m68k_getpci() + 2;
	srca += (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 2);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch(opcode, 6, 0);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(6);
		ccr_68000_long_move_ae_normal(src);
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	put_word_000(dsta + 2, src); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 28 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 28 * CYCLE_UNIT / 2 + count_cycles;
}
/* 28 (5/2) */
/* 6 0,0   */

/* MOVE.L (d8,PC,Xn),(d16,An) */
uae_u32 REGPARAM2 op_217b_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 30; 
	uaecptr srca;
	uaecptr tmppc = m68k_getpci() + 2;
	BusCyclePenalty += 2;
	srca = get_disp_ea_000(tmppc, get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 2);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch(opcode, 6, 0);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(6);
		ccr_68000_long_move_ae_normal(src);
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return 22 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	put_word_000(dsta + 2, src); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return 26 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 30 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 30 * CYCLE_UNIT / 2 + count_cycles;
}
/* 30 (5/2) */
/* 6 6,0   */

/* MOVE.L #<data>.L,(d16,An) */
uae_u32 REGPARAM2 op_217c_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 24; 
	uae_s32 src;
	src = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 8, 0);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	struct flag_struct oldflags;
	oldflags.cznv = regflags.cznv;
	if (dsta & 1) {
		m68k_incpci(8);
		ccr_68000_long_move_ae_HNZ(src);
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		ccr_68000_long_move_ae_HNZ(src);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	put_word_000(dsta + 2, src); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		ccr_68000_long_move_ae_LZN(src);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(8);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 24 * CYCLE_UNIT / 2 + count_cycles;
}
/* 24 (4/2) */
/* 8 0,0   */

/* MOVE.L Dn,(d8,An,Xn) */
uae_u32 REGPARAM2 op_2180_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 18; 
	uae_s32 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	BusCyclePenalty += 2;
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	struct flag_struct oldflags;
	oldflags.cznv = regflags.cznv;
	if (dsta & 1) {
		m68k_incpci(4);
		ccr_68000_long_move_ae_HNZ(src);
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		SET_NFLG(src < 0);
		if((src & 0xffff0000)) SET_ZFLG(0);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	put_word_000(dsta + 2, src); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		ccr_68000_long_move_ae_LZN(src);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (2/2) */
/* 4 4,0   */

/* MOVE.L An,(d8,An,Xn) */
uae_u32 REGPARAM2 op_2188_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 18; 
	uae_s32 src = m68k_areg(regs, srcreg);
	uaecptr dsta;
	BusCyclePenalty += 2;
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	struct flag_struct oldflags;
	oldflags.cznv = regflags.cznv;
	if (dsta & 1) {
		m68k_incpci(4);
		ccr_68000_long_move_ae_HNZ(src);
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		SET_NFLG(src < 0);
		if((src & 0xffff0000)) SET_ZFLG(0);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	put_word_000(dsta + 2, src); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		ccr_68000_long_move_ae_LZN(src);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (2/2) */
/* 4 4,0   */

/* MOVE.L (An),(d8,An,Xn) */
uae_u32 REGPARAM2 op_2190_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 26; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	BusCyclePenalty += 2;
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch(opcode, 4, 0);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(4);
		ccr_68000_long_move_ae_normal(src);
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	put_word_000(dsta + 2, src); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return 22 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 26 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 26 * CYCLE_UNIT / 2 + count_cycles;
}
/* 26 (4/2) */
/* 4 4,0   */

/* MOVE.L (An)+,(d8,An,Xn) */
uae_u32 REGPARAM2 op_2198_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 26; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) += 4;
	uaecptr dsta;
	BusCyclePenalty += 2;
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch(opcode, 4, 0);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(4);
		ccr_68000_long_move_ae_normal(src);
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	put_word_000(dsta + 2, src); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return 22 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 26 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 26 * CYCLE_UNIT / 2 + count_cycles;
}
/* 26 (4/2) */
/* 4 4,0   */

/* MOVE.L -(An),(d8,An,Xn) */
uae_u32 REGPARAM2 op_21a0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 28; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - 4;
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return 2 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) = srca;
	uaecptr dsta;
	BusCyclePenalty += 2;
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch(opcode, 4, 0);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(4);
		ccr_68000_long_move_ae_normal(src);
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	put_word_000(dsta + 2, src); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 28 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 28 * CYCLE_UNIT / 2 + count_cycles;
}
/* 28 (4/2) */
/* 4 4,0   */

/* MOVE.L (d16,An),(d8,An,Xn) */
uae_u32 REGPARAM2 op_21a8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 30; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	BusCyclePenalty += 2;
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_000_prefetch(6));
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch(opcode, 6, 0);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(6);
		ccr_68000_long_move_ae_normal(src);
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return 22 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	put_word_000(dsta + 2, src); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return 26 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 30 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 30 * CYCLE_UNIT / 2 + count_cycles;
}
/* 30 (5/2) */
/* 6 4,0   */

/* MOVE.L (d8,An,Xn),(d8,An,Xn) */
uae_u32 REGPARAM2 op_21b0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 32; 
	uaecptr srca;
	BusCyclePenalty += 2;
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	BusCyclePenalty += 2;
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_000_prefetch(6));
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch(opcode, 6, 0);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(6);
		ccr_68000_long_move_ae_normal(src);
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	put_word_000(dsta + 2, src); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return 28 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 32 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 32 * CYCLE_UNIT / 2 + count_cycles;
}
/* 32 (5/2) */
/* 6 6,4   */

/* MOVE.L (xxx).W,(d8,An,Xn) */
uae_u32 REGPARAM2 op_21b8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 30; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, srca, 2, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	BusCyclePenalty += 2;
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_000_prefetch(6));
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch(opcode, 6, 0);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(6);
		ccr_68000_long_move_ae_normal(src);
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return 22 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	put_word_000(dsta + 2, src); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return 26 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 30 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 30 * CYCLE_UNIT / 2 + count_cycles;
}
/* 30 (5/2) */
/* 6 4,0   */

/* MOVE.L (xxx).L,(d8,An,Xn) */
uae_u32 REGPARAM2 op_21b9_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 34; 
	uaecptr srca;
	srca = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	srca |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, srca, 2, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	BusCyclePenalty += 2;
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_000_prefetch(8));
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch(opcode, 8, 0);
		return 22 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(8);
		ccr_68000_long_move_ae_normal(src);
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return 22 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return 26 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	put_word_000(dsta + 2, src); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return 30 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(8);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 34 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 34 * CYCLE_UNIT / 2 + count_cycles;
}
/* 34 (6/2) */
/* 8 4,0   */

/* MOVE.L (d16,PC),(d8,An,Xn) */
uae_u32 REGPARAM2 op_21ba_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 30; 
	uaecptr srca;
	srca = m68k_getpci() + 2;
	srca += (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 2);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	BusCyclePenalty += 2;
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_000_prefetch(6));
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch(opcode, 6, 0);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(6);
		ccr_68000_long_move_ae_normal(src);
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return 22 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	put_word_000(dsta + 2, src); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return 26 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 30 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 30 * CYCLE_UNIT / 2 + count_cycles;
}
/* 30 (5/2) */
/* 6 4,0   */

/* MOVE.L (d8,PC,Xn),(d8,An,Xn) */
uae_u32 REGPARAM2 op_21bb_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 32; 
	uaecptr srca;
	uaecptr tmppc = m68k_getpci() + 2;
	BusCyclePenalty += 2;
	srca = get_disp_ea_000(tmppc, get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 2);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	BusCyclePenalty += 2;
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_000_prefetch(6));
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch(opcode, 6, 0);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(6);
		ccr_68000_long_move_ae_normal(src);
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	put_word_000(dsta + 2, src); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return 28 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 32 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 32 * CYCLE_UNIT / 2 + count_cycles;
}
/* 32 (5/2) */
/* 6 6,4   */

/* MOVE.L #<data>.L,(d8,An,Xn) */
uae_u32 REGPARAM2 op_21bc_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 26; 
	uae_s32 src;
	src = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	BusCyclePenalty += 2;
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_000_prefetch(8));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 8, 0);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	struct flag_struct oldflags;
	oldflags.cznv = regflags.cznv;
	if (dsta & 1) {
		m68k_incpci(8);
		ccr_68000_long_move_ae_HNZ(src);
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		ccr_68000_long_move_ae_HNZ(src);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	put_word_000(dsta + 2, src); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		ccr_68000_long_move_ae_LZN(src);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return 22 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(8);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 26 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 26 * CYCLE_UNIT / 2 + count_cycles;
}
/* 26 (4/2) */
/* 8 4,0   */

/* MOVE.L Dn,(xxx).W */
uae_u32 REGPARAM2 op_21c0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 30;
	CurrentInstrCycles = 16; 
	uae_s32 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	struct flag_struct oldflags;
	oldflags.cznv = regflags.cznv;
	if (dsta & 1) {
		m68k_incpci(4);
		ccr_68000_long_move_ae_normal(src);
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	put_word_000(dsta + 2, src); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (2/2) */
/* 4 0,0   */

/* MOVE.L An,(xxx).W */
uae_u32 REGPARAM2 op_21c8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 30;
	CurrentInstrCycles = 16; 
	uae_s32 src = m68k_areg(regs, srcreg);
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	struct flag_struct oldflags;
	oldflags.cznv = regflags.cznv;
	if (dsta & 1) {
		m68k_incpci(4);
		ccr_68000_long_move_ae_normal(src);
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	put_word_000(dsta + 2, src); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (2/2) */
/* 4 0,0   */

/* MOVE.L (An),(xxx).W */
uae_u32 REGPARAM2 op_21d0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 30;
	CurrentInstrCycles = 24; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch(opcode, 4, 0);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(4);
		ccr_68000_long_move_ae_normal(src);
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		ccr_68000_long_move_ae_LZN(src);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	put_word_000(dsta + 2, src); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 24 * CYCLE_UNIT / 2 + count_cycles;
}
/* 24 (4/2) */
/* 4 0,0   */

/* MOVE.L (An)+,(xxx).W */
uae_u32 REGPARAM2 op_21d8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 30;
	CurrentInstrCycles = 24; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) += 4;
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch(opcode, 4, 0);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(4);
		ccr_68000_long_move_ae_normal(src);
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		ccr_68000_long_move_ae_LZN(src);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	put_word_000(dsta + 2, src); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 24 * CYCLE_UNIT / 2 + count_cycles;
}
/* 24 (4/2) */
/* 4 0,0   */

/* MOVE.L -(An),(xxx).W */
uae_u32 REGPARAM2 op_21e0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 30;
	CurrentInstrCycles = 26; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - 4;
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return 2 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) = srca;
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch(opcode, 4, 0);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(4);
		ccr_68000_long_move_ae_normal(src);
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		ccr_68000_long_move_ae_LZN(src);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	put_word_000(dsta + 2, src); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return 22 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 26 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 26 * CYCLE_UNIT / 2 + count_cycles;
}
/* 26 (4/2) */
/* 4 0,0   */

/* MOVE.L (d16,An),(xxx).W */
uae_u32 REGPARAM2 op_21e8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 30;
	CurrentInstrCycles = 28; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch(opcode, 6, 0);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(6);
		ccr_68000_long_move_ae_normal(src);
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		ccr_68000_long_move_ae_LZN(src);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	put_word_000(dsta + 2, src); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 28 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 28 * CYCLE_UNIT / 2 + count_cycles;
}
/* 28 (5/2) */
/* 6 0,0   */

/* MOVE.L (d8,An,Xn),(xxx).W */
uae_u32 REGPARAM2 op_21f0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 30;
	CurrentInstrCycles = 30; 
	uaecptr srca;
	BusCyclePenalty += 2;
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch(opcode, 6, 0);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(6);
		ccr_68000_long_move_ae_normal(src);
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		ccr_68000_long_move_ae_LZN(src);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return 22 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	put_word_000(dsta + 2, src); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return 26 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 30 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 30 * CYCLE_UNIT / 2 + count_cycles;
}
/* 30 (5/2) */
/* 6 6,0   */

/* MOVE.L (xxx).W,(xxx).W */
uae_u32 REGPARAM2 op_21f8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 30;
	CurrentInstrCycles = 28; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, srca, 2, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch(opcode, 6, 0);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(6);
		ccr_68000_long_move_ae_normal(src);
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		ccr_68000_long_move_ae_LZN(src);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	put_word_000(dsta + 2, src); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 28 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 28 * CYCLE_UNIT / 2 + count_cycles;
}
/* 28 (5/2) */
/* 6 0,0   */

/* MOVE.L (xxx).L,(xxx).W */
uae_u32 REGPARAM2 op_21f9_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 30;
	CurrentInstrCycles = 32; 
	uaecptr srca;
	srca = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	srca |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, srca, 2, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch(opcode, 8, 0);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(8);
		ccr_68000_long_move_ae_normal(src);
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		ccr_68000_long_move_ae_LZN(src);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	put_word_000(dsta + 2, src); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return 28 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(8);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 32 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 32 * CYCLE_UNIT / 2 + count_cycles;
}
/* 32 (6/2) */
/* 8 0,0   */

/* MOVE.L (d16,PC),(xxx).W */
uae_u32 REGPARAM2 op_21fa_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 30;
	CurrentInstrCycles = 28; 
	uaecptr srca;
	srca = m68k_getpci() + 2;
	srca += (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 2);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch(opcode, 6, 0);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(6);
		ccr_68000_long_move_ae_normal(src);
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		ccr_68000_long_move_ae_LZN(src);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	put_word_000(dsta + 2, src); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 28 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 28 * CYCLE_UNIT / 2 + count_cycles;
}
/* 28 (5/2) */
/* 6 0,0   */

/* MOVE.L (d8,PC,Xn),(xxx).W */
uae_u32 REGPARAM2 op_21fb_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 30;
	CurrentInstrCycles = 30; 
	uaecptr srca;
	uaecptr tmppc = m68k_getpci() + 2;
	BusCyclePenalty += 2;
	srca = get_disp_ea_000(tmppc, get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 2);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch(opcode, 6, 0);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(6);
		ccr_68000_long_move_ae_normal(src);
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		ccr_68000_long_move_ae_LZN(src);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return 22 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	put_word_000(dsta + 2, src); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return 26 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 30 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 30 * CYCLE_UNIT / 2 + count_cycles;
}
/* 30 (5/2) */
/* 6 6,0   */

/* MOVE.L #<data>.L,(xxx).W */
uae_u32 REGPARAM2 op_21fc_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 30;
	CurrentInstrCycles = 24; 
	uae_s32 src;
	src = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch(opcode, 8, 0);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	struct flag_struct oldflags;
	oldflags.cznv = regflags.cznv;
	if (dsta & 1) {
		m68k_incpci(8);
		ccr_68000_long_move_ae_normal(src);
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	put_word_000(dsta + 2, src); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(8);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 24 * CYCLE_UNIT / 2 + count_cycles;
}
/* 24 (4/2) */
/* 8 0,0   */

/* MOVE.L Dn,(xxx).L */
uae_u32 REGPARAM2 op_23c0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 30;
	CurrentInstrCycles = 20; 
	uae_s32 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		// nothing;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	dsta |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	struct flag_struct oldflags;
	oldflags.cznv = regflags.cznv;
	if (dsta & 1) {
		m68k_incpci(6);
		ccr_68000_long_move_ae_normal(src);
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	put_word_000(dsta + 2, src); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (3/2) */
/* 6 0,0   */

/* MOVE.L An,(xxx).L */
uae_u32 REGPARAM2 op_23c8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 30;
	CurrentInstrCycles = 20; 
	uae_s32 src = m68k_areg(regs, srcreg);
	uaecptr dsta;
	dsta = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		// nothing;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	dsta |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	struct flag_struct oldflags;
	oldflags.cznv = regflags.cznv;
	if (dsta & 1) {
		m68k_incpci(6);
		ccr_68000_long_move_ae_normal(src);
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	put_word_000(dsta + 2, src); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (3/2) */
/* 6 0,0   */

/* MOVE.L (An),(xxx).L */
uae_u32 REGPARAM2 op_23d0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 30;
	CurrentInstrCycles = 28; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = get_word_000_prefetch(4) << 16;
	dsta |= regs.irc;
	if(hardware_bus_error) {
		int pcoffset = 0;
		// nothing;
		exception2_fetch(opcode, 4, 0);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(4);
		regs.irc = dsta >> 16;
		ccr_68000_long_move_ae_LZN(src);
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		ccr_68000_long_move_ae_LZN(src);
		regs.irc = dsta >> 16;
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	put_word_000(dsta + 2, src); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		ccr_68000_long_move_ae_normal(src);
		regs.irc = dsta >> 16;
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	get_word_000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, 0);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 28 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 28 * CYCLE_UNIT / 2 + count_cycles;
}
/* 28 (5/2) */
/* 6 0,0   */

/* MOVE.L (An)+,(xxx).L */
uae_u32 REGPARAM2 op_23d8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 30;
	CurrentInstrCycles = 28; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) += 4;
	uaecptr dsta;
	dsta = get_word_000_prefetch(4) << 16;
	dsta |= regs.irc;
	if(hardware_bus_error) {
		int pcoffset = 0;
		// nothing;
		exception2_fetch(opcode, 4, 0);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(4);
		regs.irc = dsta >> 16;
		ccr_68000_long_move_ae_LZN(src);
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		ccr_68000_long_move_ae_LZN(src);
		regs.irc = dsta >> 16;
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	put_word_000(dsta + 2, src); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		ccr_68000_long_move_ae_normal(src);
		regs.irc = dsta >> 16;
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	get_word_000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, 0);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 28 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 28 * CYCLE_UNIT / 2 + count_cycles;
}
/* 28 (5/2) */
/* 6 0,0   */

/* MOVE.L -(An),(xxx).L */
uae_u32 REGPARAM2 op_23e0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 30;
	CurrentInstrCycles = 30; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - 4;
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return 2 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) = srca;
	uaecptr dsta;
	dsta = get_word_000_prefetch(4) << 16;
	dsta |= regs.irc;
	if(hardware_bus_error) {
		int pcoffset = 0;
		// nothing;
		exception2_fetch(opcode, 4, 0);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(4);
		regs.irc = dsta >> 16;
		ccr_68000_long_move_ae_LZN(src);
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		ccr_68000_long_move_ae_LZN(src);
		regs.irc = dsta >> 16;
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	put_word_000(dsta + 2, src); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		ccr_68000_long_move_ae_normal(src);
		regs.irc = dsta >> 16;
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return 22 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	get_word_000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, 0);
		return 26 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 30 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 30 * CYCLE_UNIT / 2 + count_cycles;
}
/* 30 (5/2) */
/* 6 0,0   */

/* MOVE.L (d16,An),(xxx).L */
uae_u32 REGPARAM2 op_23e8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 30;
	CurrentInstrCycles = 32; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = get_word_000_prefetch(6) << 16;
	dsta |= regs.irc;
	if(hardware_bus_error) {
		int pcoffset = 0;
		// nothing;
		exception2_fetch(opcode, 6, 0);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(6);
		regs.irc = dsta >> 16;
		ccr_68000_long_move_ae_LZN(src);
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		ccr_68000_long_move_ae_LZN(src);
		regs.irc = dsta >> 16;
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	put_word_000(dsta + 2, src); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		ccr_68000_long_move_ae_normal(src);
		regs.irc = dsta >> 16;
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(8);
	get_word_000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, 0);
		return 28 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 32 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 32 * CYCLE_UNIT / 2 + count_cycles;
}
/* 32 (6/2) */
/* 8 0,0   */

/* MOVE.L (d8,An,Xn),(xxx).L */
uae_u32 REGPARAM2 op_23f0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 30;
	CurrentInstrCycles = 34; 
	uaecptr srca;
	BusCyclePenalty += 2;
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = get_word_000_prefetch(6) << 16;
	dsta |= regs.irc;
	if(hardware_bus_error) {
		int pcoffset = 0;
		// nothing;
		exception2_fetch(opcode, 6, 0);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(6);
		regs.irc = dsta >> 16;
		ccr_68000_long_move_ae_LZN(src);
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		ccr_68000_long_move_ae_LZN(src);
		regs.irc = dsta >> 16;
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return 22 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	put_word_000(dsta + 2, src); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		ccr_68000_long_move_ae_normal(src);
		regs.irc = dsta >> 16;
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return 26 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(8);
	get_word_000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, 0);
		return 30 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 34 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 34 * CYCLE_UNIT / 2 + count_cycles;
}
/* 34 (6/2) */
/* 8 8,0   */

/* MOVE.L (xxx).W,(xxx).L */
uae_u32 REGPARAM2 op_23f8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 30;
	CurrentInstrCycles = 32; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, srca, 2, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = get_word_000_prefetch(6) << 16;
	dsta |= regs.irc;
	if(hardware_bus_error) {
		int pcoffset = 0;
		// nothing;
		exception2_fetch(opcode, 6, 0);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(6);
		regs.irc = dsta >> 16;
		ccr_68000_long_move_ae_LZN(src);
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		ccr_68000_long_move_ae_LZN(src);
		regs.irc = dsta >> 16;
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	put_word_000(dsta + 2, src); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		ccr_68000_long_move_ae_normal(src);
		regs.irc = dsta >> 16;
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(8);
	get_word_000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, 0);
		return 28 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 32 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 32 * CYCLE_UNIT / 2 + count_cycles;
}
/* 32 (6/2) */
/* 8 0,0   */

/* MOVE.L (xxx).L,(xxx).L */
uae_u32 REGPARAM2 op_23f9_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 30;
	CurrentInstrCycles = 36; 
	uaecptr srca;
	srca = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	srca |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, srca, 2, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = get_word_000_prefetch(8) << 16;
	dsta |= regs.irc;
	if(hardware_bus_error) {
		int pcoffset = 0;
		// nothing;
		exception2_fetch(opcode, 8, 0);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(8);
		regs.irc = dsta >> 16;
		ccr_68000_long_move_ae_LZN(src);
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		ccr_68000_long_move_ae_LZN(src);
		regs.irc = dsta >> 16;
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	put_word_000(dsta + 2, src); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		ccr_68000_long_move_ae_normal(src);
		regs.irc = dsta >> 16;
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return 28 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(10);
	get_word_000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, 0);
		return 32 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 36 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 36 * CYCLE_UNIT / 2 + count_cycles;
}
/* 36 (7/2) */
/* 10 0,0   */

/* MOVE.L (d16,PC),(xxx).L */
uae_u32 REGPARAM2 op_23fa_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 30;
	CurrentInstrCycles = 32; 
	uaecptr srca;
	srca = m68k_getpci() + 2;
	srca += (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 2);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = get_word_000_prefetch(6) << 16;
	dsta |= regs.irc;
	if(hardware_bus_error) {
		int pcoffset = 0;
		// nothing;
		exception2_fetch(opcode, 6, 0);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(6);
		regs.irc = dsta >> 16;
		ccr_68000_long_move_ae_LZN(src);
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		ccr_68000_long_move_ae_LZN(src);
		regs.irc = dsta >> 16;
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	put_word_000(dsta + 2, src); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		ccr_68000_long_move_ae_normal(src);
		regs.irc = dsta >> 16;
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(8);
	get_word_000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, 0);
		return 28 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 32 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 32 * CYCLE_UNIT / 2 + count_cycles;
}
/* 32 (6/2) */
/* 8 0,0   */

/* MOVE.L (d8,PC,Xn),(xxx).L */
uae_u32 REGPARAM2 op_23fb_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 30;
	CurrentInstrCycles = 34; 
	uaecptr srca;
	uaecptr tmppc = m68k_getpci() + 2;
	BusCyclePenalty += 2;
	srca = get_disp_ea_000(tmppc, get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 2);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = get_word_000_prefetch(6) << 16;
	dsta |= regs.irc;
	if(hardware_bus_error) {
		int pcoffset = 0;
		// nothing;
		exception2_fetch(opcode, 6, 0);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(6);
		regs.irc = dsta >> 16;
		ccr_68000_long_move_ae_LZN(src);
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		ccr_68000_long_move_ae_LZN(src);
		regs.irc = dsta >> 16;
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return 22 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	put_word_000(dsta + 2, src); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		ccr_68000_long_move_ae_normal(src);
		regs.irc = dsta >> 16;
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return 26 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(8);
	get_word_000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, 0);
		return 30 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 34 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 34 * CYCLE_UNIT / 2 + count_cycles;
}
/* 34 (6/2) */
/* 8 8,0   */

/* MOVE.L #<data>.L,(xxx).L */
uae_u32 REGPARAM2 op_23fc_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 30;
	CurrentInstrCycles = 28; 
	uae_s32 src;
	src = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = get_word_000_prefetch(8) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 8, -2);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	dsta |= get_word_000_prefetch(10);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch(opcode, 10, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	struct flag_struct oldflags;
	oldflags.cznv = regflags.cznv;
	if (dsta & 1) {
		m68k_incpci(10);
		ccr_68000_long_move_ae_normal(src);
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(10);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	put_word_000(dsta + 2, src); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(10);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(10);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 28 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 28 * CYCLE_UNIT / 2 + count_cycles;
}
/* 28 (5/2) */
/* 10 0,0   */

/* MOVE.W Dn,Dn */
uae_u32 REGPARAM2 op_3000_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 4;  
	uae_s16 src = m68k_dreg(regs, srcreg);
	struct flag_struct oldflags;
	oldflags.cznv = regflags.cznv;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
	m68k_incpci(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 4 * CYCLE_UNIT / 2 + count_cycles;
}
/* 4 (1/0) */
/* 2 0,0   */

/* MOVE.W An,Dn */
uae_u32 REGPARAM2 op_3008_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 4;  
	uae_s16 src = m68k_areg(regs, srcreg);
	struct flag_struct oldflags;
	oldflags.cznv = regflags.cznv;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
	m68k_incpci(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 4 * CYCLE_UNIT / 2 + count_cycles;
}
/* 4 (1/0) */
/* 2 0,0   */

/* MOVE.W (An),Dn */
uae_u32 REGPARAM2 op_3010_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 8;  
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access2(opcode, srca, 1, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
	m68k_incpci(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8 (2/0) */
/* 2 0,0   */

/* MOVE.W (An)+,Dn */
uae_u32 REGPARAM2 op_3018_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 8;  
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_areg(regs, srcreg) += 2 + 0;
		m68k_incpci(2);
		exception3_read_access2(opcode, srca, 1, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) += 2 + 0;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) += 2;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
	m68k_incpci(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8 (2/0) */
/* 2 0,0   */

/* MOVE.W -(An),Dn */
uae_u32 REGPARAM2 op_3020_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 10; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - 2;
	if (srca & 1) {
		m68k_areg(regs, srcreg) = srca;
		m68k_incpci(2);
		exception3_read_access2(opcode, srca, 1, 1);
		return 2 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) = srca;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
	m68k_incpci(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 10 * CYCLE_UNIT / 2 + count_cycles;
}
/* 10 (2/0) */
/* 2 0,0   */

/* MOVE.W (d16,An),Dn */
uae_u32 REGPARAM2 op_3028_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (3/0) */
/* 4 0,0   */

/* MOVE.W (d8,An,Xn),Dn */
uae_u32 REGPARAM2 op_3030_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	BusCyclePenalty += 2;
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 14 * CYCLE_UNIT / 2 + count_cycles;
}
/* 14 (3/0) */
/* 4 4,0   */

/* MOVE.W (xxx).W,Dn */
uae_u32 REGPARAM2 op_3038_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, srca, 1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (3/0) */
/* 4 0,0   */

/* MOVE.W (xxx).L,Dn */
uae_u32 REGPARAM2 op_3039_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	srca |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, srca, 1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (4/0) */
/* 6 0,0   */

/* MOVE.W (d16,PC),Dn */
uae_u32 REGPARAM2 op_303a_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_getpci() + 2;
	srca += (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (3/0) */
/* 4 0,0   */

/* MOVE.W (d8,PC,Xn),Dn */
uae_u32 REGPARAM2 op_303b_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	uaecptr tmppc = m68k_getpci() + 2;
	BusCyclePenalty += 2;
	srca = get_disp_ea_000(tmppc, get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 14 * CYCLE_UNIT / 2 + count_cycles;
}
/* 14 (3/0) */
/* 4 4,0   */

/* MOVE.W #<data>.W,Dn */
uae_u32 REGPARAM2 op_303c_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 8;  
	uae_s16 src = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	struct flag_struct oldflags;
	oldflags.cznv = regflags.cznv;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8 (2/0) */
/* 4 0,0   */

/* MOVEA.W Dn,An */
uae_u32 REGPARAM2 op_3040_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 31;
	CurrentInstrCycles = 4;  
	uae_s16 src = m68k_dreg(regs, srcreg);
	src = (uae_s32)(uae_s16)src;
	m68k_areg(regs, dstreg) = (uae_s32)(uae_s16)(src);
	m68k_incpci(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 4 * CYCLE_UNIT / 2 + count_cycles;
}
/* 4 (1/0) */
/* 2 0,0   */

/* MOVEA.W An,An */
uae_u32 REGPARAM2 op_3048_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 31;
	CurrentInstrCycles = 4;  
	uae_s16 src = m68k_areg(regs, srcreg);
	src = (uae_s32)(uae_s16)src;
	m68k_areg(regs, dstreg) = (uae_s32)(uae_s16)(src);
	m68k_incpci(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 4 * CYCLE_UNIT / 2 + count_cycles;
}
/* 4 (1/0) */
/* 2 0,0   */

/* MOVEA.W (An),An */
uae_u32 REGPARAM2 op_3050_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 31;
	CurrentInstrCycles = 8;  
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access2(opcode, srca, 1, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	src = (uae_s32)(uae_s16)src;
	m68k_areg(regs, dstreg) = (uae_s32)(uae_s16)(src);
	m68k_incpci(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8 (2/0) */
/* 2 0,0   */

/* MOVEA.W (An)+,An */
uae_u32 REGPARAM2 op_3058_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 31;
	CurrentInstrCycles = 8;  
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_areg(regs, srcreg) += 2 + 0;
		m68k_incpci(2);
		exception3_read_access2(opcode, srca, 1, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) += 2 + 0;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) += 2;
	src = (uae_s32)(uae_s16)src;
	m68k_areg(regs, dstreg) = (uae_s32)(uae_s16)(src);
	m68k_incpci(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8 (2/0) */
/* 2 0,0   */

/* MOVEA.W -(An),An */
uae_u32 REGPARAM2 op_3060_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 31;
	CurrentInstrCycles = 10; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - 2;
	if (srca & 1) {
		m68k_areg(regs, srcreg) = srca;
		m68k_incpci(2);
		exception3_read_access2(opcode, srca, 1, 1);
		return 2 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) = srca;
	src = (uae_s32)(uae_s16)src;
	m68k_areg(regs, dstreg) = (uae_s32)(uae_s16)(src);
	m68k_incpci(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 10 * CYCLE_UNIT / 2 + count_cycles;
}
/* 10 (2/0) */
/* 2 0,0   */

/* MOVEA.W (d16,An),An */
uae_u32 REGPARAM2 op_3068_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 31;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	src = (uae_s32)(uae_s16)src;
	m68k_areg(regs, dstreg) = (uae_s32)(uae_s16)(src);
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (3/0) */
/* 4 0,0   */

/* MOVEA.W (d8,An,Xn),An */
uae_u32 REGPARAM2 op_3070_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 31;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	BusCyclePenalty += 2;
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	src = (uae_s32)(uae_s16)src;
	m68k_areg(regs, dstreg) = (uae_s32)(uae_s16)(src);
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 14 * CYCLE_UNIT / 2 + count_cycles;
}
/* 14 (3/0) */
/* 4 4,0   */

/* MOVEA.W (xxx).W,An */
uae_u32 REGPARAM2 op_3078_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 31;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, srca, 1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	src = (uae_s32)(uae_s16)src;
	m68k_areg(regs, dstreg) = (uae_s32)(uae_s16)(src);
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (3/0) */
/* 4 0,0   */

/* MOVEA.W (xxx).L,An */
uae_u32 REGPARAM2 op_3079_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 31;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	srca |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, srca, 1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	src = (uae_s32)(uae_s16)src;
	m68k_areg(regs, dstreg) = (uae_s32)(uae_s16)(src);
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (4/0) */
/* 6 0,0   */

/* MOVEA.W (d16,PC),An */
uae_u32 REGPARAM2 op_307a_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 31;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_getpci() + 2;
	srca += (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	src = (uae_s32)(uae_s16)src;
	m68k_areg(regs, dstreg) = (uae_s32)(uae_s16)(src);
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (3/0) */
/* 4 0,0   */

/* MOVEA.W (d8,PC,Xn),An */
uae_u32 REGPARAM2 op_307b_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 31;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	uaecptr tmppc = m68k_getpci() + 2;
	BusCyclePenalty += 2;
	srca = get_disp_ea_000(tmppc, get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	src = (uae_s32)(uae_s16)src;
	m68k_areg(regs, dstreg) = (uae_s32)(uae_s16)(src);
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 14 * CYCLE_UNIT / 2 + count_cycles;
}
/* 14 (3/0) */
/* 4 4,0   */

/* MOVEA.W #<data>.W,An */
uae_u32 REGPARAM2 op_307c_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 31;
	CurrentInstrCycles = 8;  
	uae_s16 src = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	src = (uae_s32)(uae_s16)src;
	m68k_areg(regs, dstreg) = (uae_s32)(uae_s16)(src);
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8 (2/0) */
/* 4 0,0   */

/* MOVE.W Dn,(An) */
uae_u32 REGPARAM2 op_3080_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 4;  
	int loop_mode = regs.loop_mode;
	uae_s16 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	struct flag_struct oldflags;
	oldflags.cznv = regflags.cznv;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(4);
		regflags.cznv = oldflags.cznv;
		exception3_write_access(opcode, dsta, 1, src, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	if(!loop_mode) {
		regs.ir = regs.irc;
		opcode = regs.ir;
		get_word_000_prefetch(2);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 2, pcoffset);
			return 4 * CYCLE_UNIT / 2 + count_cycles;
		}
	} else {
		loop_mode = 0;
		loop_mode |= 2;
		loop_mode |= 4 << 16;
	}
	regs.loop_mode = loop_mode;
	return 4 * CYCLE_UNIT / 2 + count_cycles;
}
/* 4+ (0/1) */
/* 2 0,0   */

/* MOVE.W An,(An) */
uae_u32 REGPARAM2 op_3088_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 4;  
	int loop_mode = regs.loop_mode;
	uae_s16 src = m68k_areg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	struct flag_struct oldflags;
	oldflags.cznv = regflags.cznv;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(4);
		regflags.cznv = oldflags.cznv;
		exception3_write_access(opcode, dsta, 1, src, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	if(!loop_mode) {
		regs.ir = regs.irc;
		opcode = regs.ir;
		get_word_000_prefetch(2);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 2, pcoffset);
			return 4 * CYCLE_UNIT / 2 + count_cycles;
		}
	} else {
		loop_mode = 0;
		loop_mode |= 2;
		loop_mode |= 4 << 16;
	}
	regs.loop_mode = loop_mode;
	return 4 * CYCLE_UNIT / 2 + count_cycles;
}
/* 4+ (0/1) */
/* 2 0,0   */

/* MOVE.W (An),(An) */
uae_u32 REGPARAM2 op_3090_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 8;  
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access2(opcode, srca, 1, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(4);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		exception3_write_access(opcode, dsta, 1, src, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	if(!loop_mode) {
		regs.ir = regs.irc;
		opcode = regs.ir;
		get_word_000_prefetch(2);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 2, pcoffset);
			return 8 * CYCLE_UNIT / 2 + count_cycles;
		}
	} else {
		loop_mode = 0;
		loop_mode |= 2;
		loop_mode |= 2 << 16;
	}
	regs.loop_mode = loop_mode;
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8+ (1/1) */
/* 2 0,0   */

/* MOVE.W (An)+,(An) */
uae_u32 REGPARAM2 op_3098_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 8;  
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_areg(regs, srcreg) += 2 + 0;
		m68k_incpci(2);
		exception3_read_access2(opcode, srca, 1, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) += 2 + 0;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) += 2;
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(4);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		exception3_write_access(opcode, dsta, 1, src, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	if(!loop_mode) {
		regs.ir = regs.irc;
		opcode = regs.ir;
		get_word_000_prefetch(2);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 2, pcoffset);
			return 8 * CYCLE_UNIT / 2 + count_cycles;
		}
	} else {
		loop_mode = 0;
		loop_mode |= 2;
		loop_mode |= 2 << 16;
	}
	regs.loop_mode = loop_mode;
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8+ (1/1) */
/* 2 0,0   */

/* MOVE.W -(An),(An) */
uae_u32 REGPARAM2 op_30a0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 10; 
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - 2;
	if (srca & 1) {
		m68k_areg(regs, srcreg) = srca;
		m68k_incpci(2);
		exception3_read_access2(opcode, srca, 1, 1);
		return 2 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) = srca;
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(4);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		exception3_write_access(opcode, dsta, 1, src, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	if(!loop_mode) {
		regs.ir = regs.irc;
		opcode = regs.ir;
		get_word_000_prefetch(2);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 2, pcoffset);
			return 10 * CYCLE_UNIT / 2 + count_cycles;
		}
	} else {
		loop_mode = 0;
		loop_mode |= 2;
		loop_mode |= 2 << 16;
	}
	regs.loop_mode = loop_mode;
	return 10 * CYCLE_UNIT / 2 + count_cycles;
}
/* 10+ (1/1) */
/* 2 0,0   */

/* MOVE.W (d16,An),(An) */
uae_u32 REGPARAM2 op_30a8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(6);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		exception3_write_access(opcode, dsta, 1, src, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 4 0,0   */

/* MOVE.W (d8,An,Xn),(An) */
uae_u32 REGPARAM2 op_30b0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	BusCyclePenalty += 2;
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(6);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		exception3_write_access(opcode, dsta, 1, src, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (3/1) */
/* 4 4,0   */

/* MOVE.W (xxx).W,(An) */
uae_u32 REGPARAM2 op_30b8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, srca, 1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(6);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		exception3_write_access(opcode, dsta, 1, src, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 4 0,0   */

/* MOVE.W (xxx).L,(An) */
uae_u32 REGPARAM2 op_30b9_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	srca = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	srca |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, srca, 1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(8);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		exception3_write_access(opcode, dsta, 1, src, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (4/1) */
/* 6 0,0   */

/* MOVE.W (d16,PC),(An) */
uae_u32 REGPARAM2 op_30ba_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = m68k_getpci() + 2;
	srca += (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(6);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		exception3_write_access(opcode, dsta, 1, src, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 4 0,0   */

/* MOVE.W (d8,PC,Xn),(An) */
uae_u32 REGPARAM2 op_30bb_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	uaecptr tmppc = m68k_getpci() + 2;
	BusCyclePenalty += 2;
	srca = get_disp_ea_000(tmppc, get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(6);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		exception3_write_access(opcode, dsta, 1, src, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (3/1) */
/* 4 4,0   */

/* MOVE.W #<data>.W,(An) */
uae_u32 REGPARAM2 op_30bc_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 12; 
	uae_s16 src = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	struct flag_struct oldflags;
	oldflags.cznv = regflags.cznv;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(6);
		regflags.cznv = oldflags.cznv;
		exception3_write_access(opcode, dsta, 1, src, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (2/1) */
/* 4 0,0   */

/* MOVE.W Dn,(An)+ */
uae_u32 REGPARAM2 op_30c0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 4;  
	int loop_mode = regs.loop_mode;
	uae_s16 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	m68k_areg(regs, dstreg) += 2;
	struct flag_struct oldflags;
	oldflags.cznv = regflags.cznv;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(4);
		regflags.cznv = oldflags.cznv;
		m68k_areg(regs, dstreg) = dsta;
		exception3_write_access(opcode, dsta, 1, src, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, dstreg) -= 2;
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	if(!loop_mode) {
		regs.ir = regs.irc;
		opcode = regs.ir;
		get_word_000_prefetch(2);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 2, pcoffset);
			return 4 * CYCLE_UNIT / 2 + count_cycles;
		}
	} else {
		loop_mode = 0;
		loop_mode |= 2;
		loop_mode |= 4 << 16;
	}
	regs.loop_mode = loop_mode;
	return 4 * CYCLE_UNIT / 2 + count_cycles;
}
/* 4+ (0/1) */
/* 2 0,0   */

/* MOVE.W An,(An)+ */
uae_u32 REGPARAM2 op_30c8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 4;  
	int loop_mode = regs.loop_mode;
	uae_s16 src = m68k_areg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	m68k_areg(regs, dstreg) += 2;
	struct flag_struct oldflags;
	oldflags.cznv = regflags.cznv;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(4);
		regflags.cznv = oldflags.cznv;
		m68k_areg(regs, dstreg) = dsta;
		exception3_write_access(opcode, dsta, 1, src, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, dstreg) -= 2;
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	if(!loop_mode) {
		regs.ir = regs.irc;
		opcode = regs.ir;
		get_word_000_prefetch(2);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 2, pcoffset);
			return 4 * CYCLE_UNIT / 2 + count_cycles;
		}
	} else {
		loop_mode = 0;
		loop_mode |= 2;
		loop_mode |= 4 << 16;
	}
	regs.loop_mode = loop_mode;
	return 4 * CYCLE_UNIT / 2 + count_cycles;
}
/* 4+ (0/1) */
/* 2 0,0   */

/* MOVE.W (An),(An)+ */
uae_u32 REGPARAM2 op_30d0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 8;  
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access2(opcode, srca, 1, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	m68k_areg(regs, dstreg) += 2;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(4);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		m68k_areg(regs, dstreg) = dsta;
		exception3_write_access(opcode, dsta, 1, src, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, dstreg) -= 2;
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	if(!loop_mode) {
		regs.ir = regs.irc;
		opcode = regs.ir;
		get_word_000_prefetch(2);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 2, pcoffset);
			return 8 * CYCLE_UNIT / 2 + count_cycles;
		}
	} else {
		loop_mode = 0;
		loop_mode |= 2;
		loop_mode |= 2 << 16;
	}
	regs.loop_mode = loop_mode;
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8+ (1/1) */
/* 2 0,0   */

/* MOVE.W (An)+,(An)+ */
uae_u32 REGPARAM2 op_30d8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 8;  
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_areg(regs, srcreg) += 2 + 0;
		m68k_incpci(2);
		exception3_read_access2(opcode, srca, 1, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) += 2 + 0;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) += 2;
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	m68k_areg(regs, dstreg) += 2;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(4);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		m68k_areg(regs, dstreg) = dsta;
		exception3_write_access(opcode, dsta, 1, src, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, dstreg) -= 2;
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	if(!loop_mode) {
		regs.ir = regs.irc;
		opcode = regs.ir;
		get_word_000_prefetch(2);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 2, pcoffset);
			return 8 * CYCLE_UNIT / 2 + count_cycles;
		}
	} else {
		loop_mode = 0;
		loop_mode |= 2;
		loop_mode |= 2 << 16;
	}
	regs.loop_mode = loop_mode;
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8+ (1/1) */
/* 2 0,0   */

/* MOVE.W -(An),(An)+ */
uae_u32 REGPARAM2 op_30e0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 10; 
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - 2;
	if (srca & 1) {
		m68k_areg(regs, srcreg) = srca;
		m68k_incpci(2);
		exception3_read_access2(opcode, srca, 1, 1);
		return 2 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) = srca;
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	m68k_areg(regs, dstreg) += 2;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(4);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		m68k_areg(regs, dstreg) = dsta;
		exception3_write_access(opcode, dsta, 1, src, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, dstreg) -= 2;
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	if(!loop_mode) {
		regs.ir = regs.irc;
		opcode = regs.ir;
		get_word_000_prefetch(2);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 2, pcoffset);
			return 10 * CYCLE_UNIT / 2 + count_cycles;
		}
	} else {
		loop_mode = 0;
		loop_mode |= 2;
		loop_mode |= 2 << 16;
	}
	regs.loop_mode = loop_mode;
	return 10 * CYCLE_UNIT / 2 + count_cycles;
}
/* 10+ (1/1) */
/* 2 0,0   */

/* MOVE.W (d16,An),(An)+ */
uae_u32 REGPARAM2 op_30e8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	m68k_areg(regs, dstreg) += 2;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(6);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		m68k_areg(regs, dstreg) = dsta;
		exception3_write_access(opcode, dsta, 1, src, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, dstreg) -= 2;
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 4 0,0   */

/* MOVE.W (d8,An,Xn),(An)+ */
uae_u32 REGPARAM2 op_30f0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	BusCyclePenalty += 2;
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	m68k_areg(regs, dstreg) += 2;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(6);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		m68k_areg(regs, dstreg) = dsta;
		exception3_write_access(opcode, dsta, 1, src, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, dstreg) -= 2;
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (3/1) */
/* 4 4,0   */

/* MOVE.W (xxx).W,(An)+ */
uae_u32 REGPARAM2 op_30f8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, srca, 1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	m68k_areg(regs, dstreg) += 2;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(6);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		m68k_areg(regs, dstreg) = dsta;
		exception3_write_access(opcode, dsta, 1, src, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, dstreg) -= 2;
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 4 0,0   */

/* MOVE.W (xxx).L,(An)+ */
uae_u32 REGPARAM2 op_30f9_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	srca = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	srca |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, srca, 1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	m68k_areg(regs, dstreg) += 2;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(8);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		m68k_areg(regs, dstreg) = dsta;
		exception3_write_access(opcode, dsta, 1, src, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		m68k_areg(regs, dstreg) -= 2;
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (4/1) */
/* 6 0,0   */

/* MOVE.W (d16,PC),(An)+ */
uae_u32 REGPARAM2 op_30fa_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = m68k_getpci() + 2;
	srca += (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	m68k_areg(regs, dstreg) += 2;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(6);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		m68k_areg(regs, dstreg) = dsta;
		exception3_write_access(opcode, dsta, 1, src, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, dstreg) -= 2;
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 4 0,0   */

/* MOVE.W (d8,PC,Xn),(An)+ */
uae_u32 REGPARAM2 op_30fb_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	uaecptr tmppc = m68k_getpci() + 2;
	BusCyclePenalty += 2;
	srca = get_disp_ea_000(tmppc, get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	m68k_areg(regs, dstreg) += 2;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(6);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		m68k_areg(regs, dstreg) = dsta;
		exception3_write_access(opcode, dsta, 1, src, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, dstreg) -= 2;
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (3/1) */
/* 4 4,0   */

/* MOVE.W #<data>.W,(An)+ */
uae_u32 REGPARAM2 op_30fc_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 12; 
	uae_s16 src = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	m68k_areg(regs, dstreg) += 2;
	struct flag_struct oldflags;
	oldflags.cznv = regflags.cznv;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(6);
		regflags.cznv = oldflags.cznv;
		m68k_areg(regs, dstreg) = dsta;
		exception3_write_access(opcode, dsta, 1, src, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, dstreg) -= 2;
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (2/1) */
/* 4 0,0   */

/* MOVE.W Dn,-(An) */
uae_u32 REGPARAM2 op_3100_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 8;  
	uae_s16 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - 2;
	m68k_areg(regs, dstreg) = dsta;
	regs.ir = regs.irc;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		m68k_areg(regs, dstreg) += 2;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	struct flag_struct oldflags;
	oldflags.cznv = regflags.cznv;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_areg(regs, dstreg) = dsta;
		m68k_incpci(4);
		get_word_000_prefetch((m68k_getpci() & 1) ? -1 : 0);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		m68k_areg(regs, dstreg) = dsta;
		exception3_write_access(opcode, dsta, 1, src, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8 (1/1) */
/* 2 0,0   */

/* MOVE.W An,-(An) */
uae_u32 REGPARAM2 op_3108_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 8;  
	uae_s16 src = m68k_areg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - 2;
	m68k_areg(regs, dstreg) = dsta;
	regs.ir = regs.irc;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		m68k_areg(regs, dstreg) += 2;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	struct flag_struct oldflags;
	oldflags.cznv = regflags.cznv;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_areg(regs, dstreg) = dsta;
		m68k_incpci(4);
		get_word_000_prefetch((m68k_getpci() & 1) ? -1 : 0);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		m68k_areg(regs, dstreg) = dsta;
		exception3_write_access(opcode, dsta, 1, src, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8 (1/1) */
/* 2 0,0   */

/* MOVE.W (An),-(An) */
uae_u32 REGPARAM2 op_3110_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 8;  
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access2(opcode, srca, 1, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - 2;
	m68k_areg(regs, dstreg) = dsta;
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_000_prefetch(4);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			int pcoffset = 0;
			m68k_areg(regs, dstreg) += 2;
			ccr_68000_word_move_ae_normal((uae_s16)src);
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return 4 * CYCLE_UNIT / 2 + count_cycles;
		}
		opcode = regs.ir;
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if(loop_mode & 0xfffe) {
		count_cycles += (loop_mode & 0xfffe) * CYCLE_UNIT / 2;
		loop_mode = 1;
	}
	if (dsta & 1) {
		m68k_areg(regs, dstreg) = dsta;
		m68k_incpci(4);
		get_word_000_prefetch((m68k_getpci() & 1) ? -1 : 0);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		m68k_areg(regs, dstreg) = dsta;
		exception3_write_access(opcode, dsta, 1, src, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	regs.loop_mode = loop_mode;
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8+ (1/1) */
/* 2 0,0   */

/* MOVE.W (An)+,-(An) */
uae_u32 REGPARAM2 op_3118_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 8;  
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_areg(regs, srcreg) += 2 + 0;
		m68k_incpci(2);
		exception3_read_access2(opcode, srca, 1, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) += 2 + 0;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) += 2;
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - 2;
	m68k_areg(regs, dstreg) = dsta;
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_000_prefetch(4);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			int pcoffset = 0;
			m68k_areg(regs, dstreg) += 2;
			ccr_68000_word_move_ae_normal((uae_s16)src);
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return 4 * CYCLE_UNIT / 2 + count_cycles;
		}
		opcode = regs.ir;
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if(loop_mode & 0xfffe) {
		count_cycles += (loop_mode & 0xfffe) * CYCLE_UNIT / 2;
		loop_mode = 1;
	}
	if (dsta & 1) {
		m68k_areg(regs, dstreg) = dsta;
		m68k_incpci(4);
		get_word_000_prefetch((m68k_getpci() & 1) ? -1 : 0);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		m68k_areg(regs, dstreg) = dsta;
		exception3_write_access(opcode, dsta, 1, src, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	regs.loop_mode = loop_mode;
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8+ (1/1) */
/* 2 0,0   */

/* MOVE.W -(An),-(An) */
uae_u32 REGPARAM2 op_3120_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 10; 
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - 2;
	if (srca & 1) {
		m68k_areg(regs, srcreg) = srca;
		m68k_incpci(2);
		exception3_read_access2(opcode, srca, 1, 1);
		return 2 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) = srca;
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - 2;
	m68k_areg(regs, dstreg) = dsta;
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_000_prefetch(4);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			int pcoffset = 0;
			m68k_areg(regs, dstreg) += 2;
			ccr_68000_word_move_ae_normal((uae_s16)src);
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return 6 * CYCLE_UNIT / 2 + count_cycles;
		}
		opcode = regs.ir;
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if(loop_mode & 0xfffe) {
		count_cycles += (loop_mode & 0xfffe) * CYCLE_UNIT / 2;
		loop_mode = 1;
	}
	if (dsta & 1) {
		m68k_areg(regs, dstreg) = dsta;
		m68k_incpci(4);
		get_word_000_prefetch((m68k_getpci() & 1) ? -1 : 0);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		m68k_areg(regs, dstreg) = dsta;
		exception3_write_access(opcode, dsta, 1, src, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	regs.loop_mode = loop_mode;
	return 10 * CYCLE_UNIT / 2 + count_cycles;
}
/* 10+ (1/1) */
/* 2 0,0   */

/* MOVE.W (d16,An),-(An) */
uae_u32 REGPARAM2 op_3128_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - 2;
	m68k_areg(regs, dstreg) = dsta;
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		m68k_areg(regs, dstreg) += 2;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_areg(regs, dstreg) = dsta;
		m68k_incpci(6);
		get_word_000_prefetch((m68k_getpci() & 1) ? -1 : 0);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		m68k_areg(regs, dstreg) = dsta;
		exception3_write_access(opcode, dsta, 1, src, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 4 0,0   */

/* MOVE.W (d8,An,Xn),-(An) */
uae_u32 REGPARAM2 op_3130_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	BusCyclePenalty += 2;
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - 2;
	m68k_areg(regs, dstreg) = dsta;
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		m68k_areg(regs, dstreg) += 2;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_areg(regs, dstreg) = dsta;
		m68k_incpci(6);
		get_word_000_prefetch((m68k_getpci() & 1) ? -1 : 0);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		m68k_areg(regs, dstreg) = dsta;
		exception3_write_access(opcode, dsta, 1, src, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (3/1) */
/* 4 4,0   */

/* MOVE.W (xxx).W,-(An) */
uae_u32 REGPARAM2 op_3138_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, srca, 1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - 2;
	m68k_areg(regs, dstreg) = dsta;
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		m68k_areg(regs, dstreg) += 2;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_areg(regs, dstreg) = dsta;
		m68k_incpci(6);
		get_word_000_prefetch((m68k_getpci() & 1) ? -1 : 0);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		m68k_areg(regs, dstreg) = dsta;
		exception3_write_access(opcode, dsta, 1, src, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 4 0,0   */

/* MOVE.W (xxx).L,-(An) */
uae_u32 REGPARAM2 op_3139_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	srca = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	srca |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, srca, 1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - 2;
	m68k_areg(regs, dstreg) = dsta;
	regs.ir = regs.irc;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		m68k_areg(regs, dstreg) += 2;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_areg(regs, dstreg) = dsta;
		m68k_incpci(8);
		get_word_000_prefetch((m68k_getpci() & 1) ? -1 : 0);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		m68k_areg(regs, dstreg) = dsta;
		exception3_write_access(opcode, dsta, 1, src, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (4/1) */
/* 6 0,0   */

/* MOVE.W (d16,PC),-(An) */
uae_u32 REGPARAM2 op_313a_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = m68k_getpci() + 2;
	srca += (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - 2;
	m68k_areg(regs, dstreg) = dsta;
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		m68k_areg(regs, dstreg) += 2;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_areg(regs, dstreg) = dsta;
		m68k_incpci(6);
		get_word_000_prefetch((m68k_getpci() & 1) ? -1 : 0);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		m68k_areg(regs, dstreg) = dsta;
		exception3_write_access(opcode, dsta, 1, src, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 4 0,0   */

/* MOVE.W (d8,PC,Xn),-(An) */
uae_u32 REGPARAM2 op_313b_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	uaecptr tmppc = m68k_getpci() + 2;
	BusCyclePenalty += 2;
	srca = get_disp_ea_000(tmppc, get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - 2;
	m68k_areg(regs, dstreg) = dsta;
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		m68k_areg(regs, dstreg) += 2;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_areg(regs, dstreg) = dsta;
		m68k_incpci(6);
		get_word_000_prefetch((m68k_getpci() & 1) ? -1 : 0);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		m68k_areg(regs, dstreg) = dsta;
		exception3_write_access(opcode, dsta, 1, src, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (3/1) */
/* 4 4,0   */

/* MOVE.W #<data>.W,-(An) */
uae_u32 REGPARAM2 op_313c_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 12; 
	uae_s16 src = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - 2;
	m68k_areg(regs, dstreg) = dsta;
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		m68k_areg(regs, dstreg) += 2;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	struct flag_struct oldflags;
	oldflags.cznv = regflags.cznv;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_areg(regs, dstreg) = dsta;
		m68k_incpci(6);
		get_word_000_prefetch((m68k_getpci() & 1) ? -1 : 0);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		m68k_areg(regs, dstreg) = dsta;
		exception3_write_access(opcode, dsta, 1, src, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (2/1) */
/* 4 0,0   */

/* MOVE.W Dn,(d16,An) */
uae_u32 REGPARAM2 op_3140_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 12; 
	uae_s16 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	struct flag_struct oldflags;
	oldflags.cznv = regflags.cznv;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(4);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		exception3_write_access(opcode, dsta, 1, src, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (2/1) */
/* 4 0,0   */

/* MOVE.W An,(d16,An) */
uae_u32 REGPARAM2 op_3148_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 12; 
	uae_s16 src = m68k_areg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	struct flag_struct oldflags;
	oldflags.cznv = regflags.cznv;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(4);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		exception3_write_access(opcode, dsta, 1, src, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (2/1) */
/* 4 0,0   */

/* MOVE.W (An),(d16,An) */
uae_u32 REGPARAM2 op_3150_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access2(opcode, srca, 1, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 4, 0);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(4);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		exception3_write_access(opcode, dsta, 1, src, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 4 0,0   */

/* MOVE.W (An)+,(d16,An) */
uae_u32 REGPARAM2 op_3158_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_areg(regs, srcreg) += 2 + 0;
		m68k_incpci(2);
		exception3_read_access2(opcode, srca, 1, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) += 2 + 0;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) += 2;
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 4, 0);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(4);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		exception3_write_access(opcode, dsta, 1, src, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 4 0,0   */

/* MOVE.W -(An),(d16,An) */
uae_u32 REGPARAM2 op_3160_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - 2;
	if (srca & 1) {
		m68k_areg(regs, srcreg) = srca;
		m68k_incpci(2);
		exception3_read_access2(opcode, srca, 1, 1);
		return 2 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) = srca;
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 4, 0);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(4);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		exception3_write_access(opcode, dsta, 1, src, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (3/1) */
/* 4 0,0   */

/* MOVE.W (d16,An),(d16,An) */
uae_u32 REGPARAM2 op_3168_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 6, 0);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(6);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		exception3_write_access(opcode, dsta, 1, src, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (4/1) */
/* 6 0,0   */

/* MOVE.W (d8,An,Xn),(d16,An) */
uae_u32 REGPARAM2 op_3170_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 22; 
	uaecptr srca;
	BusCyclePenalty += 2;
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 6, 0);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(6);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		exception3_write_access(opcode, dsta, 1, src, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 22 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 22 * CYCLE_UNIT / 2 + count_cycles;
}
/* 22 (4/1) */
/* 6 6,0   */

/* MOVE.W (xxx).W,(d16,An) */
uae_u32 REGPARAM2 op_3178_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, srca, 1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 6, 0);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(6);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		exception3_write_access(opcode, dsta, 1, src, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (4/1) */
/* 6 0,0   */

/* MOVE.W (xxx).L,(d16,An) */
uae_u32 REGPARAM2 op_3179_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 24; 
	uaecptr srca;
	srca = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	srca |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, srca, 1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 8, 0);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(8);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		exception3_write_access(opcode, dsta, 1, src, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(8);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 24 * CYCLE_UNIT / 2 + count_cycles;
}
/* 24 (5/1) */
/* 8 0,0   */

/* MOVE.W (d16,PC),(d16,An) */
uae_u32 REGPARAM2 op_317a_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	srca = m68k_getpci() + 2;
	srca += (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 6, 0);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(6);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		exception3_write_access(opcode, dsta, 1, src, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (4/1) */
/* 6 0,0   */

/* MOVE.W (d8,PC,Xn),(d16,An) */
uae_u32 REGPARAM2 op_317b_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 22; 
	uaecptr srca;
	uaecptr tmppc = m68k_getpci() + 2;
	BusCyclePenalty += 2;
	srca = get_disp_ea_000(tmppc, get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 6, 0);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(6);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		exception3_write_access(opcode, dsta, 1, src, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 22 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 22 * CYCLE_UNIT / 2 + count_cycles;
}
/* 22 (4/1) */
/* 6 6,0   */

/* MOVE.W #<data>.W,(d16,An) */
uae_u32 REGPARAM2 op_317c_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 16; 
	uae_s16 src = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, 0);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	struct flag_struct oldflags;
	oldflags.cznv = regflags.cznv;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(6);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		exception3_write_access(opcode, dsta, 1, src, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 6 0,0   */

/* MOVE.W Dn,(d8,An,Xn) */
uae_u32 REGPARAM2 op_3180_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 14; 
	uae_s16 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	BusCyclePenalty += 2;
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	struct flag_struct oldflags;
	oldflags.cznv = regflags.cznv;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(4);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		exception3_write_access(opcode, dsta, 1, src, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 14 * CYCLE_UNIT / 2 + count_cycles;
}
/* 14 (2/1) */
/* 4 4,0   */

/* MOVE.W An,(d8,An,Xn) */
uae_u32 REGPARAM2 op_3188_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 14; 
	uae_s16 src = m68k_areg(regs, srcreg);
	uaecptr dsta;
	BusCyclePenalty += 2;
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	struct flag_struct oldflags;
	oldflags.cznv = regflags.cznv;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(4);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		exception3_write_access(opcode, dsta, 1, src, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 14 * CYCLE_UNIT / 2 + count_cycles;
}
/* 14 (2/1) */
/* 4 4,0   */

/* MOVE.W (An),(d8,An,Xn) */
uae_u32 REGPARAM2 op_3190_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access2(opcode, srca, 1, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	BusCyclePenalty += 2;
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 4, 0);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(4);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		exception3_write_access(opcode, dsta, 1, src, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (3/1) */
/* 4 4,0   */

/* MOVE.W (An)+,(d8,An,Xn) */
uae_u32 REGPARAM2 op_3198_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_areg(regs, srcreg) += 2 + 0;
		m68k_incpci(2);
		exception3_read_access2(opcode, srca, 1, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) += 2 + 0;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) += 2;
	uaecptr dsta;
	BusCyclePenalty += 2;
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 4, 0);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(4);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		exception3_write_access(opcode, dsta, 1, src, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (3/1) */
/* 4 4,0   */

/* MOVE.W -(An),(d8,An,Xn) */
uae_u32 REGPARAM2 op_31a0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - 2;
	if (srca & 1) {
		m68k_areg(regs, srcreg) = srca;
		m68k_incpci(2);
		exception3_read_access2(opcode, srca, 1, 1);
		return 2 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) = srca;
	uaecptr dsta;
	BusCyclePenalty += 2;
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 4, 0);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(4);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		exception3_write_access(opcode, dsta, 1, src, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (3/1) */
/* 4 4,0   */

/* MOVE.W (d16,An),(d8,An,Xn) */
uae_u32 REGPARAM2 op_31a8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 22; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	BusCyclePenalty += 2;
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_000_prefetch(6));
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 6, 0);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(6);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		exception3_write_access(opcode, dsta, 1, src, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 22 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 22 * CYCLE_UNIT / 2 + count_cycles;
}
/* 22 (4/1) */
/* 6 4,0   */

/* MOVE.W (d8,An,Xn),(d8,An,Xn) */
uae_u32 REGPARAM2 op_31b0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 24; 
	uaecptr srca;
	BusCyclePenalty += 2;
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	BusCyclePenalty += 2;
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_000_prefetch(6));
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 6, 0);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(6);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		exception3_write_access(opcode, dsta, 1, src, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 24 * CYCLE_UNIT / 2 + count_cycles;
}
/* 24 (4/1) */
/* 6 6,4   */

/* MOVE.W (xxx).W,(d8,An,Xn) */
uae_u32 REGPARAM2 op_31b8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 22; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, srca, 1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	BusCyclePenalty += 2;
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_000_prefetch(6));
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 6, 0);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(6);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		exception3_write_access(opcode, dsta, 1, src, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 22 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 22 * CYCLE_UNIT / 2 + count_cycles;
}
/* 22 (4/1) */
/* 6 4,0   */

/* MOVE.W (xxx).L,(d8,An,Xn) */
uae_u32 REGPARAM2 op_31b9_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 26; 
	uaecptr srca;
	srca = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	srca |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, srca, 1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	BusCyclePenalty += 2;
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_000_prefetch(8));
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 8, 0);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(8);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		exception3_write_access(opcode, dsta, 1, src, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return 22 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(8);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 26 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 26 * CYCLE_UNIT / 2 + count_cycles;
}
/* 26 (5/1) */
/* 8 4,0   */

/* MOVE.W (d16,PC),(d8,An,Xn) */
uae_u32 REGPARAM2 op_31ba_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 22; 
	uaecptr srca;
	srca = m68k_getpci() + 2;
	srca += (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	BusCyclePenalty += 2;
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_000_prefetch(6));
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 6, 0);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(6);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		exception3_write_access(opcode, dsta, 1, src, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 22 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 22 * CYCLE_UNIT / 2 + count_cycles;
}
/* 22 (4/1) */
/* 6 4,0   */

/* MOVE.W (d8,PC,Xn),(d8,An,Xn) */
uae_u32 REGPARAM2 op_31bb_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 24; 
	uaecptr srca;
	uaecptr tmppc = m68k_getpci() + 2;
	BusCyclePenalty += 2;
	srca = get_disp_ea_000(tmppc, get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	BusCyclePenalty += 2;
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_000_prefetch(6));
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 6, 0);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(6);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		exception3_write_access(opcode, dsta, 1, src, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 24 * CYCLE_UNIT / 2 + count_cycles;
}
/* 24 (4/1) */
/* 6 6,4   */

/* MOVE.W #<data>.W,(d8,An,Xn) */
uae_u32 REGPARAM2 op_31bc_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 18; 
	uae_s16 src = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	BusCyclePenalty += 2;
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_000_prefetch(6));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, 0);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	struct flag_struct oldflags;
	oldflags.cznv = regflags.cznv;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(6);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		exception3_write_access(opcode, dsta, 1, src, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (3/1) */
/* 6 4,0   */

/* MOVE.W Dn,(xxx).W */
uae_u32 REGPARAM2 op_31c0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 30;
	CurrentInstrCycles = 12; 
	uae_s16 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	struct flag_struct oldflags;
	oldflags.cznv = regflags.cznv;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(4);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		exception3_write_access(opcode, dsta, 1, src, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (2/1) */
/* 4 0,0   */

/* MOVE.W An,(xxx).W */
uae_u32 REGPARAM2 op_31c8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 30;
	CurrentInstrCycles = 12; 
	uae_s16 src = m68k_areg(regs, srcreg);
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	struct flag_struct oldflags;
	oldflags.cznv = regflags.cznv;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(4);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		exception3_write_access(opcode, dsta, 1, src, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (2/1) */
/* 4 0,0   */

/* MOVE.W (An),(xxx).W */
uae_u32 REGPARAM2 op_31d0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 30;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access2(opcode, srca, 1, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 4, 0);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(4);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		exception3_write_access(opcode, dsta, 1, src, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 4 0,0   */

/* MOVE.W (An)+,(xxx).W */
uae_u32 REGPARAM2 op_31d8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 30;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_areg(regs, srcreg) += 2 + 0;
		m68k_incpci(2);
		exception3_read_access2(opcode, srca, 1, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) += 2 + 0;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) += 2;
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 4, 0);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(4);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		exception3_write_access(opcode, dsta, 1, src, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 4 0,0   */

/* MOVE.W -(An),(xxx).W */
uae_u32 REGPARAM2 op_31e0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 30;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - 2;
	if (srca & 1) {
		m68k_areg(regs, srcreg) = srca;
		m68k_incpci(2);
		exception3_read_access2(opcode, srca, 1, 1);
		return 2 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) = srca;
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 4, 0);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(4);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		exception3_write_access(opcode, dsta, 1, src, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (3/1) */
/* 4 0,0   */

/* MOVE.W (d16,An),(xxx).W */
uae_u32 REGPARAM2 op_31e8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 30;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 6, 0);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(6);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		exception3_write_access(opcode, dsta, 1, src, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (4/1) */
/* 6 0,0   */

/* MOVE.W (d8,An,Xn),(xxx).W */
uae_u32 REGPARAM2 op_31f0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 30;
	CurrentInstrCycles = 22; 
	uaecptr srca;
	BusCyclePenalty += 2;
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 6, 0);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(6);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		exception3_write_access(opcode, dsta, 1, src, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 22 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 22 * CYCLE_UNIT / 2 + count_cycles;
}
/* 22 (4/1) */
/* 6 6,0   */

/* MOVE.W (xxx).W,(xxx).W */
uae_u32 REGPARAM2 op_31f8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 30;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, srca, 1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 6, 0);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(6);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		exception3_write_access(opcode, dsta, 1, src, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (4/1) */
/* 6 0,0   */

/* MOVE.W (xxx).L,(xxx).W */
uae_u32 REGPARAM2 op_31f9_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 30;
	CurrentInstrCycles = 24; 
	uaecptr srca;
	srca = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	srca |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, srca, 1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 8, 0);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(8);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		exception3_write_access(opcode, dsta, 1, src, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(8);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 24 * CYCLE_UNIT / 2 + count_cycles;
}
/* 24 (5/1) */
/* 8 0,0   */

/* MOVE.W (d16,PC),(xxx).W */
uae_u32 REGPARAM2 op_31fa_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 30;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	srca = m68k_getpci() + 2;
	srca += (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 6, 0);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(6);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		exception3_write_access(opcode, dsta, 1, src, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (4/1) */
/* 6 0,0   */

/* MOVE.W (d8,PC,Xn),(xxx).W */
uae_u32 REGPARAM2 op_31fb_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 30;
	CurrentInstrCycles = 22; 
	uaecptr srca;
	uaecptr tmppc = m68k_getpci() + 2;
	BusCyclePenalty += 2;
	srca = get_disp_ea_000(tmppc, get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 6, 0);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(6);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		exception3_write_access(opcode, dsta, 1, src, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 22 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 22 * CYCLE_UNIT / 2 + count_cycles;
}
/* 22 (4/1) */
/* 6 6,0   */

/* MOVE.W #<data>.W,(xxx).W */
uae_u32 REGPARAM2 op_31fc_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 30;
	CurrentInstrCycles = 16; 
	uae_s16 src = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 6, 0);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	struct flag_struct oldflags;
	oldflags.cznv = regflags.cznv;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(6);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		exception3_write_access(opcode, dsta, 1, src, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 6 0,0   */

/* MOVE.W Dn,(xxx).L */
uae_u32 REGPARAM2 op_33c0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 30;
	CurrentInstrCycles = 16; 
	uae_s16 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	dsta |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	struct flag_struct oldflags;
	oldflags.cznv = regflags.cznv;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(6);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		exception3_write_access(opcode, dsta, 1, src, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 6 0,0   */

/* MOVE.W An,(xxx).L */
uae_u32 REGPARAM2 op_33c8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 30;
	CurrentInstrCycles = 16; 
	uae_s16 src = m68k_areg(regs, srcreg);
	uaecptr dsta;
	dsta = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	dsta |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	struct flag_struct oldflags;
	oldflags.cznv = regflags.cznv;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(6);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		exception3_write_access(opcode, dsta, 1, src, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 6 0,0   */

/* MOVE.W (An),(xxx).L */
uae_u32 REGPARAM2 op_33d0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 30;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access2(opcode, srca, 1, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = get_word_000_prefetch(4) << 16;
	dsta |= regs.irc;
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 4, 0);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(4);
		regs.irc = dsta >> 16;
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		exception3_write_access(opcode, dsta, 1, src, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		regs.irc = dsta >> 16;
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	get_word_000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, 0);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (4/1) */
/* 6 0,0   */

/* MOVE.W (An)+,(xxx).L */
uae_u32 REGPARAM2 op_33d8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 30;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_areg(regs, srcreg) += 2 + 0;
		m68k_incpci(2);
		exception3_read_access2(opcode, srca, 1, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) += 2 + 0;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) += 2;
	uaecptr dsta;
	dsta = get_word_000_prefetch(4) << 16;
	dsta |= regs.irc;
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 4, 0);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(4);
		regs.irc = dsta >> 16;
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		exception3_write_access(opcode, dsta, 1, src, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		regs.irc = dsta >> 16;
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	get_word_000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, 0);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (4/1) */
/* 6 0,0   */

/* MOVE.W -(An),(xxx).L */
uae_u32 REGPARAM2 op_33e0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 30;
	CurrentInstrCycles = 22; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - 2;
	if (srca & 1) {
		m68k_areg(regs, srcreg) = srca;
		m68k_incpci(2);
		exception3_read_access2(opcode, srca, 1, 1);
		return 2 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) = srca;
	uaecptr dsta;
	dsta = get_word_000_prefetch(4) << 16;
	dsta |= regs.irc;
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 4, 0);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(4);
		regs.irc = dsta >> 16;
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		exception3_write_access(opcode, dsta, 1, src, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		regs.irc = dsta >> 16;
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	get_word_000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, 0);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 22 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 22 * CYCLE_UNIT / 2 + count_cycles;
}
/* 22 (4/1) */
/* 6 0,0   */

/* MOVE.W (d16,An),(xxx).L */
uae_u32 REGPARAM2 op_33e8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 30;
	CurrentInstrCycles = 24; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = get_word_000_prefetch(6) << 16;
	dsta |= regs.irc;
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 6, 0);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(6);
		regs.irc = dsta >> 16;
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		exception3_write_access(opcode, dsta, 1, src, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		regs.irc = dsta >> 16;
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(8);
	get_word_000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, 0);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 24 * CYCLE_UNIT / 2 + count_cycles;
}
/* 24 (5/1) */
/* 8 0,0   */

/* MOVE.W (d8,An,Xn),(xxx).L */
uae_u32 REGPARAM2 op_33f0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 30;
	CurrentInstrCycles = 26; 
	uaecptr srca;
	BusCyclePenalty += 2;
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = get_word_000_prefetch(6) << 16;
	dsta |= regs.irc;
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 6, 0);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(6);
		regs.irc = dsta >> 16;
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		exception3_write_access(opcode, dsta, 1, src, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		regs.irc = dsta >> 16;
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(8);
	get_word_000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, 0);
		return 22 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 26 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 26 * CYCLE_UNIT / 2 + count_cycles;
}
/* 26 (5/1) */
/* 8 8,0   */

/* MOVE.W (xxx).W,(xxx).L */
uae_u32 REGPARAM2 op_33f8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 30;
	CurrentInstrCycles = 24; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, srca, 1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = get_word_000_prefetch(6) << 16;
	dsta |= regs.irc;
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 6, 0);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(6);
		regs.irc = dsta >> 16;
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		exception3_write_access(opcode, dsta, 1, src, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		regs.irc = dsta >> 16;
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(8);
	get_word_000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, 0);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 24 * CYCLE_UNIT / 2 + count_cycles;
}
/* 24 (5/1) */
/* 8 0,0   */

/* MOVE.W (xxx).L,(xxx).L */
uae_u32 REGPARAM2 op_33f9_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 30;
	CurrentInstrCycles = 28; 
	uaecptr srca;
	srca = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	srca |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, srca, 1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = get_word_000_prefetch(8) << 16;
	dsta |= regs.irc;
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 8, 0);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(8);
		regs.irc = dsta >> 16;
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		exception3_write_access(opcode, dsta, 1, src, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		regs.irc = dsta >> 16;
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(10);
	get_word_000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, 0);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 28 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 28 * CYCLE_UNIT / 2 + count_cycles;
}
/* 28 (6/1) */
/* 10 0,0   */

/* MOVE.W (d16,PC),(xxx).L */
uae_u32 REGPARAM2 op_33fa_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 30;
	CurrentInstrCycles = 24; 
	uaecptr srca;
	srca = m68k_getpci() + 2;
	srca += (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = get_word_000_prefetch(6) << 16;
	dsta |= regs.irc;
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 6, 0);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(6);
		regs.irc = dsta >> 16;
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		exception3_write_access(opcode, dsta, 1, src, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		regs.irc = dsta >> 16;
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(8);
	get_word_000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, 0);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 24 * CYCLE_UNIT / 2 + count_cycles;
}
/* 24 (5/1) */
/* 8 0,0   */

/* MOVE.W (d8,PC,Xn),(xxx).L */
uae_u32 REGPARAM2 op_33fb_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 30;
	CurrentInstrCycles = 26; 
	uaecptr srca;
	uaecptr tmppc = m68k_getpci() + 2;
	BusCyclePenalty += 2;
	srca = get_disp_ea_000(tmppc, get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = get_word_000_prefetch(6) << 16;
	dsta |= regs.irc;
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 6, 0);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(6);
		regs.irc = dsta >> 16;
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		exception3_write_access(opcode, dsta, 1, src, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		regs.irc = dsta >> 16;
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(8);
	get_word_000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, 0);
		return 22 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 26 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 26 * CYCLE_UNIT / 2 + count_cycles;
}
/* 26 (5/1) */
/* 8 8,0   */

/* MOVE.W #<data>.W,(xxx).L */
uae_u32 REGPARAM2 op_33fc_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 30;
	CurrentInstrCycles = 20; 
	uae_s16 src = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = get_word_000_prefetch(6) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	dsta |= get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 8, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	struct flag_struct oldflags;
	oldflags.cznv = regflags.cznv;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(8);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		exception3_write_access(opcode, dsta, 1, src, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(8);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (4/1) */
/* 8 0,0   */

/* NEGX.B Dn */
uae_u32 REGPARAM2 op_4000_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 16;
	CurrentInstrCycles = 4;  
	uae_s8 src = m68k_dreg(regs, srcreg);
	uae_u32 newv = 0 - src - (GET_XFLG() ? 1 : 0);
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(0)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_VFLG((flgs ^ flgo) & (flgo ^ flgn));
	SET_CFLG(flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
	COPY_CARRY();
	SET_ZFLG(GET_ZFLG() & (((uae_s8)(newv)) == 0));
	SET_NFLG(((uae_s8)(newv)) < 0);
	m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((newv) & 0xff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 4 * CYCLE_UNIT / 2 + count_cycles;
}
/* 4 (1/0) */
/* 2 0,0   */

/* NEGX.B (An) */
uae_u32 REGPARAM2 op_4010_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 16;
	CurrentInstrCycles = 8;  
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 newv = 0 - src - (GET_XFLG() ? 1 : 0);
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(0)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_VFLG((flgs ^ flgo) & (flgo ^ flgn));
	SET_CFLG(flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
	COPY_CARRY();
	SET_ZFLG(GET_ZFLG() & (((uae_s8)(newv)) == 0));
	SET_NFLG(((uae_s8)(newv)) < 0);
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_000_prefetch(4);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return 4 * CYCLE_UNIT / 2 + count_cycles;
		}
		opcode = regs.ir;
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	if(loop_mode & 0xfffe) {
		count_cycles += (loop_mode & 0xfffe) * CYCLE_UNIT / 2;
		loop_mode = 1;
	}
	put_byte_000(srca, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, srca + 0, 0x0, newv, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8+ (1/1) */
/* 2 0,0   */

/* NEGX.B (An)+ */
uae_u32 REGPARAM2 op_4018_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 16;
	CurrentInstrCycles = 8;  
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
	uae_u32 newv = 0 - src - (GET_XFLG() ? 1 : 0);
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(0)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_VFLG((flgs ^ flgo) & (flgo ^ flgn));
	SET_CFLG(flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
	COPY_CARRY();
	SET_ZFLG(GET_ZFLG() & (((uae_s8)(newv)) == 0));
	SET_NFLG(((uae_s8)(newv)) < 0);
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_000_prefetch(4);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return 4 * CYCLE_UNIT / 2 + count_cycles;
		}
		opcode = regs.ir;
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	if(loop_mode & 0xfffe) {
		count_cycles += (loop_mode & 0xfffe) * CYCLE_UNIT / 2;
		loop_mode = 1;
	}
	put_byte_000(srca, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, srca + 0, 0x0, newv, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8+ (1/1) */
/* 2 0,0   */

/* NEGX.B -(An) */
uae_u32 REGPARAM2 op_4020_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 16;
	CurrentInstrCycles = 10; 
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) = srca;
	uae_u32 newv = 0 - src - (GET_XFLG() ? 1 : 0);
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(0)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_VFLG((flgs ^ flgo) & (flgo ^ flgn));
	SET_CFLG(flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
	COPY_CARRY();
	SET_ZFLG(GET_ZFLG() & (((uae_s8)(newv)) == 0));
	SET_NFLG(((uae_s8)(newv)) < 0);
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_000_prefetch(4);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return 6 * CYCLE_UNIT / 2 + count_cycles;
		}
		opcode = regs.ir;
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	if(loop_mode & 0xfffe) {
		count_cycles += (loop_mode & 0xfffe) * CYCLE_UNIT / 2;
		loop_mode = 1;
	}
	put_byte_000(srca, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, srca + 0, 0x0, newv, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return 10 * CYCLE_UNIT / 2 + count_cycles;
}
/* 10+ (1/1) */
/* 2 0,0   */

/* NEGX.B (d16,An) */
uae_u32 REGPARAM2 op_4028_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 16;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 newv = 0 - src - (GET_XFLG() ? 1 : 0);
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(0)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_VFLG((flgs ^ flgo) & (flgo ^ flgn));
	SET_CFLG(flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
	COPY_CARRY();
	SET_ZFLG(GET_ZFLG() & (((uae_s8)(newv)) == 0));
	SET_NFLG(((uae_s8)(newv)) < 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_byte_000(srca, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, srca + 0, 0x0, newv, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 4 0,0   */

/* NEGX.B (d8,An,Xn) */
uae_u32 REGPARAM2 op_4030_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 16;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	BusCyclePenalty += 2;
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 newv = 0 - src - (GET_XFLG() ? 1 : 0);
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(0)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_VFLG((flgs ^ flgo) & (flgo ^ flgn));
	SET_CFLG(flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
	COPY_CARRY();
	SET_ZFLG(GET_ZFLG() & (((uae_s8)(newv)) == 0));
	SET_NFLG(((uae_s8)(newv)) < 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_byte_000(srca, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, srca + 0, 0x0, newv, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (3/1) */
/* 4 4,0   */

/* NEGX.B (xxx).W */
uae_u32 REGPARAM2 op_4038_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 16;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 newv = 0 - src - (GET_XFLG() ? 1 : 0);
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(0)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_VFLG((flgs ^ flgo) & (flgo ^ flgn));
	SET_CFLG(flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
	COPY_CARRY();
	SET_ZFLG(GET_ZFLG() & (((uae_s8)(newv)) == 0));
	SET_NFLG(((uae_s8)(newv)) < 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_byte_000(srca, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, srca + 0, 0x0, newv, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 4 0,0   */

/* NEGX.B (xxx).L */
uae_u32 REGPARAM2 op_4039_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 16;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	srca = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	srca |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 newv = 0 - src - (GET_XFLG() ? 1 : 0);
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(0)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_VFLG((flgs ^ flgo) & (flgo ^ flgn));
	SET_CFLG(flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
	COPY_CARRY();
	SET_ZFLG(GET_ZFLG() & (((uae_s8)(newv)) == 0));
	SET_NFLG(((uae_s8)(newv)) < 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_byte_000(srca, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, srca + 0, 0x0, newv, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (4/1) */
/* 6 0,0   */

/* NEGX.W Dn */
uae_u32 REGPARAM2 op_4040_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 16;
	CurrentInstrCycles = 4;  
	uae_s16 src = m68k_dreg(regs, srcreg);
	uae_u32 newv = 0 - src - (GET_XFLG() ? 1 : 0);
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(0)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_VFLG((flgs ^ flgo) & (flgo ^ flgn));
	SET_CFLG(flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
	COPY_CARRY();
	SET_ZFLG(GET_ZFLG() & (((uae_s16)(newv)) == 0));
	SET_NFLG(((uae_s16)(newv)) < 0);
	m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | ((newv) & 0xffff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 4 * CYCLE_UNIT / 2 + count_cycles;
}
/* 4 (1/0) */
/* 2 0,0   */

/* NEGX.W (An) */
uae_u32 REGPARAM2 op_4050_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 16;
	CurrentInstrCycles = 8;  
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access2(opcode, srca, 1, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 newv = 0 - src - (GET_XFLG() ? 1 : 0);
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(0)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_VFLG((flgs ^ flgo) & (flgo ^ flgn));
	SET_CFLG(flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
	COPY_CARRY();
	SET_ZFLG(GET_ZFLG() & (((uae_s16)(newv)) == 0));
	SET_NFLG(((uae_s16)(newv)) < 0);
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_000_prefetch(4);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return 4 * CYCLE_UNIT / 2 + count_cycles;
		}
		opcode = regs.ir;
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	if(loop_mode & 0xfffe) {
		count_cycles += (loop_mode & 0xfffe) * CYCLE_UNIT / 2;
		loop_mode = 1;
	}
	put_word_000(srca, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, srca + 0, 0x1, newv, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8+ (1/1) */
/* 2 0,0   */

/* NEGX.W (An)+ */
uae_u32 REGPARAM2 op_4058_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 16;
	CurrentInstrCycles = 8;  
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_areg(regs, srcreg) += 2 + 0;
		m68k_incpci(2);
		exception3_read_access2(opcode, srca, 1, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) += 2 + 0;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) += 2;
	uae_u32 newv = 0 - src - (GET_XFLG() ? 1 : 0);
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(0)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_VFLG((flgs ^ flgo) & (flgo ^ flgn));
	SET_CFLG(flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
	COPY_CARRY();
	SET_ZFLG(GET_ZFLG() & (((uae_s16)(newv)) == 0));
	SET_NFLG(((uae_s16)(newv)) < 0);
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_000_prefetch(4);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return 4 * CYCLE_UNIT / 2 + count_cycles;
		}
		opcode = regs.ir;
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	if(loop_mode & 0xfffe) {
		count_cycles += (loop_mode & 0xfffe) * CYCLE_UNIT / 2;
		loop_mode = 1;
	}
	put_word_000(srca, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, srca + 0, 0x1, newv, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8+ (1/1) */
/* 2 0,0   */

/* NEGX.W -(An) */
uae_u32 REGPARAM2 op_4060_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 16;
	CurrentInstrCycles = 10; 
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - 2;
	if (srca & 1) {
		m68k_areg(regs, srcreg) = srca;
		m68k_incpci(2);
		exception3_read_access2(opcode, srca, 1, 1);
		return 2 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) = srca;
	uae_u32 newv = 0 - src - (GET_XFLG() ? 1 : 0);
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(0)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_VFLG((flgs ^ flgo) & (flgo ^ flgn));
	SET_CFLG(flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
	COPY_CARRY();
	SET_ZFLG(GET_ZFLG() & (((uae_s16)(newv)) == 0));
	SET_NFLG(((uae_s16)(newv)) < 0);
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_000_prefetch(4);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return 6 * CYCLE_UNIT / 2 + count_cycles;
		}
		opcode = regs.ir;
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	if(loop_mode & 0xfffe) {
		count_cycles += (loop_mode & 0xfffe) * CYCLE_UNIT / 2;
		loop_mode = 1;
	}
	put_word_000(srca, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, srca + 0, 0x1, newv, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return 10 * CYCLE_UNIT / 2 + count_cycles;
}
/* 10+ (1/1) */
/* 2 0,0   */

/* NEGX.W (d16,An) */
uae_u32 REGPARAM2 op_4068_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 16;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 newv = 0 - src - (GET_XFLG() ? 1 : 0);
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(0)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_VFLG((flgs ^ flgo) & (flgo ^ flgn));
	SET_CFLG(flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
	COPY_CARRY();
	SET_ZFLG(GET_ZFLG() & (((uae_s16)(newv)) == 0));
	SET_NFLG(((uae_s16)(newv)) < 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_word_000(srca, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, srca + 0, 0x1, newv, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 4 0,0   */

/* NEGX.W (d8,An,Xn) */
uae_u32 REGPARAM2 op_4070_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 16;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	BusCyclePenalty += 2;
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 newv = 0 - src - (GET_XFLG() ? 1 : 0);
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(0)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_VFLG((flgs ^ flgo) & (flgo ^ flgn));
	SET_CFLG(flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
	COPY_CARRY();
	SET_ZFLG(GET_ZFLG() & (((uae_s16)(newv)) == 0));
	SET_NFLG(((uae_s16)(newv)) < 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_word_000(srca, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, srca + 0, 0x1, newv, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (3/1) */
/* 4 4,0   */

/* NEGX.W (xxx).W */
uae_u32 REGPARAM2 op_4078_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 16;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, srca, 1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 newv = 0 - src - (GET_XFLG() ? 1 : 0);
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(0)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_VFLG((flgs ^ flgo) & (flgo ^ flgn));
	SET_CFLG(flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
	COPY_CARRY();
	SET_ZFLG(GET_ZFLG() & (((uae_s16)(newv)) == 0));
	SET_NFLG(((uae_s16)(newv)) < 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_word_000(srca, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, srca + 0, 0x1, newv, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 4 0,0   */

/* NEGX.W (xxx).L */
uae_u32 REGPARAM2 op_4079_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 16;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	srca = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	srca |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, srca, 1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 newv = 0 - src - (GET_XFLG() ? 1 : 0);
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(0)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_VFLG((flgs ^ flgo) & (flgo ^ flgn));
	SET_CFLG(flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
	COPY_CARRY();
	SET_ZFLG(GET_ZFLG() & (((uae_s16)(newv)) == 0));
	SET_NFLG(((uae_s16)(newv)) < 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_word_000(srca, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, srca + 0, 0x1, newv, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (4/1) */
/* 6 0,0   */

/* NEGX.L Dn */
uae_u32 REGPARAM2 op_4080_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 16;
	CurrentInstrCycles = 6;  
	uae_s32 src = m68k_dreg(regs, srcreg);
	uae_u32 newv = 0 - src - (GET_XFLG() ? 1 : 0);
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(0)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_VFLG((flgs ^ flgo) & (flgo ^ flgn));
	SET_CFLG(flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
	COPY_CARRY();
	SET_ZFLG(GET_ZFLG() & (((uae_s32)(newv)) == 0));
	SET_NFLG(((uae_s32)(newv)) < 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		dreg_68000_long_replace_low(srcreg, newv);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	m68k_dreg(regs, srcreg) = (newv);
	m68k_incpci(2);
	return 6 * CYCLE_UNIT / 2 + count_cycles;
}
/* 6 (1/0) */
/* 2 0,0   */

/* NEGX.L (An) */
uae_u32 REGPARAM2 op_4090_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 16;
	CurrentInstrCycles = 16; 
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 newv = 0 - src - (GET_XFLG() ? 1 : 0);
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(0)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_VFLG((flgs ^ flgo) & (flgo ^ flgn));
	SET_CFLG(flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
	COPY_CARRY();
	SET_ZFLG(GET_ZFLG() & (((uae_s32)(newv)) == 0));
	SET_NFLG(((uae_s32)(newv)) < 0);
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_000_prefetch(4);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			int pcoffset = 0;
			int bflgs = ((uae_s16)(src)) < 0;
			int bflgo = ((uae_s16)(0)) < 0;
			int bflgn = ((uae_s16)(newv)) < 0;
			SET_VFLG((bflgs ^ bflgo) & (bflgo ^ bflgn));
			SET_CFLG(bflgs ^ ((bflgs ^ bflgn) & (bflgo ^ bflgn)));
			SET_ZFLG(GET_ZFLG() & (((uae_s16)(newv)) == 0));
			SET_NFLG(((uae_s16)(newv)) < 0);
			SET_XFLG(GET_CFLG());
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return 8 * CYCLE_UNIT / 2 + count_cycles;
		}
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	if(loop_mode & 0xfffe) {
		count_cycles += (loop_mode & 0xfffe) * CYCLE_UNIT / 2;
		loop_mode = 1;
	}
	put_word_000(srca + 2, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, srca + 2, 0x1, newv, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(srca, newv >> 16); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, srca + 0, 0x1, newv >> 16, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16+ (2/2) */
/* 2 0,0   */

/* NEGX.L (An)+ */
uae_u32 REGPARAM2 op_4098_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 16;
	CurrentInstrCycles = 16; 
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) += 4;
	uae_u32 newv = 0 - src - (GET_XFLG() ? 1 : 0);
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(0)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_VFLG((flgs ^ flgo) & (flgo ^ flgn));
	SET_CFLG(flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
	COPY_CARRY();
	SET_ZFLG(GET_ZFLG() & (((uae_s32)(newv)) == 0));
	SET_NFLG(((uae_s32)(newv)) < 0);
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_000_prefetch(4);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			int pcoffset = 0;
			int bflgs = ((uae_s16)(src)) < 0;
			int bflgo = ((uae_s16)(0)) < 0;
			int bflgn = ((uae_s16)(newv)) < 0;
			SET_VFLG((bflgs ^ bflgo) & (bflgo ^ bflgn));
			SET_CFLG(bflgs ^ ((bflgs ^ bflgn) & (bflgo ^ bflgn)));
			SET_ZFLG(GET_ZFLG() & (((uae_s16)(newv)) == 0));
			SET_NFLG(((uae_s16)(newv)) < 0);
			SET_XFLG(GET_CFLG());
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return 8 * CYCLE_UNIT / 2 + count_cycles;
		}
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	if(loop_mode & 0xfffe) {
		count_cycles += (loop_mode & 0xfffe) * CYCLE_UNIT / 2;
		loop_mode = 1;
	}
	put_word_000(srca + 2, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, srca + 2, 0x1, newv, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(srca, newv >> 16); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, srca + 0, 0x1, newv >> 16, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16+ (2/2) */
/* 2 0,0   */

/* NEGX.L -(An) */
uae_u32 REGPARAM2 op_40a0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 16;
	CurrentInstrCycles = 18; 
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - 4;
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return 2 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) = srca;
	uae_u32 newv = 0 - src - (GET_XFLG() ? 1 : 0);
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(0)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_VFLG((flgs ^ flgo) & (flgo ^ flgn));
	SET_CFLG(flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
	COPY_CARRY();
	SET_ZFLG(GET_ZFLG() & (((uae_s32)(newv)) == 0));
	SET_NFLG(((uae_s32)(newv)) < 0);
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_000_prefetch(4);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			int pcoffset = 0;
			int bflgs = ((uae_s16)(src)) < 0;
			int bflgo = ((uae_s16)(0)) < 0;
			int bflgn = ((uae_s16)(newv)) < 0;
			SET_VFLG((bflgs ^ bflgo) & (bflgo ^ bflgn));
			SET_CFLG(bflgs ^ ((bflgs ^ bflgn) & (bflgo ^ bflgn)));
			SET_ZFLG(GET_ZFLG() & (((uae_s16)(newv)) == 0));
			SET_NFLG(((uae_s16)(newv)) < 0);
			SET_XFLG(GET_CFLG());
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return 10 * CYCLE_UNIT / 2 + count_cycles;
		}
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	if(loop_mode & 0xfffe) {
		count_cycles += (loop_mode & 0xfffe) * CYCLE_UNIT / 2;
		loop_mode = 1;
	}
	put_word_000(srca + 2, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, srca + 2, 0x1, newv, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(srca, newv >> 16); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, srca + 0, 0x1, newv >> 16, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18+ (2/2) */
/* 2 0,0   */

/* NEGX.L (d16,An) */
uae_u32 REGPARAM2 op_40a8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 16;
	CurrentInstrCycles = 24; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 newv = 0 - src - (GET_XFLG() ? 1 : 0);
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(0)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_VFLG((flgs ^ flgo) & (flgo ^ flgn));
	SET_CFLG(flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
	COPY_CARRY();
	SET_ZFLG(GET_ZFLG() & (((uae_s32)(newv)) == 0));
	SET_NFLG(((uae_s32)(newv)) < 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		int bflgs = ((uae_s16)(src)) < 0;
		int bflgo = ((uae_s16)(0)) < 0;
		int bflgn = ((uae_s16)(newv)) < 0;
		SET_VFLG((bflgs ^ bflgo) & (bflgo ^ bflgn));
		SET_CFLG(bflgs ^ ((bflgs ^ bflgn) & (bflgo ^ bflgn)));
		SET_ZFLG(GET_ZFLG() & (((uae_s16)(newv)) == 0));
		SET_NFLG(((uae_s16)(newv)) < 0);
		SET_XFLG(GET_CFLG());
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(srca + 2, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, srca + 2, 0x1, newv, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(srca, newv >> 16); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, srca + 0, 0x1, newv >> 16, 1);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 24 * CYCLE_UNIT / 2 + count_cycles;
}
/* 24 (4/2) */
/* 4 0,0   */

/* NEGX.L (d8,An,Xn) */
uae_u32 REGPARAM2 op_40b0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 16;
	CurrentInstrCycles = 26; 
	uaecptr srca;
	BusCyclePenalty += 2;
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 newv = 0 - src - (GET_XFLG() ? 1 : 0);
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(0)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_VFLG((flgs ^ flgo) & (flgo ^ flgn));
	SET_CFLG(flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
	COPY_CARRY();
	SET_ZFLG(GET_ZFLG() & (((uae_s32)(newv)) == 0));
	SET_NFLG(((uae_s32)(newv)) < 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		int bflgs = ((uae_s16)(src)) < 0;
		int bflgo = ((uae_s16)(0)) < 0;
		int bflgn = ((uae_s16)(newv)) < 0;
		SET_VFLG((bflgs ^ bflgo) & (bflgo ^ bflgn));
		SET_CFLG(bflgs ^ ((bflgs ^ bflgn) & (bflgo ^ bflgn)));
		SET_ZFLG(GET_ZFLG() & (((uae_s16)(newv)) == 0));
		SET_NFLG(((uae_s16)(newv)) < 0);
		SET_XFLG(GET_CFLG());
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(srca + 2, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, srca + 2, 0x1, newv, 1);
		return 22 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(srca, newv >> 16); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, srca + 0, 0x1, newv >> 16, 1);
		return 26 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 26 * CYCLE_UNIT / 2 + count_cycles;
}
/* 26 (4/2) */
/* 4 4,0   */

/* NEGX.L (xxx).W */
uae_u32 REGPARAM2 op_40b8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 16;
	CurrentInstrCycles = 24; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, srca, 2, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 newv = 0 - src - (GET_XFLG() ? 1 : 0);
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(0)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_VFLG((flgs ^ flgo) & (flgo ^ flgn));
	SET_CFLG(flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
	COPY_CARRY();
	SET_ZFLG(GET_ZFLG() & (((uae_s32)(newv)) == 0));
	SET_NFLG(((uae_s32)(newv)) < 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		int bflgs = ((uae_s16)(src)) < 0;
		int bflgo = ((uae_s16)(0)) < 0;
		int bflgn = ((uae_s16)(newv)) < 0;
		SET_VFLG((bflgs ^ bflgo) & (bflgo ^ bflgn));
		SET_CFLG(bflgs ^ ((bflgs ^ bflgn) & (bflgo ^ bflgn)));
		SET_ZFLG(GET_ZFLG() & (((uae_s16)(newv)) == 0));
		SET_NFLG(((uae_s16)(newv)) < 0);
		SET_XFLG(GET_CFLG());
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(srca + 2, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, srca + 2, 0x1, newv, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(srca, newv >> 16); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, srca + 0, 0x1, newv >> 16, 1);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 24 * CYCLE_UNIT / 2 + count_cycles;
}
/* 24 (4/2) */
/* 4 0,0   */

/* NEGX.L (xxx).L */
uae_u32 REGPARAM2 op_40b9_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 16;
	CurrentInstrCycles = 28; 
	uaecptr srca;
	srca = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	srca |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, srca, 2, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 newv = 0 - src - (GET_XFLG() ? 1 : 0);
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(0)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_VFLG((flgs ^ flgo) & (flgo ^ flgn));
	SET_CFLG(flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
	COPY_CARRY();
	SET_ZFLG(GET_ZFLG() & (((uae_s32)(newv)) == 0));
	SET_NFLG(((uae_s32)(newv)) < 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		int bflgs = ((uae_s16)(src)) < 0;
		int bflgo = ((uae_s16)(0)) < 0;
		int bflgn = ((uae_s16)(newv)) < 0;
		SET_VFLG((bflgs ^ bflgo) & (bflgo ^ bflgn));
		SET_CFLG(bflgs ^ ((bflgs ^ bflgn) & (bflgo ^ bflgn)));
		SET_ZFLG(GET_ZFLG() & (((uae_s16)(newv)) == 0));
		SET_NFLG(((uae_s16)(newv)) < 0);
		SET_XFLG(GET_CFLG());
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(srca + 2, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, srca + 2, 0x1, newv, 1);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(srca, newv >> 16); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, srca + 0, 0x1, newv >> 16, 1);
		return 28 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 28 * CYCLE_UNIT / 2 + count_cycles;
}
/* 28 (5/2) */
/* 6 0,0   */

/* MVSR2.W Dn */
uae_u32 REGPARAM2 op_40c0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 32;
	CurrentInstrCycles = 4;  
	if (!regs.s) {
		Exception(8);
		return 0;
	}
	MakeSR();
	regs.ir = regs.irc;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | ((regs.sr) & 0xffff);
	m68k_incpci(2);
	return 4 * CYCLE_UNIT / 2 + count_cycles;
}
/* 4 (1/0) */
/* 2 0,0   */

/* MVSR2.W (An) */
uae_u32 REGPARAM2 op_40d0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 32;
	CurrentInstrCycles = 10; 
	if (!regs.s) {
		Exception(8);
		return 0;
	}
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	MakeSR();
	regs.ir = regs.irc;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	if(srca & 1) {
		m68k_incpci(4);
		exception3_write(opcode, srca, 1, regs.sr & 0xffff, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(srca, regs.sr);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, srca + 0, 0x1, regs.sr, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 10 * CYCLE_UNIT / 2 + count_cycles;
}
/* 10 (1/1) */
/* 2 0,0   */

/* MVSR2.W (An)+ */
uae_u32 REGPARAM2 op_40d8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 32;
	CurrentInstrCycles = 12; 
	if (!regs.s) {
		Exception(8);
		return 0;
	}
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	m68k_areg(regs, srcreg) += 2;
	MakeSR();
	regs.ir = regs.irc;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	if(srca & 1) {
		m68k_incpci(4);
		exception3_write(opcode, srca, 1, regs.sr & 0xffff, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(srca, regs.sr);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, srca + 0, 0x1, regs.sr, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (1/1) */
/* 2 0,0   */

/* MVSR2.W -(An) */
uae_u32 REGPARAM2 op_40e0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 32;
	CurrentInstrCycles = 12; 
	if (!regs.s) {
		Exception(8);
		return 0;
	}
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - 2;
	m68k_areg(regs, srcreg) = srca;
	MakeSR();
	regs.ir = regs.irc;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	if(srca & 1) {
		m68k_incpci(4);
		exception3_write(opcode, srca, 1, regs.sr & 0xffff, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(srca, regs.sr);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, srca + 0, 0x1, regs.sr, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (1/1) */
/* 2 0,0   */

/* MVSR2.W (d16,An) */
uae_u32 REGPARAM2 op_40e8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 32;
	CurrentInstrCycles = 12; 
	if (!regs.s) {
		Exception(8);
		return 0;
	}
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	MakeSR();
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	if(srca & 1) {
		m68k_incpci(6);
		exception3_write(opcode, srca, 1, regs.sr & 0xffff, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(srca, regs.sr);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, srca + 0, 0x1, regs.sr, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (2/1) */
/* 4 0,0   */

/* MVSR2.W (d8,An,Xn) */
uae_u32 REGPARAM2 op_40f0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 32;
	CurrentInstrCycles = 16; 
	if (!regs.s) {
		Exception(8);
		return 0;
	}
	uaecptr srca;
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	MakeSR();
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	if(srca & 1) {
		m68k_incpci(6);
		exception3_write(opcode, srca, 1, regs.sr & 0xffff, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(srca, regs.sr);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, srca + 0, 0x1, regs.sr, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (2/1) */
/* 4 4,0   */

/* MVSR2.W (xxx).W */
uae_u32 REGPARAM2 op_40f8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 32;
	CurrentInstrCycles = 12; 
	if (!regs.s) {
		Exception(8);
		return 0;
	}
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	MakeSR();
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	if(srca & 1) {
		m68k_incpci(6);
		exception3_write(opcode, srca, 1, regs.sr & 0xffff, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(srca, regs.sr);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, srca + 0, 0x1, regs.sr, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (2/1) */
/* 4 0,0   */

/* MVSR2.W (xxx).L */
uae_u32 REGPARAM2 op_40f9_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 32;
	CurrentInstrCycles = 16; 
	if (!regs.s) {
		Exception(8);
		return 0;
	}
	uaecptr srca;
	srca = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	srca |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	MakeSR();
	regs.ir = regs.irc;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	if(srca & 1) {
		m68k_incpci(8);
		exception3_write(opcode, srca, 1, regs.sr & 0xffff, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(srca, regs.sr);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, srca + 0, 0x1, regs.sr, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 6 0,0   */

/* CHK.W Dn,Dn */
uae_u32 REGPARAM2 op_4180_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 80;
	CurrentInstrCycles = 10; 
	uae_s16 src = m68k_dreg(regs, srcreg);
	uae_s16 dst = m68k_dreg(regs, dstreg);
	m68k_incpci(2);
	if (dst > src) {
		setchkundefinedflags(src, dst, 1);
		Exception_cpu(6);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if ((uae_s32)dst < 0) {
		setchkundefinedflags(src, dst, 1);
		Exception_cpu(6);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	setchkundefinedflags(src, dst, 1);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 10 * CYCLE_UNIT / 2 + count_cycles;
}
/* 10 (1/0) */
/* 2 0,0   */

/* CHK.W (An),Dn */
uae_u32 REGPARAM2 op_4190_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 80;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access2(opcode, srca, 1, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	m68k_incpci(2);
	if (dst > src) {
		setchkundefinedflags(src, dst, 1);
		Exception_cpu(6);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	if ((uae_s32)dst < 0) {
		setchkundefinedflags(src, dst, 1);
		Exception_cpu(6);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	setchkundefinedflags(src, dst, 1);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 14 * CYCLE_UNIT / 2 + count_cycles;
}
/* 14 (2/0) */
/* 2 0,0   */

/* CHK.W (An)+,Dn */
uae_u32 REGPARAM2 op_4198_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 80;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_areg(regs, srcreg) += 2 + 0;
		m68k_incpci(2);
		exception3_read_access2(opcode, srca, 1, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) += 2 + 0;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) += 2;
	uae_s16 dst = m68k_dreg(regs, dstreg);
	m68k_incpci(2);
	if (dst > src) {
		setchkundefinedflags(src, dst, 1);
		Exception_cpu(6);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	if ((uae_s32)dst < 0) {
		setchkundefinedflags(src, dst, 1);
		Exception_cpu(6);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	setchkundefinedflags(src, dst, 1);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 14 * CYCLE_UNIT / 2 + count_cycles;
}
/* 14 (2/0) */
/* 2 0,0   */

/* CHK.W -(An),Dn */
uae_u32 REGPARAM2 op_41a0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 80;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - 2;
	if (srca & 1) {
		m68k_areg(regs, srcreg) = srca;
		m68k_incpci(2);
		exception3_read_access2(opcode, srca, 1, 1);
		return 2 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) = srca;
	uae_s16 dst = m68k_dreg(regs, dstreg);
	m68k_incpci(2);
	if (dst > src) {
		setchkundefinedflags(src, dst, 1);
		Exception_cpu(6);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	if ((uae_s32)dst < 0) {
		setchkundefinedflags(src, dst, 1);
		Exception_cpu(6);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	setchkundefinedflags(src, dst, 1);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (2/0) */
/* 2 0,0   */

/* CHK.W (d16,An),Dn */
uae_u32 REGPARAM2 op_41a8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 80;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	m68k_incpci(4);
	if (dst > src) {
		setchkundefinedflags(src, dst, 1);
		Exception_cpu(6);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	if ((uae_s32)dst < 0) {
		setchkundefinedflags(src, dst, 1);
		Exception_cpu(6);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	setchkundefinedflags(src, dst, 1);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (3/0) */
/* 4 0,0   */

/* CHK.W (d8,An,Xn),Dn */
uae_u32 REGPARAM2 op_41b0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 80;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	BusCyclePenalty += 2;
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	m68k_incpci(4);
	if (dst > src) {
		setchkundefinedflags(src, dst, 1);
		Exception_cpu(6);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	if ((uae_s32)dst < 0) {
		setchkundefinedflags(src, dst, 1);
		Exception_cpu(6);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	setchkundefinedflags(src, dst, 1);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (3/0) */
/* 4 4,0   */

/* CHK.W (xxx).W,Dn */
uae_u32 REGPARAM2 op_41b8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 80;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, srca, 1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	m68k_incpci(4);
	if (dst > src) {
		setchkundefinedflags(src, dst, 1);
		Exception_cpu(6);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	if ((uae_s32)dst < 0) {
		setchkundefinedflags(src, dst, 1);
		Exception_cpu(6);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	setchkundefinedflags(src, dst, 1);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (3/0) */
/* 4 0,0   */

/* CHK.W (xxx).L,Dn */
uae_u32 REGPARAM2 op_41b9_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 80;
	CurrentInstrCycles = 22; 
	uaecptr srca;
	srca = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	srca |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, srca, 1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	m68k_incpci(6);
	if (dst > src) {
		setchkundefinedflags(src, dst, 1);
		Exception_cpu(6);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	if ((uae_s32)dst < 0) {
		setchkundefinedflags(src, dst, 1);
		Exception_cpu(6);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	setchkundefinedflags(src, dst, 1);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 22 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 22 * CYCLE_UNIT / 2 + count_cycles;
}
/* 22 (4/0) */
/* 6 0,0   */

/* CHK.W (d16,PC),Dn */
uae_u32 REGPARAM2 op_41ba_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 80;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	srca = m68k_getpci() + 2;
	srca += (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	m68k_incpci(4);
	if (dst > src) {
		setchkundefinedflags(src, dst, 1);
		Exception_cpu(6);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	if ((uae_s32)dst < 0) {
		setchkundefinedflags(src, dst, 1);
		Exception_cpu(6);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	setchkundefinedflags(src, dst, 1);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (3/0) */
/* 4 0,0   */

/* CHK.W (d8,PC,Xn),Dn */
uae_u32 REGPARAM2 op_41bb_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 80;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	uaecptr tmppc = m68k_getpci() + 2;
	BusCyclePenalty += 2;
	srca = get_disp_ea_000(tmppc, get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	m68k_incpci(4);
	if (dst > src) {
		setchkundefinedflags(src, dst, 1);
		Exception_cpu(6);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	if ((uae_s32)dst < 0) {
		setchkundefinedflags(src, dst, 1);
		Exception_cpu(6);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	setchkundefinedflags(src, dst, 1);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (3/0) */
/* 4 4,0   */

/* CHK.W #<data>.W,Dn */
uae_u32 REGPARAM2 op_41bc_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 80;
	CurrentInstrCycles = 14; 
	uae_s16 src = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	m68k_incpci(4);
	if (dst > src) {
		setchkundefinedflags(src, dst, 1);
		Exception_cpu(6);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	if ((uae_s32)dst < 0) {
		setchkundefinedflags(src, dst, 1);
		Exception_cpu(6);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	setchkundefinedflags(src, dst, 1);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 14 * CYCLE_UNIT / 2 + count_cycles;
}
/* 14 (2/0) */
/* 4 0,0   */

/* LEA.L (An),An */
uae_u32 REGPARAM2 op_41d0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 56;
	CurrentInstrCycles = 4;  
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	m68k_areg(regs, dstreg) = (srca);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 4 * CYCLE_UNIT / 2 + count_cycles;
}
/* 4 (1/0) */
/* 2 0,0   */

/* LEA.L (d16,An),An */
uae_u32 REGPARAM2 op_41e8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 56;
	CurrentInstrCycles = 8;  
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) = (srca);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8 (2/0) */
/* 4 0,0   */

/* LEA.L (d8,An,Xn),An */
uae_u32 REGPARAM2 op_41f0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 56;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) = (srca);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 14 * CYCLE_UNIT / 2 + count_cycles;
}
/* 14 (2/0) */
/* 4 4,0   */

/* LEA.L (xxx).W,An */
uae_u32 REGPARAM2 op_41f8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 56;
	CurrentInstrCycles = 8;  
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) = (srca);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8 (2/0) */
/* 4 0,0   */

/* LEA.L (xxx).L,An */
uae_u32 REGPARAM2 op_41f9_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 56;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	srca |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) = (srca);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (3/0) */
/* 6 0,0   */

/* LEA.L (d16,PC),An */
uae_u32 REGPARAM2 op_41fa_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 56;
	CurrentInstrCycles = 8;  
	uaecptr srca;
	srca = m68k_getpci() + 2;
	srca += (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) = (srca);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8 (2/0) */
/* 4 0,0   */

/* LEA.L (d8,PC,Xn),An */
uae_u32 REGPARAM2 op_41fb_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 56;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	uaecptr tmppc = m68k_getpci() + 2;
	srca = get_disp_ea_000(tmppc, get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) = (srca);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 14 * CYCLE_UNIT / 2 + count_cycles;
}
/* 14 (2/0) */
/* 4 4,0   */

/* CLR.B Dn */
uae_u32 REGPARAM2 op_4200_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 18;
	CurrentInstrCycles = 4;  
	struct flag_struct oldflags;
	oldflags.cznv = regflags.cznv;
	regs.ir = regs.irc;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();
		SET_ZFLG(1);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(0)) == 0);
	SET_NFLG(((uae_s8)(0)) < 0);
	m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((0) & 0xff);
	m68k_incpci(2);
	return 4 * CYCLE_UNIT / 2 + count_cycles;
}
/* 4 (1/0) */
/* 2 0,0   */

/* CLR.B (An) */
uae_u32 REGPARAM2 op_4210_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 18;
	CurrentInstrCycles = 4;  
	int loop_mode = regs.loop_mode;
	struct flag_struct oldflags;
	oldflags.cznv = regflags.cznv;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_000_prefetch(4);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			int pcoffset = 0;
			CLEAR_CZNV();
			SET_ZFLG(1);
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return 4 * CYCLE_UNIT / 2 + count_cycles;
		}
	} else {
		loop_mode = 0;
		loop_mode |= 2;
		loop_mode |= 4 << 16;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(0)) == 0);
	SET_NFLG(((uae_s8)(0)) < 0);
	if(loop_mode & 0xfffe) {
		count_cycles += (loop_mode & 0xfffe) * CYCLE_UNIT / 2;
		loop_mode &= 0xffff0000;
		loop_mode |= 1;
	}
	put_byte_000(srca, 0);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		regflags.cznv = oldflags.cznv;
		exception2_write(opcode, srca + 0, 0x0, 0, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return 4 * CYCLE_UNIT / 2 + count_cycles;
}
/* 4+ (0/1) */
/* 2 0,0   */

/* CLR.B (An)+ */
uae_u32 REGPARAM2 op_4218_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 18;
	CurrentInstrCycles = 4;  
	int loop_mode = regs.loop_mode;
	struct flag_struct oldflags;
	oldflags.cznv = regflags.cznv;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_000_prefetch(4);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			int pcoffset = 0;
			CLEAR_CZNV();
			SET_ZFLG(1);
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return 4 * CYCLE_UNIT / 2 + count_cycles;
		}
	} else {
		loop_mode = 0;
		loop_mode |= 2;
		loop_mode |= 4 << 16;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(0)) == 0);
	SET_NFLG(((uae_s8)(0)) < 0);
	if(loop_mode & 0xfffe) {
		count_cycles += (loop_mode & 0xfffe) * CYCLE_UNIT / 2;
		loop_mode &= 0xffff0000;
		loop_mode |= 1;
	}
	put_byte_000(srca, 0);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		regflags.cznv = oldflags.cznv;
		m68k_areg(regs, srcreg) -= areg_byteinc[srcreg];
		exception2_write(opcode, srca + 0, 0x0, 0, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return 4 * CYCLE_UNIT / 2 + count_cycles;
}
/* 4+ (0/1) */
/* 2 0,0   */

/* CLR.B -(An) */
uae_u32 REGPARAM2 op_4220_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 18;
	CurrentInstrCycles = 6;  
	int loop_mode = regs.loop_mode;
	struct flag_struct oldflags;
	oldflags.cznv = regflags.cznv;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
	m68k_areg(regs, srcreg) = srca;
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_000_prefetch(4);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			int pcoffset = 0;
			CLEAR_CZNV();
			SET_ZFLG(1);
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return 2 * CYCLE_UNIT / 2 + count_cycles;
		}
	} else {
		loop_mode = 0;
		loop_mode |= 2;
		loop_mode |= 4 << 16;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(0)) == 0);
	SET_NFLG(((uae_s8)(0)) < 0);
	if(loop_mode & 0xfffe) {
		count_cycles += (loop_mode & 0xfffe) * CYCLE_UNIT / 2;
		loop_mode &= 0xffff0000;
		loop_mode |= 1;
	}
	put_byte_000(srca, 0);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		regflags.cznv = oldflags.cznv;
		m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
		exception2_write(opcode, srca + 0, 0x0, 0, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return 6 * CYCLE_UNIT / 2 + count_cycles;
}
/* 6+ (0/1) */
/* 2 0,0   */

/* CLR.B (d16,An) */
uae_u32 REGPARAM2 op_4228_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 18;
	CurrentInstrCycles = 12; 
	struct flag_struct oldflags;
	oldflags.cznv = regflags.cznv;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();
		SET_ZFLG(1);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(0)) == 0);
	SET_NFLG(((uae_s8)(0)) < 0);
	put_byte_000(srca, 0);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, srca + 0, 0x0, 0, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (2/1) */
/* 4 0,0   */

/* CLR.B (d8,An,Xn) */
uae_u32 REGPARAM2 op_4230_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 18;
	CurrentInstrCycles = 16; 
	struct flag_struct oldflags;
	oldflags.cznv = regflags.cznv;
	uaecptr srca;
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();
		SET_ZFLG(1);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(0)) == 0);
	SET_NFLG(((uae_s8)(0)) < 0);
	put_byte_000(srca, 0);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, srca + 0, 0x0, 0, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (2/1) */
/* 4 4,0   */

/* CLR.B (xxx).W */
uae_u32 REGPARAM2 op_4238_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 18;
	CurrentInstrCycles = 12; 
	struct flag_struct oldflags;
	oldflags.cznv = regflags.cznv;
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();
		SET_ZFLG(1);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(0)) == 0);
	SET_NFLG(((uae_s8)(0)) < 0);
	put_byte_000(srca, 0);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, srca + 0, 0x0, 0, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (2/1) */
/* 4 0,0   */

/* CLR.B (xxx).L */
uae_u32 REGPARAM2 op_4239_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 18;
	CurrentInstrCycles = 16; 
	struct flag_struct oldflags;
	oldflags.cznv = regflags.cznv;
	uaecptr srca;
	srca = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	srca |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();
		SET_ZFLG(1);
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(0)) == 0);
	SET_NFLG(((uae_s8)(0)) < 0);
	put_byte_000(srca, 0);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, srca + 0, 0x0, 0, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 6 0,0   */

/* CLR.W Dn */
uae_u32 REGPARAM2 op_4240_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 18;
	CurrentInstrCycles = 4;  
	struct flag_struct oldflags;
	oldflags.cznv = regflags.cznv;
	regs.ir = regs.irc;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();
		SET_ZFLG(1);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(0)) == 0);
	SET_NFLG(((uae_s16)(0)) < 0);
	m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | ((0) & 0xffff);
	m68k_incpci(2);
	return 4 * CYCLE_UNIT / 2 + count_cycles;
}
/* 4 (1/0) */
/* 2 0,0   */

/* CLR.W (An) */
uae_u32 REGPARAM2 op_4250_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 18;
	CurrentInstrCycles = 4;  
	int loop_mode = regs.loop_mode;
	struct flag_struct oldflags;
	oldflags.cznv = regflags.cznv;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if(srca & 1) {
		m68k_incpci(4);
		exception3_write(opcode, srca, 1, 0, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_000_prefetch(4);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			int pcoffset = 0;
			CLEAR_CZNV();
			SET_ZFLG(1);
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return 4 * CYCLE_UNIT / 2 + count_cycles;
		}
	} else {
		loop_mode = 0;
		loop_mode |= 2;
		loop_mode |= 4 << 16;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(0)) == 0);
	SET_NFLG(((uae_s16)(0)) < 0);
	if(loop_mode & 0xfffe) {
		count_cycles += (loop_mode & 0xfffe) * CYCLE_UNIT / 2;
		loop_mode &= 0xffff0000;
		loop_mode |= 1;
	}
	put_word_000(srca, 0);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		regflags.cznv = oldflags.cznv;
		exception2_write(opcode, srca + 0, 0x1, 0, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return 4 * CYCLE_UNIT / 2 + count_cycles;
}
/* 4+ (0/1) */
/* 2 0,0   */

/* CLR.W (An)+ */
uae_u32 REGPARAM2 op_4258_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 18;
	CurrentInstrCycles = 4;  
	int loop_mode = regs.loop_mode;
	struct flag_struct oldflags;
	oldflags.cznv = regflags.cznv;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	m68k_areg(regs, srcreg) += 2;
	if(srca & 1) {
		m68k_areg(regs, srcreg) -= 2;
		m68k_incpci(4);
		exception3_write(opcode, srca, 1, 0, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_000_prefetch(4);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			int pcoffset = 0;
			CLEAR_CZNV();
			SET_ZFLG(1);
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return 4 * CYCLE_UNIT / 2 + count_cycles;
		}
	} else {
		loop_mode = 0;
		loop_mode |= 2;
		loop_mode |= 4 << 16;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(0)) == 0);
	SET_NFLG(((uae_s16)(0)) < 0);
	if(loop_mode & 0xfffe) {
		count_cycles += (loop_mode & 0xfffe) * CYCLE_UNIT / 2;
		loop_mode &= 0xffff0000;
		loop_mode |= 1;
	}
	put_word_000(srca, 0);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		regflags.cznv = oldflags.cznv;
		m68k_areg(regs, srcreg) -= 2;
		exception2_write(opcode, srca + 0, 0x1, 0, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return 4 * CYCLE_UNIT / 2 + count_cycles;
}
/* 4+ (0/1) */
/* 2 0,0   */

/* CLR.W -(An) */
uae_u32 REGPARAM2 op_4260_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 18;
	CurrentInstrCycles = 6;  
	int loop_mode = regs.loop_mode;
	struct flag_struct oldflags;
	oldflags.cznv = regflags.cznv;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - 2;
	m68k_areg(regs, srcreg) = srca;
	if(srca & 1) {
		m68k_areg(regs, srcreg) += 2;
		m68k_incpci(4);
		exception3_write(opcode, srca, 1, 0, 1);
		return 2 * CYCLE_UNIT / 2 + count_cycles;
	}
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_000_prefetch(4);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			int pcoffset = 0;
			CLEAR_CZNV();
			SET_ZFLG(1);
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return 2 * CYCLE_UNIT / 2 + count_cycles;
		}
	} else {
		loop_mode = 0;
		loop_mode |= 2;
		loop_mode |= 4 << 16;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(0)) == 0);
	SET_NFLG(((uae_s16)(0)) < 0);
	if(loop_mode & 0xfffe) {
		count_cycles += (loop_mode & 0xfffe) * CYCLE_UNIT / 2;
		loop_mode &= 0xffff0000;
		loop_mode |= 1;
	}
	put_word_000(srca, 0);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		regflags.cznv = oldflags.cznv;
		m68k_areg(regs, srcreg) += 2;
		exception2_write(opcode, srca + 0, 0x1, 0, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return 6 * CYCLE_UNIT / 2 + count_cycles;
}
/* 6+ (0/1) */
/* 2 0,0   */

/* CLR.W (d16,An) */
uae_u32 REGPARAM2 op_4268_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 18;
	CurrentInstrCycles = 12; 
	struct flag_struct oldflags;
	oldflags.cznv = regflags.cznv;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if(srca & 1) {
		get_word_000_prefetch(6);
		CLEAR_CZNV();
		SET_ZFLG(((uae_s16)(0)) == 0);
		SET_NFLG(((uae_s16)(0)) < 0);
		m68k_incpci(6);
		exception3_write(opcode, srca, 1, 0, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();
		SET_ZFLG(1);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(0)) == 0);
	SET_NFLG(((uae_s16)(0)) < 0);
	put_word_000(srca, 0);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, srca + 0, 0x1, 0, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (2/1) */
/* 4 0,0   */

/* CLR.W (d8,An,Xn) */
uae_u32 REGPARAM2 op_4270_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 18;
	CurrentInstrCycles = 16; 
	struct flag_struct oldflags;
	oldflags.cznv = regflags.cznv;
	uaecptr srca;
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	if(srca & 1) {
		get_word_000_prefetch(6);
		CLEAR_CZNV();
		SET_ZFLG(((uae_s16)(0)) == 0);
		SET_NFLG(((uae_s16)(0)) < 0);
		m68k_incpci(6);
		exception3_write(opcode, srca, 1, 0, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();
		SET_ZFLG(1);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(0)) == 0);
	SET_NFLG(((uae_s16)(0)) < 0);
	put_word_000(srca, 0);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, srca + 0, 0x1, 0, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (2/1) */
/* 4 4,0   */

/* CLR.W (xxx).W */
uae_u32 REGPARAM2 op_4278_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 18;
	CurrentInstrCycles = 12; 
	struct flag_struct oldflags;
	oldflags.cznv = regflags.cznv;
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if(srca & 1) {
		get_word_000_prefetch(6);
		CLEAR_CZNV();
		SET_ZFLG(((uae_s16)(0)) == 0);
		SET_NFLG(((uae_s16)(0)) < 0);
		m68k_incpci(6);
		exception3_write(opcode, srca, 1, 0, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();
		SET_ZFLG(1);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(0)) == 0);
	SET_NFLG(((uae_s16)(0)) < 0);
	put_word_000(srca, 0);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, srca + 0, 0x1, 0, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (2/1) */
/* 4 0,0   */

/* CLR.W (xxx).L */
uae_u32 REGPARAM2 op_4279_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 18;
	CurrentInstrCycles = 16; 
	struct flag_struct oldflags;
	oldflags.cznv = regflags.cznv;
	uaecptr srca;
	srca = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	srca |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	if(srca & 1) {
		get_word_000_prefetch(8);
		CLEAR_CZNV();
		SET_ZFLG(((uae_s16)(0)) == 0);
		SET_NFLG(((uae_s16)(0)) < 0);
		m68k_incpci(8);
		exception3_write(opcode, srca, 1, 0, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();
		SET_ZFLG(1);
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(0)) == 0);
	SET_NFLG(((uae_s16)(0)) < 0);
	put_word_000(srca, 0);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, srca + 0, 0x1, 0, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 6 0,0   */

/* CLR.L Dn */
uae_u32 REGPARAM2 op_4280_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 18;
	CurrentInstrCycles = 6;  
	struct flag_struct oldflags;
	oldflags.cznv = regflags.cznv;
	regs.ir = regs.irc;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();
		SET_ZFLG(1);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(0)) == 0);
	SET_NFLG(((uae_s32)(0)) < 0);
	m68k_dreg(regs, srcreg) = (0);
	m68k_incpci(2);
	return 6 * CYCLE_UNIT / 2 + count_cycles;
}
/* 6 (1/0) */
/* 2 0,0   */

/* CLR.L (An) */
uae_u32 REGPARAM2 op_4290_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 18;
	CurrentInstrCycles = 8;  
	int loop_mode = regs.loop_mode;
	struct flag_struct oldflags;
	oldflags.cznv = regflags.cznv;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if(srca & 1) {
		m68k_incpci(4);
		exception3_write(opcode, srca, 1, 0, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_000_prefetch(4);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			int pcoffset = 0;
			CLEAR_CZNV();
			SET_ZFLG(1);
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return 4 * CYCLE_UNIT / 2 + count_cycles;
		}
	} else {
		loop_mode = 0;
		loop_mode |= 2;
		loop_mode |= 4 << 16;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(0)) == 0);
	SET_NFLG(((uae_s32)(0)) < 0);
	if(loop_mode & 0xfffe) {
		count_cycles += (loop_mode & 0xfffe) * CYCLE_UNIT / 2;
		loop_mode &= 0xffff0000;
		loop_mode |= 1;
	}
	put_word_000(srca + 2, 0);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		regflags.cznv = oldflags.cznv;
		exception2_write(opcode, srca + 2, 0x1, 0, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(srca, 0 >> 16); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		regflags.cznv = oldflags.cznv;
		exception2_write(opcode, srca + 0, 0x1, 0 >> 16, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8+ (0/2) */
/* 2 0,0   */

/* CLR.L (An)+ */
uae_u32 REGPARAM2 op_4298_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 18;
	CurrentInstrCycles = 8;  
	int loop_mode = regs.loop_mode;
	struct flag_struct oldflags;
	oldflags.cznv = regflags.cznv;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	m68k_areg(regs, srcreg) += 4;
	if(srca & 1) {
		m68k_areg(regs, srcreg) -= 4;
		m68k_incpci(4);
		exception3_write(opcode, srca, 1, 0, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_000_prefetch(4);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			int pcoffset = 0;
			CLEAR_CZNV();
			SET_ZFLG(1);
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return 4 * CYCLE_UNIT / 2 + count_cycles;
		}
	} else {
		loop_mode = 0;
		loop_mode |= 2;
		loop_mode |= 4 << 16;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(0)) == 0);
	SET_NFLG(((uae_s32)(0)) < 0);
	if(loop_mode & 0xfffe) {
		count_cycles += (loop_mode & 0xfffe) * CYCLE_UNIT / 2;
		loop_mode &= 0xffff0000;
		loop_mode |= 1;
	}
	put_word_000(srca + 2, 0);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		regflags.cznv = oldflags.cznv;
		m68k_areg(regs, srcreg) -= 4;
		exception2_write(opcode, srca + 2, 0x1, 0, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(srca, 0 >> 16); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		regflags.cznv = oldflags.cznv;
		m68k_areg(regs, srcreg) -= 4;
		exception2_write(opcode, srca + 0, 0x1, 0 >> 16, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8+ (0/2) */
/* 2 0,0   */

/* CLR.L -(An) */
uae_u32 REGPARAM2 op_42a0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 18;
	CurrentInstrCycles = 10; 
	int loop_mode = regs.loop_mode;
	struct flag_struct oldflags;
	oldflags.cznv = regflags.cznv;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - 4;
	m68k_areg(regs, srcreg) = srca;
	if(srca & 1) {
		m68k_areg(regs, srcreg) += 4;
		srca += 2;
		m68k_incpci(4);
		exception3_write(opcode, srca, 1, 0, 1);
		return 2 * CYCLE_UNIT / 2 + count_cycles;
	}
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_000_prefetch(4);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			int pcoffset = 0;
			CLEAR_CZNV();
			SET_ZFLG(1);
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return 2 * CYCLE_UNIT / 2 + count_cycles;
		}
	} else {
		loop_mode = 0;
		loop_mode |= 2;
		loop_mode |= 4 << 16;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(0)) == 0);
	SET_NFLG(((uae_s32)(0)) < 0);
	if(loop_mode & 0xfffe) {
		count_cycles += (loop_mode & 0xfffe) * CYCLE_UNIT / 2;
		loop_mode &= 0xffff0000;
		loop_mode |= 1;
	}
	put_word_000(srca + 2, 0);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		regflags.cznv = oldflags.cznv;
		m68k_areg(regs, srcreg) += 4;
		exception2_write(opcode, srca + 2, 0x1, 0, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(srca, 0 >> 16); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		regflags.cznv = oldflags.cznv;
		m68k_areg(regs, srcreg) += 4;
		exception2_write(opcode, srca + 0, 0x1, 0 >> 16, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return 10 * CYCLE_UNIT / 2 + count_cycles;
}
/* 10+ (0/2) */
/* 2 0,0   */

/* CLR.L (d16,An) */
uae_u32 REGPARAM2 op_42a8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 18;
	CurrentInstrCycles = 16; 
	struct flag_struct oldflags;
	oldflags.cznv = regflags.cznv;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if(srca & 1) {
		srca += 2;
		get_word_000_prefetch(6);
		CLEAR_CZNV();
		SET_ZFLG(((uae_s32)(0)) == 0);
		SET_NFLG(((uae_s32)(0)) < 0);
		m68k_incpci(6);
		exception3_write(opcode, srca, 1, 0, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();
		SET_ZFLG(1);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(0)) == 0);
	SET_NFLG(((uae_s32)(0)) < 0);
	put_word_000(srca + 2, 0);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, srca + 2, 0x1, 0, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(srca, 0 >> 16); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, srca + 0, 0x1, 0 >> 16, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (2/2) */
/* 4 0,0   */

/* CLR.L (d8,An,Xn) */
uae_u32 REGPARAM2 op_42b0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 18;
	CurrentInstrCycles = 20; 
	struct flag_struct oldflags;
	oldflags.cznv = regflags.cznv;
	uaecptr srca;
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	if(srca & 1) {
		srca += 2;
		get_word_000_prefetch(6);
		CLEAR_CZNV();
		SET_ZFLG(((uae_s32)(0)) == 0);
		SET_NFLG(((uae_s32)(0)) < 0);
		m68k_incpci(6);
		exception3_write(opcode, srca, 1, 0, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();
		SET_ZFLG(1);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(0)) == 0);
	SET_NFLG(((uae_s32)(0)) < 0);
	put_word_000(srca + 2, 0);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, srca + 2, 0x1, 0, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(srca, 0 >> 16); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, srca + 0, 0x1, 0 >> 16, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (2/2) */
/* 4 4,0   */

/* CLR.L (xxx).W */
uae_u32 REGPARAM2 op_42b8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 18;
	CurrentInstrCycles = 16; 
	struct flag_struct oldflags;
	oldflags.cznv = regflags.cznv;
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if(srca & 1) {
		srca += 2;
		get_word_000_prefetch(6);
		CLEAR_CZNV();
		SET_ZFLG(((uae_s32)(0)) == 0);
		SET_NFLG(((uae_s32)(0)) < 0);
		m68k_incpci(6);
		exception3_write(opcode, srca, 1, 0, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();
		SET_ZFLG(1);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(0)) == 0);
	SET_NFLG(((uae_s32)(0)) < 0);
	put_word_000(srca + 2, 0);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, srca + 2, 0x1, 0, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(srca, 0 >> 16); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, srca + 0, 0x1, 0 >> 16, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (2/2) */
/* 4 0,0   */

/* CLR.L (xxx).L */
uae_u32 REGPARAM2 op_42b9_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 18;
	CurrentInstrCycles = 20; 
	struct flag_struct oldflags;
	oldflags.cznv = regflags.cznv;
	uaecptr srca;
	srca = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	srca |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	if(srca & 1) {
		srca += 2;
		get_word_000_prefetch(8);
		CLEAR_CZNV();
		SET_ZFLG(((uae_s32)(0)) == 0);
		SET_NFLG(((uae_s32)(0)) < 0);
		m68k_incpci(8);
		exception3_write(opcode, srca, 1, 0, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();
		SET_ZFLG(1);
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(0)) == 0);
	SET_NFLG(((uae_s32)(0)) < 0);
	put_word_000(srca + 2, 0);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, srca + 2, 0x1, 0, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(srca, 0 >> 16); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, srca + 0, 0x1, 0 >> 16, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (3/2) */
/* 6 0,0   */

/* MVSR2.B Dn */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_42c0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 32;
	CurrentInstrCycles = 4;  
	MakeSR();
	regs.ir = regs.irc;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | ((regs.sr & 0xff) & 0xffff);
	m68k_incpci(2);
	return 4 * CYCLE_UNIT / 2 + count_cycles;
}
/* 4 (1/0) */
/* 2 0,0   */

#endif
/* MVSR2.B (An) */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_42d0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 32;
	CurrentInstrCycles = 10; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	MakeSR();
	regs.ir = regs.irc;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	if(srca & 1) {
		m68k_incpci(4);
		exception3_write(opcode, srca, 1, regs.sr & 0xff, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(srca, regs.sr & 0xff);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, srca + 0, 0x1, regs.sr & 0xff, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 10 * CYCLE_UNIT / 2 + count_cycles;
}
/* 10 (1/1) */
/* 2 0,0   */

#endif
/* MVSR2.B (An)+ */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_42d8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 32;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	m68k_areg(regs, srcreg) += 2;
	MakeSR();
	regs.ir = regs.irc;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	if(srca & 1) {
		m68k_incpci(4);
		exception3_write(opcode, srca, 1, regs.sr & 0xff, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(srca, regs.sr & 0xff);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, srca + 0, 0x1, regs.sr & 0xff, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (1/1) */
/* 2 0,0   */

#endif
/* MVSR2.B -(An) */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_42e0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 32;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - 2;
	m68k_areg(regs, srcreg) = srca;
	MakeSR();
	regs.ir = regs.irc;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	if(srca & 1) {
		m68k_incpci(4);
		exception3_write(opcode, srca, 1, regs.sr & 0xff, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(srca, regs.sr & 0xff);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, srca + 0, 0x1, regs.sr & 0xff, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (1/1) */
/* 2 0,0   */

#endif
/* MVSR2.B (d16,An) */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_42e8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 32;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	MakeSR();
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	if(srca & 1) {
		m68k_incpci(6);
		exception3_write(opcode, srca, 1, regs.sr & 0xff, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(srca, regs.sr & 0xff);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, srca + 0, 0x1, regs.sr & 0xff, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (2/1) */
/* 4 0,0   */

#endif
/* MVSR2.B (d8,An,Xn) */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_42f0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 32;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	MakeSR();
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	if(srca & 1) {
		m68k_incpci(6);
		exception3_write(opcode, srca, 1, regs.sr & 0xff, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(srca, regs.sr & 0xff);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, srca + 0, 0x1, regs.sr & 0xff, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (2/1) */
/* 4 4,0   */

#endif
/* MVSR2.B (xxx).W */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_42f8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 32;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	MakeSR();
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	if(srca & 1) {
		m68k_incpci(6);
		exception3_write(opcode, srca, 1, regs.sr & 0xff, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(srca, regs.sr & 0xff);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, srca + 0, 0x1, regs.sr & 0xff, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (2/1) */
/* 4 0,0   */

#endif
/* MVSR2.B (xxx).L */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_42f9_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 32;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	srca |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	MakeSR();
	regs.ir = regs.irc;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	if(srca & 1) {
		m68k_incpci(8);
		exception3_write(opcode, srca, 1, regs.sr & 0xff, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(srca, regs.sr & 0xff);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, srca + 0, 0x1, regs.sr & 0xff, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 6 0,0   */

#endif
/* NEG.B Dn */
uae_u32 REGPARAM2 op_4400_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 15;
	CurrentInstrCycles = 4;  
	uae_s8 src = m68k_dreg(regs, srcreg);
	uae_u32 dst = ((uae_u8)(0)) - ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(0)) < 0;
	int flgn = ((uae_s8)(dst)) < 0;
	SET_ZFLG(((uae_s8)(dst)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u8)(src)) > ((uae_u8)(0)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((dst) & 0xff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 4 * CYCLE_UNIT / 2 + count_cycles;
}
/* 4 (1/0) */
/* 2 0,0   */

/* NEG.B (An) */
uae_u32 REGPARAM2 op_4410_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 15;
	CurrentInstrCycles = 8;  
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 dst = ((uae_u8)(0)) - ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(0)) < 0;
	int flgn = ((uae_s8)(dst)) < 0;
	SET_ZFLG(((uae_s8)(dst)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u8)(src)) > ((uae_u8)(0)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_000_prefetch(4);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return 4 * CYCLE_UNIT / 2 + count_cycles;
		}
		opcode = regs.ir;
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	if(loop_mode & 0xfffe) {
		count_cycles += (loop_mode & 0xfffe) * CYCLE_UNIT / 2;
		loop_mode = 1;
	}
	put_byte_000(srca, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, srca + 0, 0x0, dst, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8+ (1/1) */
/* 2 0,0   */

/* NEG.B (An)+ */
uae_u32 REGPARAM2 op_4418_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 15;
	CurrentInstrCycles = 8;  
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
	uae_u32 dst = ((uae_u8)(0)) - ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(0)) < 0;
	int flgn = ((uae_s8)(dst)) < 0;
	SET_ZFLG(((uae_s8)(dst)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u8)(src)) > ((uae_u8)(0)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_000_prefetch(4);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return 4 * CYCLE_UNIT / 2 + count_cycles;
		}
		opcode = regs.ir;
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	if(loop_mode & 0xfffe) {
		count_cycles += (loop_mode & 0xfffe) * CYCLE_UNIT / 2;
		loop_mode = 1;
	}
	put_byte_000(srca, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, srca + 0, 0x0, dst, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8+ (1/1) */
/* 2 0,0   */

/* NEG.B -(An) */
uae_u32 REGPARAM2 op_4420_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 15;
	CurrentInstrCycles = 10; 
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) = srca;
	uae_u32 dst = ((uae_u8)(0)) - ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(0)) < 0;
	int flgn = ((uae_s8)(dst)) < 0;
	SET_ZFLG(((uae_s8)(dst)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u8)(src)) > ((uae_u8)(0)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_000_prefetch(4);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return 6 * CYCLE_UNIT / 2 + count_cycles;
		}
		opcode = regs.ir;
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	if(loop_mode & 0xfffe) {
		count_cycles += (loop_mode & 0xfffe) * CYCLE_UNIT / 2;
		loop_mode = 1;
	}
	put_byte_000(srca, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, srca + 0, 0x0, dst, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return 10 * CYCLE_UNIT / 2 + count_cycles;
}
/* 10+ (1/1) */
/* 2 0,0   */

/* NEG.B (d16,An) */
uae_u32 REGPARAM2 op_4428_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 15;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 dst = ((uae_u8)(0)) - ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(0)) < 0;
	int flgn = ((uae_s8)(dst)) < 0;
	SET_ZFLG(((uae_s8)(dst)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u8)(src)) > ((uae_u8)(0)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_byte_000(srca, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, srca + 0, 0x0, dst, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 4 0,0   */

/* NEG.B (d8,An,Xn) */
uae_u32 REGPARAM2 op_4430_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 15;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	BusCyclePenalty += 2;
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 dst = ((uae_u8)(0)) - ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(0)) < 0;
	int flgn = ((uae_s8)(dst)) < 0;
	SET_ZFLG(((uae_s8)(dst)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u8)(src)) > ((uae_u8)(0)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_byte_000(srca, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, srca + 0, 0x0, dst, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (3/1) */
/* 4 4,0   */

/* NEG.B (xxx).W */
uae_u32 REGPARAM2 op_4438_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 15;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 dst = ((uae_u8)(0)) - ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(0)) < 0;
	int flgn = ((uae_s8)(dst)) < 0;
	SET_ZFLG(((uae_s8)(dst)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u8)(src)) > ((uae_u8)(0)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_byte_000(srca, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, srca + 0, 0x0, dst, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 4 0,0   */

/* NEG.B (xxx).L */
uae_u32 REGPARAM2 op_4439_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 15;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	srca = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	srca |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 dst = ((uae_u8)(0)) - ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(0)) < 0;
	int flgn = ((uae_s8)(dst)) < 0;
	SET_ZFLG(((uae_s8)(dst)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u8)(src)) > ((uae_u8)(0)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_byte_000(srca, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, srca + 0, 0x0, dst, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (4/1) */
/* 6 0,0   */

/* NEG.W Dn */
uae_u32 REGPARAM2 op_4440_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 15;
	CurrentInstrCycles = 4;  
	uae_s16 src = m68k_dreg(regs, srcreg);
	uae_u32 dst = ((uae_u16)(0)) - ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(0)) < 0;
	int flgn = ((uae_s16)(dst)) < 0;
	SET_ZFLG(((uae_s16)(dst)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u16)(src)) > ((uae_u16)(0)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | ((dst) & 0xffff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 4 * CYCLE_UNIT / 2 + count_cycles;
}
/* 4 (1/0) */
/* 2 0,0   */

/* NEG.W (An) */
uae_u32 REGPARAM2 op_4450_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 15;
	CurrentInstrCycles = 8;  
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access2(opcode, srca, 1, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 dst = ((uae_u16)(0)) - ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(0)) < 0;
	int flgn = ((uae_s16)(dst)) < 0;
	SET_ZFLG(((uae_s16)(dst)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u16)(src)) > ((uae_u16)(0)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_000_prefetch(4);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return 4 * CYCLE_UNIT / 2 + count_cycles;
		}
		opcode = regs.ir;
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	if(loop_mode & 0xfffe) {
		count_cycles += (loop_mode & 0xfffe) * CYCLE_UNIT / 2;
		loop_mode = 1;
	}
	put_word_000(srca, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, srca + 0, 0x1, dst, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8+ (1/1) */
/* 2 0,0   */

/* NEG.W (An)+ */
uae_u32 REGPARAM2 op_4458_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 15;
	CurrentInstrCycles = 8;  
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_areg(regs, srcreg) += 2 + 0;
		m68k_incpci(2);
		exception3_read_access2(opcode, srca, 1, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) += 2 + 0;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) += 2;
	uae_u32 dst = ((uae_u16)(0)) - ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(0)) < 0;
	int flgn = ((uae_s16)(dst)) < 0;
	SET_ZFLG(((uae_s16)(dst)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u16)(src)) > ((uae_u16)(0)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_000_prefetch(4);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return 4 * CYCLE_UNIT / 2 + count_cycles;
		}
		opcode = regs.ir;
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	if(loop_mode & 0xfffe) {
		count_cycles += (loop_mode & 0xfffe) * CYCLE_UNIT / 2;
		loop_mode = 1;
	}
	put_word_000(srca, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, srca + 0, 0x1, dst, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8+ (1/1) */
/* 2 0,0   */

/* NEG.W -(An) */
uae_u32 REGPARAM2 op_4460_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 15;
	CurrentInstrCycles = 10; 
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - 2;
	if (srca & 1) {
		m68k_areg(regs, srcreg) = srca;
		m68k_incpci(2);
		exception3_read_access2(opcode, srca, 1, 1);
		return 2 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) = srca;
	uae_u32 dst = ((uae_u16)(0)) - ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(0)) < 0;
	int flgn = ((uae_s16)(dst)) < 0;
	SET_ZFLG(((uae_s16)(dst)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u16)(src)) > ((uae_u16)(0)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_000_prefetch(4);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return 6 * CYCLE_UNIT / 2 + count_cycles;
		}
		opcode = regs.ir;
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	if(loop_mode & 0xfffe) {
		count_cycles += (loop_mode & 0xfffe) * CYCLE_UNIT / 2;
		loop_mode = 1;
	}
	put_word_000(srca, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, srca + 0, 0x1, dst, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return 10 * CYCLE_UNIT / 2 + count_cycles;
}
/* 10+ (1/1) */
/* 2 0,0   */

/* NEG.W (d16,An) */
uae_u32 REGPARAM2 op_4468_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 15;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 dst = ((uae_u16)(0)) - ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(0)) < 0;
	int flgn = ((uae_s16)(dst)) < 0;
	SET_ZFLG(((uae_s16)(dst)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u16)(src)) > ((uae_u16)(0)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_word_000(srca, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, srca + 0, 0x1, dst, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 4 0,0   */

/* NEG.W (d8,An,Xn) */
uae_u32 REGPARAM2 op_4470_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 15;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	BusCyclePenalty += 2;
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 dst = ((uae_u16)(0)) - ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(0)) < 0;
	int flgn = ((uae_s16)(dst)) < 0;
	SET_ZFLG(((uae_s16)(dst)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u16)(src)) > ((uae_u16)(0)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_word_000(srca, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, srca + 0, 0x1, dst, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (3/1) */
/* 4 4,0   */

/* NEG.W (xxx).W */
uae_u32 REGPARAM2 op_4478_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 15;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, srca, 1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 dst = ((uae_u16)(0)) - ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(0)) < 0;
	int flgn = ((uae_s16)(dst)) < 0;
	SET_ZFLG(((uae_s16)(dst)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u16)(src)) > ((uae_u16)(0)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_word_000(srca, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, srca + 0, 0x1, dst, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 4 0,0   */

/* NEG.W (xxx).L */
uae_u32 REGPARAM2 op_4479_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 15;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	srca = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	srca |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, srca, 1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 dst = ((uae_u16)(0)) - ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(0)) < 0;
	int flgn = ((uae_s16)(dst)) < 0;
	SET_ZFLG(((uae_s16)(dst)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u16)(src)) > ((uae_u16)(0)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_word_000(srca, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, srca + 0, 0x1, dst, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (4/1) */
/* 6 0,0   */

/* NEG.L Dn */
uae_u32 REGPARAM2 op_4480_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 15;
	CurrentInstrCycles = 6;  
	uae_s32 src = m68k_dreg(regs, srcreg);
	uae_u32 dst = ((uae_u32)(0)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(0)) < 0;
	int flgn = ((uae_s32)(dst)) < 0;
	SET_ZFLG(((uae_s32)(dst)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(0)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		dreg_68000_long_replace_low(srcreg, dst);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	m68k_dreg(regs, srcreg) = (dst);
	m68k_incpci(2);
	return 6 * CYCLE_UNIT / 2 + count_cycles;
}
/* 6 (1/0) */
/* 2 0,0   */

/* NEG.L (An) */
uae_u32 REGPARAM2 op_4490_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 15;
	CurrentInstrCycles = 16; 
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 dst = ((uae_u32)(0)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(0)) < 0;
	int flgn = ((uae_s32)(dst)) < 0;
	SET_ZFLG(((uae_s32)(dst)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(0)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_000_prefetch(4);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			int pcoffset = 0;
			int bflgs = ((uae_s16)(src)) < 0;
			int bflgo = ((uae_s16)(0)) < 0;
			int bflgn = ((uae_s16)(dst)) < 0;
			SET_ZFLG(((uae_s16)(dst)) == 0);
			SET_VFLG((bflgs ^ bflgo) & (bflgn ^ bflgo));
			SET_CFLG(((uae_u16)(src)) > ((uae_u16)(0)));
			SET_NFLG(bflgn != 0);
			SET_XFLG(GET_CFLG());
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return 8 * CYCLE_UNIT / 2 + count_cycles;
		}
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	if(loop_mode & 0xfffe) {
		count_cycles += (loop_mode & 0xfffe) * CYCLE_UNIT / 2;
		loop_mode = 1;
	}
	put_word_000(srca + 2, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, srca + 2, 0x1, dst, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(srca, dst >> 16); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, srca + 0, 0x1, dst >> 16, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16+ (2/2) */
/* 2 0,0   */

/* NEG.L (An)+ */
uae_u32 REGPARAM2 op_4498_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 15;
	CurrentInstrCycles = 16; 
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) += 4;
	uae_u32 dst = ((uae_u32)(0)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(0)) < 0;
	int flgn = ((uae_s32)(dst)) < 0;
	SET_ZFLG(((uae_s32)(dst)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(0)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_000_prefetch(4);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			int pcoffset = 0;
			int bflgs = ((uae_s16)(src)) < 0;
			int bflgo = ((uae_s16)(0)) < 0;
			int bflgn = ((uae_s16)(dst)) < 0;
			SET_ZFLG(((uae_s16)(dst)) == 0);
			SET_VFLG((bflgs ^ bflgo) & (bflgn ^ bflgo));
			SET_CFLG(((uae_u16)(src)) > ((uae_u16)(0)));
			SET_NFLG(bflgn != 0);
			SET_XFLG(GET_CFLG());
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return 8 * CYCLE_UNIT / 2 + count_cycles;
		}
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	if(loop_mode & 0xfffe) {
		count_cycles += (loop_mode & 0xfffe) * CYCLE_UNIT / 2;
		loop_mode = 1;
	}
	put_word_000(srca + 2, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, srca + 2, 0x1, dst, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(srca, dst >> 16); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, srca + 0, 0x1, dst >> 16, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16+ (2/2) */
/* 2 0,0   */

/* NEG.L -(An) */
uae_u32 REGPARAM2 op_44a0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 15;
	CurrentInstrCycles = 18; 
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - 4;
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return 2 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) = srca;
	uae_u32 dst = ((uae_u32)(0)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(0)) < 0;
	int flgn = ((uae_s32)(dst)) < 0;
	SET_ZFLG(((uae_s32)(dst)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(0)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_000_prefetch(4);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			int pcoffset = 0;
			int bflgs = ((uae_s16)(src)) < 0;
			int bflgo = ((uae_s16)(0)) < 0;
			int bflgn = ((uae_s16)(dst)) < 0;
			SET_ZFLG(((uae_s16)(dst)) == 0);
			SET_VFLG((bflgs ^ bflgo) & (bflgn ^ bflgo));
			SET_CFLG(((uae_u16)(src)) > ((uae_u16)(0)));
			SET_NFLG(bflgn != 0);
			SET_XFLG(GET_CFLG());
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return 10 * CYCLE_UNIT / 2 + count_cycles;
		}
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	if(loop_mode & 0xfffe) {
		count_cycles += (loop_mode & 0xfffe) * CYCLE_UNIT / 2;
		loop_mode = 1;
	}
	put_word_000(srca + 2, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, srca + 2, 0x1, dst, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(srca, dst >> 16); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, srca + 0, 0x1, dst >> 16, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18+ (2/2) */
/* 2 0,0   */

/* NEG.L (d16,An) */
uae_u32 REGPARAM2 op_44a8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 15;
	CurrentInstrCycles = 24; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 dst = ((uae_u32)(0)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(0)) < 0;
	int flgn = ((uae_s32)(dst)) < 0;
	SET_ZFLG(((uae_s32)(dst)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(0)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		int bflgs = ((uae_s16)(src)) < 0;
		int bflgo = ((uae_s16)(0)) < 0;
		int bflgn = ((uae_s16)(dst)) < 0;
		SET_ZFLG(((uae_s16)(dst)) == 0);
		SET_VFLG((bflgs ^ bflgo) & (bflgn ^ bflgo));
		SET_CFLG(((uae_u16)(src)) > ((uae_u16)(0)));
		SET_NFLG(bflgn != 0);
		SET_XFLG(GET_CFLG());
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(srca + 2, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, srca + 2, 0x1, dst, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(srca, dst >> 16); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, srca + 0, 0x1, dst >> 16, 1);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 24 * CYCLE_UNIT / 2 + count_cycles;
}
/* 24 (4/2) */
/* 4 0,0   */

/* NEG.L (d8,An,Xn) */
uae_u32 REGPARAM2 op_44b0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 15;
	CurrentInstrCycles = 26; 
	uaecptr srca;
	BusCyclePenalty += 2;
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 dst = ((uae_u32)(0)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(0)) < 0;
	int flgn = ((uae_s32)(dst)) < 0;
	SET_ZFLG(((uae_s32)(dst)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(0)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		int bflgs = ((uae_s16)(src)) < 0;
		int bflgo = ((uae_s16)(0)) < 0;
		int bflgn = ((uae_s16)(dst)) < 0;
		SET_ZFLG(((uae_s16)(dst)) == 0);
		SET_VFLG((bflgs ^ bflgo) & (bflgn ^ bflgo));
		SET_CFLG(((uae_u16)(src)) > ((uae_u16)(0)));
		SET_NFLG(bflgn != 0);
		SET_XFLG(GET_CFLG());
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(srca + 2, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, srca + 2, 0x1, dst, 1);
		return 22 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(srca, dst >> 16); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, srca + 0, 0x1, dst >> 16, 1);
		return 26 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 26 * CYCLE_UNIT / 2 + count_cycles;
}
/* 26 (4/2) */
/* 4 4,0   */

/* NEG.L (xxx).W */
uae_u32 REGPARAM2 op_44b8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 15;
	CurrentInstrCycles = 24; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, srca, 2, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 dst = ((uae_u32)(0)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(0)) < 0;
	int flgn = ((uae_s32)(dst)) < 0;
	SET_ZFLG(((uae_s32)(dst)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(0)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		int bflgs = ((uae_s16)(src)) < 0;
		int bflgo = ((uae_s16)(0)) < 0;
		int bflgn = ((uae_s16)(dst)) < 0;
		SET_ZFLG(((uae_s16)(dst)) == 0);
		SET_VFLG((bflgs ^ bflgo) & (bflgn ^ bflgo));
		SET_CFLG(((uae_u16)(src)) > ((uae_u16)(0)));
		SET_NFLG(bflgn != 0);
		SET_XFLG(GET_CFLG());
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(srca + 2, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, srca + 2, 0x1, dst, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(srca, dst >> 16); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, srca + 0, 0x1, dst >> 16, 1);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 24 * CYCLE_UNIT / 2 + count_cycles;
}
/* 24 (4/2) */
/* 4 0,0   */

/* NEG.L (xxx).L */
uae_u32 REGPARAM2 op_44b9_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 15;
	CurrentInstrCycles = 28; 
	uaecptr srca;
	srca = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	srca |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, srca, 2, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 dst = ((uae_u32)(0)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(0)) < 0;
	int flgn = ((uae_s32)(dst)) < 0;
	SET_ZFLG(((uae_s32)(dst)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(0)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		int bflgs = ((uae_s16)(src)) < 0;
		int bflgo = ((uae_s16)(0)) < 0;
		int bflgn = ((uae_s16)(dst)) < 0;
		SET_ZFLG(((uae_s16)(dst)) == 0);
		SET_VFLG((bflgs ^ bflgo) & (bflgn ^ bflgo));
		SET_CFLG(((uae_u16)(src)) > ((uae_u16)(0)));
		SET_NFLG(bflgn != 0);
		SET_XFLG(GET_CFLG());
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(srca + 2, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, srca + 2, 0x1, dst, 1);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(srca, dst >> 16); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, srca + 0, 0x1, dst >> 16, 1);
		return 28 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 28 * CYCLE_UNIT / 2 + count_cycles;
}
/* 28 (5/2) */
/* 6 0,0   */

/* MV2SR.B Dn */
uae_u32 REGPARAM2 op_44c0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 33;
	CurrentInstrCycles = 12; 
	uae_s16 src = m68k_dreg(regs, srcreg);
	MakeSR();
	regs.sr &= 0xFF00;
	regs.sr |= src & 0xFF;
	MakeFromSR();
	m68k_incpci(2);
	get_word_000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, 0);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (2/0) */
/* 2 0,0   */

/* MV2SR.B (An) */
uae_u32 REGPARAM2 op_44d0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 33;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access2(opcode, srca, 1, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	MakeSR();
	regs.sr &= 0xFF00;
	regs.sr |= src & 0xFF;
	MakeFromSR();
	m68k_incpci(2);
	get_word_000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, 0);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/0) */
/* 2 0,0   */

/* MV2SR.B (An)+ */
uae_u32 REGPARAM2 op_44d8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 33;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_areg(regs, srcreg) += 2 + 0;
		m68k_incpci(2);
		exception3_read_access2(opcode, srca, 1, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) += 2 + 0;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) += 2;
	MakeSR();
	regs.sr &= 0xFF00;
	regs.sr |= src & 0xFF;
	MakeFromSR();
	m68k_incpci(2);
	get_word_000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, 0);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/0) */
/* 2 0,0   */

/* MV2SR.B -(An) */
uae_u32 REGPARAM2 op_44e0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 33;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - 2;
	if (srca & 1) {
		m68k_areg(regs, srcreg) = srca;
		m68k_incpci(2);
		exception3_read_access2(opcode, srca, 1, 1);
		return 2 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) = srca;
	MakeSR();
	regs.sr &= 0xFF00;
	regs.sr |= src & 0xFF;
	MakeFromSR();
	m68k_incpci(2);
	get_word_000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, 0);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (3/0) */
/* 2 0,0   */

/* MV2SR.B (d16,An) */
uae_u32 REGPARAM2 op_44e8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 33;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	MakeSR();
	regs.sr &= 0xFF00;
	regs.sr |= src & 0xFF;
	MakeFromSR();
	m68k_incpci(4);
	get_word_000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, 0);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (4/0) */
/* 4 0,0   */

/* MV2SR.B (d8,An,Xn) */
uae_u32 REGPARAM2 op_44f0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 33;
	CurrentInstrCycles = 22; 
	uaecptr srca;
	BusCyclePenalty += 2;
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	MakeSR();
	regs.sr &= 0xFF00;
	regs.sr |= src & 0xFF;
	MakeFromSR();
	m68k_incpci(4);
	get_word_000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, 0);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 22 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 22 * CYCLE_UNIT / 2 + count_cycles;
}
/* 22 (4/0) */
/* 4 4,0   */

/* MV2SR.B (xxx).W */
uae_u32 REGPARAM2 op_44f8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 33;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, srca, 1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	MakeSR();
	regs.sr &= 0xFF00;
	regs.sr |= src & 0xFF;
	MakeFromSR();
	m68k_incpci(4);
	get_word_000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, 0);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (4/0) */
/* 4 0,0   */

/* MV2SR.B (xxx).L */
uae_u32 REGPARAM2 op_44f9_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 33;
	CurrentInstrCycles = 24; 
	uaecptr srca;
	srca = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	srca |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, srca, 1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	MakeSR();
	regs.sr &= 0xFF00;
	regs.sr |= src & 0xFF;
	MakeFromSR();
	m68k_incpci(6);
	get_word_000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, 0);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 24 * CYCLE_UNIT / 2 + count_cycles;
}
/* 24 (5/0) */
/* 6 0,0   */

/* MV2SR.B (d16,PC) */
uae_u32 REGPARAM2 op_44fa_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 33;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	srca = m68k_getpci() + 2;
	srca += (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	MakeSR();
	regs.sr &= 0xFF00;
	regs.sr |= src & 0xFF;
	MakeFromSR();
	m68k_incpci(4);
	get_word_000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, 0);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (4/0) */
/* 4 0,0   */

/* MV2SR.B (d8,PC,Xn) */
uae_u32 REGPARAM2 op_44fb_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 33;
	CurrentInstrCycles = 22; 
	uaecptr srca;
	uaecptr tmppc = m68k_getpci() + 2;
	BusCyclePenalty += 2;
	srca = get_disp_ea_000(tmppc, get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	MakeSR();
	regs.sr &= 0xFF00;
	regs.sr |= src & 0xFF;
	MakeFromSR();
	m68k_incpci(4);
	get_word_000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, 0);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 22 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 22 * CYCLE_UNIT / 2 + count_cycles;
}
/* 22 (4/0) */
/* 4 4,0   */

/* MV2SR.B #<data>.B */
uae_u32 REGPARAM2 op_44fc_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 33;
	CurrentInstrCycles = 16; 
	uae_s16 src = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	MakeSR();
	regs.sr &= 0xFF00;
	regs.sr |= src & 0xFF;
	MakeFromSR();
	m68k_incpci(4);
	get_word_000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, 0);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/0) */
/* 4 0,0   */

/* NOT.B Dn */
uae_u32 REGPARAM2 op_4600_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 19;
	CurrentInstrCycles = 4;  
	uae_s8 src = m68k_dreg(regs, srcreg);
	uae_u32 dst = ~src;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(dst)) == 0);
	SET_NFLG(((uae_s8)(dst)) < 0);
	m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((dst) & 0xff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 4 * CYCLE_UNIT / 2 + count_cycles;
}
/* 4 (1/0) */
/* 2 0,0   */

/* NOT.B (An) */
uae_u32 REGPARAM2 op_4610_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 19;
	CurrentInstrCycles = 8;  
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 dst = ~src;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(dst)) == 0);
	SET_NFLG(((uae_s8)(dst)) < 0);
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_000_prefetch(4);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return 4 * CYCLE_UNIT / 2 + count_cycles;
		}
		opcode = regs.ir;
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	if(loop_mode & 0xfffe) {
		count_cycles += (loop_mode & 0xfffe) * CYCLE_UNIT / 2;
		loop_mode = 1;
	}
	put_byte_000(srca, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, srca + 0, 0x0, dst, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8+ (1/1) */
/* 2 0,0   */

/* NOT.B (An)+ */
uae_u32 REGPARAM2 op_4618_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 19;
	CurrentInstrCycles = 8;  
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
	uae_u32 dst = ~src;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(dst)) == 0);
	SET_NFLG(((uae_s8)(dst)) < 0);
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_000_prefetch(4);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return 4 * CYCLE_UNIT / 2 + count_cycles;
		}
		opcode = regs.ir;
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	if(loop_mode & 0xfffe) {
		count_cycles += (loop_mode & 0xfffe) * CYCLE_UNIT / 2;
		loop_mode = 1;
	}
	put_byte_000(srca, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, srca + 0, 0x0, dst, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8+ (1/1) */
/* 2 0,0   */

/* NOT.B -(An) */
uae_u32 REGPARAM2 op_4620_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 19;
	CurrentInstrCycles = 10; 
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) = srca;
	uae_u32 dst = ~src;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(dst)) == 0);
	SET_NFLG(((uae_s8)(dst)) < 0);
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_000_prefetch(4);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return 6 * CYCLE_UNIT / 2 + count_cycles;
		}
		opcode = regs.ir;
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	if(loop_mode & 0xfffe) {
		count_cycles += (loop_mode & 0xfffe) * CYCLE_UNIT / 2;
		loop_mode = 1;
	}
	put_byte_000(srca, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, srca + 0, 0x0, dst, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return 10 * CYCLE_UNIT / 2 + count_cycles;
}
/* 10+ (1/1) */
/* 2 0,0   */

/* NOT.B (d16,An) */
uae_u32 REGPARAM2 op_4628_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 19;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 dst = ~src;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(dst)) == 0);
	SET_NFLG(((uae_s8)(dst)) < 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_byte_000(srca, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, srca + 0, 0x0, dst, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 4 0,0   */

/* NOT.B (d8,An,Xn) */
uae_u32 REGPARAM2 op_4630_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 19;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	BusCyclePenalty += 2;
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 dst = ~src;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(dst)) == 0);
	SET_NFLG(((uae_s8)(dst)) < 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_byte_000(srca, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, srca + 0, 0x0, dst, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (3/1) */
/* 4 4,0   */

/* NOT.B (xxx).W */
uae_u32 REGPARAM2 op_4638_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 19;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 dst = ~src;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(dst)) == 0);
	SET_NFLG(((uae_s8)(dst)) < 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_byte_000(srca, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, srca + 0, 0x0, dst, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 4 0,0   */

/* NOT.B (xxx).L */
uae_u32 REGPARAM2 op_4639_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 19;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	srca = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	srca |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 dst = ~src;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(dst)) == 0);
	SET_NFLG(((uae_s8)(dst)) < 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_byte_000(srca, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, srca + 0, 0x0, dst, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (4/1) */
/* 6 0,0   */

/* NOT.W Dn */
uae_u32 REGPARAM2 op_4640_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 19;
	CurrentInstrCycles = 4;  
	uae_s16 src = m68k_dreg(regs, srcreg);
	uae_u32 dst = ~src;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(dst)) == 0);
	SET_NFLG(((uae_s16)(dst)) < 0);
	m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | ((dst) & 0xffff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 4 * CYCLE_UNIT / 2 + count_cycles;
}
/* 4 (1/0) */
/* 2 0,0   */

/* NOT.W (An) */
uae_u32 REGPARAM2 op_4650_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 19;
	CurrentInstrCycles = 8;  
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access2(opcode, srca, 1, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 dst = ~src;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(dst)) == 0);
	SET_NFLG(((uae_s16)(dst)) < 0);
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_000_prefetch(4);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return 4 * CYCLE_UNIT / 2 + count_cycles;
		}
		opcode = regs.ir;
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	if(loop_mode & 0xfffe) {
		count_cycles += (loop_mode & 0xfffe) * CYCLE_UNIT / 2;
		loop_mode = 1;
	}
	put_word_000(srca, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, srca + 0, 0x1, dst, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8+ (1/1) */
/* 2 0,0   */

/* NOT.W (An)+ */
uae_u32 REGPARAM2 op_4658_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 19;
	CurrentInstrCycles = 8;  
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_areg(regs, srcreg) += 2 + 0;
		m68k_incpci(2);
		exception3_read_access2(opcode, srca, 1, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) += 2 + 0;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) += 2;
	uae_u32 dst = ~src;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(dst)) == 0);
	SET_NFLG(((uae_s16)(dst)) < 0);
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_000_prefetch(4);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return 4 * CYCLE_UNIT / 2 + count_cycles;
		}
		opcode = regs.ir;
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	if(loop_mode & 0xfffe) {
		count_cycles += (loop_mode & 0xfffe) * CYCLE_UNIT / 2;
		loop_mode = 1;
	}
	put_word_000(srca, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, srca + 0, 0x1, dst, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8+ (1/1) */
/* 2 0,0   */

/* NOT.W -(An) */
uae_u32 REGPARAM2 op_4660_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 19;
	CurrentInstrCycles = 10; 
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - 2;
	if (srca & 1) {
		m68k_areg(regs, srcreg) = srca;
		m68k_incpci(2);
		exception3_read_access2(opcode, srca, 1, 1);
		return 2 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) = srca;
	uae_u32 dst = ~src;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(dst)) == 0);
	SET_NFLG(((uae_s16)(dst)) < 0);
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_000_prefetch(4);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return 6 * CYCLE_UNIT / 2 + count_cycles;
		}
		opcode = regs.ir;
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	if(loop_mode & 0xfffe) {
		count_cycles += (loop_mode & 0xfffe) * CYCLE_UNIT / 2;
		loop_mode = 1;
	}
	put_word_000(srca, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, srca + 0, 0x1, dst, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return 10 * CYCLE_UNIT / 2 + count_cycles;
}
/* 10+ (1/1) */
/* 2 0,0   */

/* NOT.W (d16,An) */
uae_u32 REGPARAM2 op_4668_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 19;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 dst = ~src;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(dst)) == 0);
	SET_NFLG(((uae_s16)(dst)) < 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_word_000(srca, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, srca + 0, 0x1, dst, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 4 0,0   */

/* NOT.W (d8,An,Xn) */
uae_u32 REGPARAM2 op_4670_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 19;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	BusCyclePenalty += 2;
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 dst = ~src;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(dst)) == 0);
	SET_NFLG(((uae_s16)(dst)) < 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_word_000(srca, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, srca + 0, 0x1, dst, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (3/1) */
/* 4 4,0   */

/* NOT.W (xxx).W */
uae_u32 REGPARAM2 op_4678_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 19;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, srca, 1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 dst = ~src;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(dst)) == 0);
	SET_NFLG(((uae_s16)(dst)) < 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_word_000(srca, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, srca + 0, 0x1, dst, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 4 0,0   */

/* NOT.W (xxx).L */
uae_u32 REGPARAM2 op_4679_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 19;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	srca = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	srca |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, srca, 1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 dst = ~src;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(dst)) == 0);
	SET_NFLG(((uae_s16)(dst)) < 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_word_000(srca, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, srca + 0, 0x1, dst, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (4/1) */
/* 6 0,0   */

/* NOT.L Dn */
uae_u32 REGPARAM2 op_4680_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 19;
	CurrentInstrCycles = 6;  
	uae_s32 src = m68k_dreg(regs, srcreg);
	uae_u32 dst = ~src;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(dst)) == 0);
	SET_NFLG(((uae_s32)(dst)) < 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		dreg_68000_long_replace_low(srcreg, dst);
		SET_VFLG(0);SET_ZFLG(!dst);
		SET_NFLG(dst & 0x80000000);
		SET_CFLG(0);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	m68k_dreg(regs, srcreg) = (dst);
	m68k_incpci(2);
	return 6 * CYCLE_UNIT / 2 + count_cycles;
}
/* 6 (1/0) */
/* 2 0,0   */

/* NOT.L (An) */
uae_u32 REGPARAM2 op_4690_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 19;
	CurrentInstrCycles = 16; 
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 dst = ~src;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(dst)) == 0);
	SET_NFLG(((uae_s32)(dst)) < 0);
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_000_prefetch(4);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			int pcoffset = 0;
			SET_VFLG(0);
			SET_ZFLG(!(dst & 0xffff));
			SET_NFLG(dst & 0x8000);
			SET_CFLG(0);
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return 8 * CYCLE_UNIT / 2 + count_cycles;
		}
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	if(loop_mode & 0xfffe) {
		count_cycles += (loop_mode & 0xfffe) * CYCLE_UNIT / 2;
		loop_mode = 1;
	}
	put_word_000(srca + 2, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, srca + 2, 0x1, dst, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(srca, dst >> 16); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, srca + 0, 0x1, dst >> 16, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16+ (2/2) */
/* 2 0,0   */

/* NOT.L (An)+ */
uae_u32 REGPARAM2 op_4698_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 19;
	CurrentInstrCycles = 16; 
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) += 4;
	uae_u32 dst = ~src;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(dst)) == 0);
	SET_NFLG(((uae_s32)(dst)) < 0);
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_000_prefetch(4);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			int pcoffset = 0;
			SET_VFLG(0);
			SET_ZFLG(!(dst & 0xffff));
			SET_NFLG(dst & 0x8000);
			SET_CFLG(0);
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return 8 * CYCLE_UNIT / 2 + count_cycles;
		}
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	if(loop_mode & 0xfffe) {
		count_cycles += (loop_mode & 0xfffe) * CYCLE_UNIT / 2;
		loop_mode = 1;
	}
	put_word_000(srca + 2, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, srca + 2, 0x1, dst, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(srca, dst >> 16); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, srca + 0, 0x1, dst >> 16, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16+ (2/2) */
/* 2 0,0   */

/* NOT.L -(An) */
uae_u32 REGPARAM2 op_46a0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 19;
	CurrentInstrCycles = 18; 
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - 4;
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return 2 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) = srca;
	uae_u32 dst = ~src;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(dst)) == 0);
	SET_NFLG(((uae_s32)(dst)) < 0);
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_000_prefetch(4);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			int pcoffset = 0;
			SET_VFLG(0);
			SET_ZFLG(!(dst & 0xffff));
			SET_NFLG(dst & 0x8000);
			SET_CFLG(0);
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return 10 * CYCLE_UNIT / 2 + count_cycles;
		}
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	if(loop_mode & 0xfffe) {
		count_cycles += (loop_mode & 0xfffe) * CYCLE_UNIT / 2;
		loop_mode = 1;
	}
	put_word_000(srca + 2, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, srca + 2, 0x1, dst, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(srca, dst >> 16); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, srca + 0, 0x1, dst >> 16, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18+ (2/2) */
/* 2 0,0   */

/* NOT.L (d16,An) */
uae_u32 REGPARAM2 op_46a8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 19;
	CurrentInstrCycles = 24; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 dst = ~src;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(dst)) == 0);
	SET_NFLG(((uae_s32)(dst)) < 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		SET_VFLG(0);
		SET_ZFLG(!(dst & 0xffff));
		SET_NFLG(dst & 0x8000);
		SET_CFLG(0);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(srca + 2, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, srca + 2, 0x1, dst, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(srca, dst >> 16); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, srca + 0, 0x1, dst >> 16, 1);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 24 * CYCLE_UNIT / 2 + count_cycles;
}
/* 24 (4/2) */
/* 4 0,0   */

/* NOT.L (d8,An,Xn) */
uae_u32 REGPARAM2 op_46b0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 19;
	CurrentInstrCycles = 26; 
	uaecptr srca;
	BusCyclePenalty += 2;
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 dst = ~src;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(dst)) == 0);
	SET_NFLG(((uae_s32)(dst)) < 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		SET_VFLG(0);
		SET_ZFLG(!(dst & 0xffff));
		SET_NFLG(dst & 0x8000);
		SET_CFLG(0);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(srca + 2, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, srca + 2, 0x1, dst, 1);
		return 22 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(srca, dst >> 16); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, srca + 0, 0x1, dst >> 16, 1);
		return 26 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 26 * CYCLE_UNIT / 2 + count_cycles;
}
/* 26 (4/2) */
/* 4 4,0   */

/* NOT.L (xxx).W */
uae_u32 REGPARAM2 op_46b8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 19;
	CurrentInstrCycles = 24; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, srca, 2, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 dst = ~src;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(dst)) == 0);
	SET_NFLG(((uae_s32)(dst)) < 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		SET_VFLG(0);
		SET_ZFLG(!(dst & 0xffff));
		SET_NFLG(dst & 0x8000);
		SET_CFLG(0);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(srca + 2, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, srca + 2, 0x1, dst, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(srca, dst >> 16); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, srca + 0, 0x1, dst >> 16, 1);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 24 * CYCLE_UNIT / 2 + count_cycles;
}
/* 24 (4/2) */
/* 4 0,0   */

/* NOT.L (xxx).L */
uae_u32 REGPARAM2 op_46b9_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 19;
	CurrentInstrCycles = 28; 
	uaecptr srca;
	srca = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	srca |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, srca, 2, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 dst = ~src;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(dst)) == 0);
	SET_NFLG(((uae_s32)(dst)) < 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		SET_VFLG(0);
		SET_ZFLG(!(dst & 0xffff));
		SET_NFLG(dst & 0x8000);
		SET_CFLG(0);
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(srca + 2, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, srca + 2, 0x1, dst, 1);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(srca, dst >> 16); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, srca + 0, 0x1, dst >> 16, 1);
		return 28 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 28 * CYCLE_UNIT / 2 + count_cycles;
}
/* 28 (5/2) */
/* 6 0,0   */

/* MV2SR.W Dn */
uae_u32 REGPARAM2 op_46c0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 33;
	CurrentInstrCycles = 12; 
	if (!regs.s) {
		Exception(8);
		return 0;
	}
	uae_s16 src = m68k_dreg(regs, srcreg);
	regs.sr = src;
	MakeFromSR();
	m68k_incpci(2);
	get_word_000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, 0);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (2/0) */
/* 2 0,0   */

/* MV2SR.W (An) */
uae_u32 REGPARAM2 op_46d0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 33;
	CurrentInstrCycles = 16; 
	if (!regs.s) {
		Exception(8);
		return 0;
	}
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access2(opcode, srca, 1, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.sr = src;
	MakeFromSR();
	m68k_incpci(2);
	get_word_000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, 0);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/0) */
/* 2 0,0   */

/* MV2SR.W (An)+ */
uae_u32 REGPARAM2 op_46d8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 33;
	CurrentInstrCycles = 16; 
	if (!regs.s) {
		Exception(8);
		return 0;
	}
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_areg(regs, srcreg) += 2 + 0;
		m68k_incpci(2);
		exception3_read_access2(opcode, srca, 1, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) += 2 + 0;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) += 2;
	regs.sr = src;
	MakeFromSR();
	m68k_incpci(2);
	get_word_000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, 0);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/0) */
/* 2 0,0   */

/* MV2SR.W -(An) */
uae_u32 REGPARAM2 op_46e0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 33;
	CurrentInstrCycles = 18; 
	if (!regs.s) {
		Exception(8);
		return 0;
	}
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - 2;
	if (srca & 1) {
		m68k_areg(regs, srcreg) = srca;
		m68k_incpci(2);
		exception3_read_access2(opcode, srca, 1, 1);
		return 2 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) = srca;
	regs.sr = src;
	MakeFromSR();
	m68k_incpci(2);
	get_word_000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, 0);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (3/0) */
/* 2 0,0   */

/* MV2SR.W (d16,An) */
uae_u32 REGPARAM2 op_46e8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 33;
	CurrentInstrCycles = 20; 
	if (!regs.s) {
		Exception(8);
		return 0;
	}
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.sr = src;
	MakeFromSR();
	m68k_incpci(4);
	get_word_000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, 0);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (4/0) */
/* 4 0,0   */

/* MV2SR.W (d8,An,Xn) */
uae_u32 REGPARAM2 op_46f0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 33;
	CurrentInstrCycles = 22; 
	if (!regs.s) {
		Exception(8);
		return 0;
	}
	uaecptr srca;
	BusCyclePenalty += 2;
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.sr = src;
	MakeFromSR();
	m68k_incpci(4);
	get_word_000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, 0);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 22 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 22 * CYCLE_UNIT / 2 + count_cycles;
}
/* 22 (4/0) */
/* 4 4,0   */

/* MV2SR.W (xxx).W */
uae_u32 REGPARAM2 op_46f8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 33;
	CurrentInstrCycles = 20; 
	if (!regs.s) {
		Exception(8);
		return 0;
	}
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, srca, 1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.sr = src;
	MakeFromSR();
	m68k_incpci(4);
	get_word_000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, 0);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (4/0) */
/* 4 0,0   */

/* MV2SR.W (xxx).L */
uae_u32 REGPARAM2 op_46f9_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 33;
	CurrentInstrCycles = 24; 
	if (!regs.s) {
		Exception(8);
		return 0;
	}
	uaecptr srca;
	srca = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	srca |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, srca, 1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.sr = src;
	MakeFromSR();
	m68k_incpci(6);
	get_word_000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, 0);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 24 * CYCLE_UNIT / 2 + count_cycles;
}
/* 24 (5/0) */
/* 6 0,0   */

/* MV2SR.W (d16,PC) */
uae_u32 REGPARAM2 op_46fa_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 33;
	CurrentInstrCycles = 20; 
	if (!regs.s) {
		Exception(8);
		return 0;
	}
	uaecptr srca;
	srca = m68k_getpci() + 2;
	srca += (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.sr = src;
	MakeFromSR();
	m68k_incpci(4);
	get_word_000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, 0);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (4/0) */
/* 4 0,0   */

/* MV2SR.W (d8,PC,Xn) */
uae_u32 REGPARAM2 op_46fb_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 33;
	CurrentInstrCycles = 22; 
	if (!regs.s) {
		Exception(8);
		return 0;
	}
	uaecptr srca;
	uaecptr tmppc = m68k_getpci() + 2;
	BusCyclePenalty += 2;
	srca = get_disp_ea_000(tmppc, get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.sr = src;
	MakeFromSR();
	m68k_incpci(4);
	get_word_000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, 0);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 22 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 22 * CYCLE_UNIT / 2 + count_cycles;
}
/* 22 (4/0) */
/* 4 4,0   */

/* MV2SR.W #<data>.W */
uae_u32 REGPARAM2 op_46fc_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 33;
	CurrentInstrCycles = 16; 
	if (!regs.s) {
		Exception(8);
		return 0;
	}
	uae_s16 src = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.sr = src;
	MakeFromSR();
	m68k_incpci(4);
	get_word_000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, 0);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/0) */
/* 4 0,0   */

/* NBCD.B Dn */
uae_u32 REGPARAM2 op_4800_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 17;
	CurrentInstrCycles = 6;  
	uae_s8 src = m68k_dreg(regs, srcreg);
	uae_u16 newv_lo = - (src & 0xF) - (GET_XFLG() ? 1 : 0);
	uae_u16 newv_hi = - (src & 0xF0);
	uae_u16 newv;
	int cflg, tmp_newv;
	tmp_newv = newv_hi + newv_lo;
	if (newv_lo > 9) newv_lo -= 6;
	newv = newv_hi + newv_lo;
	cflg = (newv & 0x1F0) > 0x90;
	if (cflg) newv -= 0x60;
	SET_CFLG(cflg);
	COPY_CARRY();
	SET_ZFLG(GET_ZFLG() & (((uae_s8)(newv)) == 0));
	SET_NFLG(((uae_s8)(newv)) < 0);
	SET_VFLG((tmp_newv & 0x80) != 0 && (newv & 0x80) == 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((newv) & 0xff);
	m68k_incpci(2);
	return 6 * CYCLE_UNIT / 2 + count_cycles;
}
/* 6 (1/0) */
/* 2 0,0   */

/* NBCD.B (An) */
uae_u32 REGPARAM2 op_4810_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 17;
	CurrentInstrCycles = 8;  
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u16 newv_lo = - (src & 0xF) - (GET_XFLG() ? 1 : 0);
	uae_u16 newv_hi = - (src & 0xF0);
	uae_u16 newv;
	int cflg, tmp_newv;
	tmp_newv = newv_hi + newv_lo;
	if (newv_lo > 9) newv_lo -= 6;
	newv = newv_hi + newv_lo;
	cflg = (newv & 0x1F0) > 0x90;
	if (cflg) newv -= 0x60;
	SET_CFLG(cflg);
	COPY_CARRY();
	SET_ZFLG(GET_ZFLG() & (((uae_s8)(newv)) == 0));
	SET_NFLG(((uae_s8)(newv)) < 0);
	SET_VFLG((tmp_newv & 0x80) != 0 && (newv & 0x80) == 0);
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_000_prefetch(4);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return 4 * CYCLE_UNIT / 2 + count_cycles;
		}
		opcode = regs.ir;
	} else {
		loop_mode = 0;
		loop_mode |= 6;
		loop_mode |= 6 << 16;
	}
	if(loop_mode & 0xfffe) {
		count_cycles += (loop_mode & 0xfffe) * CYCLE_UNIT / 2;
		loop_mode = 1;
	}
	put_byte_000(srca, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, srca + 0, 0x0, newv, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8+ (1/1) */
/* 2 0,0   */

/* NBCD.B (An)+ */
uae_u32 REGPARAM2 op_4818_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 17;
	CurrentInstrCycles = 8;  
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
	uae_u16 newv_lo = - (src & 0xF) - (GET_XFLG() ? 1 : 0);
	uae_u16 newv_hi = - (src & 0xF0);
	uae_u16 newv;
	int cflg, tmp_newv;
	tmp_newv = newv_hi + newv_lo;
	if (newv_lo > 9) newv_lo -= 6;
	newv = newv_hi + newv_lo;
	cflg = (newv & 0x1F0) > 0x90;
	if (cflg) newv -= 0x60;
	SET_CFLG(cflg);
	COPY_CARRY();
	SET_ZFLG(GET_ZFLG() & (((uae_s8)(newv)) == 0));
	SET_NFLG(((uae_s8)(newv)) < 0);
	SET_VFLG((tmp_newv & 0x80) != 0 && (newv & 0x80) == 0);
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_000_prefetch(4);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return 4 * CYCLE_UNIT / 2 + count_cycles;
		}
		opcode = regs.ir;
	} else {
		loop_mode = 0;
		loop_mode |= 6;
		loop_mode |= 6 << 16;
	}
	if(loop_mode & 0xfffe) {
		count_cycles += (loop_mode & 0xfffe) * CYCLE_UNIT / 2;
		loop_mode = 1;
	}
	put_byte_000(srca, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, srca + 0, 0x0, newv, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8+ (1/1) */
/* 2 0,0   */

/* NBCD.B -(An) */
uae_u32 REGPARAM2 op_4820_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 17;
	CurrentInstrCycles = 10; 
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) = srca;
	uae_u16 newv_lo = - (src & 0xF) - (GET_XFLG() ? 1 : 0);
	uae_u16 newv_hi = - (src & 0xF0);
	uae_u16 newv;
	int cflg, tmp_newv;
	tmp_newv = newv_hi + newv_lo;
	if (newv_lo > 9) newv_lo -= 6;
	newv = newv_hi + newv_lo;
	cflg = (newv & 0x1F0) > 0x90;
	if (cflg) newv -= 0x60;
	SET_CFLG(cflg);
	COPY_CARRY();
	SET_ZFLG(GET_ZFLG() & (((uae_s8)(newv)) == 0));
	SET_NFLG(((uae_s8)(newv)) < 0);
	SET_VFLG((tmp_newv & 0x80) != 0 && (newv & 0x80) == 0);
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_000_prefetch(4);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return 6 * CYCLE_UNIT / 2 + count_cycles;
		}
		opcode = regs.ir;
	} else {
		loop_mode = 0;
		loop_mode |= 6;
		loop_mode |= 6 << 16;
	}
	if(loop_mode & 0xfffe) {
		count_cycles += (loop_mode & 0xfffe) * CYCLE_UNIT / 2;
		loop_mode = 1;
	}
	put_byte_000(srca, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, srca + 0, 0x0, newv, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return 10 * CYCLE_UNIT / 2 + count_cycles;
}
/* 10+ (1/1) */
/* 2 0,0   */

/* NBCD.B (d16,An) */
uae_u32 REGPARAM2 op_4828_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 17;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u16 newv_lo = - (src & 0xF) - (GET_XFLG() ? 1 : 0);
	uae_u16 newv_hi = - (src & 0xF0);
	uae_u16 newv;
	int cflg, tmp_newv;
	tmp_newv = newv_hi + newv_lo;
	if (newv_lo > 9) newv_lo -= 6;
	newv = newv_hi + newv_lo;
	cflg = (newv & 0x1F0) > 0x90;
	if (cflg) newv -= 0x60;
	SET_CFLG(cflg);
	COPY_CARRY();
	SET_ZFLG(GET_ZFLG() & (((uae_s8)(newv)) == 0));
	SET_NFLG(((uae_s8)(newv)) < 0);
	SET_VFLG((tmp_newv & 0x80) != 0 && (newv & 0x80) == 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_byte_000(srca, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, srca + 0, 0x0, newv, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 4 0,0   */

/* NBCD.B (d8,An,Xn) */
uae_u32 REGPARAM2 op_4830_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 17;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	BusCyclePenalty += 2;
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u16 newv_lo = - (src & 0xF) - (GET_XFLG() ? 1 : 0);
	uae_u16 newv_hi = - (src & 0xF0);
	uae_u16 newv;
	int cflg, tmp_newv;
	tmp_newv = newv_hi + newv_lo;
	if (newv_lo > 9) newv_lo -= 6;
	newv = newv_hi + newv_lo;
	cflg = (newv & 0x1F0) > 0x90;
	if (cflg) newv -= 0x60;
	SET_CFLG(cflg);
	COPY_CARRY();
	SET_ZFLG(GET_ZFLG() & (((uae_s8)(newv)) == 0));
	SET_NFLG(((uae_s8)(newv)) < 0);
	SET_VFLG((tmp_newv & 0x80) != 0 && (newv & 0x80) == 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_byte_000(srca, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, srca + 0, 0x0, newv, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (3/1) */
/* 4 4,0   */

/* NBCD.B (xxx).W */
uae_u32 REGPARAM2 op_4838_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 17;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u16 newv_lo = - (src & 0xF) - (GET_XFLG() ? 1 : 0);
	uae_u16 newv_hi = - (src & 0xF0);
	uae_u16 newv;
	int cflg, tmp_newv;
	tmp_newv = newv_hi + newv_lo;
	if (newv_lo > 9) newv_lo -= 6;
	newv = newv_hi + newv_lo;
	cflg = (newv & 0x1F0) > 0x90;
	if (cflg) newv -= 0x60;
	SET_CFLG(cflg);
	COPY_CARRY();
	SET_ZFLG(GET_ZFLG() & (((uae_s8)(newv)) == 0));
	SET_NFLG(((uae_s8)(newv)) < 0);
	SET_VFLG((tmp_newv & 0x80) != 0 && (newv & 0x80) == 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_byte_000(srca, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, srca + 0, 0x0, newv, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 4 0,0   */

/* NBCD.B (xxx).L */
uae_u32 REGPARAM2 op_4839_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 17;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	srca = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	srca |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u16 newv_lo = - (src & 0xF) - (GET_XFLG() ? 1 : 0);
	uae_u16 newv_hi = - (src & 0xF0);
	uae_u16 newv;
	int cflg, tmp_newv;
	tmp_newv = newv_hi + newv_lo;
	if (newv_lo > 9) newv_lo -= 6;
	newv = newv_hi + newv_lo;
	cflg = (newv & 0x1F0) > 0x90;
	if (cflg) newv -= 0x60;
	SET_CFLG(cflg);
	COPY_CARRY();
	SET_ZFLG(GET_ZFLG() & (((uae_s8)(newv)) == 0));
	SET_NFLG(((uae_s8)(newv)) < 0);
	SET_VFLG((tmp_newv & 0x80) != 0 && (newv & 0x80) == 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_byte_000(srca, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, srca + 0, 0x0, newv, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (4/1) */
/* 6 0,0   */

/* SWAP.W Dn */
uae_u32 REGPARAM2 op_4840_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 34;
	CurrentInstrCycles = 4;  
	uae_s32 src = m68k_dreg(regs, srcreg);
	uae_u32 dst = ((src >> 16)&0xFFFF) | ((src&0xFFFF)<<16);
	m68k_dreg(regs, srcreg) = (dst);
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(dst)) == 0);
	SET_NFLG(((uae_s32)(dst)) < 0);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 4 * CYCLE_UNIT / 2 + count_cycles;
}
/* 4 (1/0) */
/* 2 0,0   */

/* BKPTQ.L #<data> */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_4848_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 99;
	CurrentInstrCycles = 4;  
	op_illg(opcode);
	return 4 * CYCLE_UNIT / 2 + count_cycles;
}
/* 4 (0/0) */
/* 2 0,0   */

#endif
/* PEA.L (An) */
uae_u32 REGPARAM2 op_4850_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 57;
	CurrentInstrCycles = 12; 
	uae_u16 old_opcode = opcode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, 7) - 4;
	m68k_areg(regs, 7) = dsta;
	regs.ir = regs.irc;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		m68k_areg(regs, 7) += 4;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		regs.ir = old_opcode;
		m68k_incpci(2);
		exception3_write_access(old_opcode, dsta, sz_word, srca >> 16, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, srca >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x1, srca >> 16, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta + 2, srca); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 2, 0x1, srca, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (1/2) */
/* 2 0,0   */

/* PEA.L (d16,An) */
uae_u32 REGPARAM2 op_4868_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 57;
	CurrentInstrCycles = 16; 
	uae_u16 old_opcode = opcode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, 7) - 4;
	m68k_areg(regs, 7) = dsta;
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		m68k_areg(regs, 7) += 4;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		regs.ir = old_opcode;
		m68k_incpci(2);
		exception3_write_access(old_opcode, dsta, sz_word, srca >> 16, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, srca >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, srca >> 16, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta + 2, srca); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 2, 0x1, srca, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (2/2) */
/* 4 0,0   */

/* PEA.L (d8,An,Xn) */
uae_u32 REGPARAM2 op_4870_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 57;
	CurrentInstrCycles = 22; 
	uae_u16 old_opcode = opcode;
	uaecptr srca;
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, 7) - 4;
	m68k_areg(regs, 7) = dsta;
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		m68k_areg(regs, 7) += 4;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		regs.ir = old_opcode;
		m68k_incpci(2);
		exception3_write_access(old_opcode, dsta, sz_word, srca >> 16, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, srca >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, srca >> 16, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta + 2, srca); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 2, 0x1, srca, 1);
		return 22 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 22 * CYCLE_UNIT / 2 + count_cycles;
}
/* 22 (2/2) */
/* 4 4,0   */

/* PEA.L (xxx).W */
uae_u32 REGPARAM2 op_4878_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 57;
	CurrentInstrCycles = 16; 
	uae_u16 old_opcode = opcode;
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, 7) - 4;
	m68k_areg(regs, 7) = dsta;
	if (dsta & 1) {
		regs.ir = old_opcode;
		m68k_incpci(2);
		exception3_write_access(old_opcode, dsta, sz_word, srca >> 16, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, srca >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, srca >> 16, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta + 2, srca); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 2, 0x1, srca, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (2/2) */
/* 4 0,0   */

/* PEA.L (xxx).L */
uae_u32 REGPARAM2 op_4879_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 57;
	CurrentInstrCycles = 20; 
	uae_u16 old_opcode = opcode;
	uaecptr srca;
	srca = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	srca |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, 7) - 4;
	m68k_areg(regs, 7) = dsta;
	if (dsta & 1) {
		regs.ir = old_opcode;
		m68k_incpci(2);
		exception3_write_access(old_opcode, dsta, sz_word, srca >> 16, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, srca >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 0, 0x1, srca >> 16, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta + 2, srca); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 2, 0x1, srca, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (3/2) */
/* 6 0,0   */

/* PEA.L (d16,PC) */
uae_u32 REGPARAM2 op_487a_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 57;
	CurrentInstrCycles = 16; 
	uae_u16 old_opcode = opcode;
	uaecptr srca;
	srca = m68k_getpci() + 2;
	srca += (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, 7) - 4;
	m68k_areg(regs, 7) = dsta;
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		m68k_areg(regs, 7) += 4;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		regs.ir = old_opcode;
		m68k_incpci(2);
		exception3_write_access(old_opcode, dsta, sz_word, srca >> 16, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, srca >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, srca >> 16, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta + 2, srca); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 2, 0x1, srca, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (2/2) */
/* 4 0,0   */

/* PEA.L (d8,PC,Xn) */
uae_u32 REGPARAM2 op_487b_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 57;
	CurrentInstrCycles = 22; 
	uae_u16 old_opcode = opcode;
	uaecptr srca;
	uaecptr tmppc = m68k_getpci() + 2;
	srca = get_disp_ea_000(tmppc, get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, 7) - 4;
	m68k_areg(regs, 7) = dsta;
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		m68k_areg(regs, 7) += 4;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		regs.ir = old_opcode;
		m68k_incpci(2);
		exception3_write_access(old_opcode, dsta, sz_word, srca >> 16, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, srca >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, srca >> 16, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta + 2, srca); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 2, 0x1, srca, 1);
		return 22 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 22 * CYCLE_UNIT / 2 + count_cycles;
}
/* 22 (2/2) */
/* 4 4,0   */

/* EXT.W Dn */
uae_u32 REGPARAM2 op_4880_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 36;
	CurrentInstrCycles = 4;  
	uae_s32 src = m68k_dreg(regs, srcreg);
	uae_u16 dst = (uae_s16)(uae_s8)src;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(dst)) == 0);
	SET_NFLG(((uae_s16)(dst)) < 0);
	m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | ((dst) & 0xffff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 4 * CYCLE_UNIT / 2 + count_cycles;
}
/* 4 (1/0) */
/* 2 0,0   */

/* MVMLE.W #<data>.W,(An) */
uae_u32 REGPARAM2 op_4890_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 38;
	CurrentInstrCycles = 8;  
	uae_u16 mask = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr srca;
	srca = m68k_areg(regs, dstreg);
	uae_u16 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
	if ((amask || dmask) && (srca & 1)) {
		uaecptr srcav = srca;
		if(dmask) {
			srcav = m68k_dreg(regs, movem_index1[dmask]) >> 0;
		} else if (amask) {
			srcav = m68k_areg(regs, movem_index1[amask]) >> 0;
		}
		regs.read_buffer = mask;
		m68k_incpci(6);
		exception3_write_access(opcode, srca, 1, srcav, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	while (dmask) {
		put_word_000(srca, m68k_dreg(regs, movem_index1[dmask]));
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(6);
			exception2_write(opcode, srca + 0, 0x1, m68k_dreg(regs, movem_index1[dmask]), 1);
			return 4 * CYCLE_UNIT / 2 + count_cycles;
		}
		srca += 2;
		dmask = movem_next[dmask];
	}
	while (amask) {
		put_word_000(srca, m68k_areg(regs, movem_index1[amask]));
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(6);
			exception2_write(opcode, srca + 0, 0x1, m68k_areg(regs, movem_index1[amask]), 1);
			return 4 * CYCLE_UNIT / 2 + count_cycles;
		}
		srca += 2;
		amask = movem_next[amask];
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8+ (2/0) */
/* 4 0,0   */

/* MVMLE.W #<data>.W,-(An) */
uae_u32 REGPARAM2 op_48a0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 38;
	CurrentInstrCycles = 8;  
	uae_u16 mask = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr srca;
	srca = m68k_areg(regs, dstreg) - 0;
	uae_u16 amask = mask & 0xff, dmask = (mask >> 8) & 0xff;
	if ((amask || dmask) && (srca & 1)) {
		srca -= 2;
		uaecptr srcav = srca;
		if(amask) {
			srcav = m68k_areg(regs, movem_index2[amask]);
		} else if (dmask) {
			srcav = m68k_dreg(regs, movem_index2[dmask]);
		}
		regs.read_buffer = mask;
		m68k_incpci(6);
		exception3_write_access(opcode, srca, 1, srcav, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	while (amask) {
		srca -= 2;
		put_word_000(srca, m68k_areg(regs, movem_index2[amask]));
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(6);
			exception2_write(opcode, srca + 0, 0x1, m68k_areg(regs, movem_index2[amask]), 1);
			return 4 * CYCLE_UNIT / 2 + count_cycles;
		}
		amask = movem_next[amask];
	}
	while (dmask) {
		srca -= 2;
		put_word_000(srca, m68k_dreg(regs, movem_index2[dmask]));
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(6);
			exception2_write(opcode, srca + 0, 0x1, m68k_dreg(regs, movem_index2[dmask]), 1);
			return 4 * CYCLE_UNIT / 2 + count_cycles;
		}
		dmask = movem_next[dmask];
	}
	m68k_areg(regs, dstreg) = srca;
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8+ (2/0) */
/* 4 0,0   */

/* MVMLE.W #<data>.W,(d16,An) */
uae_u32 REGPARAM2 op_48a8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 38;
	CurrentInstrCycles = 12; 
	uae_u16 mask = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr srca;
	srca = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, 2);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u16 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
	if ((amask || dmask) && (srca & 1)) {
		uaecptr srcav = srca;
		if(dmask) {
			srcav = m68k_dreg(regs, movem_index1[dmask]) >> 0;
		} else if (amask) {
			srcav = m68k_areg(regs, movem_index1[amask]) >> 0;
		}
		m68k_incpci(8);
		exception3_write_access(opcode, srca, 1, srcav, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	while (dmask) {
		put_word_000(srca, m68k_dreg(regs, movem_index1[dmask]));
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(8);
			exception2_write(opcode, srca + 0, 0x1, m68k_dreg(regs, movem_index1[dmask]), 1);
			return 8 * CYCLE_UNIT / 2 + count_cycles;
		}
		srca += 2;
		dmask = movem_next[dmask];
	}
	while (amask) {
		put_word_000(srca, m68k_areg(regs, movem_index1[amask]));
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(8);
			exception2_write(opcode, srca + 0, 0x1, m68k_areg(regs, movem_index1[amask]), 1);
			return 8 * CYCLE_UNIT / 2 + count_cycles;
		}
		srca += 2;
		amask = movem_next[amask];
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12+ (3/0) */
/* 6 0,0   */

/* MVMLE.W #<data>.W,(d8,An,Xn) */
uae_u32 REGPARAM2 op_48b0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 38;
	CurrentInstrCycles = 14; 
	uae_u16 mask = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr srca;
	srca = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_000_prefetch(6));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, 2);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u16 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
	if ((amask || dmask) && (srca & 1)) {
		uaecptr srcav = srca;
		if(dmask) {
			srcav = m68k_dreg(regs, movem_index1[dmask]) >> 0;
		} else if (amask) {
			srcav = m68k_areg(regs, movem_index1[amask]) >> 0;
		}
		m68k_incpci(8);
		exception3_write_access(opcode, srca, 1, srcav, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	while (dmask) {
		put_word_000(srca, m68k_dreg(regs, movem_index1[dmask]));
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(8);
			exception2_write(opcode, srca + 0, 0x1, m68k_dreg(regs, movem_index1[dmask]), 1);
			return 10 * CYCLE_UNIT / 2 + count_cycles;
		}
		srca += 2;
		dmask = movem_next[dmask];
	}
	while (amask) {
		put_word_000(srca, m68k_areg(regs, movem_index1[amask]));
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(8);
			exception2_write(opcode, srca + 0, 0x1, m68k_areg(regs, movem_index1[amask]), 1);
			return 10 * CYCLE_UNIT / 2 + count_cycles;
		}
		srca += 2;
		amask = movem_next[amask];
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 14 * CYCLE_UNIT / 2 + count_cycles;
}
/* 14+ (3/0) */
/* 6 4,0   */

/* MVMLE.W #<data>.W,(xxx).W */
uae_u32 REGPARAM2 op_48b8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 38;
	CurrentInstrCycles = 12; 
	uae_u16 mask = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, 2);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u16 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
	if ((amask || dmask) && (srca & 1)) {
		uaecptr srcav = srca;
		if(dmask) {
			srcav = m68k_dreg(regs, movem_index1[dmask]) >> 0;
		} else if (amask) {
			srcav = m68k_areg(regs, movem_index1[amask]) >> 0;
		}
		m68k_incpci(8);
		exception3_write_access(opcode, srca, 1, srcav, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	while (dmask) {
		put_word_000(srca, m68k_dreg(regs, movem_index1[dmask]));
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(8);
			exception2_write(opcode, srca + 0, 0x1, m68k_dreg(regs, movem_index1[dmask]), 1);
			return 8 * CYCLE_UNIT / 2 + count_cycles;
		}
		srca += 2;
		dmask = movem_next[dmask];
	}
	while (amask) {
		put_word_000(srca, m68k_areg(regs, movem_index1[amask]));
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(8);
			exception2_write(opcode, srca + 0, 0x1, m68k_areg(regs, movem_index1[amask]), 1);
			return 8 * CYCLE_UNIT / 2 + count_cycles;
		}
		srca += 2;
		amask = movem_next[amask];
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12+ (3/0) */
/* 6 0,0   */

/* MVMLE.W #<data>.W,(xxx).L */
uae_u32 REGPARAM2 op_48b9_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 38;
	CurrentInstrCycles = 16; 
	uae_u16 mask = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr srca;
	srca = get_word_000_prefetch(6) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	srca |= get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		pcoffset += 2;
		exception2_fetch(opcode, 8, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u16 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
	if ((amask || dmask) && (srca & 1)) {
		uaecptr srcav = srca;
		if(dmask) {
			srcav = m68k_dreg(regs, movem_index1[dmask]) >> 0;
		} else if (amask) {
			srcav = m68k_areg(regs, movem_index1[amask]) >> 0;
		}
		m68k_incpci(10);
		exception3_write_access(opcode, srca, 1, srcav, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	while (dmask) {
		put_word_000(srca, m68k_dreg(regs, movem_index1[dmask]));
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(10);
			exception2_write(opcode, srca + 0, 0x1, m68k_dreg(regs, movem_index1[dmask]), 1);
			return 12 * CYCLE_UNIT / 2 + count_cycles;
		}
		srca += 2;
		dmask = movem_next[dmask];
	}
	while (amask) {
		put_word_000(srca, m68k_areg(regs, movem_index1[amask]));
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(10);
			exception2_write(opcode, srca + 0, 0x1, m68k_areg(regs, movem_index1[amask]), 1);
			return 12 * CYCLE_UNIT / 2 + count_cycles;
		}
		srca += 2;
		amask = movem_next[amask];
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(10);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 10, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(8);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16+ (4/0) */
/* 8 0,0   */

/* EXT.L Dn */
uae_u32 REGPARAM2 op_48c0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 36;
	CurrentInstrCycles = 4;  
	uae_s32 src = m68k_dreg(regs, srcreg);
	uae_u32 dst = (uae_s32)(uae_s16)src;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(dst)) == 0);
	SET_NFLG(((uae_s32)(dst)) < 0);
	m68k_dreg(regs, srcreg) = (dst);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 4 * CYCLE_UNIT / 2 + count_cycles;
}
/* 4 (1/0) */
/* 2 0,0   */

/* MVMLE.L #<data>.W,(An) */
uae_u32 REGPARAM2 op_48d0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 38;
	CurrentInstrCycles = 8;  
	uae_u16 mask = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr srca;
	srca = m68k_areg(regs, dstreg);
	uae_u16 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
	if ((amask || dmask) && (srca & 1)) {
		uaecptr srcav = srca;
		if(dmask) {
			srcav = m68k_dreg(regs, movem_index1[dmask]) >> 16;
		} else if (amask) {
			srcav = m68k_areg(regs, movem_index1[amask]) >> 16;
		}
		regs.read_buffer = mask;
		m68k_incpci(6);
		exception3_write_access(opcode, srca, 2, srcav, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	while (dmask) {
		put_word_000(srca, m68k_dreg(regs, movem_index1[dmask]) >> 16);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(6);
			exception2_write(opcode, srca + 0, 0x1, m68k_dreg(regs, movem_index1[dmask]) >> 16, 1);
			return 4 * CYCLE_UNIT / 2 + count_cycles;
		}
		put_word_000(srca + 2, m68k_dreg(regs, movem_index1[dmask]));
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(6);
			exception2_write(opcode, srca + 2, 0x1, m68k_dreg(regs, movem_index1[dmask]), 1);
			return 4 * CYCLE_UNIT / 2 + count_cycles;
		}
		srca += 4;
		dmask = movem_next[dmask];
	}
	while (amask) {
		put_word_000(srca, m68k_areg(regs, movem_index1[amask]) >> 16);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(6);
			exception2_write(opcode, srca + 0, 0x1, m68k_areg(regs, movem_index1[amask]) >> 16, 1);
			return 4 * CYCLE_UNIT / 2 + count_cycles;
		}
		put_word_000(srca + 2, m68k_areg(regs, movem_index1[amask]));
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(6);
			exception2_write(opcode, srca + 2, 0x1, m68k_areg(regs, movem_index1[amask]), 1);
			return 4 * CYCLE_UNIT / 2 + count_cycles;
		}
		srca += 4;
		amask = movem_next[amask];
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8+ (2/0) */
/* 4 0,0   */

/* MVMLE.L #<data>.W,-(An) */
uae_u32 REGPARAM2 op_48e0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 38;
	CurrentInstrCycles = 8;  
	uae_u16 mask = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr srca;
	srca = m68k_areg(regs, dstreg) - 0;
	uae_u16 amask = mask & 0xff, dmask = (mask >> 8) & 0xff;
	if ((amask || dmask) && (srca & 1)) {
		srca -= 2;
		uaecptr srcav = srca;
		if(amask) {
			srcav = m68k_areg(regs, movem_index2[amask]);
		} else if (dmask) {
			srcav = m68k_dreg(regs, movem_index2[dmask]);
		}
		regs.read_buffer = mask;
		m68k_incpci(6);
		exception3_write_access(opcode, srca, 2, srcav, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	while (amask) {
		put_word_000(srca - 2, m68k_areg(regs, movem_index2[amask]));
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(6);
			exception2_write(opcode, srca + -2, 0x1, m68k_areg(regs, movem_index2[amask]), 1);
			return 4 * CYCLE_UNIT / 2 + count_cycles;
		}
		put_word_000(srca - 4, m68k_areg(regs, movem_index2[amask]) >> 16);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(6);
			exception2_write(opcode, srca + -4, 0x1, m68k_areg(regs, movem_index2[amask]) >> 16, 1);
			return 4 * CYCLE_UNIT / 2 + count_cycles;
		}
		srca -= 4;
		amask = movem_next[amask];
	}
	while (dmask) {
		put_word_000(srca - 2, m68k_dreg(regs, movem_index2[dmask]));
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(6);
			exception2_write(opcode, srca + -2, 0x1, m68k_dreg(regs, movem_index2[dmask]), 1);
			return 4 * CYCLE_UNIT / 2 + count_cycles;
		}
		put_word_000(srca - 4, m68k_dreg(regs, movem_index2[dmask]) >> 16);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(6);
			exception2_write(opcode, srca + -4, 0x1, m68k_dreg(regs, movem_index2[dmask]) >> 16, 1);
			return 4 * CYCLE_UNIT / 2 + count_cycles;
		}
		srca -= 4;
		dmask = movem_next[dmask];
	}
	m68k_areg(regs, dstreg) = srca;
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8+ (2/0) */
/* 4 0,0   */

/* MVMLE.L #<data>.W,(d16,An) */
uae_u32 REGPARAM2 op_48e8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 38;
	CurrentInstrCycles = 12; 
	uae_u16 mask = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr srca;
	srca = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, 2);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u16 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
	if ((amask || dmask) && (srca & 1)) {
		uaecptr srcav = srca;
		if(dmask) {
			srcav = m68k_dreg(regs, movem_index1[dmask]) >> 16;
		} else if (amask) {
			srcav = m68k_areg(regs, movem_index1[amask]) >> 16;
		}
		m68k_incpci(8);
		exception3_write_access(opcode, srca, 2, srcav, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	while (dmask) {
		put_word_000(srca, m68k_dreg(regs, movem_index1[dmask]) >> 16);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(8);
			exception2_write(opcode, srca + 0, 0x1, m68k_dreg(regs, movem_index1[dmask]) >> 16, 1);
			return 8 * CYCLE_UNIT / 2 + count_cycles;
		}
		put_word_000(srca + 2, m68k_dreg(regs, movem_index1[dmask]));
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(8);
			exception2_write(opcode, srca + 2, 0x1, m68k_dreg(regs, movem_index1[dmask]), 1);
			return 8 * CYCLE_UNIT / 2 + count_cycles;
		}
		srca += 4;
		dmask = movem_next[dmask];
	}
	while (amask) {
		put_word_000(srca, m68k_areg(regs, movem_index1[amask]) >> 16);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(8);
			exception2_write(opcode, srca + 0, 0x1, m68k_areg(regs, movem_index1[amask]) >> 16, 1);
			return 8 * CYCLE_UNIT / 2 + count_cycles;
		}
		put_word_000(srca + 2, m68k_areg(regs, movem_index1[amask]));
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(8);
			exception2_write(opcode, srca + 2, 0x1, m68k_areg(regs, movem_index1[amask]), 1);
			return 8 * CYCLE_UNIT / 2 + count_cycles;
		}
		srca += 4;
		amask = movem_next[amask];
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12+ (3/0) */
/* 6 0,0   */

/* MVMLE.L #<data>.W,(d8,An,Xn) */
uae_u32 REGPARAM2 op_48f0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 38;
	CurrentInstrCycles = 14; 
	uae_u16 mask = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr srca;
	srca = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_000_prefetch(6));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, 2);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u16 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
	if ((amask || dmask) && (srca & 1)) {
		uaecptr srcav = srca;
		if(dmask) {
			srcav = m68k_dreg(regs, movem_index1[dmask]) >> 16;
		} else if (amask) {
			srcav = m68k_areg(regs, movem_index1[amask]) >> 16;
		}
		m68k_incpci(8);
		exception3_write_access(opcode, srca, 2, srcav, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	while (dmask) {
		put_word_000(srca, m68k_dreg(regs, movem_index1[dmask]) >> 16);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(8);
			exception2_write(opcode, srca + 0, 0x1, m68k_dreg(regs, movem_index1[dmask]) >> 16, 1);
			return 10 * CYCLE_UNIT / 2 + count_cycles;
		}
		put_word_000(srca + 2, m68k_dreg(regs, movem_index1[dmask]));
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(8);
			exception2_write(opcode, srca + 2, 0x1, m68k_dreg(regs, movem_index1[dmask]), 1);
			return 10 * CYCLE_UNIT / 2 + count_cycles;
		}
		srca += 4;
		dmask = movem_next[dmask];
	}
	while (amask) {
		put_word_000(srca, m68k_areg(regs, movem_index1[amask]) >> 16);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(8);
			exception2_write(opcode, srca + 0, 0x1, m68k_areg(regs, movem_index1[amask]) >> 16, 1);
			return 10 * CYCLE_UNIT / 2 + count_cycles;
		}
		put_word_000(srca + 2, m68k_areg(regs, movem_index1[amask]));
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(8);
			exception2_write(opcode, srca + 2, 0x1, m68k_areg(regs, movem_index1[amask]), 1);
			return 10 * CYCLE_UNIT / 2 + count_cycles;
		}
		srca += 4;
		amask = movem_next[amask];
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 14 * CYCLE_UNIT / 2 + count_cycles;
}
/* 14+ (3/0) */
/* 6 4,0   */

/* MVMLE.L #<data>.W,(xxx).W */
uae_u32 REGPARAM2 op_48f8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 38;
	CurrentInstrCycles = 12; 
	uae_u16 mask = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, 2);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u16 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
	if ((amask || dmask) && (srca & 1)) {
		uaecptr srcav = srca;
		if(dmask) {
			srcav = m68k_dreg(regs, movem_index1[dmask]) >> 16;
		} else if (amask) {
			srcav = m68k_areg(regs, movem_index1[amask]) >> 16;
		}
		m68k_incpci(8);
		exception3_write_access(opcode, srca, 2, srcav, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	while (dmask) {
		put_word_000(srca, m68k_dreg(regs, movem_index1[dmask]) >> 16);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(8);
			exception2_write(opcode, srca + 0, 0x1, m68k_dreg(regs, movem_index1[dmask]) >> 16, 1);
			return 8 * CYCLE_UNIT / 2 + count_cycles;
		}
		put_word_000(srca + 2, m68k_dreg(regs, movem_index1[dmask]));
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(8);
			exception2_write(opcode, srca + 2, 0x1, m68k_dreg(regs, movem_index1[dmask]), 1);
			return 8 * CYCLE_UNIT / 2 + count_cycles;
		}
		srca += 4;
		dmask = movem_next[dmask];
	}
	while (amask) {
		put_word_000(srca, m68k_areg(regs, movem_index1[amask]) >> 16);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(8);
			exception2_write(opcode, srca + 0, 0x1, m68k_areg(regs, movem_index1[amask]) >> 16, 1);
			return 8 * CYCLE_UNIT / 2 + count_cycles;
		}
		put_word_000(srca + 2, m68k_areg(regs, movem_index1[amask]));
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(8);
			exception2_write(opcode, srca + 2, 0x1, m68k_areg(regs, movem_index1[amask]), 1);
			return 8 * CYCLE_UNIT / 2 + count_cycles;
		}
		srca += 4;
		amask = movem_next[amask];
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12+ (3/0) */
/* 6 0,0   */

/* MVMLE.L #<data>.W,(xxx).L */
uae_u32 REGPARAM2 op_48f9_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 38;
	CurrentInstrCycles = 16; 
	uae_u16 mask = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr srca;
	srca = get_word_000_prefetch(6) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	srca |= get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		pcoffset += 2;
		exception2_fetch(opcode, 8, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u16 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
	if ((amask || dmask) && (srca & 1)) {
		uaecptr srcav = srca;
		if(dmask) {
			srcav = m68k_dreg(regs, movem_index1[dmask]) >> 16;
		} else if (amask) {
			srcav = m68k_areg(regs, movem_index1[amask]) >> 16;
		}
		m68k_incpci(10);
		exception3_write_access(opcode, srca, 2, srcav, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	while (dmask) {
		put_word_000(srca, m68k_dreg(regs, movem_index1[dmask]) >> 16);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(10);
			exception2_write(opcode, srca + 0, 0x1, m68k_dreg(regs, movem_index1[dmask]) >> 16, 1);
			return 12 * CYCLE_UNIT / 2 + count_cycles;
		}
		put_word_000(srca + 2, m68k_dreg(regs, movem_index1[dmask]));
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(10);
			exception2_write(opcode, srca + 2, 0x1, m68k_dreg(regs, movem_index1[dmask]), 1);
			return 12 * CYCLE_UNIT / 2 + count_cycles;
		}
		srca += 4;
		dmask = movem_next[dmask];
	}
	while (amask) {
		put_word_000(srca, m68k_areg(regs, movem_index1[amask]) >> 16);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(10);
			exception2_write(opcode, srca + 0, 0x1, m68k_areg(regs, movem_index1[amask]) >> 16, 1);
			return 12 * CYCLE_UNIT / 2 + count_cycles;
		}
		put_word_000(srca + 2, m68k_areg(regs, movem_index1[amask]));
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(10);
			exception2_write(opcode, srca + 2, 0x1, m68k_areg(regs, movem_index1[amask]), 1);
			return 12 * CYCLE_UNIT / 2 + count_cycles;
		}
		srca += 4;
		amask = movem_next[amask];
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(10);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 10, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(8);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16+ (4/0) */
/* 8 0,0   */

/* TST.B Dn */
uae_u32 REGPARAM2 op_4a00_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 20;
	CurrentInstrCycles = 4;  
	uae_s8 src = m68k_dreg(regs, srcreg);
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 4 * CYCLE_UNIT / 2 + count_cycles;
}
/* 4 (1/0) */
/* 2 0,0   */

/* TST.B (An) */
uae_u32 REGPARAM2 op_4a10_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 20;
	CurrentInstrCycles = 4;  
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	if(!loop_mode) {
		regs.ir = regs.irc;
		opcode = regs.ir;
		get_word_000_prefetch(4);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return 4 * CYCLE_UNIT / 2 + count_cycles;
		}
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return 4 * CYCLE_UNIT / 2 + count_cycles;
}
/* 4+ (1/0) */
/* 2 0,0   */

/* TST.B (An)+ */
uae_u32 REGPARAM2 op_4a18_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 20;
	CurrentInstrCycles = 4;  
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	if(!loop_mode) {
		regs.ir = regs.irc;
		opcode = regs.ir;
		get_word_000_prefetch(4);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return 4 * CYCLE_UNIT / 2 + count_cycles;
		}
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return 4 * CYCLE_UNIT / 2 + count_cycles;
}
/* 4+ (1/0) */
/* 2 0,0   */

/* TST.B -(An) */
uae_u32 REGPARAM2 op_4a20_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 20;
	CurrentInstrCycles = 6;  
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) = srca;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	if(!loop_mode) {
		regs.ir = regs.irc;
		opcode = regs.ir;
		get_word_000_prefetch(4);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return 6 * CYCLE_UNIT / 2 + count_cycles;
		}
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return 6 * CYCLE_UNIT / 2 + count_cycles;
}
/* 6+ (1/0) */
/* 2 0,0   */

/* TST.B (d16,An) */
uae_u32 REGPARAM2 op_4a28_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 20;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (3/0) */
/* 4 0,0   */

/* TST.B (d8,An,Xn) */
uae_u32 REGPARAM2 op_4a30_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 20;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	BusCyclePenalty += 2;
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 14 * CYCLE_UNIT / 2 + count_cycles;
}
/* 14 (3/0) */
/* 4 4,0   */

/* TST.B (xxx).W */
uae_u32 REGPARAM2 op_4a38_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 20;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (3/0) */
/* 4 0,0   */

/* TST.B (xxx).L */
uae_u32 REGPARAM2 op_4a39_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 20;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	srca |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (4/0) */
/* 6 0,0   */

/* TST.W Dn */
uae_u32 REGPARAM2 op_4a40_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 20;
	CurrentInstrCycles = 4;  
	uae_s16 src = m68k_dreg(regs, srcreg);
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 4 * CYCLE_UNIT / 2 + count_cycles;
}
/* 4 (1/0) */
/* 2 0,0   */

/* TST.W (An) */
uae_u32 REGPARAM2 op_4a50_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 20;
	CurrentInstrCycles = 4;  
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access2(opcode, srca, 1, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if(!loop_mode) {
		regs.ir = regs.irc;
		opcode = regs.ir;
		get_word_000_prefetch(4);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return 4 * CYCLE_UNIT / 2 + count_cycles;
		}
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return 4 * CYCLE_UNIT / 2 + count_cycles;
}
/* 4+ (1/0) */
/* 2 0,0   */

/* TST.W (An)+ */
uae_u32 REGPARAM2 op_4a58_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 20;
	CurrentInstrCycles = 4;  
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_areg(regs, srcreg) += 2 + 0;
		m68k_incpci(2);
		exception3_read_access2(opcode, srca, 1, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) += 2 + 0;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) += 2;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if(!loop_mode) {
		regs.ir = regs.irc;
		opcode = regs.ir;
		get_word_000_prefetch(4);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return 4 * CYCLE_UNIT / 2 + count_cycles;
		}
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return 4 * CYCLE_UNIT / 2 + count_cycles;
}
/* 4+ (1/0) */
/* 2 0,0   */

/* TST.W -(An) */
uae_u32 REGPARAM2 op_4a60_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 20;
	CurrentInstrCycles = 6;  
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - 2;
	if (srca & 1) {
		m68k_areg(regs, srcreg) = srca;
		m68k_incpci(2);
		exception3_read_access2(opcode, srca, 1, 1);
		return 2 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) = srca;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if(!loop_mode) {
		regs.ir = regs.irc;
		opcode = regs.ir;
		get_word_000_prefetch(4);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return 6 * CYCLE_UNIT / 2 + count_cycles;
		}
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return 6 * CYCLE_UNIT / 2 + count_cycles;
}
/* 6+ (1/0) */
/* 2 0,0   */

/* TST.W (d16,An) */
uae_u32 REGPARAM2 op_4a68_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 20;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (3/0) */
/* 4 0,0   */

/* TST.W (d8,An,Xn) */
uae_u32 REGPARAM2 op_4a70_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 20;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	BusCyclePenalty += 2;
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 14 * CYCLE_UNIT / 2 + count_cycles;
}
/* 14 (3/0) */
/* 4 4,0   */

/* TST.W (xxx).W */
uae_u32 REGPARAM2 op_4a78_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 20;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, srca, 1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (3/0) */
/* 4 0,0   */

/* TST.W (xxx).L */
uae_u32 REGPARAM2 op_4a79_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 20;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	srca |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, srca, 1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (4/0) */
/* 6 0,0   */

/* TST.L Dn */
uae_u32 REGPARAM2 op_4a80_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 20;
	CurrentInstrCycles = 4;  
	uae_s32 src = m68k_dreg(regs, srcreg);
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 4 * CYCLE_UNIT / 2 + count_cycles;
}
/* 4 (1/0) */
/* 2 0,0   */

/* TST.L (An) */
uae_u32 REGPARAM2 op_4a90_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 20;
	CurrentInstrCycles = 8;  
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	if(!loop_mode) {
		regs.ir = regs.irc;
		opcode = regs.ir;
		get_word_000_prefetch(4);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return 8 * CYCLE_UNIT / 2 + count_cycles;
		}
	} else {
		loop_mode = 0;
		loop_mode |= 6;
		loop_mode |= 4 << 16;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8+ (2/0) */
/* 2 0,0   */

/* TST.L (An)+ */
uae_u32 REGPARAM2 op_4a98_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 20;
	CurrentInstrCycles = 8;  
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) += 4;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	if(!loop_mode) {
		regs.ir = regs.irc;
		opcode = regs.ir;
		get_word_000_prefetch(4);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return 8 * CYCLE_UNIT / 2 + count_cycles;
		}
	} else {
		loop_mode = 0;
		loop_mode |= 6;
		loop_mode |= 4 << 16;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8+ (2/0) */
/* 2 0,0   */

/* TST.L -(An) */
uae_u32 REGPARAM2 op_4aa0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 20;
	CurrentInstrCycles = 10; 
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - 4;
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return 2 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) = srca;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	if(!loop_mode) {
		regs.ir = regs.irc;
		opcode = regs.ir;
		get_word_000_prefetch(4);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return 10 * CYCLE_UNIT / 2 + count_cycles;
		}
	} else {
		loop_mode = 0;
		loop_mode |= 6;
		loop_mode |= 4 << 16;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return 10 * CYCLE_UNIT / 2 + count_cycles;
}
/* 10+ (2/0) */
/* 2 0,0   */

/* TST.L (d16,An) */
uae_u32 REGPARAM2 op_4aa8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 20;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (4/0) */
/* 4 0,0   */

/* TST.L (d8,An,Xn) */
uae_u32 REGPARAM2 op_4ab0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 20;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	BusCyclePenalty += 2;
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (4/0) */
/* 4 4,0   */

/* TST.L (xxx).W */
uae_u32 REGPARAM2 op_4ab8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 20;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, srca, 2, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (4/0) */
/* 4 0,0   */

/* TST.L (xxx).L */
uae_u32 REGPARAM2 op_4ab9_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 20;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	srca = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	srca |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, srca, 2, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (5/0) */
/* 6 0,0   */

/* TAS.B Dn */
uae_u32 REGPARAM2 op_4ac0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 98;
	CurrentInstrCycles = 4;  
	uae_s8 src = m68k_dreg(regs, srcreg);
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	src |= 0x80;
	m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((src) & 0xff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 4 * CYCLE_UNIT / 2 + count_cycles;
}
/* 4 (1/0) */
/* 2 0,0   */

/* TAS.B (An) */
uae_u32 REGPARAM2 op_4ad0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 98;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	uae_u8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		regs.read_buffer = regs.irc & 0xff00;
		regs.read_buffer |= 0x80;
		opcode |= 0x80000;
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 2 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	src |= 0x80;
	put_byte_000(srca, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		opcode |= 0x80000;
		exception2_write(opcode, srca + 0, 0x0, src, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (1/1) */
/* 2 0,0   */

/* TAS.B (An)+ */
uae_u32 REGPARAM2 op_4ad8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 98;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
	uae_u8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		regs.read_buffer = regs.irc & 0xff00;
		regs.read_buffer |= 0x80;
		opcode |= 0x80000;
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	src |= 0x80;
	put_byte_000(srca, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		opcode |= 0x80000;
		exception2_write(opcode, srca + 0, 0x0, src, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 14 * CYCLE_UNIT / 2 + count_cycles;
}
/* 14 (1/1) */
/* 2 0,0   */

/* TAS.B -(An) */
uae_u32 REGPARAM2 op_4ae0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 98;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
	m68k_areg(regs, srcreg) = srca;
	uae_u8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		regs.read_buffer = regs.irc & 0xff00;
		regs.read_buffer |= 0x80;
		opcode |= 0x80000;
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	src |= 0x80;
	put_byte_000(srca, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		opcode |= 0x80000;
		exception2_write(opcode, srca + 0, 0x0, src, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 14 * CYCLE_UNIT / 2 + count_cycles;
}
/* 14 (1/1) */
/* 2 0,0   */

/* TAS.B (d16,An) */
uae_u32 REGPARAM2 op_4ae8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 98;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		regs.read_buffer = regs.irc & 0xff00;
		regs.read_buffer |= 0x80;
		m68k_incpci(2);
		opcode |= 0x80000;
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	src |= 0x80;
	put_byte_000(srca, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		opcode |= 0x80000;
		exception2_write(opcode, srca + 0, 0x0, src, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 14 * CYCLE_UNIT / 2 + count_cycles;
}
/* 14 (2/1) */
/* 4 0,0   */

/* TAS.B (d8,An,Xn) */
uae_u32 REGPARAM2 op_4af0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 98;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		regs.read_buffer = regs.irc & 0xff00;
		regs.read_buffer |= 0x80;
		m68k_incpci(2);
		opcode |= 0x80000;
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	src |= 0x80;
	put_byte_000(srca, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		opcode |= 0x80000;
		exception2_write(opcode, srca + 0, 0x0, src, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (2/1) */
/* 4 4,0   */

/* TAS.B (xxx).W */
uae_u32 REGPARAM2 op_4af8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 98;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		regs.read_buffer = regs.irc & 0xff00;
		regs.read_buffer |= 0x80;
		m68k_incpci(2);
		opcode |= 0x80000;
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	src |= 0x80;
	put_byte_000(srca, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		opcode |= 0x80000;
		exception2_write(opcode, srca + 0, 0x0, src, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 14 * CYCLE_UNIT / 2 + count_cycles;
}
/* 14 (2/1) */
/* 4 0,0   */

/* TAS.B (xxx).L */
uae_u32 REGPARAM2 op_4af9_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 98;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	srca = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	srca |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		regs.read_buffer = regs.irc & 0xff00;
		regs.read_buffer |= 0x80;
		m68k_incpci(2);
		opcode |= 0x80000;
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	src |= 0x80;
	put_byte_000(srca, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		opcode |= 0x80000;
		exception2_write(opcode, srca + 0, 0x0, src, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (3/1) */
/* 6 0,0   */

/* MVMEL.W #<data>.W,(An) */
uae_u32 REGPARAM2 op_4c90_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 37;
	CurrentInstrCycles = 12; 
	uae_u16 mask = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
	uaecptr srca;
	srca = m68k_areg(regs, dstreg);
	if (srca & 1) {
		uaecptr srcav = srca;
		m68k_incpci(6);
		exception3_read_access(opcode, srca, 1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	while (dmask) {
		uae_u32 v = (uae_s32)(uae_s16)get_word_000(srca);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(6);
			exception2_read(opcode, srca + 0, 0x1, 1);
			return 4 * CYCLE_UNIT / 2 + count_cycles;
		}
		m68k_dreg(regs, movem_index1[dmask]) = v;
		srca += 2;
		dmask = movem_next[dmask];
	}
	while (amask) {
		uae_u32 v = (uae_s32)(uae_s16)get_word_000(srca);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(6);
			exception2_read(opcode, srca + 0, 0x1, 1);
			return 4 * CYCLE_UNIT / 2 + count_cycles;
		}
		m68k_areg(regs, movem_index1[amask]) = v;
		srca += 2;
		amask = movem_next[amask];
	}
	get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12+ (3/0) */
/* 4 0,0   */

/* MVMEL.W #<data>.W,(An)+ */
uae_u32 REGPARAM2 op_4c98_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 37;
	CurrentInstrCycles = 12; 
	uae_u16 mask = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
	uaecptr srca;
	srca = m68k_areg(regs, dstreg);
	if (srca & 1) {
		uaecptr srcav = srca;
		m68k_incpci(6);
		exception3_read_access(opcode, srca, 1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	while (dmask) {
		uae_u32 v = (uae_s32)(uae_s16)get_word_000(srca);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(6);
			exception2_read(opcode, srca + 0, 0x1, 1);
			return 4 * CYCLE_UNIT / 2 + count_cycles;
		}
		m68k_dreg(regs, movem_index1[dmask]) = v;
		srca += 2;
		dmask = movem_next[dmask];
	}
	while (amask) {
		uae_u32 v = (uae_s32)(uae_s16)get_word_000(srca);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(6);
			exception2_read(opcode, srca + 0, 0x1, 1);
			return 4 * CYCLE_UNIT / 2 + count_cycles;
		}
		m68k_areg(regs, movem_index1[amask]) = v;
		srca += 2;
		amask = movem_next[amask];
	}
	get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) = srca;
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12+ (3/0) */
/* 4 0,0   */

/* MVMEL.W #<data>.W,(d16,An) */
uae_u32 REGPARAM2 op_4ca8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 37;
	CurrentInstrCycles = 16; 
	uae_u16 mask = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
	uaecptr srca;
	srca = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		uaecptr srcav = srca;
		m68k_incpci(8);
		exception3_read_access(opcode, srca, 1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	while (dmask) {
		uae_u32 v = (uae_s32)(uae_s16)get_word_000(srca);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(8);
			exception2_read(opcode, srca + 0, 0x1, 1);
			return 8 * CYCLE_UNIT / 2 + count_cycles;
		}
		m68k_dreg(regs, movem_index1[dmask]) = v;
		srca += 2;
		dmask = movem_next[dmask];
	}
	while (amask) {
		uae_u32 v = (uae_s32)(uae_s16)get_word_000(srca);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(8);
			exception2_read(opcode, srca + 0, 0x1, 1);
			return 8 * CYCLE_UNIT / 2 + count_cycles;
		}
		m68k_areg(regs, movem_index1[amask]) = v;
		srca += 2;
		amask = movem_next[amask];
	}
	get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16+ (4/0) */
/* 6 0,0   */

/* MVMEL.W #<data>.W,(d8,An,Xn) */
uae_u32 REGPARAM2 op_4cb0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 37;
	CurrentInstrCycles = 18; 
	uae_u16 mask = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
	uaecptr srca;
	srca = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_000_prefetch(6));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		uaecptr srcav = srca;
		m68k_incpci(8);
		exception3_read_access(opcode, srca, 1, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	while (dmask) {
		uae_u32 v = (uae_s32)(uae_s16)get_word_000(srca);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(8);
			exception2_read(opcode, srca + 0, 0x1, 1);
			return 10 * CYCLE_UNIT / 2 + count_cycles;
		}
		m68k_dreg(regs, movem_index1[dmask]) = v;
		srca += 2;
		dmask = movem_next[dmask];
	}
	while (amask) {
		uae_u32 v = (uae_s32)(uae_s16)get_word_000(srca);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(8);
			exception2_read(opcode, srca + 0, 0x1, 1);
			return 10 * CYCLE_UNIT / 2 + count_cycles;
		}
		m68k_areg(regs, movem_index1[amask]) = v;
		srca += 2;
		amask = movem_next[amask];
	}
	get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18+ (4/0) */
/* 6 4,0   */

/* MVMEL.W #<data>.W,(xxx).W */
uae_u32 REGPARAM2 op_4cb8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 37;
	CurrentInstrCycles = 16; 
	uae_u16 mask = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		uaecptr srcav = srca;
		m68k_incpci(8);
		exception3_read_access(opcode, srca, 1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	while (dmask) {
		uae_u32 v = (uae_s32)(uae_s16)get_word_000(srca);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(8);
			exception2_read(opcode, srca + 0, 0x1, 1);
			return 8 * CYCLE_UNIT / 2 + count_cycles;
		}
		m68k_dreg(regs, movem_index1[dmask]) = v;
		srca += 2;
		dmask = movem_next[dmask];
	}
	while (amask) {
		uae_u32 v = (uae_s32)(uae_s16)get_word_000(srca);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(8);
			exception2_read(opcode, srca + 0, 0x1, 1);
			return 8 * CYCLE_UNIT / 2 + count_cycles;
		}
		m68k_areg(regs, movem_index1[amask]) = v;
		srca += 2;
		amask = movem_next[amask];
	}
	get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16+ (4/0) */
/* 6 0,0   */

/* MVMEL.W #<data>.W,(xxx).L */
uae_u32 REGPARAM2 op_4cb9_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 37;
	CurrentInstrCycles = 20; 
	uae_u16 mask = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
	uaecptr srca;
	srca = get_word_000_prefetch(6) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	srca |= get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 8, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		uaecptr srcav = srca;
		m68k_incpci(10);
		exception3_read_access(opcode, srca, 1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	while (dmask) {
		uae_u32 v = (uae_s32)(uae_s16)get_word_000(srca);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(10);
			exception2_read(opcode, srca + 0, 0x1, 1);
			return 12 * CYCLE_UNIT / 2 + count_cycles;
		}
		m68k_dreg(regs, movem_index1[dmask]) = v;
		srca += 2;
		dmask = movem_next[dmask];
	}
	while (amask) {
		uae_u32 v = (uae_s32)(uae_s16)get_word_000(srca);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(10);
			exception2_read(opcode, srca + 0, 0x1, 1);
			return 12 * CYCLE_UNIT / 2 + count_cycles;
		}
		m68k_areg(regs, movem_index1[amask]) = v;
		srca += 2;
		amask = movem_next[amask];
	}
	get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(10);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(10);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 10, pcoffset);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(8);
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20+ (5/0) */
/* 8 0,0   */

/* MVMEL.W #<data>.W,(d16,PC) */
uae_u32 REGPARAM2 op_4cba_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 dstreg = 2;
	OpcodeFamily = 37;
	CurrentInstrCycles = 16; 
	uae_u16 mask = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
	uaecptr srca;
	srca = m68k_getpci() + 4;
	srca += (uae_s32)(uae_s16)get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		uaecptr srcav = srca;
		m68k_incpci(8);
		exception3_read_access(opcode, srca, 1, 2);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	while (dmask) {
		uae_u32 v = (uae_s32)(uae_s16)get_word_000(srca);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(8);
			exception2_read(opcode, srca + 0, 0x1, 2);
			return 8 * CYCLE_UNIT / 2 + count_cycles;
		}
		m68k_dreg(regs, movem_index1[dmask]) = v;
		srca += 2;
		dmask = movem_next[dmask];
	}
	while (amask) {
		uae_u32 v = (uae_s32)(uae_s16)get_word_000(srca);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(8);
			exception2_read(opcode, srca + 0, 0x1, 2);
			return 8 * CYCLE_UNIT / 2 + count_cycles;
		}
		m68k_areg(regs, movem_index1[amask]) = v;
		srca += 2;
		amask = movem_next[amask];
	}
	get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16+ (4/0) */
/* 6 0,0   */

/* MVMEL.W #<data>.W,(d8,PC,Xn) */
uae_u32 REGPARAM2 op_4cbb_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 dstreg = 3;
	OpcodeFamily = 37;
	CurrentInstrCycles = 18; 
	uae_u16 mask = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
	uaecptr srca;
	uaecptr tmppc = m68k_getpci() + 4;
	srca = get_disp_ea_000(tmppc, get_word_000_prefetch(6));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		uaecptr srcav = srca;
		m68k_incpci(8);
		exception3_read_access(opcode, srca, 1, 2);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	while (dmask) {
		uae_u32 v = (uae_s32)(uae_s16)get_word_000(srca);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(8);
			exception2_read(opcode, srca + 0, 0x1, 2);
			return 10 * CYCLE_UNIT / 2 + count_cycles;
		}
		m68k_dreg(regs, movem_index1[dmask]) = v;
		srca += 2;
		dmask = movem_next[dmask];
	}
	while (amask) {
		uae_u32 v = (uae_s32)(uae_s16)get_word_000(srca);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(8);
			exception2_read(opcode, srca + 0, 0x1, 2);
			return 10 * CYCLE_UNIT / 2 + count_cycles;
		}
		m68k_areg(regs, movem_index1[amask]) = v;
		srca += 2;
		amask = movem_next[amask];
	}
	get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18+ (4/0) */
/* 6 4,0   */

/* MVMEL.L #<data>.W,(An) */
uae_u32 REGPARAM2 op_4cd0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 37;
	CurrentInstrCycles = 12; 
	uae_u16 mask = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
	uaecptr srca;
	srca = m68k_areg(regs, dstreg);
	if (srca & 1) {
		uaecptr srcav = srca;
		m68k_incpci(6);
		exception3_read_access(opcode, srca, 2, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	while (dmask) {
		uae_u32 v = (get_word_000(srca) << 16) | (m68k_dreg(regs, movem_index1[dmask]) & 0xffff);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(6);
			exception2_read(opcode, srca + 0, 0x1, 1);
			return 4 * CYCLE_UNIT / 2 + count_cycles;
		}
		v &= 0xffff0000;
		v |= get_word_000(srca + 2); 
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(6);
			exception2_read(opcode, srca + 2, 0x1, 1);
			return 4 * CYCLE_UNIT / 2 + count_cycles;
		}
		m68k_dreg(regs, movem_index1[dmask]) = v;
		srca += 4;
		dmask = movem_next[dmask];
	}
	while (amask) {
		uae_u32 v = (get_word_000(srca) << 16) | (m68k_areg(regs, movem_index1[amask]) & 0xffff);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(6);
			exception2_read(opcode, srca + 0, 0x1, 1);
			return 4 * CYCLE_UNIT / 2 + count_cycles;
		}
		v &= 0xffff0000;
		v |= get_word_000(srca + 2);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(6);
			exception2_read(opcode, srca + 2, 0x1, 1);
			return 4 * CYCLE_UNIT / 2 + count_cycles;
		}
		m68k_areg(regs, movem_index1[amask]) = v;
		srca += 4;
		amask = movem_next[amask];
	}
	get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12+ (3/0) */
/* 4 0,0   */

/* MVMEL.L #<data>.W,(An)+ */
uae_u32 REGPARAM2 op_4cd8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 37;
	CurrentInstrCycles = 12; 
	uae_u16 mask = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
	uaecptr srca;
	srca = m68k_areg(regs, dstreg);
	if (srca & 1) {
		uaecptr srcav = srca;
		m68k_incpci(6);
		exception3_read_access(opcode, srca, 2, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	while (dmask) {
		uae_u32 v = (get_word_000(srca) << 16) | (m68k_dreg(regs, movem_index1[dmask]) & 0xffff);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(6);
			exception2_read(opcode, srca + 0, 0x1, 1);
			return 4 * CYCLE_UNIT / 2 + count_cycles;
		}
		v &= 0xffff0000;
		v |= get_word_000(srca + 2); 
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(6);
			exception2_read(opcode, srca + 2, 0x1, 1);
			return 4 * CYCLE_UNIT / 2 + count_cycles;
		}
		m68k_dreg(regs, movem_index1[dmask]) = v;
		srca += 4;
		dmask = movem_next[dmask];
	}
	while (amask) {
		uae_u32 v = (get_word_000(srca) << 16) | (m68k_areg(regs, movem_index1[amask]) & 0xffff);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(6);
			exception2_read(opcode, srca + 0, 0x1, 1);
			return 4 * CYCLE_UNIT / 2 + count_cycles;
		}
		v &= 0xffff0000;
		v |= get_word_000(srca + 2);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(6);
			exception2_read(opcode, srca + 2, 0x1, 1);
			return 4 * CYCLE_UNIT / 2 + count_cycles;
		}
		m68k_areg(regs, movem_index1[amask]) = v;
		srca += 4;
		amask = movem_next[amask];
	}
	get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) = srca;
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12+ (3/0) */
/* 4 0,0   */

/* MVMEL.L #<data>.W,(d16,An) */
uae_u32 REGPARAM2 op_4ce8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 37;
	CurrentInstrCycles = 16; 
	uae_u16 mask = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
	uaecptr srca;
	srca = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		uaecptr srcav = srca;
		m68k_incpci(8);
		exception3_read_access(opcode, srca, 2, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	while (dmask) {
		uae_u32 v = (get_word_000(srca) << 16) | (m68k_dreg(regs, movem_index1[dmask]) & 0xffff);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(8);
			exception2_read(opcode, srca + 0, 0x1, 1);
			return 8 * CYCLE_UNIT / 2 + count_cycles;
		}
		v &= 0xffff0000;
		v |= get_word_000(srca + 2); 
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(8);
			exception2_read(opcode, srca + 2, 0x1, 1);
			return 8 * CYCLE_UNIT / 2 + count_cycles;
		}
		m68k_dreg(regs, movem_index1[dmask]) = v;
		srca += 4;
		dmask = movem_next[dmask];
	}
	while (amask) {
		uae_u32 v = (get_word_000(srca) << 16) | (m68k_areg(regs, movem_index1[amask]) & 0xffff);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(8);
			exception2_read(opcode, srca + 0, 0x1, 1);
			return 8 * CYCLE_UNIT / 2 + count_cycles;
		}
		v &= 0xffff0000;
		v |= get_word_000(srca + 2);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(8);
			exception2_read(opcode, srca + 2, 0x1, 1);
			return 8 * CYCLE_UNIT / 2 + count_cycles;
		}
		m68k_areg(regs, movem_index1[amask]) = v;
		srca += 4;
		amask = movem_next[amask];
	}
	get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16+ (4/0) */
/* 6 0,0   */

/* MVMEL.L #<data>.W,(d8,An,Xn) */
uae_u32 REGPARAM2 op_4cf0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 37;
	CurrentInstrCycles = 18; 
	uae_u16 mask = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
	uaecptr srca;
	srca = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_000_prefetch(6));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		uaecptr srcav = srca;
		m68k_incpci(8);
		exception3_read_access(opcode, srca, 2, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	while (dmask) {
		uae_u32 v = (get_word_000(srca) << 16) | (m68k_dreg(regs, movem_index1[dmask]) & 0xffff);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(8);
			exception2_read(opcode, srca + 0, 0x1, 1);
			return 10 * CYCLE_UNIT / 2 + count_cycles;
		}
		v &= 0xffff0000;
		v |= get_word_000(srca + 2); 
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(8);
			exception2_read(opcode, srca + 2, 0x1, 1);
			return 10 * CYCLE_UNIT / 2 + count_cycles;
		}
		m68k_dreg(regs, movem_index1[dmask]) = v;
		srca += 4;
		dmask = movem_next[dmask];
	}
	while (amask) {
		uae_u32 v = (get_word_000(srca) << 16) | (m68k_areg(regs, movem_index1[amask]) & 0xffff);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(8);
			exception2_read(opcode, srca + 0, 0x1, 1);
			return 10 * CYCLE_UNIT / 2 + count_cycles;
		}
		v &= 0xffff0000;
		v |= get_word_000(srca + 2);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(8);
			exception2_read(opcode, srca + 2, 0x1, 1);
			return 10 * CYCLE_UNIT / 2 + count_cycles;
		}
		m68k_areg(regs, movem_index1[amask]) = v;
		srca += 4;
		amask = movem_next[amask];
	}
	get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18+ (4/0) */
/* 6 4,0   */

/* MVMEL.L #<data>.W,(xxx).W */
uae_u32 REGPARAM2 op_4cf8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 37;
	CurrentInstrCycles = 16; 
	uae_u16 mask = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		uaecptr srcav = srca;
		m68k_incpci(8);
		exception3_read_access(opcode, srca, 2, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	while (dmask) {
		uae_u32 v = (get_word_000(srca) << 16) | (m68k_dreg(regs, movem_index1[dmask]) & 0xffff);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(8);
			exception2_read(opcode, srca + 0, 0x1, 1);
			return 8 * CYCLE_UNIT / 2 + count_cycles;
		}
		v &= 0xffff0000;
		v |= get_word_000(srca + 2); 
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(8);
			exception2_read(opcode, srca + 2, 0x1, 1);
			return 8 * CYCLE_UNIT / 2 + count_cycles;
		}
		m68k_dreg(regs, movem_index1[dmask]) = v;
		srca += 4;
		dmask = movem_next[dmask];
	}
	while (amask) {
		uae_u32 v = (get_word_000(srca) << 16) | (m68k_areg(regs, movem_index1[amask]) & 0xffff);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(8);
			exception2_read(opcode, srca + 0, 0x1, 1);
			return 8 * CYCLE_UNIT / 2 + count_cycles;
		}
		v &= 0xffff0000;
		v |= get_word_000(srca + 2);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(8);
			exception2_read(opcode, srca + 2, 0x1, 1);
			return 8 * CYCLE_UNIT / 2 + count_cycles;
		}
		m68k_areg(regs, movem_index1[amask]) = v;
		srca += 4;
		amask = movem_next[amask];
	}
	get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16+ (4/0) */
/* 6 0,0   */

/* MVMEL.L #<data>.W,(xxx).L */
uae_u32 REGPARAM2 op_4cf9_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 37;
	CurrentInstrCycles = 20; 
	uae_u16 mask = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
	uaecptr srca;
	srca = get_word_000_prefetch(6) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	srca |= get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 8, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		uaecptr srcav = srca;
		m68k_incpci(10);
		exception3_read_access(opcode, srca, 2, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	while (dmask) {
		uae_u32 v = (get_word_000(srca) << 16) | (m68k_dreg(regs, movem_index1[dmask]) & 0xffff);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(10);
			exception2_read(opcode, srca + 0, 0x1, 1);
			return 12 * CYCLE_UNIT / 2 + count_cycles;
		}
		v &= 0xffff0000;
		v |= get_word_000(srca + 2); 
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(10);
			exception2_read(opcode, srca + 2, 0x1, 1);
			return 12 * CYCLE_UNIT / 2 + count_cycles;
		}
		m68k_dreg(regs, movem_index1[dmask]) = v;
		srca += 4;
		dmask = movem_next[dmask];
	}
	while (amask) {
		uae_u32 v = (get_word_000(srca) << 16) | (m68k_areg(regs, movem_index1[amask]) & 0xffff);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(10);
			exception2_read(opcode, srca + 0, 0x1, 1);
			return 12 * CYCLE_UNIT / 2 + count_cycles;
		}
		v &= 0xffff0000;
		v |= get_word_000(srca + 2);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(10);
			exception2_read(opcode, srca + 2, 0x1, 1);
			return 12 * CYCLE_UNIT / 2 + count_cycles;
		}
		m68k_areg(regs, movem_index1[amask]) = v;
		srca += 4;
		amask = movem_next[amask];
	}
	get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(10);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(10);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 10, pcoffset);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(8);
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20+ (5/0) */
/* 8 0,0   */

/* MVMEL.L #<data>.W,(d16,PC) */
uae_u32 REGPARAM2 op_4cfa_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 dstreg = 2;
	OpcodeFamily = 37;
	CurrentInstrCycles = 16; 
	uae_u16 mask = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
	uaecptr srca;
	srca = m68k_getpci() + 4;
	srca += (uae_s32)(uae_s16)get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		uaecptr srcav = srca;
		m68k_incpci(8);
		exception3_read_access(opcode, srca, 2, 2);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	while (dmask) {
		uae_u32 v = (get_word_000(srca) << 16) | (m68k_dreg(regs, movem_index1[dmask]) & 0xffff);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(8);
			exception2_read(opcode, srca + 0, 0x1, 2);
			return 8 * CYCLE_UNIT / 2 + count_cycles;
		}
		v &= 0xffff0000;
		v |= get_word_000(srca + 2); 
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(8);
			exception2_read(opcode, srca + 2, 0x1, 2);
			return 8 * CYCLE_UNIT / 2 + count_cycles;
		}
		m68k_dreg(regs, movem_index1[dmask]) = v;
		srca += 4;
		dmask = movem_next[dmask];
	}
	while (amask) {
		uae_u32 v = (get_word_000(srca) << 16) | (m68k_areg(regs, movem_index1[amask]) & 0xffff);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(8);
			exception2_read(opcode, srca + 0, 0x1, 2);
			return 8 * CYCLE_UNIT / 2 + count_cycles;
		}
		v &= 0xffff0000;
		v |= get_word_000(srca + 2);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(8);
			exception2_read(opcode, srca + 2, 0x1, 2);
			return 8 * CYCLE_UNIT / 2 + count_cycles;
		}
		m68k_areg(regs, movem_index1[amask]) = v;
		srca += 4;
		amask = movem_next[amask];
	}
	get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16+ (4/0) */
/* 6 0,0   */

/* MVMEL.L #<data>.W,(d8,PC,Xn) */
uae_u32 REGPARAM2 op_4cfb_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 dstreg = 3;
	OpcodeFamily = 37;
	CurrentInstrCycles = 18; 
	uae_u16 mask = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
	uaecptr srca;
	uaecptr tmppc = m68k_getpci() + 4;
	srca = get_disp_ea_000(tmppc, get_word_000_prefetch(6));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		uaecptr srcav = srca;
		m68k_incpci(8);
		exception3_read_access(opcode, srca, 2, 2);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	while (dmask) {
		uae_u32 v = (get_word_000(srca) << 16) | (m68k_dreg(regs, movem_index1[dmask]) & 0xffff);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(8);
			exception2_read(opcode, srca + 0, 0x1, 2);
			return 10 * CYCLE_UNIT / 2 + count_cycles;
		}
		v &= 0xffff0000;
		v |= get_word_000(srca + 2); 
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(8);
			exception2_read(opcode, srca + 2, 0x1, 2);
			return 10 * CYCLE_UNIT / 2 + count_cycles;
		}
		m68k_dreg(regs, movem_index1[dmask]) = v;
		srca += 4;
		dmask = movem_next[dmask];
	}
	while (amask) {
		uae_u32 v = (get_word_000(srca) << 16) | (m68k_areg(regs, movem_index1[amask]) & 0xffff);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(8);
			exception2_read(opcode, srca + 0, 0x1, 2);
			return 10 * CYCLE_UNIT / 2 + count_cycles;
		}
		v &= 0xffff0000;
		v |= get_word_000(srca + 2);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(8);
			exception2_read(opcode, srca + 2, 0x1, 2);
			return 10 * CYCLE_UNIT / 2 + count_cycles;
		}
		m68k_areg(regs, movem_index1[amask]) = v;
		srca += 4;
		amask = movem_next[amask];
	}
	get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18+ (4/0) */
/* 6 4,0   */

/* TRAPQ.L #<data> */
uae_u32 REGPARAM2 op_4e40_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 15);
	OpcodeFamily = 39;
	CurrentInstrCycles = 4;  
	uae_u32 src = srcreg;
	m68k_incpci(2);
	Exception_cpu(src + 32);
	return 0 * CYCLE_UNIT / 2 + count_cycles;
	return 4 * CYCLE_UNIT / 2 + count_cycles;
}
/* 4 (0/0) */
/* 2 0,0   */

/* LINK.W An,#<data>.W */
uae_u32 REGPARAM2 op_4e50_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 47;
	CurrentInstrCycles = 16; 
	uae_s32 src = m68k_areg(regs, srcreg);
	uaecptr olda;
	olda = m68k_areg(regs, 7) - 4;
	m68k_areg(regs, 7) = olda;
	uae_s16 offs = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		m68k_areg(regs, 7) += 4;
		exception2_fetch(opcode, 4, 2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (olda & 1) {
		m68k_areg(regs, 7) += 4;
		m68k_areg(regs, srcreg) = olda;
		m68k_incpci(6);
		exception3_write_access(opcode, olda, sz_word, src >> 16, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(olda, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		m68k_areg(regs, 7) += 4;
		m68k_areg(regs, srcreg) = olda;
		exception2_write(opcode, olda + 0, 0x1, src >> 16, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(olda + 2, src); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		m68k_areg(regs, 7) += 4;
		m68k_areg(regs, srcreg) = olda;
		exception2_write(opcode, olda + 2, 0x1, src, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) = (m68k_areg(regs, 7));
	m68k_areg(regs, 7) += offs;
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (2/2) */
/* 4 0,0   */

/* UNLK.L An */
uae_u32 REGPARAM2 op_4e58_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 48;
	CurrentInstrCycles = 12; 
	uae_s32 src = m68k_areg(regs, srcreg);
	uae_u32 olda = src;
	if (olda & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, olda, 2, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 old = get_word_000(olda) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, olda + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	old |= get_word_000(olda + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, olda + 2, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, 7) = src + 4;
	m68k_areg(regs, srcreg) = (old);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (3/0) */
/* 2 0,0   */

/* MVR2USP.L An */
uae_u32 REGPARAM2 op_4e60_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 40;
	CurrentInstrCycles = 6;  
	if (!regs.s) {
		Exception(8);
		return 0;
	}
	uae_s32 src = m68k_areg(regs, srcreg);
	regs.usp = src;
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 6 * CYCLE_UNIT / 2 + count_cycles;
}
/* 6 (1/0) */
/* 2 0,0   */

/* MVUSP2R.L An */
uae_u32 REGPARAM2 op_4e68_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 41;
	CurrentInstrCycles = 6;  
	if (!regs.s) {
		Exception(8);
		return 0;
	}
	m68k_areg(regs, srcreg) = (regs.usp);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 6 * CYCLE_UNIT / 2 + count_cycles;
}
/* 6 (1/0) */
/* 2 0,0   */

/* RESET.L  */
uae_u32 REGPARAM2 op_4e70_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 42;
	CurrentInstrCycles = 132;
	if (!regs.s) {
		Exception(8);
		return 0;
	}
	bool r = cpureset();
	if (r) {
		return 128 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 132 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 132 * CYCLE_UNIT / 2 + count_cycles;
}
/* 132 (1/0) */
/* 2 0,0   */

/* NOP.L  */
uae_u32 REGPARAM2 op_4e71_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 43;
	CurrentInstrCycles = 4;  
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 4 * CYCLE_UNIT / 2 + count_cycles;
}
/* 4 (1/0) */
/* 2 0,0   */

/* STOP.L #<data>.W */
uae_u32 REGPARAM2 op_4e72_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 44;
	CurrentInstrCycles = 4;  
	if (!regs.s) {
		Exception(8);
		return 0;
	}
	if (!regs.stopped) {
		uae_u16 src = regs.irc;
		regs.irc = src;
	}
	uae_u16 sr = regs.irc;
	checkint();
	regs.sr = sr;
	MakeFromSR_STOP();
	do_cycles_stop(4);
	m68k_setstopped(1);
	return 4 * CYCLE_UNIT / 2 + count_cycles;
}
/* 4 (0/0) */

/* RTE.L  */
uae_u32 REGPARAM2 op_4e73_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 45;
	CurrentInstrCycles = 24; 
	if (!regs.s) {
		Exception(8);
		return 0;
	}
	if (m68k_areg(regs, 7) & 1) {
		exception3_read_access(opcode, m68k_areg(regs, 7), 1, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr oldpc = m68k_getpci();
	uae_u16 newsr;
	uae_u32 newpc;
	uaecptr a = m68k_areg(regs, 7);
	uae_u16 sr = get_word_000(a);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		exception2_read(opcode, a + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u16 format = get_word_000(a + 2 + 4);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		exception2_read(opcode, a + 6, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 pc = get_word_000(a + 2) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		exception2_read(opcode, a + 2, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	int frame = format >> 12;
	int offset = 8;
	if (frame == 0x0) {
		m68k_areg(regs, 7) += offset;
	} else if (frame == 0x8) {
		m68k_areg(regs, 7) += offset + 50;
	} else {
		SET_NFLG(((uae_s16)format) < 0); 
		SET_ZFLG(format == 0);
		SET_VFLG(0);
		Exception_cpu(14);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	pc |= get_word_000(a + 2 + 2); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		exception2_read(opcode, a + 4, 0x1, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.sr = sr;
	MakeFromSR();
	if (pc & 1) {
		m68k_incpci(2);
		exception3_read_prefetch_only(opcode, pc);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	newsr = sr; newpc = pc;
	m68k_setpci_j(newpc);
	#ifdef DEBUGGER
	branch_stack_pop_rte(oldpc);
	#endif
	int pcadjust = oldpc - m68k_getpci() + 2;
	get_word_000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		pcoffset += pcadjust;
		exception2_fetch_opcode(opcode, 0, pcoffset);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 24 * CYCLE_UNIT / 2 + count_cycles;
}
/* 24 (6/0) */
/* 2 0,0 B */

/* RTD.L #<data>.W */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_4e74_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 46;
	CurrentInstrCycles = 16; 
	uaecptr oldpc = m68k_getpci();
	uaecptr pca;
	pca = m68k_areg(regs, 7);
	if (pca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, pca, 2, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 pc = get_word_000(pca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, pca + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	pc |= get_word_000(pca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, pca + 2, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, 7) += 4;
	uae_s16 offs = regs.irc;
	m68k_areg(regs, 7) += offs;
	if (pc & 1) {
		m68k_incpci(2);
		exception3_read_prefetch_only(opcode, pc);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_setpci_j(pc);
	get_word_000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		m68k_setpci_j(oldpc + 2);
		exception2_fetch_opcode(opcode, 0, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		m68k_setpci_j(oldpc + 2);
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (4/0) */
/* 4 0,0 B */

#endif
/* RTS.L  */
uae_u32 REGPARAM2 op_4e75_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 49;
	CurrentInstrCycles = 16; 
	uaecptr oldpc = m68k_getpci();
	if (m68k_areg(regs, 7) & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, m68k_areg(regs, 7), 1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr newpc, dsta = m68k_areg(regs, 7);
	newpc = get_word_000(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	newpc |= get_word_000(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, 7) += 4;
	m68k_setpci_j(newpc);
	#ifdef DEBUGGER
	if (debugmem_trace) {
		branch_stack_pop_rts(oldpc);
	}
	#endif
	if (m68k_getpci() & 1) {
		uaecptr faultpc = m68k_getpci();
		m68k_setpci_j(oldpc);
		m68k_incpci(2);
		exception3_read_prefetch_only(opcode, faultpc);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	int pcadjust = oldpc - m68k_getpci() + 2;
	get_word_000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		pcoffset += pcadjust;
		exception2_fetch_opcode(opcode, 0, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (4/0) */
/* 2 0,0 B */

/* TRAPV.L  */
uae_u32 REGPARAM2 op_4e76_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 50;
	CurrentInstrCycles = 4;  
	m68k_incpci(2);
	if (GET_VFLG()) {
		Exception_cpu(7);
		return 2 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 4 * CYCLE_UNIT / 2 + count_cycles;
}
/* 4 (1/0) */
/* 2 0,0   */

/* RTR.L  */
uae_u32 REGPARAM2 op_4e77_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 51;
	CurrentInstrCycles = 20; 
	if (m68k_areg(regs, 7) & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, m68k_areg(regs, 7), 1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr oldpc = m68k_getpci();
	MakeSR();
	uaecptr sra;
	sra = m68k_areg(regs, 7);
	if (sra & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, sra, 1, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 sr = get_word_000(sra);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, sra + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, 7) += 2;
	uaecptr pca;
	pca = m68k_areg(regs, 7);
	if (pca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, pca, 2, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 pc = get_word_000(pca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, pca + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	pc |= get_word_000(pca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, pca + 2, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, 7) += 4;
	regs.sr &= 0xFF00; sr &= 0xFF;
	regs.sr |= sr;
	MakeFromSR();
	m68k_setpci_j(pc);
	if (m68k_getpci() & 1) {
		uaecptr faultpc = m68k_getpci();
		m68k_setpci_j(oldpc + 2);
		exception3_read_prefetch_only(opcode, faultpc);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	int pcadjust = oldpc - m68k_getpci() + 2;
	get_word_000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		pcoffset += pcadjust;
		exception2_fetch_opcode(opcode, 0, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (5/0) */
/* 2 0,0 B */

/* MOVEC2.L #<data>.W */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_4e7a_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 82;
	CurrentInstrCycles = 12; 
	if(!regs.s) {
		Exception(8);
		return 0;
	}
	uae_s16 src = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	int regno = (src >> 12) & 15;
	uae_u32 *regp = regs.regs + regno;
	if (!m68k_movec2(src & 0xFFF, regp)) {
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (2/0) */
/* 4 0,0   */

#endif
/* MOVE2C.L #<data>.W */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_4e7b_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 83;
	CurrentInstrCycles = 10; 
	if(!regs.s) {
		Exception(8);
		return 0;
	}
	uae_s16 src = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	int regno = (src >> 12) & 15;
	uae_u32 *regp = regs.regs + regno;
	if (!m68k_move2c(src & 0xFFF, regp)) {
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 10 * CYCLE_UNIT / 2 + count_cycles;
}
/* 10 (2/0) */
/* 4 0,0   */

#endif
/* JSR.L (An) */
uae_u32 REGPARAM2 op_4e90_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 52;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	uaecptr oldpc = m68k_getpci();
	uaecptr nextpc = oldpc + 2;
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_prefetch_only(opcode, srca);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_setpci_j(srca);
	get_word_000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		pcoffset = (oldpc - srca) + 2;
		exception2_fetch_opcode(opcode, 0, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, 7) -= 4;
	if (m68k_areg(regs, 7) & 1) {
		m68k_setpci_j(oldpc);
		m68k_incpci(2);
		exception3_write_access(opcode, m68k_areg(regs, 7), 1, oldpc >> 16, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta = m68k_areg(regs, 7);
	put_word_000(dsta, nextpc >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_write(opcode, dsta + 0, 0x1, nextpc >> 16, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta + 2, nextpc);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_write(opcode, dsta + 2, 0x1, nextpc, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	#ifdef DEBUGGER
	if (debugmem_trace) {
		branch_stack_push(oldpc, nextpc);
	}
	#endif
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, 0);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (2/2) */
/* 2 0,0 B */

/* JSR.L (d16,An) */
uae_u32 REGPARAM2 op_4ea8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 52;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)regs.irc;
	uaecptr oldpc = m68k_getpci();
	uaecptr nextpc = oldpc + 4;
	if (srca & 1) {
		count_cycles += 2 * CYCLE_UNIT / 2;
		m68k_incpci(2);
		exception3_read_prefetch_only(opcode, srca);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_setpci_j(srca);
	get_word_000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		pcoffset = (oldpc - srca) + 4;
		exception2_fetch_opcode(opcode, 0, pcoffset);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, 7) -= 4;
	if (m68k_areg(regs, 7) & 1) {
		m68k_setpci_j(oldpc);
		m68k_incpci(4);
		exception3_write_access(opcode, m68k_areg(regs, 7), 1, oldpc >> 16, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta = m68k_areg(regs, 7);
	put_word_000(dsta, nextpc >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_write(opcode, dsta + 0, 0x1, nextpc >> 16, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta + 2, nextpc);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_write(opcode, dsta + 2, 0x1, nextpc, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	#ifdef DEBUGGER
	if (debugmem_trace) {
		branch_stack_push(oldpc, nextpc);
	}
	#endif
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, 0);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (2/2) */
/* 4 0,0 B */

/* JSR.L (d8,An,Xn) */
uae_u32 REGPARAM2 op_4eb0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 52;
	CurrentInstrCycles = 24; 
	uaecptr srca;
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), regs.irc);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr oldpc = m68k_getpci();
	uaecptr nextpc = oldpc + 2;
	if (srca & 1) {
		count_cycles += 6 * CYCLE_UNIT / 2;
		m68k_incpci(2);
		exception3_read_prefetch_only(opcode, srca);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	nextpc += 2;
	m68k_setpci_j(srca);
	get_word_000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		pcoffset = (oldpc - srca) + 4;
		exception2_fetch_opcode(opcode, 0, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, 7) -= 4;
	if (m68k_areg(regs, 7) & 1) {
		m68k_setpci_j(oldpc);
		m68k_incpci(4);
		exception3_write_access(opcode, m68k_areg(regs, 7), 1, oldpc >> 16, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta = m68k_areg(regs, 7);
	put_word_000(dsta, nextpc >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_write(opcode, dsta + 0, 0x1, nextpc >> 16, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta + 2, nextpc);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_write(opcode, dsta + 2, 0x1, nextpc, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	#ifdef DEBUGGER
	if (debugmem_trace) {
		branch_stack_push(oldpc, nextpc);
	}
	#endif
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, 0);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 24 * CYCLE_UNIT / 2 + count_cycles;
}
/* 24 (2/2) */
/* 2 2,0 B */

/* JSR.L (xxx).W */
uae_u32 REGPARAM2 op_4eb8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 52;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)regs.irc;
	uaecptr oldpc = m68k_getpci();
	uaecptr nextpc = oldpc + 4;
	if (srca & 1) {
		count_cycles += 2 * CYCLE_UNIT / 2;
		m68k_incpci(4);
		exception3_read_prefetch_only(opcode, srca);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_setpci_j(srca);
	get_word_000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		pcoffset = (oldpc - srca) + 4;
		exception2_fetch_opcode(opcode, 0, pcoffset);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, 7) -= 4;
	if (m68k_areg(regs, 7) & 1) {
		m68k_setpci_j(oldpc);
		m68k_incpci(4);
		exception3_write_access(opcode, m68k_areg(regs, 7), 1, oldpc >> 16, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta = m68k_areg(regs, 7);
	put_word_000(dsta, nextpc >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x1, nextpc >> 16, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta + 2, nextpc);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 2, 0x1, nextpc, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	#ifdef DEBUGGER
	if (debugmem_trace) {
		branch_stack_push(oldpc, nextpc);
	}
	#endif
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, 0);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (2/2) */
/* 4 0,0 B */

/* JSR.L (xxx).L */
uae_u32 REGPARAM2 op_4eb9_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 52;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	srca = get_word_000_prefetch(4) << 16;
	srca |= regs.irc;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr oldpc = m68k_getpci();
	uaecptr nextpc = oldpc + 6;
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_prefetch_only(opcode, srca);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_setpci_j(srca);
	get_word_000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		pcoffset = (oldpc - srca) + 6;
		exception2_fetch_opcode(opcode, 0, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, 7) -= 4;
	if (m68k_areg(regs, 7) & 1) {
		m68k_setpci_j(oldpc);
		m68k_incpci(6);
		exception3_write_access(opcode, m68k_areg(regs, 7), 1, oldpc >> 16, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta = m68k_areg(regs, 7);
	put_word_000(dsta, nextpc >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, nextpc >> 16, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta + 2, nextpc);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 2, 0x1, nextpc, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	#ifdef DEBUGGER
	if (debugmem_trace) {
		branch_stack_push(oldpc, nextpc);
	}
	#endif
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, 0);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (3/2) */
/* 6 0,0 B */

/* JSR.L (d16,PC) */
uae_u32 REGPARAM2 op_4eba_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 52;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	srca = m68k_getpci() + 2;
	srca += (uae_s32)(uae_s16)regs.irc;
	uaecptr oldpc = m68k_getpci();
	uaecptr nextpc = oldpc + 4;
	if (srca & 1) {
		count_cycles += 2 * CYCLE_UNIT / 2;
		m68k_incpci(2);
		exception3_read_prefetch_only(opcode, srca);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_setpci_j(srca);
	get_word_000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		pcoffset = (oldpc - srca) + 4;
		exception2_fetch_opcode(opcode, 0, pcoffset);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, 7) -= 4;
	if (m68k_areg(regs, 7) & 1) {
		m68k_setpci_j(oldpc);
		m68k_incpci(4);
		exception3_write_access(opcode, m68k_areg(regs, 7), 1, oldpc >> 16, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta = m68k_areg(regs, 7);
	put_word_000(dsta, nextpc >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_write(opcode, dsta + 0, 0x1, nextpc >> 16, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta + 2, nextpc);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_write(opcode, dsta + 2, 0x1, nextpc, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	#ifdef DEBUGGER
	if (debugmem_trace) {
		branch_stack_push(oldpc, nextpc);
	}
	#endif
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, 0);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (2/2) */
/* 4 0,0 B */

/* JSR.L (d8,PC,Xn) */
uae_u32 REGPARAM2 op_4ebb_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 52;
	CurrentInstrCycles = 24; 
	uaecptr srca;
	uaecptr tmppc = m68k_getpci() + 2;
	srca = get_disp_ea_000(tmppc, regs.irc);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr oldpc = m68k_getpci();
	uaecptr nextpc = oldpc + 2;
	if (srca & 1) {
		count_cycles += 6 * CYCLE_UNIT / 2;
		m68k_incpci(2);
		exception3_read_prefetch_only(opcode, srca);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	nextpc += 2;
	m68k_setpci_j(srca);
	get_word_000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		pcoffset = (oldpc - srca) + 4;
		exception2_fetch_opcode(opcode, 0, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, 7) -= 4;
	if (m68k_areg(regs, 7) & 1) {
		m68k_setpci_j(oldpc);
		m68k_incpci(4);
		exception3_write_access(opcode, m68k_areg(regs, 7), 1, oldpc >> 16, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta = m68k_areg(regs, 7);
	put_word_000(dsta, nextpc >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_write(opcode, dsta + 0, 0x1, nextpc >> 16, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta + 2, nextpc);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_write(opcode, dsta + 2, 0x1, nextpc, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	#ifdef DEBUGGER
	if (debugmem_trace) {
		branch_stack_push(oldpc, nextpc);
	}
	#endif
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, 0);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 24 * CYCLE_UNIT / 2 + count_cycles;
}
/* 24 (2/2) */
/* 2 2,0 B */

/* JMP.L (An) */
uae_u32 REGPARAM2 op_4ed0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 53;
	CurrentInstrCycles = 8;  
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	uaecptr oldpc = m68k_getpci();
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_prefetch_only(opcode, srca);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_setpci_j(srca);
	get_word_000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		pcoffset = (oldpc - srca) + 2;
		exception2_fetch_opcode(opcode, 0, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	get_word_000_prefetch(2);
	opcode = regs.ir;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, 0);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8 (2/0) */
/* 2 0,0 B */

/* JMP.L (d16,An) */
uae_u32 REGPARAM2 op_4ee8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 53;
	CurrentInstrCycles = 10; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)regs.irc;
	uaecptr oldpc = m68k_getpci();
	if (srca & 1) {
		count_cycles += 2 * CYCLE_UNIT / 2;
		m68k_incpci(2);
		exception3_read_prefetch_only(opcode, srca);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_setpci_j(srca);
	get_word_000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		pcoffset = (oldpc - srca) + 2;
		exception2_fetch_opcode(opcode, 0, pcoffset);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	get_word_000_prefetch(2);
	opcode = regs.ir;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, 0);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 10 * CYCLE_UNIT / 2 + count_cycles;
}
/* 10 (2/0) */
/* 4 0,0 B */

/* JMP.L (d8,An,Xn) */
uae_u32 REGPARAM2 op_4ef0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 53;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), regs.irc);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr oldpc = m68k_getpci();
	if (srca & 1) {
		count_cycles += 6 * CYCLE_UNIT / 2;
		m68k_incpci(2);
		exception3_read_prefetch_only(opcode, srca);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_setpci_j(srca);
	get_word_000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		pcoffset = (oldpc - srca) + 2;
		exception2_fetch_opcode(opcode, 0, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	get_word_000_prefetch(2);
	opcode = regs.ir;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, 0);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (2/0) */
/* 2 2,0 B */

/* JMP.L (xxx).W */
uae_u32 REGPARAM2 op_4ef8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 53;
	CurrentInstrCycles = 10; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)regs.irc;
	uaecptr oldpc = m68k_getpci();
	if (srca & 1) {
		count_cycles += 2 * CYCLE_UNIT / 2;
		m68k_incpci(2);
		exception3_read_prefetch_only(opcode, srca);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_setpci_j(srca);
	get_word_000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		pcoffset = (oldpc - srca) + 2;
		exception2_fetch_opcode(opcode, 0, pcoffset);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	get_word_000_prefetch(2);
	opcode = regs.ir;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, 0);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 10 * CYCLE_UNIT / 2 + count_cycles;
}
/* 10 (2/0) */
/* 4 0,0 B */

/* JMP.L (xxx).L */
uae_u32 REGPARAM2 op_4ef9_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 53;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = get_word_000_prefetch(4) << 16;
	srca |= regs.irc;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr oldpc = m68k_getpci();
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_prefetch_only(opcode, srca);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_setpci_j(srca);
	get_word_000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		pcoffset = (oldpc - srca) + 2;
		exception2_fetch_opcode(opcode, 0, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	get_word_000_prefetch(2);
	opcode = regs.ir;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, 0);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (3/0) */
/* 6 0,0 B */

/* JMP.L (d16,PC) */
uae_u32 REGPARAM2 op_4efa_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 53;
	CurrentInstrCycles = 10; 
	uaecptr srca;
	srca = m68k_getpci() + 2;
	srca += (uae_s32)(uae_s16)regs.irc;
	uaecptr oldpc = m68k_getpci();
	if (srca & 1) {
		count_cycles += 2 * CYCLE_UNIT / 2;
		m68k_incpci(2);
		exception3_read_prefetch_only(opcode, srca);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_setpci_j(srca);
	get_word_000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		pcoffset = (oldpc - srca) + 2;
		exception2_fetch_opcode(opcode, 0, pcoffset);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	get_word_000_prefetch(2);
	opcode = regs.ir;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, 0);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 10 * CYCLE_UNIT / 2 + count_cycles;
}
/* 10 (2/0) */
/* 4 0,0 B */

/* JMP.L (d8,PC,Xn) */
uae_u32 REGPARAM2 op_4efb_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 53;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	uaecptr tmppc = m68k_getpci() + 2;
	srca = get_disp_ea_000(tmppc, regs.irc);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr oldpc = m68k_getpci();
	if (srca & 1) {
		count_cycles += 6 * CYCLE_UNIT / 2;
		m68k_incpci(2);
		exception3_read_prefetch_only(opcode, srca);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_setpci_j(srca);
	get_word_000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		pcoffset = (oldpc - srca) + 2;
		exception2_fetch_opcode(opcode, 0, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	get_word_000_prefetch(2);
	opcode = regs.ir;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, 0);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (2/0) */
/* 2 2,0 B */

/* ADDQ.B #<data>,Dn */
uae_u32 REGPARAM2 op_5000_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 4;  
	uae_u32 src = srcreg;
	uae_s8 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u8)(~dst)) < ((uae_u8)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 4 * CYCLE_UNIT / 2 + count_cycles;
}
/* 4 (1/0) */
/* 2 0,0   */

/* ADDQ.B #<data>,(An) */
uae_u32 REGPARAM2 op_5010_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 12; 
	uae_u32 src = srcreg;
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u8)(~dst)) < ((uae_u8)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_byte_000(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x0, newv, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (2/1) */
/* 2 0,0   */

/* ADDQ.B #<data>,(An)+ */
uae_u32 REGPARAM2 op_5018_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 12; 
	uae_u32 src = srcreg;
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
	uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u8)(~dst)) < ((uae_u8)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_byte_000(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x0, newv, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (2/1) */
/* 2 0,0   */

/* ADDQ.B #<data>,-(An) */
uae_u32 REGPARAM2 op_5020_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 14; 
	uae_u32 src = srcreg;
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, dstreg) = dsta;
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) = dsta;
	uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u8)(~dst)) < ((uae_u8)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_byte_000(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x0, newv, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 14 * CYCLE_UNIT / 2 + count_cycles;
}
/* 14 (2/1) */
/* 2 0,0   */

/* ADDQ.B #<data>,(d16,An) */
uae_u32 REGPARAM2 op_5028_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 16; 
	uae_u32 src = srcreg;
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u8)(~dst)) < ((uae_u8)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_byte_000(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x0, newv, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 4 0,0   */

/* ADDQ.B #<data>,(d8,An,Xn) */
uae_u32 REGPARAM2 op_5030_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 18; 
	uae_u32 src = srcreg;
	uaecptr dsta;
	BusCyclePenalty += 2;
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u8)(~dst)) < ((uae_u8)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_byte_000(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x0, newv, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (3/1) */
/* 4 4,0   */

/* ADDQ.B #<data>,(xxx).W */
uae_u32 REGPARAM2 op_5038_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	OpcodeFamily = 11;
	CurrentInstrCycles = 16; 
	uae_u32 src = srcreg;
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u8)(~dst)) < ((uae_u8)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_byte_000(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x0, newv, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 4 0,0   */

/* ADDQ.B #<data>,(xxx).L */
uae_u32 REGPARAM2 op_5039_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	OpcodeFamily = 11;
	CurrentInstrCycles = 20; 
	uae_u32 src = srcreg;
	uaecptr dsta;
	dsta = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	dsta |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u8)(~dst)) < ((uae_u8)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_byte_000(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 0, 0x0, newv, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (4/1) */
/* 6 0,0   */

/* ADDQ.W #<data>,Dn */
uae_u32 REGPARAM2 op_5040_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 4;  
	uae_u32 src = srcreg;
	uae_s16 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 4 * CYCLE_UNIT / 2 + count_cycles;
}
/* 4 (1/0) */
/* 2 0,0   */

/* ADDAQ.W #<data>,An */
uae_u32 REGPARAM2 op_5048_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 12;
	CurrentInstrCycles = 8;  
	uae_u32 src = srcreg;
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = dst + src;
	regs.ir = regs.irc;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		areg_68000_long_replace_low(dstreg, newv);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	m68k_areg(regs, dstreg) = (newv);
	m68k_incpci(2);
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8 (1/0) */
/* 2 0,0   */

/* ADDQ.W #<data>,(An) */
uae_u32 REGPARAM2 op_5050_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 12; 
	uae_u32 src = srcreg;
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	if (dsta & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dsta, 1, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = get_word_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_word_000(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x1, newv, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (2/1) */
/* 2 0,0   */

/* ADDQ.W #<data>,(An)+ */
uae_u32 REGPARAM2 op_5058_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 12; 
	uae_u32 src = srcreg;
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	if (dsta & 1) {
		m68k_areg(regs, dstreg) += 2 + 0;
		m68k_incpci(2);
		exception3_read_access(opcode, dsta, 1, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = get_word_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, dstreg) += 2 + 0;
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) += 2;
	uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_word_000(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x1, newv, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (2/1) */
/* 2 0,0   */

/* ADDQ.W #<data>,-(An) */
uae_u32 REGPARAM2 op_5060_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 14; 
	uae_u32 src = srcreg;
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - 2;
	if (dsta & 1) {
		m68k_areg(regs, dstreg) = dsta;
		m68k_incpci(2);
		exception3_read_access(opcode, dsta, 1, 1);
		return 2 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = get_word_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, dstreg) = dsta;
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) = dsta;
	uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_word_000(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x1, newv, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 14 * CYCLE_UNIT / 2 + count_cycles;
}
/* 14 (2/1) */
/* 2 0,0   */

/* ADDQ.W #<data>,(d16,An) */
uae_u32 REGPARAM2 op_5068_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 16; 
	uae_u32 src = srcreg;
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dsta, 1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = get_word_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_word_000(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, newv, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 4 0,0   */

/* ADDQ.W #<data>,(d8,An,Xn) */
uae_u32 REGPARAM2 op_5070_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 18; 
	uae_u32 src = srcreg;
	uaecptr dsta;
	BusCyclePenalty += 2;
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dsta, 1, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = get_word_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_word_000(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, newv, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (3/1) */
/* 4 4,0   */

/* ADDQ.W #<data>,(xxx).W */
uae_u32 REGPARAM2 op_5078_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	OpcodeFamily = 11;
	CurrentInstrCycles = 16; 
	uae_u32 src = srcreg;
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, dsta, 1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = get_word_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_word_000(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, newv, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 4 0,0   */

/* ADDQ.W #<data>,(xxx).L */
uae_u32 REGPARAM2 op_5079_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	OpcodeFamily = 11;
	CurrentInstrCycles = 20; 
	uae_u32 src = srcreg;
	uaecptr dsta;
	dsta = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	dsta |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, dsta, 1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = get_word_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_word_000(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 0, 0x1, newv, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (4/1) */
/* 6 0,0   */

/* ADDQ.L #<data>,Dn */
uae_u32 REGPARAM2 op_5080_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 8;  
	uae_u32 src = srcreg;
	uae_s32 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u32)(~dst)) < ((uae_u32)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		uae_s16 bnewv = (uae_s16)dst + (uae_s16)src;
		int bflgs = ((uae_s16)(src)) < 0;
		int bflgo = ((uae_s16)(dst)) < 0;
		int bflgn = bnewv < 0;
		ccr_68000_long_move_ae_LZN(bnewv);
		SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
		SET_XFLG(GET_CFLG());
		SET_VFLG((bflgs ^ bflgn) & (bflgo ^ bflgn));
		dreg_68000_long_replace_low(dstreg, bnewv);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	m68k_dreg(regs, dstreg) = (newv);
	m68k_incpci(2);
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8 (1/0) */
/* 2 0,0   */

/* ADDAQ.L #<data>,An */
uae_u32 REGPARAM2 op_5088_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 12;
	CurrentInstrCycles = 8;  
	uae_u32 src = srcreg;
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = dst + src;
	regs.ir = regs.irc;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		areg_68000_long_replace_low(dstreg, newv);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	m68k_areg(regs, dstreg) = (newv);
	m68k_incpci(2);
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8 (1/0) */
/* 2 0,0   */

/* ADDQ.L #<data>,(An) */
uae_u32 REGPARAM2 op_5090_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 20; 
	uae_u32 src = srcreg;
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	if (dsta & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dsta, 2, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = get_word_000(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	dst |= get_word_000(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u32)(~dst)) < ((uae_u32)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		uae_s16 bnewv = (uae_s16)dst + (uae_s16)src;
		int bflgs = ((uae_s16)(src)) < 0;
		int bflgo = ((uae_s16)(dst)) < 0;
		int bflgn = bnewv < 0;
		ccr_68000_long_move_ae_LZN(bnewv);
		SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
		SET_XFLG(GET_CFLG());
		SET_VFLG((bflgs ^ bflgn) & (bflgo ^ bflgn));
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta + 2, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 2, 0x1, newv, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, newv >> 16); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x1, newv >> 16, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (3/2) */
/* 2 0,0   */

/* ADDQ.L #<data>,(An)+ */
uae_u32 REGPARAM2 op_5098_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 20; 
	uae_u32 src = srcreg;
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	if (dsta & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dsta, 2, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = get_word_000(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	dst |= get_word_000(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) += 4;
	uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u32)(~dst)) < ((uae_u32)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		uae_s16 bnewv = (uae_s16)dst + (uae_s16)src;
		int bflgs = ((uae_s16)(src)) < 0;
		int bflgo = ((uae_s16)(dst)) < 0;
		int bflgn = bnewv < 0;
		ccr_68000_long_move_ae_LZN(bnewv);
		SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
		SET_XFLG(GET_CFLG());
		SET_VFLG((bflgs ^ bflgn) & (bflgo ^ bflgn));
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta + 2, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 2, 0x1, newv, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, newv >> 16); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x1, newv >> 16, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (3/2) */
/* 2 0,0   */

/* ADDQ.L #<data>,-(An) */
uae_u32 REGPARAM2 op_50a0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 22; 
	uae_u32 src = srcreg;
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - 4;
	if (dsta & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dsta, 2, 1);
		return 2 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = get_word_000(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	dst |= get_word_000(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, dstreg) = dsta;
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) = dsta;
	uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u32)(~dst)) < ((uae_u32)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		uae_s16 bnewv = (uae_s16)dst + (uae_s16)src;
		int bflgs = ((uae_s16)(src)) < 0;
		int bflgo = ((uae_s16)(dst)) < 0;
		int bflgn = bnewv < 0;
		ccr_68000_long_move_ae_LZN(bnewv);
		SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
		SET_XFLG(GET_CFLG());
		SET_VFLG((bflgs ^ bflgn) & (bflgo ^ bflgn));
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta + 2, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 2, 0x1, newv, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, newv >> 16); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x1, newv >> 16, 1);
		return 22 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 22 * CYCLE_UNIT / 2 + count_cycles;
}
/* 22 (3/2) */
/* 2 0,0   */

/* ADDQ.L #<data>,(d16,An) */
uae_u32 REGPARAM2 op_50a8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 24; 
	uae_u32 src = srcreg;
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dsta, 2, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = get_word_000(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	dst |= get_word_000(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u32)(~dst)) < ((uae_u32)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		uae_s16 bnewv = (uae_s16)dst + (uae_s16)src;
		int bflgs = ((uae_s16)(src)) < 0;
		int bflgo = ((uae_s16)(dst)) < 0;
		int bflgn = bnewv < 0;
		ccr_68000_long_move_ae_LZN(bnewv);
		SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
		SET_XFLG(GET_CFLG());
		SET_VFLG((bflgs ^ bflgn) & (bflgo ^ bflgn));
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta + 2, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 2, 0x1, newv, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, newv >> 16); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, newv >> 16, 1);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 24 * CYCLE_UNIT / 2 + count_cycles;
}
/* 24 (4/2) */
/* 4 0,0   */

/* ADDQ.L #<data>,(d8,An,Xn) */
uae_u32 REGPARAM2 op_50b0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 26; 
	uae_u32 src = srcreg;
	uaecptr dsta;
	BusCyclePenalty += 2;
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dsta, 2, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = get_word_000(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	dst |= get_word_000(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u32)(~dst)) < ((uae_u32)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		uae_s16 bnewv = (uae_s16)dst + (uae_s16)src;
		int bflgs = ((uae_s16)(src)) < 0;
		int bflgo = ((uae_s16)(dst)) < 0;
		int bflgn = bnewv < 0;
		ccr_68000_long_move_ae_LZN(bnewv);
		SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
		SET_XFLG(GET_CFLG());
		SET_VFLG((bflgs ^ bflgn) & (bflgo ^ bflgn));
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta + 2, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 2, 0x1, newv, 1);
		return 22 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, newv >> 16); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, newv >> 16, 1);
		return 26 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 26 * CYCLE_UNIT / 2 + count_cycles;
}
/* 26 (4/2) */
/* 4 4,0   */

/* ADDQ.L #<data>,(xxx).W */
uae_u32 REGPARAM2 op_50b8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	OpcodeFamily = 11;
	CurrentInstrCycles = 24; 
	uae_u32 src = srcreg;
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, dsta, 2, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = get_word_000(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	dst |= get_word_000(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u32)(~dst)) < ((uae_u32)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		uae_s16 bnewv = (uae_s16)dst + (uae_s16)src;
		int bflgs = ((uae_s16)(src)) < 0;
		int bflgo = ((uae_s16)(dst)) < 0;
		int bflgn = bnewv < 0;
		ccr_68000_long_move_ae_LZN(bnewv);
		SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
		SET_XFLG(GET_CFLG());
		SET_VFLG((bflgs ^ bflgn) & (bflgo ^ bflgn));
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta + 2, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 2, 0x1, newv, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, newv >> 16); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, newv >> 16, 1);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 24 * CYCLE_UNIT / 2 + count_cycles;
}
/* 24 (4/2) */
/* 4 0,0   */

/* ADDQ.L #<data>,(xxx).L */
uae_u32 REGPARAM2 op_50b9_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	OpcodeFamily = 11;
	CurrentInstrCycles = 28; 
	uae_u32 src = srcreg;
	uaecptr dsta;
	dsta = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	dsta |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, dsta, 2, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = get_word_000(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	dst |= get_word_000(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u32)(~dst)) < ((uae_u32)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		uae_s16 bnewv = (uae_s16)dst + (uae_s16)src;
		int bflgs = ((uae_s16)(src)) < 0;
		int bflgo = ((uae_s16)(dst)) < 0;
		int bflgn = bnewv < 0;
		ccr_68000_long_move_ae_LZN(bnewv);
		SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
		SET_XFLG(GET_CFLG());
		SET_VFLG((bflgs ^ bflgn) & (bflgo ^ bflgn));
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta + 2, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 2, 0x1, newv, 1);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, newv >> 16); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 0, 0x1, newv >> 16, 1);
		return 28 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 28 * CYCLE_UNIT / 2 + count_cycles;
}
/* 28 (5/2) */
/* 6 0,0   */

/* Scc.B Dn (T) */
uae_u32 REGPARAM2 op_50c0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 4;  
	int val = cctrue(0) ? 0xff : 0x00;
	if (!val) {
		m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff);
	}
	regs.ir = regs.irc;
	if (!val)
	opcode = regs.ir;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if(!val && regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff);
	count_cycles += ((val ? 2 : 0)) * CYCLE_UNIT / 2;
	m68k_incpci(2);
	return 4 * CYCLE_UNIT / 2 + count_cycles;
}
/* 4+ (1/0) */
/* 2 0,0   */

/* DBcc.W Dn,#<data>.W (T) */
uae_u32 REGPARAM2 op_50c8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 58;
	CurrentInstrCycles = 10; 
	int pcadjust = -2;
	uae_s16 src = m68k_dreg(regs, srcreg);
	uae_s16 offs = regs.irc;
	int was_loop_mode = regs.loop_mode;
	regs.loop_mode = 0;
	uaecptr oldpc = m68k_getpci();
	if (!cctrue(0)) {
		m68k_incpci((uae_s32)offs + 2);
		if (offs & 1) {
			get_word_000_prefetch(-1);
			exception3_read_prefetch(opcode, m68k_getpci());
			return 2 * CYCLE_UNIT / 2 + count_cycles;
		}
		if(offs == -4 && !regs.t1 && loop_mode_table[regs.ird]) {
			if(!was_loop_mode) {
				uae_u16 irc = regs.irc;
				count_cycles += 4 * CYCLE_UNIT / 2;
				get_word_000_prefetch(0);
				if(hardware_bus_error) {
					int pcoffset = 0;
					exception2_fetch_opcode(opcode, 0, 0);
					return 2 * CYCLE_UNIT / 2 + count_cycles;
				}
				count_cycles += 4 * CYCLE_UNIT / 2;
				get_word_000_prefetch(2);
				if(hardware_bus_error) {
					int pcoffset = 0;
					exception2_fetch_opcode(opcode, 2, 0);
					return 2 * CYCLE_UNIT / 2 + count_cycles;
				}
				regs.irc = irc;
			} else {
				count_cycles += 2 * CYCLE_UNIT / 2;
			}
			regs.loop_mode = 1;
			src = m68k_dreg(regs, srcreg);
			m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
			if (src) {
				count_cycles += loop_mode_table[regs.ird](regs.ird);
				 // quick exit if condition false and count expired
				if (!cctrue(0) && (m68k_dreg(regs, srcreg) & 0xffff) == 0) {
					m68k_dreg(regs, srcreg) |= 0xffff;
					 // loop exit: add possible extra cycle(s)
					if(regs.loop_mode >> 16) {
						count_cycles += (regs.loop_mode >> 16) * CYCLE_UNIT / 2;
					}
					regs.loop_mode = 0;
					m68k_setpci_j(oldpc + 4);
					get_word_000_prefetch(0);
					if(hardware_bus_error) {
						int pcoffset = 0;
						m68k_setpci_j(oldpc + 2);
						exception2_fetch_opcode(opcode, 0, pcoffset);
						return 4 * CYCLE_UNIT / 2 + count_cycles;
					}
					regs.ir = regs.irc;
					opcode = regs.ir;
					get_word_000_prefetch(2);
					if(hardware_bus_error) {
						int pcoffset = 0;
						m68k_setpci_j(oldpc + 2);
						exception2_fetch_opcode(opcode, 2, pcoffset);
						return 8 * CYCLE_UNIT / 2 + count_cycles;
					}
					return 8 * CYCLE_UNIT / 2 + count_cycles;
				}
				 // loop continue: add possible extra cycle(s)
				if(regs.loop_mode & 0xfffe) {
					count_cycles += (regs.loop_mode & 0xfffe) * CYCLE_UNIT / 2;
				}
				m68k_setpci_j(oldpc);
				return 2 * CYCLE_UNIT / 2 + count_cycles;
			}
			regs.loop_mode = 0;
			m68k_setpci_j(oldpc + 4);
			get_word_000_prefetch(0);
			if(hardware_bus_error) {
				int pcoffset = 0;
				m68k_setpci_j(oldpc + 2);
				exception2_fetch_opcode(opcode, 0, pcoffset);
				return 16 * CYCLE_UNIT / 2 + count_cycles;
			}
			regs.ir = regs.irc;
			opcode = regs.ir;
			get_word_000_prefetch(2);
			if(hardware_bus_error) {
				int pcoffset = 0;
				m68k_setpci_j(oldpc + 2);
				exception2_fetch_opcode(opcode, 2, pcoffset);
				return 20 * CYCLE_UNIT / 2 + count_cycles;
			}
			return 8 * CYCLE_UNIT / 2 + count_cycles;
		}
		get_word_000_prefetch(0);
		if(hardware_bus_error) {
			int pcoffset = 0;
			pcoffset = oldpc - m68k_getpci() + 4;
			exception2_fetch_opcode(opcode, 0, pcoffset);
			return 6 * CYCLE_UNIT / 2 + count_cycles;
		}
		if (src) {
			m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
			regs.ir = regs.irc;
			opcode = regs.ir;
			get_word_000_prefetch(2);
			if(hardware_bus_error) {
				int pcoffset = 0;
				exception2_fetch_opcode(opcode, 2, 0);
				return 6 * CYCLE_UNIT / 2 + count_cycles;
			}
			return 10 * CYCLE_UNIT / 2 + count_cycles;
		}
		count_cycles += 6 * CYCLE_UNIT / 2;
		pcadjust = 0;
	}
	m68k_setpci_j(oldpc + 4);
	get_word_000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		pcoffset += pcadjust;
		exception2_fetch_opcode(opcode, 0, pcoffset);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	if (!cctrue(0)) {
		m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
	}
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 10 * CYCLE_UNIT / 2 + count_cycles;
}
/* 10 (2/0) */
/* 4 0,0 B */

/* Scc.B (An) (T) */
uae_u32 REGPARAM2 op_50d0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 10; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	regs.ir = regs.irc;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int val = cctrue(0) ? 0xff : 0x00;
	put_byte_000(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 10 * CYCLE_UNIT / 2 + count_cycles;
}
/* 10 (1/1) */
/* 2 0,0   */

/* Scc.B (An)+ (T) */
uae_u32 REGPARAM2 op_50d8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
	regs.ir = regs.irc;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int val = cctrue(0) ? 0xff : 0x00;
	put_byte_000(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (1/1) */
/* 2 0,0   */

/* Scc.B -(An) (T) */
uae_u32 REGPARAM2 op_50e0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
	m68k_areg(regs, srcreg) = srca;
	regs.ir = regs.irc;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int val = cctrue(0) ? 0xff : 0x00;
	put_byte_000(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (1/1) */
/* 2 0,0   */

/* Scc.B (d16,An) (T) */
uae_u32 REGPARAM2 op_50e8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int val = cctrue(0) ? 0xff : 0x00;
	put_byte_000(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (2/1) */
/* 4 0,0   */

/* Scc.B (d8,An,Xn) (T) */
uae_u32 REGPARAM2 op_50f0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int val = cctrue(0) ? 0xff : 0x00;
	put_byte_000(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (2/1) */
/* 4 4,0   */

/* Scc.B (xxx).W (T) */
uae_u32 REGPARAM2 op_50f8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 59;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int val = cctrue(0) ? 0xff : 0x00;
	put_byte_000(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (2/1) */
/* 4 0,0   */

/* Scc.B (xxx).L (T) */
uae_u32 REGPARAM2 op_50f9_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 59;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	srca |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int val = cctrue(0) ? 0xff : 0x00;
	put_byte_000(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 6 0,0   */

/* SUBQ.B #<data>,Dn */
uae_u32 REGPARAM2 op_5100_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 4;  
	uae_u32 src = srcreg;
	uae_s8 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 4 * CYCLE_UNIT / 2 + count_cycles;
}
/* 4 (1/0) */
/* 2 0,0   */

/* SUBQ.B #<data>,(An) */
uae_u32 REGPARAM2 op_5110_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 12; 
	uae_u32 src = srcreg;
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_byte_000(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x0, newv, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (2/1) */
/* 2 0,0   */

/* SUBQ.B #<data>,(An)+ */
uae_u32 REGPARAM2 op_5118_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 12; 
	uae_u32 src = srcreg;
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
	uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_byte_000(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x0, newv, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (2/1) */
/* 2 0,0   */

/* SUBQ.B #<data>,-(An) */
uae_u32 REGPARAM2 op_5120_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 14; 
	uae_u32 src = srcreg;
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, dstreg) = dsta;
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) = dsta;
	uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_byte_000(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x0, newv, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 14 * CYCLE_UNIT / 2 + count_cycles;
}
/* 14 (2/1) */
/* 2 0,0   */

/* SUBQ.B #<data>,(d16,An) */
uae_u32 REGPARAM2 op_5128_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 16; 
	uae_u32 src = srcreg;
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_byte_000(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x0, newv, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 4 0,0   */

/* SUBQ.B #<data>,(d8,An,Xn) */
uae_u32 REGPARAM2 op_5130_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 18; 
	uae_u32 src = srcreg;
	uaecptr dsta;
	BusCyclePenalty += 2;
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_byte_000(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x0, newv, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (3/1) */
/* 4 4,0   */

/* SUBQ.B #<data>,(xxx).W */
uae_u32 REGPARAM2 op_5138_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	OpcodeFamily = 7;
	CurrentInstrCycles = 16; 
	uae_u32 src = srcreg;
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_byte_000(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x0, newv, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 4 0,0   */

/* SUBQ.B #<data>,(xxx).L */
uae_u32 REGPARAM2 op_5139_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	OpcodeFamily = 7;
	CurrentInstrCycles = 20; 
	uae_u32 src = srcreg;
	uaecptr dsta;
	dsta = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	dsta |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_byte_000(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 0, 0x0, newv, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (4/1) */
/* 6 0,0   */

/* SUBQ.W #<data>,Dn */
uae_u32 REGPARAM2 op_5140_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 4;  
	uae_u32 src = srcreg;
	uae_s16 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 4 * CYCLE_UNIT / 2 + count_cycles;
}
/* 4 (1/0) */
/* 2 0,0   */

/* SUBAQ.W #<data>,An */
uae_u32 REGPARAM2 op_5148_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 8;
	CurrentInstrCycles = 8;  
	uae_u32 src = srcreg;
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = dst - src;
	regs.ir = regs.irc;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		areg_68000_long_replace_low(dstreg, newv);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) = (newv);
	m68k_incpci(2);
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8 (1/0) */
/* 2 0,0   */

/* SUBQ.W #<data>,(An) */
uae_u32 REGPARAM2 op_5150_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 12; 
	uae_u32 src = srcreg;
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	if (dsta & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dsta, 1, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = get_word_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_word_000(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x1, newv, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (2/1) */
/* 2 0,0   */

/* SUBQ.W #<data>,(An)+ */
uae_u32 REGPARAM2 op_5158_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 12; 
	uae_u32 src = srcreg;
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	if (dsta & 1) {
		m68k_areg(regs, dstreg) += 2 + 0;
		m68k_incpci(2);
		exception3_read_access(opcode, dsta, 1, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = get_word_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, dstreg) += 2 + 0;
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) += 2;
	uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_word_000(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x1, newv, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (2/1) */
/* 2 0,0   */

/* SUBQ.W #<data>,-(An) */
uae_u32 REGPARAM2 op_5160_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 14; 
	uae_u32 src = srcreg;
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - 2;
	if (dsta & 1) {
		m68k_areg(regs, dstreg) = dsta;
		m68k_incpci(2);
		exception3_read_access(opcode, dsta, 1, 1);
		return 2 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = get_word_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, dstreg) = dsta;
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) = dsta;
	uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_word_000(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x1, newv, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 14 * CYCLE_UNIT / 2 + count_cycles;
}
/* 14 (2/1) */
/* 2 0,0   */

/* SUBQ.W #<data>,(d16,An) */
uae_u32 REGPARAM2 op_5168_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 16; 
	uae_u32 src = srcreg;
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dsta, 1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = get_word_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_word_000(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, newv, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 4 0,0   */

/* SUBQ.W #<data>,(d8,An,Xn) */
uae_u32 REGPARAM2 op_5170_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 18; 
	uae_u32 src = srcreg;
	uaecptr dsta;
	BusCyclePenalty += 2;
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dsta, 1, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = get_word_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_word_000(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, newv, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (3/1) */
/* 4 4,0   */

/* SUBQ.W #<data>,(xxx).W */
uae_u32 REGPARAM2 op_5178_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	OpcodeFamily = 7;
	CurrentInstrCycles = 16; 
	uae_u32 src = srcreg;
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, dsta, 1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = get_word_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_word_000(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, newv, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 4 0,0   */

/* SUBQ.W #<data>,(xxx).L */
uae_u32 REGPARAM2 op_5179_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	OpcodeFamily = 7;
	CurrentInstrCycles = 20; 
	uae_u32 src = srcreg;
	uaecptr dsta;
	dsta = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	dsta |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, dsta, 1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = get_word_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_word_000(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 0, 0x1, newv, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (4/1) */
/* 6 0,0   */

/* SUBQ.L #<data>,Dn */
uae_u32 REGPARAM2 op_5180_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 8;  
	uae_u32 src = srcreg;
	uae_s32 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		uae_s16 bnewv = (uae_s16)dst - (uae_s16)src;
		int bflgs = ((uae_s16)(src)) < 0;
		int bflgo = ((uae_s16)(dst)) < 0;
		int bflgn = bnewv < 0;
		ccr_68000_long_move_ae_LZN(bnewv);
		SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
		SET_XFLG(GET_CFLG());
		SET_VFLG((bflgs ^ bflgo) & (bflgn ^ bflgo));
		dreg_68000_long_replace_low(dstreg, bnewv);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	m68k_dreg(regs, dstreg) = (newv);
	m68k_incpci(2);
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8 (1/0) */
/* 2 0,0   */

/* SUBAQ.L #<data>,An */
uae_u32 REGPARAM2 op_5188_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 8;
	CurrentInstrCycles = 8;  
	uae_u32 src = srcreg;
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = dst - src;
	regs.ir = regs.irc;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		areg_68000_long_replace_low(dstreg, newv);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) = (newv);
	m68k_incpci(2);
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8 (1/0) */
/* 2 0,0   */

/* SUBQ.L #<data>,(An) */
uae_u32 REGPARAM2 op_5190_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 20; 
	uae_u32 src = srcreg;
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	if (dsta & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dsta, 2, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = get_word_000(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	dst |= get_word_000(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		uae_s16 bnewv = (uae_s16)dst - (uae_s16)src;
		int bflgs = ((uae_s16)(src)) < 0;
		int bflgo = ((uae_s16)(dst)) < 0;
		int bflgn = bnewv < 0;
		ccr_68000_long_move_ae_LZN(bnewv);
		SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
		SET_XFLG(GET_CFLG());
		SET_VFLG((bflgs ^ bflgo) & (bflgn ^ bflgo));
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta + 2, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 2, 0x1, newv, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, newv >> 16); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x1, newv >> 16, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (3/2) */
/* 2 0,0   */

/* SUBQ.L #<data>,(An)+ */
uae_u32 REGPARAM2 op_5198_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 20; 
	uae_u32 src = srcreg;
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	if (dsta & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dsta, 2, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = get_word_000(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	dst |= get_word_000(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) += 4;
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		uae_s16 bnewv = (uae_s16)dst - (uae_s16)src;
		int bflgs = ((uae_s16)(src)) < 0;
		int bflgo = ((uae_s16)(dst)) < 0;
		int bflgn = bnewv < 0;
		ccr_68000_long_move_ae_LZN(bnewv);
		SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
		SET_XFLG(GET_CFLG());
		SET_VFLG((bflgs ^ bflgo) & (bflgn ^ bflgo));
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta + 2, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 2, 0x1, newv, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, newv >> 16); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x1, newv >> 16, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (3/2) */
/* 2 0,0   */

/* SUBQ.L #<data>,-(An) */
uae_u32 REGPARAM2 op_51a0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 22; 
	uae_u32 src = srcreg;
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - 4;
	if (dsta & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dsta, 2, 1);
		return 2 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = get_word_000(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	dst |= get_word_000(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, dstreg) = dsta;
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) = dsta;
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		uae_s16 bnewv = (uae_s16)dst - (uae_s16)src;
		int bflgs = ((uae_s16)(src)) < 0;
		int bflgo = ((uae_s16)(dst)) < 0;
		int bflgn = bnewv < 0;
		ccr_68000_long_move_ae_LZN(bnewv);
		SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
		SET_XFLG(GET_CFLG());
		SET_VFLG((bflgs ^ bflgo) & (bflgn ^ bflgo));
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta + 2, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 2, 0x1, newv, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, newv >> 16); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x1, newv >> 16, 1);
		return 22 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 22 * CYCLE_UNIT / 2 + count_cycles;
}
/* 22 (3/2) */
/* 2 0,0   */

/* SUBQ.L #<data>,(d16,An) */
uae_u32 REGPARAM2 op_51a8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 24; 
	uae_u32 src = srcreg;
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dsta, 2, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = get_word_000(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	dst |= get_word_000(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		uae_s16 bnewv = (uae_s16)dst - (uae_s16)src;
		int bflgs = ((uae_s16)(src)) < 0;
		int bflgo = ((uae_s16)(dst)) < 0;
		int bflgn = bnewv < 0;
		ccr_68000_long_move_ae_LZN(bnewv);
		SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
		SET_XFLG(GET_CFLG());
		SET_VFLG((bflgs ^ bflgo) & (bflgn ^ bflgo));
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta + 2, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 2, 0x1, newv, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, newv >> 16); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, newv >> 16, 1);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 24 * CYCLE_UNIT / 2 + count_cycles;
}
/* 24 (4/2) */
/* 4 0,0   */

/* SUBQ.L #<data>,(d8,An,Xn) */
uae_u32 REGPARAM2 op_51b0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 26; 
	uae_u32 src = srcreg;
	uaecptr dsta;
	BusCyclePenalty += 2;
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dsta, 2, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = get_word_000(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	dst |= get_word_000(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		uae_s16 bnewv = (uae_s16)dst - (uae_s16)src;
		int bflgs = ((uae_s16)(src)) < 0;
		int bflgo = ((uae_s16)(dst)) < 0;
		int bflgn = bnewv < 0;
		ccr_68000_long_move_ae_LZN(bnewv);
		SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
		SET_XFLG(GET_CFLG());
		SET_VFLG((bflgs ^ bflgo) & (bflgn ^ bflgo));
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta + 2, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 2, 0x1, newv, 1);
		return 22 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, newv >> 16); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, newv >> 16, 1);
		return 26 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 26 * CYCLE_UNIT / 2 + count_cycles;
}
/* 26 (4/2) */
/* 4 4,0   */

/* SUBQ.L #<data>,(xxx).W */
uae_u32 REGPARAM2 op_51b8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	OpcodeFamily = 7;
	CurrentInstrCycles = 24; 
	uae_u32 src = srcreg;
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, dsta, 2, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = get_word_000(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	dst |= get_word_000(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		uae_s16 bnewv = (uae_s16)dst - (uae_s16)src;
		int bflgs = ((uae_s16)(src)) < 0;
		int bflgo = ((uae_s16)(dst)) < 0;
		int bflgn = bnewv < 0;
		ccr_68000_long_move_ae_LZN(bnewv);
		SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
		SET_XFLG(GET_CFLG());
		SET_VFLG((bflgs ^ bflgo) & (bflgn ^ bflgo));
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta + 2, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 2, 0x1, newv, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, newv >> 16); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, newv >> 16, 1);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 24 * CYCLE_UNIT / 2 + count_cycles;
}
/* 24 (4/2) */
/* 4 0,0   */

/* SUBQ.L #<data>,(xxx).L */
uae_u32 REGPARAM2 op_51b9_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	OpcodeFamily = 7;
	CurrentInstrCycles = 28; 
	uae_u32 src = srcreg;
	uaecptr dsta;
	dsta = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	dsta |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, dsta, 2, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = get_word_000(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	dst |= get_word_000(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		uae_s16 bnewv = (uae_s16)dst - (uae_s16)src;
		int bflgs = ((uae_s16)(src)) < 0;
		int bflgo = ((uae_s16)(dst)) < 0;
		int bflgn = bnewv < 0;
		ccr_68000_long_move_ae_LZN(bnewv);
		SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
		SET_XFLG(GET_CFLG());
		SET_VFLG((bflgs ^ bflgo) & (bflgn ^ bflgo));
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta + 2, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 2, 0x1, newv, 1);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, newv >> 16); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 0, 0x1, newv >> 16, 1);
		return 28 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 28 * CYCLE_UNIT / 2 + count_cycles;
}
/* 28 (5/2) */
/* 6 0,0   */

/* Scc.B Dn (F) */
uae_u32 REGPARAM2 op_51c0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 4;  
	int val = cctrue(1) ? 0xff : 0x00;
	if (!val) {
		m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff);
	}
	regs.ir = regs.irc;
	if (!val)
	opcode = regs.ir;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if(!val && regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff);
	count_cycles += ((val ? 2 : 0)) * CYCLE_UNIT / 2;
	m68k_incpci(2);
	return 4 * CYCLE_UNIT / 2 + count_cycles;
}
/* 4+ (1/0) */
/* 2 0,0   */

/* DBcc.W Dn,#<data>.W (F) */
uae_u32 REGPARAM2 op_51c8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 58;
	CurrentInstrCycles = 10; 
	int pcadjust = -2;
	uae_s16 src = m68k_dreg(regs, srcreg);
	uae_s16 offs = regs.irc;
	int was_loop_mode = regs.loop_mode;
	regs.loop_mode = 0;
	uaecptr oldpc = m68k_getpci();
	if (!cctrue(1)) {
		m68k_incpci((uae_s32)offs + 2);
		if (offs & 1) {
			get_word_000_prefetch(-1);
			exception3_read_prefetch(opcode, m68k_getpci());
			return 2 * CYCLE_UNIT / 2 + count_cycles;
		}
		if(offs == -4 && !regs.t1 && loop_mode_table[regs.ird]) {
			if(!was_loop_mode) {
				uae_u16 irc = regs.irc;
				count_cycles += 4 * CYCLE_UNIT / 2;
				get_word_000_prefetch(0);
				if(hardware_bus_error) {
					int pcoffset = 0;
					exception2_fetch_opcode(opcode, 0, 0);
					return 2 * CYCLE_UNIT / 2 + count_cycles;
				}
				count_cycles += 4 * CYCLE_UNIT / 2;
				get_word_000_prefetch(2);
				if(hardware_bus_error) {
					int pcoffset = 0;
					exception2_fetch_opcode(opcode, 2, 0);
					return 2 * CYCLE_UNIT / 2 + count_cycles;
				}
				regs.irc = irc;
			} else {
				count_cycles += 2 * CYCLE_UNIT / 2;
			}
			regs.loop_mode = 1;
			src = m68k_dreg(regs, srcreg);
			m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
			if (src) {
				count_cycles += loop_mode_table[regs.ird](regs.ird);
				 // quick exit if condition false and count expired
				if (!cctrue(1) && (m68k_dreg(regs, srcreg) & 0xffff) == 0) {
					m68k_dreg(regs, srcreg) |= 0xffff;
					 // loop exit: add possible extra cycle(s)
					if(regs.loop_mode >> 16) {
						count_cycles += (regs.loop_mode >> 16) * CYCLE_UNIT / 2;
					}
					regs.loop_mode = 0;
					m68k_setpci_j(oldpc + 4);
					get_word_000_prefetch(0);
					if(hardware_bus_error) {
						int pcoffset = 0;
						m68k_setpci_j(oldpc + 2);
						exception2_fetch_opcode(opcode, 0, pcoffset);
						return 4 * CYCLE_UNIT / 2 + count_cycles;
					}
					regs.ir = regs.irc;
					opcode = regs.ir;
					get_word_000_prefetch(2);
					if(hardware_bus_error) {
						int pcoffset = 0;
						m68k_setpci_j(oldpc + 2);
						exception2_fetch_opcode(opcode, 2, pcoffset);
						return 8 * CYCLE_UNIT / 2 + count_cycles;
					}
					return 8 * CYCLE_UNIT / 2 + count_cycles;
				}
				 // loop continue: add possible extra cycle(s)
				if(regs.loop_mode & 0xfffe) {
					count_cycles += (regs.loop_mode & 0xfffe) * CYCLE_UNIT / 2;
				}
				m68k_setpci_j(oldpc);
				return 2 * CYCLE_UNIT / 2 + count_cycles;
			}
			regs.loop_mode = 0;
			m68k_setpci_j(oldpc + 4);
			get_word_000_prefetch(0);
			if(hardware_bus_error) {
				int pcoffset = 0;
				m68k_setpci_j(oldpc + 2);
				exception2_fetch_opcode(opcode, 0, pcoffset);
				return 16 * CYCLE_UNIT / 2 + count_cycles;
			}
			regs.ir = regs.irc;
			opcode = regs.ir;
			get_word_000_prefetch(2);
			if(hardware_bus_error) {
				int pcoffset = 0;
				m68k_setpci_j(oldpc + 2);
				exception2_fetch_opcode(opcode, 2, pcoffset);
				return 20 * CYCLE_UNIT / 2 + count_cycles;
			}
			return 8 * CYCLE_UNIT / 2 + count_cycles;
		}
		get_word_000_prefetch(0);
		if(hardware_bus_error) {
			int pcoffset = 0;
			pcoffset = oldpc - m68k_getpci() + 4;
			exception2_fetch_opcode(opcode, 0, pcoffset);
			return 6 * CYCLE_UNIT / 2 + count_cycles;
		}
		if (src) {
			m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
			regs.ir = regs.irc;
			opcode = regs.ir;
			get_word_000_prefetch(2);
			if(hardware_bus_error) {
				int pcoffset = 0;
				exception2_fetch_opcode(opcode, 2, 0);
				return 6 * CYCLE_UNIT / 2 + count_cycles;
			}
			return 10 * CYCLE_UNIT / 2 + count_cycles;
		}
		count_cycles += 6 * CYCLE_UNIT / 2;
		pcadjust = 0;
	}
	m68k_setpci_j(oldpc + 4);
	get_word_000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		pcoffset += pcadjust;
		exception2_fetch_opcode(opcode, 0, pcoffset);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	if (!cctrue(1)) {
		m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
	}
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 10 * CYCLE_UNIT / 2 + count_cycles;
}
/* 10 (2/0) */
/* 4 0,0 B */

/* Scc.B (An) (F) */
uae_u32 REGPARAM2 op_51d0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 10; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	regs.ir = regs.irc;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int val = cctrue(1) ? 0xff : 0x00;
	put_byte_000(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 10 * CYCLE_UNIT / 2 + count_cycles;
}
/* 10 (1/1) */
/* 2 0,0   */

/* Scc.B (An)+ (F) */
uae_u32 REGPARAM2 op_51d8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
	regs.ir = regs.irc;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int val = cctrue(1) ? 0xff : 0x00;
	put_byte_000(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (1/1) */
/* 2 0,0   */

/* Scc.B -(An) (F) */
uae_u32 REGPARAM2 op_51e0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
	m68k_areg(regs, srcreg) = srca;
	regs.ir = regs.irc;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int val = cctrue(1) ? 0xff : 0x00;
	put_byte_000(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (1/1) */
/* 2 0,0   */

/* Scc.B (d16,An) (F) */
uae_u32 REGPARAM2 op_51e8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int val = cctrue(1) ? 0xff : 0x00;
	put_byte_000(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (2/1) */
/* 4 0,0   */

/* Scc.B (d8,An,Xn) (F) */
uae_u32 REGPARAM2 op_51f0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int val = cctrue(1) ? 0xff : 0x00;
	put_byte_000(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (2/1) */
/* 4 4,0   */

/* Scc.B (xxx).W (F) */
uae_u32 REGPARAM2 op_51f8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 59;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int val = cctrue(1) ? 0xff : 0x00;
	put_byte_000(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (2/1) */
/* 4 0,0   */

/* Scc.B (xxx).L (F) */
uae_u32 REGPARAM2 op_51f9_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 59;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	srca |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int val = cctrue(1) ? 0xff : 0x00;
	put_byte_000(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 6 0,0   */

/* Scc.B Dn (HI) */
uae_u32 REGPARAM2 op_52c0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 4;  
	int val = cctrue(2) ? 0xff : 0x00;
	if (!val) {
		m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff);
	}
	regs.ir = regs.irc;
	if (!val)
	opcode = regs.ir;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if(!val && regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff);
	count_cycles += ((val ? 2 : 0)) * CYCLE_UNIT / 2;
	m68k_incpci(2);
	return 4 * CYCLE_UNIT / 2 + count_cycles;
}
/* 4+ (1/0) */
/* 2 0,0   */

/* DBcc.W Dn,#<data>.W (HI) */
uae_u32 REGPARAM2 op_52c8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 58;
	CurrentInstrCycles = 10; 
	int pcadjust = -2;
	uae_s16 src = m68k_dreg(regs, srcreg);
	uae_s16 offs = regs.irc;
	int was_loop_mode = regs.loop_mode;
	regs.loop_mode = 0;
	uaecptr oldpc = m68k_getpci();
	if (!cctrue(2)) {
		m68k_incpci((uae_s32)offs + 2);
		if (offs & 1) {
			get_word_000_prefetch(-1);
			exception3_read_prefetch(opcode, m68k_getpci());
			return 2 * CYCLE_UNIT / 2 + count_cycles;
		}
		if(offs == -4 && !regs.t1 && loop_mode_table[regs.ird]) {
			if(!was_loop_mode) {
				uae_u16 irc = regs.irc;
				count_cycles += 4 * CYCLE_UNIT / 2;
				get_word_000_prefetch(0);
				if(hardware_bus_error) {
					int pcoffset = 0;
					exception2_fetch_opcode(opcode, 0, 0);
					return 2 * CYCLE_UNIT / 2 + count_cycles;
				}
				count_cycles += 4 * CYCLE_UNIT / 2;
				get_word_000_prefetch(2);
				if(hardware_bus_error) {
					int pcoffset = 0;
					exception2_fetch_opcode(opcode, 2, 0);
					return 2 * CYCLE_UNIT / 2 + count_cycles;
				}
				regs.irc = irc;
			} else {
				count_cycles += 2 * CYCLE_UNIT / 2;
			}
			regs.loop_mode = 1;
			src = m68k_dreg(regs, srcreg);
			m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
			if (src) {
				count_cycles += loop_mode_table[regs.ird](regs.ird);
				 // quick exit if condition false and count expired
				if (!cctrue(2) && (m68k_dreg(regs, srcreg) & 0xffff) == 0) {
					m68k_dreg(regs, srcreg) |= 0xffff;
					 // loop exit: add possible extra cycle(s)
					if(regs.loop_mode >> 16) {
						count_cycles += (regs.loop_mode >> 16) * CYCLE_UNIT / 2;
					}
					regs.loop_mode = 0;
					m68k_setpci_j(oldpc + 4);
					get_word_000_prefetch(0);
					if(hardware_bus_error) {
						int pcoffset = 0;
						m68k_setpci_j(oldpc + 2);
						exception2_fetch_opcode(opcode, 0, pcoffset);
						return 4 * CYCLE_UNIT / 2 + count_cycles;
					}
					regs.ir = regs.irc;
					opcode = regs.ir;
					get_word_000_prefetch(2);
					if(hardware_bus_error) {
						int pcoffset = 0;
						m68k_setpci_j(oldpc + 2);
						exception2_fetch_opcode(opcode, 2, pcoffset);
						return 8 * CYCLE_UNIT / 2 + count_cycles;
					}
					return 8 * CYCLE_UNIT / 2 + count_cycles;
				}
				 // loop continue: add possible extra cycle(s)
				if(regs.loop_mode & 0xfffe) {
					count_cycles += (regs.loop_mode & 0xfffe) * CYCLE_UNIT / 2;
				}
				m68k_setpci_j(oldpc);
				return 2 * CYCLE_UNIT / 2 + count_cycles;
			}
			regs.loop_mode = 0;
			m68k_setpci_j(oldpc + 4);
			get_word_000_prefetch(0);
			if(hardware_bus_error) {
				int pcoffset = 0;
				m68k_setpci_j(oldpc + 2);
				exception2_fetch_opcode(opcode, 0, pcoffset);
				return 16 * CYCLE_UNIT / 2 + count_cycles;
			}
			regs.ir = regs.irc;
			opcode = regs.ir;
			get_word_000_prefetch(2);
			if(hardware_bus_error) {
				int pcoffset = 0;
				m68k_setpci_j(oldpc + 2);
				exception2_fetch_opcode(opcode, 2, pcoffset);
				return 20 * CYCLE_UNIT / 2 + count_cycles;
			}
			return 8 * CYCLE_UNIT / 2 + count_cycles;
		}
		get_word_000_prefetch(0);
		if(hardware_bus_error) {
			int pcoffset = 0;
			pcoffset = oldpc - m68k_getpci() + 4;
			exception2_fetch_opcode(opcode, 0, pcoffset);
			return 6 * CYCLE_UNIT / 2 + count_cycles;
		}
		if (src) {
			m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
			regs.ir = regs.irc;
			opcode = regs.ir;
			get_word_000_prefetch(2);
			if(hardware_bus_error) {
				int pcoffset = 0;
				exception2_fetch_opcode(opcode, 2, 0);
				return 6 * CYCLE_UNIT / 2 + count_cycles;
			}
			return 10 * CYCLE_UNIT / 2 + count_cycles;
		}
		count_cycles += 6 * CYCLE_UNIT / 2;
		pcadjust = 0;
	}
	m68k_setpci_j(oldpc + 4);
	get_word_000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		pcoffset += pcadjust;
		exception2_fetch_opcode(opcode, 0, pcoffset);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	if (!cctrue(2)) {
		m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
	}
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 10 * CYCLE_UNIT / 2 + count_cycles;
}
/* 10 (2/0) */
/* 4 0,0 B */

/* Scc.B (An) (HI) */
uae_u32 REGPARAM2 op_52d0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 10; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	regs.ir = regs.irc;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int val = cctrue(2) ? 0xff : 0x00;
	put_byte_000(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 10 * CYCLE_UNIT / 2 + count_cycles;
}
/* 10 (1/1) */
/* 2 0,0   */

/* Scc.B (An)+ (HI) */
uae_u32 REGPARAM2 op_52d8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
	regs.ir = regs.irc;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int val = cctrue(2) ? 0xff : 0x00;
	put_byte_000(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (1/1) */
/* 2 0,0   */

/* Scc.B -(An) (HI) */
uae_u32 REGPARAM2 op_52e0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
	m68k_areg(regs, srcreg) = srca;
	regs.ir = regs.irc;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int val = cctrue(2) ? 0xff : 0x00;
	put_byte_000(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (1/1) */
/* 2 0,0   */

/* Scc.B (d16,An) (HI) */
uae_u32 REGPARAM2 op_52e8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int val = cctrue(2) ? 0xff : 0x00;
	put_byte_000(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (2/1) */
/* 4 0,0   */

/* Scc.B (d8,An,Xn) (HI) */
uae_u32 REGPARAM2 op_52f0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int val = cctrue(2) ? 0xff : 0x00;
	put_byte_000(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (2/1) */
/* 4 4,0   */

/* Scc.B (xxx).W (HI) */
uae_u32 REGPARAM2 op_52f8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 59;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int val = cctrue(2) ? 0xff : 0x00;
	put_byte_000(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (2/1) */
/* 4 0,0   */

/* Scc.B (xxx).L (HI) */
uae_u32 REGPARAM2 op_52f9_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 59;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	srca |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int val = cctrue(2) ? 0xff : 0x00;
	put_byte_000(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 6 0,0   */

/* Scc.B Dn (LS) */
uae_u32 REGPARAM2 op_53c0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 4;  
	int val = cctrue(3) ? 0xff : 0x00;
	if (!val) {
		m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff);
	}
	regs.ir = regs.irc;
	if (!val)
	opcode = regs.ir;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if(!val && regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff);
	count_cycles += ((val ? 2 : 0)) * CYCLE_UNIT / 2;
	m68k_incpci(2);
	return 4 * CYCLE_UNIT / 2 + count_cycles;
}
/* 4+ (1/0) */
/* 2 0,0   */

/* DBcc.W Dn,#<data>.W (LS) */
uae_u32 REGPARAM2 op_53c8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 58;
	CurrentInstrCycles = 10; 
	int pcadjust = -2;
	uae_s16 src = m68k_dreg(regs, srcreg);
	uae_s16 offs = regs.irc;
	int was_loop_mode = regs.loop_mode;
	regs.loop_mode = 0;
	uaecptr oldpc = m68k_getpci();
	if (!cctrue(3)) {
		m68k_incpci((uae_s32)offs + 2);
		if (offs & 1) {
			get_word_000_prefetch(-1);
			exception3_read_prefetch(opcode, m68k_getpci());
			return 2 * CYCLE_UNIT / 2 + count_cycles;
		}
		if(offs == -4 && !regs.t1 && loop_mode_table[regs.ird]) {
			if(!was_loop_mode) {
				uae_u16 irc = regs.irc;
				count_cycles += 4 * CYCLE_UNIT / 2;
				get_word_000_prefetch(0);
				if(hardware_bus_error) {
					int pcoffset = 0;
					exception2_fetch_opcode(opcode, 0, 0);
					return 2 * CYCLE_UNIT / 2 + count_cycles;
				}
				count_cycles += 4 * CYCLE_UNIT / 2;
				get_word_000_prefetch(2);
				if(hardware_bus_error) {
					int pcoffset = 0;
					exception2_fetch_opcode(opcode, 2, 0);
					return 2 * CYCLE_UNIT / 2 + count_cycles;
				}
				regs.irc = irc;
			} else {
				count_cycles += 2 * CYCLE_UNIT / 2;
			}
			regs.loop_mode = 1;
			src = m68k_dreg(regs, srcreg);
			m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
			if (src) {
				count_cycles += loop_mode_table[regs.ird](regs.ird);
				 // quick exit if condition false and count expired
				if (!cctrue(3) && (m68k_dreg(regs, srcreg) & 0xffff) == 0) {
					m68k_dreg(regs, srcreg) |= 0xffff;
					 // loop exit: add possible extra cycle(s)
					if(regs.loop_mode >> 16) {
						count_cycles += (regs.loop_mode >> 16) * CYCLE_UNIT / 2;
					}
					regs.loop_mode = 0;
					m68k_setpci_j(oldpc + 4);
					get_word_000_prefetch(0);
					if(hardware_bus_error) {
						int pcoffset = 0;
						m68k_setpci_j(oldpc + 2);
						exception2_fetch_opcode(opcode, 0, pcoffset);
						return 4 * CYCLE_UNIT / 2 + count_cycles;
					}
					regs.ir = regs.irc;
					opcode = regs.ir;
					get_word_000_prefetch(2);
					if(hardware_bus_error) {
						int pcoffset = 0;
						m68k_setpci_j(oldpc + 2);
						exception2_fetch_opcode(opcode, 2, pcoffset);
						return 8 * CYCLE_UNIT / 2 + count_cycles;
					}
					return 8 * CYCLE_UNIT / 2 + count_cycles;
				}
				 // loop continue: add possible extra cycle(s)
				if(regs.loop_mode & 0xfffe) {
					count_cycles += (regs.loop_mode & 0xfffe) * CYCLE_UNIT / 2;
				}
				m68k_setpci_j(oldpc);
				return 2 * CYCLE_UNIT / 2 + count_cycles;
			}
			regs.loop_mode = 0;
			m68k_setpci_j(oldpc + 4);
			get_word_000_prefetch(0);
			if(hardware_bus_error) {
				int pcoffset = 0;
				m68k_setpci_j(oldpc + 2);
				exception2_fetch_opcode(opcode, 0, pcoffset);
				return 16 * CYCLE_UNIT / 2 + count_cycles;
			}
			regs.ir = regs.irc;
			opcode = regs.ir;
			get_word_000_prefetch(2);
			if(hardware_bus_error) {
				int pcoffset = 0;
				m68k_setpci_j(oldpc + 2);
				exception2_fetch_opcode(opcode, 2, pcoffset);
				return 20 * CYCLE_UNIT / 2 + count_cycles;
			}
			return 8 * CYCLE_UNIT / 2 + count_cycles;
		}
		get_word_000_prefetch(0);
		if(hardware_bus_error) {
			int pcoffset = 0;
			pcoffset = oldpc - m68k_getpci() + 4;
			exception2_fetch_opcode(opcode, 0, pcoffset);
			return 6 * CYCLE_UNIT / 2 + count_cycles;
		}
		if (src) {
			m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
			regs.ir = regs.irc;
			opcode = regs.ir;
			get_word_000_prefetch(2);
			if(hardware_bus_error) {
				int pcoffset = 0;
				exception2_fetch_opcode(opcode, 2, 0);
				return 6 * CYCLE_UNIT / 2 + count_cycles;
			}
			return 10 * CYCLE_UNIT / 2 + count_cycles;
		}
		count_cycles += 6 * CYCLE_UNIT / 2;
		pcadjust = 0;
	}
	m68k_setpci_j(oldpc + 4);
	get_word_000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		pcoffset += pcadjust;
		exception2_fetch_opcode(opcode, 0, pcoffset);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	if (!cctrue(3)) {
		m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
	}
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 10 * CYCLE_UNIT / 2 + count_cycles;
}
/* 10 (2/0) */
/* 4 0,0 B */

/* Scc.B (An) (LS) */
uae_u32 REGPARAM2 op_53d0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 10; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	regs.ir = regs.irc;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int val = cctrue(3) ? 0xff : 0x00;
	put_byte_000(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 10 * CYCLE_UNIT / 2 + count_cycles;
}
/* 10 (1/1) */
/* 2 0,0   */

/* Scc.B (An)+ (LS) */
uae_u32 REGPARAM2 op_53d8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
	regs.ir = regs.irc;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int val = cctrue(3) ? 0xff : 0x00;
	put_byte_000(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (1/1) */
/* 2 0,0   */

/* Scc.B -(An) (LS) */
uae_u32 REGPARAM2 op_53e0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
	m68k_areg(regs, srcreg) = srca;
	regs.ir = regs.irc;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int val = cctrue(3) ? 0xff : 0x00;
	put_byte_000(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (1/1) */
/* 2 0,0   */

/* Scc.B (d16,An) (LS) */
uae_u32 REGPARAM2 op_53e8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int val = cctrue(3) ? 0xff : 0x00;
	put_byte_000(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (2/1) */
/* 4 0,0   */

/* Scc.B (d8,An,Xn) (LS) */
uae_u32 REGPARAM2 op_53f0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int val = cctrue(3) ? 0xff : 0x00;
	put_byte_000(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (2/1) */
/* 4 4,0   */

/* Scc.B (xxx).W (LS) */
uae_u32 REGPARAM2 op_53f8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 59;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int val = cctrue(3) ? 0xff : 0x00;
	put_byte_000(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (2/1) */
/* 4 0,0   */

/* Scc.B (xxx).L (LS) */
uae_u32 REGPARAM2 op_53f9_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 59;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	srca |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int val = cctrue(3) ? 0xff : 0x00;
	put_byte_000(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 6 0,0   */

/* Scc.B Dn (CC) */
uae_u32 REGPARAM2 op_54c0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 4;  
	int val = cctrue(4) ? 0xff : 0x00;
	if (!val) {
		m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff);
	}
	regs.ir = regs.irc;
	if (!val)
	opcode = regs.ir;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if(!val && regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff);
	count_cycles += ((val ? 2 : 0)) * CYCLE_UNIT / 2;
	m68k_incpci(2);
	return 4 * CYCLE_UNIT / 2 + count_cycles;
}
/* 4+ (1/0) */
/* 2 0,0   */

/* DBcc.W Dn,#<data>.W (CC) */
uae_u32 REGPARAM2 op_54c8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 58;
	CurrentInstrCycles = 10; 
	int pcadjust = -2;
	uae_s16 src = m68k_dreg(regs, srcreg);
	uae_s16 offs = regs.irc;
	int was_loop_mode = regs.loop_mode;
	regs.loop_mode = 0;
	uaecptr oldpc = m68k_getpci();
	if (!cctrue(4)) {
		m68k_incpci((uae_s32)offs + 2);
		if (offs & 1) {
			get_word_000_prefetch(-1);
			exception3_read_prefetch(opcode, m68k_getpci());
			return 2 * CYCLE_UNIT / 2 + count_cycles;
		}
		if(offs == -4 && !regs.t1 && loop_mode_table[regs.ird]) {
			if(!was_loop_mode) {
				uae_u16 irc = regs.irc;
				count_cycles += 4 * CYCLE_UNIT / 2;
				get_word_000_prefetch(0);
				if(hardware_bus_error) {
					int pcoffset = 0;
					exception2_fetch_opcode(opcode, 0, 0);
					return 2 * CYCLE_UNIT / 2 + count_cycles;
				}
				count_cycles += 4 * CYCLE_UNIT / 2;
				get_word_000_prefetch(2);
				if(hardware_bus_error) {
					int pcoffset = 0;
					exception2_fetch_opcode(opcode, 2, 0);
					return 2 * CYCLE_UNIT / 2 + count_cycles;
				}
				regs.irc = irc;
			} else {
				count_cycles += 2 * CYCLE_UNIT / 2;
			}
			regs.loop_mode = 1;
			src = m68k_dreg(regs, srcreg);
			m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
			if (src) {
				count_cycles += loop_mode_table[regs.ird](regs.ird);
				 // quick exit if condition false and count expired
				if (!cctrue(4) && (m68k_dreg(regs, srcreg) & 0xffff) == 0) {
					m68k_dreg(regs, srcreg) |= 0xffff;
					 // loop exit: add possible extra cycle(s)
					if(regs.loop_mode >> 16) {
						count_cycles += (regs.loop_mode >> 16) * CYCLE_UNIT / 2;
					}
					regs.loop_mode = 0;
					m68k_setpci_j(oldpc + 4);
					get_word_000_prefetch(0);
					if(hardware_bus_error) {
						int pcoffset = 0;
						m68k_setpci_j(oldpc + 2);
						exception2_fetch_opcode(opcode, 0, pcoffset);
						return 4 * CYCLE_UNIT / 2 + count_cycles;
					}
					regs.ir = regs.irc;
					opcode = regs.ir;
					get_word_000_prefetch(2);
					if(hardware_bus_error) {
						int pcoffset = 0;
						m68k_setpci_j(oldpc + 2);
						exception2_fetch_opcode(opcode, 2, pcoffset);
						return 8 * CYCLE_UNIT / 2 + count_cycles;
					}
					return 8 * CYCLE_UNIT / 2 + count_cycles;
				}
				 // loop continue: add possible extra cycle(s)
				if(regs.loop_mode & 0xfffe) {
					count_cycles += (regs.loop_mode & 0xfffe) * CYCLE_UNIT / 2;
				}
				m68k_setpci_j(oldpc);
				return 2 * CYCLE_UNIT / 2 + count_cycles;
			}
			regs.loop_mode = 0;
			m68k_setpci_j(oldpc + 4);
			get_word_000_prefetch(0);
			if(hardware_bus_error) {
				int pcoffset = 0;
				m68k_setpci_j(oldpc + 2);
				exception2_fetch_opcode(opcode, 0, pcoffset);
				return 16 * CYCLE_UNIT / 2 + count_cycles;
			}
			regs.ir = regs.irc;
			opcode = regs.ir;
			get_word_000_prefetch(2);
			if(hardware_bus_error) {
				int pcoffset = 0;
				m68k_setpci_j(oldpc + 2);
				exception2_fetch_opcode(opcode, 2, pcoffset);
				return 20 * CYCLE_UNIT / 2 + count_cycles;
			}
			return 8 * CYCLE_UNIT / 2 + count_cycles;
		}
		get_word_000_prefetch(0);
		if(hardware_bus_error) {
			int pcoffset = 0;
			pcoffset = oldpc - m68k_getpci() + 4;
			exception2_fetch_opcode(opcode, 0, pcoffset);
			return 6 * CYCLE_UNIT / 2 + count_cycles;
		}
		if (src) {
			m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
			regs.ir = regs.irc;
			opcode = regs.ir;
			get_word_000_prefetch(2);
			if(hardware_bus_error) {
				int pcoffset = 0;
				exception2_fetch_opcode(opcode, 2, 0);
				return 6 * CYCLE_UNIT / 2 + count_cycles;
			}
			return 10 * CYCLE_UNIT / 2 + count_cycles;
		}
		count_cycles += 6 * CYCLE_UNIT / 2;
		pcadjust = 0;
	}
	m68k_setpci_j(oldpc + 4);
	get_word_000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		pcoffset += pcadjust;
		exception2_fetch_opcode(opcode, 0, pcoffset);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	if (!cctrue(4)) {
		m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
	}
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 10 * CYCLE_UNIT / 2 + count_cycles;
}
/* 10 (2/0) */
/* 4 0,0 B */

/* Scc.B (An) (CC) */
uae_u32 REGPARAM2 op_54d0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 10; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	regs.ir = regs.irc;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int val = cctrue(4) ? 0xff : 0x00;
	put_byte_000(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 10 * CYCLE_UNIT / 2 + count_cycles;
}
/* 10 (1/1) */
/* 2 0,0   */

/* Scc.B (An)+ (CC) */
uae_u32 REGPARAM2 op_54d8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
	regs.ir = regs.irc;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int val = cctrue(4) ? 0xff : 0x00;
	put_byte_000(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (1/1) */
/* 2 0,0   */

/* Scc.B -(An) (CC) */
uae_u32 REGPARAM2 op_54e0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
	m68k_areg(regs, srcreg) = srca;
	regs.ir = regs.irc;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int val = cctrue(4) ? 0xff : 0x00;
	put_byte_000(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (1/1) */
/* 2 0,0   */

/* Scc.B (d16,An) (CC) */
uae_u32 REGPARAM2 op_54e8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int val = cctrue(4) ? 0xff : 0x00;
	put_byte_000(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (2/1) */
/* 4 0,0   */

/* Scc.B (d8,An,Xn) (CC) */
uae_u32 REGPARAM2 op_54f0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int val = cctrue(4) ? 0xff : 0x00;
	put_byte_000(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (2/1) */
/* 4 4,0   */

/* Scc.B (xxx).W (CC) */
uae_u32 REGPARAM2 op_54f8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 59;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int val = cctrue(4) ? 0xff : 0x00;
	put_byte_000(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (2/1) */
/* 4 0,0   */

/* Scc.B (xxx).L (CC) */
uae_u32 REGPARAM2 op_54f9_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 59;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	srca |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int val = cctrue(4) ? 0xff : 0x00;
	put_byte_000(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 6 0,0   */

/* Scc.B Dn (CS) */
uae_u32 REGPARAM2 op_55c0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 4;  
	int val = cctrue(5) ? 0xff : 0x00;
	if (!val) {
		m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff);
	}
	regs.ir = regs.irc;
	if (!val)
	opcode = regs.ir;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if(!val && regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff);
	count_cycles += ((val ? 2 : 0)) * CYCLE_UNIT / 2;
	m68k_incpci(2);
	return 4 * CYCLE_UNIT / 2 + count_cycles;
}
/* 4+ (1/0) */
/* 2 0,0   */

/* DBcc.W Dn,#<data>.W (CS) */
uae_u32 REGPARAM2 op_55c8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 58;
	CurrentInstrCycles = 10; 
	int pcadjust = -2;
	uae_s16 src = m68k_dreg(regs, srcreg);
	uae_s16 offs = regs.irc;
	int was_loop_mode = regs.loop_mode;
	regs.loop_mode = 0;
	uaecptr oldpc = m68k_getpci();
	if (!cctrue(5)) {
		m68k_incpci((uae_s32)offs + 2);
		if (offs & 1) {
			get_word_000_prefetch(-1);
			exception3_read_prefetch(opcode, m68k_getpci());
			return 2 * CYCLE_UNIT / 2 + count_cycles;
		}
		if(offs == -4 && !regs.t1 && loop_mode_table[regs.ird]) {
			if(!was_loop_mode) {
				uae_u16 irc = regs.irc;
				count_cycles += 4 * CYCLE_UNIT / 2;
				get_word_000_prefetch(0);
				if(hardware_bus_error) {
					int pcoffset = 0;
					exception2_fetch_opcode(opcode, 0, 0);
					return 2 * CYCLE_UNIT / 2 + count_cycles;
				}
				count_cycles += 4 * CYCLE_UNIT / 2;
				get_word_000_prefetch(2);
				if(hardware_bus_error) {
					int pcoffset = 0;
					exception2_fetch_opcode(opcode, 2, 0);
					return 2 * CYCLE_UNIT / 2 + count_cycles;
				}
				regs.irc = irc;
			} else {
				count_cycles += 2 * CYCLE_UNIT / 2;
			}
			regs.loop_mode = 1;
			src = m68k_dreg(regs, srcreg);
			m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
			if (src) {
				count_cycles += loop_mode_table[regs.ird](regs.ird);
				 // quick exit if condition false and count expired
				if (!cctrue(5) && (m68k_dreg(regs, srcreg) & 0xffff) == 0) {
					m68k_dreg(regs, srcreg) |= 0xffff;
					 // loop exit: add possible extra cycle(s)
					if(regs.loop_mode >> 16) {
						count_cycles += (regs.loop_mode >> 16) * CYCLE_UNIT / 2;
					}
					regs.loop_mode = 0;
					m68k_setpci_j(oldpc + 4);
					get_word_000_prefetch(0);
					if(hardware_bus_error) {
						int pcoffset = 0;
						m68k_setpci_j(oldpc + 2);
						exception2_fetch_opcode(opcode, 0, pcoffset);
						return 4 * CYCLE_UNIT / 2 + count_cycles;
					}
					regs.ir = regs.irc;
					opcode = regs.ir;
					get_word_000_prefetch(2);
					if(hardware_bus_error) {
						int pcoffset = 0;
						m68k_setpci_j(oldpc + 2);
						exception2_fetch_opcode(opcode, 2, pcoffset);
						return 8 * CYCLE_UNIT / 2 + count_cycles;
					}
					return 8 * CYCLE_UNIT / 2 + count_cycles;
				}
				 // loop continue: add possible extra cycle(s)
				if(regs.loop_mode & 0xfffe) {
					count_cycles += (regs.loop_mode & 0xfffe) * CYCLE_UNIT / 2;
				}
				m68k_setpci_j(oldpc);
				return 2 * CYCLE_UNIT / 2 + count_cycles;
			}
			regs.loop_mode = 0;
			m68k_setpci_j(oldpc + 4);
			get_word_000_prefetch(0);
			if(hardware_bus_error) {
				int pcoffset = 0;
				m68k_setpci_j(oldpc + 2);
				exception2_fetch_opcode(opcode, 0, pcoffset);
				return 16 * CYCLE_UNIT / 2 + count_cycles;
			}
			regs.ir = regs.irc;
			opcode = regs.ir;
			get_word_000_prefetch(2);
			if(hardware_bus_error) {
				int pcoffset = 0;
				m68k_setpci_j(oldpc + 2);
				exception2_fetch_opcode(opcode, 2, pcoffset);
				return 20 * CYCLE_UNIT / 2 + count_cycles;
			}
			return 8 * CYCLE_UNIT / 2 + count_cycles;
		}
		get_word_000_prefetch(0);
		if(hardware_bus_error) {
			int pcoffset = 0;
			pcoffset = oldpc - m68k_getpci() + 4;
			exception2_fetch_opcode(opcode, 0, pcoffset);
			return 6 * CYCLE_UNIT / 2 + count_cycles;
		}
		if (src) {
			m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
			regs.ir = regs.irc;
			opcode = regs.ir;
			get_word_000_prefetch(2);
			if(hardware_bus_error) {
				int pcoffset = 0;
				exception2_fetch_opcode(opcode, 2, 0);
				return 6 * CYCLE_UNIT / 2 + count_cycles;
			}
			return 10 * CYCLE_UNIT / 2 + count_cycles;
		}
		count_cycles += 6 * CYCLE_UNIT / 2;
		pcadjust = 0;
	}
	m68k_setpci_j(oldpc + 4);
	get_word_000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		pcoffset += pcadjust;
		exception2_fetch_opcode(opcode, 0, pcoffset);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	if (!cctrue(5)) {
		m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
	}
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 10 * CYCLE_UNIT / 2 + count_cycles;
}
/* 10 (2/0) */
/* 4 0,0 B */

/* Scc.B (An) (CS) */
uae_u32 REGPARAM2 op_55d0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 10; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	regs.ir = regs.irc;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int val = cctrue(5) ? 0xff : 0x00;
	put_byte_000(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 10 * CYCLE_UNIT / 2 + count_cycles;
}
/* 10 (1/1) */
/* 2 0,0   */

/* Scc.B (An)+ (CS) */
uae_u32 REGPARAM2 op_55d8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
	regs.ir = regs.irc;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int val = cctrue(5) ? 0xff : 0x00;
	put_byte_000(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (1/1) */
/* 2 0,0   */

/* Scc.B -(An) (CS) */
uae_u32 REGPARAM2 op_55e0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
	m68k_areg(regs, srcreg) = srca;
	regs.ir = regs.irc;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int val = cctrue(5) ? 0xff : 0x00;
	put_byte_000(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (1/1) */
/* 2 0,0   */

/* Scc.B (d16,An) (CS) */
uae_u32 REGPARAM2 op_55e8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int val = cctrue(5) ? 0xff : 0x00;
	put_byte_000(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (2/1) */
/* 4 0,0   */

/* Scc.B (d8,An,Xn) (CS) */
uae_u32 REGPARAM2 op_55f0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int val = cctrue(5) ? 0xff : 0x00;
	put_byte_000(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (2/1) */
/* 4 4,0   */

/* Scc.B (xxx).W (CS) */
uae_u32 REGPARAM2 op_55f8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 59;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int val = cctrue(5) ? 0xff : 0x00;
	put_byte_000(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (2/1) */
/* 4 0,0   */

/* Scc.B (xxx).L (CS) */
uae_u32 REGPARAM2 op_55f9_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 59;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	srca |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int val = cctrue(5) ? 0xff : 0x00;
	put_byte_000(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 6 0,0   */

/* Scc.B Dn (NE) */
uae_u32 REGPARAM2 op_56c0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 4;  
	int val = cctrue(6) ? 0xff : 0x00;
	if (!val) {
		m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff);
	}
	regs.ir = regs.irc;
	if (!val)
	opcode = regs.ir;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if(!val && regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff);
	count_cycles += ((val ? 2 : 0)) * CYCLE_UNIT / 2;
	m68k_incpci(2);
	return 4 * CYCLE_UNIT / 2 + count_cycles;
}
/* 4+ (1/0) */
/* 2 0,0   */

/* DBcc.W Dn,#<data>.W (NE) */
uae_u32 REGPARAM2 op_56c8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 58;
	CurrentInstrCycles = 10; 
	int pcadjust = -2;
	uae_s16 src = m68k_dreg(regs, srcreg);
	uae_s16 offs = regs.irc;
	int was_loop_mode = regs.loop_mode;
	regs.loop_mode = 0;
	uaecptr oldpc = m68k_getpci();
	if (!cctrue(6)) {
		m68k_incpci((uae_s32)offs + 2);
		if (offs & 1) {
			get_word_000_prefetch(-1);
			exception3_read_prefetch(opcode, m68k_getpci());
			return 2 * CYCLE_UNIT / 2 + count_cycles;
		}
		if(offs == -4 && !regs.t1 && loop_mode_table[regs.ird]) {
			if(!was_loop_mode) {
				uae_u16 irc = regs.irc;
				count_cycles += 4 * CYCLE_UNIT / 2;
				get_word_000_prefetch(0);
				if(hardware_bus_error) {
					int pcoffset = 0;
					exception2_fetch_opcode(opcode, 0, 0);
					return 2 * CYCLE_UNIT / 2 + count_cycles;
				}
				count_cycles += 4 * CYCLE_UNIT / 2;
				get_word_000_prefetch(2);
				if(hardware_bus_error) {
					int pcoffset = 0;
					exception2_fetch_opcode(opcode, 2, 0);
					return 2 * CYCLE_UNIT / 2 + count_cycles;
				}
				regs.irc = irc;
			} else {
				count_cycles += 2 * CYCLE_UNIT / 2;
			}
			regs.loop_mode = 1;
			src = m68k_dreg(regs, srcreg);
			m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
			if (src) {
				count_cycles += loop_mode_table[regs.ird](regs.ird);
				 // quick exit if condition false and count expired
				if (!cctrue(6) && (m68k_dreg(regs, srcreg) & 0xffff) == 0) {
					m68k_dreg(regs, srcreg) |= 0xffff;
					 // loop exit: add possible extra cycle(s)
					if(regs.loop_mode >> 16) {
						count_cycles += (regs.loop_mode >> 16) * CYCLE_UNIT / 2;
					}
					regs.loop_mode = 0;
					m68k_setpci_j(oldpc + 4);
					get_word_000_prefetch(0);
					if(hardware_bus_error) {
						int pcoffset = 0;
						m68k_setpci_j(oldpc + 2);
						exception2_fetch_opcode(opcode, 0, pcoffset);
						return 4 * CYCLE_UNIT / 2 + count_cycles;
					}
					regs.ir = regs.irc;
					opcode = regs.ir;
					get_word_000_prefetch(2);
					if(hardware_bus_error) {
						int pcoffset = 0;
						m68k_setpci_j(oldpc + 2);
						exception2_fetch_opcode(opcode, 2, pcoffset);
						return 8 * CYCLE_UNIT / 2 + count_cycles;
					}
					return 8 * CYCLE_UNIT / 2 + count_cycles;
				}
				 // loop continue: add possible extra cycle(s)
				if(regs.loop_mode & 0xfffe) {
					count_cycles += (regs.loop_mode & 0xfffe) * CYCLE_UNIT / 2;
				}
				m68k_setpci_j(oldpc);
				return 2 * CYCLE_UNIT / 2 + count_cycles;
			}
			regs.loop_mode = 0;
			m68k_setpci_j(oldpc + 4);
			get_word_000_prefetch(0);
			if(hardware_bus_error) {
				int pcoffset = 0;
				m68k_setpci_j(oldpc + 2);
				exception2_fetch_opcode(opcode, 0, pcoffset);
				return 16 * CYCLE_UNIT / 2 + count_cycles;
			}
			regs.ir = regs.irc;
			opcode = regs.ir;
			get_word_000_prefetch(2);
			if(hardware_bus_error) {
				int pcoffset = 0;
				m68k_setpci_j(oldpc + 2);
				exception2_fetch_opcode(opcode, 2, pcoffset);
				return 20 * CYCLE_UNIT / 2 + count_cycles;
			}
			return 8 * CYCLE_UNIT / 2 + count_cycles;
		}
		get_word_000_prefetch(0);
		if(hardware_bus_error) {
			int pcoffset = 0;
			pcoffset = oldpc - m68k_getpci() + 4;
			exception2_fetch_opcode(opcode, 0, pcoffset);
			return 6 * CYCLE_UNIT / 2 + count_cycles;
		}
		if (src) {
			m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
			regs.ir = regs.irc;
			opcode = regs.ir;
			get_word_000_prefetch(2);
			if(hardware_bus_error) {
				int pcoffset = 0;
				exception2_fetch_opcode(opcode, 2, 0);
				return 6 * CYCLE_UNIT / 2 + count_cycles;
			}
			return 10 * CYCLE_UNIT / 2 + count_cycles;
		}
		count_cycles += 6 * CYCLE_UNIT / 2;
		pcadjust = 0;
	}
	m68k_setpci_j(oldpc + 4);
	get_word_000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		pcoffset += pcadjust;
		exception2_fetch_opcode(opcode, 0, pcoffset);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	if (!cctrue(6)) {
		m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
	}
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 10 * CYCLE_UNIT / 2 + count_cycles;
}
/* 10 (2/0) */
/* 4 0,0 B */

/* Scc.B (An) (NE) */
uae_u32 REGPARAM2 op_56d0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 10; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	regs.ir = regs.irc;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int val = cctrue(6) ? 0xff : 0x00;
	put_byte_000(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 10 * CYCLE_UNIT / 2 + count_cycles;
}
/* 10 (1/1) */
/* 2 0,0   */

/* Scc.B (An)+ (NE) */
uae_u32 REGPARAM2 op_56d8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
	regs.ir = regs.irc;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int val = cctrue(6) ? 0xff : 0x00;
	put_byte_000(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (1/1) */
/* 2 0,0   */

/* Scc.B -(An) (NE) */
uae_u32 REGPARAM2 op_56e0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
	m68k_areg(regs, srcreg) = srca;
	regs.ir = regs.irc;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int val = cctrue(6) ? 0xff : 0x00;
	put_byte_000(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (1/1) */
/* 2 0,0   */

/* Scc.B (d16,An) (NE) */
uae_u32 REGPARAM2 op_56e8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int val = cctrue(6) ? 0xff : 0x00;
	put_byte_000(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (2/1) */
/* 4 0,0   */

/* Scc.B (d8,An,Xn) (NE) */
uae_u32 REGPARAM2 op_56f0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int val = cctrue(6) ? 0xff : 0x00;
	put_byte_000(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (2/1) */
/* 4 4,0   */

/* Scc.B (xxx).W (NE) */
uae_u32 REGPARAM2 op_56f8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 59;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int val = cctrue(6) ? 0xff : 0x00;
	put_byte_000(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (2/1) */
/* 4 0,0   */

/* Scc.B (xxx).L (NE) */
uae_u32 REGPARAM2 op_56f9_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 59;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	srca |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int val = cctrue(6) ? 0xff : 0x00;
	put_byte_000(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 6 0,0   */

/* Scc.B Dn (EQ) */
uae_u32 REGPARAM2 op_57c0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 4;  
	int val = cctrue(7) ? 0xff : 0x00;
	if (!val) {
		m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff);
	}
	regs.ir = regs.irc;
	if (!val)
	opcode = regs.ir;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if(!val && regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff);
	count_cycles += ((val ? 2 : 0)) * CYCLE_UNIT / 2;
	m68k_incpci(2);
	return 4 * CYCLE_UNIT / 2 + count_cycles;
}
/* 4+ (1/0) */
/* 2 0,0   */

/* DBcc.W Dn,#<data>.W (EQ) */
uae_u32 REGPARAM2 op_57c8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 58;
	CurrentInstrCycles = 10; 
	int pcadjust = -2;
	uae_s16 src = m68k_dreg(regs, srcreg);
	uae_s16 offs = regs.irc;
	int was_loop_mode = regs.loop_mode;
	regs.loop_mode = 0;
	uaecptr oldpc = m68k_getpci();
	if (!cctrue(7)) {
		m68k_incpci((uae_s32)offs + 2);
		if (offs & 1) {
			get_word_000_prefetch(-1);
			exception3_read_prefetch(opcode, m68k_getpci());
			return 2 * CYCLE_UNIT / 2 + count_cycles;
		}
		if(offs == -4 && !regs.t1 && loop_mode_table[regs.ird]) {
			if(!was_loop_mode) {
				uae_u16 irc = regs.irc;
				count_cycles += 4 * CYCLE_UNIT / 2;
				get_word_000_prefetch(0);
				if(hardware_bus_error) {
					int pcoffset = 0;
					exception2_fetch_opcode(opcode, 0, 0);
					return 2 * CYCLE_UNIT / 2 + count_cycles;
				}
				count_cycles += 4 * CYCLE_UNIT / 2;
				get_word_000_prefetch(2);
				if(hardware_bus_error) {
					int pcoffset = 0;
					exception2_fetch_opcode(opcode, 2, 0);
					return 2 * CYCLE_UNIT / 2 + count_cycles;
				}
				regs.irc = irc;
			} else {
				count_cycles += 2 * CYCLE_UNIT / 2;
			}
			regs.loop_mode = 1;
			src = m68k_dreg(regs, srcreg);
			m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
			if (src) {
				count_cycles += loop_mode_table[regs.ird](regs.ird);
				 // quick exit if condition false and count expired
				if (!cctrue(7) && (m68k_dreg(regs, srcreg) & 0xffff) == 0) {
					m68k_dreg(regs, srcreg) |= 0xffff;
					 // loop exit: add possible extra cycle(s)
					if(regs.loop_mode >> 16) {
						count_cycles += (regs.loop_mode >> 16) * CYCLE_UNIT / 2;
					}
					regs.loop_mode = 0;
					m68k_setpci_j(oldpc + 4);
					get_word_000_prefetch(0);
					if(hardware_bus_error) {
						int pcoffset = 0;
						m68k_setpci_j(oldpc + 2);
						exception2_fetch_opcode(opcode, 0, pcoffset);
						return 4 * CYCLE_UNIT / 2 + count_cycles;
					}
					regs.ir = regs.irc;
					opcode = regs.ir;
					get_word_000_prefetch(2);
					if(hardware_bus_error) {
						int pcoffset = 0;
						m68k_setpci_j(oldpc + 2);
						exception2_fetch_opcode(opcode, 2, pcoffset);
						return 8 * CYCLE_UNIT / 2 + count_cycles;
					}
					return 8 * CYCLE_UNIT / 2 + count_cycles;
				}
				 // loop continue: add possible extra cycle(s)
				if(regs.loop_mode & 0xfffe) {
					count_cycles += (regs.loop_mode & 0xfffe) * CYCLE_UNIT / 2;
				}
				m68k_setpci_j(oldpc);
				return 2 * CYCLE_UNIT / 2 + count_cycles;
			}
			regs.loop_mode = 0;
			m68k_setpci_j(oldpc + 4);
			get_word_000_prefetch(0);
			if(hardware_bus_error) {
				int pcoffset = 0;
				m68k_setpci_j(oldpc + 2);
				exception2_fetch_opcode(opcode, 0, pcoffset);
				return 16 * CYCLE_UNIT / 2 + count_cycles;
			}
			regs.ir = regs.irc;
			opcode = regs.ir;
			get_word_000_prefetch(2);
			if(hardware_bus_error) {
				int pcoffset = 0;
				m68k_setpci_j(oldpc + 2);
				exception2_fetch_opcode(opcode, 2, pcoffset);
				return 20 * CYCLE_UNIT / 2 + count_cycles;
			}
			return 8 * CYCLE_UNIT / 2 + count_cycles;
		}
		get_word_000_prefetch(0);
		if(hardware_bus_error) {
			int pcoffset = 0;
			pcoffset = oldpc - m68k_getpci() + 4;
			exception2_fetch_opcode(opcode, 0, pcoffset);
			return 6 * CYCLE_UNIT / 2 + count_cycles;
		}
		if (src) {
			m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
			regs.ir = regs.irc;
			opcode = regs.ir;
			get_word_000_prefetch(2);
			if(hardware_bus_error) {
				int pcoffset = 0;
				exception2_fetch_opcode(opcode, 2, 0);
				return 6 * CYCLE_UNIT / 2 + count_cycles;
			}
			return 10 * CYCLE_UNIT / 2 + count_cycles;
		}
		count_cycles += 6 * CYCLE_UNIT / 2;
		pcadjust = 0;
	}
	m68k_setpci_j(oldpc + 4);
	get_word_000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		pcoffset += pcadjust;
		exception2_fetch_opcode(opcode, 0, pcoffset);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	if (!cctrue(7)) {
		m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
	}
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 10 * CYCLE_UNIT / 2 + count_cycles;
}
/* 10 (2/0) */
/* 4 0,0 B */

/* Scc.B (An) (EQ) */
uae_u32 REGPARAM2 op_57d0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 10; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	regs.ir = regs.irc;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int val = cctrue(7) ? 0xff : 0x00;
	put_byte_000(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 10 * CYCLE_UNIT / 2 + count_cycles;
}
/* 10 (1/1) */
/* 2 0,0   */

/* Scc.B (An)+ (EQ) */
uae_u32 REGPARAM2 op_57d8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
	regs.ir = regs.irc;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int val = cctrue(7) ? 0xff : 0x00;
	put_byte_000(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (1/1) */
/* 2 0,0   */

/* Scc.B -(An) (EQ) */
uae_u32 REGPARAM2 op_57e0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
	m68k_areg(regs, srcreg) = srca;
	regs.ir = regs.irc;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int val = cctrue(7) ? 0xff : 0x00;
	put_byte_000(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (1/1) */
/* 2 0,0   */

/* Scc.B (d16,An) (EQ) */
uae_u32 REGPARAM2 op_57e8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int val = cctrue(7) ? 0xff : 0x00;
	put_byte_000(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (2/1) */
/* 4 0,0   */

/* Scc.B (d8,An,Xn) (EQ) */
uae_u32 REGPARAM2 op_57f0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int val = cctrue(7) ? 0xff : 0x00;
	put_byte_000(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (2/1) */
/* 4 4,0   */

/* Scc.B (xxx).W (EQ) */
uae_u32 REGPARAM2 op_57f8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 59;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int val = cctrue(7) ? 0xff : 0x00;
	put_byte_000(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (2/1) */
/* 4 0,0   */

/* Scc.B (xxx).L (EQ) */
uae_u32 REGPARAM2 op_57f9_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 59;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	srca |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int val = cctrue(7) ? 0xff : 0x00;
	put_byte_000(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 6 0,0   */

/* Scc.B Dn (VC) */
uae_u32 REGPARAM2 op_58c0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 4;  
	int val = cctrue(8) ? 0xff : 0x00;
	if (!val) {
		m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff);
	}
	regs.ir = regs.irc;
	if (!val)
	opcode = regs.ir;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if(!val && regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff);
	count_cycles += ((val ? 2 : 0)) * CYCLE_UNIT / 2;
	m68k_incpci(2);
	return 4 * CYCLE_UNIT / 2 + count_cycles;
}
/* 4+ (1/0) */
/* 2 0,0   */

/* DBcc.W Dn,#<data>.W (VC) */
uae_u32 REGPARAM2 op_58c8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 58;
	CurrentInstrCycles = 10; 
	int pcadjust = -2;
	uae_s16 src = m68k_dreg(regs, srcreg);
	uae_s16 offs = regs.irc;
	int was_loop_mode = regs.loop_mode;
	regs.loop_mode = 0;
	uaecptr oldpc = m68k_getpci();
	if (!cctrue(8)) {
		m68k_incpci((uae_s32)offs + 2);
		if (offs & 1) {
			get_word_000_prefetch(-1);
			exception3_read_prefetch(opcode, m68k_getpci());
			return 2 * CYCLE_UNIT / 2 + count_cycles;
		}
		if(offs == -4 && !regs.t1 && loop_mode_table[regs.ird]) {
			if(!was_loop_mode) {
				uae_u16 irc = regs.irc;
				count_cycles += 4 * CYCLE_UNIT / 2;
				get_word_000_prefetch(0);
				if(hardware_bus_error) {
					int pcoffset = 0;
					exception2_fetch_opcode(opcode, 0, 0);
					return 2 * CYCLE_UNIT / 2 + count_cycles;
				}
				count_cycles += 4 * CYCLE_UNIT / 2;
				get_word_000_prefetch(2);
				if(hardware_bus_error) {
					int pcoffset = 0;
					exception2_fetch_opcode(opcode, 2, 0);
					return 2 * CYCLE_UNIT / 2 + count_cycles;
				}
				regs.irc = irc;
			} else {
				count_cycles += 2 * CYCLE_UNIT / 2;
			}
			regs.loop_mode = 1;
			src = m68k_dreg(regs, srcreg);
			m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
			if (src) {
				count_cycles += loop_mode_table[regs.ird](regs.ird);
				 // quick exit if condition false and count expired
				if (!cctrue(8) && (m68k_dreg(regs, srcreg) & 0xffff) == 0) {
					m68k_dreg(regs, srcreg) |= 0xffff;
					 // loop exit: add possible extra cycle(s)
					if(regs.loop_mode >> 16) {
						count_cycles += (regs.loop_mode >> 16) * CYCLE_UNIT / 2;
					}
					regs.loop_mode = 0;
					m68k_setpci_j(oldpc + 4);
					get_word_000_prefetch(0);
					if(hardware_bus_error) {
						int pcoffset = 0;
						m68k_setpci_j(oldpc + 2);
						exception2_fetch_opcode(opcode, 0, pcoffset);
						return 4 * CYCLE_UNIT / 2 + count_cycles;
					}
					regs.ir = regs.irc;
					opcode = regs.ir;
					get_word_000_prefetch(2);
					if(hardware_bus_error) {
						int pcoffset = 0;
						m68k_setpci_j(oldpc + 2);
						exception2_fetch_opcode(opcode, 2, pcoffset);
						return 8 * CYCLE_UNIT / 2 + count_cycles;
					}
					return 8 * CYCLE_UNIT / 2 + count_cycles;
				}
				 // loop continue: add possible extra cycle(s)
				if(regs.loop_mode & 0xfffe) {
					count_cycles += (regs.loop_mode & 0xfffe) * CYCLE_UNIT / 2;
				}
				m68k_setpci_j(oldpc);
				return 2 * CYCLE_UNIT / 2 + count_cycles;
			}
			regs.loop_mode = 0;
			m68k_setpci_j(oldpc + 4);
			get_word_000_prefetch(0);
			if(hardware_bus_error) {
				int pcoffset = 0;
				m68k_setpci_j(oldpc + 2);
				exception2_fetch_opcode(opcode, 0, pcoffset);
				return 16 * CYCLE_UNIT / 2 + count_cycles;
			}
			regs.ir = regs.irc;
			opcode = regs.ir;
			get_word_000_prefetch(2);
			if(hardware_bus_error) {
				int pcoffset = 0;
				m68k_setpci_j(oldpc + 2);
				exception2_fetch_opcode(opcode, 2, pcoffset);
				return 20 * CYCLE_UNIT / 2 + count_cycles;
			}
			return 8 * CYCLE_UNIT / 2 + count_cycles;
		}
		get_word_000_prefetch(0);
		if(hardware_bus_error) {
			int pcoffset = 0;
			pcoffset = oldpc - m68k_getpci() + 4;
			exception2_fetch_opcode(opcode, 0, pcoffset);
			return 6 * CYCLE_UNIT / 2 + count_cycles;
		}
		if (src) {
			m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
			regs.ir = regs.irc;
			opcode = regs.ir;
			get_word_000_prefetch(2);
			if(hardware_bus_error) {
				int pcoffset = 0;
				exception2_fetch_opcode(opcode, 2, 0);
				return 6 * CYCLE_UNIT / 2 + count_cycles;
			}
			return 10 * CYCLE_UNIT / 2 + count_cycles;
		}
		count_cycles += 6 * CYCLE_UNIT / 2;
		pcadjust = 0;
	}
	m68k_setpci_j(oldpc + 4);
	get_word_000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		pcoffset += pcadjust;
		exception2_fetch_opcode(opcode, 0, pcoffset);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	if (!cctrue(8)) {
		m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
	}
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 10 * CYCLE_UNIT / 2 + count_cycles;
}
/* 10 (2/0) */
/* 4 0,0 B */

/* Scc.B (An) (VC) */
uae_u32 REGPARAM2 op_58d0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 10; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	regs.ir = regs.irc;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int val = cctrue(8) ? 0xff : 0x00;
	put_byte_000(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 10 * CYCLE_UNIT / 2 + count_cycles;
}
/* 10 (1/1) */
/* 2 0,0   */

/* Scc.B (An)+ (VC) */
uae_u32 REGPARAM2 op_58d8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
	regs.ir = regs.irc;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int val = cctrue(8) ? 0xff : 0x00;
	put_byte_000(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (1/1) */
/* 2 0,0   */

/* Scc.B -(An) (VC) */
uae_u32 REGPARAM2 op_58e0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
	m68k_areg(regs, srcreg) = srca;
	regs.ir = regs.irc;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int val = cctrue(8) ? 0xff : 0x00;
	put_byte_000(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (1/1) */
/* 2 0,0   */

/* Scc.B (d16,An) (VC) */
uae_u32 REGPARAM2 op_58e8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int val = cctrue(8) ? 0xff : 0x00;
	put_byte_000(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (2/1) */
/* 4 0,0   */

/* Scc.B (d8,An,Xn) (VC) */
uae_u32 REGPARAM2 op_58f0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int val = cctrue(8) ? 0xff : 0x00;
	put_byte_000(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (2/1) */
/* 4 4,0   */

/* Scc.B (xxx).W (VC) */
uae_u32 REGPARAM2 op_58f8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 59;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int val = cctrue(8) ? 0xff : 0x00;
	put_byte_000(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (2/1) */
/* 4 0,0   */

/* Scc.B (xxx).L (VC) */
uae_u32 REGPARAM2 op_58f9_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 59;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	srca |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int val = cctrue(8) ? 0xff : 0x00;
	put_byte_000(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 6 0,0   */

/* Scc.B Dn (VS) */
uae_u32 REGPARAM2 op_59c0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 4;  
	int val = cctrue(9) ? 0xff : 0x00;
	if (!val) {
		m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff);
	}
	regs.ir = regs.irc;
	if (!val)
	opcode = regs.ir;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if(!val && regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff);
	count_cycles += ((val ? 2 : 0)) * CYCLE_UNIT / 2;
	m68k_incpci(2);
	return 4 * CYCLE_UNIT / 2 + count_cycles;
}
/* 4+ (1/0) */
/* 2 0,0   */

/* DBcc.W Dn,#<data>.W (VS) */
uae_u32 REGPARAM2 op_59c8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 58;
	CurrentInstrCycles = 10; 
	int pcadjust = -2;
	uae_s16 src = m68k_dreg(regs, srcreg);
	uae_s16 offs = regs.irc;
	int was_loop_mode = regs.loop_mode;
	regs.loop_mode = 0;
	uaecptr oldpc = m68k_getpci();
	if (!cctrue(9)) {
		m68k_incpci((uae_s32)offs + 2);
		if (offs & 1) {
			get_word_000_prefetch(-1);
			exception3_read_prefetch(opcode, m68k_getpci());
			return 2 * CYCLE_UNIT / 2 + count_cycles;
		}
		if(offs == -4 && !regs.t1 && loop_mode_table[regs.ird]) {
			if(!was_loop_mode) {
				uae_u16 irc = regs.irc;
				count_cycles += 4 * CYCLE_UNIT / 2;
				get_word_000_prefetch(0);
				if(hardware_bus_error) {
					int pcoffset = 0;
					exception2_fetch_opcode(opcode, 0, 0);
					return 2 * CYCLE_UNIT / 2 + count_cycles;
				}
				count_cycles += 4 * CYCLE_UNIT / 2;
				get_word_000_prefetch(2);
				if(hardware_bus_error) {
					int pcoffset = 0;
					exception2_fetch_opcode(opcode, 2, 0);
					return 2 * CYCLE_UNIT / 2 + count_cycles;
				}
				regs.irc = irc;
			} else {
				count_cycles += 2 * CYCLE_UNIT / 2;
			}
			regs.loop_mode = 1;
			src = m68k_dreg(regs, srcreg);
			m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
			if (src) {
				count_cycles += loop_mode_table[regs.ird](regs.ird);
				 // quick exit if condition false and count expired
				if (!cctrue(9) && (m68k_dreg(regs, srcreg) & 0xffff) == 0) {
					m68k_dreg(regs, srcreg) |= 0xffff;
					 // loop exit: add possible extra cycle(s)
					if(regs.loop_mode >> 16) {
						count_cycles += (regs.loop_mode >> 16) * CYCLE_UNIT / 2;
					}
					regs.loop_mode = 0;
					m68k_setpci_j(oldpc + 4);
					get_word_000_prefetch(0);
					if(hardware_bus_error) {
						int pcoffset = 0;
						m68k_setpci_j(oldpc + 2);
						exception2_fetch_opcode(opcode, 0, pcoffset);
						return 4 * CYCLE_UNIT / 2 + count_cycles;
					}
					regs.ir = regs.irc;
					opcode = regs.ir;
					get_word_000_prefetch(2);
					if(hardware_bus_error) {
						int pcoffset = 0;
						m68k_setpci_j(oldpc + 2);
						exception2_fetch_opcode(opcode, 2, pcoffset);
						return 8 * CYCLE_UNIT / 2 + count_cycles;
					}
					return 8 * CYCLE_UNIT / 2 + count_cycles;
				}
				 // loop continue: add possible extra cycle(s)
				if(regs.loop_mode & 0xfffe) {
					count_cycles += (regs.loop_mode & 0xfffe) * CYCLE_UNIT / 2;
				}
				m68k_setpci_j(oldpc);
				return 2 * CYCLE_UNIT / 2 + count_cycles;
			}
			regs.loop_mode = 0;
			m68k_setpci_j(oldpc + 4);
			get_word_000_prefetch(0);
			if(hardware_bus_error) {
				int pcoffset = 0;
				m68k_setpci_j(oldpc + 2);
				exception2_fetch_opcode(opcode, 0, pcoffset);
				return 16 * CYCLE_UNIT / 2 + count_cycles;
			}
			regs.ir = regs.irc;
			opcode = regs.ir;
			get_word_000_prefetch(2);
			if(hardware_bus_error) {
				int pcoffset = 0;
				m68k_setpci_j(oldpc + 2);
				exception2_fetch_opcode(opcode, 2, pcoffset);
				return 20 * CYCLE_UNIT / 2 + count_cycles;
			}
			return 8 * CYCLE_UNIT / 2 + count_cycles;
		}
		get_word_000_prefetch(0);
		if(hardware_bus_error) {
			int pcoffset = 0;
			pcoffset = oldpc - m68k_getpci() + 4;
			exception2_fetch_opcode(opcode, 0, pcoffset);
			return 6 * CYCLE_UNIT / 2 + count_cycles;
		}
		if (src) {
			m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
			regs.ir = regs.irc;
			opcode = regs.ir;
			get_word_000_prefetch(2);
			if(hardware_bus_error) {
				int pcoffset = 0;
				exception2_fetch_opcode(opcode, 2, 0);
				return 6 * CYCLE_UNIT / 2 + count_cycles;
			}
			return 10 * CYCLE_UNIT / 2 + count_cycles;
		}
		count_cycles += 6 * CYCLE_UNIT / 2;
		pcadjust = 0;
	}
	m68k_setpci_j(oldpc + 4);
	get_word_000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		pcoffset += pcadjust;
		exception2_fetch_opcode(opcode, 0, pcoffset);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	if (!cctrue(9)) {
		m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
	}
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 10 * CYCLE_UNIT / 2 + count_cycles;
}
/* 10 (2/0) */
/* 4 0,0 B */

/* Scc.B (An) (VS) */
uae_u32 REGPARAM2 op_59d0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 10; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	regs.ir = regs.irc;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int val = cctrue(9) ? 0xff : 0x00;
	put_byte_000(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 10 * CYCLE_UNIT / 2 + count_cycles;
}
/* 10 (1/1) */
/* 2 0,0   */

/* Scc.B (An)+ (VS) */
uae_u32 REGPARAM2 op_59d8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
	regs.ir = regs.irc;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int val = cctrue(9) ? 0xff : 0x00;
	put_byte_000(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (1/1) */
/* 2 0,0   */

/* Scc.B -(An) (VS) */
uae_u32 REGPARAM2 op_59e0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
	m68k_areg(regs, srcreg) = srca;
	regs.ir = regs.irc;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int val = cctrue(9) ? 0xff : 0x00;
	put_byte_000(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (1/1) */
/* 2 0,0   */

/* Scc.B (d16,An) (VS) */
uae_u32 REGPARAM2 op_59e8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int val = cctrue(9) ? 0xff : 0x00;
	put_byte_000(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (2/1) */
/* 4 0,0   */

/* Scc.B (d8,An,Xn) (VS) */
uae_u32 REGPARAM2 op_59f0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int val = cctrue(9) ? 0xff : 0x00;
	put_byte_000(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (2/1) */
/* 4 4,0   */

/* Scc.B (xxx).W (VS) */
uae_u32 REGPARAM2 op_59f8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 59;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int val = cctrue(9) ? 0xff : 0x00;
	put_byte_000(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (2/1) */
/* 4 0,0   */

/* Scc.B (xxx).L (VS) */
uae_u32 REGPARAM2 op_59f9_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 59;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	srca |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int val = cctrue(9) ? 0xff : 0x00;
	put_byte_000(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 6 0,0   */

/* Scc.B Dn (PL) */
uae_u32 REGPARAM2 op_5ac0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 4;  
	int val = cctrue(10) ? 0xff : 0x00;
	if (!val) {
		m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff);
	}
	regs.ir = regs.irc;
	if (!val)
	opcode = regs.ir;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if(!val && regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff);
	count_cycles += ((val ? 2 : 0)) * CYCLE_UNIT / 2;
	m68k_incpci(2);
	return 4 * CYCLE_UNIT / 2 + count_cycles;
}
/* 4+ (1/0) */
/* 2 0,0   */

/* DBcc.W Dn,#<data>.W (PL) */
uae_u32 REGPARAM2 op_5ac8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 58;
	CurrentInstrCycles = 10; 
	int pcadjust = -2;
	uae_s16 src = m68k_dreg(regs, srcreg);
	uae_s16 offs = regs.irc;
	int was_loop_mode = regs.loop_mode;
	regs.loop_mode = 0;
	uaecptr oldpc = m68k_getpci();
	if (!cctrue(10)) {
		m68k_incpci((uae_s32)offs + 2);
		if (offs & 1) {
			get_word_000_prefetch(-1);
			exception3_read_prefetch(opcode, m68k_getpci());
			return 2 * CYCLE_UNIT / 2 + count_cycles;
		}
		if(offs == -4 && !regs.t1 && loop_mode_table[regs.ird]) {
			if(!was_loop_mode) {
				uae_u16 irc = regs.irc;
				count_cycles += 4 * CYCLE_UNIT / 2;
				get_word_000_prefetch(0);
				if(hardware_bus_error) {
					int pcoffset = 0;
					exception2_fetch_opcode(opcode, 0, 0);
					return 2 * CYCLE_UNIT / 2 + count_cycles;
				}
				count_cycles += 4 * CYCLE_UNIT / 2;
				get_word_000_prefetch(2);
				if(hardware_bus_error) {
					int pcoffset = 0;
					exception2_fetch_opcode(opcode, 2, 0);
					return 2 * CYCLE_UNIT / 2 + count_cycles;
				}
				regs.irc = irc;
			} else {
				count_cycles += 2 * CYCLE_UNIT / 2;
			}
			regs.loop_mode = 1;
			src = m68k_dreg(regs, srcreg);
			m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
			if (src) {
				count_cycles += loop_mode_table[regs.ird](regs.ird);
				 // quick exit if condition false and count expired
				if (!cctrue(10) && (m68k_dreg(regs, srcreg) & 0xffff) == 0) {
					m68k_dreg(regs, srcreg) |= 0xffff;
					 // loop exit: add possible extra cycle(s)
					if(regs.loop_mode >> 16) {
						count_cycles += (regs.loop_mode >> 16) * CYCLE_UNIT / 2;
					}
					regs.loop_mode = 0;
					m68k_setpci_j(oldpc + 4);
					get_word_000_prefetch(0);
					if(hardware_bus_error) {
						int pcoffset = 0;
						m68k_setpci_j(oldpc + 2);
						exception2_fetch_opcode(opcode, 0, pcoffset);
						return 4 * CYCLE_UNIT / 2 + count_cycles;
					}
					regs.ir = regs.irc;
					opcode = regs.ir;
					get_word_000_prefetch(2);
					if(hardware_bus_error) {
						int pcoffset = 0;
						m68k_setpci_j(oldpc + 2);
						exception2_fetch_opcode(opcode, 2, pcoffset);
						return 8 * CYCLE_UNIT / 2 + count_cycles;
					}
					return 8 * CYCLE_UNIT / 2 + count_cycles;
				}
				 // loop continue: add possible extra cycle(s)
				if(regs.loop_mode & 0xfffe) {
					count_cycles += (regs.loop_mode & 0xfffe) * CYCLE_UNIT / 2;
				}
				m68k_setpci_j(oldpc);
				return 2 * CYCLE_UNIT / 2 + count_cycles;
			}
			regs.loop_mode = 0;
			m68k_setpci_j(oldpc + 4);
			get_word_000_prefetch(0);
			if(hardware_bus_error) {
				int pcoffset = 0;
				m68k_setpci_j(oldpc + 2);
				exception2_fetch_opcode(opcode, 0, pcoffset);
				return 16 * CYCLE_UNIT / 2 + count_cycles;
			}
			regs.ir = regs.irc;
			opcode = regs.ir;
			get_word_000_prefetch(2);
			if(hardware_bus_error) {
				int pcoffset = 0;
				m68k_setpci_j(oldpc + 2);
				exception2_fetch_opcode(opcode, 2, pcoffset);
				return 20 * CYCLE_UNIT / 2 + count_cycles;
			}
			return 8 * CYCLE_UNIT / 2 + count_cycles;
		}
		get_word_000_prefetch(0);
		if(hardware_bus_error) {
			int pcoffset = 0;
			pcoffset = oldpc - m68k_getpci() + 4;
			exception2_fetch_opcode(opcode, 0, pcoffset);
			return 6 * CYCLE_UNIT / 2 + count_cycles;
		}
		if (src) {
			m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
			regs.ir = regs.irc;
			opcode = regs.ir;
			get_word_000_prefetch(2);
			if(hardware_bus_error) {
				int pcoffset = 0;
				exception2_fetch_opcode(opcode, 2, 0);
				return 6 * CYCLE_UNIT / 2 + count_cycles;
			}
			return 10 * CYCLE_UNIT / 2 + count_cycles;
		}
		count_cycles += 6 * CYCLE_UNIT / 2;
		pcadjust = 0;
	}
	m68k_setpci_j(oldpc + 4);
	get_word_000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		pcoffset += pcadjust;
		exception2_fetch_opcode(opcode, 0, pcoffset);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	if (!cctrue(10)) {
		m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
	}
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 10 * CYCLE_UNIT / 2 + count_cycles;
}
/* 10 (2/0) */
/* 4 0,0 B */

/* Scc.B (An) (PL) */
uae_u32 REGPARAM2 op_5ad0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 10; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	regs.ir = regs.irc;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int val = cctrue(10) ? 0xff : 0x00;
	put_byte_000(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 10 * CYCLE_UNIT / 2 + count_cycles;
}
/* 10 (1/1) */
/* 2 0,0   */

/* Scc.B (An)+ (PL) */
uae_u32 REGPARAM2 op_5ad8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
	regs.ir = regs.irc;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int val = cctrue(10) ? 0xff : 0x00;
	put_byte_000(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (1/1) */
/* 2 0,0   */

/* Scc.B -(An) (PL) */
uae_u32 REGPARAM2 op_5ae0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
	m68k_areg(regs, srcreg) = srca;
	regs.ir = regs.irc;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int val = cctrue(10) ? 0xff : 0x00;
	put_byte_000(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (1/1) */
/* 2 0,0   */

/* Scc.B (d16,An) (PL) */
uae_u32 REGPARAM2 op_5ae8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int val = cctrue(10) ? 0xff : 0x00;
	put_byte_000(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (2/1) */
/* 4 0,0   */

/* Scc.B (d8,An,Xn) (PL) */
uae_u32 REGPARAM2 op_5af0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int val = cctrue(10) ? 0xff : 0x00;
	put_byte_000(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (2/1) */
/* 4 4,0   */

/* Scc.B (xxx).W (PL) */
uae_u32 REGPARAM2 op_5af8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 59;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int val = cctrue(10) ? 0xff : 0x00;
	put_byte_000(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (2/1) */
/* 4 0,0   */

/* Scc.B (xxx).L (PL) */
uae_u32 REGPARAM2 op_5af9_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 59;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	srca |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int val = cctrue(10) ? 0xff : 0x00;
	put_byte_000(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 6 0,0   */

/* Scc.B Dn (MI) */
uae_u32 REGPARAM2 op_5bc0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 4;  
	int val = cctrue(11) ? 0xff : 0x00;
	if (!val) {
		m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff);
	}
	regs.ir = regs.irc;
	if (!val)
	opcode = regs.ir;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if(!val && regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff);
	count_cycles += ((val ? 2 : 0)) * CYCLE_UNIT / 2;
	m68k_incpci(2);
	return 4 * CYCLE_UNIT / 2 + count_cycles;
}
/* 4+ (1/0) */
/* 2 0,0   */

/* DBcc.W Dn,#<data>.W (MI) */
uae_u32 REGPARAM2 op_5bc8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 58;
	CurrentInstrCycles = 10; 
	int pcadjust = -2;
	uae_s16 src = m68k_dreg(regs, srcreg);
	uae_s16 offs = regs.irc;
	int was_loop_mode = regs.loop_mode;
	regs.loop_mode = 0;
	uaecptr oldpc = m68k_getpci();
	if (!cctrue(11)) {
		m68k_incpci((uae_s32)offs + 2);
		if (offs & 1) {
			get_word_000_prefetch(-1);
			exception3_read_prefetch(opcode, m68k_getpci());
			return 2 * CYCLE_UNIT / 2 + count_cycles;
		}
		if(offs == -4 && !regs.t1 && loop_mode_table[regs.ird]) {
			if(!was_loop_mode) {
				uae_u16 irc = regs.irc;
				count_cycles += 4 * CYCLE_UNIT / 2;
				get_word_000_prefetch(0);
				if(hardware_bus_error) {
					int pcoffset = 0;
					exception2_fetch_opcode(opcode, 0, 0);
					return 2 * CYCLE_UNIT / 2 + count_cycles;
				}
				count_cycles += 4 * CYCLE_UNIT / 2;
				get_word_000_prefetch(2);
				if(hardware_bus_error) {
					int pcoffset = 0;
					exception2_fetch_opcode(opcode, 2, 0);
					return 2 * CYCLE_UNIT / 2 + count_cycles;
				}
				regs.irc = irc;
			} else {
				count_cycles += 2 * CYCLE_UNIT / 2;
			}
			regs.loop_mode = 1;
			src = m68k_dreg(regs, srcreg);
			m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
			if (src) {
				count_cycles += loop_mode_table[regs.ird](regs.ird);
				 // quick exit if condition false and count expired
				if (!cctrue(11) && (m68k_dreg(regs, srcreg) & 0xffff) == 0) {
					m68k_dreg(regs, srcreg) |= 0xffff;
					 // loop exit: add possible extra cycle(s)
					if(regs.loop_mode >> 16) {
						count_cycles += (regs.loop_mode >> 16) * CYCLE_UNIT / 2;
					}
					regs.loop_mode = 0;
					m68k_setpci_j(oldpc + 4);
					get_word_000_prefetch(0);
					if(hardware_bus_error) {
						int pcoffset = 0;
						m68k_setpci_j(oldpc + 2);
						exception2_fetch_opcode(opcode, 0, pcoffset);
						return 4 * CYCLE_UNIT / 2 + count_cycles;
					}
					regs.ir = regs.irc;
					opcode = regs.ir;
					get_word_000_prefetch(2);
					if(hardware_bus_error) {
						int pcoffset = 0;
						m68k_setpci_j(oldpc + 2);
						exception2_fetch_opcode(opcode, 2, pcoffset);
						return 8 * CYCLE_UNIT / 2 + count_cycles;
					}
					return 8 * CYCLE_UNIT / 2 + count_cycles;
				}
				 // loop continue: add possible extra cycle(s)
				if(regs.loop_mode & 0xfffe) {
					count_cycles += (regs.loop_mode & 0xfffe) * CYCLE_UNIT / 2;
				}
				m68k_setpci_j(oldpc);
				return 2 * CYCLE_UNIT / 2 + count_cycles;
			}
			regs.loop_mode = 0;
			m68k_setpci_j(oldpc + 4);
			get_word_000_prefetch(0);
			if(hardware_bus_error) {
				int pcoffset = 0;
				m68k_setpci_j(oldpc + 2);
				exception2_fetch_opcode(opcode, 0, pcoffset);
				return 16 * CYCLE_UNIT / 2 + count_cycles;
			}
			regs.ir = regs.irc;
			opcode = regs.ir;
			get_word_000_prefetch(2);
			if(hardware_bus_error) {
				int pcoffset = 0;
				m68k_setpci_j(oldpc + 2);
				exception2_fetch_opcode(opcode, 2, pcoffset);
				return 20 * CYCLE_UNIT / 2 + count_cycles;
			}
			return 8 * CYCLE_UNIT / 2 + count_cycles;
		}
		get_word_000_prefetch(0);
		if(hardware_bus_error) {
			int pcoffset = 0;
			pcoffset = oldpc - m68k_getpci() + 4;
			exception2_fetch_opcode(opcode, 0, pcoffset);
			return 6 * CYCLE_UNIT / 2 + count_cycles;
		}
		if (src) {
			m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
			regs.ir = regs.irc;
			opcode = regs.ir;
			get_word_000_prefetch(2);
			if(hardware_bus_error) {
				int pcoffset = 0;
				exception2_fetch_opcode(opcode, 2, 0);
				return 6 * CYCLE_UNIT / 2 + count_cycles;
			}
			return 10 * CYCLE_UNIT / 2 + count_cycles;
		}
		count_cycles += 6 * CYCLE_UNIT / 2;
		pcadjust = 0;
	}
	m68k_setpci_j(oldpc + 4);
	get_word_000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		pcoffset += pcadjust;
		exception2_fetch_opcode(opcode, 0, pcoffset);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	if (!cctrue(11)) {
		m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
	}
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 10 * CYCLE_UNIT / 2 + count_cycles;
}
/* 10 (2/0) */
/* 4 0,0 B */

/* Scc.B (An) (MI) */
uae_u32 REGPARAM2 op_5bd0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 10; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	regs.ir = regs.irc;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int val = cctrue(11) ? 0xff : 0x00;
	put_byte_000(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 10 * CYCLE_UNIT / 2 + count_cycles;
}
/* 10 (1/1) */
/* 2 0,0   */

/* Scc.B (An)+ (MI) */
uae_u32 REGPARAM2 op_5bd8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
	regs.ir = regs.irc;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int val = cctrue(11) ? 0xff : 0x00;
	put_byte_000(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (1/1) */
/* 2 0,0   */

/* Scc.B -(An) (MI) */
uae_u32 REGPARAM2 op_5be0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
	m68k_areg(regs, srcreg) = srca;
	regs.ir = regs.irc;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int val = cctrue(11) ? 0xff : 0x00;
	put_byte_000(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (1/1) */
/* 2 0,0   */

/* Scc.B (d16,An) (MI) */
uae_u32 REGPARAM2 op_5be8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int val = cctrue(11) ? 0xff : 0x00;
	put_byte_000(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (2/1) */
/* 4 0,0   */

/* Scc.B (d8,An,Xn) (MI) */
uae_u32 REGPARAM2 op_5bf0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int val = cctrue(11) ? 0xff : 0x00;
	put_byte_000(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (2/1) */
/* 4 4,0   */

/* Scc.B (xxx).W (MI) */
uae_u32 REGPARAM2 op_5bf8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 59;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int val = cctrue(11) ? 0xff : 0x00;
	put_byte_000(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (2/1) */
/* 4 0,0   */

/* Scc.B (xxx).L (MI) */
uae_u32 REGPARAM2 op_5bf9_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 59;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	srca |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int val = cctrue(11) ? 0xff : 0x00;
	put_byte_000(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 6 0,0   */

/* Scc.B Dn (GE) */
uae_u32 REGPARAM2 op_5cc0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 4;  
	int val = cctrue(12) ? 0xff : 0x00;
	if (!val) {
		m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff);
	}
	regs.ir = regs.irc;
	if (!val)
	opcode = regs.ir;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if(!val && regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff);
	count_cycles += ((val ? 2 : 0)) * CYCLE_UNIT / 2;
	m68k_incpci(2);
	return 4 * CYCLE_UNIT / 2 + count_cycles;
}
/* 4+ (1/0) */
/* 2 0,0   */

/* DBcc.W Dn,#<data>.W (GE) */
uae_u32 REGPARAM2 op_5cc8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 58;
	CurrentInstrCycles = 10; 
	int pcadjust = -2;
	uae_s16 src = m68k_dreg(regs, srcreg);
	uae_s16 offs = regs.irc;
	int was_loop_mode = regs.loop_mode;
	regs.loop_mode = 0;
	uaecptr oldpc = m68k_getpci();
	if (!cctrue(12)) {
		m68k_incpci((uae_s32)offs + 2);
		if (offs & 1) {
			get_word_000_prefetch(-1);
			exception3_read_prefetch(opcode, m68k_getpci());
			return 2 * CYCLE_UNIT / 2 + count_cycles;
		}
		if(offs == -4 && !regs.t1 && loop_mode_table[regs.ird]) {
			if(!was_loop_mode) {
				uae_u16 irc = regs.irc;
				count_cycles += 4 * CYCLE_UNIT / 2;
				get_word_000_prefetch(0);
				if(hardware_bus_error) {
					int pcoffset = 0;
					exception2_fetch_opcode(opcode, 0, 0);
					return 2 * CYCLE_UNIT / 2 + count_cycles;
				}
				count_cycles += 4 * CYCLE_UNIT / 2;
				get_word_000_prefetch(2);
				if(hardware_bus_error) {
					int pcoffset = 0;
					exception2_fetch_opcode(opcode, 2, 0);
					return 2 * CYCLE_UNIT / 2 + count_cycles;
				}
				regs.irc = irc;
			} else {
				count_cycles += 2 * CYCLE_UNIT / 2;
			}
			regs.loop_mode = 1;
			src = m68k_dreg(regs, srcreg);
			m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
			if (src) {
				count_cycles += loop_mode_table[regs.ird](regs.ird);
				 // quick exit if condition false and count expired
				if (!cctrue(12) && (m68k_dreg(regs, srcreg) & 0xffff) == 0) {
					m68k_dreg(regs, srcreg) |= 0xffff;
					 // loop exit: add possible extra cycle(s)
					if(regs.loop_mode >> 16) {
						count_cycles += (regs.loop_mode >> 16) * CYCLE_UNIT / 2;
					}
					regs.loop_mode = 0;
					m68k_setpci_j(oldpc + 4);
					get_word_000_prefetch(0);
					if(hardware_bus_error) {
						int pcoffset = 0;
						m68k_setpci_j(oldpc + 2);
						exception2_fetch_opcode(opcode, 0, pcoffset);
						return 4 * CYCLE_UNIT / 2 + count_cycles;
					}
					regs.ir = regs.irc;
					opcode = regs.ir;
					get_word_000_prefetch(2);
					if(hardware_bus_error) {
						int pcoffset = 0;
						m68k_setpci_j(oldpc + 2);
						exception2_fetch_opcode(opcode, 2, pcoffset);
						return 8 * CYCLE_UNIT / 2 + count_cycles;
					}
					return 8 * CYCLE_UNIT / 2 + count_cycles;
				}
				 // loop continue: add possible extra cycle(s)
				if(regs.loop_mode & 0xfffe) {
					count_cycles += (regs.loop_mode & 0xfffe) * CYCLE_UNIT / 2;
				}
				m68k_setpci_j(oldpc);
				return 2 * CYCLE_UNIT / 2 + count_cycles;
			}
			regs.loop_mode = 0;
			m68k_setpci_j(oldpc + 4);
			get_word_000_prefetch(0);
			if(hardware_bus_error) {
				int pcoffset = 0;
				m68k_setpci_j(oldpc + 2);
				exception2_fetch_opcode(opcode, 0, pcoffset);
				return 16 * CYCLE_UNIT / 2 + count_cycles;
			}
			regs.ir = regs.irc;
			opcode = regs.ir;
			get_word_000_prefetch(2);
			if(hardware_bus_error) {
				int pcoffset = 0;
				m68k_setpci_j(oldpc + 2);
				exception2_fetch_opcode(opcode, 2, pcoffset);
				return 20 * CYCLE_UNIT / 2 + count_cycles;
			}
			return 8 * CYCLE_UNIT / 2 + count_cycles;
		}
		get_word_000_prefetch(0);
		if(hardware_bus_error) {
			int pcoffset = 0;
			pcoffset = oldpc - m68k_getpci() + 4;
			exception2_fetch_opcode(opcode, 0, pcoffset);
			return 6 * CYCLE_UNIT / 2 + count_cycles;
		}
		if (src) {
			m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
			regs.ir = regs.irc;
			opcode = regs.ir;
			get_word_000_prefetch(2);
			if(hardware_bus_error) {
				int pcoffset = 0;
				exception2_fetch_opcode(opcode, 2, 0);
				return 6 * CYCLE_UNIT / 2 + count_cycles;
			}
			return 10 * CYCLE_UNIT / 2 + count_cycles;
		}
		count_cycles += 6 * CYCLE_UNIT / 2;
		pcadjust = 0;
	}
	m68k_setpci_j(oldpc + 4);
	get_word_000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		pcoffset += pcadjust;
		exception2_fetch_opcode(opcode, 0, pcoffset);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	if (!cctrue(12)) {
		m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
	}
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 10 * CYCLE_UNIT / 2 + count_cycles;
}
/* 10 (2/0) */
/* 4 0,0 B */

/* Scc.B (An) (GE) */
uae_u32 REGPARAM2 op_5cd0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 10; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	regs.ir = regs.irc;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int val = cctrue(12) ? 0xff : 0x00;
	put_byte_000(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 10 * CYCLE_UNIT / 2 + count_cycles;
}
/* 10 (1/1) */
/* 2 0,0   */

/* Scc.B (An)+ (GE) */
uae_u32 REGPARAM2 op_5cd8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
	regs.ir = regs.irc;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int val = cctrue(12) ? 0xff : 0x00;
	put_byte_000(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (1/1) */
/* 2 0,0   */

/* Scc.B -(An) (GE) */
uae_u32 REGPARAM2 op_5ce0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
	m68k_areg(regs, srcreg) = srca;
	regs.ir = regs.irc;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int val = cctrue(12) ? 0xff : 0x00;
	put_byte_000(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (1/1) */
/* 2 0,0   */

/* Scc.B (d16,An) (GE) */
uae_u32 REGPARAM2 op_5ce8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int val = cctrue(12) ? 0xff : 0x00;
	put_byte_000(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (2/1) */
/* 4 0,0   */

/* Scc.B (d8,An,Xn) (GE) */
uae_u32 REGPARAM2 op_5cf0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int val = cctrue(12) ? 0xff : 0x00;
	put_byte_000(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (2/1) */
/* 4 4,0   */

/* Scc.B (xxx).W (GE) */
uae_u32 REGPARAM2 op_5cf8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 59;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int val = cctrue(12) ? 0xff : 0x00;
	put_byte_000(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (2/1) */
/* 4 0,0   */

/* Scc.B (xxx).L (GE) */
uae_u32 REGPARAM2 op_5cf9_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 59;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	srca |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int val = cctrue(12) ? 0xff : 0x00;
	put_byte_000(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 6 0,0   */

/* Scc.B Dn (LT) */
uae_u32 REGPARAM2 op_5dc0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 4;  
	int val = cctrue(13) ? 0xff : 0x00;
	if (!val) {
		m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff);
	}
	regs.ir = regs.irc;
	if (!val)
	opcode = regs.ir;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if(!val && regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff);
	count_cycles += ((val ? 2 : 0)) * CYCLE_UNIT / 2;
	m68k_incpci(2);
	return 4 * CYCLE_UNIT / 2 + count_cycles;
}
/* 4+ (1/0) */
/* 2 0,0   */

/* DBcc.W Dn,#<data>.W (LT) */
uae_u32 REGPARAM2 op_5dc8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 58;
	CurrentInstrCycles = 10; 
	int pcadjust = -2;
	uae_s16 src = m68k_dreg(regs, srcreg);
	uae_s16 offs = regs.irc;
	int was_loop_mode = regs.loop_mode;
	regs.loop_mode = 0;
	uaecptr oldpc = m68k_getpci();
	if (!cctrue(13)) {
		m68k_incpci((uae_s32)offs + 2);
		if (offs & 1) {
			get_word_000_prefetch(-1);
			exception3_read_prefetch(opcode, m68k_getpci());
			return 2 * CYCLE_UNIT / 2 + count_cycles;
		}
		if(offs == -4 && !regs.t1 && loop_mode_table[regs.ird]) {
			if(!was_loop_mode) {
				uae_u16 irc = regs.irc;
				count_cycles += 4 * CYCLE_UNIT / 2;
				get_word_000_prefetch(0);
				if(hardware_bus_error) {
					int pcoffset = 0;
					exception2_fetch_opcode(opcode, 0, 0);
					return 2 * CYCLE_UNIT / 2 + count_cycles;
				}
				count_cycles += 4 * CYCLE_UNIT / 2;
				get_word_000_prefetch(2);
				if(hardware_bus_error) {
					int pcoffset = 0;
					exception2_fetch_opcode(opcode, 2, 0);
					return 2 * CYCLE_UNIT / 2 + count_cycles;
				}
				regs.irc = irc;
			} else {
				count_cycles += 2 * CYCLE_UNIT / 2;
			}
			regs.loop_mode = 1;
			src = m68k_dreg(regs, srcreg);
			m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
			if (src) {
				count_cycles += loop_mode_table[regs.ird](regs.ird);
				 // quick exit if condition false and count expired
				if (!cctrue(13) && (m68k_dreg(regs, srcreg) & 0xffff) == 0) {
					m68k_dreg(regs, srcreg) |= 0xffff;
					 // loop exit: add possible extra cycle(s)
					if(regs.loop_mode >> 16) {
						count_cycles += (regs.loop_mode >> 16) * CYCLE_UNIT / 2;
					}
					regs.loop_mode = 0;
					m68k_setpci_j(oldpc + 4);
					get_word_000_prefetch(0);
					if(hardware_bus_error) {
						int pcoffset = 0;
						m68k_setpci_j(oldpc + 2);
						exception2_fetch_opcode(opcode, 0, pcoffset);
						return 4 * CYCLE_UNIT / 2 + count_cycles;
					}
					regs.ir = regs.irc;
					opcode = regs.ir;
					get_word_000_prefetch(2);
					if(hardware_bus_error) {
						int pcoffset = 0;
						m68k_setpci_j(oldpc + 2);
						exception2_fetch_opcode(opcode, 2, pcoffset);
						return 8 * CYCLE_UNIT / 2 + count_cycles;
					}
					return 8 * CYCLE_UNIT / 2 + count_cycles;
				}
				 // loop continue: add possible extra cycle(s)
				if(regs.loop_mode & 0xfffe) {
					count_cycles += (regs.loop_mode & 0xfffe) * CYCLE_UNIT / 2;
				}
				m68k_setpci_j(oldpc);
				return 2 * CYCLE_UNIT / 2 + count_cycles;
			}
			regs.loop_mode = 0;
			m68k_setpci_j(oldpc + 4);
			get_word_000_prefetch(0);
			if(hardware_bus_error) {
				int pcoffset = 0;
				m68k_setpci_j(oldpc + 2);
				exception2_fetch_opcode(opcode, 0, pcoffset);
				return 16 * CYCLE_UNIT / 2 + count_cycles;
			}
			regs.ir = regs.irc;
			opcode = regs.ir;
			get_word_000_prefetch(2);
			if(hardware_bus_error) {
				int pcoffset = 0;
				m68k_setpci_j(oldpc + 2);
				exception2_fetch_opcode(opcode, 2, pcoffset);
				return 20 * CYCLE_UNIT / 2 + count_cycles;
			}
			return 8 * CYCLE_UNIT / 2 + count_cycles;
		}
		get_word_000_prefetch(0);
		if(hardware_bus_error) {
			int pcoffset = 0;
			pcoffset = oldpc - m68k_getpci() + 4;
			exception2_fetch_opcode(opcode, 0, pcoffset);
			return 6 * CYCLE_UNIT / 2 + count_cycles;
		}
		if (src) {
			m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
			regs.ir = regs.irc;
			opcode = regs.ir;
			get_word_000_prefetch(2);
			if(hardware_bus_error) {
				int pcoffset = 0;
				exception2_fetch_opcode(opcode, 2, 0);
				return 6 * CYCLE_UNIT / 2 + count_cycles;
			}
			return 10 * CYCLE_UNIT / 2 + count_cycles;
		}
		count_cycles += 6 * CYCLE_UNIT / 2;
		pcadjust = 0;
	}
	m68k_setpci_j(oldpc + 4);
	get_word_000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		pcoffset += pcadjust;
		exception2_fetch_opcode(opcode, 0, pcoffset);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	if (!cctrue(13)) {
		m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
	}
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 10 * CYCLE_UNIT / 2 + count_cycles;
}
/* 10 (2/0) */
/* 4 0,0 B */

/* Scc.B (An) (LT) */
uae_u32 REGPARAM2 op_5dd0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 10; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	regs.ir = regs.irc;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int val = cctrue(13) ? 0xff : 0x00;
	put_byte_000(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 10 * CYCLE_UNIT / 2 + count_cycles;
}
/* 10 (1/1) */
/* 2 0,0   */

/* Scc.B (An)+ (LT) */
uae_u32 REGPARAM2 op_5dd8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
	regs.ir = regs.irc;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int val = cctrue(13) ? 0xff : 0x00;
	put_byte_000(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (1/1) */
/* 2 0,0   */

/* Scc.B -(An) (LT) */
uae_u32 REGPARAM2 op_5de0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
	m68k_areg(regs, srcreg) = srca;
	regs.ir = regs.irc;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int val = cctrue(13) ? 0xff : 0x00;
	put_byte_000(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (1/1) */
/* 2 0,0   */

/* Scc.B (d16,An) (LT) */
uae_u32 REGPARAM2 op_5de8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int val = cctrue(13) ? 0xff : 0x00;
	put_byte_000(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (2/1) */
/* 4 0,0   */

/* Scc.B (d8,An,Xn) (LT) */
uae_u32 REGPARAM2 op_5df0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int val = cctrue(13) ? 0xff : 0x00;
	put_byte_000(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (2/1) */
/* 4 4,0   */

/* Scc.B (xxx).W (LT) */
uae_u32 REGPARAM2 op_5df8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 59;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int val = cctrue(13) ? 0xff : 0x00;
	put_byte_000(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (2/1) */
/* 4 0,0   */

/* Scc.B (xxx).L (LT) */
uae_u32 REGPARAM2 op_5df9_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 59;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	srca |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int val = cctrue(13) ? 0xff : 0x00;
	put_byte_000(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 6 0,0   */

/* Scc.B Dn (GT) */
uae_u32 REGPARAM2 op_5ec0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 4;  
	int val = cctrue(14) ? 0xff : 0x00;
	if (!val) {
		m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff);
	}
	regs.ir = regs.irc;
	if (!val)
	opcode = regs.ir;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if(!val && regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff);
	count_cycles += ((val ? 2 : 0)) * CYCLE_UNIT / 2;
	m68k_incpci(2);
	return 4 * CYCLE_UNIT / 2 + count_cycles;
}
/* 4+ (1/0) */
/* 2 0,0   */

/* DBcc.W Dn,#<data>.W (GT) */
uae_u32 REGPARAM2 op_5ec8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 58;
	CurrentInstrCycles = 10; 
	int pcadjust = -2;
	uae_s16 src = m68k_dreg(regs, srcreg);
	uae_s16 offs = regs.irc;
	int was_loop_mode = regs.loop_mode;
	regs.loop_mode = 0;
	uaecptr oldpc = m68k_getpci();
	if (!cctrue(14)) {
		m68k_incpci((uae_s32)offs + 2);
		if (offs & 1) {
			get_word_000_prefetch(-1);
			exception3_read_prefetch(opcode, m68k_getpci());
			return 2 * CYCLE_UNIT / 2 + count_cycles;
		}
		if(offs == -4 && !regs.t1 && loop_mode_table[regs.ird]) {
			if(!was_loop_mode) {
				uae_u16 irc = regs.irc;
				count_cycles += 4 * CYCLE_UNIT / 2;
				get_word_000_prefetch(0);
				if(hardware_bus_error) {
					int pcoffset = 0;
					exception2_fetch_opcode(opcode, 0, 0);
					return 2 * CYCLE_UNIT / 2 + count_cycles;
				}
				count_cycles += 4 * CYCLE_UNIT / 2;
				get_word_000_prefetch(2);
				if(hardware_bus_error) {
					int pcoffset = 0;
					exception2_fetch_opcode(opcode, 2, 0);
					return 2 * CYCLE_UNIT / 2 + count_cycles;
				}
				regs.irc = irc;
			} else {
				count_cycles += 2 * CYCLE_UNIT / 2;
			}
			regs.loop_mode = 1;
			src = m68k_dreg(regs, srcreg);
			m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
			if (src) {
				count_cycles += loop_mode_table[regs.ird](regs.ird);
				 // quick exit if condition false and count expired
				if (!cctrue(14) && (m68k_dreg(regs, srcreg) & 0xffff) == 0) {
					m68k_dreg(regs, srcreg) |= 0xffff;
					 // loop exit: add possible extra cycle(s)
					if(regs.loop_mode >> 16) {
						count_cycles += (regs.loop_mode >> 16) * CYCLE_UNIT / 2;
					}
					regs.loop_mode = 0;
					m68k_setpci_j(oldpc + 4);
					get_word_000_prefetch(0);
					if(hardware_bus_error) {
						int pcoffset = 0;
						m68k_setpci_j(oldpc + 2);
						exception2_fetch_opcode(opcode, 0, pcoffset);
						return 4 * CYCLE_UNIT / 2 + count_cycles;
					}
					regs.ir = regs.irc;
					opcode = regs.ir;
					get_word_000_prefetch(2);
					if(hardware_bus_error) {
						int pcoffset = 0;
						m68k_setpci_j(oldpc + 2);
						exception2_fetch_opcode(opcode, 2, pcoffset);
						return 8 * CYCLE_UNIT / 2 + count_cycles;
					}
					return 8 * CYCLE_UNIT / 2 + count_cycles;
				}
				 // loop continue: add possible extra cycle(s)
				if(regs.loop_mode & 0xfffe) {
					count_cycles += (regs.loop_mode & 0xfffe) * CYCLE_UNIT / 2;
				}
				m68k_setpci_j(oldpc);
				return 2 * CYCLE_UNIT / 2 + count_cycles;
			}
			regs.loop_mode = 0;
			m68k_setpci_j(oldpc + 4);
			get_word_000_prefetch(0);
			if(hardware_bus_error) {
				int pcoffset = 0;
				m68k_setpci_j(oldpc + 2);
				exception2_fetch_opcode(opcode, 0, pcoffset);
				return 16 * CYCLE_UNIT / 2 + count_cycles;
			}
			regs.ir = regs.irc;
			opcode = regs.ir;
			get_word_000_prefetch(2);
			if(hardware_bus_error) {
				int pcoffset = 0;
				m68k_setpci_j(oldpc + 2);
				exception2_fetch_opcode(opcode, 2, pcoffset);
				return 20 * CYCLE_UNIT / 2 + count_cycles;
			}
			return 8 * CYCLE_UNIT / 2 + count_cycles;
		}
		get_word_000_prefetch(0);
		if(hardware_bus_error) {
			int pcoffset = 0;
			pcoffset = oldpc - m68k_getpci() + 4;
			exception2_fetch_opcode(opcode, 0, pcoffset);
			return 6 * CYCLE_UNIT / 2 + count_cycles;
		}
		if (src) {
			m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
			regs.ir = regs.irc;
			opcode = regs.ir;
			get_word_000_prefetch(2);
			if(hardware_bus_error) {
				int pcoffset = 0;
				exception2_fetch_opcode(opcode, 2, 0);
				return 6 * CYCLE_UNIT / 2 + count_cycles;
			}
			return 10 * CYCLE_UNIT / 2 + count_cycles;
		}
		count_cycles += 6 * CYCLE_UNIT / 2;
		pcadjust = 0;
	}
	m68k_setpci_j(oldpc + 4);
	get_word_000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		pcoffset += pcadjust;
		exception2_fetch_opcode(opcode, 0, pcoffset);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	if (!cctrue(14)) {
		m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
	}
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 10 * CYCLE_UNIT / 2 + count_cycles;
}
/* 10 (2/0) */
/* 4 0,0 B */

/* Scc.B (An) (GT) */
uae_u32 REGPARAM2 op_5ed0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 10; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	regs.ir = regs.irc;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int val = cctrue(14) ? 0xff : 0x00;
	put_byte_000(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 10 * CYCLE_UNIT / 2 + count_cycles;
}
/* 10 (1/1) */
/* 2 0,0   */

/* Scc.B (An)+ (GT) */
uae_u32 REGPARAM2 op_5ed8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
	regs.ir = regs.irc;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int val = cctrue(14) ? 0xff : 0x00;
	put_byte_000(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (1/1) */
/* 2 0,0   */

/* Scc.B -(An) (GT) */
uae_u32 REGPARAM2 op_5ee0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
	m68k_areg(regs, srcreg) = srca;
	regs.ir = regs.irc;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int val = cctrue(14) ? 0xff : 0x00;
	put_byte_000(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (1/1) */
/* 2 0,0   */

/* Scc.B (d16,An) (GT) */
uae_u32 REGPARAM2 op_5ee8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int val = cctrue(14) ? 0xff : 0x00;
	put_byte_000(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (2/1) */
/* 4 0,0   */

/* Scc.B (d8,An,Xn) (GT) */
uae_u32 REGPARAM2 op_5ef0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int val = cctrue(14) ? 0xff : 0x00;
	put_byte_000(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (2/1) */
/* 4 4,0   */

/* Scc.B (xxx).W (GT) */
uae_u32 REGPARAM2 op_5ef8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 59;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int val = cctrue(14) ? 0xff : 0x00;
	put_byte_000(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (2/1) */
/* 4 0,0   */

/* Scc.B (xxx).L (GT) */
uae_u32 REGPARAM2 op_5ef9_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 59;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	srca |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int val = cctrue(14) ? 0xff : 0x00;
	put_byte_000(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 6 0,0   */

/* Scc.B Dn (LE) */
uae_u32 REGPARAM2 op_5fc0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 4;  
	int val = cctrue(15) ? 0xff : 0x00;
	if (!val) {
		m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff);
	}
	regs.ir = regs.irc;
	if (!val)
	opcode = regs.ir;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if(!val && regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff);
	count_cycles += ((val ? 2 : 0)) * CYCLE_UNIT / 2;
	m68k_incpci(2);
	return 4 * CYCLE_UNIT / 2 + count_cycles;
}
/* 4+ (1/0) */
/* 2 0,0   */

/* DBcc.W Dn,#<data>.W (LE) */
uae_u32 REGPARAM2 op_5fc8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 58;
	CurrentInstrCycles = 10; 
	int pcadjust = -2;
	uae_s16 src = m68k_dreg(regs, srcreg);
	uae_s16 offs = regs.irc;
	int was_loop_mode = regs.loop_mode;
	regs.loop_mode = 0;
	uaecptr oldpc = m68k_getpci();
	if (!cctrue(15)) {
		m68k_incpci((uae_s32)offs + 2);
		if (offs & 1) {
			get_word_000_prefetch(-1);
			exception3_read_prefetch(opcode, m68k_getpci());
			return 2 * CYCLE_UNIT / 2 + count_cycles;
		}
		if(offs == -4 && !regs.t1 && loop_mode_table[regs.ird]) {
			if(!was_loop_mode) {
				uae_u16 irc = regs.irc;
				count_cycles += 4 * CYCLE_UNIT / 2;
				get_word_000_prefetch(0);
				if(hardware_bus_error) {
					int pcoffset = 0;
					exception2_fetch_opcode(opcode, 0, 0);
					return 2 * CYCLE_UNIT / 2 + count_cycles;
				}
				count_cycles += 4 * CYCLE_UNIT / 2;
				get_word_000_prefetch(2);
				if(hardware_bus_error) {
					int pcoffset = 0;
					exception2_fetch_opcode(opcode, 2, 0);
					return 2 * CYCLE_UNIT / 2 + count_cycles;
				}
				regs.irc = irc;
			} else {
				count_cycles += 2 * CYCLE_UNIT / 2;
			}
			regs.loop_mode = 1;
			src = m68k_dreg(regs, srcreg);
			m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
			if (src) {
				count_cycles += loop_mode_table[regs.ird](regs.ird);
				 // quick exit if condition false and count expired
				if (!cctrue(15) && (m68k_dreg(regs, srcreg) & 0xffff) == 0) {
					m68k_dreg(regs, srcreg) |= 0xffff;
					 // loop exit: add possible extra cycle(s)
					if(regs.loop_mode >> 16) {
						count_cycles += (regs.loop_mode >> 16) * CYCLE_UNIT / 2;
					}
					regs.loop_mode = 0;
					m68k_setpci_j(oldpc + 4);
					get_word_000_prefetch(0);
					if(hardware_bus_error) {
						int pcoffset = 0;
						m68k_setpci_j(oldpc + 2);
						exception2_fetch_opcode(opcode, 0, pcoffset);
						return 4 * CYCLE_UNIT / 2 + count_cycles;
					}
					regs.ir = regs.irc;
					opcode = regs.ir;
					get_word_000_prefetch(2);
					if(hardware_bus_error) {
						int pcoffset = 0;
						m68k_setpci_j(oldpc + 2);
						exception2_fetch_opcode(opcode, 2, pcoffset);
						return 8 * CYCLE_UNIT / 2 + count_cycles;
					}
					return 8 * CYCLE_UNIT / 2 + count_cycles;
				}
				 // loop continue: add possible extra cycle(s)
				if(regs.loop_mode & 0xfffe) {
					count_cycles += (regs.loop_mode & 0xfffe) * CYCLE_UNIT / 2;
				}
				m68k_setpci_j(oldpc);
				return 2 * CYCLE_UNIT / 2 + count_cycles;
			}
			regs.loop_mode = 0;
			m68k_setpci_j(oldpc + 4);
			get_word_000_prefetch(0);
			if(hardware_bus_error) {
				int pcoffset = 0;
				m68k_setpci_j(oldpc + 2);
				exception2_fetch_opcode(opcode, 0, pcoffset);
				return 16 * CYCLE_UNIT / 2 + count_cycles;
			}
			regs.ir = regs.irc;
			opcode = regs.ir;
			get_word_000_prefetch(2);
			if(hardware_bus_error) {
				int pcoffset = 0;
				m68k_setpci_j(oldpc + 2);
				exception2_fetch_opcode(opcode, 2, pcoffset);
				return 20 * CYCLE_UNIT / 2 + count_cycles;
			}
			return 8 * CYCLE_UNIT / 2 + count_cycles;
		}
		get_word_000_prefetch(0);
		if(hardware_bus_error) {
			int pcoffset = 0;
			pcoffset = oldpc - m68k_getpci() + 4;
			exception2_fetch_opcode(opcode, 0, pcoffset);
			return 6 * CYCLE_UNIT / 2 + count_cycles;
		}
		if (src) {
			m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
			regs.ir = regs.irc;
			opcode = regs.ir;
			get_word_000_prefetch(2);
			if(hardware_bus_error) {
				int pcoffset = 0;
				exception2_fetch_opcode(opcode, 2, 0);
				return 6 * CYCLE_UNIT / 2 + count_cycles;
			}
			return 10 * CYCLE_UNIT / 2 + count_cycles;
		}
		count_cycles += 6 * CYCLE_UNIT / 2;
		pcadjust = 0;
	}
	m68k_setpci_j(oldpc + 4);
	get_word_000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		pcoffset += pcadjust;
		exception2_fetch_opcode(opcode, 0, pcoffset);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	if (!cctrue(15)) {
		m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
	}
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 10 * CYCLE_UNIT / 2 + count_cycles;
}
/* 10 (2/0) */
/* 4 0,0 B */

/* Scc.B (An) (LE) */
uae_u32 REGPARAM2 op_5fd0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 10; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	regs.ir = regs.irc;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int val = cctrue(15) ? 0xff : 0x00;
	put_byte_000(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 10 * CYCLE_UNIT / 2 + count_cycles;
}
/* 10 (1/1) */
/* 2 0,0   */

/* Scc.B (An)+ (LE) */
uae_u32 REGPARAM2 op_5fd8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
	regs.ir = regs.irc;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int val = cctrue(15) ? 0xff : 0x00;
	put_byte_000(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (1/1) */
/* 2 0,0   */

/* Scc.B -(An) (LE) */
uae_u32 REGPARAM2 op_5fe0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
	m68k_areg(regs, srcreg) = srca;
	regs.ir = regs.irc;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int val = cctrue(15) ? 0xff : 0x00;
	put_byte_000(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (1/1) */
/* 2 0,0   */

/* Scc.B (d16,An) (LE) */
uae_u32 REGPARAM2 op_5fe8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int val = cctrue(15) ? 0xff : 0x00;
	put_byte_000(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (2/1) */
/* 4 0,0   */

/* Scc.B (d8,An,Xn) (LE) */
uae_u32 REGPARAM2 op_5ff0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int val = cctrue(15) ? 0xff : 0x00;
	put_byte_000(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (2/1) */
/* 4 4,0   */

/* Scc.B (xxx).W (LE) */
uae_u32 REGPARAM2 op_5ff8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 59;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int val = cctrue(15) ? 0xff : 0x00;
	put_byte_000(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (2/1) */
/* 4 0,0   */

/* Scc.B (xxx).L (LE) */
uae_u32 REGPARAM2 op_5ff9_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 59;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	srca |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int val = cctrue(15) ? 0xff : 0x00;
	put_byte_000(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 6 0,0   */

/* Bcc.W #<data>.W (T) */
uae_u32 REGPARAM2 op_6000_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 55;
	CurrentInstrCycles = 12; 
	uaecptr oldpc = m68k_getpci();
	uae_s16 src = regs.irc;
	if (cctrue(0)) {
		if (src & 1) {
			uaecptr oldpc = m68k_getpci();
			uae_u16 rb = regs.irc;
			m68k_incpci(((uae_s32)src + 2) & ~1);
			get_word_000_prefetch(0);
			m68k_setpci_j(oldpc);
			uaecptr newpc = m68k_getpci() + (uae_s32)src + 2;
			m68k_incpci(2);
			regs.read_buffer = rb;
			exception3_read_prefetch(opcode, newpc);
			return 2 * CYCLE_UNIT / 2 + count_cycles;
		}
		m68k_incpci((uae_s32)src + 2);
		int pcadjust = oldpc - m68k_getpci() + 2;
		get_word_000_prefetch(0);
		if(hardware_bus_error) {
			int pcoffset = 0;
			pcoffset += pcadjust;
			exception2_fetch_opcode(opcode, 0, pcoffset);
			return 6 * CYCLE_UNIT / 2 + count_cycles;
		}
		regs.ir = regs.irc;
		opcode = regs.ir;
		get_word_000_prefetch(2);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 2, pcoffset);
			return 10 * CYCLE_UNIT / 2 + count_cycles;
		}
		return 10 * CYCLE_UNIT / 2;
	}
	m68k_incpci(4);
	get_word_000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (2/0) */
/* 4 0,0 B */

/* BccQ.B #<data> (T) */
uae_u32 REGPARAM2 op_6001_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (uae_s32)(uae_s8)(real_opcode & 255);
	OpcodeFamily = 55;
	CurrentInstrCycles = 6;  
	uaecptr oldpc = m68k_getpci();
	uae_u32 src = srcreg;
	if (cctrue(0)) {
		if (src & 1) {
			uaecptr oldpc = m68k_getpci();
			uae_u16 rb = regs.irc;
			m68k_incpci(((uae_s32)src + 2) & ~1);
			get_word_000_prefetch(0);
			m68k_setpci_j(oldpc);
			uaecptr newpc = m68k_getpci() + (uae_s32)src + 2;
			m68k_incpci(2);
			regs.read_buffer = rb;
			exception3_read_prefetch(opcode, newpc);
			return 2 * CYCLE_UNIT / 2 + count_cycles;
		}
		m68k_incpci((uae_s32)src + 2);
		int pcadjust = oldpc - m68k_getpci() + 2;
		get_word_000_prefetch(0);
		if(hardware_bus_error) {
			int pcoffset = 0;
			pcoffset += pcadjust;
			exception2_fetch_opcode(opcode, 0, pcoffset);
			return 6 * CYCLE_UNIT / 2 + count_cycles;
		}
		regs.ir = regs.irc;
		opcode = regs.ir;
		get_word_000_prefetch(2);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 2, pcoffset);
			return 10 * CYCLE_UNIT / 2 + count_cycles;
		}
		return 10 * CYCLE_UNIT / 2;
	}
	m68k_incpci(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 6 * CYCLE_UNIT / 2 + count_cycles;
}
/* 6 (1/0) */
/* 2 0,0 B */

/* Bcc.L #<data>.L (T) */
uae_u32 REGPARAM2 op_60ff_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 55;
	CurrentInstrCycles = 8;  
	uaecptr oldpc = m68k_getpci();
	if (cctrue(0)) {
		exception3_read_prefetch(opcode, m68k_getpci() + 1);
		return 2 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8 (1/0) */
/* 2 0,0   */

/* BSR.W #<data>.W */
uae_u32 REGPARAM2 op_6100_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 54;
	CurrentInstrCycles = 18; 
	uae_s32 s;
	uae_s16 src = regs.irc;
	s = (uae_s32)src + 2;
	uaecptr oldpc = m68k_getpci();
	uaecptr nextpc = oldpc + 4;
	if (m68k_areg(regs, 7) & 1) {
		m68k_incpci(2);
		exception3_write_access(opcode, oldpc + s, sz_word, oldpc, 1);
		return 2 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (s & 1) {
		m68k_incpci(2);
		exception3_read_prefetch_only(opcode, oldpc + s);
		return 2 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, 7) -= 4;
	uaecptr dsta = m68k_areg(regs, 7);
	put_word_000(dsta, nextpc >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		exception2_write(opcode, dsta + 0, 0x1, nextpc >> 16, 1);
		return 2 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta + 2, nextpc);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		exception2_write(opcode, dsta + 2, 0x1, nextpc, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(s);
	#ifdef DEBUGGER
	if (debugmem_trace) {
		branch_stack_push(oldpc, nextpc);
	}
	#endif
	get_word_000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (2/2) */
/* 4 0,0 B */

/* BSRQ.B #<data> */
uae_u32 REGPARAM2 op_6101_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (uae_s32)(uae_s8)(real_opcode & 255);
	OpcodeFamily = 54;
	CurrentInstrCycles = 18; 
	uae_s32 s;
	uae_u32 src = srcreg;
	s = (uae_s32)src + 2;
	uaecptr oldpc = m68k_getpci();
	uaecptr nextpc = oldpc + 2;
	if (m68k_areg(regs, 7) & 1) {
		m68k_incpci(2);
		exception3_write_access(opcode, oldpc + s, sz_word, oldpc, 1);
		return 2 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (s & 1) {
		m68k_incpci(2);
		exception3_read_prefetch_only(opcode, oldpc + s);
		return 2 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, 7) -= 4;
	uaecptr dsta = m68k_areg(regs, 7);
	put_word_000(dsta, nextpc >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		exception2_write(opcode, dsta + 0, 0x1, nextpc >> 16, 1);
		return 2 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta + 2, nextpc);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		exception2_write(opcode, dsta + 2, 0x1, nextpc, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(s);
	#ifdef DEBUGGER
	if (debugmem_trace) {
		branch_stack_push(oldpc, nextpc);
	}
	#endif
	get_word_000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (2/2) */
/* 2 0,0 B */

/* BSR.L #<data>.L */
uae_u32 REGPARAM2 op_61ff_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 54;
	CurrentInstrCycles = 18; 
	uae_s32 s;
	uae_u32 src = 0xffffffff;
	s = (uae_s32)src + 2;
	uaecptr oldpc = m68k_getpci();
	uaecptr nextpc = oldpc + 2;
	if (m68k_areg(regs, 7) & 1) {
		m68k_incpci(2);
		exception3_write_access(opcode, oldpc + s, sz_word, oldpc, 1);
		return 2 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (s & 1) {
		m68k_incpci(2);
		exception3_read_prefetch_only(opcode, oldpc + s);
		return 2 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, 7) -= 4;
	uaecptr dsta = m68k_areg(regs, 7);
	put_word_000(dsta, nextpc >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		exception2_write(opcode, dsta + 0, 0x1, nextpc >> 16, 1);
		return 2 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta + 2, nextpc);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		exception2_write(opcode, dsta + 2, 0x1, nextpc, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(s);
	#ifdef DEBUGGER
	if (debugmem_trace) {
		branch_stack_push(oldpc, nextpc);
	}
	#endif
	get_word_000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (2/2) */
/* 2 0,0 B */

/* Bcc.W #<data>.W (HI) */
uae_u32 REGPARAM2 op_6200_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 55;
	CurrentInstrCycles = 12; 
	uaecptr oldpc = m68k_getpci();
	uae_s16 src = regs.irc;
	if (cctrue(2)) {
		if (src & 1) {
			uaecptr oldpc = m68k_getpci();
			uae_u16 rb = regs.irc;
			m68k_incpci(((uae_s32)src + 2) & ~1);
			get_word_000_prefetch(0);
			m68k_setpci_j(oldpc);
			uaecptr newpc = m68k_getpci() + (uae_s32)src + 2;
			m68k_incpci(2);
			regs.read_buffer = rb;
			exception3_read_prefetch(opcode, newpc);
			return 2 * CYCLE_UNIT / 2 + count_cycles;
		}
		m68k_incpci((uae_s32)src + 2);
		int pcadjust = oldpc - m68k_getpci() + 2;
		get_word_000_prefetch(0);
		if(hardware_bus_error) {
			int pcoffset = 0;
			pcoffset += pcadjust;
			exception2_fetch_opcode(opcode, 0, pcoffset);
			return 6 * CYCLE_UNIT / 2 + count_cycles;
		}
		regs.ir = regs.irc;
		opcode = regs.ir;
		get_word_000_prefetch(2);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 2, pcoffset);
			return 10 * CYCLE_UNIT / 2 + count_cycles;
		}
		return 10 * CYCLE_UNIT / 2;
	}
	m68k_incpci(4);
	get_word_000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (2/0) */
/* 4 0,0 B */

/* BccQ.B #<data> (HI) */
uae_u32 REGPARAM2 op_6201_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (uae_s32)(uae_s8)(real_opcode & 255);
	OpcodeFamily = 55;
	CurrentInstrCycles = 6;  
	uaecptr oldpc = m68k_getpci();
	uae_u32 src = srcreg;
	if (cctrue(2)) {
		if (src & 1) {
			uaecptr oldpc = m68k_getpci();
			uae_u16 rb = regs.irc;
			m68k_incpci(((uae_s32)src + 2) & ~1);
			get_word_000_prefetch(0);
			m68k_setpci_j(oldpc);
			uaecptr newpc = m68k_getpci() + (uae_s32)src + 2;
			m68k_incpci(2);
			regs.read_buffer = rb;
			exception3_read_prefetch(opcode, newpc);
			return 2 * CYCLE_UNIT / 2 + count_cycles;
		}
		m68k_incpci((uae_s32)src + 2);
		int pcadjust = oldpc - m68k_getpci() + 2;
		get_word_000_prefetch(0);
		if(hardware_bus_error) {
			int pcoffset = 0;
			pcoffset += pcadjust;
			exception2_fetch_opcode(opcode, 0, pcoffset);
			return 6 * CYCLE_UNIT / 2 + count_cycles;
		}
		regs.ir = regs.irc;
		opcode = regs.ir;
		get_word_000_prefetch(2);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 2, pcoffset);
			return 10 * CYCLE_UNIT / 2 + count_cycles;
		}
		return 10 * CYCLE_UNIT / 2;
	}
	m68k_incpci(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 6 * CYCLE_UNIT / 2 + count_cycles;
}
/* 6 (1/0) */
/* 2 0,0 B */

/* Bcc.L #<data>.L (HI) */
uae_u32 REGPARAM2 op_62ff_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 55;
	CurrentInstrCycles = 8;  
	uaecptr oldpc = m68k_getpci();
	if (cctrue(2)) {
		exception3_read_prefetch(opcode, m68k_getpci() + 1);
		return 2 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8 (1/0) */
/* 2 0,0   */

/* Bcc.W #<data>.W (LS) */
uae_u32 REGPARAM2 op_6300_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 55;
	CurrentInstrCycles = 12; 
	uaecptr oldpc = m68k_getpci();
	uae_s16 src = regs.irc;
	if (cctrue(3)) {
		if (src & 1) {
			uaecptr oldpc = m68k_getpci();
			uae_u16 rb = regs.irc;
			m68k_incpci(((uae_s32)src + 2) & ~1);
			get_word_000_prefetch(0);
			m68k_setpci_j(oldpc);
			uaecptr newpc = m68k_getpci() + (uae_s32)src + 2;
			m68k_incpci(2);
			regs.read_buffer = rb;
			exception3_read_prefetch(opcode, newpc);
			return 2 * CYCLE_UNIT / 2 + count_cycles;
		}
		m68k_incpci((uae_s32)src + 2);
		int pcadjust = oldpc - m68k_getpci() + 2;
		get_word_000_prefetch(0);
		if(hardware_bus_error) {
			int pcoffset = 0;
			pcoffset += pcadjust;
			exception2_fetch_opcode(opcode, 0, pcoffset);
			return 6 * CYCLE_UNIT / 2 + count_cycles;
		}
		regs.ir = regs.irc;
		opcode = regs.ir;
		get_word_000_prefetch(2);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 2, pcoffset);
			return 10 * CYCLE_UNIT / 2 + count_cycles;
		}
		return 10 * CYCLE_UNIT / 2;
	}
	m68k_incpci(4);
	get_word_000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (2/0) */
/* 4 0,0 B */

/* BccQ.B #<data> (LS) */
uae_u32 REGPARAM2 op_6301_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (uae_s32)(uae_s8)(real_opcode & 255);
	OpcodeFamily = 55;
	CurrentInstrCycles = 6;  
	uaecptr oldpc = m68k_getpci();
	uae_u32 src = srcreg;
	if (cctrue(3)) {
		if (src & 1) {
			uaecptr oldpc = m68k_getpci();
			uae_u16 rb = regs.irc;
			m68k_incpci(((uae_s32)src + 2) & ~1);
			get_word_000_prefetch(0);
			m68k_setpci_j(oldpc);
			uaecptr newpc = m68k_getpci() + (uae_s32)src + 2;
			m68k_incpci(2);
			regs.read_buffer = rb;
			exception3_read_prefetch(opcode, newpc);
			return 2 * CYCLE_UNIT / 2 + count_cycles;
		}
		m68k_incpci((uae_s32)src + 2);
		int pcadjust = oldpc - m68k_getpci() + 2;
		get_word_000_prefetch(0);
		if(hardware_bus_error) {
			int pcoffset = 0;
			pcoffset += pcadjust;
			exception2_fetch_opcode(opcode, 0, pcoffset);
			return 6 * CYCLE_UNIT / 2 + count_cycles;
		}
		regs.ir = regs.irc;
		opcode = regs.ir;
		get_word_000_prefetch(2);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 2, pcoffset);
			return 10 * CYCLE_UNIT / 2 + count_cycles;
		}
		return 10 * CYCLE_UNIT / 2;
	}
	m68k_incpci(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 6 * CYCLE_UNIT / 2 + count_cycles;
}
/* 6 (1/0) */
/* 2 0,0 B */

/* Bcc.L #<data>.L (LS) */
uae_u32 REGPARAM2 op_63ff_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 55;
	CurrentInstrCycles = 8;  
	uaecptr oldpc = m68k_getpci();
	if (cctrue(3)) {
		exception3_read_prefetch(opcode, m68k_getpci() + 1);
		return 2 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8 (1/0) */
/* 2 0,0   */

/* Bcc.W #<data>.W (CC) */
uae_u32 REGPARAM2 op_6400_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 55;
	CurrentInstrCycles = 12; 
	uaecptr oldpc = m68k_getpci();
	uae_s16 src = regs.irc;
	if (cctrue(4)) {
		if (src & 1) {
			uaecptr oldpc = m68k_getpci();
			uae_u16 rb = regs.irc;
			m68k_incpci(((uae_s32)src + 2) & ~1);
			get_word_000_prefetch(0);
			m68k_setpci_j(oldpc);
			uaecptr newpc = m68k_getpci() + (uae_s32)src + 2;
			m68k_incpci(2);
			regs.read_buffer = rb;
			exception3_read_prefetch(opcode, newpc);
			return 2 * CYCLE_UNIT / 2 + count_cycles;
		}
		m68k_incpci((uae_s32)src + 2);
		int pcadjust = oldpc - m68k_getpci() + 2;
		get_word_000_prefetch(0);
		if(hardware_bus_error) {
			int pcoffset = 0;
			pcoffset += pcadjust;
			exception2_fetch_opcode(opcode, 0, pcoffset);
			return 6 * CYCLE_UNIT / 2 + count_cycles;
		}
		regs.ir = regs.irc;
		opcode = regs.ir;
		get_word_000_prefetch(2);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 2, pcoffset);
			return 10 * CYCLE_UNIT / 2 + count_cycles;
		}
		return 10 * CYCLE_UNIT / 2;
	}
	m68k_incpci(4);
	get_word_000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (2/0) */
/* 4 0,0 B */

/* BccQ.B #<data> (CC) */
uae_u32 REGPARAM2 op_6401_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (uae_s32)(uae_s8)(real_opcode & 255);
	OpcodeFamily = 55;
	CurrentInstrCycles = 6;  
	uaecptr oldpc = m68k_getpci();
	uae_u32 src = srcreg;
	if (cctrue(4)) {
		if (src & 1) {
			uaecptr oldpc = m68k_getpci();
			uae_u16 rb = regs.irc;
			m68k_incpci(((uae_s32)src + 2) & ~1);
			get_word_000_prefetch(0);
			m68k_setpci_j(oldpc);
			uaecptr newpc = m68k_getpci() + (uae_s32)src + 2;
			m68k_incpci(2);
			regs.read_buffer = rb;
			exception3_read_prefetch(opcode, newpc);
			return 2 * CYCLE_UNIT / 2 + count_cycles;
		}
		m68k_incpci((uae_s32)src + 2);
		int pcadjust = oldpc - m68k_getpci() + 2;
		get_word_000_prefetch(0);
		if(hardware_bus_error) {
			int pcoffset = 0;
			pcoffset += pcadjust;
			exception2_fetch_opcode(opcode, 0, pcoffset);
			return 6 * CYCLE_UNIT / 2 + count_cycles;
		}
		regs.ir = regs.irc;
		opcode = regs.ir;
		get_word_000_prefetch(2);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 2, pcoffset);
			return 10 * CYCLE_UNIT / 2 + count_cycles;
		}
		return 10 * CYCLE_UNIT / 2;
	}
	m68k_incpci(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 6 * CYCLE_UNIT / 2 + count_cycles;
}
/* 6 (1/0) */
/* 2 0,0 B */

/* Bcc.L #<data>.L (CC) */
uae_u32 REGPARAM2 op_64ff_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 55;
	CurrentInstrCycles = 8;  
	uaecptr oldpc = m68k_getpci();
	if (cctrue(4)) {
		exception3_read_prefetch(opcode, m68k_getpci() + 1);
		return 2 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8 (1/0) */
/* 2 0,0   */

/* Bcc.W #<data>.W (CS) */
uae_u32 REGPARAM2 op_6500_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 55;
	CurrentInstrCycles = 12; 
	uaecptr oldpc = m68k_getpci();
	uae_s16 src = regs.irc;
	if (cctrue(5)) {
		if (src & 1) {
			uaecptr oldpc = m68k_getpci();
			uae_u16 rb = regs.irc;
			m68k_incpci(((uae_s32)src + 2) & ~1);
			get_word_000_prefetch(0);
			m68k_setpci_j(oldpc);
			uaecptr newpc = m68k_getpci() + (uae_s32)src + 2;
			m68k_incpci(2);
			regs.read_buffer = rb;
			exception3_read_prefetch(opcode, newpc);
			return 2 * CYCLE_UNIT / 2 + count_cycles;
		}
		m68k_incpci((uae_s32)src + 2);
		int pcadjust = oldpc - m68k_getpci() + 2;
		get_word_000_prefetch(0);
		if(hardware_bus_error) {
			int pcoffset = 0;
			pcoffset += pcadjust;
			exception2_fetch_opcode(opcode, 0, pcoffset);
			return 6 * CYCLE_UNIT / 2 + count_cycles;
		}
		regs.ir = regs.irc;
		opcode = regs.ir;
		get_word_000_prefetch(2);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 2, pcoffset);
			return 10 * CYCLE_UNIT / 2 + count_cycles;
		}
		return 10 * CYCLE_UNIT / 2;
	}
	m68k_incpci(4);
	get_word_000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (2/0) */
/* 4 0,0 B */

/* BccQ.B #<data> (CS) */
uae_u32 REGPARAM2 op_6501_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (uae_s32)(uae_s8)(real_opcode & 255);
	OpcodeFamily = 55;
	CurrentInstrCycles = 6;  
	uaecptr oldpc = m68k_getpci();
	uae_u32 src = srcreg;
	if (cctrue(5)) {
		if (src & 1) {
			uaecptr oldpc = m68k_getpci();
			uae_u16 rb = regs.irc;
			m68k_incpci(((uae_s32)src + 2) & ~1);
			get_word_000_prefetch(0);
			m68k_setpci_j(oldpc);
			uaecptr newpc = m68k_getpci() + (uae_s32)src + 2;
			m68k_incpci(2);
			regs.read_buffer = rb;
			exception3_read_prefetch(opcode, newpc);
			return 2 * CYCLE_UNIT / 2 + count_cycles;
		}
		m68k_incpci((uae_s32)src + 2);
		int pcadjust = oldpc - m68k_getpci() + 2;
		get_word_000_prefetch(0);
		if(hardware_bus_error) {
			int pcoffset = 0;
			pcoffset += pcadjust;
			exception2_fetch_opcode(opcode, 0, pcoffset);
			return 6 * CYCLE_UNIT / 2 + count_cycles;
		}
		regs.ir = regs.irc;
		opcode = regs.ir;
		get_word_000_prefetch(2);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 2, pcoffset);
			return 10 * CYCLE_UNIT / 2 + count_cycles;
		}
		return 10 * CYCLE_UNIT / 2;
	}
	m68k_incpci(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 6 * CYCLE_UNIT / 2 + count_cycles;
}
/* 6 (1/0) */
/* 2 0,0 B */

/* Bcc.L #<data>.L (CS) */
uae_u32 REGPARAM2 op_65ff_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 55;
	CurrentInstrCycles = 8;  
	uaecptr oldpc = m68k_getpci();
	if (cctrue(5)) {
		exception3_read_prefetch(opcode, m68k_getpci() + 1);
		return 2 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8 (1/0) */
/* 2 0,0   */

/* Bcc.W #<data>.W (NE) */
uae_u32 REGPARAM2 op_6600_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 55;
	CurrentInstrCycles = 12; 
	uaecptr oldpc = m68k_getpci();
	uae_s16 src = regs.irc;
	if (cctrue(6)) {
		if (src & 1) {
			uaecptr oldpc = m68k_getpci();
			uae_u16 rb = regs.irc;
			m68k_incpci(((uae_s32)src + 2) & ~1);
			get_word_000_prefetch(0);
			m68k_setpci_j(oldpc);
			uaecptr newpc = m68k_getpci() + (uae_s32)src + 2;
			m68k_incpci(2);
			regs.read_buffer = rb;
			exception3_read_prefetch(opcode, newpc);
			return 2 * CYCLE_UNIT / 2 + count_cycles;
		}
		m68k_incpci((uae_s32)src + 2);
		int pcadjust = oldpc - m68k_getpci() + 2;
		get_word_000_prefetch(0);
		if(hardware_bus_error) {
			int pcoffset = 0;
			pcoffset += pcadjust;
			exception2_fetch_opcode(opcode, 0, pcoffset);
			return 6 * CYCLE_UNIT / 2 + count_cycles;
		}
		regs.ir = regs.irc;
		opcode = regs.ir;
		get_word_000_prefetch(2);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 2, pcoffset);
			return 10 * CYCLE_UNIT / 2 + count_cycles;
		}
		return 10 * CYCLE_UNIT / 2;
	}
	m68k_incpci(4);
	get_word_000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (2/0) */
/* 4 0,0 B */

/* BccQ.B #<data> (NE) */
uae_u32 REGPARAM2 op_6601_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (uae_s32)(uae_s8)(real_opcode & 255);
	OpcodeFamily = 55;
	CurrentInstrCycles = 6;  
	uaecptr oldpc = m68k_getpci();
	uae_u32 src = srcreg;
	if (cctrue(6)) {
		if (src & 1) {
			uaecptr oldpc = m68k_getpci();
			uae_u16 rb = regs.irc;
			m68k_incpci(((uae_s32)src + 2) & ~1);
			get_word_000_prefetch(0);
			m68k_setpci_j(oldpc);
			uaecptr newpc = m68k_getpci() + (uae_s32)src + 2;
			m68k_incpci(2);
			regs.read_buffer = rb;
			exception3_read_prefetch(opcode, newpc);
			return 2 * CYCLE_UNIT / 2 + count_cycles;
		}
		m68k_incpci((uae_s32)src + 2);
		int pcadjust = oldpc - m68k_getpci() + 2;
		get_word_000_prefetch(0);
		if(hardware_bus_error) {
			int pcoffset = 0;
			pcoffset += pcadjust;
			exception2_fetch_opcode(opcode, 0, pcoffset);
			return 6 * CYCLE_UNIT / 2 + count_cycles;
		}
		regs.ir = regs.irc;
		opcode = regs.ir;
		get_word_000_prefetch(2);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 2, pcoffset);
			return 10 * CYCLE_UNIT / 2 + count_cycles;
		}
		return 10 * CYCLE_UNIT / 2;
	}
	m68k_incpci(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 6 * CYCLE_UNIT / 2 + count_cycles;
}
/* 6 (1/0) */
/* 2 0,0 B */

/* Bcc.L #<data>.L (NE) */
uae_u32 REGPARAM2 op_66ff_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 55;
	CurrentInstrCycles = 8;  
	uaecptr oldpc = m68k_getpci();
	if (cctrue(6)) {
		exception3_read_prefetch(opcode, m68k_getpci() + 1);
		return 2 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8 (1/0) */
/* 2 0,0   */

/* Bcc.W #<data>.W (EQ) */
uae_u32 REGPARAM2 op_6700_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 55;
	CurrentInstrCycles = 12; 
	uaecptr oldpc = m68k_getpci();
	uae_s16 src = regs.irc;
	if (cctrue(7)) {
		if (src & 1) {
			uaecptr oldpc = m68k_getpci();
			uae_u16 rb = regs.irc;
			m68k_incpci(((uae_s32)src + 2) & ~1);
			get_word_000_prefetch(0);
			m68k_setpci_j(oldpc);
			uaecptr newpc = m68k_getpci() + (uae_s32)src + 2;
			m68k_incpci(2);
			regs.read_buffer = rb;
			exception3_read_prefetch(opcode, newpc);
			return 2 * CYCLE_UNIT / 2 + count_cycles;
		}
		m68k_incpci((uae_s32)src + 2);
		int pcadjust = oldpc - m68k_getpci() + 2;
		get_word_000_prefetch(0);
		if(hardware_bus_error) {
			int pcoffset = 0;
			pcoffset += pcadjust;
			exception2_fetch_opcode(opcode, 0, pcoffset);
			return 6 * CYCLE_UNIT / 2 + count_cycles;
		}
		regs.ir = regs.irc;
		opcode = regs.ir;
		get_word_000_prefetch(2);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 2, pcoffset);
			return 10 * CYCLE_UNIT / 2 + count_cycles;
		}
		return 10 * CYCLE_UNIT / 2;
	}
	m68k_incpci(4);
	get_word_000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (2/0) */
/* 4 0,0 B */

/* BccQ.B #<data> (EQ) */
uae_u32 REGPARAM2 op_6701_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (uae_s32)(uae_s8)(real_opcode & 255);
	OpcodeFamily = 55;
	CurrentInstrCycles = 6;  
	uaecptr oldpc = m68k_getpci();
	uae_u32 src = srcreg;
	if (cctrue(7)) {
		if (src & 1) {
			uaecptr oldpc = m68k_getpci();
			uae_u16 rb = regs.irc;
			m68k_incpci(((uae_s32)src + 2) & ~1);
			get_word_000_prefetch(0);
			m68k_setpci_j(oldpc);
			uaecptr newpc = m68k_getpci() + (uae_s32)src + 2;
			m68k_incpci(2);
			regs.read_buffer = rb;
			exception3_read_prefetch(opcode, newpc);
			return 2 * CYCLE_UNIT / 2 + count_cycles;
		}
		m68k_incpci((uae_s32)src + 2);
		int pcadjust = oldpc - m68k_getpci() + 2;
		get_word_000_prefetch(0);
		if(hardware_bus_error) {
			int pcoffset = 0;
			pcoffset += pcadjust;
			exception2_fetch_opcode(opcode, 0, pcoffset);
			return 6 * CYCLE_UNIT / 2 + count_cycles;
		}
		regs.ir = regs.irc;
		opcode = regs.ir;
		get_word_000_prefetch(2);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 2, pcoffset);
			return 10 * CYCLE_UNIT / 2 + count_cycles;
		}
		return 10 * CYCLE_UNIT / 2;
	}
	m68k_incpci(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 6 * CYCLE_UNIT / 2 + count_cycles;
}
/* 6 (1/0) */
/* 2 0,0 B */

/* Bcc.L #<data>.L (EQ) */
uae_u32 REGPARAM2 op_67ff_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 55;
	CurrentInstrCycles = 8;  
	uaecptr oldpc = m68k_getpci();
	if (cctrue(7)) {
		exception3_read_prefetch(opcode, m68k_getpci() + 1);
		return 2 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8 (1/0) */
/* 2 0,0   */

/* Bcc.W #<data>.W (VC) */
uae_u32 REGPARAM2 op_6800_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 55;
	CurrentInstrCycles = 12; 
	uaecptr oldpc = m68k_getpci();
	uae_s16 src = regs.irc;
	if (cctrue(8)) {
		if (src & 1) {
			uaecptr oldpc = m68k_getpci();
			uae_u16 rb = regs.irc;
			m68k_incpci(((uae_s32)src + 2) & ~1);
			get_word_000_prefetch(0);
			m68k_setpci_j(oldpc);
			uaecptr newpc = m68k_getpci() + (uae_s32)src + 2;
			m68k_incpci(2);
			regs.read_buffer = rb;
			exception3_read_prefetch(opcode, newpc);
			return 2 * CYCLE_UNIT / 2 + count_cycles;
		}
		m68k_incpci((uae_s32)src + 2);
		int pcadjust = oldpc - m68k_getpci() + 2;
		get_word_000_prefetch(0);
		if(hardware_bus_error) {
			int pcoffset = 0;
			pcoffset += pcadjust;
			exception2_fetch_opcode(opcode, 0, pcoffset);
			return 6 * CYCLE_UNIT / 2 + count_cycles;
		}
		regs.ir = regs.irc;
		opcode = regs.ir;
		get_word_000_prefetch(2);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 2, pcoffset);
			return 10 * CYCLE_UNIT / 2 + count_cycles;
		}
		return 10 * CYCLE_UNIT / 2;
	}
	m68k_incpci(4);
	get_word_000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (2/0) */
/* 4 0,0 B */

/* BccQ.B #<data> (VC) */
uae_u32 REGPARAM2 op_6801_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (uae_s32)(uae_s8)(real_opcode & 255);
	OpcodeFamily = 55;
	CurrentInstrCycles = 6;  
	uaecptr oldpc = m68k_getpci();
	uae_u32 src = srcreg;
	if (cctrue(8)) {
		if (src & 1) {
			uaecptr oldpc = m68k_getpci();
			uae_u16 rb = regs.irc;
			m68k_incpci(((uae_s32)src + 2) & ~1);
			get_word_000_prefetch(0);
			m68k_setpci_j(oldpc);
			uaecptr newpc = m68k_getpci() + (uae_s32)src + 2;
			m68k_incpci(2);
			regs.read_buffer = rb;
			exception3_read_prefetch(opcode, newpc);
			return 2 * CYCLE_UNIT / 2 + count_cycles;
		}
		m68k_incpci((uae_s32)src + 2);
		int pcadjust = oldpc - m68k_getpci() + 2;
		get_word_000_prefetch(0);
		if(hardware_bus_error) {
			int pcoffset = 0;
			pcoffset += pcadjust;
			exception2_fetch_opcode(opcode, 0, pcoffset);
			return 6 * CYCLE_UNIT / 2 + count_cycles;
		}
		regs.ir = regs.irc;
		opcode = regs.ir;
		get_word_000_prefetch(2);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 2, pcoffset);
			return 10 * CYCLE_UNIT / 2 + count_cycles;
		}
		return 10 * CYCLE_UNIT / 2;
	}
	m68k_incpci(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 6 * CYCLE_UNIT / 2 + count_cycles;
}
/* 6 (1/0) */
/* 2 0,0 B */

/* Bcc.L #<data>.L (VC) */
uae_u32 REGPARAM2 op_68ff_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 55;
	CurrentInstrCycles = 8;  
	uaecptr oldpc = m68k_getpci();
	if (cctrue(8)) {
		exception3_read_prefetch(opcode, m68k_getpci() + 1);
		return 2 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8 (1/0) */
/* 2 0,0   */

/* Bcc.W #<data>.W (VS) */
uae_u32 REGPARAM2 op_6900_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 55;
	CurrentInstrCycles = 12; 
	uaecptr oldpc = m68k_getpci();
	uae_s16 src = regs.irc;
	if (cctrue(9)) {
		if (src & 1) {
			uaecptr oldpc = m68k_getpci();
			uae_u16 rb = regs.irc;
			m68k_incpci(((uae_s32)src + 2) & ~1);
			get_word_000_prefetch(0);
			m68k_setpci_j(oldpc);
			uaecptr newpc = m68k_getpci() + (uae_s32)src + 2;
			m68k_incpci(2);
			regs.read_buffer = rb;
			exception3_read_prefetch(opcode, newpc);
			return 2 * CYCLE_UNIT / 2 + count_cycles;
		}
		m68k_incpci((uae_s32)src + 2);
		int pcadjust = oldpc - m68k_getpci() + 2;
		get_word_000_prefetch(0);
		if(hardware_bus_error) {
			int pcoffset = 0;
			pcoffset += pcadjust;
			exception2_fetch_opcode(opcode, 0, pcoffset);
			return 6 * CYCLE_UNIT / 2 + count_cycles;
		}
		regs.ir = regs.irc;
		opcode = regs.ir;
		get_word_000_prefetch(2);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 2, pcoffset);
			return 10 * CYCLE_UNIT / 2 + count_cycles;
		}
		return 10 * CYCLE_UNIT / 2;
	}
	m68k_incpci(4);
	get_word_000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (2/0) */
/* 4 0,0 B */

/* BccQ.B #<data> (VS) */
uae_u32 REGPARAM2 op_6901_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (uae_s32)(uae_s8)(real_opcode & 255);
	OpcodeFamily = 55;
	CurrentInstrCycles = 6;  
	uaecptr oldpc = m68k_getpci();
	uae_u32 src = srcreg;
	if (cctrue(9)) {
		if (src & 1) {
			uaecptr oldpc = m68k_getpci();
			uae_u16 rb = regs.irc;
			m68k_incpci(((uae_s32)src + 2) & ~1);
			get_word_000_prefetch(0);
			m68k_setpci_j(oldpc);
			uaecptr newpc = m68k_getpci() + (uae_s32)src + 2;
			m68k_incpci(2);
			regs.read_buffer = rb;
			exception3_read_prefetch(opcode, newpc);
			return 2 * CYCLE_UNIT / 2 + count_cycles;
		}
		m68k_incpci((uae_s32)src + 2);
		int pcadjust = oldpc - m68k_getpci() + 2;
		get_word_000_prefetch(0);
		if(hardware_bus_error) {
			int pcoffset = 0;
			pcoffset += pcadjust;
			exception2_fetch_opcode(opcode, 0, pcoffset);
			return 6 * CYCLE_UNIT / 2 + count_cycles;
		}
		regs.ir = regs.irc;
		opcode = regs.ir;
		get_word_000_prefetch(2);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 2, pcoffset);
			return 10 * CYCLE_UNIT / 2 + count_cycles;
		}
		return 10 * CYCLE_UNIT / 2;
	}
	m68k_incpci(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 6 * CYCLE_UNIT / 2 + count_cycles;
}
/* 6 (1/0) */
/* 2 0,0 B */

/* Bcc.L #<data>.L (VS) */
uae_u32 REGPARAM2 op_69ff_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 55;
	CurrentInstrCycles = 8;  
	uaecptr oldpc = m68k_getpci();
	if (cctrue(9)) {
		exception3_read_prefetch(opcode, m68k_getpci() + 1);
		return 2 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8 (1/0) */
/* 2 0,0   */

/* Bcc.W #<data>.W (PL) */
uae_u32 REGPARAM2 op_6a00_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 55;
	CurrentInstrCycles = 12; 
	uaecptr oldpc = m68k_getpci();
	uae_s16 src = regs.irc;
	if (cctrue(10)) {
		if (src & 1) {
			uaecptr oldpc = m68k_getpci();
			uae_u16 rb = regs.irc;
			m68k_incpci(((uae_s32)src + 2) & ~1);
			get_word_000_prefetch(0);
			m68k_setpci_j(oldpc);
			uaecptr newpc = m68k_getpci() + (uae_s32)src + 2;
			m68k_incpci(2);
			regs.read_buffer = rb;
			exception3_read_prefetch(opcode, newpc);
			return 2 * CYCLE_UNIT / 2 + count_cycles;
		}
		m68k_incpci((uae_s32)src + 2);
		int pcadjust = oldpc - m68k_getpci() + 2;
		get_word_000_prefetch(0);
		if(hardware_bus_error) {
			int pcoffset = 0;
			pcoffset += pcadjust;
			exception2_fetch_opcode(opcode, 0, pcoffset);
			return 6 * CYCLE_UNIT / 2 + count_cycles;
		}
		regs.ir = regs.irc;
		opcode = regs.ir;
		get_word_000_prefetch(2);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 2, pcoffset);
			return 10 * CYCLE_UNIT / 2 + count_cycles;
		}
		return 10 * CYCLE_UNIT / 2;
	}
	m68k_incpci(4);
	get_word_000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (2/0) */
/* 4 0,0 B */

/* BccQ.B #<data> (PL) */
uae_u32 REGPARAM2 op_6a01_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (uae_s32)(uae_s8)(real_opcode & 255);
	OpcodeFamily = 55;
	CurrentInstrCycles = 6;  
	uaecptr oldpc = m68k_getpci();
	uae_u32 src = srcreg;
	if (cctrue(10)) {
		if (src & 1) {
			uaecptr oldpc = m68k_getpci();
			uae_u16 rb = regs.irc;
			m68k_incpci(((uae_s32)src + 2) & ~1);
			get_word_000_prefetch(0);
			m68k_setpci_j(oldpc);
			uaecptr newpc = m68k_getpci() + (uae_s32)src + 2;
			m68k_incpci(2);
			regs.read_buffer = rb;
			exception3_read_prefetch(opcode, newpc);
			return 2 * CYCLE_UNIT / 2 + count_cycles;
		}
		m68k_incpci((uae_s32)src + 2);
		int pcadjust = oldpc - m68k_getpci() + 2;
		get_word_000_prefetch(0);
		if(hardware_bus_error) {
			int pcoffset = 0;
			pcoffset += pcadjust;
			exception2_fetch_opcode(opcode, 0, pcoffset);
			return 6 * CYCLE_UNIT / 2 + count_cycles;
		}
		regs.ir = regs.irc;
		opcode = regs.ir;
		get_word_000_prefetch(2);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 2, pcoffset);
			return 10 * CYCLE_UNIT / 2 + count_cycles;
		}
		return 10 * CYCLE_UNIT / 2;
	}
	m68k_incpci(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 6 * CYCLE_UNIT / 2 + count_cycles;
}
/* 6 (1/0) */
/* 2 0,0 B */

/* Bcc.L #<data>.L (PL) */
uae_u32 REGPARAM2 op_6aff_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 55;
	CurrentInstrCycles = 8;  
	uaecptr oldpc = m68k_getpci();
	if (cctrue(10)) {
		exception3_read_prefetch(opcode, m68k_getpci() + 1);
		return 2 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8 (1/0) */
/* 2 0,0   */

/* Bcc.W #<data>.W (MI) */
uae_u32 REGPARAM2 op_6b00_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 55;
	CurrentInstrCycles = 12; 
	uaecptr oldpc = m68k_getpci();
	uae_s16 src = regs.irc;
	if (cctrue(11)) {
		if (src & 1) {
			uaecptr oldpc = m68k_getpci();
			uae_u16 rb = regs.irc;
			m68k_incpci(((uae_s32)src + 2) & ~1);
			get_word_000_prefetch(0);
			m68k_setpci_j(oldpc);
			uaecptr newpc = m68k_getpci() + (uae_s32)src + 2;
			m68k_incpci(2);
			regs.read_buffer = rb;
			exception3_read_prefetch(opcode, newpc);
			return 2 * CYCLE_UNIT / 2 + count_cycles;
		}
		m68k_incpci((uae_s32)src + 2);
		int pcadjust = oldpc - m68k_getpci() + 2;
		get_word_000_prefetch(0);
		if(hardware_bus_error) {
			int pcoffset = 0;
			pcoffset += pcadjust;
			exception2_fetch_opcode(opcode, 0, pcoffset);
			return 6 * CYCLE_UNIT / 2 + count_cycles;
		}
		regs.ir = regs.irc;
		opcode = regs.ir;
		get_word_000_prefetch(2);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 2, pcoffset);
			return 10 * CYCLE_UNIT / 2 + count_cycles;
		}
		return 10 * CYCLE_UNIT / 2;
	}
	m68k_incpci(4);
	get_word_000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (2/0) */
/* 4 0,0 B */

/* BccQ.B #<data> (MI) */
uae_u32 REGPARAM2 op_6b01_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (uae_s32)(uae_s8)(real_opcode & 255);
	OpcodeFamily = 55;
	CurrentInstrCycles = 6;  
	uaecptr oldpc = m68k_getpci();
	uae_u32 src = srcreg;
	if (cctrue(11)) {
		if (src & 1) {
			uaecptr oldpc = m68k_getpci();
			uae_u16 rb = regs.irc;
			m68k_incpci(((uae_s32)src + 2) & ~1);
			get_word_000_prefetch(0);
			m68k_setpci_j(oldpc);
			uaecptr newpc = m68k_getpci() + (uae_s32)src + 2;
			m68k_incpci(2);
			regs.read_buffer = rb;
			exception3_read_prefetch(opcode, newpc);
			return 2 * CYCLE_UNIT / 2 + count_cycles;
		}
		m68k_incpci((uae_s32)src + 2);
		int pcadjust = oldpc - m68k_getpci() + 2;
		get_word_000_prefetch(0);
		if(hardware_bus_error) {
			int pcoffset = 0;
			pcoffset += pcadjust;
			exception2_fetch_opcode(opcode, 0, pcoffset);
			return 6 * CYCLE_UNIT / 2 + count_cycles;
		}
		regs.ir = regs.irc;
		opcode = regs.ir;
		get_word_000_prefetch(2);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 2, pcoffset);
			return 10 * CYCLE_UNIT / 2 + count_cycles;
		}
		return 10 * CYCLE_UNIT / 2;
	}
	m68k_incpci(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 6 * CYCLE_UNIT / 2 + count_cycles;
}
/* 6 (1/0) */
/* 2 0,0 B */

/* Bcc.L #<data>.L (MI) */
uae_u32 REGPARAM2 op_6bff_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 55;
	CurrentInstrCycles = 8;  
	uaecptr oldpc = m68k_getpci();
	if (cctrue(11)) {
		exception3_read_prefetch(opcode, m68k_getpci() + 1);
		return 2 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8 (1/0) */
/* 2 0,0   */

/* Bcc.W #<data>.W (GE) */
uae_u32 REGPARAM2 op_6c00_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 55;
	CurrentInstrCycles = 12; 
	uaecptr oldpc = m68k_getpci();
	uae_s16 src = regs.irc;
	if (cctrue(12)) {
		if (src & 1) {
			uaecptr oldpc = m68k_getpci();
			uae_u16 rb = regs.irc;
			m68k_incpci(((uae_s32)src + 2) & ~1);
			get_word_000_prefetch(0);
			m68k_setpci_j(oldpc);
			uaecptr newpc = m68k_getpci() + (uae_s32)src + 2;
			m68k_incpci(2);
			regs.read_buffer = rb;
			exception3_read_prefetch(opcode, newpc);
			return 2 * CYCLE_UNIT / 2 + count_cycles;
		}
		m68k_incpci((uae_s32)src + 2);
		int pcadjust = oldpc - m68k_getpci() + 2;
		get_word_000_prefetch(0);
		if(hardware_bus_error) {
			int pcoffset = 0;
			pcoffset += pcadjust;
			exception2_fetch_opcode(opcode, 0, pcoffset);
			return 6 * CYCLE_UNIT / 2 + count_cycles;
		}
		regs.ir = regs.irc;
		opcode = regs.ir;
		get_word_000_prefetch(2);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 2, pcoffset);
			return 10 * CYCLE_UNIT / 2 + count_cycles;
		}
		return 10 * CYCLE_UNIT / 2;
	}
	m68k_incpci(4);
	get_word_000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (2/0) */
/* 4 0,0 B */

/* BccQ.B #<data> (GE) */
uae_u32 REGPARAM2 op_6c01_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (uae_s32)(uae_s8)(real_opcode & 255);
	OpcodeFamily = 55;
	CurrentInstrCycles = 6;  
	uaecptr oldpc = m68k_getpci();
	uae_u32 src = srcreg;
	if (cctrue(12)) {
		if (src & 1) {
			uaecptr oldpc = m68k_getpci();
			uae_u16 rb = regs.irc;
			m68k_incpci(((uae_s32)src + 2) & ~1);
			get_word_000_prefetch(0);
			m68k_setpci_j(oldpc);
			uaecptr newpc = m68k_getpci() + (uae_s32)src + 2;
			m68k_incpci(2);
			regs.read_buffer = rb;
			exception3_read_prefetch(opcode, newpc);
			return 2 * CYCLE_UNIT / 2 + count_cycles;
		}
		m68k_incpci((uae_s32)src + 2);
		int pcadjust = oldpc - m68k_getpci() + 2;
		get_word_000_prefetch(0);
		if(hardware_bus_error) {
			int pcoffset = 0;
			pcoffset += pcadjust;
			exception2_fetch_opcode(opcode, 0, pcoffset);
			return 6 * CYCLE_UNIT / 2 + count_cycles;
		}
		regs.ir = regs.irc;
		opcode = regs.ir;
		get_word_000_prefetch(2);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 2, pcoffset);
			return 10 * CYCLE_UNIT / 2 + count_cycles;
		}
		return 10 * CYCLE_UNIT / 2;
	}
	m68k_incpci(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 6 * CYCLE_UNIT / 2 + count_cycles;
}
/* 6 (1/0) */
/* 2 0,0 B */

/* Bcc.L #<data>.L (GE) */
uae_u32 REGPARAM2 op_6cff_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 55;
	CurrentInstrCycles = 8;  
	uaecptr oldpc = m68k_getpci();
	if (cctrue(12)) {
		exception3_read_prefetch(opcode, m68k_getpci() + 1);
		return 2 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8 (1/0) */
/* 2 0,0   */

/* Bcc.W #<data>.W (LT) */
uae_u32 REGPARAM2 op_6d00_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 55;
	CurrentInstrCycles = 12; 
	uaecptr oldpc = m68k_getpci();
	uae_s16 src = regs.irc;
	if (cctrue(13)) {
		if (src & 1) {
			uaecptr oldpc = m68k_getpci();
			uae_u16 rb = regs.irc;
			m68k_incpci(((uae_s32)src + 2) & ~1);
			get_word_000_prefetch(0);
			m68k_setpci_j(oldpc);
			uaecptr newpc = m68k_getpci() + (uae_s32)src + 2;
			m68k_incpci(2);
			regs.read_buffer = rb;
			exception3_read_prefetch(opcode, newpc);
			return 2 * CYCLE_UNIT / 2 + count_cycles;
		}
		m68k_incpci((uae_s32)src + 2);
		int pcadjust = oldpc - m68k_getpci() + 2;
		get_word_000_prefetch(0);
		if(hardware_bus_error) {
			int pcoffset = 0;
			pcoffset += pcadjust;
			exception2_fetch_opcode(opcode, 0, pcoffset);
			return 6 * CYCLE_UNIT / 2 + count_cycles;
		}
		regs.ir = regs.irc;
		opcode = regs.ir;
		get_word_000_prefetch(2);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 2, pcoffset);
			return 10 * CYCLE_UNIT / 2 + count_cycles;
		}
		return 10 * CYCLE_UNIT / 2;
	}
	m68k_incpci(4);
	get_word_000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (2/0) */
/* 4 0,0 B */

/* BccQ.B #<data> (LT) */
uae_u32 REGPARAM2 op_6d01_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (uae_s32)(uae_s8)(real_opcode & 255);
	OpcodeFamily = 55;
	CurrentInstrCycles = 6;  
	uaecptr oldpc = m68k_getpci();
	uae_u32 src = srcreg;
	if (cctrue(13)) {
		if (src & 1) {
			uaecptr oldpc = m68k_getpci();
			uae_u16 rb = regs.irc;
			m68k_incpci(((uae_s32)src + 2) & ~1);
			get_word_000_prefetch(0);
			m68k_setpci_j(oldpc);
			uaecptr newpc = m68k_getpci() + (uae_s32)src + 2;
			m68k_incpci(2);
			regs.read_buffer = rb;
			exception3_read_prefetch(opcode, newpc);
			return 2 * CYCLE_UNIT / 2 + count_cycles;
		}
		m68k_incpci((uae_s32)src + 2);
		int pcadjust = oldpc - m68k_getpci() + 2;
		get_word_000_prefetch(0);
		if(hardware_bus_error) {
			int pcoffset = 0;
			pcoffset += pcadjust;
			exception2_fetch_opcode(opcode, 0, pcoffset);
			return 6 * CYCLE_UNIT / 2 + count_cycles;
		}
		regs.ir = regs.irc;
		opcode = regs.ir;
		get_word_000_prefetch(2);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 2, pcoffset);
			return 10 * CYCLE_UNIT / 2 + count_cycles;
		}
		return 10 * CYCLE_UNIT / 2;
	}
	m68k_incpci(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 6 * CYCLE_UNIT / 2 + count_cycles;
}
/* 6 (1/0) */
/* 2 0,0 B */

/* Bcc.L #<data>.L (LT) */
uae_u32 REGPARAM2 op_6dff_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 55;
	CurrentInstrCycles = 8;  
	uaecptr oldpc = m68k_getpci();
	if (cctrue(13)) {
		exception3_read_prefetch(opcode, m68k_getpci() + 1);
		return 2 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8 (1/0) */
/* 2 0,0   */

/* Bcc.W #<data>.W (GT) */
uae_u32 REGPARAM2 op_6e00_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 55;
	CurrentInstrCycles = 12; 
	uaecptr oldpc = m68k_getpci();
	uae_s16 src = regs.irc;
	if (cctrue(14)) {
		if (src & 1) {
			uaecptr oldpc = m68k_getpci();
			uae_u16 rb = regs.irc;
			m68k_incpci(((uae_s32)src + 2) & ~1);
			get_word_000_prefetch(0);
			m68k_setpci_j(oldpc);
			uaecptr newpc = m68k_getpci() + (uae_s32)src + 2;
			m68k_incpci(2);
			regs.read_buffer = rb;
			exception3_read_prefetch(opcode, newpc);
			return 2 * CYCLE_UNIT / 2 + count_cycles;
		}
		m68k_incpci((uae_s32)src + 2);
		int pcadjust = oldpc - m68k_getpci() + 2;
		get_word_000_prefetch(0);
		if(hardware_bus_error) {
			int pcoffset = 0;
			pcoffset += pcadjust;
			exception2_fetch_opcode(opcode, 0, pcoffset);
			return 6 * CYCLE_UNIT / 2 + count_cycles;
		}
		regs.ir = regs.irc;
		opcode = regs.ir;
		get_word_000_prefetch(2);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 2, pcoffset);
			return 10 * CYCLE_UNIT / 2 + count_cycles;
		}
		return 10 * CYCLE_UNIT / 2;
	}
	m68k_incpci(4);
	get_word_000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (2/0) */
/* 4 0,0 B */

/* BccQ.B #<data> (GT) */
uae_u32 REGPARAM2 op_6e01_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (uae_s32)(uae_s8)(real_opcode & 255);
	OpcodeFamily = 55;
	CurrentInstrCycles = 6;  
	uaecptr oldpc = m68k_getpci();
	uae_u32 src = srcreg;
	if (cctrue(14)) {
		if (src & 1) {
			uaecptr oldpc = m68k_getpci();
			uae_u16 rb = regs.irc;
			m68k_incpci(((uae_s32)src + 2) & ~1);
			get_word_000_prefetch(0);
			m68k_setpci_j(oldpc);
			uaecptr newpc = m68k_getpci() + (uae_s32)src + 2;
			m68k_incpci(2);
			regs.read_buffer = rb;
			exception3_read_prefetch(opcode, newpc);
			return 2 * CYCLE_UNIT / 2 + count_cycles;
		}
		m68k_incpci((uae_s32)src + 2);
		int pcadjust = oldpc - m68k_getpci() + 2;
		get_word_000_prefetch(0);
		if(hardware_bus_error) {
			int pcoffset = 0;
			pcoffset += pcadjust;
			exception2_fetch_opcode(opcode, 0, pcoffset);
			return 6 * CYCLE_UNIT / 2 + count_cycles;
		}
		regs.ir = regs.irc;
		opcode = regs.ir;
		get_word_000_prefetch(2);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 2, pcoffset);
			return 10 * CYCLE_UNIT / 2 + count_cycles;
		}
		return 10 * CYCLE_UNIT / 2;
	}
	m68k_incpci(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 6 * CYCLE_UNIT / 2 + count_cycles;
}
/* 6 (1/0) */
/* 2 0,0 B */

/* Bcc.L #<data>.L (GT) */
uae_u32 REGPARAM2 op_6eff_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 55;
	CurrentInstrCycles = 8;  
	uaecptr oldpc = m68k_getpci();
	if (cctrue(14)) {
		exception3_read_prefetch(opcode, m68k_getpci() + 1);
		return 2 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8 (1/0) */
/* 2 0,0   */

/* Bcc.W #<data>.W (LE) */
uae_u32 REGPARAM2 op_6f00_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 55;
	CurrentInstrCycles = 12; 
	uaecptr oldpc = m68k_getpci();
	uae_s16 src = regs.irc;
	if (cctrue(15)) {
		if (src & 1) {
			uaecptr oldpc = m68k_getpci();
			uae_u16 rb = regs.irc;
			m68k_incpci(((uae_s32)src + 2) & ~1);
			get_word_000_prefetch(0);
			m68k_setpci_j(oldpc);
			uaecptr newpc = m68k_getpci() + (uae_s32)src + 2;
			m68k_incpci(2);
			regs.read_buffer = rb;
			exception3_read_prefetch(opcode, newpc);
			return 2 * CYCLE_UNIT / 2 + count_cycles;
		}
		m68k_incpci((uae_s32)src + 2);
		int pcadjust = oldpc - m68k_getpci() + 2;
		get_word_000_prefetch(0);
		if(hardware_bus_error) {
			int pcoffset = 0;
			pcoffset += pcadjust;
			exception2_fetch_opcode(opcode, 0, pcoffset);
			return 6 * CYCLE_UNIT / 2 + count_cycles;
		}
		regs.ir = regs.irc;
		opcode = regs.ir;
		get_word_000_prefetch(2);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 2, pcoffset);
			return 10 * CYCLE_UNIT / 2 + count_cycles;
		}
		return 10 * CYCLE_UNIT / 2;
	}
	m68k_incpci(4);
	get_word_000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (2/0) */
/* 4 0,0 B */

/* BccQ.B #<data> (LE) */
uae_u32 REGPARAM2 op_6f01_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (uae_s32)(uae_s8)(real_opcode & 255);
	OpcodeFamily = 55;
	CurrentInstrCycles = 6;  
	uaecptr oldpc = m68k_getpci();
	uae_u32 src = srcreg;
	if (cctrue(15)) {
		if (src & 1) {
			uaecptr oldpc = m68k_getpci();
			uae_u16 rb = regs.irc;
			m68k_incpci(((uae_s32)src + 2) & ~1);
			get_word_000_prefetch(0);
			m68k_setpci_j(oldpc);
			uaecptr newpc = m68k_getpci() + (uae_s32)src + 2;
			m68k_incpci(2);
			regs.read_buffer = rb;
			exception3_read_prefetch(opcode, newpc);
			return 2 * CYCLE_UNIT / 2 + count_cycles;
		}
		m68k_incpci((uae_s32)src + 2);
		int pcadjust = oldpc - m68k_getpci() + 2;
		get_word_000_prefetch(0);
		if(hardware_bus_error) {
			int pcoffset = 0;
			pcoffset += pcadjust;
			exception2_fetch_opcode(opcode, 0, pcoffset);
			return 6 * CYCLE_UNIT / 2 + count_cycles;
		}
		regs.ir = regs.irc;
		opcode = regs.ir;
		get_word_000_prefetch(2);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 2, pcoffset);
			return 10 * CYCLE_UNIT / 2 + count_cycles;
		}
		return 10 * CYCLE_UNIT / 2;
	}
	m68k_incpci(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 6 * CYCLE_UNIT / 2 + count_cycles;
}
/* 6 (1/0) */
/* 2 0,0 B */

/* Bcc.L #<data>.L (LE) */
uae_u32 REGPARAM2 op_6fff_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 55;
	CurrentInstrCycles = 8;  
	uaecptr oldpc = m68k_getpci();
	if (cctrue(15)) {
		exception3_read_prefetch(opcode, m68k_getpci() + 1);
		return 2 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8 (1/0) */
/* 2 0,0   */

/* MOVEQ.L #<data>,Dn */
uae_u32 REGPARAM2 op_7000_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (uae_s32)(uae_s8)(real_opcode & 255);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 4;  
	uae_u32 src = srcreg;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	m68k_dreg(regs, dstreg) = (src);
	m68k_incpci(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 4 * CYCLE_UNIT / 2 + count_cycles;
}
/* 4 (1/0) */
/* 2 0,0   */

/* OR.B Dn,Dn */
uae_u32 REGPARAM2 op_8000_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 4;  
	uae_s8 src = m68k_dreg(regs, srcreg);
	uae_s8 dst = m68k_dreg(regs, dstreg);
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 4 * CYCLE_UNIT / 2 + count_cycles;
}
/* 4 (1/0) */
/* 2 0,0   */

/* OR.B (An),Dn */
uae_u32 REGPARAM2 op_8010_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 4;  
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = m68k_dreg(regs, dstreg);
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
	if(!loop_mode) {
		regs.ir = regs.irc;
		opcode = regs.ir;
		get_word_000_prefetch(4);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return 4 * CYCLE_UNIT / 2 + count_cycles;
		}
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	if (loop_mode) {
		count_cycles += 4 * CYCLE_UNIT / 2;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return 4 * CYCLE_UNIT / 2 + count_cycles;
}
/* 4+ (1/0) */
/* 2 0,0   */

/* OR.B (An)+,Dn */
uae_u32 REGPARAM2 op_8018_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 4;  
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
	uae_s8 dst = m68k_dreg(regs, dstreg);
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
	if(!loop_mode) {
		regs.ir = regs.irc;
		opcode = regs.ir;
		get_word_000_prefetch(4);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return 4 * CYCLE_UNIT / 2 + count_cycles;
		}
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	if (loop_mode) {
		count_cycles += 4 * CYCLE_UNIT / 2;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return 4 * CYCLE_UNIT / 2 + count_cycles;
}
/* 4+ (1/0) */
/* 2 0,0   */

/* OR.B -(An),Dn */
uae_u32 REGPARAM2 op_8020_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 6;  
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) = srca;
	uae_s8 dst = m68k_dreg(regs, dstreg);
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
	if(!loop_mode) {
		regs.ir = regs.irc;
		opcode = regs.ir;
		get_word_000_prefetch(4);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return 6 * CYCLE_UNIT / 2 + count_cycles;
		}
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	if (loop_mode) {
		count_cycles += 4 * CYCLE_UNIT / 2;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return 6 * CYCLE_UNIT / 2 + count_cycles;
}
/* 6+ (1/0) */
/* 2 0,0   */

/* OR.B (d16,An),Dn */
uae_u32 REGPARAM2 op_8028_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = m68k_dreg(regs, dstreg);
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (3/0) */
/* 4 0,0   */

/* OR.B (d8,An,Xn),Dn */
uae_u32 REGPARAM2 op_8030_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	BusCyclePenalty += 2;
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = m68k_dreg(regs, dstreg);
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 14 * CYCLE_UNIT / 2 + count_cycles;
}
/* 14 (3/0) */
/* 4 4,0   */

/* OR.B (xxx).W,Dn */
uae_u32 REGPARAM2 op_8038_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = m68k_dreg(regs, dstreg);
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (3/0) */
/* 4 0,0   */

/* OR.B (xxx).L,Dn */
uae_u32 REGPARAM2 op_8039_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	srca |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = m68k_dreg(regs, dstreg);
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (4/0) */
/* 6 0,0   */

/* OR.B (d16,PC),Dn */
uae_u32 REGPARAM2 op_803a_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_getpci() + 2;
	srca += (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 2);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = m68k_dreg(regs, dstreg);
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (3/0) */
/* 4 0,0   */

/* OR.B (d8,PC,Xn),Dn */
uae_u32 REGPARAM2 op_803b_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	uaecptr tmppc = m68k_getpci() + 2;
	BusCyclePenalty += 2;
	srca = get_disp_ea_000(tmppc, get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 2);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = m68k_dreg(regs, dstreg);
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 14 * CYCLE_UNIT / 2 + count_cycles;
}
/* 14 (3/0) */
/* 4 4,0   */

/* OR.B #<data>.B,Dn */
uae_u32 REGPARAM2 op_803c_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 8;  
	uae_s8 src = (uae_u8)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = m68k_dreg(regs, dstreg);
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8 (2/0) */
/* 4 0,0   */

/* OR.W Dn,Dn */
uae_u32 REGPARAM2 op_8040_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 4;  
	uae_s16 src = m68k_dreg(regs, srcreg);
	uae_s16 dst = m68k_dreg(regs, dstreg);
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 4 * CYCLE_UNIT / 2 + count_cycles;
}
/* 4 (1/0) */
/* 2 0,0   */

/* OR.W (An),Dn */
uae_u32 REGPARAM2 op_8050_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 4;  
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access2(opcode, srca, 1, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
	if(!loop_mode) {
		regs.ir = regs.irc;
		opcode = regs.ir;
		get_word_000_prefetch(4);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return 4 * CYCLE_UNIT / 2 + count_cycles;
		}
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	if (loop_mode) {
		count_cycles += 4 * CYCLE_UNIT / 2;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return 4 * CYCLE_UNIT / 2 + count_cycles;
}
/* 4+ (1/0) */
/* 2 0,0   */

/* OR.W (An)+,Dn */
uae_u32 REGPARAM2 op_8058_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 4;  
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_areg(regs, srcreg) += 2 + 0;
		m68k_incpci(2);
		exception3_read_access2(opcode, srca, 1, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) += 2 + 0;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) += 2;
	uae_s16 dst = m68k_dreg(regs, dstreg);
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
	if(!loop_mode) {
		regs.ir = regs.irc;
		opcode = regs.ir;
		get_word_000_prefetch(4);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return 4 * CYCLE_UNIT / 2 + count_cycles;
		}
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	if (loop_mode) {
		count_cycles += 4 * CYCLE_UNIT / 2;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return 4 * CYCLE_UNIT / 2 + count_cycles;
}
/* 4+ (1/0) */
/* 2 0,0   */

/* OR.W -(An),Dn */
uae_u32 REGPARAM2 op_8060_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 6;  
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - 2;
	if (srca & 1) {
		m68k_areg(regs, srcreg) = srca;
		m68k_incpci(2);
		exception3_read_access2(opcode, srca, 1, 1);
		return 2 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) = srca;
	uae_s16 dst = m68k_dreg(regs, dstreg);
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
	if(!loop_mode) {
		regs.ir = regs.irc;
		opcode = regs.ir;
		get_word_000_prefetch(4);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return 6 * CYCLE_UNIT / 2 + count_cycles;
		}
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	if (loop_mode) {
		count_cycles += 4 * CYCLE_UNIT / 2;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return 6 * CYCLE_UNIT / 2 + count_cycles;
}
/* 6+ (1/0) */
/* 2 0,0   */

/* OR.W (d16,An),Dn */
uae_u32 REGPARAM2 op_8068_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (3/0) */
/* 4 0,0   */

/* OR.W (d8,An,Xn),Dn */
uae_u32 REGPARAM2 op_8070_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	BusCyclePenalty += 2;
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 14 * CYCLE_UNIT / 2 + count_cycles;
}
/* 14 (3/0) */
/* 4 4,0   */

/* OR.W (xxx).W,Dn */
uae_u32 REGPARAM2 op_8078_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, srca, 1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (3/0) */
/* 4 0,0   */

/* OR.W (xxx).L,Dn */
uae_u32 REGPARAM2 op_8079_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	srca |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, srca, 1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (4/0) */
/* 6 0,0   */

/* OR.W (d16,PC),Dn */
uae_u32 REGPARAM2 op_807a_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_getpci() + 2;
	srca += (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (3/0) */
/* 4 0,0   */

/* OR.W (d8,PC,Xn),Dn */
uae_u32 REGPARAM2 op_807b_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	uaecptr tmppc = m68k_getpci() + 2;
	BusCyclePenalty += 2;
	srca = get_disp_ea_000(tmppc, get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 14 * CYCLE_UNIT / 2 + count_cycles;
}
/* 14 (3/0) */
/* 4 4,0   */

/* OR.W #<data>.W,Dn */
uae_u32 REGPARAM2 op_807c_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 8;  
	uae_s16 src = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8 (2/0) */
/* 4 0,0   */

/* OR.L Dn,Dn */
uae_u32 REGPARAM2 op_8080_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 6;  
	uae_s32 src = m68k_dreg(regs, srcreg);
	uae_s32 dst = m68k_dreg(regs, dstreg);
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		m68k_dreg(regs, dstreg) = (src);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_dreg(regs, dstreg) = (src);
	m68k_incpci(2);
	return 6 * CYCLE_UNIT / 2 + count_cycles;
}
/* 6 (1/0) */
/* 2 0,0   */

/* OR.L (An),Dn */
uae_u32 REGPARAM2 op_8090_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 10; 
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_000_prefetch(4);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			int pcoffset = 0;
			m68k_dreg(regs, dstreg) = (src);
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return 8 * CYCLE_UNIT / 2 + count_cycles;
		}
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	if(loop_mode & 0xfffe) {
		count_cycles += (loop_mode & 0xfffe) * CYCLE_UNIT / 2;
		loop_mode = 1;
	}
	m68k_dreg(regs, dstreg) = (src);
	if (loop_mode) {
		count_cycles += 4 * CYCLE_UNIT / 2;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return 10 * CYCLE_UNIT / 2 + count_cycles;
}
/* 10+ (2/0) */
/* 2 0,0   */

/* OR.L (An)+,Dn */
uae_u32 REGPARAM2 op_8098_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 10; 
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) += 4;
	uae_s32 dst = m68k_dreg(regs, dstreg);
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_000_prefetch(4);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			int pcoffset = 0;
			m68k_dreg(regs, dstreg) = (src);
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return 8 * CYCLE_UNIT / 2 + count_cycles;
		}
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	if(loop_mode & 0xfffe) {
		count_cycles += (loop_mode & 0xfffe) * CYCLE_UNIT / 2;
		loop_mode = 1;
	}
	m68k_dreg(regs, dstreg) = (src);
	if (loop_mode) {
		count_cycles += 4 * CYCLE_UNIT / 2;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return 10 * CYCLE_UNIT / 2 + count_cycles;
}
/* 10+ (2/0) */
/* 2 0,0   */

/* OR.L -(An),Dn */
uae_u32 REGPARAM2 op_80a0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 12; 
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - 4;
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return 2 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) = srca;
	uae_s32 dst = m68k_dreg(regs, dstreg);
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_000_prefetch(4);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			int pcoffset = 0;
			m68k_dreg(regs, dstreg) = (src);
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return 10 * CYCLE_UNIT / 2 + count_cycles;
		}
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	if(loop_mode & 0xfffe) {
		count_cycles += (loop_mode & 0xfffe) * CYCLE_UNIT / 2;
		loop_mode = 1;
	}
	m68k_dreg(regs, dstreg) = (src);
	if (loop_mode) {
		count_cycles += 4 * CYCLE_UNIT / 2;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12+ (2/0) */
/* 2 0,0   */

/* OR.L (d16,An),Dn */
uae_u32 REGPARAM2 op_80a8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		m68k_dreg(regs, dstreg) = (src);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_dreg(regs, dstreg) = (src);
	m68k_incpci(4);
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (4/0) */
/* 4 0,0   */

/* OR.L (d8,An,Xn),Dn */
uae_u32 REGPARAM2 op_80b0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	BusCyclePenalty += 2;
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		m68k_dreg(regs, dstreg) = (src);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_dreg(regs, dstreg) = (src);
	m68k_incpci(4);
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (4/0) */
/* 4 4,0   */

/* OR.L (xxx).W,Dn */
uae_u32 REGPARAM2 op_80b8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, srca, 2, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		m68k_dreg(regs, dstreg) = (src);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_dreg(regs, dstreg) = (src);
	m68k_incpci(4);
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (4/0) */
/* 4 0,0   */

/* OR.L (xxx).L,Dn */
uae_u32 REGPARAM2 op_80b9_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 22; 
	uaecptr srca;
	srca = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	srca |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, srca, 2, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		m68k_dreg(regs, dstreg) = (src);
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_dreg(regs, dstreg) = (src);
	m68k_incpci(6);
	return 22 * CYCLE_UNIT / 2 + count_cycles;
}
/* 22 (5/0) */
/* 6 0,0   */

/* OR.L (d16,PC),Dn */
uae_u32 REGPARAM2 op_80ba_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	srca = m68k_getpci() + 2;
	srca += (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 2);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		m68k_dreg(regs, dstreg) = (src);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_dreg(regs, dstreg) = (src);
	m68k_incpci(4);
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (4/0) */
/* 4 0,0   */

/* OR.L (d8,PC,Xn),Dn */
uae_u32 REGPARAM2 op_80bb_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	uaecptr tmppc = m68k_getpci() + 2;
	BusCyclePenalty += 2;
	srca = get_disp_ea_000(tmppc, get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 2);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		m68k_dreg(regs, dstreg) = (src);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_dreg(regs, dstreg) = (src);
	m68k_incpci(4);
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (4/0) */
/* 4 4,0   */

/* OR.L #<data>.L,Dn */
uae_u32 REGPARAM2 op_80bc_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 16; 
	uae_s32 src;
	src = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		m68k_dreg(regs, dstreg) = (src);
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_dreg(regs, dstreg) = (src);
	m68k_incpci(6);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/0) */
/* 6 0,0   */

/* DIVU.W Dn,Dn */
uae_u32 REGPARAM2 op_80c0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 60;
	CurrentInstrCycles = 4;  
	uae_s16 src = m68k_dreg(regs, srcreg);
	uae_s32 dst = m68k_dreg(regs, dstreg);
	if (src == 0) {
		divbyzero_special(0, dst);
		m68k_incpci(2);
		Exception_cpu(5);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 newv = (uae_u32)dst / (uae_u32)(uae_u16)src;
	uae_u32 rem = (uae_u32)dst % (uae_u32)(uae_u16)src;
	count_cycles += (getDivu68kCycles((uae_u32)dst, (uae_u16)src)) * CYCLE_UNIT / 2;
	if (newv > 0xffff) {
		setdivuflags((uae_u32)dst, (uae_u16)src);
	} else {
		CLEAR_CZNV();
		SET_ZFLG(((uae_s16)(newv)) == 0);
		SET_NFLG(((uae_s16)(newv)) < 0);
		newv = (newv & 0xffff) | ((uae_u32)rem << 16);
		m68k_dreg(regs, dstreg) = (newv);
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 4 * CYCLE_UNIT / 2 + count_cycles;
}
/* 4+ (1/0) */
/* 2 0,0   */

/* DIVU.W (An),Dn */
uae_u32 REGPARAM2 op_80d0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 60;
	CurrentInstrCycles = 8;  
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access2(opcode, srca, 1, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	if (src == 0) {
		divbyzero_special(0, dst);
		m68k_incpci(2);
		Exception_cpu(5);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 newv = (uae_u32)dst / (uae_u32)(uae_u16)src;
	uae_u32 rem = (uae_u32)dst % (uae_u32)(uae_u16)src;
	count_cycles += (getDivu68kCycles((uae_u32)dst, (uae_u16)src)) * CYCLE_UNIT / 2;
	if (newv > 0xffff) {
		setdivuflags((uae_u32)dst, (uae_u16)src);
	} else {
		CLEAR_CZNV();
		SET_ZFLG(((uae_s16)(newv)) == 0);
		SET_NFLG(((uae_s16)(newv)) < 0);
		newv = (newv & 0xffff) | ((uae_u32)rem << 16);
		m68k_dreg(regs, dstreg) = (newv);
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8+ (2/0) */
/* 2 0,0   */

/* DIVU.W (An)+,Dn */
uae_u32 REGPARAM2 op_80d8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 60;
	CurrentInstrCycles = 8;  
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_areg(regs, srcreg) += 2 + 0;
		m68k_incpci(2);
		exception3_read_access2(opcode, srca, 1, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) += 2 + 0;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) += 2;
	uae_s32 dst = m68k_dreg(regs, dstreg);
	if (src == 0) {
		divbyzero_special(0, dst);
		m68k_incpci(2);
		Exception_cpu(5);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 newv = (uae_u32)dst / (uae_u32)(uae_u16)src;
	uae_u32 rem = (uae_u32)dst % (uae_u32)(uae_u16)src;
	count_cycles += (getDivu68kCycles((uae_u32)dst, (uae_u16)src)) * CYCLE_UNIT / 2;
	if (newv > 0xffff) {
		setdivuflags((uae_u32)dst, (uae_u16)src);
	} else {
		CLEAR_CZNV();
		SET_ZFLG(((uae_s16)(newv)) == 0);
		SET_NFLG(((uae_s16)(newv)) < 0);
		newv = (newv & 0xffff) | ((uae_u32)rem << 16);
		m68k_dreg(regs, dstreg) = (newv);
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8+ (2/0) */
/* 2 0,0   */

/* DIVU.W -(An),Dn */
uae_u32 REGPARAM2 op_80e0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 60;
	CurrentInstrCycles = 10; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - 2;
	if (srca & 1) {
		m68k_areg(regs, srcreg) = srca;
		m68k_incpci(2);
		exception3_read_access2(opcode, srca, 1, 1);
		return 2 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) = srca;
	uae_s32 dst = m68k_dreg(regs, dstreg);
	if (src == 0) {
		divbyzero_special(0, dst);
		m68k_incpci(2);
		Exception_cpu(5);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 newv = (uae_u32)dst / (uae_u32)(uae_u16)src;
	uae_u32 rem = (uae_u32)dst % (uae_u32)(uae_u16)src;
	count_cycles += (getDivu68kCycles((uae_u32)dst, (uae_u16)src)) * CYCLE_UNIT / 2;
	if (newv > 0xffff) {
		setdivuflags((uae_u32)dst, (uae_u16)src);
	} else {
		CLEAR_CZNV();
		SET_ZFLG(((uae_s16)(newv)) == 0);
		SET_NFLG(((uae_s16)(newv)) < 0);
		newv = (newv & 0xffff) | ((uae_u32)rem << 16);
		m68k_dreg(regs, dstreg) = (newv);
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 10 * CYCLE_UNIT / 2 + count_cycles;
}
/* 10+ (2/0) */
/* 2 0,0   */

/* DIVU.W (d16,An),Dn */
uae_u32 REGPARAM2 op_80e8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 60;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	if (src == 0) {
		divbyzero_special(0, dst);
		m68k_incpci(4);
		Exception_cpu(5);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 newv = (uae_u32)dst / (uae_u32)(uae_u16)src;
	uae_u32 rem = (uae_u32)dst % (uae_u32)(uae_u16)src;
	count_cycles += (getDivu68kCycles((uae_u32)dst, (uae_u16)src)) * CYCLE_UNIT / 2;
	if (newv > 0xffff) {
		setdivuflags((uae_u32)dst, (uae_u16)src);
	} else {
		CLEAR_CZNV();
		SET_ZFLG(((uae_s16)(newv)) == 0);
		SET_NFLG(((uae_s16)(newv)) < 0);
		newv = (newv & 0xffff) | ((uae_u32)rem << 16);
		m68k_dreg(regs, dstreg) = (newv);
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12+ (3/0) */
/* 4 0,0   */

/* DIVU.W (d8,An,Xn),Dn */
uae_u32 REGPARAM2 op_80f0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 60;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	BusCyclePenalty += 2;
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	if (src == 0) {
		divbyzero_special(0, dst);
		m68k_incpci(4);
		Exception_cpu(5);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 newv = (uae_u32)dst / (uae_u32)(uae_u16)src;
	uae_u32 rem = (uae_u32)dst % (uae_u32)(uae_u16)src;
	count_cycles += (getDivu68kCycles((uae_u32)dst, (uae_u16)src)) * CYCLE_UNIT / 2;
	if (newv > 0xffff) {
		setdivuflags((uae_u32)dst, (uae_u16)src);
	} else {
		CLEAR_CZNV();
		SET_ZFLG(((uae_s16)(newv)) == 0);
		SET_NFLG(((uae_s16)(newv)) < 0);
		newv = (newv & 0xffff) | ((uae_u32)rem << 16);
		m68k_dreg(regs, dstreg) = (newv);
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 14 * CYCLE_UNIT / 2 + count_cycles;
}
/* 14+ (3/0) */
/* 4 4,0   */

/* DIVU.W (xxx).W,Dn */
uae_u32 REGPARAM2 op_80f8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 60;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, srca, 1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	if (src == 0) {
		divbyzero_special(0, dst);
		m68k_incpci(4);
		Exception_cpu(5);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 newv = (uae_u32)dst / (uae_u32)(uae_u16)src;
	uae_u32 rem = (uae_u32)dst % (uae_u32)(uae_u16)src;
	count_cycles += (getDivu68kCycles((uae_u32)dst, (uae_u16)src)) * CYCLE_UNIT / 2;
	if (newv > 0xffff) {
		setdivuflags((uae_u32)dst, (uae_u16)src);
	} else {
		CLEAR_CZNV();
		SET_ZFLG(((uae_s16)(newv)) == 0);
		SET_NFLG(((uae_s16)(newv)) < 0);
		newv = (newv & 0xffff) | ((uae_u32)rem << 16);
		m68k_dreg(regs, dstreg) = (newv);
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12+ (3/0) */
/* 4 0,0   */

/* DIVU.W (xxx).L,Dn */
uae_u32 REGPARAM2 op_80f9_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 60;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	srca |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, srca, 1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	if (src == 0) {
		divbyzero_special(0, dst);
		m68k_incpci(6);
		Exception_cpu(5);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 newv = (uae_u32)dst / (uae_u32)(uae_u16)src;
	uae_u32 rem = (uae_u32)dst % (uae_u32)(uae_u16)src;
	count_cycles += (getDivu68kCycles((uae_u32)dst, (uae_u16)src)) * CYCLE_UNIT / 2;
	if (newv > 0xffff) {
		setdivuflags((uae_u32)dst, (uae_u16)src);
	} else {
		CLEAR_CZNV();
		SET_ZFLG(((uae_s16)(newv)) == 0);
		SET_NFLG(((uae_s16)(newv)) < 0);
		newv = (newv & 0xffff) | ((uae_u32)rem << 16);
		m68k_dreg(regs, dstreg) = (newv);
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16+ (4/0) */
/* 6 0,0   */

/* DIVU.W (d16,PC),Dn */
uae_u32 REGPARAM2 op_80fa_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 60;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_getpci() + 2;
	srca += (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	if (src == 0) {
		divbyzero_special(0, dst);
		m68k_incpci(4);
		Exception_cpu(5);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 newv = (uae_u32)dst / (uae_u32)(uae_u16)src;
	uae_u32 rem = (uae_u32)dst % (uae_u32)(uae_u16)src;
	count_cycles += (getDivu68kCycles((uae_u32)dst, (uae_u16)src)) * CYCLE_UNIT / 2;
	if (newv > 0xffff) {
		setdivuflags((uae_u32)dst, (uae_u16)src);
	} else {
		CLEAR_CZNV();
		SET_ZFLG(((uae_s16)(newv)) == 0);
		SET_NFLG(((uae_s16)(newv)) < 0);
		newv = (newv & 0xffff) | ((uae_u32)rem << 16);
		m68k_dreg(regs, dstreg) = (newv);
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12+ (3/0) */
/* 4 0,0   */

/* DIVU.W (d8,PC,Xn),Dn */
uae_u32 REGPARAM2 op_80fb_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 60;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	uaecptr tmppc = m68k_getpci() + 2;
	BusCyclePenalty += 2;
	srca = get_disp_ea_000(tmppc, get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	if (src == 0) {
		divbyzero_special(0, dst);
		m68k_incpci(4);
		Exception_cpu(5);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 newv = (uae_u32)dst / (uae_u32)(uae_u16)src;
	uae_u32 rem = (uae_u32)dst % (uae_u32)(uae_u16)src;
	count_cycles += (getDivu68kCycles((uae_u32)dst, (uae_u16)src)) * CYCLE_UNIT / 2;
	if (newv > 0xffff) {
		setdivuflags((uae_u32)dst, (uae_u16)src);
	} else {
		CLEAR_CZNV();
		SET_ZFLG(((uae_s16)(newv)) == 0);
		SET_NFLG(((uae_s16)(newv)) < 0);
		newv = (newv & 0xffff) | ((uae_u32)rem << 16);
		m68k_dreg(regs, dstreg) = (newv);
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 14 * CYCLE_UNIT / 2 + count_cycles;
}
/* 14+ (3/0) */
/* 4 4,0   */

/* DIVU.W #<data>.W,Dn */
uae_u32 REGPARAM2 op_80fc_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 60;
	CurrentInstrCycles = 8;  
	uae_s16 src = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	if (src == 0) {
		divbyzero_special(0, dst);
		m68k_incpci(4);
		Exception_cpu(5);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 newv = (uae_u32)dst / (uae_u32)(uae_u16)src;
	uae_u32 rem = (uae_u32)dst % (uae_u32)(uae_u16)src;
	count_cycles += (getDivu68kCycles((uae_u32)dst, (uae_u16)src)) * CYCLE_UNIT / 2;
	if (newv > 0xffff) {
		setdivuflags((uae_u32)dst, (uae_u16)src);
	} else {
		CLEAR_CZNV();
		SET_ZFLG(((uae_s16)(newv)) == 0);
		SET_NFLG(((uae_s16)(newv)) < 0);
		newv = (newv & 0xffff) | ((uae_u32)rem << 16);
		m68k_dreg(regs, dstreg) = (newv);
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8+ (2/0) */
/* 4 0,0   */

/* SBCD.B Dn,Dn */
uae_u32 REGPARAM2 op_8100_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 10;
	CurrentInstrCycles = 6;  
	uae_s8 src = m68k_dreg(regs, srcreg);
	uae_s8 dst = m68k_dreg(regs, dstreg);
	uae_u16 newv_lo = (dst & 0xF) - (src & 0xF) - (GET_XFLG() ? 1 : 0);
	uae_u16 newv_hi = (dst & 0xF0) - (src & 0xF0);
	uae_u16 newv, tmp_newv;
	int bcd = 0;
	newv = tmp_newv = newv_hi + newv_lo;
if (newv_lo & 0xF0) { newv -= 6; bcd = 6; };
if ((((dst & 0xFF) - (src & 0xFF) - (GET_XFLG() ? 1 : 0)) & 0x100) > 0xFF) { newv -= 0x60; }
	SET_CFLG((((dst & 0xFF) - (src & 0xFF) - bcd - (GET_XFLG() ? 1 : 0)) & 0x300) > 0xFF);
	COPY_CARRY();
	SET_ZFLG(GET_ZFLG() & (((uae_s8)(newv)) == 0));
	SET_NFLG(((uae_s8)(newv)) < 0);
	SET_VFLG((tmp_newv & 0x80) != 0 && (newv & 0x80) == 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
	m68k_incpci(2);
	return 6 * CYCLE_UNIT / 2 + count_cycles;
}
/* 6 (1/0) */
/* 2 0,0   */

/* SBCD.B -(An),-(An) */
uae_u32 REGPARAM2 op_8108_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 10;
	CurrentInstrCycles = 14; 
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) = srca;
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, dstreg) = dsta;
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) = dsta;
	uae_u16 newv_lo = (dst & 0xF) - (src & 0xF) - (GET_XFLG() ? 1 : 0);
	uae_u16 newv_hi = (dst & 0xF0) - (src & 0xF0);
	uae_u16 newv, tmp_newv;
	int bcd = 0;
	newv = tmp_newv = newv_hi + newv_lo;
if (newv_lo & 0xF0) { newv -= 6; bcd = 6; };
if ((((dst & 0xFF) - (src & 0xFF) - (GET_XFLG() ? 1 : 0)) & 0x100) > 0xFF) { newv -= 0x60; }
	SET_CFLG((((dst & 0xFF) - (src & 0xFF) - bcd - (GET_XFLG() ? 1 : 0)) & 0x300) > 0xFF);
	COPY_CARRY();
	SET_ZFLG(GET_ZFLG() & (((uae_s8)(newv)) == 0));
	SET_NFLG(((uae_s8)(newv)) < 0);
	SET_VFLG((tmp_newv & 0x80) != 0 && (newv & 0x80) == 0);
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_000_prefetch(4);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return 10 * CYCLE_UNIT / 2 + count_cycles;
		}
		opcode = regs.ir;
	} else {
		loop_mode = 0;
		loop_mode |= 6;
		loop_mode |= 6 << 16;
	}
	if(loop_mode & 0xfffe) {
		count_cycles += (loop_mode & 0xfffe) * CYCLE_UNIT / 2;
		loop_mode = 1;
	}
	put_byte_000(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x0, newv, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return 14 * CYCLE_UNIT / 2 + count_cycles;
}
/* 14+ (2/1) */
/* 2 0,0   */

/* OR.B Dn,(An) */
uae_u32 REGPARAM2 op_8110_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 8;  
	int loop_mode = regs.loop_mode;
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_000_prefetch(4);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return 4 * CYCLE_UNIT / 2 + count_cycles;
		}
		opcode = regs.ir;
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	if(loop_mode & 0xfffe) {
		count_cycles += (loop_mode & 0xfffe) * CYCLE_UNIT / 2;
		loop_mode = 1;
	}
	put_byte_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8+ (1/1) */
/* 2 0,0   */

/* OR.B Dn,(An)+ */
uae_u32 REGPARAM2 op_8118_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 8;  
	int loop_mode = regs.loop_mode;
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_000_prefetch(4);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return 4 * CYCLE_UNIT / 2 + count_cycles;
		}
		opcode = regs.ir;
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	if(loop_mode & 0xfffe) {
		count_cycles += (loop_mode & 0xfffe) * CYCLE_UNIT / 2;
		loop_mode = 1;
	}
	put_byte_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8+ (1/1) */
/* 2 0,0   */

/* OR.B Dn,-(An) */
uae_u32 REGPARAM2 op_8120_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 10; 
	int loop_mode = regs.loop_mode;
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, dstreg) = dsta;
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) = dsta;
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_000_prefetch(4);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return 6 * CYCLE_UNIT / 2 + count_cycles;
		}
		opcode = regs.ir;
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	if(loop_mode & 0xfffe) {
		count_cycles += (loop_mode & 0xfffe) * CYCLE_UNIT / 2;
		loop_mode = 1;
	}
	put_byte_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return 10 * CYCLE_UNIT / 2 + count_cycles;
}
/* 10+ (1/1) */
/* 2 0,0   */

/* OR.B Dn,(d16,An) */
uae_u32 REGPARAM2 op_8128_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 16; 
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_byte_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 4 0,0   */

/* OR.B Dn,(d8,An,Xn) */
uae_u32 REGPARAM2 op_8130_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 18; 
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	BusCyclePenalty += 2;
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_byte_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (3/1) */
/* 4 4,0   */

/* OR.B Dn,(xxx).W */
uae_u32 REGPARAM2 op_8138_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	OpcodeFamily = 1;
	CurrentInstrCycles = 16; 
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_byte_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 4 0,0   */

/* OR.B Dn,(xxx).L */
uae_u32 REGPARAM2 op_8139_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	OpcodeFamily = 1;
	CurrentInstrCycles = 20; 
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	dsta |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_byte_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (4/1) */
/* 6 0,0   */

/* OR.W Dn,(An) */
uae_u32 REGPARAM2 op_8150_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 8;  
	int loop_mode = regs.loop_mode;
	uae_s16 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	if (dsta & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dsta, 1, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = get_word_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_000_prefetch(4);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return 4 * CYCLE_UNIT / 2 + count_cycles;
		}
		opcode = regs.ir;
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	if(loop_mode & 0xfffe) {
		count_cycles += (loop_mode & 0xfffe) * CYCLE_UNIT / 2;
		loop_mode = 1;
	}
	put_word_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8+ (1/1) */
/* 2 0,0   */

/* OR.W Dn,(An)+ */
uae_u32 REGPARAM2 op_8158_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 8;  
	int loop_mode = regs.loop_mode;
	uae_s16 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	if (dsta & 1) {
		m68k_areg(regs, dstreg) += 2 + 0;
		m68k_incpci(2);
		exception3_read_access(opcode, dsta, 1, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = get_word_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, dstreg) += 2 + 0;
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) += 2;
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_000_prefetch(4);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return 4 * CYCLE_UNIT / 2 + count_cycles;
		}
		opcode = regs.ir;
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	if(loop_mode & 0xfffe) {
		count_cycles += (loop_mode & 0xfffe) * CYCLE_UNIT / 2;
		loop_mode = 1;
	}
	put_word_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8+ (1/1) */
/* 2 0,0   */

/* OR.W Dn,-(An) */
uae_u32 REGPARAM2 op_8160_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 10; 
	int loop_mode = regs.loop_mode;
	uae_s16 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - 2;
	if (dsta & 1) {
		m68k_areg(regs, dstreg) = dsta;
		m68k_incpci(2);
		exception3_read_access(opcode, dsta, 1, 1);
		return 2 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = get_word_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, dstreg) = dsta;
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) = dsta;
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_000_prefetch(4);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return 6 * CYCLE_UNIT / 2 + count_cycles;
		}
		opcode = regs.ir;
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	if(loop_mode & 0xfffe) {
		count_cycles += (loop_mode & 0xfffe) * CYCLE_UNIT / 2;
		loop_mode = 1;
	}
	put_word_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return 10 * CYCLE_UNIT / 2 + count_cycles;
}
/* 10+ (1/1) */
/* 2 0,0   */

/* OR.W Dn,(d16,An) */
uae_u32 REGPARAM2 op_8168_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 16; 
	uae_s16 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dsta, 1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = get_word_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_word_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 4 0,0   */

/* OR.W Dn,(d8,An,Xn) */
uae_u32 REGPARAM2 op_8170_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 18; 
	uae_s16 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	BusCyclePenalty += 2;
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dsta, 1, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = get_word_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_word_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (3/1) */
/* 4 4,0   */

/* OR.W Dn,(xxx).W */
uae_u32 REGPARAM2 op_8178_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	OpcodeFamily = 1;
	CurrentInstrCycles = 16; 
	uae_s16 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, dsta, 1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = get_word_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_word_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 4 0,0   */

/* OR.W Dn,(xxx).L */
uae_u32 REGPARAM2 op_8179_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	OpcodeFamily = 1;
	CurrentInstrCycles = 20; 
	uae_s16 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	dsta |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, dsta, 1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = get_word_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_word_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (4/1) */
/* 6 0,0   */

/* OR.L Dn,(An) */
uae_u32 REGPARAM2 op_8190_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 16; 
	int loop_mode = regs.loop_mode;
	uae_s32 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	if (dsta & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dsta, 2, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = get_word_000(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	dst |= get_word_000(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_000_prefetch(4);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			int pcoffset = 0;
			ccr_68000_long_move_ae_LZN(src);
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return 8 * CYCLE_UNIT / 2 + count_cycles;
		}
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	if(loop_mode & 0xfffe) {
		count_cycles += (loop_mode & 0xfffe) * CYCLE_UNIT / 2;
		loop_mode = 1;
	}
	put_word_000(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src >> 16); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16+ (2/2) */
/* 2 0,0   */

/* OR.L Dn,(An)+ */
uae_u32 REGPARAM2 op_8198_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 16; 
	int loop_mode = regs.loop_mode;
	uae_s32 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	if (dsta & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dsta, 2, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = get_word_000(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	dst |= get_word_000(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) += 4;
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_000_prefetch(4);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			int pcoffset = 0;
			ccr_68000_long_move_ae_LZN(src);
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return 8 * CYCLE_UNIT / 2 + count_cycles;
		}
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	if(loop_mode & 0xfffe) {
		count_cycles += (loop_mode & 0xfffe) * CYCLE_UNIT / 2;
		loop_mode = 1;
	}
	put_word_000(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src >> 16); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16+ (2/2) */
/* 2 0,0   */

/* OR.L Dn,-(An) */
uae_u32 REGPARAM2 op_81a0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 18; 
	int loop_mode = regs.loop_mode;
	uae_s32 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - 4;
	if (dsta & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dsta, 2, 1);
		return 2 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = get_word_000(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	dst |= get_word_000(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, dstreg) = dsta;
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) = dsta;
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_000_prefetch(4);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			int pcoffset = 0;
			ccr_68000_long_move_ae_LZN(src);
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return 10 * CYCLE_UNIT / 2 + count_cycles;
		}
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	if(loop_mode & 0xfffe) {
		count_cycles += (loop_mode & 0xfffe) * CYCLE_UNIT / 2;
		loop_mode = 1;
	}
	put_word_000(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src >> 16); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18+ (2/2) */
/* 2 0,0   */

/* OR.L Dn,(d16,An) */
uae_u32 REGPARAM2 op_81a8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 24; 
	uae_s32 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dsta, 2, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = get_word_000(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	dst |= get_word_000(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src >> 16); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 24 * CYCLE_UNIT / 2 + count_cycles;
}
/* 24 (4/2) */
/* 4 0,0   */

/* OR.L Dn,(d8,An,Xn) */
uae_u32 REGPARAM2 op_81b0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 26; 
	uae_s32 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	BusCyclePenalty += 2;
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dsta, 2, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = get_word_000(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	dst |= get_word_000(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return 22 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src >> 16); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return 26 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 26 * CYCLE_UNIT / 2 + count_cycles;
}
/* 26 (4/2) */
/* 4 4,0   */

/* OR.L Dn,(xxx).W */
uae_u32 REGPARAM2 op_81b8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	OpcodeFamily = 1;
	CurrentInstrCycles = 24; 
	uae_s32 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, dsta, 2, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = get_word_000(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	dst |= get_word_000(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src >> 16); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 24 * CYCLE_UNIT / 2 + count_cycles;
}
/* 24 (4/2) */
/* 4 0,0   */

/* OR.L Dn,(xxx).L */
uae_u32 REGPARAM2 op_81b9_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	OpcodeFamily = 1;
	CurrentInstrCycles = 28; 
	uae_s32 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	dsta |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, dsta, 2, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = get_word_000(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	dst |= get_word_000(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src >> 16); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return 28 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 28 * CYCLE_UNIT / 2 + count_cycles;
}
/* 28 (5/2) */
/* 6 0,0   */

/* DIVS.W Dn,Dn */
uae_u32 REGPARAM2 op_81c0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 61;
	CurrentInstrCycles = 4;  
	uae_s16 src = m68k_dreg(regs, srcreg);
	uae_s32 dst = m68k_dreg(regs, dstreg);
	if (src == 0) {
		divbyzero_special(1, dst);
		m68k_incpci(2);
		Exception_cpu(5);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	int extra = 0;
	count_cycles += (getDivs68kCycles((uae_s32)dst, (uae_s16)src, &extra)) * CYCLE_UNIT / 2;
	if (dst == 0x80000000 && src == -1) {
		setdivsflags((uae_s32)dst, (uae_s16)src);
	} else {
		uae_s32 newv = (uae_s32)dst / (uae_s32)(uae_s16)src;
		uae_u16 rem = (uae_s32)dst % (uae_s32)(uae_s16)src;
		if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) {
			setdivsflags((uae_s32)dst, (uae_s16)src);
		} else {
			if (((uae_s16)rem < 0) != ((uae_s32)dst < 0)) rem = -rem;
			CLEAR_CZNV();
			SET_ZFLG(((uae_s16)(newv)) == 0);
			SET_NFLG(((uae_s16)(newv)) < 0);
			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
			m68k_dreg(regs, dstreg) = (newv);
		}
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 4 * CYCLE_UNIT / 2 + count_cycles;
}
/* 4+ (1/0) */
/* 2 0,0   */

/* DIVS.W (An),Dn */
uae_u32 REGPARAM2 op_81d0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 61;
	CurrentInstrCycles = 8;  
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access2(opcode, srca, 1, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	if (src == 0) {
		divbyzero_special(1, dst);
		m68k_incpci(2);
		Exception_cpu(5);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	int extra = 0;
	count_cycles += (getDivs68kCycles((uae_s32)dst, (uae_s16)src, &extra)) * CYCLE_UNIT / 2;
	if (dst == 0x80000000 && src == -1) {
		setdivsflags((uae_s32)dst, (uae_s16)src);
	} else {
		uae_s32 newv = (uae_s32)dst / (uae_s32)(uae_s16)src;
		uae_u16 rem = (uae_s32)dst % (uae_s32)(uae_s16)src;
		if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) {
			setdivsflags((uae_s32)dst, (uae_s16)src);
		} else {
			if (((uae_s16)rem < 0) != ((uae_s32)dst < 0)) rem = -rem;
			CLEAR_CZNV();
			SET_ZFLG(((uae_s16)(newv)) == 0);
			SET_NFLG(((uae_s16)(newv)) < 0);
			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
			m68k_dreg(regs, dstreg) = (newv);
		}
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8+ (2/0) */
/* 2 0,0   */

/* DIVS.W (An)+,Dn */
uae_u32 REGPARAM2 op_81d8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 61;
	CurrentInstrCycles = 8;  
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_areg(regs, srcreg) += 2 + 0;
		m68k_incpci(2);
		exception3_read_access2(opcode, srca, 1, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) += 2 + 0;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) += 2;
	uae_s32 dst = m68k_dreg(regs, dstreg);
	if (src == 0) {
		divbyzero_special(1, dst);
		m68k_incpci(2);
		Exception_cpu(5);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	int extra = 0;
	count_cycles += (getDivs68kCycles((uae_s32)dst, (uae_s16)src, &extra)) * CYCLE_UNIT / 2;
	if (dst == 0x80000000 && src == -1) {
		setdivsflags((uae_s32)dst, (uae_s16)src);
	} else {
		uae_s32 newv = (uae_s32)dst / (uae_s32)(uae_s16)src;
		uae_u16 rem = (uae_s32)dst % (uae_s32)(uae_s16)src;
		if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) {
			setdivsflags((uae_s32)dst, (uae_s16)src);
		} else {
			if (((uae_s16)rem < 0) != ((uae_s32)dst < 0)) rem = -rem;
			CLEAR_CZNV();
			SET_ZFLG(((uae_s16)(newv)) == 0);
			SET_NFLG(((uae_s16)(newv)) < 0);
			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
			m68k_dreg(regs, dstreg) = (newv);
		}
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8+ (2/0) */
/* 2 0,0   */

/* DIVS.W -(An),Dn */
uae_u32 REGPARAM2 op_81e0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 61;
	CurrentInstrCycles = 10; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - 2;
	if (srca & 1) {
		m68k_areg(regs, srcreg) = srca;
		m68k_incpci(2);
		exception3_read_access2(opcode, srca, 1, 1);
		return 2 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) = srca;
	uae_s32 dst = m68k_dreg(regs, dstreg);
	if (src == 0) {
		divbyzero_special(1, dst);
		m68k_incpci(2);
		Exception_cpu(5);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	int extra = 0;
	count_cycles += (getDivs68kCycles((uae_s32)dst, (uae_s16)src, &extra)) * CYCLE_UNIT / 2;
	if (dst == 0x80000000 && src == -1) {
		setdivsflags((uae_s32)dst, (uae_s16)src);
	} else {
		uae_s32 newv = (uae_s32)dst / (uae_s32)(uae_s16)src;
		uae_u16 rem = (uae_s32)dst % (uae_s32)(uae_s16)src;
		if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) {
			setdivsflags((uae_s32)dst, (uae_s16)src);
		} else {
			if (((uae_s16)rem < 0) != ((uae_s32)dst < 0)) rem = -rem;
			CLEAR_CZNV();
			SET_ZFLG(((uae_s16)(newv)) == 0);
			SET_NFLG(((uae_s16)(newv)) < 0);
			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
			m68k_dreg(regs, dstreg) = (newv);
		}
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 10 * CYCLE_UNIT / 2 + count_cycles;
}
/* 10+ (2/0) */
/* 2 0,0   */

/* DIVS.W (d16,An),Dn */
uae_u32 REGPARAM2 op_81e8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 61;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	if (src == 0) {
		divbyzero_special(1, dst);
		m68k_incpci(4);
		Exception_cpu(5);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	int extra = 0;
	count_cycles += (getDivs68kCycles((uae_s32)dst, (uae_s16)src, &extra)) * CYCLE_UNIT / 2;
	if (dst == 0x80000000 && src == -1) {
		setdivsflags((uae_s32)dst, (uae_s16)src);
	} else {
		uae_s32 newv = (uae_s32)dst / (uae_s32)(uae_s16)src;
		uae_u16 rem = (uae_s32)dst % (uae_s32)(uae_s16)src;
		if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) {
			setdivsflags((uae_s32)dst, (uae_s16)src);
		} else {
			if (((uae_s16)rem < 0) != ((uae_s32)dst < 0)) rem = -rem;
			CLEAR_CZNV();
			SET_ZFLG(((uae_s16)(newv)) == 0);
			SET_NFLG(((uae_s16)(newv)) < 0);
			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
			m68k_dreg(regs, dstreg) = (newv);
		}
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12+ (3/0) */
/* 4 0,0   */

/* DIVS.W (d8,An,Xn),Dn */
uae_u32 REGPARAM2 op_81f0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 61;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	BusCyclePenalty += 2;
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	if (src == 0) {
		divbyzero_special(1, dst);
		m68k_incpci(4);
		Exception_cpu(5);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	int extra = 0;
	count_cycles += (getDivs68kCycles((uae_s32)dst, (uae_s16)src, &extra)) * CYCLE_UNIT / 2;
	if (dst == 0x80000000 && src == -1) {
		setdivsflags((uae_s32)dst, (uae_s16)src);
	} else {
		uae_s32 newv = (uae_s32)dst / (uae_s32)(uae_s16)src;
		uae_u16 rem = (uae_s32)dst % (uae_s32)(uae_s16)src;
		if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) {
			setdivsflags((uae_s32)dst, (uae_s16)src);
		} else {
			if (((uae_s16)rem < 0) != ((uae_s32)dst < 0)) rem = -rem;
			CLEAR_CZNV();
			SET_ZFLG(((uae_s16)(newv)) == 0);
			SET_NFLG(((uae_s16)(newv)) < 0);
			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
			m68k_dreg(regs, dstreg) = (newv);
		}
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 14 * CYCLE_UNIT / 2 + count_cycles;
}
/* 14+ (3/0) */
/* 4 4,0   */

/* DIVS.W (xxx).W,Dn */
uae_u32 REGPARAM2 op_81f8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 61;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, srca, 1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	if (src == 0) {
		divbyzero_special(1, dst);
		m68k_incpci(4);
		Exception_cpu(5);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	int extra = 0;
	count_cycles += (getDivs68kCycles((uae_s32)dst, (uae_s16)src, &extra)) * CYCLE_UNIT / 2;
	if (dst == 0x80000000 && src == -1) {
		setdivsflags((uae_s32)dst, (uae_s16)src);
	} else {
		uae_s32 newv = (uae_s32)dst / (uae_s32)(uae_s16)src;
		uae_u16 rem = (uae_s32)dst % (uae_s32)(uae_s16)src;
		if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) {
			setdivsflags((uae_s32)dst, (uae_s16)src);
		} else {
			if (((uae_s16)rem < 0) != ((uae_s32)dst < 0)) rem = -rem;
			CLEAR_CZNV();
			SET_ZFLG(((uae_s16)(newv)) == 0);
			SET_NFLG(((uae_s16)(newv)) < 0);
			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
			m68k_dreg(regs, dstreg) = (newv);
		}
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12+ (3/0) */
/* 4 0,0   */

/* DIVS.W (xxx).L,Dn */
uae_u32 REGPARAM2 op_81f9_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 61;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	srca |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, srca, 1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	if (src == 0) {
		divbyzero_special(1, dst);
		m68k_incpci(6);
		Exception_cpu(5);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	int extra = 0;
	count_cycles += (getDivs68kCycles((uae_s32)dst, (uae_s16)src, &extra)) * CYCLE_UNIT / 2;
	if (dst == 0x80000000 && src == -1) {
		setdivsflags((uae_s32)dst, (uae_s16)src);
	} else {
		uae_s32 newv = (uae_s32)dst / (uae_s32)(uae_s16)src;
		uae_u16 rem = (uae_s32)dst % (uae_s32)(uae_s16)src;
		if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) {
			setdivsflags((uae_s32)dst, (uae_s16)src);
		} else {
			if (((uae_s16)rem < 0) != ((uae_s32)dst < 0)) rem = -rem;
			CLEAR_CZNV();
			SET_ZFLG(((uae_s16)(newv)) == 0);
			SET_NFLG(((uae_s16)(newv)) < 0);
			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
			m68k_dreg(regs, dstreg) = (newv);
		}
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16+ (4/0) */
/* 6 0,0   */

/* DIVS.W (d16,PC),Dn */
uae_u32 REGPARAM2 op_81fa_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 61;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_getpci() + 2;
	srca += (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	if (src == 0) {
		divbyzero_special(1, dst);
		m68k_incpci(4);
		Exception_cpu(5);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	int extra = 0;
	count_cycles += (getDivs68kCycles((uae_s32)dst, (uae_s16)src, &extra)) * CYCLE_UNIT / 2;
	if (dst == 0x80000000 && src == -1) {
		setdivsflags((uae_s32)dst, (uae_s16)src);
	} else {
		uae_s32 newv = (uae_s32)dst / (uae_s32)(uae_s16)src;
		uae_u16 rem = (uae_s32)dst % (uae_s32)(uae_s16)src;
		if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) {
			setdivsflags((uae_s32)dst, (uae_s16)src);
		} else {
			if (((uae_s16)rem < 0) != ((uae_s32)dst < 0)) rem = -rem;
			CLEAR_CZNV();
			SET_ZFLG(((uae_s16)(newv)) == 0);
			SET_NFLG(((uae_s16)(newv)) < 0);
			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
			m68k_dreg(regs, dstreg) = (newv);
		}
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12+ (3/0) */
/* 4 0,0   */

/* DIVS.W (d8,PC,Xn),Dn */
uae_u32 REGPARAM2 op_81fb_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 61;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	uaecptr tmppc = m68k_getpci() + 2;
	BusCyclePenalty += 2;
	srca = get_disp_ea_000(tmppc, get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	if (src == 0) {
		divbyzero_special(1, dst);
		m68k_incpci(4);
		Exception_cpu(5);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	int extra = 0;
	count_cycles += (getDivs68kCycles((uae_s32)dst, (uae_s16)src, &extra)) * CYCLE_UNIT / 2;
	if (dst == 0x80000000 && src == -1) {
		setdivsflags((uae_s32)dst, (uae_s16)src);
	} else {
		uae_s32 newv = (uae_s32)dst / (uae_s32)(uae_s16)src;
		uae_u16 rem = (uae_s32)dst % (uae_s32)(uae_s16)src;
		if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) {
			setdivsflags((uae_s32)dst, (uae_s16)src);
		} else {
			if (((uae_s16)rem < 0) != ((uae_s32)dst < 0)) rem = -rem;
			CLEAR_CZNV();
			SET_ZFLG(((uae_s16)(newv)) == 0);
			SET_NFLG(((uae_s16)(newv)) < 0);
			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
			m68k_dreg(regs, dstreg) = (newv);
		}
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 14 * CYCLE_UNIT / 2 + count_cycles;
}
/* 14+ (3/0) */
/* 4 4,0   */

/* DIVS.W #<data>.W,Dn */
uae_u32 REGPARAM2 op_81fc_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 61;
	CurrentInstrCycles = 8;  
	uae_s16 src = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	if (src == 0) {
		divbyzero_special(1, dst);
		m68k_incpci(4);
		Exception_cpu(5);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	int extra = 0;
	count_cycles += (getDivs68kCycles((uae_s32)dst, (uae_s16)src, &extra)) * CYCLE_UNIT / 2;
	if (dst == 0x80000000 && src == -1) {
		setdivsflags((uae_s32)dst, (uae_s16)src);
	} else {
		uae_s32 newv = (uae_s32)dst / (uae_s32)(uae_s16)src;
		uae_u16 rem = (uae_s32)dst % (uae_s32)(uae_s16)src;
		if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) {
			setdivsflags((uae_s32)dst, (uae_s16)src);
		} else {
			if (((uae_s16)rem < 0) != ((uae_s32)dst < 0)) rem = -rem;
			CLEAR_CZNV();
			SET_ZFLG(((uae_s16)(newv)) == 0);
			SET_NFLG(((uae_s16)(newv)) < 0);
			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
			m68k_dreg(regs, dstreg) = (newv);
		}
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8+ (2/0) */
/* 4 0,0   */

/* SUB.B Dn,Dn */
uae_u32 REGPARAM2 op_9000_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 4;  
	uae_s8 src = m68k_dreg(regs, srcreg);
	uae_s8 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 4 * CYCLE_UNIT / 2 + count_cycles;
}
/* 4 (1/0) */
/* 2 0,0   */

/* SUB.B (An),Dn */
uae_u32 REGPARAM2 op_9010_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 4;  
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
	if(!loop_mode) {
		regs.ir = regs.irc;
		opcode = regs.ir;
		get_word_000_prefetch(4);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return 4 * CYCLE_UNIT / 2 + count_cycles;
		}
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	if (loop_mode) {
		count_cycles += 4 * CYCLE_UNIT / 2;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return 4 * CYCLE_UNIT / 2 + count_cycles;
}
/* 4+ (1/0) */
/* 2 0,0   */

/* SUB.B (An)+,Dn */
uae_u32 REGPARAM2 op_9018_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 4;  
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
	uae_s8 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
	if(!loop_mode) {
		regs.ir = regs.irc;
		opcode = regs.ir;
		get_word_000_prefetch(4);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return 4 * CYCLE_UNIT / 2 + count_cycles;
		}
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	if (loop_mode) {
		count_cycles += 4 * CYCLE_UNIT / 2;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return 4 * CYCLE_UNIT / 2 + count_cycles;
}
/* 4+ (1/0) */
/* 2 0,0   */

/* SUB.B -(An),Dn */
uae_u32 REGPARAM2 op_9020_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 6;  
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) = srca;
	uae_s8 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
	if(!loop_mode) {
		regs.ir = regs.irc;
		opcode = regs.ir;
		get_word_000_prefetch(4);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return 6 * CYCLE_UNIT / 2 + count_cycles;
		}
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	if (loop_mode) {
		count_cycles += 4 * CYCLE_UNIT / 2;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return 6 * CYCLE_UNIT / 2 + count_cycles;
}
/* 6+ (1/0) */
/* 2 0,0   */

/* SUB.B (d16,An),Dn */
uae_u32 REGPARAM2 op_9028_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (3/0) */
/* 4 0,0   */

/* SUB.B (d8,An,Xn),Dn */
uae_u32 REGPARAM2 op_9030_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	BusCyclePenalty += 2;
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 14 * CYCLE_UNIT / 2 + count_cycles;
}
/* 14 (3/0) */
/* 4 4,0   */

/* SUB.B (xxx).W,Dn */
uae_u32 REGPARAM2 op_9038_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (3/0) */
/* 4 0,0   */

/* SUB.B (xxx).L,Dn */
uae_u32 REGPARAM2 op_9039_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	srca |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (4/0) */
/* 6 0,0   */

/* SUB.B (d16,PC),Dn */
uae_u32 REGPARAM2 op_903a_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_getpci() + 2;
	srca += (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 2);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (3/0) */
/* 4 0,0   */

/* SUB.B (d8,PC,Xn),Dn */
uae_u32 REGPARAM2 op_903b_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	uaecptr tmppc = m68k_getpci() + 2;
	BusCyclePenalty += 2;
	srca = get_disp_ea_000(tmppc, get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 2);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 14 * CYCLE_UNIT / 2 + count_cycles;
}
/* 14 (3/0) */
/* 4 4,0   */

/* SUB.B #<data>.B,Dn */
uae_u32 REGPARAM2 op_903c_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 8;  
	uae_s8 src = (uae_u8)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8 (2/0) */
/* 4 0,0   */

/* SUB.W Dn,Dn */
uae_u32 REGPARAM2 op_9040_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 4;  
	uae_s16 src = m68k_dreg(regs, srcreg);
	uae_s16 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 4 * CYCLE_UNIT / 2 + count_cycles;
}
/* 4 (1/0) */
/* 2 0,0   */

/* SUB.W An,Dn */
uae_u32 REGPARAM2 op_9048_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 4;  
	uae_s16 src = m68k_areg(regs, srcreg);
	uae_s16 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 4 * CYCLE_UNIT / 2 + count_cycles;
}
/* 4 (1/0) */
/* 2 0,0   */

/* SUB.W (An),Dn */
uae_u32 REGPARAM2 op_9050_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 4;  
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access2(opcode, srca, 1, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
	if(!loop_mode) {
		regs.ir = regs.irc;
		opcode = regs.ir;
		get_word_000_prefetch(4);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return 4 * CYCLE_UNIT / 2 + count_cycles;
		}
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	if (loop_mode) {
		count_cycles += 4 * CYCLE_UNIT / 2;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return 4 * CYCLE_UNIT / 2 + count_cycles;
}
/* 4+ (1/0) */
/* 2 0,0   */

/* SUB.W (An)+,Dn */
uae_u32 REGPARAM2 op_9058_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 4;  
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_areg(regs, srcreg) += 2 + 0;
		m68k_incpci(2);
		exception3_read_access2(opcode, srca, 1, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) += 2 + 0;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) += 2;
	uae_s16 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
	if(!loop_mode) {
		regs.ir = regs.irc;
		opcode = regs.ir;
		get_word_000_prefetch(4);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return 4 * CYCLE_UNIT / 2 + count_cycles;
		}
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	if (loop_mode) {
		count_cycles += 4 * CYCLE_UNIT / 2;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return 4 * CYCLE_UNIT / 2 + count_cycles;
}
/* 4+ (1/0) */
/* 2 0,0   */

/* SUB.W -(An),Dn */
uae_u32 REGPARAM2 op_9060_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 6;  
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - 2;
	if (srca & 1) {
		m68k_areg(regs, srcreg) = srca;
		m68k_incpci(2);
		exception3_read_access2(opcode, srca, 1, 1);
		return 2 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) = srca;
	uae_s16 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
	if(!loop_mode) {
		regs.ir = regs.irc;
		opcode = regs.ir;
		get_word_000_prefetch(4);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return 6 * CYCLE_UNIT / 2 + count_cycles;
		}
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	if (loop_mode) {
		count_cycles += 4 * CYCLE_UNIT / 2;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return 6 * CYCLE_UNIT / 2 + count_cycles;
}
/* 6+ (1/0) */
/* 2 0,0   */

/* SUB.W (d16,An),Dn */
uae_u32 REGPARAM2 op_9068_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (3/0) */
/* 4 0,0   */

/* SUB.W (d8,An,Xn),Dn */
uae_u32 REGPARAM2 op_9070_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	BusCyclePenalty += 2;
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 14 * CYCLE_UNIT / 2 + count_cycles;
}
/* 14 (3/0) */
/* 4 4,0   */

/* SUB.W (xxx).W,Dn */
uae_u32 REGPARAM2 op_9078_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, srca, 1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (3/0) */
/* 4 0,0   */

/* SUB.W (xxx).L,Dn */
uae_u32 REGPARAM2 op_9079_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	srca |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, srca, 1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (4/0) */
/* 6 0,0   */

/* SUB.W (d16,PC),Dn */
uae_u32 REGPARAM2 op_907a_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_getpci() + 2;
	srca += (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (3/0) */
/* 4 0,0   */

/* SUB.W (d8,PC,Xn),Dn */
uae_u32 REGPARAM2 op_907b_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	uaecptr tmppc = m68k_getpci() + 2;
	BusCyclePenalty += 2;
	srca = get_disp_ea_000(tmppc, get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 14 * CYCLE_UNIT / 2 + count_cycles;
}
/* 14 (3/0) */
/* 4 4,0   */

/* SUB.W #<data>.W,Dn */
uae_u32 REGPARAM2 op_907c_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 8;  
	uae_s16 src = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8 (2/0) */
/* 4 0,0   */

/* SUB.L Dn,Dn */
uae_u32 REGPARAM2 op_9080_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 6;  
	uae_s32 src = m68k_dreg(regs, srcreg);
	uae_s32 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		uae_s16 bnewv = (uae_s16)dst - (uae_s16)src;
		int bflgs = ((uae_s16)(src)) < 0;
		int bflgo = ((uae_s16)(dst)) < 0;
		int bflgn = bnewv < 0;
		ccr_68000_long_move_ae_LZN(bnewv);
		SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
		SET_XFLG(GET_CFLG());
		SET_VFLG((bflgs ^ bflgo) & (bflgn ^ bflgo));
		dreg_68000_long_replace_low(dstreg, bnewv);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	m68k_dreg(regs, dstreg) = (newv);
	m68k_incpci(2);
	return 6 * CYCLE_UNIT / 2 + count_cycles;
}
/* 6 (1/0) */
/* 2 0,0   */

/* SUB.L An,Dn */
uae_u32 REGPARAM2 op_9088_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 6;  
	uae_s32 src = m68k_areg(regs, srcreg);
	uae_s32 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		uae_s16 bnewv = (uae_s16)dst - (uae_s16)src;
		int bflgs = ((uae_s16)(src)) < 0;
		int bflgo = ((uae_s16)(dst)) < 0;
		int bflgn = bnewv < 0;
		ccr_68000_long_move_ae_LZN(bnewv);
		SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
		SET_XFLG(GET_CFLG());
		SET_VFLG((bflgs ^ bflgo) & (bflgn ^ bflgo));
		dreg_68000_long_replace_low(dstreg, bnewv);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	m68k_dreg(regs, dstreg) = (newv);
	m68k_incpci(2);
	return 6 * CYCLE_UNIT / 2 + count_cycles;
}
/* 6 (1/0) */
/* 2 0,0   */

/* SUB.L (An),Dn */
uae_u32 REGPARAM2 op_9090_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 10; 
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_000_prefetch(4);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			int pcoffset = 0;
			dreg_68000_long_replace_low(dstreg, newv);
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return 8 * CYCLE_UNIT / 2 + count_cycles;
		}
		opcode = regs.ir;
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	if(loop_mode & 0xfffe) {
		count_cycles += (loop_mode & 0xfffe) * CYCLE_UNIT / 2;
		loop_mode = 1;
	}
	m68k_dreg(regs, dstreg) = (newv);
	if (loop_mode) {
		count_cycles += 4 * CYCLE_UNIT / 2;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return 10 * CYCLE_UNIT / 2 + count_cycles;
}
/* 10+ (2/0) */
/* 2 0,0   */

/* SUB.L (An)+,Dn */
uae_u32 REGPARAM2 op_9098_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 10; 
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) += 4;
	uae_s32 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_000_prefetch(4);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			int pcoffset = 0;
			dreg_68000_long_replace_low(dstreg, newv);
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return 8 * CYCLE_UNIT / 2 + count_cycles;
		}
		opcode = regs.ir;
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	if(loop_mode & 0xfffe) {
		count_cycles += (loop_mode & 0xfffe) * CYCLE_UNIT / 2;
		loop_mode = 1;
	}
	m68k_dreg(regs, dstreg) = (newv);
	if (loop_mode) {
		count_cycles += 4 * CYCLE_UNIT / 2;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return 10 * CYCLE_UNIT / 2 + count_cycles;
}
/* 10+ (2/0) */
/* 2 0,0   */

/* SUB.L -(An),Dn */
uae_u32 REGPARAM2 op_90a0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 12; 
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - 4;
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return 2 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) = srca;
	uae_s32 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_000_prefetch(4);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			int pcoffset = 0;
			dreg_68000_long_replace_low(dstreg, newv);
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return 10 * CYCLE_UNIT / 2 + count_cycles;
		}
		opcode = regs.ir;
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	if(loop_mode & 0xfffe) {
		count_cycles += (loop_mode & 0xfffe) * CYCLE_UNIT / 2;
		loop_mode = 1;
	}
	m68k_dreg(regs, dstreg) = (newv);
	if (loop_mode) {
		count_cycles += 4 * CYCLE_UNIT / 2;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12+ (2/0) */
/* 2 0,0   */

/* SUB.L (d16,An),Dn */
uae_u32 REGPARAM2 op_90a8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		dreg_68000_long_replace_low(dstreg, newv);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	m68k_dreg(regs, dstreg) = (newv);
	m68k_incpci(4);
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (4/0) */
/* 4 0,0   */

/* SUB.L (d8,An,Xn),Dn */
uae_u32 REGPARAM2 op_90b0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	BusCyclePenalty += 2;
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		dreg_68000_long_replace_low(dstreg, newv);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	m68k_dreg(regs, dstreg) = (newv);
	m68k_incpci(4);
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (4/0) */
/* 4 4,0   */

/* SUB.L (xxx).W,Dn */
uae_u32 REGPARAM2 op_90b8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, srca, 2, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		dreg_68000_long_replace_low(dstreg, newv);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	m68k_dreg(regs, dstreg) = (newv);
	m68k_incpci(4);
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (4/0) */
/* 4 0,0   */

/* SUB.L (xxx).L,Dn */
uae_u32 REGPARAM2 op_90b9_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 22; 
	uaecptr srca;
	srca = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	srca |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, srca, 2, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		dreg_68000_long_replace_low(dstreg, newv);
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	m68k_dreg(regs, dstreg) = (newv);
	m68k_incpci(6);
	return 22 * CYCLE_UNIT / 2 + count_cycles;
}
/* 22 (5/0) */
/* 6 0,0   */

/* SUB.L (d16,PC),Dn */
uae_u32 REGPARAM2 op_90ba_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	srca = m68k_getpci() + 2;
	srca += (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 2);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		dreg_68000_long_replace_low(dstreg, newv);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	m68k_dreg(regs, dstreg) = (newv);
	m68k_incpci(4);
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (4/0) */
/* 4 0,0   */

/* SUB.L (d8,PC,Xn),Dn */
uae_u32 REGPARAM2 op_90bb_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	uaecptr tmppc = m68k_getpci() + 2;
	BusCyclePenalty += 2;
	srca = get_disp_ea_000(tmppc, get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 2);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		dreg_68000_long_replace_low(dstreg, newv);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	m68k_dreg(regs, dstreg) = (newv);
	m68k_incpci(4);
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (4/0) */
/* 4 4,0   */

/* SUB.L #<data>.L,Dn */
uae_u32 REGPARAM2 op_90bc_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 14; 
	uae_s32 src;
	src = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		uae_s16 bnewv = (uae_s16)dst - (uae_s16)src;
		int bflgs = ((uae_s16)(src)) < 0;
		int bflgo = ((uae_s16)(dst)) < 0;
		int bflgn = bnewv < 0;
		ccr_68000_long_move_ae_LZN(bnewv);
		SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
		SET_XFLG(GET_CFLG());
		SET_VFLG((bflgs ^ bflgo) & (bflgn ^ bflgo));
		dreg_68000_long_replace_low(dstreg, bnewv);
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	m68k_dreg(regs, dstreg) = (newv);
	m68k_incpci(6);
	return 14 * CYCLE_UNIT / 2 + count_cycles;
}
/* 14 (3/0) */
/* 6 0,0   */

/* SUBA.W Dn,An */
uae_u32 REGPARAM2 op_90c0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 8;
	CurrentInstrCycles = 8;  
	uae_s16 src = m68k_dreg(regs, srcreg);
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = dst - src;
	regs.ir = regs.irc;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		areg_68000_long_replace_low(dstreg, newv);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) = (newv);
	m68k_incpci(2);
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8 (1/0) */
/* 2 0,0   */

/* SUBA.W An,An */
uae_u32 REGPARAM2 op_90c8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 8;
	CurrentInstrCycles = 8;  
	uae_s16 src = m68k_areg(regs, srcreg);
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = dst - src;
	regs.ir = regs.irc;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		areg_68000_long_replace_low(dstreg, newv);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) = (newv);
	m68k_incpci(2);
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8 (1/0) */
/* 2 0,0   */

/* SUBA.W (An),An */
uae_u32 REGPARAM2 op_90d0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 8;
	CurrentInstrCycles = 8;  
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access2(opcode, srca, 1, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = dst - src;
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_000_prefetch(4);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			int pcoffset = 0;
			areg_68000_long_replace_low(dstreg, newv);
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return 4 * CYCLE_UNIT / 2 + count_cycles;
		}
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	if(loop_mode & 0xfffe) {
		count_cycles += (loop_mode & 0xfffe) * CYCLE_UNIT / 2;
		loop_mode = 1;
	}
	m68k_areg(regs, dstreg) = (newv);
	if (loop_mode) {
		count_cycles += 2 * CYCLE_UNIT / 2;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8+ (1/0) */
/* 2 0,0   */

/* SUBA.W (An)+,An */
uae_u32 REGPARAM2 op_90d8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 8;
	CurrentInstrCycles = 8;  
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_areg(regs, srcreg) += 2 + 0;
		m68k_incpci(2);
		exception3_read_access2(opcode, srca, 1, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) += 2 + 0;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) += 2;
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = dst - src;
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_000_prefetch(4);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			int pcoffset = 0;
			areg_68000_long_replace_low(dstreg, newv);
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return 4 * CYCLE_UNIT / 2 + count_cycles;
		}
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	if(loop_mode & 0xfffe) {
		count_cycles += (loop_mode & 0xfffe) * CYCLE_UNIT / 2;
		loop_mode = 1;
	}
	m68k_areg(regs, dstreg) = (newv);
	if (loop_mode) {
		count_cycles += 2 * CYCLE_UNIT / 2;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8+ (1/0) */
/* 2 0,0   */

/* SUBA.W -(An),An */
uae_u32 REGPARAM2 op_90e0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 8;
	CurrentInstrCycles = 10; 
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - 2;
	if (srca & 1) {
		m68k_areg(regs, srcreg) = srca;
		m68k_incpci(2);
		exception3_read_access2(opcode, srca, 1, 1);
		return 2 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) = srca;
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = dst - src;
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_000_prefetch(4);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			int pcoffset = 0;
			areg_68000_long_replace_low(dstreg, newv);
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return 6 * CYCLE_UNIT / 2 + count_cycles;
		}
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	if(loop_mode & 0xfffe) {
		count_cycles += (loop_mode & 0xfffe) * CYCLE_UNIT / 2;
		loop_mode = 1;
	}
	m68k_areg(regs, dstreg) = (newv);
	if (loop_mode) {
		count_cycles += 2 * CYCLE_UNIT / 2;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return 10 * CYCLE_UNIT / 2 + count_cycles;
}
/* 10+ (1/0) */
/* 2 0,0   */

/* SUBA.W (d16,An),An */
uae_u32 REGPARAM2 op_90e8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 8;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = dst - src;
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		areg_68000_long_replace_low(dstreg, newv);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) = (newv);
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/0) */
/* 4 0,0   */

/* SUBA.W (d8,An,Xn),An */
uae_u32 REGPARAM2 op_90f0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 8;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	BusCyclePenalty += 2;
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = dst - src;
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		areg_68000_long_replace_low(dstreg, newv);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) = (newv);
	m68k_incpci(4);
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (3/0) */
/* 4 4,0   */

/* SUBA.W (xxx).W,An */
uae_u32 REGPARAM2 op_90f8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 8;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, srca, 1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = dst - src;
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		areg_68000_long_replace_low(dstreg, newv);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) = (newv);
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/0) */
/* 4 0,0   */

/* SUBA.W (xxx).L,An */
uae_u32 REGPARAM2 op_90f9_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 8;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	srca = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	srca |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, srca, 1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = dst - src;
	regs.ir = regs.irc;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		areg_68000_long_replace_low(dstreg, newv);
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) = (newv);
	m68k_incpci(6);
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (4/0) */
/* 6 0,0   */

/* SUBA.W (d16,PC),An */
uae_u32 REGPARAM2 op_90fa_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 8;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = m68k_getpci() + 2;
	srca += (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = dst - src;
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		areg_68000_long_replace_low(dstreg, newv);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) = (newv);
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/0) */
/* 4 0,0   */

/* SUBA.W (d8,PC,Xn),An */
uae_u32 REGPARAM2 op_90fb_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 8;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	uaecptr tmppc = m68k_getpci() + 2;
	BusCyclePenalty += 2;
	srca = get_disp_ea_000(tmppc, get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = dst - src;
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		areg_68000_long_replace_low(dstreg, newv);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) = (newv);
	m68k_incpci(4);
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (3/0) */
/* 4 4,0   */

/* SUBA.W #<data>.W,An */
uae_u32 REGPARAM2 op_90fc_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 8;
	CurrentInstrCycles = 12; 
	uae_s16 src = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = dst - src;
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		areg_68000_long_replace_low(dstreg, newv);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) = (newv);
	m68k_incpci(4);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (2/0) */
/* 4 0,0   */

/* SUBX.B Dn,Dn */
uae_u32 REGPARAM2 op_9100_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 9;
	CurrentInstrCycles = 4;  
	uae_s8 src = m68k_dreg(regs, srcreg);
	uae_s8 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = dst - src - (GET_XFLG() ? 1 : 0);
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_VFLG((flgs ^ flgo) & (flgo ^ flgn));
	SET_CFLG(flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
	COPY_CARRY();
	SET_ZFLG(GET_ZFLG() & (((uae_s8)(newv)) == 0));
	SET_NFLG(((uae_s8)(newv)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
	m68k_incpci(2);
	return 4 * CYCLE_UNIT / 2 + count_cycles;
}
/* 4 (1/0) */
/* 2 0,0   */

/* SUBX.B -(An),-(An) */
uae_u32 REGPARAM2 op_9108_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 9;
	CurrentInstrCycles = 14; 
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) = srca;
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, dstreg) = dsta;
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) = dsta;
	uae_u32 newv = dst - src - (GET_XFLG() ? 1 : 0);
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_VFLG((flgs ^ flgo) & (flgo ^ flgn));
	SET_CFLG(flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
	COPY_CARRY();
	SET_ZFLG(GET_ZFLG() & (((uae_s8)(newv)) == 0));
	SET_NFLG(((uae_s8)(newv)) < 0);
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_000_prefetch(4);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return 10 * CYCLE_UNIT / 2 + count_cycles;
		}
		opcode = regs.ir;
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	if(loop_mode & 0xfffe) {
		count_cycles += (loop_mode & 0xfffe) * CYCLE_UNIT / 2;
		loop_mode = 1;
	}
	put_byte_000(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x0, newv, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return 14 * CYCLE_UNIT / 2 + count_cycles;
}
/* 14+ (2/1) */
/* 2 0,0   */

/* SUB.B Dn,(An) */
uae_u32 REGPARAM2 op_9110_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 8;  
	int loop_mode = regs.loop_mode;
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_000_prefetch(4);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return 4 * CYCLE_UNIT / 2 + count_cycles;
		}
		opcode = regs.ir;
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	if(loop_mode & 0xfffe) {
		count_cycles += (loop_mode & 0xfffe) * CYCLE_UNIT / 2;
		loop_mode = 1;
	}
	put_byte_000(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x0, newv, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8+ (1/1) */
/* 2 0,0   */

/* SUB.B Dn,(An)+ */
uae_u32 REGPARAM2 op_9118_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 8;  
	int loop_mode = regs.loop_mode;
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
	uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_000_prefetch(4);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return 4 * CYCLE_UNIT / 2 + count_cycles;
		}
		opcode = regs.ir;
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	if(loop_mode & 0xfffe) {
		count_cycles += (loop_mode & 0xfffe) * CYCLE_UNIT / 2;
		loop_mode = 1;
	}
	put_byte_000(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x0, newv, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8+ (1/1) */
/* 2 0,0   */

/* SUB.B Dn,-(An) */
uae_u32 REGPARAM2 op_9120_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 10; 
	int loop_mode = regs.loop_mode;
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, dstreg) = dsta;
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) = dsta;
	uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_000_prefetch(4);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return 6 * CYCLE_UNIT / 2 + count_cycles;
		}
		opcode = regs.ir;
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	if(loop_mode & 0xfffe) {
		count_cycles += (loop_mode & 0xfffe) * CYCLE_UNIT / 2;
		loop_mode = 1;
	}
	put_byte_000(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x0, newv, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return 10 * CYCLE_UNIT / 2 + count_cycles;
}
/* 10+ (1/1) */
/* 2 0,0   */

/* SUB.B Dn,(d16,An) */
uae_u32 REGPARAM2 op_9128_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 16; 
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_byte_000(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x0, newv, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 4 0,0   */

/* SUB.B Dn,(d8,An,Xn) */
uae_u32 REGPARAM2 op_9130_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 18; 
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	BusCyclePenalty += 2;
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_byte_000(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x0, newv, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (3/1) */
/* 4 4,0   */

/* SUB.B Dn,(xxx).W */
uae_u32 REGPARAM2 op_9138_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	OpcodeFamily = 7;
	CurrentInstrCycles = 16; 
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_byte_000(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x0, newv, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 4 0,0   */

/* SUB.B Dn,(xxx).L */
uae_u32 REGPARAM2 op_9139_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	OpcodeFamily = 7;
	CurrentInstrCycles = 20; 
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	dsta |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_byte_000(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 0, 0x0, newv, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (4/1) */
/* 6 0,0   */

/* SUBX.W Dn,Dn */
uae_u32 REGPARAM2 op_9140_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 9;
	CurrentInstrCycles = 4;  
	uae_s16 src = m68k_dreg(regs, srcreg);
	uae_s16 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = dst - src - (GET_XFLG() ? 1 : 0);
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_VFLG((flgs ^ flgo) & (flgo ^ flgn));
	SET_CFLG(flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
	COPY_CARRY();
	SET_ZFLG(GET_ZFLG() & (((uae_s16)(newv)) == 0));
	SET_NFLG(((uae_s16)(newv)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
	m68k_incpci(2);
	return 4 * CYCLE_UNIT / 2 + count_cycles;
}
/* 4 (1/0) */
/* 2 0,0   */

/* SUBX.W -(An),-(An) */
uae_u32 REGPARAM2 op_9148_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 9;
	CurrentInstrCycles = 14; 
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - 2;
	if (srca & 1) {
		m68k_areg(regs, srcreg) = srca;
		m68k_areg(regs, srcreg) = srca;
		m68k_incpci(2);
		exception3_read_access2(opcode, srca, 1, 1);
		return 2 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) = srca;
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - 2;
	if (dsta & 1) {
		m68k_areg(regs, dstreg) = dsta;
		m68k_areg(regs, dstreg) = dsta;
		m68k_incpci(2);
		exception3_read_access2(opcode, dsta, 1, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = get_word_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, dstreg) = dsta;
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) = dsta;
	uae_u32 newv = dst - src - (GET_XFLG() ? 1 : 0);
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_VFLG((flgs ^ flgo) & (flgo ^ flgn));
	SET_CFLG(flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
	COPY_CARRY();
	SET_ZFLG(GET_ZFLG() & (((uae_s16)(newv)) == 0));
	SET_NFLG(((uae_s16)(newv)) < 0);
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_000_prefetch(4);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return 10 * CYCLE_UNIT / 2 + count_cycles;
		}
		opcode = regs.ir;
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	if(loop_mode & 0xfffe) {
		count_cycles += (loop_mode & 0xfffe) * CYCLE_UNIT / 2;
		loop_mode = 1;
	}
	put_word_000(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x1, newv, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return 14 * CYCLE_UNIT / 2 + count_cycles;
}
/* 14+ (2/1) */
/* 2 0,0   */

/* SUB.W Dn,(An) */
uae_u32 REGPARAM2 op_9150_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 8;  
	int loop_mode = regs.loop_mode;
	uae_s16 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	if (dsta & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dsta, 1, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = get_word_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_000_prefetch(4);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return 4 * CYCLE_UNIT / 2 + count_cycles;
		}
		opcode = regs.ir;
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	if(loop_mode & 0xfffe) {
		count_cycles += (loop_mode & 0xfffe) * CYCLE_UNIT / 2;
		loop_mode = 1;
	}
	put_word_000(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x1, newv, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8+ (1/1) */
/* 2 0,0   */

/* SUB.W Dn,(An)+ */
uae_u32 REGPARAM2 op_9158_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 8;  
	int loop_mode = regs.loop_mode;
	uae_s16 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	if (dsta & 1) {
		m68k_areg(regs, dstreg) += 2 + 0;
		m68k_incpci(2);
		exception3_read_access(opcode, dsta, 1, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = get_word_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, dstreg) += 2 + 0;
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) += 2;
	uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_000_prefetch(4);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return 4 * CYCLE_UNIT / 2 + count_cycles;
		}
		opcode = regs.ir;
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	if(loop_mode & 0xfffe) {
		count_cycles += (loop_mode & 0xfffe) * CYCLE_UNIT / 2;
		loop_mode = 1;
	}
	put_word_000(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x1, newv, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8+ (1/1) */
/* 2 0,0   */

/* SUB.W Dn,-(An) */
uae_u32 REGPARAM2 op_9160_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 10; 
	int loop_mode = regs.loop_mode;
	uae_s16 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - 2;
	if (dsta & 1) {
		m68k_areg(regs, dstreg) = dsta;
		m68k_incpci(2);
		exception3_read_access(opcode, dsta, 1, 1);
		return 2 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = get_word_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, dstreg) = dsta;
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) = dsta;
	uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_000_prefetch(4);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return 6 * CYCLE_UNIT / 2 + count_cycles;
		}
		opcode = regs.ir;
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	if(loop_mode & 0xfffe) {
		count_cycles += (loop_mode & 0xfffe) * CYCLE_UNIT / 2;
		loop_mode = 1;
	}
	put_word_000(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x1, newv, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return 10 * CYCLE_UNIT / 2 + count_cycles;
}
/* 10+ (1/1) */
/* 2 0,0   */

/* SUB.W Dn,(d16,An) */
uae_u32 REGPARAM2 op_9168_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 16; 
	uae_s16 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dsta, 1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = get_word_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_word_000(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, newv, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 4 0,0   */

/* SUB.W Dn,(d8,An,Xn) */
uae_u32 REGPARAM2 op_9170_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 18; 
	uae_s16 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	BusCyclePenalty += 2;
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dsta, 1, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = get_word_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_word_000(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, newv, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (3/1) */
/* 4 4,0   */

/* SUB.W Dn,(xxx).W */
uae_u32 REGPARAM2 op_9178_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	OpcodeFamily = 7;
	CurrentInstrCycles = 16; 
	uae_s16 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, dsta, 1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = get_word_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_word_000(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, newv, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 4 0,0   */

/* SUB.W Dn,(xxx).L */
uae_u32 REGPARAM2 op_9179_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	OpcodeFamily = 7;
	CurrentInstrCycles = 20; 
	uae_s16 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	dsta |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, dsta, 1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = get_word_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_word_000(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 0, 0x1, newv, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (4/1) */
/* 6 0,0   */

/* SUBX.L Dn,Dn */
uae_u32 REGPARAM2 op_9180_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 9;
	CurrentInstrCycles = 6;  
	uae_s32 src = m68k_dreg(regs, srcreg);
	uae_s32 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = dst - src - (GET_XFLG() ? 1 : 0);
	int oldz = GET_ZFLG();
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_VFLG((flgs ^ flgo) & (flgo ^ flgn));
	SET_CFLG(flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
	COPY_CARRY();
	SET_ZFLG(GET_ZFLG() & (((uae_s32)(newv)) == 0));
	SET_NFLG(((uae_s32)(newv)) < 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		int bflgs = ((uae_s16)(src)) < 0;
		int bflgo = ((uae_s16)(dst)) < 0;
		int bflgn = ((uae_s16)(newv)) < 0;
		SET_VFLG((bflgs ^ bflgo) & (bflgo ^ bflgn));
		SET_CFLG(bflgs ^ ((bflgs ^ bflgn) & (bflgo ^ bflgn)));
		SET_XFLG(GET_CFLG());
		SET_ZFLG(oldz);
		if (newv & 0xffff) SET_ZFLG(0);
		SET_NFLG(newv & 0x8000); 
		dreg_68000_long_replace_low(dstreg, newv);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	m68k_dreg(regs, dstreg) = (newv);
	m68k_incpci(2);
	return 6 * CYCLE_UNIT / 2 + count_cycles;
}
/* 6 (1/0) */
/* 2 0,0   */

/* SUBX.L -(An),-(An) */
uae_u32 REGPARAM2 op_9188_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 9;
	CurrentInstrCycles = 26; 
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - 4;
	if (srca & 1) {
		m68k_incpci(2);
		srca += 2;
		exception3_read_access(opcode, srca, 2, 1);
		return 2 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) = srca;
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - 4;
	if (dsta & 1) {
		m68k_incpci(2);
		dsta += 2;
		exception3_read_access(opcode, dsta, 2, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = get_word_000(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	dst |= get_word_000(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) = dsta;
	uae_u32 newv = dst - src - (GET_XFLG() ? 1 : 0);
	int oldz = GET_ZFLG();
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_VFLG((flgs ^ flgo) & (flgo ^ flgn));
	SET_CFLG(flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
	COPY_CARRY();
	SET_ZFLG(GET_ZFLG() & (((uae_s32)(newv)) == 0));
	SET_NFLG(((uae_s32)(newv)) < 0);
	put_word_000(dsta + 2, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		int bflgs = ((uae_s16)(src)) < 0;
		int bflgo = ((uae_s16)(dst)) < 0;
		int bflgn = ((uae_s16)(newv)) < 0;
		SET_VFLG((bflgs ^ bflgo) & (bflgo ^ bflgn));
		SET_CFLG(bflgs ^ ((bflgs ^ bflgn) & (bflgo ^ bflgn)));
		COPY_CARRY();
		SET_ZFLG(GET_ZFLG() & (((uae_s16)(newv)) == 0));
		SET_NFLG(((uae_s16)(newv)) < 0);
		exception2_write(opcode, dsta + 2, 0x1, newv, 1);
		return 22 * CYCLE_UNIT / 2 + count_cycles;
	}
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_000_prefetch(4);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return 22 * CYCLE_UNIT / 2 + count_cycles;
		}
	} else {
		loop_mode = 0;
		loop_mode |= 2;
		loop_mode |= 2 << 16;
	}
	put_word_000(dsta, newv >> 16); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x1, newv >> 16, 1);
		return 26 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return 26 * CYCLE_UNIT / 2 + count_cycles;
}
/* 26+ (4/2) */
/* 2 0,0   */

/* SUB.L Dn,(An) */
uae_u32 REGPARAM2 op_9190_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 16; 
	int loop_mode = regs.loop_mode;
	uae_s32 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	if (dsta & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dsta, 2, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = get_word_000(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	dst |= get_word_000(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_000_prefetch(4);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			int pcoffset = 0;
			uae_s16 bnewv = (uae_s16)dst - (uae_s16)src;
			int bflgs = ((uae_s16)(src)) < 0;
			int bflgo = ((uae_s16)(dst)) < 0;
			int bflgn = bnewv < 0;
			ccr_68000_long_move_ae_LZN(bnewv);
			SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
			SET_XFLG(GET_CFLG());
			SET_VFLG((bflgs ^ bflgo) & (bflgn ^ bflgo));
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return 8 * CYCLE_UNIT / 2 + count_cycles;
		}
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	if(loop_mode & 0xfffe) {
		count_cycles += (loop_mode & 0xfffe) * CYCLE_UNIT / 2;
		loop_mode = 1;
	}
	put_word_000(dsta + 2, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 2, 0x1, newv, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, newv >> 16); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x1, newv >> 16, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16+ (2/2) */
/* 2 0,0   */

/* SUB.L Dn,(An)+ */
uae_u32 REGPARAM2 op_9198_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 16; 
	int loop_mode = regs.loop_mode;
	uae_s32 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	if (dsta & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dsta, 2, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = get_word_000(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	dst |= get_word_000(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) += 4;
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_000_prefetch(4);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			int pcoffset = 0;
			uae_s16 bnewv = (uae_s16)dst - (uae_s16)src;
			int bflgs = ((uae_s16)(src)) < 0;
			int bflgo = ((uae_s16)(dst)) < 0;
			int bflgn = bnewv < 0;
			ccr_68000_long_move_ae_LZN(bnewv);
			SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
			SET_XFLG(GET_CFLG());
			SET_VFLG((bflgs ^ bflgo) & (bflgn ^ bflgo));
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return 8 * CYCLE_UNIT / 2 + count_cycles;
		}
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	if(loop_mode & 0xfffe) {
		count_cycles += (loop_mode & 0xfffe) * CYCLE_UNIT / 2;
		loop_mode = 1;
	}
	put_word_000(dsta + 2, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 2, 0x1, newv, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, newv >> 16); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x1, newv >> 16, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16+ (2/2) */
/* 2 0,0   */

/* SUB.L Dn,-(An) */
uae_u32 REGPARAM2 op_91a0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 18; 
	int loop_mode = regs.loop_mode;
	uae_s32 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - 4;
	if (dsta & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dsta, 2, 1);
		return 2 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = get_word_000(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	dst |= get_word_000(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, dstreg) = dsta;
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) = dsta;
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_000_prefetch(4);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			int pcoffset = 0;
			uae_s16 bnewv = (uae_s16)dst - (uae_s16)src;
			int bflgs = ((uae_s16)(src)) < 0;
			int bflgo = ((uae_s16)(dst)) < 0;
			int bflgn = bnewv < 0;
			ccr_68000_long_move_ae_LZN(bnewv);
			SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
			SET_XFLG(GET_CFLG());
			SET_VFLG((bflgs ^ bflgo) & (bflgn ^ bflgo));
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return 10 * CYCLE_UNIT / 2 + count_cycles;
		}
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	if(loop_mode & 0xfffe) {
		count_cycles += (loop_mode & 0xfffe) * CYCLE_UNIT / 2;
		loop_mode = 1;
	}
	put_word_000(dsta + 2, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 2, 0x1, newv, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, newv >> 16); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x1, newv >> 16, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18+ (2/2) */
/* 2 0,0   */

/* SUB.L Dn,(d16,An) */
uae_u32 REGPARAM2 op_91a8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 24; 
	uae_s32 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dsta, 2, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = get_word_000(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	dst |= get_word_000(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		uae_s16 bnewv = (uae_s16)dst - (uae_s16)src;
		int bflgs = ((uae_s16)(src)) < 0;
		int bflgo = ((uae_s16)(dst)) < 0;
		int bflgn = bnewv < 0;
		ccr_68000_long_move_ae_LZN(bnewv);
		SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
		SET_XFLG(GET_CFLG());
		SET_VFLG((bflgs ^ bflgo) & (bflgn ^ bflgo));
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta + 2, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 2, 0x1, newv, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, newv >> 16); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, newv >> 16, 1);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 24 * CYCLE_UNIT / 2 + count_cycles;
}
/* 24 (4/2) */
/* 4 0,0   */

/* SUB.L Dn,(d8,An,Xn) */
uae_u32 REGPARAM2 op_91b0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 26; 
	uae_s32 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	BusCyclePenalty += 2;
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dsta, 2, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = get_word_000(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	dst |= get_word_000(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		uae_s16 bnewv = (uae_s16)dst - (uae_s16)src;
		int bflgs = ((uae_s16)(src)) < 0;
		int bflgo = ((uae_s16)(dst)) < 0;
		int bflgn = bnewv < 0;
		ccr_68000_long_move_ae_LZN(bnewv);
		SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
		SET_XFLG(GET_CFLG());
		SET_VFLG((bflgs ^ bflgo) & (bflgn ^ bflgo));
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta + 2, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 2, 0x1, newv, 1);
		return 22 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, newv >> 16); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, newv >> 16, 1);
		return 26 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 26 * CYCLE_UNIT / 2 + count_cycles;
}
/* 26 (4/2) */
/* 4 4,0   */

/* SUB.L Dn,(xxx).W */
uae_u32 REGPARAM2 op_91b8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	OpcodeFamily = 7;
	CurrentInstrCycles = 24; 
	uae_s32 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, dsta, 2, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = get_word_000(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	dst |= get_word_000(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		uae_s16 bnewv = (uae_s16)dst - (uae_s16)src;
		int bflgs = ((uae_s16)(src)) < 0;
		int bflgo = ((uae_s16)(dst)) < 0;
		int bflgn = bnewv < 0;
		ccr_68000_long_move_ae_LZN(bnewv);
		SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
		SET_XFLG(GET_CFLG());
		SET_VFLG((bflgs ^ bflgo) & (bflgn ^ bflgo));
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta + 2, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 2, 0x1, newv, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, newv >> 16); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, newv >> 16, 1);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 24 * CYCLE_UNIT / 2 + count_cycles;
}
/* 24 (4/2) */
/* 4 0,0   */

/* SUB.L Dn,(xxx).L */
uae_u32 REGPARAM2 op_91b9_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	OpcodeFamily = 7;
	CurrentInstrCycles = 28; 
	uae_s32 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	dsta |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, dsta, 2, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = get_word_000(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	dst |= get_word_000(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		uae_s16 bnewv = (uae_s16)dst - (uae_s16)src;
		int bflgs = ((uae_s16)(src)) < 0;
		int bflgo = ((uae_s16)(dst)) < 0;
		int bflgn = bnewv < 0;
		ccr_68000_long_move_ae_LZN(bnewv);
		SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
		SET_XFLG(GET_CFLG());
		SET_VFLG((bflgs ^ bflgo) & (bflgn ^ bflgo));
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta + 2, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 2, 0x1, newv, 1);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, newv >> 16); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 0, 0x1, newv >> 16, 1);
		return 28 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 28 * CYCLE_UNIT / 2 + count_cycles;
}
/* 28 (5/2) */
/* 6 0,0   */

/* SUBA.L Dn,An */
uae_u32 REGPARAM2 op_91c0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 8;
	CurrentInstrCycles = 8;  
	uae_s32 src = m68k_dreg(regs, srcreg);
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = dst - src;
	regs.ir = regs.irc;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		areg_68000_long_replace_low(dstreg, newv);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) = (newv);
	m68k_incpci(2);
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8 (1/0) */
/* 2 0,0   */

/* SUBA.L An,An */
uae_u32 REGPARAM2 op_91c8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 8;
	CurrentInstrCycles = 8;  
	uae_s32 src = m68k_areg(regs, srcreg);
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = dst - src;
	regs.ir = regs.irc;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		areg_68000_long_replace_low(dstreg, newv);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) = (newv);
	m68k_incpci(2);
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8 (1/0) */
/* 2 0,0   */

/* SUBA.L (An),An */
uae_u32 REGPARAM2 op_91d0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 8;
	CurrentInstrCycles = 10; 
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = dst - src;
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_000_prefetch(4);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			int pcoffset = 0;
			areg_68000_long_replace_low(dstreg, newv);
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return 8 * CYCLE_UNIT / 2 + count_cycles;
		}
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	if(loop_mode & 0xfffe) {
		count_cycles += (loop_mode & 0xfffe) * CYCLE_UNIT / 2;
		loop_mode = 1;
	}
	m68k_areg(regs, dstreg) = (newv);
	if (loop_mode) {
		count_cycles += 4 * CYCLE_UNIT / 2;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return 10 * CYCLE_UNIT / 2 + count_cycles;
}
/* 10+ (2/0) */
/* 2 0,0   */

/* SUBA.L (An)+,An */
uae_u32 REGPARAM2 op_91d8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 8;
	CurrentInstrCycles = 10; 
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) += 4;
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = dst - src;
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_000_prefetch(4);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			int pcoffset = 0;
			areg_68000_long_replace_low(dstreg, newv);
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return 8 * CYCLE_UNIT / 2 + count_cycles;
		}
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	if(loop_mode & 0xfffe) {
		count_cycles += (loop_mode & 0xfffe) * CYCLE_UNIT / 2;
		loop_mode = 1;
	}
	m68k_areg(regs, dstreg) = (newv);
	if (loop_mode) {
		count_cycles += 4 * CYCLE_UNIT / 2;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return 10 * CYCLE_UNIT / 2 + count_cycles;
}
/* 10+ (2/0) */
/* 2 0,0   */

/* SUBA.L -(An),An */
uae_u32 REGPARAM2 op_91e0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 8;
	CurrentInstrCycles = 12; 
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - 4;
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return 2 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) = srca;
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = dst - src;
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_000_prefetch(4);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			int pcoffset = 0;
			areg_68000_long_replace_low(dstreg, newv);
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return 10 * CYCLE_UNIT / 2 + count_cycles;
		}
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	if(loop_mode & 0xfffe) {
		count_cycles += (loop_mode & 0xfffe) * CYCLE_UNIT / 2;
		loop_mode = 1;
	}
	m68k_areg(regs, dstreg) = (newv);
	if (loop_mode) {
		count_cycles += 4 * CYCLE_UNIT / 2;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12+ (2/0) */
/* 2 0,0   */

/* SUBA.L (d16,An),An */
uae_u32 REGPARAM2 op_91e8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 8;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = dst - src;
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		areg_68000_long_replace_low(dstreg, newv);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) = (newv);
	m68k_incpci(4);
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (4/0) */
/* 4 0,0   */

/* SUBA.L (d8,An,Xn),An */
uae_u32 REGPARAM2 op_91f0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 8;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	BusCyclePenalty += 2;
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = dst - src;
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		areg_68000_long_replace_low(dstreg, newv);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) = (newv);
	m68k_incpci(4);
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (4/0) */
/* 4 4,0   */

/* SUBA.L (xxx).W,An */
uae_u32 REGPARAM2 op_91f8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 8;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, srca, 2, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = dst - src;
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		areg_68000_long_replace_low(dstreg, newv);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) = (newv);
	m68k_incpci(4);
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (4/0) */
/* 4 0,0   */

/* SUBA.L (xxx).L,An */
uae_u32 REGPARAM2 op_91f9_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 8;
	CurrentInstrCycles = 22; 
	uaecptr srca;
	srca = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	srca |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, srca, 2, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = dst - src;
	regs.ir = regs.irc;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		areg_68000_long_replace_low(dstreg, newv);
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) = (newv);
	m68k_incpci(6);
	return 22 * CYCLE_UNIT / 2 + count_cycles;
}
/* 22 (5/0) */
/* 6 0,0   */

/* SUBA.L (d16,PC),An */
uae_u32 REGPARAM2 op_91fa_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 8;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	srca = m68k_getpci() + 2;
	srca += (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 2);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = dst - src;
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		areg_68000_long_replace_low(dstreg, newv);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) = (newv);
	m68k_incpci(4);
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (4/0) */
/* 4 0,0   */

/* SUBA.L (d8,PC,Xn),An */
uae_u32 REGPARAM2 op_91fb_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 8;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	uaecptr tmppc = m68k_getpci() + 2;
	BusCyclePenalty += 2;
	srca = get_disp_ea_000(tmppc, get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 2);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = dst - src;
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		areg_68000_long_replace_low(dstreg, newv);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) = (newv);
	m68k_incpci(4);
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (4/0) */
/* 4 4,0   */

/* SUBA.L #<data>.L,An */
uae_u32 REGPARAM2 op_91fc_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 8;
	CurrentInstrCycles = 16; 
	uae_s32 src;
	src = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = dst - src;
	regs.ir = regs.irc;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		areg_68000_long_replace_low(dstreg, newv);
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) = (newv);
	m68k_incpci(6);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/0) */
/* 6 0,0   */

/* CMP.B Dn,Dn */
uae_u32 REGPARAM2 op_b000_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 25;
	CurrentInstrCycles = 4;  
	uae_s8 src = m68k_dreg(regs, srcreg);
	uae_s8 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 4 * CYCLE_UNIT / 2 + count_cycles;
}
/* 4 (1/0) */
/* 2 0,0   */

/* CMP.B (An),Dn */
uae_u32 REGPARAM2 op_b010_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 25;
	CurrentInstrCycles = 4;  
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
	SET_NFLG(flgn != 0);
	if(!loop_mode) {
		regs.ir = regs.irc;
		opcode = regs.ir;
		get_word_000_prefetch(4);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return 4 * CYCLE_UNIT / 2 + count_cycles;
		}
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return 4 * CYCLE_UNIT / 2 + count_cycles;
}
/* 4+ (1/0) */
/* 2 0,0   */

/* CMP.B (An)+,Dn */
uae_u32 REGPARAM2 op_b018_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 25;
	CurrentInstrCycles = 4;  
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
	uae_s8 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
	SET_NFLG(flgn != 0);
	if(!loop_mode) {
		regs.ir = regs.irc;
		opcode = regs.ir;
		get_word_000_prefetch(4);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return 4 * CYCLE_UNIT / 2 + count_cycles;
		}
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return 4 * CYCLE_UNIT / 2 + count_cycles;
}
/* 4+ (1/0) */
/* 2 0,0   */

/* CMP.B -(An),Dn */
uae_u32 REGPARAM2 op_b020_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 25;
	CurrentInstrCycles = 6;  
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) = srca;
	uae_s8 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
	SET_NFLG(flgn != 0);
	if(!loop_mode) {
		regs.ir = regs.irc;
		opcode = regs.ir;
		get_word_000_prefetch(4);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return 6 * CYCLE_UNIT / 2 + count_cycles;
		}
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return 6 * CYCLE_UNIT / 2 + count_cycles;
}
/* 6+ (1/0) */
/* 2 0,0   */

/* CMP.B (d16,An),Dn */
uae_u32 REGPARAM2 op_b028_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 25;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (3/0) */
/* 4 0,0   */

/* CMP.B (d8,An,Xn),Dn */
uae_u32 REGPARAM2 op_b030_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 25;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	BusCyclePenalty += 2;
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 14 * CYCLE_UNIT / 2 + count_cycles;
}
/* 14 (3/0) */
/* 4 4,0   */

/* CMP.B (xxx).W,Dn */
uae_u32 REGPARAM2 op_b038_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 25;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (3/0) */
/* 4 0,0   */

/* CMP.B (xxx).L,Dn */
uae_u32 REGPARAM2 op_b039_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 25;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	srca |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (4/0) */
/* 6 0,0   */

/* CMP.B (d16,PC),Dn */
uae_u32 REGPARAM2 op_b03a_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 25;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_getpci() + 2;
	srca += (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 2);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (3/0) */
/* 4 0,0   */

/* CMP.B (d8,PC,Xn),Dn */
uae_u32 REGPARAM2 op_b03b_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 25;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	uaecptr tmppc = m68k_getpci() + 2;
	BusCyclePenalty += 2;
	srca = get_disp_ea_000(tmppc, get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 2);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 14 * CYCLE_UNIT / 2 + count_cycles;
}
/* 14 (3/0) */
/* 4 4,0   */

/* CMP.B #<data>.B,Dn */
uae_u32 REGPARAM2 op_b03c_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 25;
	CurrentInstrCycles = 8;  
	uae_s8 src = (uae_u8)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8 (2/0) */
/* 4 0,0   */

/* CMP.W Dn,Dn */
uae_u32 REGPARAM2 op_b040_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 25;
	CurrentInstrCycles = 4;  
	uae_s16 src = m68k_dreg(regs, srcreg);
	uae_s16 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 4 * CYCLE_UNIT / 2 + count_cycles;
}
/* 4 (1/0) */
/* 2 0,0   */

/* CMP.W An,Dn */
uae_u32 REGPARAM2 op_b048_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 25;
	CurrentInstrCycles = 4;  
	uae_s16 src = m68k_areg(regs, srcreg);
	uae_s16 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 4 * CYCLE_UNIT / 2 + count_cycles;
}
/* 4 (1/0) */
/* 2 0,0   */

/* CMP.W (An),Dn */
uae_u32 REGPARAM2 op_b050_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 25;
	CurrentInstrCycles = 4;  
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access2(opcode, srca, 1, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
	SET_NFLG(flgn != 0);
	if(!loop_mode) {
		regs.ir = regs.irc;
		opcode = regs.ir;
		get_word_000_prefetch(4);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return 4 * CYCLE_UNIT / 2 + count_cycles;
		}
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return 4 * CYCLE_UNIT / 2 + count_cycles;
}
/* 4+ (1/0) */
/* 2 0,0   */

/* CMP.W (An)+,Dn */
uae_u32 REGPARAM2 op_b058_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 25;
	CurrentInstrCycles = 4;  
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_areg(regs, srcreg) += 2 + 0;
		m68k_incpci(2);
		exception3_read_access2(opcode, srca, 1, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) += 2 + 0;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) += 2;
	uae_s16 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
	SET_NFLG(flgn != 0);
	if(!loop_mode) {
		regs.ir = regs.irc;
		opcode = regs.ir;
		get_word_000_prefetch(4);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return 4 * CYCLE_UNIT / 2 + count_cycles;
		}
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return 4 * CYCLE_UNIT / 2 + count_cycles;
}
/* 4+ (1/0) */
/* 2 0,0   */

/* CMP.W -(An),Dn */
uae_u32 REGPARAM2 op_b060_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 25;
	CurrentInstrCycles = 6;  
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - 2;
	if (srca & 1) {
		m68k_areg(regs, srcreg) = srca;
		m68k_incpci(2);
		exception3_read_access2(opcode, srca, 1, 1);
		return 2 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) = srca;
	uae_s16 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
	SET_NFLG(flgn != 0);
	if(!loop_mode) {
		regs.ir = regs.irc;
		opcode = regs.ir;
		get_word_000_prefetch(4);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return 6 * CYCLE_UNIT / 2 + count_cycles;
		}
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return 6 * CYCLE_UNIT / 2 + count_cycles;
}
/* 6+ (1/0) */
/* 2 0,0   */

/* CMP.W (d16,An),Dn */
uae_u32 REGPARAM2 op_b068_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 25;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (3/0) */
/* 4 0,0   */

/* CMP.W (d8,An,Xn),Dn */
uae_u32 REGPARAM2 op_b070_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 25;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	BusCyclePenalty += 2;
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 14 * CYCLE_UNIT / 2 + count_cycles;
}
/* 14 (3/0) */
/* 4 4,0   */

/* CMP.W (xxx).W,Dn */
uae_u32 REGPARAM2 op_b078_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 25;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, srca, 1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (3/0) */
/* 4 0,0   */

/* CMP.W (xxx).L,Dn */
uae_u32 REGPARAM2 op_b079_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 25;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	srca |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, srca, 1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (4/0) */
/* 6 0,0   */

/* CMP.W (d16,PC),Dn */
uae_u32 REGPARAM2 op_b07a_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 25;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_getpci() + 2;
	srca += (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (3/0) */
/* 4 0,0   */

/* CMP.W (d8,PC,Xn),Dn */
uae_u32 REGPARAM2 op_b07b_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 25;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	uaecptr tmppc = m68k_getpci() + 2;
	BusCyclePenalty += 2;
	srca = get_disp_ea_000(tmppc, get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 14 * CYCLE_UNIT / 2 + count_cycles;
}
/* 14 (3/0) */
/* 4 4,0   */

/* CMP.W #<data>.W,Dn */
uae_u32 REGPARAM2 op_b07c_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 25;
	CurrentInstrCycles = 8;  
	uae_s16 src = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8 (2/0) */
/* 4 0,0   */

/* CMP.L Dn,Dn */
uae_u32 REGPARAM2 op_b080_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 25;
	CurrentInstrCycles = 6;  
	uae_s32 src = m68k_dreg(regs, srcreg);
	uae_s32 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	m68k_incpci(2);
	return 6 * CYCLE_UNIT / 2 + count_cycles;
}
/* 6 (1/0) */
/* 2 0,0   */

/* CMP.L An,Dn */
uae_u32 REGPARAM2 op_b088_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 25;
	CurrentInstrCycles = 6;  
	uae_s32 src = m68k_areg(regs, srcreg);
	uae_s32 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	m68k_incpci(2);
	return 6 * CYCLE_UNIT / 2 + count_cycles;
}
/* 6 (1/0) */
/* 2 0,0   */

/* CMP.L (An),Dn */
uae_u32 REGPARAM2 op_b090_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 25;
	CurrentInstrCycles = 10; 
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	SET_NFLG(flgn != 0);
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_000_prefetch(4);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return 8 * CYCLE_UNIT / 2 + count_cycles;
		}
		opcode = regs.ir;
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 2 << 16;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return 10 * CYCLE_UNIT / 2 + count_cycles;
}
/* 10+ (2/0) */
/* 2 0,0   */

/* CMP.L (An)+,Dn */
uae_u32 REGPARAM2 op_b098_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 25;
	CurrentInstrCycles = 10; 
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) += 4;
	uae_s32 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	SET_NFLG(flgn != 0);
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_000_prefetch(4);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return 8 * CYCLE_UNIT / 2 + count_cycles;
		}
		opcode = regs.ir;
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 2 << 16;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return 10 * CYCLE_UNIT / 2 + count_cycles;
}
/* 10+ (2/0) */
/* 2 0,0   */

/* CMP.L -(An),Dn */
uae_u32 REGPARAM2 op_b0a0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 25;
	CurrentInstrCycles = 12; 
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - 4;
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return 2 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) = srca;
	uae_s32 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	SET_NFLG(flgn != 0);
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_000_prefetch(4);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return 10 * CYCLE_UNIT / 2 + count_cycles;
		}
		opcode = regs.ir;
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 2 << 16;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12+ (2/0) */
/* 2 0,0   */

/* CMP.L (d16,An),Dn */
uae_u32 REGPARAM2 op_b0a8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 25;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	m68k_incpci(4);
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (4/0) */
/* 4 0,0   */

/* CMP.L (d8,An,Xn),Dn */
uae_u32 REGPARAM2 op_b0b0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 25;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	BusCyclePenalty += 2;
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	m68k_incpci(4);
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (4/0) */
/* 4 4,0   */

/* CMP.L (xxx).W,Dn */
uae_u32 REGPARAM2 op_b0b8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 25;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, srca, 2, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	m68k_incpci(4);
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (4/0) */
/* 4 0,0   */

/* CMP.L (xxx).L,Dn */
uae_u32 REGPARAM2 op_b0b9_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 25;
	CurrentInstrCycles = 22; 
	uaecptr srca;
	srca = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	srca |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, srca, 2, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	m68k_incpci(6);
	return 22 * CYCLE_UNIT / 2 + count_cycles;
}
/* 22 (5/0) */
/* 6 0,0   */

/* CMP.L (d16,PC),Dn */
uae_u32 REGPARAM2 op_b0ba_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 25;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	srca = m68k_getpci() + 2;
	srca += (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 2);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	m68k_incpci(4);
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (4/0) */
/* 4 0,0   */

/* CMP.L (d8,PC,Xn),Dn */
uae_u32 REGPARAM2 op_b0bb_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 25;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	uaecptr tmppc = m68k_getpci() + 2;
	BusCyclePenalty += 2;
	srca = get_disp_ea_000(tmppc, get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 2);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	m68k_incpci(4);
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (4/0) */
/* 4 4,0   */

/* CMP.L #<data>.L,Dn */
uae_u32 REGPARAM2 op_b0bc_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 25;
	CurrentInstrCycles = 14; 
	uae_s32 src;
	src = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	m68k_incpci(6);
	return 14 * CYCLE_UNIT / 2 + count_cycles;
}
/* 14 (3/0) */
/* 6 0,0   */

/* CMPA.W Dn,An */
uae_u32 REGPARAM2 op_b0c0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 27;
	CurrentInstrCycles = 6;  
	uae_s16 src = m68k_dreg(regs, srcreg);
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	m68k_incpci(2);
	return 6 * CYCLE_UNIT / 2 + count_cycles;
}
/* 6 (1/0) */
/* 2 0,0   */

/* CMPA.W An,An */
uae_u32 REGPARAM2 op_b0c8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 27;
	CurrentInstrCycles = 6;  
	uae_s16 src = m68k_areg(regs, srcreg);
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	m68k_incpci(2);
	return 6 * CYCLE_UNIT / 2 + count_cycles;
}
/* 6 (1/0) */
/* 2 0,0   */

/* CMPA.W (An),An */
uae_u32 REGPARAM2 op_b0d0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 27;
	CurrentInstrCycles = 6;  
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access2(opcode, srca, 1, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	SET_NFLG(flgn != 0);
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_000_prefetch(4);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return 4 * CYCLE_UNIT / 2 + count_cycles;
		}
		opcode = regs.ir;
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return 6 * CYCLE_UNIT / 2 + count_cycles;
}
/* 6+ (1/0) */
/* 2 0,0   */

/* CMPA.W (An)+,An */
uae_u32 REGPARAM2 op_b0d8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 27;
	CurrentInstrCycles = 6;  
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_areg(regs, srcreg) += 2 + 0;
		m68k_incpci(2);
		exception3_read_access2(opcode, srca, 1, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) += 2 + 0;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) += 2;
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	SET_NFLG(flgn != 0);
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_000_prefetch(4);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return 4 * CYCLE_UNIT / 2 + count_cycles;
		}
		opcode = regs.ir;
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return 6 * CYCLE_UNIT / 2 + count_cycles;
}
/* 6+ (1/0) */
/* 2 0,0   */

/* CMPA.W -(An),An */
uae_u32 REGPARAM2 op_b0e0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 27;
	CurrentInstrCycles = 8;  
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - 2;
	if (srca & 1) {
		m68k_areg(regs, srcreg) = srca;
		m68k_incpci(2);
		exception3_read_access2(opcode, srca, 1, 1);
		return 2 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) = srca;
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	SET_NFLG(flgn != 0);
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_000_prefetch(4);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return 6 * CYCLE_UNIT / 2 + count_cycles;
		}
		opcode = regs.ir;
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8+ (1/0) */
/* 2 0,0   */

/* CMPA.W (d16,An),An */
uae_u32 REGPARAM2 op_b0e8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 27;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	m68k_incpci(4);
	return 14 * CYCLE_UNIT / 2 + count_cycles;
}
/* 14 (3/0) */
/* 4 0,0   */

/* CMPA.W (d8,An,Xn),An */
uae_u32 REGPARAM2 op_b0f0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 27;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	BusCyclePenalty += 2;
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/0) */
/* 4 4,0   */

/* CMPA.W (xxx).W,An */
uae_u32 REGPARAM2 op_b0f8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 27;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, srca, 1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	m68k_incpci(4);
	return 14 * CYCLE_UNIT / 2 + count_cycles;
}
/* 14 (3/0) */
/* 4 0,0   */

/* CMPA.W (xxx).L,An */
uae_u32 REGPARAM2 op_b0f9_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 27;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	srca = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	srca |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, srca, 1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	m68k_incpci(6);
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (4/0) */
/* 6 0,0   */

/* CMPA.W (d16,PC),An */
uae_u32 REGPARAM2 op_b0fa_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 27;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	srca = m68k_getpci() + 2;
	srca += (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	m68k_incpci(4);
	return 14 * CYCLE_UNIT / 2 + count_cycles;
}
/* 14 (3/0) */
/* 4 0,0   */

/* CMPA.W (d8,PC,Xn),An */
uae_u32 REGPARAM2 op_b0fb_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 27;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	uaecptr tmppc = m68k_getpci() + 2;
	BusCyclePenalty += 2;
	srca = get_disp_ea_000(tmppc, get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/0) */
/* 4 4,0   */

/* CMPA.W #<data>.W,An */
uae_u32 REGPARAM2 op_b0fc_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 27;
	CurrentInstrCycles = 10; 
	uae_s16 src = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	m68k_incpci(4);
	return 10 * CYCLE_UNIT / 2 + count_cycles;
}
/* 10 (2/0) */
/* 4 0,0   */

/* EOR.B Dn,Dn */
uae_u32 REGPARAM2 op_b100_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 3;
	CurrentInstrCycles = 4;  
	uae_s8 src = m68k_dreg(regs, srcreg);
	uae_s8 dst = m68k_dreg(regs, dstreg);
	src ^= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 4 * CYCLE_UNIT / 2 + count_cycles;
}
/* 4 (1/0) */
/* 2 0,0   */

/* CMPM.B (An)+,(An)+ */
uae_u32 REGPARAM2 op_b108_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 26;
	CurrentInstrCycles = 8;  
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) += areg_byteinc[srcreg] + 0;
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
	uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
	SET_NFLG(flgn != 0);
	if(!loop_mode) {
		regs.ir = regs.irc;
		opcode = regs.ir;
		get_word_000_prefetch(4);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return 8 * CYCLE_UNIT / 2 + count_cycles;
		}
	} else {
		loop_mode = 0;
		loop_mode |= 2;
		loop_mode |= 2 << 16;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8+ (2/0) */
/* 2 0,0   */

/* EOR.B Dn,(An) */
uae_u32 REGPARAM2 op_b110_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 3;
	CurrentInstrCycles = 8;  
	int loop_mode = regs.loop_mode;
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	src ^= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_000_prefetch(4);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return 4 * CYCLE_UNIT / 2 + count_cycles;
		}
		opcode = regs.ir;
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	if(loop_mode & 0xfffe) {
		count_cycles += (loop_mode & 0xfffe) * CYCLE_UNIT / 2;
		loop_mode = 1;
	}
	put_byte_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8+ (1/1) */
/* 2 0,0   */

/* EOR.B Dn,(An)+ */
uae_u32 REGPARAM2 op_b118_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 3;
	CurrentInstrCycles = 8;  
	int loop_mode = regs.loop_mode;
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
	src ^= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_000_prefetch(4);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return 4 * CYCLE_UNIT / 2 + count_cycles;
		}
		opcode = regs.ir;
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	if(loop_mode & 0xfffe) {
		count_cycles += (loop_mode & 0xfffe) * CYCLE_UNIT / 2;
		loop_mode = 1;
	}
	put_byte_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8+ (1/1) */
/* 2 0,0   */

/* EOR.B Dn,-(An) */
uae_u32 REGPARAM2 op_b120_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 3;
	CurrentInstrCycles = 10; 
	int loop_mode = regs.loop_mode;
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, dstreg) = dsta;
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) = dsta;
	src ^= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_000_prefetch(4);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return 6 * CYCLE_UNIT / 2 + count_cycles;
		}
		opcode = regs.ir;
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	if(loop_mode & 0xfffe) {
		count_cycles += (loop_mode & 0xfffe) * CYCLE_UNIT / 2;
		loop_mode = 1;
	}
	put_byte_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return 10 * CYCLE_UNIT / 2 + count_cycles;
}
/* 10+ (1/1) */
/* 2 0,0   */

/* EOR.B Dn,(d16,An) */
uae_u32 REGPARAM2 op_b128_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 3;
	CurrentInstrCycles = 16; 
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	src ^= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_byte_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 4 0,0   */

/* EOR.B Dn,(d8,An,Xn) */
uae_u32 REGPARAM2 op_b130_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 3;
	CurrentInstrCycles = 18; 
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	BusCyclePenalty += 2;
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	src ^= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_byte_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (3/1) */
/* 4 4,0   */

/* EOR.B Dn,(xxx).W */
uae_u32 REGPARAM2 op_b138_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	OpcodeFamily = 3;
	CurrentInstrCycles = 16; 
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	src ^= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_byte_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 4 0,0   */

/* EOR.B Dn,(xxx).L */
uae_u32 REGPARAM2 op_b139_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	OpcodeFamily = 3;
	CurrentInstrCycles = 20; 
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	dsta |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	src ^= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_byte_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (4/1) */
/* 6 0,0   */

/* EOR.W Dn,Dn */
uae_u32 REGPARAM2 op_b140_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 3;
	CurrentInstrCycles = 4;  
	uae_s16 src = m68k_dreg(regs, srcreg);
	uae_s16 dst = m68k_dreg(regs, dstreg);
	src ^= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 4 * CYCLE_UNIT / 2 + count_cycles;
}
/* 4 (1/0) */
/* 2 0,0   */

/* CMPM.W (An)+,(An)+ */
uae_u32 REGPARAM2 op_b148_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 26;
	CurrentInstrCycles = 8;  
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_areg(regs, srcreg) += 2 + 0;
		m68k_incpci(2);
		exception3_read_access2(opcode, srca, 1, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) += 2 + 0;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) += 2;
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	if (dsta & 1) {
		m68k_areg(regs, dstreg) += 2 + 0;
		m68k_incpci(2);
		exception3_read_access2(opcode, dsta, 1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = get_word_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, dstreg) += 2 + 0;
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) += 2;
	uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
	SET_NFLG(flgn != 0);
	if(!loop_mode) {
		regs.ir = regs.irc;
		opcode = regs.ir;
		get_word_000_prefetch(4);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return 8 * CYCLE_UNIT / 2 + count_cycles;
		}
	} else {
		loop_mode = 0;
		loop_mode |= 2;
		loop_mode |= 2 << 16;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8+ (2/0) */
/* 2 0,0   */

/* EOR.W Dn,(An) */
uae_u32 REGPARAM2 op_b150_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 3;
	CurrentInstrCycles = 8;  
	int loop_mode = regs.loop_mode;
	uae_s16 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	if (dsta & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dsta, 1, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = get_word_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	src ^= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_000_prefetch(4);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return 4 * CYCLE_UNIT / 2 + count_cycles;
		}
		opcode = regs.ir;
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	if(loop_mode & 0xfffe) {
		count_cycles += (loop_mode & 0xfffe) * CYCLE_UNIT / 2;
		loop_mode = 1;
	}
	put_word_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8+ (1/1) */
/* 2 0,0   */

/* EOR.W Dn,(An)+ */
uae_u32 REGPARAM2 op_b158_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 3;
	CurrentInstrCycles = 8;  
	int loop_mode = regs.loop_mode;
	uae_s16 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	if (dsta & 1) {
		m68k_areg(regs, dstreg) += 2 + 0;
		m68k_incpci(2);
		exception3_read_access(opcode, dsta, 1, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = get_word_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, dstreg) += 2 + 0;
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) += 2;
	src ^= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_000_prefetch(4);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return 4 * CYCLE_UNIT / 2 + count_cycles;
		}
		opcode = regs.ir;
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	if(loop_mode & 0xfffe) {
		count_cycles += (loop_mode & 0xfffe) * CYCLE_UNIT / 2;
		loop_mode = 1;
	}
	put_word_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8+ (1/1) */
/* 2 0,0   */

/* EOR.W Dn,-(An) */
uae_u32 REGPARAM2 op_b160_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 3;
	CurrentInstrCycles = 10; 
	int loop_mode = regs.loop_mode;
	uae_s16 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - 2;
	if (dsta & 1) {
		m68k_areg(regs, dstreg) = dsta;
		m68k_incpci(2);
		exception3_read_access(opcode, dsta, 1, 1);
		return 2 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = get_word_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, dstreg) = dsta;
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) = dsta;
	src ^= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_000_prefetch(4);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return 6 * CYCLE_UNIT / 2 + count_cycles;
		}
		opcode = regs.ir;
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	if(loop_mode & 0xfffe) {
		count_cycles += (loop_mode & 0xfffe) * CYCLE_UNIT / 2;
		loop_mode = 1;
	}
	put_word_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return 10 * CYCLE_UNIT / 2 + count_cycles;
}
/* 10+ (1/1) */
/* 2 0,0   */

/* EOR.W Dn,(d16,An) */
uae_u32 REGPARAM2 op_b168_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 3;
	CurrentInstrCycles = 16; 
	uae_s16 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dsta, 1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = get_word_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	src ^= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_word_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 4 0,0   */

/* EOR.W Dn,(d8,An,Xn) */
uae_u32 REGPARAM2 op_b170_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 3;
	CurrentInstrCycles = 18; 
	uae_s16 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	BusCyclePenalty += 2;
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dsta, 1, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = get_word_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	src ^= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_word_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (3/1) */
/* 4 4,0   */

/* EOR.W Dn,(xxx).W */
uae_u32 REGPARAM2 op_b178_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	OpcodeFamily = 3;
	CurrentInstrCycles = 16; 
	uae_s16 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, dsta, 1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = get_word_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	src ^= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_word_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 4 0,0   */

/* EOR.W Dn,(xxx).L */
uae_u32 REGPARAM2 op_b179_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	OpcodeFamily = 3;
	CurrentInstrCycles = 20; 
	uae_s16 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	dsta |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, dsta, 1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = get_word_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	src ^= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_word_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (4/1) */
/* 6 0,0   */

/* EOR.L Dn,Dn */
uae_u32 REGPARAM2 op_b180_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 3;
	CurrentInstrCycles = 6;  
	uae_s32 src = m68k_dreg(regs, srcreg);
	uae_s32 dst = m68k_dreg(regs, dstreg);
	src ^= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		m68k_dreg(regs, dstreg) = (src);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_dreg(regs, dstreg) = (src);
	m68k_incpci(2);
	return 6 * CYCLE_UNIT / 2 + count_cycles;
}
/* 6 (1/0) */
/* 2 0,0   */

/* CMPM.L (An)+,(An)+ */
uae_u32 REGPARAM2 op_b188_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 26;
	CurrentInstrCycles = 16; 
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_areg(regs, srcreg) += 2 + 0;
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) += 2 + 0;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) += 2 + 2;
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) += 4;
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	if (dsta & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dsta, 2, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = get_word_000(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	dst |= get_word_000(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) += 4;
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	SET_NFLG(flgn != 0);
	if(!loop_mode) {
		regs.ir = regs.irc;
		opcode = regs.ir;
		get_word_000_prefetch(4);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return 16 * CYCLE_UNIT / 2 + count_cycles;
		}
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16+ (4/0) */
/* 2 0,0   */

/* EOR.L Dn,(An) */
uae_u32 REGPARAM2 op_b190_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 3;
	CurrentInstrCycles = 16; 
	int loop_mode = regs.loop_mode;
	uae_s32 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	if (dsta & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dsta, 2, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = get_word_000(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	dst |= get_word_000(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	src ^= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_000_prefetch(4);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			int pcoffset = 0;
			ccr_68000_long_move_ae_LZN(src);
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return 8 * CYCLE_UNIT / 2 + count_cycles;
		}
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	if(loop_mode & 0xfffe) {
		count_cycles += (loop_mode & 0xfffe) * CYCLE_UNIT / 2;
		loop_mode = 1;
	}
	put_word_000(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src >> 16); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16+ (2/2) */
/* 2 0,0   */

/* EOR.L Dn,(An)+ */
uae_u32 REGPARAM2 op_b198_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 3;
	CurrentInstrCycles = 16; 
	int loop_mode = regs.loop_mode;
	uae_s32 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	if (dsta & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dsta, 2, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = get_word_000(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	dst |= get_word_000(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) += 4;
	src ^= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_000_prefetch(4);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			int pcoffset = 0;
			ccr_68000_long_move_ae_LZN(src);
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return 8 * CYCLE_UNIT / 2 + count_cycles;
		}
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	if(loop_mode & 0xfffe) {
		count_cycles += (loop_mode & 0xfffe) * CYCLE_UNIT / 2;
		loop_mode = 1;
	}
	put_word_000(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src >> 16); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16+ (2/2) */
/* 2 0,0   */

/* EOR.L Dn,-(An) */
uae_u32 REGPARAM2 op_b1a0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 3;
	CurrentInstrCycles = 18; 
	int loop_mode = regs.loop_mode;
	uae_s32 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - 4;
	if (dsta & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dsta, 2, 1);
		return 2 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = get_word_000(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	dst |= get_word_000(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, dstreg) = dsta;
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) = dsta;
	src ^= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_000_prefetch(4);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			int pcoffset = 0;
			ccr_68000_long_move_ae_LZN(src);
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return 10 * CYCLE_UNIT / 2 + count_cycles;
		}
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	if(loop_mode & 0xfffe) {
		count_cycles += (loop_mode & 0xfffe) * CYCLE_UNIT / 2;
		loop_mode = 1;
	}
	put_word_000(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src >> 16); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18+ (2/2) */
/* 2 0,0   */

/* EOR.L Dn,(d16,An) */
uae_u32 REGPARAM2 op_b1a8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 3;
	CurrentInstrCycles = 24; 
	uae_s32 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dsta, 2, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = get_word_000(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	dst |= get_word_000(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	src ^= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src >> 16); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 24 * CYCLE_UNIT / 2 + count_cycles;
}
/* 24 (4/2) */
/* 4 0,0   */

/* EOR.L Dn,(d8,An,Xn) */
uae_u32 REGPARAM2 op_b1b0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 3;
	CurrentInstrCycles = 26; 
	uae_s32 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	BusCyclePenalty += 2;
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dsta, 2, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = get_word_000(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	dst |= get_word_000(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	src ^= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return 22 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src >> 16); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return 26 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 26 * CYCLE_UNIT / 2 + count_cycles;
}
/* 26 (4/2) */
/* 4 4,0   */

/* EOR.L Dn,(xxx).W */
uae_u32 REGPARAM2 op_b1b8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	OpcodeFamily = 3;
	CurrentInstrCycles = 24; 
	uae_s32 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, dsta, 2, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = get_word_000(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	dst |= get_word_000(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	src ^= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src >> 16); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 24 * CYCLE_UNIT / 2 + count_cycles;
}
/* 24 (4/2) */
/* 4 0,0   */

/* EOR.L Dn,(xxx).L */
uae_u32 REGPARAM2 op_b1b9_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	OpcodeFamily = 3;
	CurrentInstrCycles = 28; 
	uae_s32 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	dsta |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, dsta, 2, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = get_word_000(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	dst |= get_word_000(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	src ^= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src >> 16); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return 28 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 28 * CYCLE_UNIT / 2 + count_cycles;
}
/* 28 (5/2) */
/* 6 0,0   */

/* CMPA.L Dn,An */
uae_u32 REGPARAM2 op_b1c0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 27;
	CurrentInstrCycles = 6;  
	uae_s32 src = m68k_dreg(regs, srcreg);
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	m68k_incpci(2);
	return 6 * CYCLE_UNIT / 2 + count_cycles;
}
/* 6 (1/0) */
/* 2 0,0   */

/* CMPA.L An,An */
uae_u32 REGPARAM2 op_b1c8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 27;
	CurrentInstrCycles = 6;  
	uae_s32 src = m68k_areg(regs, srcreg);
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	m68k_incpci(2);
	return 6 * CYCLE_UNIT / 2 + count_cycles;
}
/* 6 (1/0) */
/* 2 0,0   */

/* CMPA.L (An),An */
uae_u32 REGPARAM2 op_b1d0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 27;
	CurrentInstrCycles = 10; 
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	SET_NFLG(flgn != 0);
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_000_prefetch(4);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return 8 * CYCLE_UNIT / 2 + count_cycles;
		}
		opcode = regs.ir;
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return 10 * CYCLE_UNIT / 2 + count_cycles;
}
/* 10+ (2/0) */
/* 2 0,0   */

/* CMPA.L (An)+,An */
uae_u32 REGPARAM2 op_b1d8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 27;
	CurrentInstrCycles = 10; 
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) += 4;
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	SET_NFLG(flgn != 0);
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_000_prefetch(4);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return 8 * CYCLE_UNIT / 2 + count_cycles;
		}
		opcode = regs.ir;
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return 10 * CYCLE_UNIT / 2 + count_cycles;
}
/* 10+ (2/0) */
/* 2 0,0   */

/* CMPA.L -(An),An */
uae_u32 REGPARAM2 op_b1e0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 27;
	CurrentInstrCycles = 12; 
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - 4;
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return 2 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) = srca;
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	SET_NFLG(flgn != 0);
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_000_prefetch(4);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return 10 * CYCLE_UNIT / 2 + count_cycles;
		}
		opcode = regs.ir;
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12+ (2/0) */
/* 2 0,0   */

/* CMPA.L (d16,An),An */
uae_u32 REGPARAM2 op_b1e8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 27;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	m68k_incpci(4);
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (4/0) */
/* 4 0,0   */

/* CMPA.L (d8,An,Xn),An */
uae_u32 REGPARAM2 op_b1f0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 27;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	BusCyclePenalty += 2;
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	m68k_incpci(4);
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (4/0) */
/* 4 4,0   */

/* CMPA.L (xxx).W,An */
uae_u32 REGPARAM2 op_b1f8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 27;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, srca, 2, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	m68k_incpci(4);
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (4/0) */
/* 4 0,0   */

/* CMPA.L (xxx).L,An */
uae_u32 REGPARAM2 op_b1f9_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 27;
	CurrentInstrCycles = 22; 
	uaecptr srca;
	srca = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	srca |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, srca, 2, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	m68k_incpci(6);
	return 22 * CYCLE_UNIT / 2 + count_cycles;
}
/* 22 (5/0) */
/* 6 0,0   */

/* CMPA.L (d16,PC),An */
uae_u32 REGPARAM2 op_b1fa_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 27;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	srca = m68k_getpci() + 2;
	srca += (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 2);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	m68k_incpci(4);
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (4/0) */
/* 4 0,0   */

/* CMPA.L (d8,PC,Xn),An */
uae_u32 REGPARAM2 op_b1fb_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 27;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	uaecptr tmppc = m68k_getpci() + 2;
	BusCyclePenalty += 2;
	srca = get_disp_ea_000(tmppc, get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 2);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	m68k_incpci(4);
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (4/0) */
/* 4 4,0   */

/* CMPA.L #<data>.L,An */
uae_u32 REGPARAM2 op_b1fc_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 27;
	CurrentInstrCycles = 14; 
	uae_s32 src;
	src = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	m68k_incpci(6);
	return 14 * CYCLE_UNIT / 2 + count_cycles;
}
/* 14 (3/0) */
/* 6 0,0   */

/* AND.B Dn,Dn */
uae_u32 REGPARAM2 op_c000_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 4;  
	uae_s8 src = m68k_dreg(regs, srcreg);
	uae_s8 dst = m68k_dreg(regs, dstreg);
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 4 * CYCLE_UNIT / 2 + count_cycles;
}
/* 4 (1/0) */
/* 2 0,0   */

/* AND.B (An),Dn */
uae_u32 REGPARAM2 op_c010_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 4;  
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = m68k_dreg(regs, dstreg);
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
	if(!loop_mode) {
		regs.ir = regs.irc;
		opcode = regs.ir;
		get_word_000_prefetch(4);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return 4 * CYCLE_UNIT / 2 + count_cycles;
		}
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	if (loop_mode) {
		count_cycles += 4 * CYCLE_UNIT / 2;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return 4 * CYCLE_UNIT / 2 + count_cycles;
}
/* 4+ (1/0) */
/* 2 0,0   */

/* AND.B (An)+,Dn */
uae_u32 REGPARAM2 op_c018_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 4;  
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
	uae_s8 dst = m68k_dreg(regs, dstreg);
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
	if(!loop_mode) {
		regs.ir = regs.irc;
		opcode = regs.ir;
		get_word_000_prefetch(4);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return 4 * CYCLE_UNIT / 2 + count_cycles;
		}
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	if (loop_mode) {
		count_cycles += 4 * CYCLE_UNIT / 2;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return 4 * CYCLE_UNIT / 2 + count_cycles;
}
/* 4+ (1/0) */
/* 2 0,0   */

/* AND.B -(An),Dn */
uae_u32 REGPARAM2 op_c020_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 6;  
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) = srca;
	uae_s8 dst = m68k_dreg(regs, dstreg);
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
	if(!loop_mode) {
		regs.ir = regs.irc;
		opcode = regs.ir;
		get_word_000_prefetch(4);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return 6 * CYCLE_UNIT / 2 + count_cycles;
		}
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	if (loop_mode) {
		count_cycles += 4 * CYCLE_UNIT / 2;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return 6 * CYCLE_UNIT / 2 + count_cycles;
}
/* 6+ (1/0) */
/* 2 0,0   */

/* AND.B (d16,An),Dn */
uae_u32 REGPARAM2 op_c028_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = m68k_dreg(regs, dstreg);
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (3/0) */
/* 4 0,0   */

/* AND.B (d8,An,Xn),Dn */
uae_u32 REGPARAM2 op_c030_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	BusCyclePenalty += 2;
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = m68k_dreg(regs, dstreg);
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 14 * CYCLE_UNIT / 2 + count_cycles;
}
/* 14 (3/0) */
/* 4 4,0   */

/* AND.B (xxx).W,Dn */
uae_u32 REGPARAM2 op_c038_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = m68k_dreg(regs, dstreg);
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (3/0) */
/* 4 0,0   */

/* AND.B (xxx).L,Dn */
uae_u32 REGPARAM2 op_c039_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	srca |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = m68k_dreg(regs, dstreg);
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (4/0) */
/* 6 0,0   */

/* AND.B (d16,PC),Dn */
uae_u32 REGPARAM2 op_c03a_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_getpci() + 2;
	srca += (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 2);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = m68k_dreg(regs, dstreg);
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (3/0) */
/* 4 0,0   */

/* AND.B (d8,PC,Xn),Dn */
uae_u32 REGPARAM2 op_c03b_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	uaecptr tmppc = m68k_getpci() + 2;
	BusCyclePenalty += 2;
	srca = get_disp_ea_000(tmppc, get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 2);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = m68k_dreg(regs, dstreg);
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 14 * CYCLE_UNIT / 2 + count_cycles;
}
/* 14 (3/0) */
/* 4 4,0   */

/* AND.B #<data>.B,Dn */
uae_u32 REGPARAM2 op_c03c_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 8;  
	uae_s8 src = (uae_u8)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = m68k_dreg(regs, dstreg);
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8 (2/0) */
/* 4 0,0   */

/* AND.W Dn,Dn */
uae_u32 REGPARAM2 op_c040_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 4;  
	uae_s16 src = m68k_dreg(regs, srcreg);
	uae_s16 dst = m68k_dreg(regs, dstreg);
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 4 * CYCLE_UNIT / 2 + count_cycles;
}
/* 4 (1/0) */
/* 2 0,0   */

/* AND.W (An),Dn */
uae_u32 REGPARAM2 op_c050_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 4;  
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access2(opcode, srca, 1, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
	if(!loop_mode) {
		regs.ir = regs.irc;
		opcode = regs.ir;
		get_word_000_prefetch(4);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return 4 * CYCLE_UNIT / 2 + count_cycles;
		}
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	if (loop_mode) {
		count_cycles += 4 * CYCLE_UNIT / 2;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return 4 * CYCLE_UNIT / 2 + count_cycles;
}
/* 4+ (1/0) */
/* 2 0,0   */

/* AND.W (An)+,Dn */
uae_u32 REGPARAM2 op_c058_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 4;  
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_areg(regs, srcreg) += 2 + 0;
		m68k_incpci(2);
		exception3_read_access2(opcode, srca, 1, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) += 2 + 0;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) += 2;
	uae_s16 dst = m68k_dreg(regs, dstreg);
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
	if(!loop_mode) {
		regs.ir = regs.irc;
		opcode = regs.ir;
		get_word_000_prefetch(4);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return 4 * CYCLE_UNIT / 2 + count_cycles;
		}
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	if (loop_mode) {
		count_cycles += 4 * CYCLE_UNIT / 2;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return 4 * CYCLE_UNIT / 2 + count_cycles;
}
/* 4+ (1/0) */
/* 2 0,0   */

/* AND.W -(An),Dn */
uae_u32 REGPARAM2 op_c060_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 6;  
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - 2;
	if (srca & 1) {
		m68k_areg(regs, srcreg) = srca;
		m68k_incpci(2);
		exception3_read_access2(opcode, srca, 1, 1);
		return 2 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) = srca;
	uae_s16 dst = m68k_dreg(regs, dstreg);
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
	if(!loop_mode) {
		regs.ir = regs.irc;
		opcode = regs.ir;
		get_word_000_prefetch(4);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return 6 * CYCLE_UNIT / 2 + count_cycles;
		}
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	if (loop_mode) {
		count_cycles += 4 * CYCLE_UNIT / 2;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return 6 * CYCLE_UNIT / 2 + count_cycles;
}
/* 6+ (1/0) */
/* 2 0,0   */

/* AND.W (d16,An),Dn */
uae_u32 REGPARAM2 op_c068_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (3/0) */
/* 4 0,0   */

/* AND.W (d8,An,Xn),Dn */
uae_u32 REGPARAM2 op_c070_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	BusCyclePenalty += 2;
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 14 * CYCLE_UNIT / 2 + count_cycles;
}
/* 14 (3/0) */
/* 4 4,0   */

/* AND.W (xxx).W,Dn */
uae_u32 REGPARAM2 op_c078_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, srca, 1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (3/0) */
/* 4 0,0   */

/* AND.W (xxx).L,Dn */
uae_u32 REGPARAM2 op_c079_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	srca |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, srca, 1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (4/0) */
/* 6 0,0   */

/* AND.W (d16,PC),Dn */
uae_u32 REGPARAM2 op_c07a_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_getpci() + 2;
	srca += (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (3/0) */
/* 4 0,0   */

/* AND.W (d8,PC,Xn),Dn */
uae_u32 REGPARAM2 op_c07b_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	uaecptr tmppc = m68k_getpci() + 2;
	BusCyclePenalty += 2;
	srca = get_disp_ea_000(tmppc, get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 14 * CYCLE_UNIT / 2 + count_cycles;
}
/* 14 (3/0) */
/* 4 4,0   */

/* AND.W #<data>.W,Dn */
uae_u32 REGPARAM2 op_c07c_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 8;  
	uae_s16 src = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8 (2/0) */
/* 4 0,0   */

/* AND.L Dn,Dn */
uae_u32 REGPARAM2 op_c080_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 6;  
	uae_s32 src = m68k_dreg(regs, srcreg);
	uae_s32 dst = m68k_dreg(regs, dstreg);
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		m68k_dreg(regs, dstreg) = (src);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_dreg(regs, dstreg) = (src);
	m68k_incpci(2);
	return 6 * CYCLE_UNIT / 2 + count_cycles;
}
/* 6 (1/0) */
/* 2 0,0   */

/* AND.L (An),Dn */
uae_u32 REGPARAM2 op_c090_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 10; 
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_000_prefetch(4);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			int pcoffset = 0;
			m68k_dreg(regs, dstreg) = (src);
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return 8 * CYCLE_UNIT / 2 + count_cycles;
		}
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	if(loop_mode & 0xfffe) {
		count_cycles += (loop_mode & 0xfffe) * CYCLE_UNIT / 2;
		loop_mode = 1;
	}
	m68k_dreg(regs, dstreg) = (src);
	if (loop_mode) {
		count_cycles += 4 * CYCLE_UNIT / 2;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return 10 * CYCLE_UNIT / 2 + count_cycles;
}
/* 10+ (2/0) */
/* 2 0,0   */

/* AND.L (An)+,Dn */
uae_u32 REGPARAM2 op_c098_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 10; 
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) += 4;
	uae_s32 dst = m68k_dreg(regs, dstreg);
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_000_prefetch(4);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			int pcoffset = 0;
			m68k_dreg(regs, dstreg) = (src);
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return 8 * CYCLE_UNIT / 2 + count_cycles;
		}
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	if(loop_mode & 0xfffe) {
		count_cycles += (loop_mode & 0xfffe) * CYCLE_UNIT / 2;
		loop_mode = 1;
	}
	m68k_dreg(regs, dstreg) = (src);
	if (loop_mode) {
		count_cycles += 4 * CYCLE_UNIT / 2;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return 10 * CYCLE_UNIT / 2 + count_cycles;
}
/* 10+ (2/0) */
/* 2 0,0   */

/* AND.L -(An),Dn */
uae_u32 REGPARAM2 op_c0a0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 12; 
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - 4;
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return 2 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) = srca;
	uae_s32 dst = m68k_dreg(regs, dstreg);
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_000_prefetch(4);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			int pcoffset = 0;
			m68k_dreg(regs, dstreg) = (src);
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return 10 * CYCLE_UNIT / 2 + count_cycles;
		}
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	if(loop_mode & 0xfffe) {
		count_cycles += (loop_mode & 0xfffe) * CYCLE_UNIT / 2;
		loop_mode = 1;
	}
	m68k_dreg(regs, dstreg) = (src);
	if (loop_mode) {
		count_cycles += 4 * CYCLE_UNIT / 2;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12+ (2/0) */
/* 2 0,0   */

/* AND.L (d16,An),Dn */
uae_u32 REGPARAM2 op_c0a8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		m68k_dreg(regs, dstreg) = (src);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_dreg(regs, dstreg) = (src);
	m68k_incpci(4);
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (4/0) */
/* 4 0,0   */

/* AND.L (d8,An,Xn),Dn */
uae_u32 REGPARAM2 op_c0b0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	BusCyclePenalty += 2;
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		m68k_dreg(regs, dstreg) = (src);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_dreg(regs, dstreg) = (src);
	m68k_incpci(4);
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (4/0) */
/* 4 4,0   */

/* AND.L (xxx).W,Dn */
uae_u32 REGPARAM2 op_c0b8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, srca, 2, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		m68k_dreg(regs, dstreg) = (src);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_dreg(regs, dstreg) = (src);
	m68k_incpci(4);
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (4/0) */
/* 4 0,0   */

/* AND.L (xxx).L,Dn */
uae_u32 REGPARAM2 op_c0b9_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 22; 
	uaecptr srca;
	srca = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	srca |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, srca, 2, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		m68k_dreg(regs, dstreg) = (src);
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_dreg(regs, dstreg) = (src);
	m68k_incpci(6);
	return 22 * CYCLE_UNIT / 2 + count_cycles;
}
/* 22 (5/0) */
/* 6 0,0   */

/* AND.L (d16,PC),Dn */
uae_u32 REGPARAM2 op_c0ba_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	srca = m68k_getpci() + 2;
	srca += (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 2);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		m68k_dreg(regs, dstreg) = (src);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_dreg(regs, dstreg) = (src);
	m68k_incpci(4);
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (4/0) */
/* 4 0,0   */

/* AND.L (d8,PC,Xn),Dn */
uae_u32 REGPARAM2 op_c0bb_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	uaecptr tmppc = m68k_getpci() + 2;
	BusCyclePenalty += 2;
	srca = get_disp_ea_000(tmppc, get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 2);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		m68k_dreg(regs, dstreg) = (src);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_dreg(regs, dstreg) = (src);
	m68k_incpci(4);
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (4/0) */
/* 4 4,0   */

/* AND.L #<data>.L,Dn */
uae_u32 REGPARAM2 op_c0bc_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 16; 
	uae_s32 src;
	src = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		m68k_dreg(regs, dstreg) = (src);
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_dreg(regs, dstreg) = (src);
	m68k_incpci(6);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/0) */
/* 6 0,0   */

/* MULU.W Dn,Dn */
uae_u32 REGPARAM2 op_c0c0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 62;
	CurrentInstrCycles = 4;  
	uae_s16 src = m68k_dreg(regs, srcreg);
	uae_s16 dst = m68k_dreg(regs, dstreg);
	regs.ir = regs.irc;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();
		SET_ZFLG(1);
		pcoffset -= 2;
		m68k_dreg(regs, dstreg) &= 0xffff0000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	uae_u32 newv = (uae_u32)(uae_u16)dst * (uae_u32)(uae_u16)src;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_NFLG(((uae_s32)(newv)) < 0);
	count_cycles += (getMulu68kCycles(src)) * CYCLE_UNIT / 2;
	m68k_dreg(regs, dstreg) = (newv);
	m68k_incpci(2);
	return 4 * CYCLE_UNIT / 2 + count_cycles;
}
/* 4+ (1/0) */
/* 2 0,0   */

/* MULU.W (An),Dn */
uae_u32 REGPARAM2 op_c0d0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 62;
	CurrentInstrCycles = 8;  
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access2(opcode, srca, 1, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	regs.ir = regs.irc;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();
		SET_ZFLG(1);
		pcoffset -= 2;
		m68k_dreg(regs, dstreg) &= 0xffff0000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	uae_u32 newv = (uae_u32)(uae_u16)dst * (uae_u32)(uae_u16)src;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_NFLG(((uae_s32)(newv)) < 0);
	count_cycles += (getMulu68kCycles(src)) * CYCLE_UNIT / 2;
	m68k_dreg(regs, dstreg) = (newv);
	m68k_incpci(2);
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8+ (2/0) */
/* 2 0,0   */

/* MULU.W (An)+,Dn */
uae_u32 REGPARAM2 op_c0d8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 62;
	CurrentInstrCycles = 8;  
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_areg(regs, srcreg) += 2 + 0;
		m68k_incpci(2);
		exception3_read_access2(opcode, srca, 1, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) += 2 + 0;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) += 2;
	uae_s16 dst = m68k_dreg(regs, dstreg);
	regs.ir = regs.irc;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();
		SET_ZFLG(1);
		pcoffset -= 2;
		m68k_dreg(regs, dstreg) &= 0xffff0000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	uae_u32 newv = (uae_u32)(uae_u16)dst * (uae_u32)(uae_u16)src;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_NFLG(((uae_s32)(newv)) < 0);
	count_cycles += (getMulu68kCycles(src)) * CYCLE_UNIT / 2;
	m68k_dreg(regs, dstreg) = (newv);
	m68k_incpci(2);
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8+ (2/0) */
/* 2 0,0   */

/* MULU.W -(An),Dn */
uae_u32 REGPARAM2 op_c0e0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 62;
	CurrentInstrCycles = 10; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - 2;
	if (srca & 1) {
		m68k_areg(regs, srcreg) = srca;
		m68k_incpci(2);
		exception3_read_access2(opcode, srca, 1, 1);
		return 2 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) = srca;
	uae_s16 dst = m68k_dreg(regs, dstreg);
	regs.ir = regs.irc;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();
		SET_ZFLG(1);
		pcoffset -= 0;
		m68k_dreg(regs, dstreg) &= 0xffff0000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	uae_u32 newv = (uae_u32)(uae_u16)dst * (uae_u32)(uae_u16)src;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_NFLG(((uae_s32)(newv)) < 0);
	count_cycles += (getMulu68kCycles(src)) * CYCLE_UNIT / 2;
	m68k_dreg(regs, dstreg) = (newv);
	m68k_incpci(2);
	return 10 * CYCLE_UNIT / 2 + count_cycles;
}
/* 10+ (2/0) */
/* 2 0,0   */

/* MULU.W (d16,An),Dn */
uae_u32 REGPARAM2 op_c0e8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 62;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();
		SET_ZFLG(1);
		pcoffset -= 4;
		m68k_dreg(regs, dstreg) &= 0xffff0000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	uae_u32 newv = (uae_u32)(uae_u16)dst * (uae_u32)(uae_u16)src;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_NFLG(((uae_s32)(newv)) < 0);
	count_cycles += (getMulu68kCycles(src)) * CYCLE_UNIT / 2;
	m68k_dreg(regs, dstreg) = (newv);
	m68k_incpci(4);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12+ (3/0) */
/* 4 0,0   */

/* MULU.W (d8,An,Xn),Dn */
uae_u32 REGPARAM2 op_c0f0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 62;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	BusCyclePenalty += 2;
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();
		SET_ZFLG(1);
		pcoffset -= 4;
		m68k_dreg(regs, dstreg) &= 0xffff0000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	uae_u32 newv = (uae_u32)(uae_u16)dst * (uae_u32)(uae_u16)src;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_NFLG(((uae_s32)(newv)) < 0);
	count_cycles += (getMulu68kCycles(src)) * CYCLE_UNIT / 2;
	m68k_dreg(regs, dstreg) = (newv);
	m68k_incpci(4);
	return 14 * CYCLE_UNIT / 2 + count_cycles;
}
/* 14+ (3/0) */
/* 4 4,0   */

/* MULU.W (xxx).W,Dn */
uae_u32 REGPARAM2 op_c0f8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 62;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, srca, 1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();
		SET_ZFLG(1);
		pcoffset -= 2;
		m68k_dreg(regs, dstreg) &= 0xffff0000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	uae_u32 newv = (uae_u32)(uae_u16)dst * (uae_u32)(uae_u16)src;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_NFLG(((uae_s32)(newv)) < 0);
	count_cycles += (getMulu68kCycles(src)) * CYCLE_UNIT / 2;
	m68k_dreg(regs, dstreg) = (newv);
	m68k_incpci(4);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12+ (3/0) */
/* 4 0,0   */

/* MULU.W (xxx).L,Dn */
uae_u32 REGPARAM2 op_c0f9_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 62;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	srca |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, srca, 1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	regs.ir = regs.irc;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();
		SET_ZFLG(1);
		pcoffset -= 2;
		m68k_dreg(regs, dstreg) &= 0xffff0000;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	uae_u32 newv = (uae_u32)(uae_u16)dst * (uae_u32)(uae_u16)src;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_NFLG(((uae_s32)(newv)) < 0);
	count_cycles += (getMulu68kCycles(src)) * CYCLE_UNIT / 2;
	m68k_dreg(regs, dstreg) = (newv);
	m68k_incpci(6);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16+ (4/0) */
/* 6 0,0   */

/* MULU.W (d16,PC),Dn */
uae_u32 REGPARAM2 op_c0fa_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 62;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_getpci() + 2;
	srca += (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();
		SET_ZFLG(1);
		pcoffset -= 4;
		m68k_dreg(regs, dstreg) &= 0xffff0000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	uae_u32 newv = (uae_u32)(uae_u16)dst * (uae_u32)(uae_u16)src;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_NFLG(((uae_s32)(newv)) < 0);
	count_cycles += (getMulu68kCycles(src)) * CYCLE_UNIT / 2;
	m68k_dreg(regs, dstreg) = (newv);
	m68k_incpci(4);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12+ (3/0) */
/* 4 0,0   */

/* MULU.W (d8,PC,Xn),Dn */
uae_u32 REGPARAM2 op_c0fb_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 62;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	uaecptr tmppc = m68k_getpci() + 2;
	BusCyclePenalty += 2;
	srca = get_disp_ea_000(tmppc, get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();
		SET_ZFLG(1);
		pcoffset -= 4;
		m68k_dreg(regs, dstreg) &= 0xffff0000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	uae_u32 newv = (uae_u32)(uae_u16)dst * (uae_u32)(uae_u16)src;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_NFLG(((uae_s32)(newv)) < 0);
	count_cycles += (getMulu68kCycles(src)) * CYCLE_UNIT / 2;
	m68k_dreg(regs, dstreg) = (newv);
	m68k_incpci(4);
	return 14 * CYCLE_UNIT / 2 + count_cycles;
}
/* 14+ (3/0) */
/* 4 4,0   */

/* MULU.W #<data>.W,Dn */
uae_u32 REGPARAM2 op_c0fc_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 62;
	CurrentInstrCycles = 8;  
	uae_s16 src = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();
		SET_ZFLG(1);
		pcoffset -= 2;
		m68k_dreg(regs, dstreg) &= 0xffff0000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	uae_u32 newv = (uae_u32)(uae_u16)dst * (uae_u32)(uae_u16)src;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_NFLG(((uae_s32)(newv)) < 0);
	count_cycles += (getMulu68kCycles(src)) * CYCLE_UNIT / 2;
	m68k_dreg(regs, dstreg) = (newv);
	m68k_incpci(4);
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8+ (2/0) */
/* 4 0,0   */

/* ABCD.B Dn,Dn */
uae_u32 REGPARAM2 op_c100_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 14;
	CurrentInstrCycles = 6;  
	uae_s8 src = m68k_dreg(regs, srcreg);
	uae_s8 dst = m68k_dreg(regs, dstreg);
	uae_u16 newv_lo = (src & 0xF) + (dst & 0xF) + (GET_XFLG() ? 1 : 0);
	uae_u16 newv_hi = (src & 0xF0) + (dst & 0xF0);
	uae_u16 newv, tmp_newv;
	int cflg;
	newv = tmp_newv = newv_hi + newv_lo;if (newv_lo > 9) { newv += 6; }
	cflg = (newv & 0x3F0) > 0x90;
	if (cflg) newv += 0x60;
	SET_CFLG(cflg);
	COPY_CARRY();
	SET_ZFLG(GET_ZFLG() & (((uae_s8)(newv)) == 0));
	SET_NFLG(((uae_s8)(newv)) < 0);
	SET_VFLG((tmp_newv & 0x80) == 0 && (newv & 0x80) != 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
	m68k_incpci(2);
	return 6 * CYCLE_UNIT / 2 + count_cycles;
}
/* 6 (1/0) */
/* 2 0,0   */

/* ABCD.B -(An),-(An) */
uae_u32 REGPARAM2 op_c108_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 14;
	CurrentInstrCycles = 14; 
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) = srca;
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, dstreg) = dsta;
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) = dsta;
	uae_u16 newv_lo = (src & 0xF) + (dst & 0xF) + (GET_XFLG() ? 1 : 0);
	uae_u16 newv_hi = (src & 0xF0) + (dst & 0xF0);
	uae_u16 newv, tmp_newv;
	int cflg;
	newv = tmp_newv = newv_hi + newv_lo;if (newv_lo > 9) { newv += 6; }
	cflg = (newv & 0x3F0) > 0x90;
	if (cflg) newv += 0x60;
	SET_CFLG(cflg);
	COPY_CARRY();
	SET_ZFLG(GET_ZFLG() & (((uae_s8)(newv)) == 0));
	SET_NFLG(((uae_s8)(newv)) < 0);
	SET_VFLG((tmp_newv & 0x80) == 0 && (newv & 0x80) != 0);
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_000_prefetch(4);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return 10 * CYCLE_UNIT / 2 + count_cycles;
		}
		opcode = regs.ir;
	} else {
		loop_mode = 0;
		loop_mode |= 6;
		loop_mode |= 6 << 16;
	}
	if(loop_mode & 0xfffe) {
		count_cycles += (loop_mode & 0xfffe) * CYCLE_UNIT / 2;
		loop_mode = 1;
	}
	put_byte_000(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x0, newv, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return 14 * CYCLE_UNIT / 2 + count_cycles;
}
/* 14+ (2/1) */
/* 2 0,0   */

/* AND.B Dn,(An) */
uae_u32 REGPARAM2 op_c110_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 8;  
	int loop_mode = regs.loop_mode;
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_000_prefetch(4);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return 4 * CYCLE_UNIT / 2 + count_cycles;
		}
		opcode = regs.ir;
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	if(loop_mode & 0xfffe) {
		count_cycles += (loop_mode & 0xfffe) * CYCLE_UNIT / 2;
		loop_mode = 1;
	}
	put_byte_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8+ (1/1) */
/* 2 0,0   */

/* AND.B Dn,(An)+ */
uae_u32 REGPARAM2 op_c118_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 8;  
	int loop_mode = regs.loop_mode;
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_000_prefetch(4);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return 4 * CYCLE_UNIT / 2 + count_cycles;
		}
		opcode = regs.ir;
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	if(loop_mode & 0xfffe) {
		count_cycles += (loop_mode & 0xfffe) * CYCLE_UNIT / 2;
		loop_mode = 1;
	}
	put_byte_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8+ (1/1) */
/* 2 0,0   */

/* AND.B Dn,-(An) */
uae_u32 REGPARAM2 op_c120_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 10; 
	int loop_mode = regs.loop_mode;
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, dstreg) = dsta;
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) = dsta;
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_000_prefetch(4);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return 6 * CYCLE_UNIT / 2 + count_cycles;
		}
		opcode = regs.ir;
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	if(loop_mode & 0xfffe) {
		count_cycles += (loop_mode & 0xfffe) * CYCLE_UNIT / 2;
		loop_mode = 1;
	}
	put_byte_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return 10 * CYCLE_UNIT / 2 + count_cycles;
}
/* 10+ (1/1) */
/* 2 0,0   */

/* AND.B Dn,(d16,An) */
uae_u32 REGPARAM2 op_c128_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 16; 
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_byte_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 4 0,0   */

/* AND.B Dn,(d8,An,Xn) */
uae_u32 REGPARAM2 op_c130_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 18; 
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	BusCyclePenalty += 2;
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_byte_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (3/1) */
/* 4 4,0   */

/* AND.B Dn,(xxx).W */
uae_u32 REGPARAM2 op_c138_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	OpcodeFamily = 2;
	CurrentInstrCycles = 16; 
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_byte_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 4 0,0   */

/* AND.B Dn,(xxx).L */
uae_u32 REGPARAM2 op_c139_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	OpcodeFamily = 2;
	CurrentInstrCycles = 20; 
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	dsta |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_byte_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (4/1) */
/* 6 0,0   */

/* EXG.L Dn,Dn */
uae_u32 REGPARAM2 op_c140_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 35;
	CurrentInstrCycles = 6;  
	uae_s32 src = m68k_dreg(regs, srcreg);
	uae_s32 dst = m68k_dreg(regs, dstreg);
	m68k_dreg(regs, srcreg) = (dst);
	m68k_dreg(regs, dstreg) = (src);
	regs.ir = regs.irc;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	m68k_incpci(2);
	return 6 * CYCLE_UNIT / 2 + count_cycles;
}
/* 6 (1/0) */
/* 2 0,0   */

/* EXG.L An,An */
uae_u32 REGPARAM2 op_c148_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 35;
	CurrentInstrCycles = 6;  
	uae_s32 src = m68k_areg(regs, srcreg);
	uae_s32 dst = m68k_areg(regs, dstreg);
	m68k_areg(regs, srcreg) = (dst);
	m68k_areg(regs, dstreg) = (src);
	regs.ir = regs.irc;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	m68k_incpci(2);
	return 6 * CYCLE_UNIT / 2 + count_cycles;
}
/* 6 (1/0) */
/* 2 0,0   */

/* AND.W Dn,(An) */
uae_u32 REGPARAM2 op_c150_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 8;  
	int loop_mode = regs.loop_mode;
	uae_s16 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	if (dsta & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dsta, 1, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = get_word_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_000_prefetch(4);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return 4 * CYCLE_UNIT / 2 + count_cycles;
		}
		opcode = regs.ir;
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	if(loop_mode & 0xfffe) {
		count_cycles += (loop_mode & 0xfffe) * CYCLE_UNIT / 2;
		loop_mode = 1;
	}
	put_word_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8+ (1/1) */
/* 2 0,0   */

/* AND.W Dn,(An)+ */
uae_u32 REGPARAM2 op_c158_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 8;  
	int loop_mode = regs.loop_mode;
	uae_s16 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	if (dsta & 1) {
		m68k_areg(regs, dstreg) += 2 + 0;
		m68k_incpci(2);
		exception3_read_access(opcode, dsta, 1, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = get_word_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, dstreg) += 2 + 0;
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) += 2;
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_000_prefetch(4);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return 4 * CYCLE_UNIT / 2 + count_cycles;
		}
		opcode = regs.ir;
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	if(loop_mode & 0xfffe) {
		count_cycles += (loop_mode & 0xfffe) * CYCLE_UNIT / 2;
		loop_mode = 1;
	}
	put_word_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8+ (1/1) */
/* 2 0,0   */

/* AND.W Dn,-(An) */
uae_u32 REGPARAM2 op_c160_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 10; 
	int loop_mode = regs.loop_mode;
	uae_s16 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - 2;
	if (dsta & 1) {
		m68k_areg(regs, dstreg) = dsta;
		m68k_incpci(2);
		exception3_read_access(opcode, dsta, 1, 1);
		return 2 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = get_word_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, dstreg) = dsta;
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) = dsta;
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_000_prefetch(4);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return 6 * CYCLE_UNIT / 2 + count_cycles;
		}
		opcode = regs.ir;
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	if(loop_mode & 0xfffe) {
		count_cycles += (loop_mode & 0xfffe) * CYCLE_UNIT / 2;
		loop_mode = 1;
	}
	put_word_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return 10 * CYCLE_UNIT / 2 + count_cycles;
}
/* 10+ (1/1) */
/* 2 0,0   */

/* AND.W Dn,(d16,An) */
uae_u32 REGPARAM2 op_c168_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 16; 
	uae_s16 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dsta, 1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = get_word_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_word_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 4 0,0   */

/* AND.W Dn,(d8,An,Xn) */
uae_u32 REGPARAM2 op_c170_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 18; 
	uae_s16 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	BusCyclePenalty += 2;
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dsta, 1, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = get_word_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_word_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (3/1) */
/* 4 4,0   */

/* AND.W Dn,(xxx).W */
uae_u32 REGPARAM2 op_c178_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	OpcodeFamily = 2;
	CurrentInstrCycles = 16; 
	uae_s16 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, dsta, 1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = get_word_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_word_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 4 0,0   */

/* AND.W Dn,(xxx).L */
uae_u32 REGPARAM2 op_c179_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	OpcodeFamily = 2;
	CurrentInstrCycles = 20; 
	uae_s16 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	dsta |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, dsta, 1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = get_word_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_word_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (4/1) */
/* 6 0,0   */

/* EXG.L Dn,An */
uae_u32 REGPARAM2 op_c188_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 35;
	CurrentInstrCycles = 6;  
	uae_s32 src = m68k_dreg(regs, srcreg);
	uae_s32 dst = m68k_areg(regs, dstreg);
	m68k_dreg(regs, srcreg) = (dst);
	m68k_areg(regs, dstreg) = (src);
	regs.ir = regs.irc;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	m68k_incpci(2);
	return 6 * CYCLE_UNIT / 2 + count_cycles;
}
/* 6 (1/0) */
/* 2 0,0   */

/* AND.L Dn,(An) */
uae_u32 REGPARAM2 op_c190_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 16; 
	int loop_mode = regs.loop_mode;
	uae_s32 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	if (dsta & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dsta, 2, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = get_word_000(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	dst |= get_word_000(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_000_prefetch(4);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			int pcoffset = 0;
			ccr_68000_long_move_ae_LZN(src);
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return 8 * CYCLE_UNIT / 2 + count_cycles;
		}
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	if(loop_mode & 0xfffe) {
		count_cycles += (loop_mode & 0xfffe) * CYCLE_UNIT / 2;
		loop_mode = 1;
	}
	put_word_000(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src >> 16); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16+ (2/2) */
/* 2 0,0   */

/* AND.L Dn,(An)+ */
uae_u32 REGPARAM2 op_c198_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 16; 
	int loop_mode = regs.loop_mode;
	uae_s32 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	if (dsta & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dsta, 2, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = get_word_000(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	dst |= get_word_000(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) += 4;
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_000_prefetch(4);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			int pcoffset = 0;
			ccr_68000_long_move_ae_LZN(src);
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return 8 * CYCLE_UNIT / 2 + count_cycles;
		}
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	if(loop_mode & 0xfffe) {
		count_cycles += (loop_mode & 0xfffe) * CYCLE_UNIT / 2;
		loop_mode = 1;
	}
	put_word_000(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src >> 16); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16+ (2/2) */
/* 2 0,0   */

/* AND.L Dn,-(An) */
uae_u32 REGPARAM2 op_c1a0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 18; 
	int loop_mode = regs.loop_mode;
	uae_s32 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - 4;
	if (dsta & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dsta, 2, 1);
		return 2 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = get_word_000(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	dst |= get_word_000(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, dstreg) = dsta;
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) = dsta;
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_000_prefetch(4);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			int pcoffset = 0;
			ccr_68000_long_move_ae_LZN(src);
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return 10 * CYCLE_UNIT / 2 + count_cycles;
		}
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	if(loop_mode & 0xfffe) {
		count_cycles += (loop_mode & 0xfffe) * CYCLE_UNIT / 2;
		loop_mode = 1;
	}
	put_word_000(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src >> 16); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18+ (2/2) */
/* 2 0,0   */

/* AND.L Dn,(d16,An) */
uae_u32 REGPARAM2 op_c1a8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 24; 
	uae_s32 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dsta, 2, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = get_word_000(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	dst |= get_word_000(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src >> 16); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 24 * CYCLE_UNIT / 2 + count_cycles;
}
/* 24 (4/2) */
/* 4 0,0   */

/* AND.L Dn,(d8,An,Xn) */
uae_u32 REGPARAM2 op_c1b0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 26; 
	uae_s32 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	BusCyclePenalty += 2;
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dsta, 2, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = get_word_000(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	dst |= get_word_000(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return 22 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src >> 16); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return 26 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 26 * CYCLE_UNIT / 2 + count_cycles;
}
/* 26 (4/2) */
/* 4 4,0   */

/* AND.L Dn,(xxx).W */
uae_u32 REGPARAM2 op_c1b8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	OpcodeFamily = 2;
	CurrentInstrCycles = 24; 
	uae_s32 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, dsta, 2, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = get_word_000(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	dst |= get_word_000(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src >> 16); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 24 * CYCLE_UNIT / 2 + count_cycles;
}
/* 24 (4/2) */
/* 4 0,0   */

/* AND.L Dn,(xxx).L */
uae_u32 REGPARAM2 op_c1b9_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	OpcodeFamily = 2;
	CurrentInstrCycles = 28; 
	uae_s32 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	dsta |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, dsta, 2, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = get_word_000(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	dst |= get_word_000(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src >> 16); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return 28 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 28 * CYCLE_UNIT / 2 + count_cycles;
}
/* 28 (5/2) */
/* 6 0,0   */

/* MULS.W Dn,Dn */
uae_u32 REGPARAM2 op_c1c0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 63;
	CurrentInstrCycles = 4;  
	uae_s16 src = m68k_dreg(regs, srcreg);
	uae_s16 dst = m68k_dreg(regs, dstreg);
	regs.ir = regs.irc;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();
		SET_ZFLG(1);
		pcoffset -= 2;
		m68k_dreg(regs, dstreg) &= 0xffff0000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	uae_u32 newv = (uae_s32)(uae_s16)dst * (uae_s32)(uae_s16)src;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_NFLG(((uae_s32)(newv)) < 0);
	count_cycles += (getMuls68kCycles(src)) * CYCLE_UNIT / 2;
	m68k_dreg(regs, dstreg) = (newv);
	m68k_incpci(2);
	return 4 * CYCLE_UNIT / 2 + count_cycles;
}
/* 4+ (1/0) */
/* 2 0,0   */

/* MULS.W (An),Dn */
uae_u32 REGPARAM2 op_c1d0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 63;
	CurrentInstrCycles = 8;  
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access2(opcode, srca, 1, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	regs.ir = regs.irc;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();
		SET_ZFLG(1);
		pcoffset -= 2;
		m68k_dreg(regs, dstreg) &= 0xffff0000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	uae_u32 newv = (uae_s32)(uae_s16)dst * (uae_s32)(uae_s16)src;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_NFLG(((uae_s32)(newv)) < 0);
	count_cycles += (getMuls68kCycles(src)) * CYCLE_UNIT / 2;
	m68k_dreg(regs, dstreg) = (newv);
	m68k_incpci(2);
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8+ (2/0) */
/* 2 0,0   */

/* MULS.W (An)+,Dn */
uae_u32 REGPARAM2 op_c1d8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 63;
	CurrentInstrCycles = 8;  
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_areg(regs, srcreg) += 2 + 0;
		m68k_incpci(2);
		exception3_read_access2(opcode, srca, 1, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) += 2 + 0;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) += 2;
	uae_s16 dst = m68k_dreg(regs, dstreg);
	regs.ir = regs.irc;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();
		SET_ZFLG(1);
		pcoffset -= 2;
		m68k_dreg(regs, dstreg) &= 0xffff0000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	uae_u32 newv = (uae_s32)(uae_s16)dst * (uae_s32)(uae_s16)src;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_NFLG(((uae_s32)(newv)) < 0);
	count_cycles += (getMuls68kCycles(src)) * CYCLE_UNIT / 2;
	m68k_dreg(regs, dstreg) = (newv);
	m68k_incpci(2);
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8+ (2/0) */
/* 2 0,0   */

/* MULS.W -(An),Dn */
uae_u32 REGPARAM2 op_c1e0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 63;
	CurrentInstrCycles = 10; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - 2;
	if (srca & 1) {
		m68k_areg(regs, srcreg) = srca;
		m68k_incpci(2);
		exception3_read_access2(opcode, srca, 1, 1);
		return 2 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) = srca;
	uae_s16 dst = m68k_dreg(regs, dstreg);
	regs.ir = regs.irc;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();
		SET_ZFLG(1);
		pcoffset -= 0;
		m68k_dreg(regs, dstreg) &= 0xffff0000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	uae_u32 newv = (uae_s32)(uae_s16)dst * (uae_s32)(uae_s16)src;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_NFLG(((uae_s32)(newv)) < 0);
	count_cycles += (getMuls68kCycles(src)) * CYCLE_UNIT / 2;
	m68k_dreg(regs, dstreg) = (newv);
	m68k_incpci(2);
	return 10 * CYCLE_UNIT / 2 + count_cycles;
}
/* 10+ (2/0) */
/* 2 0,0   */

/* MULS.W (d16,An),Dn */
uae_u32 REGPARAM2 op_c1e8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 63;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();
		SET_ZFLG(1);
		pcoffset -= 4;
		m68k_dreg(regs, dstreg) &= 0xffff0000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	uae_u32 newv = (uae_s32)(uae_s16)dst * (uae_s32)(uae_s16)src;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_NFLG(((uae_s32)(newv)) < 0);
	count_cycles += (getMuls68kCycles(src)) * CYCLE_UNIT / 2;
	m68k_dreg(regs, dstreg) = (newv);
	m68k_incpci(4);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12+ (3/0) */
/* 4 0,0   */

/* MULS.W (d8,An,Xn),Dn */
uae_u32 REGPARAM2 op_c1f0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 63;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	BusCyclePenalty += 2;
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();
		SET_ZFLG(1);
		pcoffset -= 4;
		m68k_dreg(regs, dstreg) &= 0xffff0000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	uae_u32 newv = (uae_s32)(uae_s16)dst * (uae_s32)(uae_s16)src;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_NFLG(((uae_s32)(newv)) < 0);
	count_cycles += (getMuls68kCycles(src)) * CYCLE_UNIT / 2;
	m68k_dreg(regs, dstreg) = (newv);
	m68k_incpci(4);
	return 14 * CYCLE_UNIT / 2 + count_cycles;
}
/* 14+ (3/0) */
/* 4 4,0   */

/* MULS.W (xxx).W,Dn */
uae_u32 REGPARAM2 op_c1f8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 63;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, srca, 1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();
		SET_ZFLG(1);
		pcoffset -= 2;
		m68k_dreg(regs, dstreg) &= 0xffff0000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	uae_u32 newv = (uae_s32)(uae_s16)dst * (uae_s32)(uae_s16)src;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_NFLG(((uae_s32)(newv)) < 0);
	count_cycles += (getMuls68kCycles(src)) * CYCLE_UNIT / 2;
	m68k_dreg(regs, dstreg) = (newv);
	m68k_incpci(4);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12+ (3/0) */
/* 4 0,0   */

/* MULS.W (xxx).L,Dn */
uae_u32 REGPARAM2 op_c1f9_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 63;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	srca |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, srca, 1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	regs.ir = regs.irc;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();
		SET_ZFLG(1);
		pcoffset -= 2;
		m68k_dreg(regs, dstreg) &= 0xffff0000;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	uae_u32 newv = (uae_s32)(uae_s16)dst * (uae_s32)(uae_s16)src;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_NFLG(((uae_s32)(newv)) < 0);
	count_cycles += (getMuls68kCycles(src)) * CYCLE_UNIT / 2;
	m68k_dreg(regs, dstreg) = (newv);
	m68k_incpci(6);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16+ (4/0) */
/* 6 0,0   */

/* MULS.W (d16,PC),Dn */
uae_u32 REGPARAM2 op_c1fa_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 63;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_getpci() + 2;
	srca += (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();
		SET_ZFLG(1);
		pcoffset -= 4;
		m68k_dreg(regs, dstreg) &= 0xffff0000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	uae_u32 newv = (uae_s32)(uae_s16)dst * (uae_s32)(uae_s16)src;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_NFLG(((uae_s32)(newv)) < 0);
	count_cycles += (getMuls68kCycles(src)) * CYCLE_UNIT / 2;
	m68k_dreg(regs, dstreg) = (newv);
	m68k_incpci(4);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12+ (3/0) */
/* 4 0,0   */

/* MULS.W (d8,PC,Xn),Dn */
uae_u32 REGPARAM2 op_c1fb_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 63;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	uaecptr tmppc = m68k_getpci() + 2;
	BusCyclePenalty += 2;
	srca = get_disp_ea_000(tmppc, get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();
		SET_ZFLG(1);
		pcoffset -= 4;
		m68k_dreg(regs, dstreg) &= 0xffff0000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	uae_u32 newv = (uae_s32)(uae_s16)dst * (uae_s32)(uae_s16)src;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_NFLG(((uae_s32)(newv)) < 0);
	count_cycles += (getMuls68kCycles(src)) * CYCLE_UNIT / 2;
	m68k_dreg(regs, dstreg) = (newv);
	m68k_incpci(4);
	return 14 * CYCLE_UNIT / 2 + count_cycles;
}
/* 14+ (3/0) */
/* 4 4,0   */

/* MULS.W #<data>.W,Dn */
uae_u32 REGPARAM2 op_c1fc_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 63;
	CurrentInstrCycles = 8;  
	uae_s16 src = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();
		SET_ZFLG(1);
		pcoffset -= 2;
		m68k_dreg(regs, dstreg) &= 0xffff0000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	uae_u32 newv = (uae_s32)(uae_s16)dst * (uae_s32)(uae_s16)src;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_NFLG(((uae_s32)(newv)) < 0);
	count_cycles += (getMuls68kCycles(src)) * CYCLE_UNIT / 2;
	m68k_dreg(regs, dstreg) = (newv);
	m68k_incpci(4);
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8+ (2/0) */
/* 4 0,0   */

/* ADD.B Dn,Dn */
uae_u32 REGPARAM2 op_d000_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 4;  
	uae_s8 src = m68k_dreg(regs, srcreg);
	uae_s8 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u8)(~dst)) < ((uae_u8)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 4 * CYCLE_UNIT / 2 + count_cycles;
}
/* 4 (1/0) */
/* 2 0,0   */

/* ADD.B (An),Dn */
uae_u32 REGPARAM2 op_d010_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 4;  
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u8)(~dst)) < ((uae_u8)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
	if(!loop_mode) {
		regs.ir = regs.irc;
		opcode = regs.ir;
		get_word_000_prefetch(4);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return 4 * CYCLE_UNIT / 2 + count_cycles;
		}
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	if (loop_mode) {
		count_cycles += 4 * CYCLE_UNIT / 2;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return 4 * CYCLE_UNIT / 2 + count_cycles;
}
/* 4+ (1/0) */
/* 2 0,0   */

/* ADD.B (An)+,Dn */
uae_u32 REGPARAM2 op_d018_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 4;  
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
	uae_s8 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u8)(~dst)) < ((uae_u8)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
	if(!loop_mode) {
		regs.ir = regs.irc;
		opcode = regs.ir;
		get_word_000_prefetch(4);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return 4 * CYCLE_UNIT / 2 + count_cycles;
		}
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	if (loop_mode) {
		count_cycles += 4 * CYCLE_UNIT / 2;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return 4 * CYCLE_UNIT / 2 + count_cycles;
}
/* 4+ (1/0) */
/* 2 0,0   */

/* ADD.B -(An),Dn */
uae_u32 REGPARAM2 op_d020_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 6;  
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) = srca;
	uae_s8 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u8)(~dst)) < ((uae_u8)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
	if(!loop_mode) {
		regs.ir = regs.irc;
		opcode = regs.ir;
		get_word_000_prefetch(4);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return 6 * CYCLE_UNIT / 2 + count_cycles;
		}
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	if (loop_mode) {
		count_cycles += 4 * CYCLE_UNIT / 2;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return 6 * CYCLE_UNIT / 2 + count_cycles;
}
/* 6+ (1/0) */
/* 2 0,0   */

/* ADD.B (d16,An),Dn */
uae_u32 REGPARAM2 op_d028_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u8)(~dst)) < ((uae_u8)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (3/0) */
/* 4 0,0   */

/* ADD.B (d8,An,Xn),Dn */
uae_u32 REGPARAM2 op_d030_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	BusCyclePenalty += 2;
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u8)(~dst)) < ((uae_u8)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 14 * CYCLE_UNIT / 2 + count_cycles;
}
/* 14 (3/0) */
/* 4 4,0   */

/* ADD.B (xxx).W,Dn */
uae_u32 REGPARAM2 op_d038_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u8)(~dst)) < ((uae_u8)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (3/0) */
/* 4 0,0   */

/* ADD.B (xxx).L,Dn */
uae_u32 REGPARAM2 op_d039_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	srca |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u8)(~dst)) < ((uae_u8)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (4/0) */
/* 6 0,0   */

/* ADD.B (d16,PC),Dn */
uae_u32 REGPARAM2 op_d03a_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_getpci() + 2;
	srca += (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 2);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u8)(~dst)) < ((uae_u8)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (3/0) */
/* 4 0,0   */

/* ADD.B (d8,PC,Xn),Dn */
uae_u32 REGPARAM2 op_d03b_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	uaecptr tmppc = m68k_getpci() + 2;
	BusCyclePenalty += 2;
	srca = get_disp_ea_000(tmppc, get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 2);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u8)(~dst)) < ((uae_u8)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 14 * CYCLE_UNIT / 2 + count_cycles;
}
/* 14 (3/0) */
/* 4 4,0   */

/* ADD.B #<data>.B,Dn */
uae_u32 REGPARAM2 op_d03c_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 8;  
	uae_s8 src = (uae_u8)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u8)(~dst)) < ((uae_u8)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8 (2/0) */
/* 4 0,0   */

/* ADD.W Dn,Dn */
uae_u32 REGPARAM2 op_d040_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 4;  
	uae_s16 src = m68k_dreg(regs, srcreg);
	uae_s16 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 4 * CYCLE_UNIT / 2 + count_cycles;
}
/* 4 (1/0) */
/* 2 0,0   */

/* ADD.W An,Dn */
uae_u32 REGPARAM2 op_d048_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 4;  
	uae_s16 src = m68k_areg(regs, srcreg);
	uae_s16 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 4 * CYCLE_UNIT / 2 + count_cycles;
}
/* 4 (1/0) */
/* 2 0,0   */

/* ADD.W (An),Dn */
uae_u32 REGPARAM2 op_d050_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 4;  
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access2(opcode, srca, 1, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
	if(!loop_mode) {
		regs.ir = regs.irc;
		opcode = regs.ir;
		get_word_000_prefetch(4);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return 4 * CYCLE_UNIT / 2 + count_cycles;
		}
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	if (loop_mode) {
		count_cycles += 4 * CYCLE_UNIT / 2;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return 4 * CYCLE_UNIT / 2 + count_cycles;
}
/* 4+ (1/0) */
/* 2 0,0   */

/* ADD.W (An)+,Dn */
uae_u32 REGPARAM2 op_d058_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 4;  
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_areg(regs, srcreg) += 2 + 0;
		m68k_incpci(2);
		exception3_read_access2(opcode, srca, 1, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) += 2 + 0;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) += 2;
	uae_s16 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
	if(!loop_mode) {
		regs.ir = regs.irc;
		opcode = regs.ir;
		get_word_000_prefetch(4);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return 4 * CYCLE_UNIT / 2 + count_cycles;
		}
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	if (loop_mode) {
		count_cycles += 4 * CYCLE_UNIT / 2;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return 4 * CYCLE_UNIT / 2 + count_cycles;
}
/* 4+ (1/0) */
/* 2 0,0   */

/* ADD.W -(An),Dn */
uae_u32 REGPARAM2 op_d060_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 6;  
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - 2;
	if (srca & 1) {
		m68k_areg(regs, srcreg) = srca;
		m68k_incpci(2);
		exception3_read_access2(opcode, srca, 1, 1);
		return 2 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) = srca;
	uae_s16 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
	if(!loop_mode) {
		regs.ir = regs.irc;
		opcode = regs.ir;
		get_word_000_prefetch(4);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return 6 * CYCLE_UNIT / 2 + count_cycles;
		}
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	if (loop_mode) {
		count_cycles += 4 * CYCLE_UNIT / 2;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return 6 * CYCLE_UNIT / 2 + count_cycles;
}
/* 6+ (1/0) */
/* 2 0,0   */

/* ADD.W (d16,An),Dn */
uae_u32 REGPARAM2 op_d068_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (3/0) */
/* 4 0,0   */

/* ADD.W (d8,An,Xn),Dn */
uae_u32 REGPARAM2 op_d070_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	BusCyclePenalty += 2;
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 14 * CYCLE_UNIT / 2 + count_cycles;
}
/* 14 (3/0) */
/* 4 4,0   */

/* ADD.W (xxx).W,Dn */
uae_u32 REGPARAM2 op_d078_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, srca, 1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (3/0) */
/* 4 0,0   */

/* ADD.W (xxx).L,Dn */
uae_u32 REGPARAM2 op_d079_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	srca |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, srca, 1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (4/0) */
/* 6 0,0   */

/* ADD.W (d16,PC),Dn */
uae_u32 REGPARAM2 op_d07a_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_getpci() + 2;
	srca += (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (3/0) */
/* 4 0,0   */

/* ADD.W (d8,PC,Xn),Dn */
uae_u32 REGPARAM2 op_d07b_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	uaecptr tmppc = m68k_getpci() + 2;
	BusCyclePenalty += 2;
	srca = get_disp_ea_000(tmppc, get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 14 * CYCLE_UNIT / 2 + count_cycles;
}
/* 14 (3/0) */
/* 4 4,0   */

/* ADD.W #<data>.W,Dn */
uae_u32 REGPARAM2 op_d07c_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 8;  
	uae_s16 src = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8 (2/0) */
/* 4 0,0   */

/* ADD.L Dn,Dn */
uae_u32 REGPARAM2 op_d080_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 6;  
	uae_s32 src = m68k_dreg(regs, srcreg);
	uae_s32 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u32)(~dst)) < ((uae_u32)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		uae_s16 bnewv = (uae_s16)dst + (uae_s16)src;
		int bflgs = ((uae_s16)(src)) < 0;
		int bflgo = ((uae_s16)(dst)) < 0;
		int bflgn = bnewv < 0;
		ccr_68000_long_move_ae_LZN(bnewv);
		SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
		SET_XFLG(GET_CFLG());
		SET_VFLG((bflgs ^ bflgn) & (bflgo ^ bflgn));
		dreg_68000_long_replace_low(dstreg, bnewv);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	m68k_dreg(regs, dstreg) = (newv);
	m68k_incpci(2);
	return 6 * CYCLE_UNIT / 2 + count_cycles;
}
/* 6 (1/0) */
/* 2 0,0   */

/* ADD.L An,Dn */
uae_u32 REGPARAM2 op_d088_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 6;  
	uae_s32 src = m68k_areg(regs, srcreg);
	uae_s32 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u32)(~dst)) < ((uae_u32)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		uae_s16 bnewv = (uae_s16)dst + (uae_s16)src;
		int bflgs = ((uae_s16)(src)) < 0;
		int bflgo = ((uae_s16)(dst)) < 0;
		int bflgn = bnewv < 0;
		ccr_68000_long_move_ae_LZN(bnewv);
		SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
		SET_XFLG(GET_CFLG());
		SET_VFLG((bflgs ^ bflgn) & (bflgo ^ bflgn));
		dreg_68000_long_replace_low(dstreg, bnewv);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	m68k_dreg(regs, dstreg) = (newv);
	m68k_incpci(2);
	return 6 * CYCLE_UNIT / 2 + count_cycles;
}
/* 6 (1/0) */
/* 2 0,0   */

/* ADD.L (An),Dn */
uae_u32 REGPARAM2 op_d090_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 10; 
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u32)(~dst)) < ((uae_u32)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_000_prefetch(4);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			int pcoffset = 0;
			dreg_68000_long_replace_low(dstreg, newv);
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return 8 * CYCLE_UNIT / 2 + count_cycles;
		}
		opcode = regs.ir;
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	if(loop_mode & 0xfffe) {
		count_cycles += (loop_mode & 0xfffe) * CYCLE_UNIT / 2;
		loop_mode = 1;
	}
	m68k_dreg(regs, dstreg) = (newv);
	if (loop_mode) {
		count_cycles += 4 * CYCLE_UNIT / 2;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return 10 * CYCLE_UNIT / 2 + count_cycles;
}
/* 10+ (2/0) */
/* 2 0,0   */

/* ADD.L (An)+,Dn */
uae_u32 REGPARAM2 op_d098_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 10; 
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) += 4;
	uae_s32 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u32)(~dst)) < ((uae_u32)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_000_prefetch(4);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			int pcoffset = 0;
			dreg_68000_long_replace_low(dstreg, newv);
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return 8 * CYCLE_UNIT / 2 + count_cycles;
		}
		opcode = regs.ir;
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	if(loop_mode & 0xfffe) {
		count_cycles += (loop_mode & 0xfffe) * CYCLE_UNIT / 2;
		loop_mode = 1;
	}
	m68k_dreg(regs, dstreg) = (newv);
	if (loop_mode) {
		count_cycles += 4 * CYCLE_UNIT / 2;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return 10 * CYCLE_UNIT / 2 + count_cycles;
}
/* 10+ (2/0) */
/* 2 0,0   */

/* ADD.L -(An),Dn */
uae_u32 REGPARAM2 op_d0a0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 12; 
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - 4;
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return 2 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) = srca;
	uae_s32 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u32)(~dst)) < ((uae_u32)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_000_prefetch(4);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			int pcoffset = 0;
			dreg_68000_long_replace_low(dstreg, newv);
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return 10 * CYCLE_UNIT / 2 + count_cycles;
		}
		opcode = regs.ir;
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	if(loop_mode & 0xfffe) {
		count_cycles += (loop_mode & 0xfffe) * CYCLE_UNIT / 2;
		loop_mode = 1;
	}
	m68k_dreg(regs, dstreg) = (newv);
	if (loop_mode) {
		count_cycles += 4 * CYCLE_UNIT / 2;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12+ (2/0) */
/* 2 0,0   */

/* ADD.L (d16,An),Dn */
uae_u32 REGPARAM2 op_d0a8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u32)(~dst)) < ((uae_u32)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		dreg_68000_long_replace_low(dstreg, newv);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	m68k_dreg(regs, dstreg) = (newv);
	m68k_incpci(4);
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (4/0) */
/* 4 0,0   */

/* ADD.L (d8,An,Xn),Dn */
uae_u32 REGPARAM2 op_d0b0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	BusCyclePenalty += 2;
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u32)(~dst)) < ((uae_u32)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		dreg_68000_long_replace_low(dstreg, newv);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	m68k_dreg(regs, dstreg) = (newv);
	m68k_incpci(4);
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (4/0) */
/* 4 4,0   */

/* ADD.L (xxx).W,Dn */
uae_u32 REGPARAM2 op_d0b8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, srca, 2, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u32)(~dst)) < ((uae_u32)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		dreg_68000_long_replace_low(dstreg, newv);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	m68k_dreg(regs, dstreg) = (newv);
	m68k_incpci(4);
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (4/0) */
/* 4 0,0   */

/* ADD.L (xxx).L,Dn */
uae_u32 REGPARAM2 op_d0b9_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 22; 
	uaecptr srca;
	srca = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	srca |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, srca, 2, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u32)(~dst)) < ((uae_u32)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		dreg_68000_long_replace_low(dstreg, newv);
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	m68k_dreg(regs, dstreg) = (newv);
	m68k_incpci(6);
	return 22 * CYCLE_UNIT / 2 + count_cycles;
}
/* 22 (5/0) */
/* 6 0,0   */

/* ADD.L (d16,PC),Dn */
uae_u32 REGPARAM2 op_d0ba_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	srca = m68k_getpci() + 2;
	srca += (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 2);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u32)(~dst)) < ((uae_u32)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		dreg_68000_long_replace_low(dstreg, newv);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	m68k_dreg(regs, dstreg) = (newv);
	m68k_incpci(4);
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (4/0) */
/* 4 0,0   */

/* ADD.L (d8,PC,Xn),Dn */
uae_u32 REGPARAM2 op_d0bb_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	uaecptr tmppc = m68k_getpci() + 2;
	BusCyclePenalty += 2;
	srca = get_disp_ea_000(tmppc, get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 2);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u32)(~dst)) < ((uae_u32)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		dreg_68000_long_replace_low(dstreg, newv);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	m68k_dreg(regs, dstreg) = (newv);
	m68k_incpci(4);
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (4/0) */
/* 4 4,0   */

/* ADD.L #<data>.L,Dn */
uae_u32 REGPARAM2 op_d0bc_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 14; 
	uae_s32 src;
	src = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u32)(~dst)) < ((uae_u32)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		uae_s16 bnewv = (uae_s16)dst + (uae_s16)src;
		int bflgs = ((uae_s16)(src)) < 0;
		int bflgo = ((uae_s16)(dst)) < 0;
		int bflgn = bnewv < 0;
		ccr_68000_long_move_ae_LZN(bnewv);
		SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
		SET_XFLG(GET_CFLG());
		SET_VFLG((bflgs ^ bflgn) & (bflgo ^ bflgn));
		dreg_68000_long_replace_low(dstreg, bnewv);
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	m68k_dreg(regs, dstreg) = (newv);
	m68k_incpci(6);
	return 14 * CYCLE_UNIT / 2 + count_cycles;
}
/* 14 (3/0) */
/* 6 0,0   */

/* ADDA.W Dn,An */
uae_u32 REGPARAM2 op_d0c0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 12;
	CurrentInstrCycles = 8;  
	uae_s16 src = m68k_dreg(regs, srcreg);
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = dst + src;
	regs.ir = regs.irc;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		areg_68000_long_replace_low(dstreg, newv);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	m68k_areg(regs, dstreg) = (newv);
	m68k_incpci(2);
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8 (1/0) */
/* 2 0,0   */

/* ADDA.W An,An */
uae_u32 REGPARAM2 op_d0c8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 12;
	CurrentInstrCycles = 8;  
	uae_s16 src = m68k_areg(regs, srcreg);
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = dst + src;
	regs.ir = regs.irc;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		areg_68000_long_replace_low(dstreg, newv);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	m68k_areg(regs, dstreg) = (newv);
	m68k_incpci(2);
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8 (1/0) */
/* 2 0,0   */

/* ADDA.W (An),An */
uae_u32 REGPARAM2 op_d0d0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 12;
	CurrentInstrCycles = 8;  
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access2(opcode, srca, 1, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = dst + src;
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_000_prefetch(4);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			int pcoffset = 0;
			areg_68000_long_replace_low(dstreg, newv);
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return 4 * CYCLE_UNIT / 2 + count_cycles;
		}
		opcode = regs.ir;
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	if(loop_mode & 0xfffe) {
		count_cycles += (loop_mode & 0xfffe) * CYCLE_UNIT / 2;
		loop_mode = 1;
	}
	m68k_areg(regs, dstreg) = (newv);
	if (loop_mode) {
		count_cycles += 2 * CYCLE_UNIT / 2;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8+ (1/0) */
/* 2 0,0   */

/* ADDA.W (An)+,An */
uae_u32 REGPARAM2 op_d0d8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 12;
	CurrentInstrCycles = 8;  
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_areg(regs, srcreg) += 2 + 0;
		m68k_incpci(2);
		exception3_read_access2(opcode, srca, 1, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) += 2 + 0;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) += 2;
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = dst + src;
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_000_prefetch(4);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			int pcoffset = 0;
			areg_68000_long_replace_low(dstreg, newv);
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return 4 * CYCLE_UNIT / 2 + count_cycles;
		}
		opcode = regs.ir;
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	if(loop_mode & 0xfffe) {
		count_cycles += (loop_mode & 0xfffe) * CYCLE_UNIT / 2;
		loop_mode = 1;
	}
	m68k_areg(regs, dstreg) = (newv);
	if (loop_mode) {
		count_cycles += 2 * CYCLE_UNIT / 2;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8+ (1/0) */
/* 2 0,0   */

/* ADDA.W -(An),An */
uae_u32 REGPARAM2 op_d0e0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 12;
	CurrentInstrCycles = 10; 
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - 2;
	if (srca & 1) {
		m68k_areg(regs, srcreg) = srca;
		m68k_incpci(2);
		exception3_read_access2(opcode, srca, 1, 1);
		return 2 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) = srca;
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = dst + src;
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_000_prefetch(4);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			int pcoffset = 0;
			areg_68000_long_replace_low(dstreg, newv);
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return 6 * CYCLE_UNIT / 2 + count_cycles;
		}
		opcode = regs.ir;
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	if(loop_mode & 0xfffe) {
		count_cycles += (loop_mode & 0xfffe) * CYCLE_UNIT / 2;
		loop_mode = 1;
	}
	m68k_areg(regs, dstreg) = (newv);
	if (loop_mode) {
		count_cycles += 2 * CYCLE_UNIT / 2;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return 10 * CYCLE_UNIT / 2 + count_cycles;
}
/* 10+ (1/0) */
/* 2 0,0   */

/* ADDA.W (d16,An),An */
uae_u32 REGPARAM2 op_d0e8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 12;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = dst + src;
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		areg_68000_long_replace_low(dstreg, newv);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	m68k_areg(regs, dstreg) = (newv);
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/0) */
/* 4 0,0   */

/* ADDA.W (d8,An,Xn),An */
uae_u32 REGPARAM2 op_d0f0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 12;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	BusCyclePenalty += 2;
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = dst + src;
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		areg_68000_long_replace_low(dstreg, newv);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	m68k_areg(regs, dstreg) = (newv);
	m68k_incpci(4);
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (3/0) */
/* 4 4,0   */

/* ADDA.W (xxx).W,An */
uae_u32 REGPARAM2 op_d0f8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 12;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, srca, 1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = dst + src;
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		areg_68000_long_replace_low(dstreg, newv);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	m68k_areg(regs, dstreg) = (newv);
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/0) */
/* 4 0,0   */

/* ADDA.W (xxx).L,An */
uae_u32 REGPARAM2 op_d0f9_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 12;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	srca = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	srca |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, srca, 1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = dst + src;
	regs.ir = regs.irc;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		areg_68000_long_replace_low(dstreg, newv);
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	m68k_areg(regs, dstreg) = (newv);
	m68k_incpci(6);
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (4/0) */
/* 6 0,0   */

/* ADDA.W (d16,PC),An */
uae_u32 REGPARAM2 op_d0fa_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 12;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = m68k_getpci() + 2;
	srca += (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = dst + src;
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		areg_68000_long_replace_low(dstreg, newv);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	m68k_areg(regs, dstreg) = (newv);
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/0) */
/* 4 0,0   */

/* ADDA.W (d8,PC,Xn),An */
uae_u32 REGPARAM2 op_d0fb_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 12;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	uaecptr tmppc = m68k_getpci() + 2;
	BusCyclePenalty += 2;
	srca = get_disp_ea_000(tmppc, get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = dst + src;
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		areg_68000_long_replace_low(dstreg, newv);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	m68k_areg(regs, dstreg) = (newv);
	m68k_incpci(4);
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (3/0) */
/* 4 4,0   */

/* ADDA.W #<data>.W,An */
uae_u32 REGPARAM2 op_d0fc_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 12;
	CurrentInstrCycles = 12; 
	uae_s16 src = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = dst + src;
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		areg_68000_long_replace_low(dstreg, newv);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	m68k_areg(regs, dstreg) = (newv);
	m68k_incpci(4);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (2/0) */
/* 4 0,0   */

/* ADDX.B Dn,Dn */
uae_u32 REGPARAM2 op_d100_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 13;
	CurrentInstrCycles = 4;  
	uae_s8 src = m68k_dreg(regs, srcreg);
	uae_s8 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = dst + src + (GET_XFLG() ? 1 : 0);
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(flgs ^ ((flgs ^ flgo) & (flgo ^ flgn)));
	COPY_CARRY();
	SET_ZFLG(GET_ZFLG() & (((uae_s8)(newv)) == 0));
	SET_NFLG(((uae_s8)(newv)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
	m68k_incpci(2);
	return 4 * CYCLE_UNIT / 2 + count_cycles;
}
/* 4 (1/0) */
/* 2 0,0   */

/* ADDX.B -(An),-(An) */
uae_u32 REGPARAM2 op_d108_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 13;
	CurrentInstrCycles = 14; 
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) = srca;
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, dstreg) = dsta;
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) = dsta;
	uae_u32 newv = dst + src + (GET_XFLG() ? 1 : 0);
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(flgs ^ ((flgs ^ flgo) & (flgo ^ flgn)));
	COPY_CARRY();
	SET_ZFLG(GET_ZFLG() & (((uae_s8)(newv)) == 0));
	SET_NFLG(((uae_s8)(newv)) < 0);
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_000_prefetch(4);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return 10 * CYCLE_UNIT / 2 + count_cycles;
		}
		opcode = regs.ir;
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	if(loop_mode & 0xfffe) {
		count_cycles += (loop_mode & 0xfffe) * CYCLE_UNIT / 2;
		loop_mode = 1;
	}
	put_byte_000(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x0, newv, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return 14 * CYCLE_UNIT / 2 + count_cycles;
}
/* 14+ (2/1) */
/* 2 0,0   */

/* ADD.B Dn,(An) */
uae_u32 REGPARAM2 op_d110_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 8;  
	int loop_mode = regs.loop_mode;
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u8)(~dst)) < ((uae_u8)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_000_prefetch(4);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return 4 * CYCLE_UNIT / 2 + count_cycles;
		}
		opcode = regs.ir;
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	if(loop_mode & 0xfffe) {
		count_cycles += (loop_mode & 0xfffe) * CYCLE_UNIT / 2;
		loop_mode = 1;
	}
	put_byte_000(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x0, newv, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8+ (1/1) */
/* 2 0,0   */

/* ADD.B Dn,(An)+ */
uae_u32 REGPARAM2 op_d118_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 8;  
	int loop_mode = regs.loop_mode;
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
	uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u8)(~dst)) < ((uae_u8)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_000_prefetch(4);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return 4 * CYCLE_UNIT / 2 + count_cycles;
		}
		opcode = regs.ir;
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	if(loop_mode & 0xfffe) {
		count_cycles += (loop_mode & 0xfffe) * CYCLE_UNIT / 2;
		loop_mode = 1;
	}
	put_byte_000(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x0, newv, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8+ (1/1) */
/* 2 0,0   */

/* ADD.B Dn,-(An) */
uae_u32 REGPARAM2 op_d120_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 10; 
	int loop_mode = regs.loop_mode;
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, dstreg) = dsta;
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) = dsta;
	uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u8)(~dst)) < ((uae_u8)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_000_prefetch(4);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return 6 * CYCLE_UNIT / 2 + count_cycles;
		}
		opcode = regs.ir;
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	if(loop_mode & 0xfffe) {
		count_cycles += (loop_mode & 0xfffe) * CYCLE_UNIT / 2;
		loop_mode = 1;
	}
	put_byte_000(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x0, newv, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return 10 * CYCLE_UNIT / 2 + count_cycles;
}
/* 10+ (1/1) */
/* 2 0,0   */

/* ADD.B Dn,(d16,An) */
uae_u32 REGPARAM2 op_d128_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 16; 
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u8)(~dst)) < ((uae_u8)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_byte_000(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x0, newv, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 4 0,0   */

/* ADD.B Dn,(d8,An,Xn) */
uae_u32 REGPARAM2 op_d130_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 18; 
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	BusCyclePenalty += 2;
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u8)(~dst)) < ((uae_u8)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_byte_000(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x0, newv, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (3/1) */
/* 4 4,0   */

/* ADD.B Dn,(xxx).W */
uae_u32 REGPARAM2 op_d138_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	OpcodeFamily = 11;
	CurrentInstrCycles = 16; 
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u8)(~dst)) < ((uae_u8)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_byte_000(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x0, newv, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 4 0,0   */

/* ADD.B Dn,(xxx).L */
uae_u32 REGPARAM2 op_d139_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	OpcodeFamily = 11;
	CurrentInstrCycles = 20; 
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	dsta |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u8)(~dst)) < ((uae_u8)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_byte_000(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 0, 0x0, newv, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (4/1) */
/* 6 0,0   */

/* ADDX.W Dn,Dn */
uae_u32 REGPARAM2 op_d140_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 13;
	CurrentInstrCycles = 4;  
	uae_s16 src = m68k_dreg(regs, srcreg);
	uae_s16 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = dst + src + (GET_XFLG() ? 1 : 0);
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(flgs ^ ((flgs ^ flgo) & (flgo ^ flgn)));
	COPY_CARRY();
	SET_ZFLG(GET_ZFLG() & (((uae_s16)(newv)) == 0));
	SET_NFLG(((uae_s16)(newv)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
	m68k_incpci(2);
	return 4 * CYCLE_UNIT / 2 + count_cycles;
}
/* 4 (1/0) */
/* 2 0,0   */

/* ADDX.W -(An),-(An) */
uae_u32 REGPARAM2 op_d148_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 13;
	CurrentInstrCycles = 14; 
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - 2;
	if (srca & 1) {
		m68k_areg(regs, srcreg) = srca;
		m68k_areg(regs, srcreg) = srca;
		m68k_incpci(2);
		exception3_read_access2(opcode, srca, 1, 1);
		return 2 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) = srca;
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - 2;
	if (dsta & 1) {
		m68k_areg(regs, dstreg) = dsta;
		m68k_areg(regs, dstreg) = dsta;
		m68k_incpci(2);
		exception3_read_access2(opcode, dsta, 1, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = get_word_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, dstreg) = dsta;
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) = dsta;
	uae_u32 newv = dst + src + (GET_XFLG() ? 1 : 0);
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(flgs ^ ((flgs ^ flgo) & (flgo ^ flgn)));
	COPY_CARRY();
	SET_ZFLG(GET_ZFLG() & (((uae_s16)(newv)) == 0));
	SET_NFLG(((uae_s16)(newv)) < 0);
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_000_prefetch(4);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return 10 * CYCLE_UNIT / 2 + count_cycles;
		}
		opcode = regs.ir;
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	if(loop_mode & 0xfffe) {
		count_cycles += (loop_mode & 0xfffe) * CYCLE_UNIT / 2;
		loop_mode = 1;
	}
	put_word_000(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x1, newv, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return 14 * CYCLE_UNIT / 2 + count_cycles;
}
/* 14+ (2/1) */
/* 2 0,0   */

/* ADD.W Dn,(An) */
uae_u32 REGPARAM2 op_d150_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 8;  
	int loop_mode = regs.loop_mode;
	uae_s16 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	if (dsta & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dsta, 1, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = get_word_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_000_prefetch(4);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return 4 * CYCLE_UNIT / 2 + count_cycles;
		}
		opcode = regs.ir;
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	if(loop_mode & 0xfffe) {
		count_cycles += (loop_mode & 0xfffe) * CYCLE_UNIT / 2;
		loop_mode = 1;
	}
	put_word_000(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x1, newv, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8+ (1/1) */
/* 2 0,0   */

/* ADD.W Dn,(An)+ */
uae_u32 REGPARAM2 op_d158_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 8;  
	int loop_mode = regs.loop_mode;
	uae_s16 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	if (dsta & 1) {
		m68k_areg(regs, dstreg) += 2 + 0;
		m68k_incpci(2);
		exception3_read_access(opcode, dsta, 1, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = get_word_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, dstreg) += 2 + 0;
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) += 2;
	uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_000_prefetch(4);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return 4 * CYCLE_UNIT / 2 + count_cycles;
		}
		opcode = regs.ir;
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	if(loop_mode & 0xfffe) {
		count_cycles += (loop_mode & 0xfffe) * CYCLE_UNIT / 2;
		loop_mode = 1;
	}
	put_word_000(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x1, newv, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8+ (1/1) */
/* 2 0,0   */

/* ADD.W Dn,-(An) */
uae_u32 REGPARAM2 op_d160_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 10; 
	int loop_mode = regs.loop_mode;
	uae_s16 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - 2;
	if (dsta & 1) {
		m68k_areg(regs, dstreg) = dsta;
		m68k_incpci(2);
		exception3_read_access(opcode, dsta, 1, 1);
		return 2 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = get_word_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, dstreg) = dsta;
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) = dsta;
	uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_000_prefetch(4);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return 6 * CYCLE_UNIT / 2 + count_cycles;
		}
		opcode = regs.ir;
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	if(loop_mode & 0xfffe) {
		count_cycles += (loop_mode & 0xfffe) * CYCLE_UNIT / 2;
		loop_mode = 1;
	}
	put_word_000(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x1, newv, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return 10 * CYCLE_UNIT / 2 + count_cycles;
}
/* 10+ (1/1) */
/* 2 0,0   */

/* ADD.W Dn,(d16,An) */
uae_u32 REGPARAM2 op_d168_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 16; 
	uae_s16 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dsta, 1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = get_word_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_word_000(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, newv, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 4 0,0   */

/* ADD.W Dn,(d8,An,Xn) */
uae_u32 REGPARAM2 op_d170_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 18; 
	uae_s16 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	BusCyclePenalty += 2;
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dsta, 1, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = get_word_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_word_000(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, newv, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (3/1) */
/* 4 4,0   */

/* ADD.W Dn,(xxx).W */
uae_u32 REGPARAM2 op_d178_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	OpcodeFamily = 11;
	CurrentInstrCycles = 16; 
	uae_s16 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, dsta, 1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = get_word_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_word_000(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, newv, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 4 0,0   */

/* ADD.W Dn,(xxx).L */
uae_u32 REGPARAM2 op_d179_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	OpcodeFamily = 11;
	CurrentInstrCycles = 20; 
	uae_s16 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	dsta |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, dsta, 1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = get_word_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_word_000(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 0, 0x1, newv, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (4/1) */
/* 6 0,0   */

/* ADDX.L Dn,Dn */
uae_u32 REGPARAM2 op_d180_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 13;
	CurrentInstrCycles = 6;  
	uae_s32 src = m68k_dreg(regs, srcreg);
	uae_s32 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = dst + src + (GET_XFLG() ? 1 : 0);
	int oldz = GET_ZFLG();
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(flgs ^ ((flgs ^ flgo) & (flgo ^ flgn)));
	COPY_CARRY();
	SET_ZFLG(GET_ZFLG() & (((uae_s32)(newv)) == 0));
	SET_NFLG(((uae_s32)(newv)) < 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		int bflgs = ((uae_s16)(src)) < 0;
		int bflgo = ((uae_s16)(dst)) < 0;
		int bflgn = ((uae_s16)(newv)) < 0;
		SET_VFLG((bflgs ^ bflgn) & (bflgo ^ bflgn));
		SET_CFLG(bflgs ^ ((bflgs ^ bflgo) & (bflgo ^ bflgn)));
		SET_XFLG(GET_CFLG());
		SET_ZFLG(oldz);
		if (newv & 0xffff) SET_ZFLG(0);
		SET_NFLG(newv & 0x8000); 
		dreg_68000_long_replace_low(dstreg, newv);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	m68k_dreg(regs, dstreg) = (newv);
	m68k_incpci(2);
	return 6 * CYCLE_UNIT / 2 + count_cycles;
}
/* 6 (1/0) */
/* 2 0,0   */

/* ADDX.L -(An),-(An) */
uae_u32 REGPARAM2 op_d188_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 13;
	CurrentInstrCycles = 26; 
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - 4;
	if (srca & 1) {
		m68k_incpci(2);
		srca += 2;
		exception3_read_access(opcode, srca, 2, 1);
		return 2 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) = srca;
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - 4;
	if (dsta & 1) {
		m68k_incpci(2);
		dsta += 2;
		exception3_read_access(opcode, dsta, 2, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = get_word_000(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	dst |= get_word_000(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) = dsta;
	uae_u32 newv = dst + src + (GET_XFLG() ? 1 : 0);
	int oldz = GET_ZFLG();
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(flgs ^ ((flgs ^ flgo) & (flgo ^ flgn)));
	COPY_CARRY();
	SET_ZFLG(GET_ZFLG() & (((uae_s32)(newv)) == 0));
	SET_NFLG(((uae_s32)(newv)) < 0);
	put_word_000(dsta + 2, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		int bflgs = ((uae_s16)(src)) < 0;
		int bflgo = ((uae_s16)(dst)) < 0;
		int bflgn = ((uae_s16)(newv)) < 0;
		SET_VFLG((bflgs ^ bflgn) & (bflgo ^ bflgn));
		SET_CFLG(bflgs ^ ((bflgs ^ bflgo) & (bflgo ^ bflgn)));
		COPY_CARRY();
		SET_ZFLG(GET_ZFLG() & (((uae_s16)(newv)) == 0));
		SET_NFLG(((uae_s16)(newv)) < 0);
		exception2_write(opcode, dsta + 2, 0x1, newv, 1);
		return 22 * CYCLE_UNIT / 2 + count_cycles;
	}
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_000_prefetch(4);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return 22 * CYCLE_UNIT / 2 + count_cycles;
		}
	} else {
		loop_mode = 0;
		loop_mode |= 2;
		loop_mode |= 2 << 16;
	}
	put_word_000(dsta, newv >> 16); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x1, newv >> 16, 1);
		return 26 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return 26 * CYCLE_UNIT / 2 + count_cycles;
}
/* 26+ (4/2) */
/* 2 0,0   */

/* ADD.L Dn,(An) */
uae_u32 REGPARAM2 op_d190_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 16; 
	int loop_mode = regs.loop_mode;
	uae_s32 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	if (dsta & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dsta, 2, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = get_word_000(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	dst |= get_word_000(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u32)(~dst)) < ((uae_u32)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_000_prefetch(4);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			int pcoffset = 0;
			uae_s16 bnewv = (uae_s16)dst + (uae_s16)src;
			int bflgs = ((uae_s16)(src)) < 0;
			int bflgo = ((uae_s16)(dst)) < 0;
			int bflgn = bnewv < 0;
			ccr_68000_long_move_ae_LZN(bnewv);
			SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
			SET_XFLG(GET_CFLG());
			SET_VFLG((bflgs ^ bflgn) & (bflgo ^ bflgn));
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return 8 * CYCLE_UNIT / 2 + count_cycles;
		}
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	if(loop_mode & 0xfffe) {
		count_cycles += (loop_mode & 0xfffe) * CYCLE_UNIT / 2;
		loop_mode = 1;
	}
	put_word_000(dsta + 2, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 2, 0x1, newv, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, newv >> 16); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x1, newv >> 16, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16+ (2/2) */
/* 2 0,0   */

/* ADD.L Dn,(An)+ */
uae_u32 REGPARAM2 op_d198_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 16; 
	int loop_mode = regs.loop_mode;
	uae_s32 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	if (dsta & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dsta, 2, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = get_word_000(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	dst |= get_word_000(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) += 4;
	uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u32)(~dst)) < ((uae_u32)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_000_prefetch(4);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			int pcoffset = 0;
			uae_s16 bnewv = (uae_s16)dst + (uae_s16)src;
			int bflgs = ((uae_s16)(src)) < 0;
			int bflgo = ((uae_s16)(dst)) < 0;
			int bflgn = bnewv < 0;
			ccr_68000_long_move_ae_LZN(bnewv);
			SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
			SET_XFLG(GET_CFLG());
			SET_VFLG((bflgs ^ bflgn) & (bflgo ^ bflgn));
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return 8 * CYCLE_UNIT / 2 + count_cycles;
		}
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	if(loop_mode & 0xfffe) {
		count_cycles += (loop_mode & 0xfffe) * CYCLE_UNIT / 2;
		loop_mode = 1;
	}
	put_word_000(dsta + 2, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 2, 0x1, newv, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, newv >> 16); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x1, newv >> 16, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16+ (2/2) */
/* 2 0,0   */

/* ADD.L Dn,-(An) */
uae_u32 REGPARAM2 op_d1a0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 18; 
	int loop_mode = regs.loop_mode;
	uae_s32 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - 4;
	if (dsta & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dsta, 2, 1);
		return 2 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = get_word_000(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	dst |= get_word_000(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, dstreg) = dsta;
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) = dsta;
	uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u32)(~dst)) < ((uae_u32)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_000_prefetch(4);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			int pcoffset = 0;
			uae_s16 bnewv = (uae_s16)dst + (uae_s16)src;
			int bflgs = ((uae_s16)(src)) < 0;
			int bflgo = ((uae_s16)(dst)) < 0;
			int bflgn = bnewv < 0;
			ccr_68000_long_move_ae_LZN(bnewv);
			SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
			SET_XFLG(GET_CFLG());
			SET_VFLG((bflgs ^ bflgn) & (bflgo ^ bflgn));
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return 10 * CYCLE_UNIT / 2 + count_cycles;
		}
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	if(loop_mode & 0xfffe) {
		count_cycles += (loop_mode & 0xfffe) * CYCLE_UNIT / 2;
		loop_mode = 1;
	}
	put_word_000(dsta + 2, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 2, 0x1, newv, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, newv >> 16); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x1, newv >> 16, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18+ (2/2) */
/* 2 0,0   */

/* ADD.L Dn,(d16,An) */
uae_u32 REGPARAM2 op_d1a8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 24; 
	uae_s32 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dsta, 2, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = get_word_000(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	dst |= get_word_000(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u32)(~dst)) < ((uae_u32)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		uae_s16 bnewv = (uae_s16)dst + (uae_s16)src;
		int bflgs = ((uae_s16)(src)) < 0;
		int bflgo = ((uae_s16)(dst)) < 0;
		int bflgn = bnewv < 0;
		ccr_68000_long_move_ae_LZN(bnewv);
		SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
		SET_XFLG(GET_CFLG());
		SET_VFLG((bflgs ^ bflgn) & (bflgo ^ bflgn));
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta + 2, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 2, 0x1, newv, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, newv >> 16); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, newv >> 16, 1);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 24 * CYCLE_UNIT / 2 + count_cycles;
}
/* 24 (4/2) */
/* 4 0,0   */

/* ADD.L Dn,(d8,An,Xn) */
uae_u32 REGPARAM2 op_d1b0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 26; 
	uae_s32 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	BusCyclePenalty += 2;
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dsta, 2, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = get_word_000(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	dst |= get_word_000(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u32)(~dst)) < ((uae_u32)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		uae_s16 bnewv = (uae_s16)dst + (uae_s16)src;
		int bflgs = ((uae_s16)(src)) < 0;
		int bflgo = ((uae_s16)(dst)) < 0;
		int bflgn = bnewv < 0;
		ccr_68000_long_move_ae_LZN(bnewv);
		SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
		SET_XFLG(GET_CFLG());
		SET_VFLG((bflgs ^ bflgn) & (bflgo ^ bflgn));
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta + 2, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 2, 0x1, newv, 1);
		return 22 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, newv >> 16); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, newv >> 16, 1);
		return 26 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 26 * CYCLE_UNIT / 2 + count_cycles;
}
/* 26 (4/2) */
/* 4 4,0   */

/* ADD.L Dn,(xxx).W */
uae_u32 REGPARAM2 op_d1b8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	OpcodeFamily = 11;
	CurrentInstrCycles = 24; 
	uae_s32 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, dsta, 2, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = get_word_000(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	dst |= get_word_000(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u32)(~dst)) < ((uae_u32)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		uae_s16 bnewv = (uae_s16)dst + (uae_s16)src;
		int bflgs = ((uae_s16)(src)) < 0;
		int bflgo = ((uae_s16)(dst)) < 0;
		int bflgn = bnewv < 0;
		ccr_68000_long_move_ae_LZN(bnewv);
		SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
		SET_XFLG(GET_CFLG());
		SET_VFLG((bflgs ^ bflgn) & (bflgo ^ bflgn));
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta + 2, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 2, 0x1, newv, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, newv >> 16); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, newv >> 16, 1);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 24 * CYCLE_UNIT / 2 + count_cycles;
}
/* 24 (4/2) */
/* 4 0,0   */

/* ADD.L Dn,(xxx).L */
uae_u32 REGPARAM2 op_d1b9_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	OpcodeFamily = 11;
	CurrentInstrCycles = 28; 
	uae_s32 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	dsta |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, dsta, 2, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = get_word_000(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	dst |= get_word_000(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u32)(~dst)) < ((uae_u32)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		uae_s16 bnewv = (uae_s16)dst + (uae_s16)src;
		int bflgs = ((uae_s16)(src)) < 0;
		int bflgo = ((uae_s16)(dst)) < 0;
		int bflgn = bnewv < 0;
		ccr_68000_long_move_ae_LZN(bnewv);
		SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
		SET_XFLG(GET_CFLG());
		SET_VFLG((bflgs ^ bflgn) & (bflgo ^ bflgn));
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta + 2, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 2, 0x1, newv, 1);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, newv >> 16); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 0, 0x1, newv >> 16, 1);
		return 28 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 28 * CYCLE_UNIT / 2 + count_cycles;
}
/* 28 (5/2) */
/* 6 0,0   */

/* ADDA.L Dn,An */
uae_u32 REGPARAM2 op_d1c0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 12;
	CurrentInstrCycles = 8;  
	uae_s32 src = m68k_dreg(regs, srcreg);
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = dst + src;
	regs.ir = regs.irc;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		areg_68000_long_replace_low(dstreg, newv);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	m68k_areg(regs, dstreg) = (newv);
	m68k_incpci(2);
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8 (1/0) */
/* 2 0,0   */

/* ADDA.L An,An */
uae_u32 REGPARAM2 op_d1c8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 12;
	CurrentInstrCycles = 8;  
	uae_s32 src = m68k_areg(regs, srcreg);
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = dst + src;
	regs.ir = regs.irc;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		areg_68000_long_replace_low(dstreg, newv);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	m68k_areg(regs, dstreg) = (newv);
	m68k_incpci(2);
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8 (1/0) */
/* 2 0,0   */

/* ADDA.L (An),An */
uae_u32 REGPARAM2 op_d1d0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 12;
	CurrentInstrCycles = 10; 
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = dst + src;
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_000_prefetch(4);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			int pcoffset = 0;
			areg_68000_long_replace_low(dstreg, newv);
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return 8 * CYCLE_UNIT / 2 + count_cycles;
		}
		opcode = regs.ir;
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	if(loop_mode & 0xfffe) {
		count_cycles += (loop_mode & 0xfffe) * CYCLE_UNIT / 2;
		loop_mode = 1;
	}
	m68k_areg(regs, dstreg) = (newv);
	if (loop_mode) {
		count_cycles += 4 * CYCLE_UNIT / 2;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return 10 * CYCLE_UNIT / 2 + count_cycles;
}
/* 10+ (2/0) */
/* 2 0,0   */

/* ADDA.L (An)+,An */
uae_u32 REGPARAM2 op_d1d8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 12;
	CurrentInstrCycles = 10; 
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) += 4;
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = dst + src;
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_000_prefetch(4);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			int pcoffset = 0;
			areg_68000_long_replace_low(dstreg, newv);
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return 8 * CYCLE_UNIT / 2 + count_cycles;
		}
		opcode = regs.ir;
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	if(loop_mode & 0xfffe) {
		count_cycles += (loop_mode & 0xfffe) * CYCLE_UNIT / 2;
		loop_mode = 1;
	}
	m68k_areg(regs, dstreg) = (newv);
	if (loop_mode) {
		count_cycles += 4 * CYCLE_UNIT / 2;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return 10 * CYCLE_UNIT / 2 + count_cycles;
}
/* 10+ (2/0) */
/* 2 0,0   */

/* ADDA.L -(An),An */
uae_u32 REGPARAM2 op_d1e0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 12;
	CurrentInstrCycles = 12; 
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - 4;
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return 2 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) = srca;
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = dst + src;
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_000_prefetch(4);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			int pcoffset = 0;
			areg_68000_long_replace_low(dstreg, newv);
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return 10 * CYCLE_UNIT / 2 + count_cycles;
		}
		opcode = regs.ir;
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	if(loop_mode & 0xfffe) {
		count_cycles += (loop_mode & 0xfffe) * CYCLE_UNIT / 2;
		loop_mode = 1;
	}
	m68k_areg(regs, dstreg) = (newv);
	if (loop_mode) {
		count_cycles += 4 * CYCLE_UNIT / 2;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12+ (2/0) */
/* 2 0,0   */

/* ADDA.L (d16,An),An */
uae_u32 REGPARAM2 op_d1e8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 12;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = dst + src;
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		areg_68000_long_replace_low(dstreg, newv);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	m68k_areg(regs, dstreg) = (newv);
	m68k_incpci(4);
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (4/0) */
/* 4 0,0   */

/* ADDA.L (d8,An,Xn),An */
uae_u32 REGPARAM2 op_d1f0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 12;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	BusCyclePenalty += 2;
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = dst + src;
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		areg_68000_long_replace_low(dstreg, newv);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	m68k_areg(regs, dstreg) = (newv);
	m68k_incpci(4);
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (4/0) */
/* 4 4,0   */

/* ADDA.L (xxx).W,An */
uae_u32 REGPARAM2 op_d1f8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 12;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, srca, 2, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = dst + src;
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		areg_68000_long_replace_low(dstreg, newv);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	m68k_areg(regs, dstreg) = (newv);
	m68k_incpci(4);
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (4/0) */
/* 4 0,0   */

/* ADDA.L (xxx).L,An */
uae_u32 REGPARAM2 op_d1f9_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 12;
	CurrentInstrCycles = 22; 
	uaecptr srca;
	srca = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	srca |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, srca, 2, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = dst + src;
	regs.ir = regs.irc;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		areg_68000_long_replace_low(dstreg, newv);
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	m68k_areg(regs, dstreg) = (newv);
	m68k_incpci(6);
	return 22 * CYCLE_UNIT / 2 + count_cycles;
}
/* 22 (5/0) */
/* 6 0,0   */

/* ADDA.L (d16,PC),An */
uae_u32 REGPARAM2 op_d1fa_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 12;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	srca = m68k_getpci() + 2;
	srca += (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 2);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = dst + src;
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		areg_68000_long_replace_low(dstreg, newv);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	m68k_areg(regs, dstreg) = (newv);
	m68k_incpci(4);
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (4/0) */
/* 4 0,0   */

/* ADDA.L (d8,PC,Xn),An */
uae_u32 REGPARAM2 op_d1fb_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 12;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	uaecptr tmppc = m68k_getpci() + 2;
	BusCyclePenalty += 2;
	srca = get_disp_ea_000(tmppc, get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 2);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = dst + src;
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		areg_68000_long_replace_low(dstreg, newv);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	m68k_areg(regs, dstreg) = (newv);
	m68k_incpci(4);
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (4/0) */
/* 4 4,0   */

/* ADDA.L #<data>.L,An */
uae_u32 REGPARAM2 op_d1fc_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 12;
	CurrentInstrCycles = 16; 
	uae_s32 src;
	src = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = dst + src;
	regs.ir = regs.irc;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		areg_68000_long_replace_low(dstreg, newv);
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	m68k_areg(regs, dstreg) = (newv);
	m68k_incpci(6);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/0) */
/* 6 0,0   */

/* ASRQ.B #<data>,Dn */
uae_u32 REGPARAM2 op_e000_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 64;
	CurrentInstrCycles = 6;  
	uae_u32 cnt = srcreg;
	uae_s8 data = m68k_dreg(regs, dstreg);
	uae_u32 val = (uae_u8)data;
	CLEAR_CZNV();
	regs.ir = regs.irc;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		SET_ZFLG(!(val & 0xff));
		SET_NFLG(val & 0x80);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	uae_u32 sign = (0x80 & val) >> 7;
	int ccnt = cnt & 63;
	cnt &= 63;
	if (cnt >= 8) {
		val = 0xff & (uae_u32)(0 - sign);
		SET_CFLG(sign);
		COPY_CARRY();
	} else {
		val >>= cnt - 1;
		SET_CFLG(val & 1);
		COPY_CARRY();
		val >>= 1;
		val |= (0xff << (8 - cnt)) & (uae_u32)(0 - sign);
		val &= 0xff;
	}
	SET_ZFLG(((uae_s8)(val)) == 0);
	SET_NFLG(((uae_s8)(val)) < 0);
	count_cycles += (2 * ccnt) * CYCLE_UNIT / 2;
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((val) & 0xff);
	m68k_incpci(2);
	return 6 * CYCLE_UNIT / 2 + count_cycles;
}
/* 6+ (1/0) */
/* 2 0,0   */

/* LSRQ.B #<data>,Dn */
uae_u32 REGPARAM2 op_e008_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 66;
	CurrentInstrCycles = 6;  
	uae_u32 cnt = srcreg;
	uae_s8 data = m68k_dreg(regs, dstreg);
	uae_u32 val = (uae_u8)data;
	CLEAR_CZNV();
	regs.ir = regs.irc;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		SET_ZFLG(!(val & 0xff));
		SET_NFLG(val & 0x80);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int ccnt = cnt & 63;
	cnt &= 63;
	if (cnt >= 8) {
		SET_CFLG((cnt == 8) & (val >> 7));
		COPY_CARRY();
		val = 0;
	} else {
		val >>= cnt - 1;
		SET_CFLG(val & 1);
		COPY_CARRY();
		val >>= 1;
	}
	SET_ZFLG(((uae_s8)(val)) == 0);
	SET_NFLG(((uae_s8)(val)) < 0);
	count_cycles += (2 * ccnt) * CYCLE_UNIT / 2;
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((val) & 0xff);
	m68k_incpci(2);
	return 6 * CYCLE_UNIT / 2 + count_cycles;
}
/* 6+ (1/0) */
/* 2 0,0   */

/* ROXRQ.B #<data>,Dn */
uae_u32 REGPARAM2 op_e010_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 71;
	CurrentInstrCycles = 6;  
	uae_u32 cnt = srcreg;
	uae_s8 data = m68k_dreg(regs, dstreg);
	uae_u32 val = (uae_u8)data;
	CLEAR_CZNV();
	regs.ir = regs.irc;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		SET_ZFLG(!(val & 0xff));
		SET_NFLG(val & 0x80);
		SET_CFLG(GET_XFLG());
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int ccnt = cnt & 63;
	cnt &= 63;
	{
		cnt--;
		{
			uae_u32 carry;
			uae_u32 hival = (val << 1) | GET_XFLG();
			hival <<= (7 - cnt);
			val >>= cnt;
			carry = val & 1;
			val >>= 1;
			val |= hival;
			SET_XFLG(carry);
			val &= 0xff;
		}
	}
	SET_CFLG(GET_XFLG());
	SET_ZFLG(((uae_s8)(val)) == 0);
	SET_NFLG(((uae_s8)(val)) < 0);
	count_cycles += (2 * ccnt) * CYCLE_UNIT / 2;
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((val) & 0xff);
	m68k_incpci(2);
	return 6 * CYCLE_UNIT / 2 + count_cycles;
}
/* 6+ (1/0) */
/* 2 0,0   */

/* RORQ.B #<data>,Dn */
uae_u32 REGPARAM2 op_e018_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 69;
	CurrentInstrCycles = 6;  
	uae_u32 cnt = srcreg;
	uae_s8 data = m68k_dreg(regs, dstreg);
	uae_u32 val = (uae_u8)data;
	CLEAR_CZNV();
	regs.ir = regs.irc;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		SET_ZFLG(!(val & 0xff));
		SET_NFLG(val & 0x80);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int ccnt = cnt & 63;
	cnt &= 63;
	{
		uae_u32 hival;
		cnt &= 7;
		hival = val << (8 - cnt);
		val >>= cnt;
		val |= hival;
		val &= 0xff;
		SET_CFLG((val & 0x80) >> 7);
	}
	SET_ZFLG(((uae_s8)(val)) == 0);
	SET_NFLG(((uae_s8)(val)) < 0);
	count_cycles += (2 * ccnt) * CYCLE_UNIT / 2;
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((val) & 0xff);
	m68k_incpci(2);
	return 6 * CYCLE_UNIT / 2 + count_cycles;
}
/* 6+ (1/0) */
/* 2 0,0   */

/* ASR.B Dn,Dn */
uae_u32 REGPARAM2 op_e020_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 64;
	CurrentInstrCycles = 6;  
	uae_s8 cnt = m68k_dreg(regs, srcreg);
	uae_s8 data = m68k_dreg(regs, dstreg);
	uae_u32 val = (uae_u8)data;
	CLEAR_CZNV();
	regs.ir = regs.irc;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		SET_ZFLG(!(val & 0xff));
		SET_NFLG(val & 0x80);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	uae_u32 sign = (0x80 & val) >> 7;
	int ccnt = cnt & 63;
	cnt &= 63;
	if (cnt >= 8) {
		val = 0xff & (uae_u32)(0 - sign);
		SET_CFLG(sign);
		COPY_CARRY();
	} else if (cnt > 0) {
		val >>= cnt - 1;
		SET_CFLG(val & 1);
		COPY_CARRY();
		val >>= 1;
		val |= (0xff << (8 - cnt)) & (uae_u32)(0 - sign);
		val &= 0xff;
	}
	SET_ZFLG(((uae_s8)(val)) == 0);
	SET_NFLG(((uae_s8)(val)) < 0);
	count_cycles += (2 * ccnt) * CYCLE_UNIT / 2;
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((val) & 0xff);
	m68k_incpci(2);
	return 6 * CYCLE_UNIT / 2 + count_cycles;
}
/* 6+ (1/0) */
/* 2 0,0   */

/* LSR.B Dn,Dn */
uae_u32 REGPARAM2 op_e028_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 66;
	CurrentInstrCycles = 6;  
	uae_s8 cnt = m68k_dreg(regs, srcreg);
	uae_s8 data = m68k_dreg(regs, dstreg);
	uae_u32 val = (uae_u8)data;
	CLEAR_CZNV();
	regs.ir = regs.irc;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		SET_ZFLG(!(val & 0xff));
		SET_NFLG(val & 0x80);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int ccnt = cnt & 63;
	cnt &= 63;
	if (cnt >= 8) {
		SET_CFLG((cnt == 8) & (val >> 7));
		COPY_CARRY();
		val = 0;
	} else if (cnt > 0) {
		val >>= cnt - 1;
		SET_CFLG(val & 1);
		COPY_CARRY();
		val >>= 1;
	}
	SET_ZFLG(((uae_s8)(val)) == 0);
	SET_NFLG(((uae_s8)(val)) < 0);
	count_cycles += (2 * ccnt) * CYCLE_UNIT / 2;
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((val) & 0xff);
	m68k_incpci(2);
	return 6 * CYCLE_UNIT / 2 + count_cycles;
}
/* 6+ (1/0) */
/* 2 0,0   */

/* ROXR.B Dn,Dn */
uae_u32 REGPARAM2 op_e030_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 71;
	CurrentInstrCycles = 6;  
	uae_s8 cnt = m68k_dreg(regs, srcreg);
	uae_s8 data = m68k_dreg(regs, dstreg);
	uae_u32 val = (uae_u8)data;
	CLEAR_CZNV();
	regs.ir = regs.irc;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		SET_ZFLG(!(val & 0xff));
		SET_NFLG(val & 0x80);
		SET_CFLG(GET_XFLG());
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int ccnt = cnt & 63;
	cnt &= 63;
	if (cnt >= 36) cnt -= 36;
	if (cnt >= 18) cnt -= 18;
	if (cnt >= 9) cnt -= 9;
	if (cnt > 0) {
		cnt--;
		{
			uae_u32 carry;
			uae_u32 hival = (val << 1) | GET_XFLG();
			hival <<= (7 - cnt);
			val >>= cnt;
			carry = val & 1;
			val >>= 1;
			val |= hival;
			SET_XFLG(carry);
			val &= 0xff;
		}
	}
	SET_CFLG(GET_XFLG());
	SET_ZFLG(((uae_s8)(val)) == 0);
	SET_NFLG(((uae_s8)(val)) < 0);
	count_cycles += (2 * ccnt) * CYCLE_UNIT / 2;
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((val) & 0xff);
	m68k_incpci(2);
	return 6 * CYCLE_UNIT / 2 + count_cycles;
}
/* 6+ (1/0) */
/* 2 0,0   */

/* ROR.B Dn,Dn */
uae_u32 REGPARAM2 op_e038_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 69;
	CurrentInstrCycles = 6;  
	uae_s8 cnt = m68k_dreg(regs, srcreg);
	uae_s8 data = m68k_dreg(regs, dstreg);
	uae_u32 val = (uae_u8)data;
	CLEAR_CZNV();
	regs.ir = regs.irc;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		SET_ZFLG(!(val & 0xff));
		SET_NFLG(val & 0x80);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int ccnt = cnt & 63;
	cnt &= 63;
	if (cnt > 0) {
		uae_u32 hival;
		cnt &= 7;
		hival = val << (8 - cnt);
		val >>= cnt;
		val |= hival;
		val &= 0xff;
		SET_CFLG((val & 0x80) >> 7);
	}
	SET_ZFLG(((uae_s8)(val)) == 0);
	SET_NFLG(((uae_s8)(val)) < 0);
	count_cycles += (2 * ccnt) * CYCLE_UNIT / 2;
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((val) & 0xff);
	m68k_incpci(2);
	return 6 * CYCLE_UNIT / 2 + count_cycles;
}
/* 6+ (1/0) */
/* 2 0,0   */

/* ASRQ.W #<data>,Dn */
uae_u32 REGPARAM2 op_e040_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 64;
	CurrentInstrCycles = 6;  
	uae_u32 cnt = srcreg;
	uae_s16 data = m68k_dreg(regs, dstreg);
	uae_u32 val = (uae_u16)data;
	CLEAR_CZNV();
	regs.ir = regs.irc;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		SET_ZFLG(!(val & 0xffff));
		SET_NFLG(val & 0x8000);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	uae_u32 sign = (0x8000 & val) >> 15;
	int ccnt = cnt & 63;
	cnt &= 63;
	if (cnt >= 16) {
		val = 0xffff & (uae_u32)(0 - sign);
		SET_CFLG(sign);
		COPY_CARRY();
	} else {
		val >>= cnt - 1;
		SET_CFLG(val & 1);
		COPY_CARRY();
		val >>= 1;
		val |= (0xffff << (16 - cnt)) & (uae_u32)(0 - sign);
		val &= 0xffff;
	}
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	count_cycles += (2 * ccnt) * CYCLE_UNIT / 2;
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((val) & 0xffff);
	m68k_incpci(2);
	return 6 * CYCLE_UNIT / 2 + count_cycles;
}
/* 6+ (1/0) */
/* 2 0,0   */

/* LSRQ.W #<data>,Dn */
uae_u32 REGPARAM2 op_e048_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 66;
	CurrentInstrCycles = 6;  
	uae_u32 cnt = srcreg;
	uae_s16 data = m68k_dreg(regs, dstreg);
	uae_u32 val = (uae_u16)data;
	CLEAR_CZNV();
	regs.ir = regs.irc;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		SET_ZFLG(!(val & 0xffff));
		SET_NFLG(val & 0x8000);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int ccnt = cnt & 63;
	cnt &= 63;
	if (cnt >= 16) {
		SET_CFLG((cnt == 16) & (val >> 15));
		COPY_CARRY();
		val = 0;
	} else {
		val >>= cnt - 1;
		SET_CFLG(val & 1);
		COPY_CARRY();
		val >>= 1;
	}
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	count_cycles += (2 * ccnt) * CYCLE_UNIT / 2;
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((val) & 0xffff);
	m68k_incpci(2);
	return 6 * CYCLE_UNIT / 2 + count_cycles;
}
/* 6+ (1/0) */
/* 2 0,0   */

/* ROXRQ.W #<data>,Dn */
uae_u32 REGPARAM2 op_e050_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 71;
	CurrentInstrCycles = 6;  
	uae_u32 cnt = srcreg;
	uae_s16 data = m68k_dreg(regs, dstreg);
	uae_u32 val = (uae_u16)data;
	CLEAR_CZNV();
	regs.ir = regs.irc;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		SET_ZFLG(!(val & 0xffff));
		SET_NFLG(val & 0x8000);
		SET_CFLG(GET_XFLG());
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int ccnt = cnt & 63;
	cnt &= 63;
	{
		cnt--;
		{
			uae_u32 carry;
			uae_u32 hival = (val << 1) | GET_XFLG();
			hival <<= (15 - cnt);
			val >>= cnt;
			carry = val & 1;
			val >>= 1;
			val |= hival;
			SET_XFLG(carry);
			val &= 0xffff;
		}
	}
	SET_CFLG(GET_XFLG());
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	count_cycles += (2 * ccnt) * CYCLE_UNIT / 2;
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((val) & 0xffff);
	m68k_incpci(2);
	return 6 * CYCLE_UNIT / 2 + count_cycles;
}
/* 6+ (1/0) */
/* 2 0,0   */

/* RORQ.W #<data>,Dn */
uae_u32 REGPARAM2 op_e058_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 69;
	CurrentInstrCycles = 6;  
	uae_u32 cnt = srcreg;
	uae_s16 data = m68k_dreg(regs, dstreg);
	uae_u32 val = (uae_u16)data;
	CLEAR_CZNV();
	regs.ir = regs.irc;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		SET_ZFLG(!(val & 0xffff));
		SET_NFLG(val & 0x8000);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int ccnt = cnt & 63;
	cnt &= 63;
	{
		uae_u32 hival;
		cnt &= 15;
		hival = val << (16 - cnt);
		val >>= cnt;
		val |= hival;
		val &= 0xffff;
		SET_CFLG((val & 0x8000) >> 15);
	}
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	count_cycles += (2 * ccnt) * CYCLE_UNIT / 2;
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((val) & 0xffff);
	m68k_incpci(2);
	return 6 * CYCLE_UNIT / 2 + count_cycles;
}
/* 6+ (1/0) */
/* 2 0,0   */

/* ASR.W Dn,Dn */
uae_u32 REGPARAM2 op_e060_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 64;
	CurrentInstrCycles = 6;  
	uae_s16 cnt = m68k_dreg(regs, srcreg);
	uae_s16 data = m68k_dreg(regs, dstreg);
	uae_u32 val = (uae_u16)data;
	CLEAR_CZNV();
	regs.ir = regs.irc;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		SET_ZFLG(!(val & 0xffff));
		SET_NFLG(val & 0x8000);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	uae_u32 sign = (0x8000 & val) >> 15;
	int ccnt = cnt & 63;
	cnt &= 63;
	if (cnt >= 16) {
		val = 0xffff & (uae_u32)(0 - sign);
		SET_CFLG(sign);
		COPY_CARRY();
	} else if (cnt > 0) {
		val >>= cnt - 1;
		SET_CFLG(val & 1);
		COPY_CARRY();
		val >>= 1;
		val |= (0xffff << (16 - cnt)) & (uae_u32)(0 - sign);
		val &= 0xffff;
	}
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	count_cycles += (2 * ccnt) * CYCLE_UNIT / 2;
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((val) & 0xffff);
	m68k_incpci(2);
	return 6 * CYCLE_UNIT / 2 + count_cycles;
}
/* 6+ (1/0) */
/* 2 0,0   */

/* LSR.W Dn,Dn */
uae_u32 REGPARAM2 op_e068_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 66;
	CurrentInstrCycles = 6;  
	uae_s16 cnt = m68k_dreg(regs, srcreg);
	uae_s16 data = m68k_dreg(regs, dstreg);
	uae_u32 val = (uae_u16)data;
	CLEAR_CZNV();
	regs.ir = regs.irc;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		SET_ZFLG(!(val & 0xffff));
		SET_NFLG(val & 0x8000);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int ccnt = cnt & 63;
	cnt &= 63;
	if (cnt >= 16) {
		SET_CFLG((cnt == 16) & (val >> 15));
		COPY_CARRY();
		val = 0;
	} else if (cnt > 0) {
		val >>= cnt - 1;
		SET_CFLG(val & 1);
		COPY_CARRY();
		val >>= 1;
	}
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	count_cycles += (2 * ccnt) * CYCLE_UNIT / 2;
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((val) & 0xffff);
	m68k_incpci(2);
	return 6 * CYCLE_UNIT / 2 + count_cycles;
}
/* 6+ (1/0) */
/* 2 0,0   */

/* ROXR.W Dn,Dn */
uae_u32 REGPARAM2 op_e070_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 71;
	CurrentInstrCycles = 6;  
	uae_s16 cnt = m68k_dreg(regs, srcreg);
	uae_s16 data = m68k_dreg(regs, dstreg);
	uae_u32 val = (uae_u16)data;
	CLEAR_CZNV();
	regs.ir = regs.irc;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		SET_ZFLG(!(val & 0xffff));
		SET_NFLG(val & 0x8000);
		SET_CFLG(GET_XFLG());
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int ccnt = cnt & 63;
	cnt &= 63;
	if (cnt >= 34) cnt -= 34;
	if (cnt >= 17) cnt -= 17;
	if (cnt > 0) {
		cnt--;
		{
			uae_u32 carry;
			uae_u32 hival = (val << 1) | GET_XFLG();
			hival <<= (15 - cnt);
			val >>= cnt;
			carry = val & 1;
			val >>= 1;
			val |= hival;
			SET_XFLG(carry);
			val &= 0xffff;
		}
	}
	SET_CFLG(GET_XFLG());
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	count_cycles += (2 * ccnt) * CYCLE_UNIT / 2;
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((val) & 0xffff);
	m68k_incpci(2);
	return 6 * CYCLE_UNIT / 2 + count_cycles;
}
/* 6+ (1/0) */
/* 2 0,0   */

/* ROR.W Dn,Dn */
uae_u32 REGPARAM2 op_e078_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 69;
	CurrentInstrCycles = 6;  
	uae_s16 cnt = m68k_dreg(regs, srcreg);
	uae_s16 data = m68k_dreg(regs, dstreg);
	uae_u32 val = (uae_u16)data;
	CLEAR_CZNV();
	regs.ir = regs.irc;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		SET_ZFLG(!(val & 0xffff));
		SET_NFLG(val & 0x8000);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int ccnt = cnt & 63;
	cnt &= 63;
	if (cnt > 0) {
		uae_u32 hival;
		cnt &= 15;
		hival = val << (16 - cnt);
		val >>= cnt;
		val |= hival;
		val &= 0xffff;
		SET_CFLG((val & 0x8000) >> 15);
	}
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	count_cycles += (2 * ccnt) * CYCLE_UNIT / 2;
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((val) & 0xffff);
	m68k_incpci(2);
	return 6 * CYCLE_UNIT / 2 + count_cycles;
}
/* 6+ (1/0) */
/* 2 0,0   */

/* ASRQ.L #<data>,Dn */
uae_u32 REGPARAM2 op_e080_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 64;
	CurrentInstrCycles = 8;  
	uae_u32 cnt = srcreg;
	uae_s32 data = m68k_dreg(regs, dstreg);
	uae_u32 val = data;
	CLEAR_CZNV();
	regs.ir = regs.irc;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		SET_NFLG(val & 0x8000);
		SET_ZFLG(!(val & 0xffff));
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	uae_u32 sign = (0x80000000 & val) >> 31;
	int ccnt = cnt & 63;
	cnt &= 63;
	if (cnt >= 32) {
		val = 0xffffffff & (uae_u32)(0 - sign);
		SET_CFLG(sign);
		COPY_CARRY();
	} else {
		val >>= cnt - 1;
		SET_CFLG(val & 1);
		COPY_CARRY();
		val >>= 1;
		val |= (0xffffffff << (32 - cnt)) & (uae_u32)(0 - sign);
		val &= 0xffffffff;
	}
	SET_ZFLG(((uae_s32)(val)) == 0);
	SET_NFLG(((uae_s32)(val)) < 0);
	count_cycles += (2 * ccnt) * CYCLE_UNIT / 2;
	m68k_dreg(regs, dstreg) = (val);
	m68k_incpci(2);
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8+ (1/0) */
/* 2 0,0   */

/* LSRQ.L #<data>,Dn */
uae_u32 REGPARAM2 op_e088_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 66;
	CurrentInstrCycles = 8;  
	uae_u32 cnt = srcreg;
	uae_s32 data = m68k_dreg(regs, dstreg);
	uae_u32 val = data;
	CLEAR_CZNV();
	regs.ir = regs.irc;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		SET_NFLG(val & 0x8000);
		SET_ZFLG(!(val & 0xffff));
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int ccnt = cnt & 63;
	cnt &= 63;
	if (cnt >= 32) {
		SET_CFLG((cnt == 32) & (val >> 31));
		COPY_CARRY();
		val = 0;
	} else {
		val >>= cnt - 1;
		SET_CFLG(val & 1);
		COPY_CARRY();
		val >>= 1;
	}
	SET_ZFLG(((uae_s32)(val)) == 0);
	SET_NFLG(((uae_s32)(val)) < 0);
	count_cycles += (2 * ccnt) * CYCLE_UNIT / 2;
	m68k_dreg(regs, dstreg) = (val);
	m68k_incpci(2);
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8+ (1/0) */
/* 2 0,0   */

/* ROXRQ.L #<data>,Dn */
uae_u32 REGPARAM2 op_e090_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 71;
	CurrentInstrCycles = 8;  
	uae_u32 cnt = srcreg;
	uae_s32 data = m68k_dreg(regs, dstreg);
	uae_u32 val = data;
	CLEAR_CZNV();
	regs.ir = regs.irc;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		SET_NFLG(val & 0x8000);
		SET_ZFLG(!(val & 0xffff));
		SET_CFLG(GET_XFLG());
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int ccnt = cnt & 63;
	cnt &= 63;
	{
		cnt--;
		{
			uae_u32 carry;
			uae_u32 hival = (val << 1) | GET_XFLG();
			hival <<= (31 - cnt);
			val >>= cnt;
			carry = val & 1;
			val >>= 1;
			val |= hival;
			SET_XFLG(carry);
			val &= 0xffffffff;
		}
	}
	SET_CFLG(GET_XFLG());
	SET_ZFLG(((uae_s32)(val)) == 0);
	SET_NFLG(((uae_s32)(val)) < 0);
	count_cycles += (2 * ccnt) * CYCLE_UNIT / 2;
	m68k_dreg(regs, dstreg) = (val);
	m68k_incpci(2);
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8+ (1/0) */
/* 2 0,0   */

/* RORQ.L #<data>,Dn */
uae_u32 REGPARAM2 op_e098_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 69;
	CurrentInstrCycles = 8;  
	uae_u32 cnt = srcreg;
	uae_s32 data = m68k_dreg(regs, dstreg);
	uae_u32 val = data;
	CLEAR_CZNV();
	regs.ir = regs.irc;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		SET_NFLG(val & 0x8000);
		SET_ZFLG(!(val & 0xffff));
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int ccnt = cnt & 63;
	cnt &= 63;
	{
		uae_u32 hival;
		cnt &= 31;
		hival = val << (32 - cnt);
		val >>= cnt;
		val |= hival;
		val &= 0xffffffff;
		SET_CFLG((val & 0x80000000) >> 31);
	}
	SET_ZFLG(((uae_s32)(val)) == 0);
	SET_NFLG(((uae_s32)(val)) < 0);
	count_cycles += (2 * ccnt) * CYCLE_UNIT / 2;
	m68k_dreg(regs, dstreg) = (val);
	m68k_incpci(2);
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8+ (1/0) */
/* 2 0,0   */

/* ASR.L Dn,Dn */
uae_u32 REGPARAM2 op_e0a0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 64;
	CurrentInstrCycles = 8;  
	uae_s32 cnt = m68k_dreg(regs, srcreg);
	uae_s32 data = m68k_dreg(regs, dstreg);
	uae_u32 val = data;
	CLEAR_CZNV();
	regs.ir = regs.irc;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		SET_NFLG(val & 0x8000);
		SET_ZFLG(!(val & 0xffff));
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	uae_u32 sign = (0x80000000 & val) >> 31;
	int ccnt = cnt & 63;
	cnt &= 63;
	if (cnt >= 32) {
		val = 0xffffffff & (uae_u32)(0 - sign);
		SET_CFLG(sign);
		COPY_CARRY();
	} else if (cnt > 0) {
		val >>= cnt - 1;
		SET_CFLG(val & 1);
		COPY_CARRY();
		val >>= 1;
		val |= (0xffffffff << (32 - cnt)) & (uae_u32)(0 - sign);
		val &= 0xffffffff;
	}
	SET_ZFLG(((uae_s32)(val)) == 0);
	SET_NFLG(((uae_s32)(val)) < 0);
	count_cycles += (2 * ccnt) * CYCLE_UNIT / 2;
	m68k_dreg(regs, dstreg) = (val);
	m68k_incpci(2);
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8+ (1/0) */
/* 2 0,0   */

/* LSR.L Dn,Dn */
uae_u32 REGPARAM2 op_e0a8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 66;
	CurrentInstrCycles = 8;  
	uae_s32 cnt = m68k_dreg(regs, srcreg);
	uae_s32 data = m68k_dreg(regs, dstreg);
	uae_u32 val = data;
	CLEAR_CZNV();
	regs.ir = regs.irc;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		SET_NFLG(val & 0x8000);
		SET_ZFLG(!(val & 0xffff));
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int ccnt = cnt & 63;
	cnt &= 63;
	if (cnt >= 32) {
		SET_CFLG((cnt == 32) & (val >> 31));
		COPY_CARRY();
		val = 0;
	} else if (cnt > 0) {
		val >>= cnt - 1;
		SET_CFLG(val & 1);
		COPY_CARRY();
		val >>= 1;
	}
	SET_ZFLG(((uae_s32)(val)) == 0);
	SET_NFLG(((uae_s32)(val)) < 0);
	count_cycles += (2 * ccnt) * CYCLE_UNIT / 2;
	m68k_dreg(regs, dstreg) = (val);
	m68k_incpci(2);
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8+ (1/0) */
/* 2 0,0   */

/* ROXR.L Dn,Dn */
uae_u32 REGPARAM2 op_e0b0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 71;
	CurrentInstrCycles = 8;  
	uae_s32 cnt = m68k_dreg(regs, srcreg);
	uae_s32 data = m68k_dreg(regs, dstreg);
	uae_u32 val = data;
	CLEAR_CZNV();
	regs.ir = regs.irc;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		SET_NFLG(val & 0x8000);
		SET_ZFLG(!(val & 0xffff));
		SET_CFLG(GET_XFLG());
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int ccnt = cnt & 63;
	cnt &= 63;
	if (cnt >= 33) cnt -= 33;
	if (cnt > 0) {
		cnt--;
		{
			uae_u32 carry;
			uae_u32 hival = (val << 1) | GET_XFLG();
			hival <<= (31 - cnt);
			val >>= cnt;
			carry = val & 1;
			val >>= 1;
			val |= hival;
			SET_XFLG(carry);
			val &= 0xffffffff;
		}
	}
	SET_CFLG(GET_XFLG());
	SET_ZFLG(((uae_s32)(val)) == 0);
	SET_NFLG(((uae_s32)(val)) < 0);
	count_cycles += (2 * ccnt) * CYCLE_UNIT / 2;
	m68k_dreg(regs, dstreg) = (val);
	m68k_incpci(2);
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8+ (1/0) */
/* 2 0,0   */

/* ROR.L Dn,Dn */
uae_u32 REGPARAM2 op_e0b8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 69;
	CurrentInstrCycles = 8;  
	uae_s32 cnt = m68k_dreg(regs, srcreg);
	uae_s32 data = m68k_dreg(regs, dstreg);
	uae_u32 val = data;
	CLEAR_CZNV();
	regs.ir = regs.irc;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		SET_NFLG(val & 0x8000);
		SET_ZFLG(!(val & 0xffff));
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int ccnt = cnt & 63;
	cnt &= 63;
	if (cnt > 0) {
		uae_u32 hival;
		cnt &= 31;
		hival = val << (32 - cnt);
		val >>= cnt;
		val |= hival;
		val &= 0xffffffff;
		SET_CFLG((val & 0x80000000) >> 31);
	}
	SET_ZFLG(((uae_s32)(val)) == 0);
	SET_NFLG(((uae_s32)(val)) < 0);
	count_cycles += (2 * ccnt) * CYCLE_UNIT / 2;
	m68k_dreg(regs, dstreg) = (val);
	m68k_incpci(2);
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8+ (1/0) */
/* 2 0,0   */

/* ASRW.W (An) */
uae_u32 REGPARAM2 op_e0d0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 72;
	CurrentInstrCycles = 8;  
	int loop_mode = regs.loop_mode;
	uaecptr dataa;
	dataa = m68k_areg(regs, srcreg);
	if (dataa & 1) {
		m68k_incpci(2);
		exception3_read_access2(opcode, dataa, 1, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 data = get_word_000(dataa);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dataa + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 val = (uae_u16)data;
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_000_prefetch(4);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			int pcoffset = 0;
			CLEAR_CZNV();
			SET_CFLG(val & 1);
			SET_ZFLG(!(val >> 1));
			SET_NFLG(val & 0x8000);
			SET_XFLG(GET_CFLG());
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return 4 * CYCLE_UNIT / 2 + count_cycles;
		}
		opcode = regs.ir;
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	uae_u32 sign = 0x8000 & val;
	uae_u32 cflg = val & 1;
	val = (val >> 1) | sign;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	SET_CFLG(cflg);
	COPY_CARRY();
	if(loop_mode & 0xfffe) {
		count_cycles += (loop_mode & 0xfffe) * CYCLE_UNIT / 2;
		loop_mode = 1;
	}
	put_word_000(dataa, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dataa + 0, 0x1, val, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (loop_mode) {
		count_cycles += 2 * CYCLE_UNIT / 2;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8+ (1/1) */
/* 2 0,0   */

/* ASRW.W (An)+ */
uae_u32 REGPARAM2 op_e0d8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 72;
	CurrentInstrCycles = 8;  
	int loop_mode = regs.loop_mode;
	uaecptr dataa;
	dataa = m68k_areg(regs, srcreg);
	if (dataa & 1) {
		m68k_areg(regs, srcreg) += 2 + 0;
		m68k_incpci(2);
		exception3_read_access2(opcode, dataa, 1, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 data = get_word_000(dataa);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) += 2 + 0;
		exception2_read(opcode, dataa + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) += 2;
	uae_u32 val = (uae_u16)data;
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_000_prefetch(4);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			int pcoffset = 0;
			CLEAR_CZNV();
			SET_CFLG(val & 1);
			SET_ZFLG(!(val >> 1));
			SET_NFLG(val & 0x8000);
			SET_XFLG(GET_CFLG());
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return 4 * CYCLE_UNIT / 2 + count_cycles;
		}
		opcode = regs.ir;
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	uae_u32 sign = 0x8000 & val;
	uae_u32 cflg = val & 1;
	val = (val >> 1) | sign;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	SET_CFLG(cflg);
	COPY_CARRY();
	if(loop_mode & 0xfffe) {
		count_cycles += (loop_mode & 0xfffe) * CYCLE_UNIT / 2;
		loop_mode = 1;
	}
	put_word_000(dataa, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dataa + 0, 0x1, val, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (loop_mode) {
		count_cycles += 2 * CYCLE_UNIT / 2;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8+ (1/1) */
/* 2 0,0   */

/* ASRW.W -(An) */
uae_u32 REGPARAM2 op_e0e0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 72;
	CurrentInstrCycles = 10; 
	int loop_mode = regs.loop_mode;
	uaecptr dataa;
	dataa = m68k_areg(regs, srcreg) - 2;
	if (dataa & 1) {
		m68k_areg(regs, srcreg) = dataa;
		m68k_incpci(2);
		exception3_read_access2(opcode, dataa, 1, 1);
		return 2 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 data = get_word_000(dataa);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = dataa;
		exception2_read(opcode, dataa + 0, 0x1, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) = dataa;
	uae_u32 val = (uae_u16)data;
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_000_prefetch(4);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			int pcoffset = 0;
			CLEAR_CZNV();
			SET_CFLG(val & 1);
			SET_ZFLG(!(val >> 1));
			SET_NFLG(val & 0x8000);
			SET_XFLG(GET_CFLG());
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return 6 * CYCLE_UNIT / 2 + count_cycles;
		}
		opcode = regs.ir;
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	uae_u32 sign = 0x8000 & val;
	uae_u32 cflg = val & 1;
	val = (val >> 1) | sign;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	SET_CFLG(cflg);
	COPY_CARRY();
	if(loop_mode & 0xfffe) {
		count_cycles += (loop_mode & 0xfffe) * CYCLE_UNIT / 2;
		loop_mode = 1;
	}
	put_word_000(dataa, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dataa + 0, 0x1, val, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (loop_mode) {
		count_cycles += 2 * CYCLE_UNIT / 2;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return 10 * CYCLE_UNIT / 2 + count_cycles;
}
/* 10+ (1/1) */
/* 2 0,0   */

/* ASRW.W (d16,An) */
uae_u32 REGPARAM2 op_e0e8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 72;
	CurrentInstrCycles = 16; 
	uaecptr dataa;
	dataa = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dataa & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dataa, 1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 data = get_word_000(dataa);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dataa + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 val = (uae_u16)data;
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();
		SET_CFLG(val & 1);
		SET_ZFLG(!(val >> 1));
		SET_NFLG(val & 0x8000);
		SET_XFLG(GET_CFLG());
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	uae_u32 sign = 0x8000 & val;
	uae_u32 cflg = val & 1;
	val = (val >> 1) | sign;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	SET_CFLG(cflg);
	COPY_CARRY();
	put_word_000(dataa, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dataa + 0, 0x1, val, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 4 0,0   */

/* ASRW.W (d8,An,Xn) */
uae_u32 REGPARAM2 op_e0f0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 72;
	CurrentInstrCycles = 18; 
	uaecptr dataa;
	BusCyclePenalty += 2;
	dataa = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dataa & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dataa, 1, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 data = get_word_000(dataa);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dataa + 0, 0x1, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 val = (uae_u16)data;
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();
		SET_CFLG(val & 1);
		SET_ZFLG(!(val >> 1));
		SET_NFLG(val & 0x8000);
		SET_XFLG(GET_CFLG());
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	uae_u32 sign = 0x8000 & val;
	uae_u32 cflg = val & 1;
	val = (val >> 1) | sign;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	SET_CFLG(cflg);
	COPY_CARRY();
	put_word_000(dataa, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dataa + 0, 0x1, val, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (3/1) */
/* 4 4,0   */

/* ASRW.W (xxx).W */
uae_u32 REGPARAM2 op_e0f8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 72;
	CurrentInstrCycles = 16; 
	uaecptr dataa;
	dataa = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dataa & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, dataa, 1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 data = get_word_000(dataa);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dataa + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 val = (uae_u16)data;
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();
		SET_CFLG(val & 1);
		SET_ZFLG(!(val >> 1));
		SET_NFLG(val & 0x8000);
		SET_XFLG(GET_CFLG());
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	uae_u32 sign = 0x8000 & val;
	uae_u32 cflg = val & 1;
	val = (val >> 1) | sign;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	SET_CFLG(cflg);
	COPY_CARRY();
	put_word_000(dataa, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dataa + 0, 0x1, val, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 4 0,0   */

/* ASRW.W (xxx).L */
uae_u32 REGPARAM2 op_e0f9_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 72;
	CurrentInstrCycles = 20; 
	uaecptr dataa;
	dataa = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	dataa |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dataa & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, dataa, 1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 data = get_word_000(dataa);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dataa + 0, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 val = (uae_u16)data;
	regs.ir = regs.irc;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();
		SET_CFLG(val & 1);
		SET_ZFLG(!(val >> 1));
		SET_NFLG(val & 0x8000);
		SET_XFLG(GET_CFLG());
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	uae_u32 sign = 0x8000 & val;
	uae_u32 cflg = val & 1;
	val = (val >> 1) | sign;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	SET_CFLG(cflg);
	COPY_CARRY();
	put_word_000(dataa, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dataa + 0, 0x1, val, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (4/1) */
/* 6 0,0   */

/* ASLQ.B #<data>,Dn */
uae_u32 REGPARAM2 op_e100_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 65;
	CurrentInstrCycles = 6;  
	uae_u32 cnt = srcreg;
	uae_s8 data = m68k_dreg(regs, dstreg);
	uae_u32 val = (uae_u8)data;
	CLEAR_CZNV();
	regs.ir = regs.irc;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		SET_ZFLG(!(val & 0xff));
		SET_NFLG(val & 0x80);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int ccnt = cnt & 63;
	cnt &= 63;
	if (cnt >= 8) {
		SET_VFLG(val != 0);
		SET_CFLG(cnt == 8 ? val & 1 : 0);
		COPY_CARRY();
		val = 0;
	} else {
		uae_u32 mask = (0xff << (7 - cnt)) & 0xff;
		SET_VFLG((val & mask) != mask && (val & mask) != 0);
		val <<= cnt - 1;
		SET_CFLG((val & 0x80) >> 7);
		COPY_CARRY();
		val <<= 1;
		val &= 0xff;
	}
	SET_ZFLG(((uae_s8)(val)) == 0);
	SET_NFLG(((uae_s8)(val)) < 0);
	count_cycles += (2 * ccnt) * CYCLE_UNIT / 2;
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((val) & 0xff);
	m68k_incpci(2);
	return 6 * CYCLE_UNIT / 2 + count_cycles;
}
/* 6+ (1/0) */
/* 2 0,0   */

/* LSLQ.B #<data>,Dn */
uae_u32 REGPARAM2 op_e108_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 67;
	CurrentInstrCycles = 6;  
	uae_u32 cnt = srcreg;
	uae_s8 data = m68k_dreg(regs, dstreg);
	uae_u32 val = (uae_u8)data;
	CLEAR_CZNV();
	regs.ir = regs.irc;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		SET_ZFLG(!(val & 0xff));
		SET_NFLG(val & 0x80);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int ccnt = cnt & 63;
	cnt &= 63;
	if (cnt >= 8) {
		SET_CFLG(cnt == 8 ? val & 1 : 0);
		COPY_CARRY();
		val = 0;
	} else {
		val <<= (cnt - 1);
		SET_CFLG((val & 0x80) >> 7);
		COPY_CARRY();
		val <<= 1;
		val &= 0xff;
	}
	SET_ZFLG(((uae_s8)(val)) == 0);
	SET_NFLG(((uae_s8)(val)) < 0);
	count_cycles += (2 * ccnt) * CYCLE_UNIT / 2;
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((val) & 0xff);
	m68k_incpci(2);
	return 6 * CYCLE_UNIT / 2 + count_cycles;
}
/* 6+ (1/0) */
/* 2 0,0   */

/* ROXLQ.B #<data>,Dn */
uae_u32 REGPARAM2 op_e110_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 70;
	CurrentInstrCycles = 6;  
	uae_u32 cnt = srcreg;
	uae_s8 data = m68k_dreg(regs, dstreg);
	uae_u32 val = (uae_u8)data;
	CLEAR_CZNV();
	regs.ir = regs.irc;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		SET_ZFLG(!(val & 0xff));
		SET_NFLG(val & 0x80);
		SET_CFLG(GET_XFLG());
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int ccnt = cnt & 63;
	cnt &= 63;
	{
		cnt--;
		{
			uae_u32 carry;
			uae_u32 loval = val >> (7 - cnt);
			carry = loval & 1;
			val = (((val << 1) | GET_XFLG()) << cnt) | (loval >> 1);
			SET_XFLG(carry);
			val &= 0xff;
		}
	}
	SET_CFLG(GET_XFLG());
	SET_ZFLG(((uae_s8)(val)) == 0);
	SET_NFLG(((uae_s8)(val)) < 0);
	count_cycles += (2 * ccnt) * CYCLE_UNIT / 2;
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((val) & 0xff);
	m68k_incpci(2);
	return 6 * CYCLE_UNIT / 2 + count_cycles;
}
/* 6+ (1/0) */
/* 2 0,0   */

/* ROLQ.B #<data>,Dn */
uae_u32 REGPARAM2 op_e118_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 68;
	CurrentInstrCycles = 6;  
	uae_u32 cnt = srcreg;
	uae_s8 data = m68k_dreg(regs, dstreg);
	uae_u32 val = (uae_u8)data;
	CLEAR_CZNV();
	regs.ir = regs.irc;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		SET_ZFLG(!(val & 0xff));
		SET_NFLG(val & 0x80);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int ccnt = cnt & 63;
	cnt &= 63;
	{
		uae_u32 loval;
		cnt &= 7;
		loval = val >> (8 - cnt);
		val <<= cnt;
		val |= loval;
		val &= 0xff;
		SET_CFLG(val & 1);
	}
	SET_ZFLG(((uae_s8)(val)) == 0);
	SET_NFLG(((uae_s8)(val)) < 0);
	count_cycles += (2 * ccnt) * CYCLE_UNIT / 2;
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((val) & 0xff);
	m68k_incpci(2);
	return 6 * CYCLE_UNIT / 2 + count_cycles;
}
/* 6+ (1/0) */
/* 2 0,0   */

/* ASL.B Dn,Dn */
uae_u32 REGPARAM2 op_e120_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 65;
	CurrentInstrCycles = 6;  
	uae_s8 cnt = m68k_dreg(regs, srcreg);
	uae_s8 data = m68k_dreg(regs, dstreg);
	uae_u32 val = (uae_u8)data;
	CLEAR_CZNV();
	regs.ir = regs.irc;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		SET_ZFLG(!(val & 0xff));
		SET_NFLG(val & 0x80);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int ccnt = cnt & 63;
	cnt &= 63;
	if (cnt >= 8) {
		SET_VFLG(val != 0);
		SET_CFLG(cnt == 8 ? val & 1 : 0);
		COPY_CARRY();
		val = 0;
	} else if (cnt > 0) {
		uae_u32 mask = (0xff << (7 - cnt)) & 0xff;
		SET_VFLG((val & mask) != mask && (val & mask) != 0);
		val <<= cnt - 1;
		SET_CFLG((val & 0x80) >> 7);
		COPY_CARRY();
		val <<= 1;
		val &= 0xff;
	}
	SET_ZFLG(((uae_s8)(val)) == 0);
	SET_NFLG(((uae_s8)(val)) < 0);
	count_cycles += (2 * ccnt) * CYCLE_UNIT / 2;
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((val) & 0xff);
	m68k_incpci(2);
	return 6 * CYCLE_UNIT / 2 + count_cycles;
}
/* 6+ (1/0) */
/* 2 0,0   */

/* LSL.B Dn,Dn */
uae_u32 REGPARAM2 op_e128_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 67;
	CurrentInstrCycles = 6;  
	uae_s8 cnt = m68k_dreg(regs, srcreg);
	uae_s8 data = m68k_dreg(regs, dstreg);
	uae_u32 val = (uae_u8)data;
	CLEAR_CZNV();
	regs.ir = regs.irc;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		SET_ZFLG(!(val & 0xff));
		SET_NFLG(val & 0x80);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int ccnt = cnt & 63;
	cnt &= 63;
	if (cnt >= 8) {
		SET_CFLG(cnt == 8 ? val & 1 : 0);
		COPY_CARRY();
		val = 0;
	} else if (cnt > 0) {
		val <<= (cnt - 1);
		SET_CFLG((val & 0x80) >> 7);
		COPY_CARRY();
		val <<= 1;
		val &= 0xff;
	}
	SET_ZFLG(((uae_s8)(val)) == 0);
	SET_NFLG(((uae_s8)(val)) < 0);
	count_cycles += (2 * ccnt) * CYCLE_UNIT / 2;
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((val) & 0xff);
	m68k_incpci(2);
	return 6 * CYCLE_UNIT / 2 + count_cycles;
}
/* 6+ (1/0) */
/* 2 0,0   */

/* ROXL.B Dn,Dn */
uae_u32 REGPARAM2 op_e130_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 70;
	CurrentInstrCycles = 6;  
	uae_s8 cnt = m68k_dreg(regs, srcreg);
	uae_s8 data = m68k_dreg(regs, dstreg);
	uae_u32 val = (uae_u8)data;
	CLEAR_CZNV();
	regs.ir = regs.irc;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		SET_ZFLG(!(val & 0xff));
		SET_NFLG(val & 0x80);
		SET_CFLG(GET_XFLG());
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int ccnt = cnt & 63;
	cnt &= 63;
	if (cnt >= 36) cnt -= 36;
	if (cnt >= 18) cnt -= 18;
	if (cnt >= 9) cnt -= 9;
	if (cnt > 0) {
		cnt--;
		{
			uae_u32 carry;
			uae_u32 loval = val >> (7 - cnt);
			carry = loval & 1;
			val = (((val << 1) | GET_XFLG()) << cnt) | (loval >> 1);
			SET_XFLG(carry);
			val &= 0xff;
		}
	}
	SET_CFLG(GET_XFLG());
	SET_ZFLG(((uae_s8)(val)) == 0);
	SET_NFLG(((uae_s8)(val)) < 0);
	count_cycles += (2 * ccnt) * CYCLE_UNIT / 2;
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((val) & 0xff);
	m68k_incpci(2);
	return 6 * CYCLE_UNIT / 2 + count_cycles;
}
/* 6+ (1/0) */
/* 2 0,0   */

/* ROL.B Dn,Dn */
uae_u32 REGPARAM2 op_e138_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 68;
	CurrentInstrCycles = 6;  
	uae_s8 cnt = m68k_dreg(regs, srcreg);
	uae_s8 data = m68k_dreg(regs, dstreg);
	uae_u32 val = (uae_u8)data;
	CLEAR_CZNV();
	regs.ir = regs.irc;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		SET_ZFLG(!(val & 0xff));
		SET_NFLG(val & 0x80);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int ccnt = cnt & 63;
	cnt &= 63;
	if (cnt > 0) {
		uae_u32 loval;
		cnt &= 7;
		loval = val >> (8 - cnt);
		val <<= cnt;
		val |= loval;
		val &= 0xff;
		SET_CFLG(val & 1);
	}
	SET_ZFLG(((uae_s8)(val)) == 0);
	SET_NFLG(((uae_s8)(val)) < 0);
	count_cycles += (2 * ccnt) * CYCLE_UNIT / 2;
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((val) & 0xff);
	m68k_incpci(2);
	return 6 * CYCLE_UNIT / 2 + count_cycles;
}
/* 6+ (1/0) */
/* 2 0,0   */

/* ASLQ.W #<data>,Dn */
uae_u32 REGPARAM2 op_e140_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 65;
	CurrentInstrCycles = 6;  
	uae_u32 cnt = srcreg;
	uae_s16 data = m68k_dreg(regs, dstreg);
	uae_u32 val = (uae_u16)data;
	CLEAR_CZNV();
	regs.ir = regs.irc;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		SET_ZFLG(!(val & 0xffff));
		SET_NFLG(val & 0x8000);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int ccnt = cnt & 63;
	cnt &= 63;
	if (cnt >= 16) {
		SET_VFLG(val != 0);
		SET_CFLG(cnt == 16 ? val & 1 : 0);
		COPY_CARRY();
		val = 0;
	} else {
		uae_u32 mask = (0xffff << (15 - cnt)) & 0xffff;
		SET_VFLG((val & mask) != mask && (val & mask) != 0);
		val <<= cnt - 1;
		SET_CFLG((val & 0x8000) >> 15);
		COPY_CARRY();
		val <<= 1;
		val &= 0xffff;
	}
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	count_cycles += (2 * ccnt) * CYCLE_UNIT / 2;
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((val) & 0xffff);
	m68k_incpci(2);
	return 6 * CYCLE_UNIT / 2 + count_cycles;
}
/* 6+ (1/0) */
/* 2 0,0   */

/* LSLQ.W #<data>,Dn */
uae_u32 REGPARAM2 op_e148_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 67;
	CurrentInstrCycles = 6;  
	uae_u32 cnt = srcreg;
	uae_s16 data = m68k_dreg(regs, dstreg);
	uae_u32 val = (uae_u16)data;
	CLEAR_CZNV();
	regs.ir = regs.irc;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		SET_ZFLG(!(val & 0xffff));
		SET_NFLG(val & 0x8000);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int ccnt = cnt & 63;
	cnt &= 63;
	if (cnt >= 16) {
		SET_CFLG(cnt == 16 ? val & 1 : 0);
		COPY_CARRY();
		val = 0;
	} else {
		val <<= (cnt - 1);
		SET_CFLG((val & 0x8000) >> 15);
		COPY_CARRY();
		val <<= 1;
		val &= 0xffff;
	}
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	count_cycles += (2 * ccnt) * CYCLE_UNIT / 2;
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((val) & 0xffff);
	m68k_incpci(2);
	return 6 * CYCLE_UNIT / 2 + count_cycles;
}
/* 6+ (1/0) */
/* 2 0,0   */

/* ROXLQ.W #<data>,Dn */
uae_u32 REGPARAM2 op_e150_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 70;
	CurrentInstrCycles = 6;  
	uae_u32 cnt = srcreg;
	uae_s16 data = m68k_dreg(regs, dstreg);
	uae_u32 val = (uae_u16)data;
	CLEAR_CZNV();
	regs.ir = regs.irc;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		SET_ZFLG(!(val & 0xffff));
		SET_NFLG(val & 0x8000);
		SET_CFLG(GET_XFLG());
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int ccnt = cnt & 63;
	cnt &= 63;
	{
		cnt--;
		{
			uae_u32 carry;
			uae_u32 loval = val >> (15 - cnt);
			carry = loval & 1;
			val = (((val << 1) | GET_XFLG()) << cnt) | (loval >> 1);
			SET_XFLG(carry);
			val &= 0xffff;
		}
	}
	SET_CFLG(GET_XFLG());
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	count_cycles += (2 * ccnt) * CYCLE_UNIT / 2;
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((val) & 0xffff);
	m68k_incpci(2);
	return 6 * CYCLE_UNIT / 2 + count_cycles;
}
/* 6+ (1/0) */
/* 2 0,0   */

/* ROLQ.W #<data>,Dn */
uae_u32 REGPARAM2 op_e158_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 68;
	CurrentInstrCycles = 6;  
	uae_u32 cnt = srcreg;
	uae_s16 data = m68k_dreg(regs, dstreg);
	uae_u32 val = (uae_u16)data;
	CLEAR_CZNV();
	regs.ir = regs.irc;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		SET_ZFLG(!(val & 0xffff));
		SET_NFLG(val & 0x8000);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int ccnt = cnt & 63;
	cnt &= 63;
	{
		uae_u32 loval;
		cnt &= 15;
		loval = val >> (16 - cnt);
		val <<= cnt;
		val |= loval;
		val &= 0xffff;
		SET_CFLG(val & 1);
	}
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	count_cycles += (2 * ccnt) * CYCLE_UNIT / 2;
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((val) & 0xffff);
	m68k_incpci(2);
	return 6 * CYCLE_UNIT / 2 + count_cycles;
}
/* 6+ (1/0) */
/* 2 0,0   */

/* ASL.W Dn,Dn */
uae_u32 REGPARAM2 op_e160_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 65;
	CurrentInstrCycles = 6;  
	uae_s16 cnt = m68k_dreg(regs, srcreg);
	uae_s16 data = m68k_dreg(regs, dstreg);
	uae_u32 val = (uae_u16)data;
	CLEAR_CZNV();
	regs.ir = regs.irc;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		SET_ZFLG(!(val & 0xffff));
		SET_NFLG(val & 0x8000);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int ccnt = cnt & 63;
	cnt &= 63;
	if (cnt >= 16) {
		SET_VFLG(val != 0);
		SET_CFLG(cnt == 16 ? val & 1 : 0);
		COPY_CARRY();
		val = 0;
	} else if (cnt > 0) {
		uae_u32 mask = (0xffff << (15 - cnt)) & 0xffff;
		SET_VFLG((val & mask) != mask && (val & mask) != 0);
		val <<= cnt - 1;
		SET_CFLG((val & 0x8000) >> 15);
		COPY_CARRY();
		val <<= 1;
		val &= 0xffff;
	}
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	count_cycles += (2 * ccnt) * CYCLE_UNIT / 2;
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((val) & 0xffff);
	m68k_incpci(2);
	return 6 * CYCLE_UNIT / 2 + count_cycles;
}
/* 6+ (1/0) */
/* 2 0,0   */

/* LSL.W Dn,Dn */
uae_u32 REGPARAM2 op_e168_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 67;
	CurrentInstrCycles = 6;  
	uae_s16 cnt = m68k_dreg(regs, srcreg);
	uae_s16 data = m68k_dreg(regs, dstreg);
	uae_u32 val = (uae_u16)data;
	CLEAR_CZNV();
	regs.ir = regs.irc;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		SET_ZFLG(!(val & 0xffff));
		SET_NFLG(val & 0x8000);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int ccnt = cnt & 63;
	cnt &= 63;
	if (cnt >= 16) {
		SET_CFLG(cnt == 16 ? val & 1 : 0);
		COPY_CARRY();
		val = 0;
	} else if (cnt > 0) {
		val <<= (cnt - 1);
		SET_CFLG((val & 0x8000) >> 15);
		COPY_CARRY();
		val <<= 1;
		val &= 0xffff;
	}
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	count_cycles += (2 * ccnt) * CYCLE_UNIT / 2;
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((val) & 0xffff);
	m68k_incpci(2);
	return 6 * CYCLE_UNIT / 2 + count_cycles;
}
/* 6+ (1/0) */
/* 2 0,0   */

/* ROXL.W Dn,Dn */
uae_u32 REGPARAM2 op_e170_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 70;
	CurrentInstrCycles = 6;  
	uae_s16 cnt = m68k_dreg(regs, srcreg);
	uae_s16 data = m68k_dreg(regs, dstreg);
	uae_u32 val = (uae_u16)data;
	CLEAR_CZNV();
	regs.ir = regs.irc;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		SET_ZFLG(!(val & 0xffff));
		SET_NFLG(val & 0x8000);
		SET_CFLG(GET_XFLG());
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int ccnt = cnt & 63;
	cnt &= 63;
	if (cnt >= 34) cnt -= 34;
	if (cnt >= 17) cnt -= 17;
	if (cnt > 0) {
		cnt--;
		{
			uae_u32 carry;
			uae_u32 loval = val >> (15 - cnt);
			carry = loval & 1;
			val = (((val << 1) | GET_XFLG()) << cnt) | (loval >> 1);
			SET_XFLG(carry);
			val &= 0xffff;
		}
	}
	SET_CFLG(GET_XFLG());
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	count_cycles += (2 * ccnt) * CYCLE_UNIT / 2;
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((val) & 0xffff);
	m68k_incpci(2);
	return 6 * CYCLE_UNIT / 2 + count_cycles;
}
/* 6+ (1/0) */
/* 2 0,0   */

/* ROL.W Dn,Dn */
uae_u32 REGPARAM2 op_e178_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 68;
	CurrentInstrCycles = 6;  
	uae_s16 cnt = m68k_dreg(regs, srcreg);
	uae_s16 data = m68k_dreg(regs, dstreg);
	uae_u32 val = (uae_u16)data;
	CLEAR_CZNV();
	regs.ir = regs.irc;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		SET_ZFLG(!(val & 0xffff));
		SET_NFLG(val & 0x8000);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int ccnt = cnt & 63;
	cnt &= 63;
	if (cnt > 0) {
		uae_u32 loval;
		cnt &= 15;
		loval = val >> (16 - cnt);
		val <<= cnt;
		val |= loval;
		val &= 0xffff;
		SET_CFLG(val & 1);
	}
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	count_cycles += (2 * ccnt) * CYCLE_UNIT / 2;
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((val) & 0xffff);
	m68k_incpci(2);
	return 6 * CYCLE_UNIT / 2 + count_cycles;
}
/* 6+ (1/0) */
/* 2 0,0   */

/* ASLQ.L #<data>,Dn */
uae_u32 REGPARAM2 op_e180_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 65;
	CurrentInstrCycles = 8;  
	uae_u32 cnt = srcreg;
	uae_s32 data = m68k_dreg(regs, dstreg);
	uae_u32 val = data;
	CLEAR_CZNV();
	regs.ir = regs.irc;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		SET_NFLG(val & 0x8000);
		SET_ZFLG(!(val & 0xffff));
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int ccnt = cnt & 63;
	cnt &= 63;
	if (cnt >= 32) {
		SET_VFLG(val != 0);
		SET_CFLG(cnt == 32 ? val & 1 : 0);
		COPY_CARRY();
		val = 0;
	} else {
		uae_u32 mask = (0xffffffff << (31 - cnt)) & 0xffffffff;
		SET_VFLG((val & mask) != mask && (val & mask) != 0);
		val <<= cnt - 1;
		SET_CFLG((val & 0x80000000) >> 31);
		COPY_CARRY();
		val <<= 1;
		val &= 0xffffffff;
	}
	SET_ZFLG(((uae_s32)(val)) == 0);
	SET_NFLG(((uae_s32)(val)) < 0);
	count_cycles += (2 * ccnt) * CYCLE_UNIT / 2;
	m68k_dreg(regs, dstreg) = (val);
	m68k_incpci(2);
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8+ (1/0) */
/* 2 0,0   */

/* LSLQ.L #<data>,Dn */
uae_u32 REGPARAM2 op_e188_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 67;
	CurrentInstrCycles = 8;  
	uae_u32 cnt = srcreg;
	uae_s32 data = m68k_dreg(regs, dstreg);
	uae_u32 val = data;
	CLEAR_CZNV();
	regs.ir = regs.irc;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		SET_NFLG(val & 0x8000);
		SET_ZFLG(!(val & 0xffff));
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int ccnt = cnt & 63;
	cnt &= 63;
	if (cnt >= 32) {
		SET_CFLG(cnt == 32 ? val & 1 : 0);
		COPY_CARRY();
		val = 0;
	} else {
		val <<= (cnt - 1);
		SET_CFLG((val & 0x80000000) >> 31);
		COPY_CARRY();
		val <<= 1;
		val &= 0xffffffff;
	}
	SET_ZFLG(((uae_s32)(val)) == 0);
	SET_NFLG(((uae_s32)(val)) < 0);
	count_cycles += (2 * ccnt) * CYCLE_UNIT / 2;
	m68k_dreg(regs, dstreg) = (val);
	m68k_incpci(2);
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8+ (1/0) */
/* 2 0,0   */

/* ROXLQ.L #<data>,Dn */
uae_u32 REGPARAM2 op_e190_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 70;
	CurrentInstrCycles = 8;  
	uae_u32 cnt = srcreg;
	uae_s32 data = m68k_dreg(regs, dstreg);
	uae_u32 val = data;
	CLEAR_CZNV();
	regs.ir = regs.irc;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		SET_NFLG(val & 0x8000);
		SET_ZFLG(!(val & 0xffff));
		SET_CFLG(GET_XFLG());
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int ccnt = cnt & 63;
	cnt &= 63;
	{
		cnt--;
		{
			uae_u32 carry;
			uae_u32 loval = val >> (31 - cnt);
			carry = loval & 1;
			val = (((val << 1) | GET_XFLG()) << cnt) | (loval >> 1);
			SET_XFLG(carry);
			val &= 0xffffffff;
		}
	}
	SET_CFLG(GET_XFLG());
	SET_ZFLG(((uae_s32)(val)) == 0);
	SET_NFLG(((uae_s32)(val)) < 0);
	count_cycles += (2 * ccnt) * CYCLE_UNIT / 2;
	m68k_dreg(regs, dstreg) = (val);
	m68k_incpci(2);
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8+ (1/0) */
/* 2 0,0   */

/* ROLQ.L #<data>,Dn */
uae_u32 REGPARAM2 op_e198_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 68;
	CurrentInstrCycles = 8;  
	uae_u32 cnt = srcreg;
	uae_s32 data = m68k_dreg(regs, dstreg);
	uae_u32 val = data;
	CLEAR_CZNV();
	regs.ir = regs.irc;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		SET_NFLG(val & 0x8000);
		SET_ZFLG(!(val & 0xffff));
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int ccnt = cnt & 63;
	cnt &= 63;
	{
		uae_u32 loval;
		cnt &= 31;
		loval = val >> (32 - cnt);
		val <<= cnt;
		val |= loval;
		val &= 0xffffffff;
		SET_CFLG(val & 1);
	}
	SET_ZFLG(((uae_s32)(val)) == 0);
	SET_NFLG(((uae_s32)(val)) < 0);
	count_cycles += (2 * ccnt) * CYCLE_UNIT / 2;
	m68k_dreg(regs, dstreg) = (val);
	m68k_incpci(2);
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8+ (1/0) */
/* 2 0,0   */

/* ASL.L Dn,Dn */
uae_u32 REGPARAM2 op_e1a0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 65;
	CurrentInstrCycles = 8;  
	uae_s32 cnt = m68k_dreg(regs, srcreg);
	uae_s32 data = m68k_dreg(regs, dstreg);
	uae_u32 val = data;
	CLEAR_CZNV();
	regs.ir = regs.irc;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		SET_NFLG(val & 0x8000);
		SET_ZFLG(!(val & 0xffff));
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int ccnt = cnt & 63;
	cnt &= 63;
	if (cnt >= 32) {
		SET_VFLG(val != 0);
		SET_CFLG(cnt == 32 ? val & 1 : 0);
		COPY_CARRY();
		val = 0;
	} else if (cnt > 0) {
		uae_u32 mask = (0xffffffff << (31 - cnt)) & 0xffffffff;
		SET_VFLG((val & mask) != mask && (val & mask) != 0);
		val <<= cnt - 1;
		SET_CFLG((val & 0x80000000) >> 31);
		COPY_CARRY();
		val <<= 1;
		val &= 0xffffffff;
	}
	SET_ZFLG(((uae_s32)(val)) == 0);
	SET_NFLG(((uae_s32)(val)) < 0);
	count_cycles += (2 * ccnt) * CYCLE_UNIT / 2;
	m68k_dreg(regs, dstreg) = (val);
	m68k_incpci(2);
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8+ (1/0) */
/* 2 0,0   */

/* LSL.L Dn,Dn */
uae_u32 REGPARAM2 op_e1a8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 67;
	CurrentInstrCycles = 8;  
	uae_s32 cnt = m68k_dreg(regs, srcreg);
	uae_s32 data = m68k_dreg(regs, dstreg);
	uae_u32 val = data;
	CLEAR_CZNV();
	regs.ir = regs.irc;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		SET_NFLG(val & 0x8000);
		SET_ZFLG(!(val & 0xffff));
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int ccnt = cnt & 63;
	cnt &= 63;
	if (cnt >= 32) {
		SET_CFLG(cnt == 32 ? val & 1 : 0);
		COPY_CARRY();
		val = 0;
	} else if (cnt > 0) {
		val <<= (cnt - 1);
		SET_CFLG((val & 0x80000000) >> 31);
		COPY_CARRY();
		val <<= 1;
		val &= 0xffffffff;
	}
	SET_ZFLG(((uae_s32)(val)) == 0);
	SET_NFLG(((uae_s32)(val)) < 0);
	count_cycles += (2 * ccnt) * CYCLE_UNIT / 2;
	m68k_dreg(regs, dstreg) = (val);
	m68k_incpci(2);
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8+ (1/0) */
/* 2 0,0   */

/* ROXL.L Dn,Dn */
uae_u32 REGPARAM2 op_e1b0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 70;
	CurrentInstrCycles = 8;  
	uae_s32 cnt = m68k_dreg(regs, srcreg);
	uae_s32 data = m68k_dreg(regs, dstreg);
	uae_u32 val = data;
	CLEAR_CZNV();
	regs.ir = regs.irc;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		SET_NFLG(val & 0x8000);
		SET_ZFLG(!(val & 0xffff));
		SET_CFLG(GET_XFLG());
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int ccnt = cnt & 63;
	cnt &= 63;
	if (cnt >= 33) cnt -= 33;
	if (cnt > 0) {
		cnt--;
		{
			uae_u32 carry;
			uae_u32 loval = val >> (31 - cnt);
			carry = loval & 1;
			val = (((val << 1) | GET_XFLG()) << cnt) | (loval >> 1);
			SET_XFLG(carry);
			val &= 0xffffffff;
		}
	}
	SET_CFLG(GET_XFLG());
	SET_ZFLG(((uae_s32)(val)) == 0);
	SET_NFLG(((uae_s32)(val)) < 0);
	count_cycles += (2 * ccnt) * CYCLE_UNIT / 2;
	m68k_dreg(regs, dstreg) = (val);
	m68k_incpci(2);
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8+ (1/0) */
/* 2 0,0   */

/* ROL.L Dn,Dn */
uae_u32 REGPARAM2 op_e1b8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 68;
	CurrentInstrCycles = 8;  
	uae_s32 cnt = m68k_dreg(regs, srcreg);
	uae_s32 data = m68k_dreg(regs, dstreg);
	uae_u32 val = data;
	CLEAR_CZNV();
	regs.ir = regs.irc;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		SET_NFLG(val & 0x8000);
		SET_ZFLG(!(val & 0xffff));
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int ccnt = cnt & 63;
	cnt &= 63;
	if (cnt > 0) {
		uae_u32 loval;
		cnt &= 31;
		loval = val >> (32 - cnt);
		val <<= cnt;
		val |= loval;
		val &= 0xffffffff;
		SET_CFLG(val & 1);
	}
	SET_ZFLG(((uae_s32)(val)) == 0);
	SET_NFLG(((uae_s32)(val)) < 0);
	count_cycles += (2 * ccnt) * CYCLE_UNIT / 2;
	m68k_dreg(regs, dstreg) = (val);
	m68k_incpci(2);
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8+ (1/0) */
/* 2 0,0   */

/* ASLW.W (An) */
uae_u32 REGPARAM2 op_e1d0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 73;
	CurrentInstrCycles = 8;  
	int loop_mode = regs.loop_mode;
	uaecptr dataa;
	dataa = m68k_areg(regs, srcreg);
	if (dataa & 1) {
		m68k_incpci(2);
		exception3_read_access2(opcode, dataa, 1, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 data = get_word_000(dataa);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dataa + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 val = (uae_u16)data;
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_000_prefetch(4);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			int pcoffset = 0;
			CLEAR_CZNV();
			SET_CFLG(val & 0x8000);
			SET_ZFLG(!(val & 0x7fff));
			SET_NFLG(val & 0x4000);
			SET_XFLG(GET_CFLG());
			SET_VFLG((val & 0x8000) != ((val << 1) & 0x8000));
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return 4 * CYCLE_UNIT / 2 + count_cycles;
		}
		opcode = regs.ir;
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	uae_u32 sign = 0x8000 & val;
	uae_u32 sign2;
	val <<= 1;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	sign2 = 0x8000 & val;
	SET_CFLG(sign != 0);
	COPY_CARRY();
	SET_VFLG(GET_VFLG() | (sign2 != sign));
	if(loop_mode & 0xfffe) {
		count_cycles += (loop_mode & 0xfffe) * CYCLE_UNIT / 2;
		loop_mode = 1;
	}
	put_word_000(dataa, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dataa + 0, 0x1, val, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (loop_mode) {
		count_cycles += 2 * CYCLE_UNIT / 2;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8+ (1/1) */
/* 2 0,0   */

/* ASLW.W (An)+ */
uae_u32 REGPARAM2 op_e1d8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 73;
	CurrentInstrCycles = 8;  
	int loop_mode = regs.loop_mode;
	uaecptr dataa;
	dataa = m68k_areg(regs, srcreg);
	if (dataa & 1) {
		m68k_areg(regs, srcreg) += 2 + 0;
		m68k_incpci(2);
		exception3_read_access2(opcode, dataa, 1, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 data = get_word_000(dataa);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) += 2 + 0;
		exception2_read(opcode, dataa + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) += 2;
	uae_u32 val = (uae_u16)data;
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_000_prefetch(4);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			int pcoffset = 0;
			CLEAR_CZNV();
			SET_CFLG(val & 0x8000);
			SET_ZFLG(!(val & 0x7fff));
			SET_NFLG(val & 0x4000);
			SET_XFLG(GET_CFLG());
			SET_VFLG((val & 0x8000) != ((val << 1) & 0x8000));
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return 4 * CYCLE_UNIT / 2 + count_cycles;
		}
		opcode = regs.ir;
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	uae_u32 sign = 0x8000 & val;
	uae_u32 sign2;
	val <<= 1;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	sign2 = 0x8000 & val;
	SET_CFLG(sign != 0);
	COPY_CARRY();
	SET_VFLG(GET_VFLG() | (sign2 != sign));
	if(loop_mode & 0xfffe) {
		count_cycles += (loop_mode & 0xfffe) * CYCLE_UNIT / 2;
		loop_mode = 1;
	}
	put_word_000(dataa, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dataa + 0, 0x1, val, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (loop_mode) {
		count_cycles += 2 * CYCLE_UNIT / 2;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8+ (1/1) */
/* 2 0,0   */

/* ASLW.W -(An) */
uae_u32 REGPARAM2 op_e1e0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 73;
	CurrentInstrCycles = 10; 
	int loop_mode = regs.loop_mode;
	uaecptr dataa;
	dataa = m68k_areg(regs, srcreg) - 2;
	if (dataa & 1) {
		m68k_areg(regs, srcreg) = dataa;
		m68k_incpci(2);
		exception3_read_access2(opcode, dataa, 1, 1);
		return 2 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 data = get_word_000(dataa);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = dataa;
		exception2_read(opcode, dataa + 0, 0x1, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) = dataa;
	uae_u32 val = (uae_u16)data;
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_000_prefetch(4);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			int pcoffset = 0;
			CLEAR_CZNV();
			SET_CFLG(val & 0x8000);
			SET_ZFLG(!(val & 0x7fff));
			SET_NFLG(val & 0x4000);
			SET_XFLG(GET_CFLG());
			SET_VFLG((val & 0x8000) != ((val << 1) & 0x8000));
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return 6 * CYCLE_UNIT / 2 + count_cycles;
		}
		opcode = regs.ir;
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	uae_u32 sign = 0x8000 & val;
	uae_u32 sign2;
	val <<= 1;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	sign2 = 0x8000 & val;
	SET_CFLG(sign != 0);
	COPY_CARRY();
	SET_VFLG(GET_VFLG() | (sign2 != sign));
	if(loop_mode & 0xfffe) {
		count_cycles += (loop_mode & 0xfffe) * CYCLE_UNIT / 2;
		loop_mode = 1;
	}
	put_word_000(dataa, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dataa + 0, 0x1, val, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (loop_mode) {
		count_cycles += 2 * CYCLE_UNIT / 2;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return 10 * CYCLE_UNIT / 2 + count_cycles;
}
/* 10+ (1/1) */
/* 2 0,0   */

/* ASLW.W (d16,An) */
uae_u32 REGPARAM2 op_e1e8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 73;
	CurrentInstrCycles = 16; 
	uaecptr dataa;
	dataa = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dataa & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dataa, 1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 data = get_word_000(dataa);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dataa + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 val = (uae_u16)data;
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();
		SET_CFLG(val & 0x8000);
		SET_ZFLG(!(val & 0x7fff));
		SET_NFLG(val & 0x4000);
		SET_XFLG(GET_CFLG());
		SET_VFLG((val & 0x8000) != ((val << 1) & 0x8000));
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	uae_u32 sign = 0x8000 & val;
	uae_u32 sign2;
	val <<= 1;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	sign2 = 0x8000 & val;
	SET_CFLG(sign != 0);
	COPY_CARRY();
	SET_VFLG(GET_VFLG() | (sign2 != sign));
	put_word_000(dataa, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dataa + 0, 0x1, val, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 4 0,0   */

/* ASLW.W (d8,An,Xn) */
uae_u32 REGPARAM2 op_e1f0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 73;
	CurrentInstrCycles = 18; 
	uaecptr dataa;
	BusCyclePenalty += 2;
	dataa = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dataa & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dataa, 1, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 data = get_word_000(dataa);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dataa + 0, 0x1, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 val = (uae_u16)data;
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();
		SET_CFLG(val & 0x8000);
		SET_ZFLG(!(val & 0x7fff));
		SET_NFLG(val & 0x4000);
		SET_XFLG(GET_CFLG());
		SET_VFLG((val & 0x8000) != ((val << 1) & 0x8000));
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	uae_u32 sign = 0x8000 & val;
	uae_u32 sign2;
	val <<= 1;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	sign2 = 0x8000 & val;
	SET_CFLG(sign != 0);
	COPY_CARRY();
	SET_VFLG(GET_VFLG() | (sign2 != sign));
	put_word_000(dataa, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dataa + 0, 0x1, val, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (3/1) */
/* 4 4,0   */

/* ASLW.W (xxx).W */
uae_u32 REGPARAM2 op_e1f8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 73;
	CurrentInstrCycles = 16; 
	uaecptr dataa;
	dataa = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dataa & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, dataa, 1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 data = get_word_000(dataa);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dataa + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 val = (uae_u16)data;
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();
		SET_CFLG(val & 0x8000);
		SET_ZFLG(!(val & 0x7fff));
		SET_NFLG(val & 0x4000);
		SET_XFLG(GET_CFLG());
		SET_VFLG((val & 0x8000) != ((val << 1) & 0x8000));
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	uae_u32 sign = 0x8000 & val;
	uae_u32 sign2;
	val <<= 1;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	sign2 = 0x8000 & val;
	SET_CFLG(sign != 0);
	COPY_CARRY();
	SET_VFLG(GET_VFLG() | (sign2 != sign));
	put_word_000(dataa, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dataa + 0, 0x1, val, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 4 0,0   */

/* ASLW.W (xxx).L */
uae_u32 REGPARAM2 op_e1f9_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 73;
	CurrentInstrCycles = 20; 
	uaecptr dataa;
	dataa = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	dataa |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dataa & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, dataa, 1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 data = get_word_000(dataa);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dataa + 0, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 val = (uae_u16)data;
	regs.ir = regs.irc;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();
		SET_CFLG(val & 0x8000);
		SET_ZFLG(!(val & 0x7fff));
		SET_NFLG(val & 0x4000);
		SET_XFLG(GET_CFLG());
		SET_VFLG((val & 0x8000) != ((val << 1) & 0x8000));
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	uae_u32 sign = 0x8000 & val;
	uae_u32 sign2;
	val <<= 1;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	sign2 = 0x8000 & val;
	SET_CFLG(sign != 0);
	COPY_CARRY();
	SET_VFLG(GET_VFLG() | (sign2 != sign));
	put_word_000(dataa, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dataa + 0, 0x1, val, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (4/1) */
/* 6 0,0   */

/* LSRW.W (An) */
uae_u32 REGPARAM2 op_e2d0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 74;
	CurrentInstrCycles = 8;  
	int loop_mode = regs.loop_mode;
	uaecptr dataa;
	dataa = m68k_areg(regs, srcreg);
	if (dataa & 1) {
		m68k_incpci(2);
		exception3_read_access2(opcode, dataa, 1, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 data = get_word_000(dataa);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dataa + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 val = (uae_u16)data;
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_000_prefetch(4);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			int pcoffset = 0;
			CLEAR_CZNV();
			SET_CFLG(val & 1);
			SET_ZFLG(!(val & 0xfffe));
			SET_NFLG(0);
			SET_XFLG(GET_CFLG());
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return 4 * CYCLE_UNIT / 2 + count_cycles;
		}
		opcode = regs.ir;
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	uae_u32 carry = val & 1;
	val >>= 1;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	SET_CFLG(carry);
	COPY_CARRY();
	if(loop_mode & 0xfffe) {
		count_cycles += (loop_mode & 0xfffe) * CYCLE_UNIT / 2;
		loop_mode = 1;
	}
	put_word_000(dataa, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dataa + 0, 0x1, val, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (loop_mode) {
		count_cycles += 2 * CYCLE_UNIT / 2;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8+ (1/1) */
/* 2 0,0   */

/* LSRW.W (An)+ */
uae_u32 REGPARAM2 op_e2d8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 74;
	CurrentInstrCycles = 8;  
	int loop_mode = regs.loop_mode;
	uaecptr dataa;
	dataa = m68k_areg(regs, srcreg);
	if (dataa & 1) {
		m68k_areg(regs, srcreg) += 2 + 0;
		m68k_incpci(2);
		exception3_read_access2(opcode, dataa, 1, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 data = get_word_000(dataa);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) += 2 + 0;
		exception2_read(opcode, dataa + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) += 2;
	uae_u32 val = (uae_u16)data;
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_000_prefetch(4);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			int pcoffset = 0;
			CLEAR_CZNV();
			SET_CFLG(val & 1);
			SET_ZFLG(!(val & 0xfffe));
			SET_NFLG(0);
			SET_XFLG(GET_CFLG());
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return 4 * CYCLE_UNIT / 2 + count_cycles;
		}
		opcode = regs.ir;
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	uae_u32 carry = val & 1;
	val >>= 1;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	SET_CFLG(carry);
	COPY_CARRY();
	if(loop_mode & 0xfffe) {
		count_cycles += (loop_mode & 0xfffe) * CYCLE_UNIT / 2;
		loop_mode = 1;
	}
	put_word_000(dataa, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dataa + 0, 0x1, val, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (loop_mode) {
		count_cycles += 2 * CYCLE_UNIT / 2;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8+ (1/1) */
/* 2 0,0   */

/* LSRW.W -(An) */
uae_u32 REGPARAM2 op_e2e0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 74;
	CurrentInstrCycles = 10; 
	int loop_mode = regs.loop_mode;
	uaecptr dataa;
	dataa = m68k_areg(regs, srcreg) - 2;
	if (dataa & 1) {
		m68k_areg(regs, srcreg) = dataa;
		m68k_incpci(2);
		exception3_read_access2(opcode, dataa, 1, 1);
		return 2 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 data = get_word_000(dataa);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = dataa;
		exception2_read(opcode, dataa + 0, 0x1, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) = dataa;
	uae_u32 val = (uae_u16)data;
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_000_prefetch(4);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			int pcoffset = 0;
			CLEAR_CZNV();
			SET_CFLG(val & 1);
			SET_ZFLG(!(val & 0xfffe));
			SET_NFLG(0);
			SET_XFLG(GET_CFLG());
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return 6 * CYCLE_UNIT / 2 + count_cycles;
		}
		opcode = regs.ir;
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	uae_u32 carry = val & 1;
	val >>= 1;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	SET_CFLG(carry);
	COPY_CARRY();
	if(loop_mode & 0xfffe) {
		count_cycles += (loop_mode & 0xfffe) * CYCLE_UNIT / 2;
		loop_mode = 1;
	}
	put_word_000(dataa, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dataa + 0, 0x1, val, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (loop_mode) {
		count_cycles += 2 * CYCLE_UNIT / 2;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return 10 * CYCLE_UNIT / 2 + count_cycles;
}
/* 10+ (1/1) */
/* 2 0,0   */

/* LSRW.W (d16,An) */
uae_u32 REGPARAM2 op_e2e8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 74;
	CurrentInstrCycles = 16; 
	uaecptr dataa;
	dataa = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dataa & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dataa, 1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 data = get_word_000(dataa);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dataa + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 val = (uae_u16)data;
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();
		SET_CFLG(val & 1);
		SET_ZFLG(!(val & 0xfffe));
		SET_NFLG(0);
		SET_XFLG(GET_CFLG());
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	uae_u32 carry = val & 1;
	val >>= 1;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	SET_CFLG(carry);
	COPY_CARRY();
	put_word_000(dataa, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dataa + 0, 0x1, val, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 4 0,0   */

/* LSRW.W (d8,An,Xn) */
uae_u32 REGPARAM2 op_e2f0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 74;
	CurrentInstrCycles = 18; 
	uaecptr dataa;
	BusCyclePenalty += 2;
	dataa = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dataa & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dataa, 1, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 data = get_word_000(dataa);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dataa + 0, 0x1, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 val = (uae_u16)data;
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();
		SET_CFLG(val & 1);
		SET_ZFLG(!(val & 0xfffe));
		SET_NFLG(0);
		SET_XFLG(GET_CFLG());
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	uae_u32 carry = val & 1;
	val >>= 1;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	SET_CFLG(carry);
	COPY_CARRY();
	put_word_000(dataa, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dataa + 0, 0x1, val, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (3/1) */
/* 4 4,0   */

/* LSRW.W (xxx).W */
uae_u32 REGPARAM2 op_e2f8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 74;
	CurrentInstrCycles = 16; 
	uaecptr dataa;
	dataa = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dataa & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, dataa, 1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 data = get_word_000(dataa);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dataa + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 val = (uae_u16)data;
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();
		SET_CFLG(val & 1);
		SET_ZFLG(!(val & 0xfffe));
		SET_NFLG(0);
		SET_XFLG(GET_CFLG());
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	uae_u32 carry = val & 1;
	val >>= 1;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	SET_CFLG(carry);
	COPY_CARRY();
	put_word_000(dataa, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dataa + 0, 0x1, val, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 4 0,0   */

/* LSRW.W (xxx).L */
uae_u32 REGPARAM2 op_e2f9_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 74;
	CurrentInstrCycles = 20; 
	uaecptr dataa;
	dataa = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	dataa |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dataa & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, dataa, 1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 data = get_word_000(dataa);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dataa + 0, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 val = (uae_u16)data;
	regs.ir = regs.irc;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();
		SET_CFLG(val & 1);
		SET_ZFLG(!(val & 0xfffe));
		SET_NFLG(0);
		SET_XFLG(GET_CFLG());
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	uae_u32 carry = val & 1;
	val >>= 1;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	SET_CFLG(carry);
	COPY_CARRY();
	put_word_000(dataa, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dataa + 0, 0x1, val, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (4/1) */
/* 6 0,0   */

/* LSLW.W (An) */
uae_u32 REGPARAM2 op_e3d0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 75;
	CurrentInstrCycles = 8;  
	int loop_mode = regs.loop_mode;
	uaecptr dataa;
	dataa = m68k_areg(regs, srcreg);
	if (dataa & 1) {
		m68k_incpci(2);
		exception3_read_access2(opcode, dataa, 1, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 data = get_word_000(dataa);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dataa + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u16 val = data;
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_000_prefetch(4);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			int pcoffset = 0;
			CLEAR_CZNV();
			SET_CFLG(val & 0x8000);
			SET_ZFLG(!(val & 0x7fff));
			SET_NFLG(val & 0x4000);
			SET_XFLG(GET_CFLG());
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return 4 * CYCLE_UNIT / 2 + count_cycles;
		}
		opcode = regs.ir;
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	uae_u32 carry = val & 0x8000;
	val <<= 1;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	SET_CFLG(carry >> 15);
	COPY_CARRY();
	if(loop_mode & 0xfffe) {
		count_cycles += (loop_mode & 0xfffe) * CYCLE_UNIT / 2;
		loop_mode = 1;
	}
	put_word_000(dataa, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dataa + 0, 0x1, val, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (loop_mode) {
		count_cycles += 2 * CYCLE_UNIT / 2;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8+ (1/1) */
/* 2 0,0   */

/* LSLW.W (An)+ */
uae_u32 REGPARAM2 op_e3d8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 75;
	CurrentInstrCycles = 8;  
	int loop_mode = regs.loop_mode;
	uaecptr dataa;
	dataa = m68k_areg(regs, srcreg);
	if (dataa & 1) {
		m68k_areg(regs, srcreg) += 2 + 0;
		m68k_incpci(2);
		exception3_read_access2(opcode, dataa, 1, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 data = get_word_000(dataa);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) += 2 + 0;
		exception2_read(opcode, dataa + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) += 2;
	uae_u16 val = data;
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_000_prefetch(4);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			int pcoffset = 0;
			CLEAR_CZNV();
			SET_CFLG(val & 0x8000);
			SET_ZFLG(!(val & 0x7fff));
			SET_NFLG(val & 0x4000);
			SET_XFLG(GET_CFLG());
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return 4 * CYCLE_UNIT / 2 + count_cycles;
		}
		opcode = regs.ir;
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	uae_u32 carry = val & 0x8000;
	val <<= 1;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	SET_CFLG(carry >> 15);
	COPY_CARRY();
	if(loop_mode & 0xfffe) {
		count_cycles += (loop_mode & 0xfffe) * CYCLE_UNIT / 2;
		loop_mode = 1;
	}
	put_word_000(dataa, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dataa + 0, 0x1, val, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (loop_mode) {
		count_cycles += 2 * CYCLE_UNIT / 2;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8+ (1/1) */
/* 2 0,0   */

/* LSLW.W -(An) */
uae_u32 REGPARAM2 op_e3e0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 75;
	CurrentInstrCycles = 10; 
	int loop_mode = regs.loop_mode;
	uaecptr dataa;
	dataa = m68k_areg(regs, srcreg) - 2;
	if (dataa & 1) {
		m68k_areg(regs, srcreg) = dataa;
		m68k_incpci(2);
		exception3_read_access2(opcode, dataa, 1, 1);
		return 2 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 data = get_word_000(dataa);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = dataa;
		exception2_read(opcode, dataa + 0, 0x1, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) = dataa;
	uae_u16 val = data;
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_000_prefetch(4);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			int pcoffset = 0;
			CLEAR_CZNV();
			SET_CFLG(val & 0x8000);
			SET_ZFLG(!(val & 0x7fff));
			SET_NFLG(val & 0x4000);
			SET_XFLG(GET_CFLG());
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return 6 * CYCLE_UNIT / 2 + count_cycles;
		}
		opcode = regs.ir;
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	uae_u32 carry = val & 0x8000;
	val <<= 1;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	SET_CFLG(carry >> 15);
	COPY_CARRY();
	if(loop_mode & 0xfffe) {
		count_cycles += (loop_mode & 0xfffe) * CYCLE_UNIT / 2;
		loop_mode = 1;
	}
	put_word_000(dataa, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dataa + 0, 0x1, val, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (loop_mode) {
		count_cycles += 2 * CYCLE_UNIT / 2;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return 10 * CYCLE_UNIT / 2 + count_cycles;
}
/* 10+ (1/1) */
/* 2 0,0   */

/* LSLW.W (d16,An) */
uae_u32 REGPARAM2 op_e3e8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 75;
	CurrentInstrCycles = 16; 
	uaecptr dataa;
	dataa = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dataa & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dataa, 1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 data = get_word_000(dataa);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dataa + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u16 val = data;
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();
		SET_CFLG(val & 0x8000);
		SET_ZFLG(!(val & 0x7fff));
		SET_NFLG(val & 0x4000);
		SET_XFLG(GET_CFLG());
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	uae_u32 carry = val & 0x8000;
	val <<= 1;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	SET_CFLG(carry >> 15);
	COPY_CARRY();
	put_word_000(dataa, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dataa + 0, 0x1, val, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 4 0,0   */

/* LSLW.W (d8,An,Xn) */
uae_u32 REGPARAM2 op_e3f0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 75;
	CurrentInstrCycles = 18; 
	uaecptr dataa;
	BusCyclePenalty += 2;
	dataa = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dataa & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dataa, 1, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 data = get_word_000(dataa);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dataa + 0, 0x1, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u16 val = data;
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();
		SET_CFLG(val & 0x8000);
		SET_ZFLG(!(val & 0x7fff));
		SET_NFLG(val & 0x4000);
		SET_XFLG(GET_CFLG());
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	uae_u32 carry = val & 0x8000;
	val <<= 1;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	SET_CFLG(carry >> 15);
	COPY_CARRY();
	put_word_000(dataa, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dataa + 0, 0x1, val, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (3/1) */
/* 4 4,0   */

/* LSLW.W (xxx).W */
uae_u32 REGPARAM2 op_e3f8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 75;
	CurrentInstrCycles = 16; 
	uaecptr dataa;
	dataa = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dataa & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, dataa, 1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 data = get_word_000(dataa);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dataa + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u16 val = data;
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();
		SET_CFLG(val & 0x8000);
		SET_ZFLG(!(val & 0x7fff));
		SET_NFLG(val & 0x4000);
		SET_XFLG(GET_CFLG());
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	uae_u32 carry = val & 0x8000;
	val <<= 1;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	SET_CFLG(carry >> 15);
	COPY_CARRY();
	put_word_000(dataa, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dataa + 0, 0x1, val, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 4 0,0   */

/* LSLW.W (xxx).L */
uae_u32 REGPARAM2 op_e3f9_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 75;
	CurrentInstrCycles = 20; 
	uaecptr dataa;
	dataa = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	dataa |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dataa & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, dataa, 1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 data = get_word_000(dataa);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dataa + 0, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u16 val = data;
	regs.ir = regs.irc;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();
		SET_CFLG(val & 0x8000);
		SET_ZFLG(!(val & 0x7fff));
		SET_NFLG(val & 0x4000);
		SET_XFLG(GET_CFLG());
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	uae_u32 carry = val & 0x8000;
	val <<= 1;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	SET_CFLG(carry >> 15);
	COPY_CARRY();
	put_word_000(dataa, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dataa + 0, 0x1, val, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (4/1) */
/* 6 0,0   */

/* ROXRW.W (An) */
uae_u32 REGPARAM2 op_e4d0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 79;
	CurrentInstrCycles = 8;  
	int loop_mode = regs.loop_mode;
	uaecptr dataa;
	dataa = m68k_areg(regs, srcreg);
	if (dataa & 1) {
		m68k_incpci(2);
		exception3_read_access2(opcode, dataa, 1, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 data = get_word_000(dataa);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dataa + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u16 val = data;
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_000_prefetch(4);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			int pcoffset = 0;
			CLEAR_CZNV();SET_CFLG(val & 1);
			SET_ZFLG(!((val &0x7ffe) | GET_XFLG()))
			;SET_NFLG(GET_XFLG())
			;SET_XFLG(GET_CFLG());
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return 4 * CYCLE_UNIT / 2 + count_cycles;
		}
		opcode = regs.ir;
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	uae_u32 carry = val & 1;
	val >>= 1;
	if (GET_XFLG()) val |= 0x8000;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	SET_CFLG(carry);
	COPY_CARRY();
	if(loop_mode & 0xfffe) {
		count_cycles += (loop_mode & 0xfffe) * CYCLE_UNIT / 2;
		loop_mode = 1;
	}
	put_word_000(dataa, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dataa + 0, 0x1, val, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (loop_mode) {
		count_cycles += 2 * CYCLE_UNIT / 2;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8+ (1/1) */
/* 2 0,0   */

/* ROXRW.W (An)+ */
uae_u32 REGPARAM2 op_e4d8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 79;
	CurrentInstrCycles = 8;  
	int loop_mode = regs.loop_mode;
	uaecptr dataa;
	dataa = m68k_areg(regs, srcreg);
	if (dataa & 1) {
		m68k_areg(regs, srcreg) += 2 + 0;
		m68k_incpci(2);
		exception3_read_access2(opcode, dataa, 1, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 data = get_word_000(dataa);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) += 2 + 0;
		exception2_read(opcode, dataa + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) += 2;
	uae_u16 val = data;
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_000_prefetch(4);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			int pcoffset = 0;
			CLEAR_CZNV();SET_CFLG(val & 1);
			SET_ZFLG(!((val &0x7ffe) | GET_XFLG()))
			;SET_NFLG(GET_XFLG())
			;SET_XFLG(GET_CFLG());
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return 4 * CYCLE_UNIT / 2 + count_cycles;
		}
		opcode = regs.ir;
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	uae_u32 carry = val & 1;
	val >>= 1;
	if (GET_XFLG()) val |= 0x8000;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	SET_CFLG(carry);
	COPY_CARRY();
	if(loop_mode & 0xfffe) {
		count_cycles += (loop_mode & 0xfffe) * CYCLE_UNIT / 2;
		loop_mode = 1;
	}
	put_word_000(dataa, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dataa + 0, 0x1, val, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (loop_mode) {
		count_cycles += 2 * CYCLE_UNIT / 2;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8+ (1/1) */
/* 2 0,0   */

/* ROXRW.W -(An) */
uae_u32 REGPARAM2 op_e4e0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 79;
	CurrentInstrCycles = 10; 
	int loop_mode = regs.loop_mode;
	uaecptr dataa;
	dataa = m68k_areg(regs, srcreg) - 2;
	if (dataa & 1) {
		m68k_areg(regs, srcreg) = dataa;
		m68k_incpci(2);
		exception3_read_access2(opcode, dataa, 1, 1);
		return 2 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 data = get_word_000(dataa);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = dataa;
		exception2_read(opcode, dataa + 0, 0x1, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) = dataa;
	uae_u16 val = data;
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_000_prefetch(4);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			int pcoffset = 0;
			CLEAR_CZNV();SET_CFLG(val & 1);
			SET_ZFLG(!((val &0x7ffe) | GET_XFLG()))
			;SET_NFLG(GET_XFLG())
			;SET_XFLG(GET_CFLG());
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return 6 * CYCLE_UNIT / 2 + count_cycles;
		}
		opcode = regs.ir;
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	uae_u32 carry = val & 1;
	val >>= 1;
	if (GET_XFLG()) val |= 0x8000;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	SET_CFLG(carry);
	COPY_CARRY();
	if(loop_mode & 0xfffe) {
		count_cycles += (loop_mode & 0xfffe) * CYCLE_UNIT / 2;
		loop_mode = 1;
	}
	put_word_000(dataa, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dataa + 0, 0x1, val, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (loop_mode) {
		count_cycles += 2 * CYCLE_UNIT / 2;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return 10 * CYCLE_UNIT / 2 + count_cycles;
}
/* 10+ (1/1) */
/* 2 0,0   */

/* ROXRW.W (d16,An) */
uae_u32 REGPARAM2 op_e4e8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 79;
	CurrentInstrCycles = 16; 
	uaecptr dataa;
	dataa = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dataa & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dataa, 1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 data = get_word_000(dataa);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dataa + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u16 val = data;
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();SET_CFLG(val & 1);
		SET_ZFLG(!((val &0x7ffe) | GET_XFLG()))
		;SET_NFLG(GET_XFLG())
		;SET_XFLG(GET_CFLG());
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	uae_u32 carry = val & 1;
	val >>= 1;
	if (GET_XFLG()) val |= 0x8000;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	SET_CFLG(carry);
	COPY_CARRY();
	put_word_000(dataa, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dataa + 0, 0x1, val, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 4 0,0   */

/* ROXRW.W (d8,An,Xn) */
uae_u32 REGPARAM2 op_e4f0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 79;
	CurrentInstrCycles = 18; 
	uaecptr dataa;
	BusCyclePenalty += 2;
	dataa = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dataa & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dataa, 1, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 data = get_word_000(dataa);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dataa + 0, 0x1, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u16 val = data;
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();SET_CFLG(val & 1);
		SET_ZFLG(!((val &0x7ffe) | GET_XFLG()))
		;SET_NFLG(GET_XFLG())
		;SET_XFLG(GET_CFLG());
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	uae_u32 carry = val & 1;
	val >>= 1;
	if (GET_XFLG()) val |= 0x8000;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	SET_CFLG(carry);
	COPY_CARRY();
	put_word_000(dataa, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dataa + 0, 0x1, val, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (3/1) */
/* 4 4,0   */

/* ROXRW.W (xxx).W */
uae_u32 REGPARAM2 op_e4f8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 79;
	CurrentInstrCycles = 16; 
	uaecptr dataa;
	dataa = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dataa & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, dataa, 1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 data = get_word_000(dataa);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dataa + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u16 val = data;
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();SET_CFLG(val & 1);
		SET_ZFLG(!((val &0x7ffe) | GET_XFLG()))
		;SET_NFLG(GET_XFLG())
		;SET_XFLG(GET_CFLG());
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	uae_u32 carry = val & 1;
	val >>= 1;
	if (GET_XFLG()) val |= 0x8000;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	SET_CFLG(carry);
	COPY_CARRY();
	put_word_000(dataa, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dataa + 0, 0x1, val, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 4 0,0   */

/* ROXRW.W (xxx).L */
uae_u32 REGPARAM2 op_e4f9_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 79;
	CurrentInstrCycles = 20; 
	uaecptr dataa;
	dataa = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	dataa |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dataa & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, dataa, 1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 data = get_word_000(dataa);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dataa + 0, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u16 val = data;
	regs.ir = regs.irc;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();SET_CFLG(val & 1);
		SET_ZFLG(!((val &0x7ffe) | GET_XFLG()))
		;SET_NFLG(GET_XFLG())
		;SET_XFLG(GET_CFLG());
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	uae_u32 carry = val & 1;
	val >>= 1;
	if (GET_XFLG()) val |= 0x8000;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	SET_CFLG(carry);
	COPY_CARRY();
	put_word_000(dataa, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dataa + 0, 0x1, val, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (4/1) */
/* 6 0,0   */

/* ROXLW.W (An) */
uae_u32 REGPARAM2 op_e5d0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 78;
	CurrentInstrCycles = 8;  
	int loop_mode = regs.loop_mode;
	uaecptr dataa;
	dataa = m68k_areg(regs, srcreg);
	if (dataa & 1) {
		m68k_incpci(2);
		exception3_read_access2(opcode, dataa, 1, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 data = get_word_000(dataa);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dataa + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u16 val = data;
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_000_prefetch(4);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			int pcoffset = 0;
			CLEAR_CZNV();
			SET_CFLG(val & 0x8000);
			SET_ZFLG(!((val & 0x7fff) | GET_XFLG()));
			SET_NFLG(val & 0x4000);
			SET_XFLG(GET_CFLG());
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return 4 * CYCLE_UNIT / 2 + count_cycles;
		}
		opcode = regs.ir;
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	uae_u32 carry = val & 0x8000;
	val <<= 1;
	if (GET_XFLG()) val |= 1;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	SET_CFLG(carry >> 15);
	COPY_CARRY();
	if(loop_mode & 0xfffe) {
		count_cycles += (loop_mode & 0xfffe) * CYCLE_UNIT / 2;
		loop_mode = 1;
	}
	put_word_000(dataa, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dataa + 0, 0x1, val, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (loop_mode) {
		count_cycles += 2 * CYCLE_UNIT / 2;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8+ (1/1) */
/* 2 0,0   */

/* ROXLW.W (An)+ */
uae_u32 REGPARAM2 op_e5d8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 78;
	CurrentInstrCycles = 8;  
	int loop_mode = regs.loop_mode;
	uaecptr dataa;
	dataa = m68k_areg(regs, srcreg);
	if (dataa & 1) {
		m68k_areg(regs, srcreg) += 2 + 0;
		m68k_incpci(2);
		exception3_read_access2(opcode, dataa, 1, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 data = get_word_000(dataa);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) += 2 + 0;
		exception2_read(opcode, dataa + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) += 2;
	uae_u16 val = data;
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_000_prefetch(4);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			int pcoffset = 0;
			CLEAR_CZNV();
			SET_CFLG(val & 0x8000);
			SET_ZFLG(!((val & 0x7fff) | GET_XFLG()));
			SET_NFLG(val & 0x4000);
			SET_XFLG(GET_CFLG());
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return 4 * CYCLE_UNIT / 2 + count_cycles;
		}
		opcode = regs.ir;
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	uae_u32 carry = val & 0x8000;
	val <<= 1;
	if (GET_XFLG()) val |= 1;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	SET_CFLG(carry >> 15);
	COPY_CARRY();
	if(loop_mode & 0xfffe) {
		count_cycles += (loop_mode & 0xfffe) * CYCLE_UNIT / 2;
		loop_mode = 1;
	}
	put_word_000(dataa, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dataa + 0, 0x1, val, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (loop_mode) {
		count_cycles += 2 * CYCLE_UNIT / 2;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8+ (1/1) */
/* 2 0,0   */

/* ROXLW.W -(An) */
uae_u32 REGPARAM2 op_e5e0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 78;
	CurrentInstrCycles = 10; 
	int loop_mode = regs.loop_mode;
	uaecptr dataa;
	dataa = m68k_areg(regs, srcreg) - 2;
	if (dataa & 1) {
		m68k_areg(regs, srcreg) = dataa;
		m68k_incpci(2);
		exception3_read_access2(opcode, dataa, 1, 1);
		return 2 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 data = get_word_000(dataa);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = dataa;
		exception2_read(opcode, dataa + 0, 0x1, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) = dataa;
	uae_u16 val = data;
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_000_prefetch(4);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			int pcoffset = 0;
			CLEAR_CZNV();
			SET_CFLG(val & 0x8000);
			SET_ZFLG(!((val & 0x7fff) | GET_XFLG()));
			SET_NFLG(val & 0x4000);
			SET_XFLG(GET_CFLG());
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return 6 * CYCLE_UNIT / 2 + count_cycles;
		}
		opcode = regs.ir;
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	uae_u32 carry = val & 0x8000;
	val <<= 1;
	if (GET_XFLG()) val |= 1;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	SET_CFLG(carry >> 15);
	COPY_CARRY();
	if(loop_mode & 0xfffe) {
		count_cycles += (loop_mode & 0xfffe) * CYCLE_UNIT / 2;
		loop_mode = 1;
	}
	put_word_000(dataa, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dataa + 0, 0x1, val, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (loop_mode) {
		count_cycles += 2 * CYCLE_UNIT / 2;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return 10 * CYCLE_UNIT / 2 + count_cycles;
}
/* 10+ (1/1) */
/* 2 0,0   */

/* ROXLW.W (d16,An) */
uae_u32 REGPARAM2 op_e5e8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 78;
	CurrentInstrCycles = 16; 
	uaecptr dataa;
	dataa = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dataa & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dataa, 1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 data = get_word_000(dataa);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dataa + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u16 val = data;
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();
		SET_CFLG(val & 0x8000);
		SET_ZFLG(!((val & 0x7fff) | GET_XFLG()));
		SET_NFLG(val & 0x4000);
		SET_XFLG(GET_CFLG());
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	uae_u32 carry = val & 0x8000;
	val <<= 1;
	if (GET_XFLG()) val |= 1;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	SET_CFLG(carry >> 15);
	COPY_CARRY();
	put_word_000(dataa, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dataa + 0, 0x1, val, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 4 0,0   */

/* ROXLW.W (d8,An,Xn) */
uae_u32 REGPARAM2 op_e5f0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 78;
	CurrentInstrCycles = 18; 
	uaecptr dataa;
	BusCyclePenalty += 2;
	dataa = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dataa & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dataa, 1, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 data = get_word_000(dataa);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dataa + 0, 0x1, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u16 val = data;
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();
		SET_CFLG(val & 0x8000);
		SET_ZFLG(!((val & 0x7fff) | GET_XFLG()));
		SET_NFLG(val & 0x4000);
		SET_XFLG(GET_CFLG());
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	uae_u32 carry = val & 0x8000;
	val <<= 1;
	if (GET_XFLG()) val |= 1;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	SET_CFLG(carry >> 15);
	COPY_CARRY();
	put_word_000(dataa, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dataa + 0, 0x1, val, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (3/1) */
/* 4 4,0   */

/* ROXLW.W (xxx).W */
uae_u32 REGPARAM2 op_e5f8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 78;
	CurrentInstrCycles = 16; 
	uaecptr dataa;
	dataa = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dataa & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, dataa, 1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 data = get_word_000(dataa);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dataa + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u16 val = data;
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();
		SET_CFLG(val & 0x8000);
		SET_ZFLG(!((val & 0x7fff) | GET_XFLG()));
		SET_NFLG(val & 0x4000);
		SET_XFLG(GET_CFLG());
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	uae_u32 carry = val & 0x8000;
	val <<= 1;
	if (GET_XFLG()) val |= 1;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	SET_CFLG(carry >> 15);
	COPY_CARRY();
	put_word_000(dataa, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dataa + 0, 0x1, val, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 4 0,0   */

/* ROXLW.W (xxx).L */
uae_u32 REGPARAM2 op_e5f9_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 78;
	CurrentInstrCycles = 20; 
	uaecptr dataa;
	dataa = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	dataa |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dataa & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, dataa, 1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 data = get_word_000(dataa);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dataa + 0, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u16 val = data;
	regs.ir = regs.irc;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();
		SET_CFLG(val & 0x8000);
		SET_ZFLG(!((val & 0x7fff) | GET_XFLG()));
		SET_NFLG(val & 0x4000);
		SET_XFLG(GET_CFLG());
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	uae_u32 carry = val & 0x8000;
	val <<= 1;
	if (GET_XFLG()) val |= 1;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	SET_CFLG(carry >> 15);
	COPY_CARRY();
	put_word_000(dataa, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dataa + 0, 0x1, val, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (4/1) */
/* 6 0,0   */

/* RORW.W (An) */
uae_u32 REGPARAM2 op_e6d0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 77;
	CurrentInstrCycles = 8;  
	int loop_mode = regs.loop_mode;
	uaecptr dataa;
	dataa = m68k_areg(regs, srcreg);
	if (dataa & 1) {
		m68k_incpci(2);
		exception3_read_access2(opcode, dataa, 1, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 data = get_word_000(dataa);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dataa + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u16 val = data;
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_000_prefetch(4);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			int pcoffset = 0;
			CLEAR_CZNV();
			SET_CFLG(val & 1);
			SET_ZFLG(!val);
			SET_NFLG(val & 0x0001);
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return 4 * CYCLE_UNIT / 2 + count_cycles;
		}
		opcode = regs.ir;
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	uae_u32 carry = val & 1;
	val >>= 1;
	if (carry) val |= 0x8000;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	SET_CFLG(carry);
	if(loop_mode & 0xfffe) {
		count_cycles += (loop_mode & 0xfffe) * CYCLE_UNIT / 2;
		loop_mode = 1;
	}
	put_word_000(dataa, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dataa + 0, 0x1, val, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (loop_mode) {
		count_cycles += 2 * CYCLE_UNIT / 2;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8+ (1/1) */
/* 2 0,0   */

/* RORW.W (An)+ */
uae_u32 REGPARAM2 op_e6d8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 77;
	CurrentInstrCycles = 8;  
	int loop_mode = regs.loop_mode;
	uaecptr dataa;
	dataa = m68k_areg(regs, srcreg);
	if (dataa & 1) {
		m68k_areg(regs, srcreg) += 2 + 0;
		m68k_incpci(2);
		exception3_read_access2(opcode, dataa, 1, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 data = get_word_000(dataa);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) += 2 + 0;
		exception2_read(opcode, dataa + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) += 2;
	uae_u16 val = data;
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_000_prefetch(4);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			int pcoffset = 0;
			CLEAR_CZNV();
			SET_CFLG(val & 1);
			SET_ZFLG(!val);
			SET_NFLG(val & 0x0001);
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return 4 * CYCLE_UNIT / 2 + count_cycles;
		}
		opcode = regs.ir;
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	uae_u32 carry = val & 1;
	val >>= 1;
	if (carry) val |= 0x8000;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	SET_CFLG(carry);
	if(loop_mode & 0xfffe) {
		count_cycles += (loop_mode & 0xfffe) * CYCLE_UNIT / 2;
		loop_mode = 1;
	}
	put_word_000(dataa, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dataa + 0, 0x1, val, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (loop_mode) {
		count_cycles += 2 * CYCLE_UNIT / 2;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8+ (1/1) */
/* 2 0,0   */

/* RORW.W -(An) */
uae_u32 REGPARAM2 op_e6e0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 77;
	CurrentInstrCycles = 10; 
	int loop_mode = regs.loop_mode;
	uaecptr dataa;
	dataa = m68k_areg(regs, srcreg) - 2;
	if (dataa & 1) {
		m68k_areg(regs, srcreg) = dataa;
		m68k_incpci(2);
		exception3_read_access2(opcode, dataa, 1, 1);
		return 2 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 data = get_word_000(dataa);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = dataa;
		exception2_read(opcode, dataa + 0, 0x1, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) = dataa;
	uae_u16 val = data;
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_000_prefetch(4);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			int pcoffset = 0;
			CLEAR_CZNV();
			SET_CFLG(val & 1);
			SET_ZFLG(!val);
			SET_NFLG(val & 0x0001);
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return 6 * CYCLE_UNIT / 2 + count_cycles;
		}
		opcode = regs.ir;
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	uae_u32 carry = val & 1;
	val >>= 1;
	if (carry) val |= 0x8000;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	SET_CFLG(carry);
	if(loop_mode & 0xfffe) {
		count_cycles += (loop_mode & 0xfffe) * CYCLE_UNIT / 2;
		loop_mode = 1;
	}
	put_word_000(dataa, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dataa + 0, 0x1, val, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (loop_mode) {
		count_cycles += 2 * CYCLE_UNIT / 2;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return 10 * CYCLE_UNIT / 2 + count_cycles;
}
/* 10+ (1/1) */
/* 2 0,0   */

/* RORW.W (d16,An) */
uae_u32 REGPARAM2 op_e6e8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 77;
	CurrentInstrCycles = 16; 
	uaecptr dataa;
	dataa = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dataa & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dataa, 1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 data = get_word_000(dataa);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dataa + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u16 val = data;
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();
		SET_CFLG(val & 1);
		SET_ZFLG(!val);
		SET_NFLG(val & 0x0001);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	uae_u32 carry = val & 1;
	val >>= 1;
	if (carry) val |= 0x8000;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	SET_CFLG(carry);
	put_word_000(dataa, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dataa + 0, 0x1, val, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 4 0,0   */

/* RORW.W (d8,An,Xn) */
uae_u32 REGPARAM2 op_e6f0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 77;
	CurrentInstrCycles = 18; 
	uaecptr dataa;
	BusCyclePenalty += 2;
	dataa = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dataa & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dataa, 1, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 data = get_word_000(dataa);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dataa + 0, 0x1, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u16 val = data;
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();
		SET_CFLG(val & 1);
		SET_ZFLG(!val);
		SET_NFLG(val & 0x0001);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	uae_u32 carry = val & 1;
	val >>= 1;
	if (carry) val |= 0x8000;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	SET_CFLG(carry);
	put_word_000(dataa, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dataa + 0, 0x1, val, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (3/1) */
/* 4 4,0   */

/* RORW.W (xxx).W */
uae_u32 REGPARAM2 op_e6f8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 77;
	CurrentInstrCycles = 16; 
	uaecptr dataa;
	dataa = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dataa & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, dataa, 1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 data = get_word_000(dataa);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dataa + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u16 val = data;
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();
		SET_CFLG(val & 1);
		SET_ZFLG(!val);
		SET_NFLG(val & 0x0001);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	uae_u32 carry = val & 1;
	val >>= 1;
	if (carry) val |= 0x8000;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	SET_CFLG(carry);
	put_word_000(dataa, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dataa + 0, 0x1, val, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 4 0,0   */

/* RORW.W (xxx).L */
uae_u32 REGPARAM2 op_e6f9_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 77;
	CurrentInstrCycles = 20; 
	uaecptr dataa;
	dataa = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	dataa |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dataa & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, dataa, 1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 data = get_word_000(dataa);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dataa + 0, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u16 val = data;
	regs.ir = regs.irc;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();
		SET_CFLG(val & 1);
		SET_ZFLG(!val);
		SET_NFLG(val & 0x0001);
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	uae_u32 carry = val & 1;
	val >>= 1;
	if (carry) val |= 0x8000;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	SET_CFLG(carry);
	put_word_000(dataa, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dataa + 0, 0x1, val, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (4/1) */
/* 6 0,0   */

/* ROLW.W (An) */
uae_u32 REGPARAM2 op_e7d0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 76;
	CurrentInstrCycles = 8;  
	int loop_mode = regs.loop_mode;
	uaecptr dataa;
	dataa = m68k_areg(regs, srcreg);
	if (dataa & 1) {
		m68k_incpci(2);
		exception3_read_access2(opcode, dataa, 1, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 data = get_word_000(dataa);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dataa + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u16 val = data;
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_000_prefetch(4);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			int pcoffset = 0;
			CLEAR_CZNV();SET_CFLG(val & 0x8000);
			SET_ZFLG(!val);
			SET_NFLG(val & 0x4000);
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return 4 * CYCLE_UNIT / 2 + count_cycles;
		}
		opcode = regs.ir;
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	uae_u32 carry = val & 0x8000;
	val <<= 1;
	if (carry)  val |= 1;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	SET_CFLG(carry >> 15);
	if(loop_mode & 0xfffe) {
		count_cycles += (loop_mode & 0xfffe) * CYCLE_UNIT / 2;
		loop_mode = 1;
	}
	put_word_000(dataa, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dataa + 0, 0x1, val, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (loop_mode) {
		count_cycles += 2 * CYCLE_UNIT / 2;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8+ (1/1) */
/* 2 0,0   */

/* ROLW.W (An)+ */
uae_u32 REGPARAM2 op_e7d8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 76;
	CurrentInstrCycles = 8;  
	int loop_mode = regs.loop_mode;
	uaecptr dataa;
	dataa = m68k_areg(regs, srcreg);
	if (dataa & 1) {
		m68k_areg(regs, srcreg) += 2 + 0;
		m68k_incpci(2);
		exception3_read_access2(opcode, dataa, 1, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 data = get_word_000(dataa);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) += 2 + 0;
		exception2_read(opcode, dataa + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) += 2;
	uae_u16 val = data;
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_000_prefetch(4);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			int pcoffset = 0;
			CLEAR_CZNV();SET_CFLG(val & 0x8000);
			SET_ZFLG(!val);
			SET_NFLG(val & 0x4000);
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return 4 * CYCLE_UNIT / 2 + count_cycles;
		}
		opcode = regs.ir;
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	uae_u32 carry = val & 0x8000;
	val <<= 1;
	if (carry)  val |= 1;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	SET_CFLG(carry >> 15);
	if(loop_mode & 0xfffe) {
		count_cycles += (loop_mode & 0xfffe) * CYCLE_UNIT / 2;
		loop_mode = 1;
	}
	put_word_000(dataa, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dataa + 0, 0x1, val, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (loop_mode) {
		count_cycles += 2 * CYCLE_UNIT / 2;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8+ (1/1) */
/* 2 0,0   */

/* ROLW.W -(An) */
uae_u32 REGPARAM2 op_e7e0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 76;
	CurrentInstrCycles = 10; 
	int loop_mode = regs.loop_mode;
	uaecptr dataa;
	dataa = m68k_areg(regs, srcreg) - 2;
	if (dataa & 1) {
		m68k_areg(regs, srcreg) = dataa;
		m68k_incpci(2);
		exception3_read_access2(opcode, dataa, 1, 1);
		return 2 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 data = get_word_000(dataa);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = dataa;
		exception2_read(opcode, dataa + 0, 0x1, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) = dataa;
	uae_u16 val = data;
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_000_prefetch(4);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			int pcoffset = 0;
			CLEAR_CZNV();SET_CFLG(val & 0x8000);
			SET_ZFLG(!val);
			SET_NFLG(val & 0x4000);
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return 6 * CYCLE_UNIT / 2 + count_cycles;
		}
		opcode = regs.ir;
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	uae_u32 carry = val & 0x8000;
	val <<= 1;
	if (carry)  val |= 1;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	SET_CFLG(carry >> 15);
	if(loop_mode & 0xfffe) {
		count_cycles += (loop_mode & 0xfffe) * CYCLE_UNIT / 2;
		loop_mode = 1;
	}
	put_word_000(dataa, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dataa + 0, 0x1, val, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (loop_mode) {
		count_cycles += 2 * CYCLE_UNIT / 2;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return 10 * CYCLE_UNIT / 2 + count_cycles;
}
/* 10+ (1/1) */
/* 2 0,0   */

/* ROLW.W (d16,An) */
uae_u32 REGPARAM2 op_e7e8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 76;
	CurrentInstrCycles = 16; 
	uaecptr dataa;
	dataa = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dataa & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dataa, 1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 data = get_word_000(dataa);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dataa + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u16 val = data;
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();SET_CFLG(val & 0x8000);
		SET_ZFLG(!val);
		SET_NFLG(val & 0x4000);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	uae_u32 carry = val & 0x8000;
	val <<= 1;
	if (carry)  val |= 1;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	SET_CFLG(carry >> 15);
	put_word_000(dataa, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dataa + 0, 0x1, val, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 4 0,0   */

/* ROLW.W (d8,An,Xn) */
uae_u32 REGPARAM2 op_e7f0_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 76;
	CurrentInstrCycles = 18; 
	uaecptr dataa;
	BusCyclePenalty += 2;
	dataa = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dataa & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dataa, 1, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 data = get_word_000(dataa);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dataa + 0, 0x1, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u16 val = data;
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();SET_CFLG(val & 0x8000);
		SET_ZFLG(!val);
		SET_NFLG(val & 0x4000);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	uae_u32 carry = val & 0x8000;
	val <<= 1;
	if (carry)  val |= 1;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	SET_CFLG(carry >> 15);
	put_word_000(dataa, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dataa + 0, 0x1, val, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (3/1) */
/* 4 4,0   */

/* ROLW.W (xxx).W */
uae_u32 REGPARAM2 op_e7f8_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 76;
	CurrentInstrCycles = 16; 
	uaecptr dataa;
	dataa = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dataa & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, dataa, 1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 data = get_word_000(dataa);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dataa + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u16 val = data;
	regs.ir = regs.irc;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();SET_CFLG(val & 0x8000);
		SET_ZFLG(!val);
		SET_NFLG(val & 0x4000);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	uae_u32 carry = val & 0x8000;
	val <<= 1;
	if (carry)  val |= 1;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	SET_CFLG(carry >> 15);
	put_word_000(dataa, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dataa + 0, 0x1, val, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 4 0,0   */

/* ROLW.W (xxx).L */
uae_u32 REGPARAM2 op_e7f9_11_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 76;
	CurrentInstrCycles = 20; 
	uaecptr dataa;
	dataa = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	dataa |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dataa & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, dataa, 1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 data = get_word_000(dataa);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dataa + 0, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u16 val = data;
	regs.ir = regs.irc;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();SET_CFLG(val & 0x8000);
		SET_ZFLG(!val);
		SET_NFLG(val & 0x4000);
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	uae_u32 carry = val & 0x8000;
	val <<= 1;
	if (carry)  val |= 1;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	SET_CFLG(carry >> 15);
	put_word_000(dataa, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dataa + 0, 0x1, val, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (4/1) */
/* 6 0,0   */

/* OR.B #<data>.B,Dn */
uae_u32 REGPARAM2 op_0000_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 8;  
	uae_s8 src = (uae_u8)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = m68k_dreg(regs, dstreg);
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8 (2/0) */
/* 4 0,0   */

/* OR.B #<data>.B,(An) */
uae_u32 REGPARAM2 op_0010_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 16; 
	uae_s8 src = (uae_u8)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_byte_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 4 0,0   */

/* OR.B #<data>.B,(An)+ */
uae_u32 REGPARAM2 op_0018_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 16; 
	uae_s8 src = (uae_u8)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_byte_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 4 0,0   */

/* OR.B #<data>.B,-(An) */
uae_u32 REGPARAM2 op_0020_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 18; 
	uae_s8 src = (uae_u8)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		m68k_areg(regs, dstreg) = dsta;
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) = dsta;
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_byte_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (3/1) */
/* 4 0,0   */

/* OR.B #<data>.B,(d16,An) */
uae_u32 REGPARAM2 op_0028_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 20; 
	uae_s8 src = (uae_u8)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_byte_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (4/1) */
/* 6 0,0   */

/* OR.B #<data>.B,(d8,An,Xn) */
uae_u32 REGPARAM2 op_0030_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 22; 
	uae_s8 src = (uae_u8)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	BusCyclePenalty += 2;
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_000_prefetch(6));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_byte_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return 22 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 22 * CYCLE_UNIT / 2 + count_cycles;
}
/* 22 (4/1) */
/* 6 4,0   */

/* OR.B #<data>.B,(xxx).W */
uae_u32 REGPARAM2 op_0038_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 1;
	CurrentInstrCycles = 20; 
	uae_s8 src = (uae_u8)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, 0);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_byte_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (4/1) */
/* 6 0,0   */

/* OR.B #<data>.B,(xxx).L */
uae_u32 REGPARAM2 op_0039_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 1;
	CurrentInstrCycles = 24; 
	uae_s8 src = (uae_u8)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = get_word_000_prefetch(6) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	dsta |= get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 8, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(10);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 10, pcoffset);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_byte_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(10);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(8);
	return 24 * CYCLE_UNIT / 2 + count_cycles;
}
/* 24 (5/1) */
/* 8 0,0   */

/* ORSR.B #<data>.W */
uae_u32 REGPARAM2 op_003c_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 4;
	CurrentInstrCycles = 20; 
	MakeSR();
	int t1 = regs.t1;
	uae_s16 src = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	src &= 0xFF;
	regs.sr |= src;
	MakeFromSR();
	m68k_incpci(4);
	get_word_000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, 0);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	if(t1) opcode |= 0x10000;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (3/0) */
/* 4 0,0   */

/* OR.W #<data>.W,Dn */
uae_u32 REGPARAM2 op_0040_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 8;  
	uae_s16 src = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8 (2/0) */
/* 4 0,0   */

/* OR.W #<data>.W,(An) */
uae_u32 REGPARAM2 op_0050_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 16; 
	uae_s16 src = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	if (dsta & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, dsta, 1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = get_word_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_word_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 4 0,0   */

/* OR.W #<data>.W,(An)+ */
uae_u32 REGPARAM2 op_0058_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 16; 
	uae_s16 src = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	if (dsta & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, dsta, 1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = get_word_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, dstreg) += 2 + 0;
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) += 2;
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_word_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 4 0,0   */

/* OR.W #<data>.W,-(An) */
uae_u32 REGPARAM2 op_0060_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 18; 
	uae_s16 src = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - 2;
	if (dsta & 1) {
		m68k_incpci(6);
		m68k_areg(regs, dstreg) = dsta;
		exception3_read_access(opcode, dsta, 1, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = get_word_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		m68k_areg(regs, dstreg) = dsta;
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) = dsta;
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_word_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (3/1) */
/* 4 0,0   */

/* OR.W #<data>.W,(d16,An) */
uae_u32 REGPARAM2 op_0068_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 20; 
	uae_s16 src = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, dsta, 1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = get_word_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_word_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (4/1) */
/* 6 0,0   */

/* OR.W #<data>.W,(d8,An,Xn) */
uae_u32 REGPARAM2 op_0070_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 22; 
	uae_s16 src = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	BusCyclePenalty += 2;
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_000_prefetch(6));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, dsta, 1, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = get_word_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_word_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return 22 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 22 * CYCLE_UNIT / 2 + count_cycles;
}
/* 22 (4/1) */
/* 6 4,0   */

/* OR.W #<data>.W,(xxx).W */
uae_u32 REGPARAM2 op_0078_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 1;
	CurrentInstrCycles = 20; 
	uae_s16 src = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, 0);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, dsta, 1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = get_word_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_word_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (4/1) */
/* 6 0,0   */

/* OR.W #<data>.W,(xxx).L */
uae_u32 REGPARAM2 op_0079_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 1;
	CurrentInstrCycles = 24; 
	uae_s16 src = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = get_word_000_prefetch(6) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	dsta |= get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 8, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(8);
		exception3_read_access(opcode, dsta, 1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = get_word_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(10);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 10, pcoffset);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_word_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(10);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(8);
	return 24 * CYCLE_UNIT / 2 + count_cycles;
}
/* 24 (5/1) */
/* 8 0,0   */

/* ORSR.W #<data>.W */
uae_u32 REGPARAM2 op_007c_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 4;
	CurrentInstrCycles = 20; 
	if (!regs.s) {
		Exception(8);
		return 0;
	}
	MakeSR();
	int t1 = regs.t1;
	uae_s16 src = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.sr |= src;
	MakeFromSR();
	m68k_incpci(4);
	get_word_000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, 0);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	if(t1) opcode |= 0x10000;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (3/0) */
/* 4 0,0   */

/* OR.L #<data>.L,Dn */
uae_u32 REGPARAM2 op_0080_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 16; 
	uae_s32 src;
	src = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		dreg_68000_long_replace_low(dstreg, src);
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	m68k_dreg(regs, dstreg) = (src);
	m68k_incpci(6);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/0) */
/* 6 0,0   */

/* OR.L #<data>.L,(An) */
uae_u32 REGPARAM2 op_0090_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 28; 
	uae_s32 src;
	src = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	if (dsta & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, dsta, 2, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = get_word_000(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	dst |= get_word_000(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src >> 16); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return 28 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 28 * CYCLE_UNIT / 2 + count_cycles;
}
/* 28 (5/2) */
/* 6 0,0   */

/* OR.L #<data>.L,(An)+ */
uae_u32 REGPARAM2 op_0098_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 28; 
	uae_s32 src;
	src = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	if (dsta & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, dsta, 2, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = get_word_000(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	dst |= get_word_000(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) += 4;
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src >> 16); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return 28 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 28 * CYCLE_UNIT / 2 + count_cycles;
}
/* 28 (5/2) */
/* 6 0,0   */

/* OR.L #<data>.L,-(An) */
uae_u32 REGPARAM2 op_00a0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 30; 
	uae_s32 src;
	src = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - 4;
	if (dsta & 1) {
		m68k_incpci(6);
		m68k_areg(regs, dstreg) = dsta;
		exception3_read_access(opcode, dsta, 2, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = get_word_000(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		m68k_areg(regs, dstreg) = dsta;
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	dst |= get_word_000(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		m68k_areg(regs, dstreg) = dsta;
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) = dsta;
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 22 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return 26 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src >> 16); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return 30 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 30 * CYCLE_UNIT / 2 + count_cycles;
}
/* 30 (5/2) */
/* 6 0,0   */

/* OR.L #<data>.L,(d16,An) */
uae_u32 REGPARAM2 op_00a8_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 32; 
	uae_s32 src;
	src = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 8, -2);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, dsta, 2, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = get_word_000(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	dst |= get_word_000(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(10);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch_opcode(opcode, 10, pcoffset);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(10);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return 28 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src >> 16); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(10);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return 32 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(8);
	return 32 * CYCLE_UNIT / 2 + count_cycles;
}
/* 32 (6/2) */
/* 8 0,0   */

/* OR.L #<data>.L,(d8,An,Xn) */
uae_u32 REGPARAM2 op_00b0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 34; 
	uae_s32 src;
	src = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	BusCyclePenalty += 2;
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_000_prefetch(8));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 8, -2);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, dsta, 2, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = get_word_000(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	dst |= get_word_000(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return 22 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(10);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch_opcode(opcode, 10, pcoffset);
		return 26 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(10);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return 30 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src >> 16); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(10);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return 34 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(8);
	return 34 * CYCLE_UNIT / 2 + count_cycles;
}
/* 34 (6/2) */
/* 8 4,0   */

/* OR.L #<data>.L,(xxx).W */
uae_u32 REGPARAM2 op_00b8_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 1;
	CurrentInstrCycles = 32; 
	uae_s32 src;
	src = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 8, 0);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(8);
		exception3_read_access(opcode, dsta, 2, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = get_word_000(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	dst |= get_word_000(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(10);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch_opcode(opcode, 10, pcoffset);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(10);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return 28 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src >> 16); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(10);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return 32 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(8);
	return 32 * CYCLE_UNIT / 2 + count_cycles;
}
/* 32 (6/2) */
/* 8 0,0   */

/* OR.L #<data>.L,(xxx).L */
uae_u32 REGPARAM2 op_00b9_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 1;
	CurrentInstrCycles = 36; 
	uae_s32 src;
	src = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = get_word_000_prefetch(8) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 8, -2);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	dsta |= get_word_000_prefetch(10);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 10, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(10);
		exception3_read_access(opcode, dsta, 2, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = get_word_000(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(10);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	dst |= get_word_000(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(10);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(12);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch_opcode(opcode, 12, pcoffset);
		return 28 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(12);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return 32 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src >> 16); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(12);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return 36 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(10);
	return 36 * CYCLE_UNIT / 2 + count_cycles;
}
/* 36 (7/2) */
/* 10 0,0   */

/* BTST.L Dn,Dn */
uae_u32 REGPARAM2 op_0100_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 21;
	CurrentInstrCycles = 6;  
	uae_s32 src = m68k_dreg(regs, srcreg);
	uae_s32 dst = m68k_dreg(regs, dstreg);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	src &= 31;
	SET_ZFLG(1 ^ ((dst >> src) & 1));
	m68k_incpci(2);
	return 6 * CYCLE_UNIT / 2 + count_cycles;
}
/* 6 (1/0) */
/* 2 0,0   */

/* MVPMR.W (d16,An),Dn */
uae_u32 REGPARAM2 op_0108_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 29;
	CurrentInstrCycles = 16; 
	uaecptr mempa = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u16 val  = (get_byte_000(mempa) & 0xff) << 8;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, mempa + 0, 0x0, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	val |= (get_byte_000(mempa + 2) & 0xff);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, mempa + 2, 0x0, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((val) & 0xffff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (4/0) */
/* 4 0,0   */

/* BTST.B Dn,(An) */
uae_u32 REGPARAM2 op_0110_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 21;
	CurrentInstrCycles = 8;  
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	src &= 7;
	SET_ZFLG(1 ^ ((dst >> src) & 1));
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8 (2/0) */
/* 2 0,0   */

/* BTST.B Dn,(An)+ */
uae_u32 REGPARAM2 op_0118_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 21;
	CurrentInstrCycles = 8;  
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
	src &= 7;
	SET_ZFLG(1 ^ ((dst >> src) & 1));
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8 (2/0) */
/* 2 0,0   */

/* BTST.B Dn,-(An) */
uae_u32 REGPARAM2 op_0120_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 21;
	CurrentInstrCycles = 10; 
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, dstreg) = dsta;
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) = dsta;
	src &= 7;
	SET_ZFLG(1 ^ ((dst >> src) & 1));
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 10 * CYCLE_UNIT / 2 + count_cycles;
}
/* 10 (2/0) */
/* 2 0,0   */

/* BTST.B Dn,(d16,An) */
uae_u32 REGPARAM2 op_0128_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 21;
	CurrentInstrCycles = 12; 
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	src &= 7;
	SET_ZFLG(1 ^ ((dst >> src) & 1));
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (3/0) */
/* 4 0,0   */

/* BTST.B Dn,(d8,An,Xn) */
uae_u32 REGPARAM2 op_0130_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 21;
	CurrentInstrCycles = 14; 
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	BusCyclePenalty += 2;
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	src &= 7;
	SET_ZFLG(1 ^ ((dst >> src) & 1));
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 14 * CYCLE_UNIT / 2 + count_cycles;
}
/* 14 (3/0) */
/* 4 4,0   */

/* BTST.B Dn,(xxx).W */
uae_u32 REGPARAM2 op_0138_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	OpcodeFamily = 21;
	CurrentInstrCycles = 12; 
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	src &= 7;
	SET_ZFLG(1 ^ ((dst >> src) & 1));
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (3/0) */
/* 4 0,0   */

/* BTST.B Dn,(xxx).L */
uae_u32 REGPARAM2 op_0139_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	OpcodeFamily = 21;
	CurrentInstrCycles = 16; 
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	dsta |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	src &= 7;
	SET_ZFLG(1 ^ ((dst >> src) & 1));
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (4/0) */
/* 6 0,0   */

/* BTST.B Dn,(d16,PC) */
uae_u32 REGPARAM2 op_013a_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = 2;
	OpcodeFamily = 21;
	CurrentInstrCycles = 12; 
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_getpci() + 2;
	dsta += (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x0, 2);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	src &= 7;
	SET_ZFLG(1 ^ ((dst >> src) & 1));
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (3/0) */
/* 4 0,0   */

/* BTST.B Dn,(d8,PC,Xn) */
uae_u32 REGPARAM2 op_013b_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = 3;
	OpcodeFamily = 21;
	CurrentInstrCycles = 14; 
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	uaecptr tmppc = m68k_getpci() + 2;
	BusCyclePenalty += 2;
	dsta = get_disp_ea_000(tmppc, get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x0, 2);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	src &= 7;
	SET_ZFLG(1 ^ ((dst >> src) & 1));
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 14 * CYCLE_UNIT / 2 + count_cycles;
}
/* 14 (3/0) */
/* 4 4,0   */

/* BTST.B Dn,#<data>.B */
uae_u32 REGPARAM2 op_013c_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	OpcodeFamily = 21;
	CurrentInstrCycles = 10; 
	uae_s8 src = m68k_dreg(regs, srcreg);
	uae_s8 dst = (uae_u8)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	src &= 7;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	SET_ZFLG(1 ^ ((dst >> src) & 1));
	m68k_incpci(4);
	return 10 * CYCLE_UNIT / 2 + count_cycles;
}
/* 10 (2/0) */
/* 4 0,0   */

/* BCHG.L Dn,Dn */
uae_u32 REGPARAM2 op_0140_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 22;
	CurrentInstrCycles = 6;  
	uae_s32 src = m68k_dreg(regs, srcreg);
	uae_s32 dst = m68k_dreg(regs, dstreg);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	src &= 31;
	if (src > 15) {
		count_cycles +=  2 * CYCLE_UNIT / 2;
	}
	dst ^= (1 << src);
	SET_ZFLG(((uae_u32)dst & (1 << src)) >> src);
	m68k_dreg(regs, dstreg) = (dst);
	m68k_incpci(2);
	return 6 * CYCLE_UNIT / 2 + count_cycles;
}
/* 6+ (1/0) */
/* 2 0,0   */

/* MVPMR.L (d16,An),Dn */
uae_u32 REGPARAM2 op_0148_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 29;
	CurrentInstrCycles = 24; 
	uaecptr mempa = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 val  = (get_byte_000(mempa) & 0xff) << 24;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, mempa + 0, 0x0, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	val |= (get_byte_000(mempa + 2) & 0xff) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, mempa + 2, 0x0, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & 0x0000ffff) | val;
	val |= (get_byte_000(mempa + 4) & 0xff) << 8;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, mempa + 4, 0x0, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	val |= (get_byte_000(mempa + 6) & 0xff);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, mempa + 6, 0x0, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_dreg(regs, dstreg) = (val);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 24 * CYCLE_UNIT / 2 + count_cycles;
}
/* 24 (6/0) */
/* 4 0,0   */

/* BCHG.B Dn,(An) */
uae_u32 REGPARAM2 op_0150_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 22;
	CurrentInstrCycles = 12; 
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	src &= 7;
	dst ^= (1 << src);
	SET_ZFLG(((uae_u32)dst & (1 << src)) >> src);
	put_byte_000(dsta, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, dst, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (2/1) */
/* 2 0,0   */

/* BCHG.B Dn,(An)+ */
uae_u32 REGPARAM2 op_0158_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 22;
	CurrentInstrCycles = 12; 
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	src &= 7;
	dst ^= (1 << src);
	SET_ZFLG(((uae_u32)dst & (1 << src)) >> src);
	put_byte_000(dsta, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, dst, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (2/1) */
/* 2 0,0   */

/* BCHG.B Dn,-(An) */
uae_u32 REGPARAM2 op_0160_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 22;
	CurrentInstrCycles = 14; 
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, dstreg) = dsta;
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) = dsta;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	src &= 7;
	dst ^= (1 << src);
	SET_ZFLG(((uae_u32)dst & (1 << src)) >> src);
	put_byte_000(dsta, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, dst, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 14 * CYCLE_UNIT / 2 + count_cycles;
}
/* 14 (2/1) */
/* 2 0,0   */

/* BCHG.B Dn,(d16,An) */
uae_u32 REGPARAM2 op_0168_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 22;
	CurrentInstrCycles = 16; 
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	src &= 7;
	dst ^= (1 << src);
	SET_ZFLG(((uae_u32)dst & (1 << src)) >> src);
	put_byte_000(dsta, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, dst, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 4 0,0   */

/* BCHG.B Dn,(d8,An,Xn) */
uae_u32 REGPARAM2 op_0170_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 22;
	CurrentInstrCycles = 18; 
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	BusCyclePenalty += 2;
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	src &= 7;
	dst ^= (1 << src);
	SET_ZFLG(((uae_u32)dst & (1 << src)) >> src);
	put_byte_000(dsta, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, dst, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (3/1) */
/* 4 4,0   */

/* BCHG.B Dn,(xxx).W */
uae_u32 REGPARAM2 op_0178_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	OpcodeFamily = 22;
	CurrentInstrCycles = 16; 
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	src &= 7;
	dst ^= (1 << src);
	SET_ZFLG(((uae_u32)dst & (1 << src)) >> src);
	put_byte_000(dsta, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, dst, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 4 0,0   */

/* BCHG.B Dn,(xxx).L */
uae_u32 REGPARAM2 op_0179_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	OpcodeFamily = 22;
	CurrentInstrCycles = 20; 
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	dsta |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	src &= 7;
	dst ^= (1 << src);
	SET_ZFLG(((uae_u32)dst & (1 << src)) >> src);
	put_byte_000(dsta, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, dst, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (4/1) */
/* 6 0,0   */

/* BCLR.L Dn,Dn */
uae_u32 REGPARAM2 op_0180_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 23;
	CurrentInstrCycles = 8;  
	uae_s32 src = m68k_dreg(regs, srcreg);
	uae_s32 dst = m68k_dreg(regs, dstreg);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	src &= 31;
	if (src > 15) {
		count_cycles +=  2 * CYCLE_UNIT / 2;
	}
	SET_ZFLG(1 ^ ((dst >> src) & 1));
	dst &= ~(1 << src);
	m68k_dreg(regs, dstreg) = (dst);
	m68k_incpci(2);
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8+ (1/0) */
/* 2 0,0   */

/* MVPRM.W Dn,(d16,An) */
uae_u32 REGPARAM2 op_0188_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 28;
	CurrentInstrCycles = 16; 
	uae_s16 src = m68k_dreg(regs, srcreg);
	uaecptr mempa = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_byte_000(mempa, src >> 8);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_write(opcode, mempa + 0, 0x0, src >> 8, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_byte_000(mempa + 2, src); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_write(opcode, mempa + 2, 0x0, src, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (2/2) */
/* 4 0,0   */

/* BCLR.B Dn,(An) */
uae_u32 REGPARAM2 op_0190_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 23;
	CurrentInstrCycles = 12; 
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	src &= 7;
	SET_ZFLG(1 ^ ((dst >> src) & 1));
	dst &= ~(1 << src);
	put_byte_000(dsta, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, dst, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (2/1) */
/* 2 0,0   */

/* BCLR.B Dn,(An)+ */
uae_u32 REGPARAM2 op_0198_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 23;
	CurrentInstrCycles = 12; 
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	src &= 7;
	SET_ZFLG(1 ^ ((dst >> src) & 1));
	dst &= ~(1 << src);
	put_byte_000(dsta, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, dst, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (2/1) */
/* 2 0,0   */

/* BCLR.B Dn,-(An) */
uae_u32 REGPARAM2 op_01a0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 23;
	CurrentInstrCycles = 14; 
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, dstreg) = dsta;
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) = dsta;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	src &= 7;
	SET_ZFLG(1 ^ ((dst >> src) & 1));
	dst &= ~(1 << src);
	put_byte_000(dsta, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, dst, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 14 * CYCLE_UNIT / 2 + count_cycles;
}
/* 14 (2/1) */
/* 2 0,0   */

/* BCLR.B Dn,(d16,An) */
uae_u32 REGPARAM2 op_01a8_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 23;
	CurrentInstrCycles = 16; 
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	src &= 7;
	SET_ZFLG(1 ^ ((dst >> src) & 1));
	dst &= ~(1 << src);
	put_byte_000(dsta, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, dst, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 4 0,0   */

/* BCLR.B Dn,(d8,An,Xn) */
uae_u32 REGPARAM2 op_01b0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 23;
	CurrentInstrCycles = 18; 
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	BusCyclePenalty += 2;
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	src &= 7;
	SET_ZFLG(1 ^ ((dst >> src) & 1));
	dst &= ~(1 << src);
	put_byte_000(dsta, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, dst, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (3/1) */
/* 4 4,0   */

/* BCLR.B Dn,(xxx).W */
uae_u32 REGPARAM2 op_01b8_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	OpcodeFamily = 23;
	CurrentInstrCycles = 16; 
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	src &= 7;
	SET_ZFLG(1 ^ ((dst >> src) & 1));
	dst &= ~(1 << src);
	put_byte_000(dsta, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, dst, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 4 0,0   */

/* BCLR.B Dn,(xxx).L */
uae_u32 REGPARAM2 op_01b9_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	OpcodeFamily = 23;
	CurrentInstrCycles = 20; 
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	dsta |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	src &= 7;
	SET_ZFLG(1 ^ ((dst >> src) & 1));
	dst &= ~(1 << src);
	put_byte_000(dsta, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, dst, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (4/1) */
/* 6 0,0   */

/* BSET.L Dn,Dn */
uae_u32 REGPARAM2 op_01c0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 24;
	CurrentInstrCycles = 6;  
	uae_s32 src = m68k_dreg(regs, srcreg);
	uae_s32 dst = m68k_dreg(regs, dstreg);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	src &= 31;
	if (src > 15) {
		count_cycles +=  2 * CYCLE_UNIT / 2;
	}
	SET_ZFLG(1 ^ ((dst >> src) & 1));
	dst |= (1 << src);
	m68k_dreg(regs, dstreg) = (dst);
	m68k_incpci(2);
	return 6 * CYCLE_UNIT / 2 + count_cycles;
}
/* 6+ (1/0) */
/* 2 0,0   */

/* MVPRM.L Dn,(d16,An) */
uae_u32 REGPARAM2 op_01c8_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 28;
	CurrentInstrCycles = 24; 
	uae_s32 src = m68k_dreg(regs, srcreg);
	uaecptr mempa = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_byte_000(mempa, src >> 24);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_write(opcode, mempa + 0, 0x0, src >> 24, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_byte_000(mempa + 2, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_write(opcode, mempa + 2, 0x0, src >> 16, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_byte_000(mempa + 4, src >> 8);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_write(opcode, mempa + 4, 0x0, src >> 8, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_byte_000(mempa + 6, src); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_write(opcode, mempa + 6, 0x0, src, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 24 * CYCLE_UNIT / 2 + count_cycles;
}
/* 24 (2/4) */
/* 4 0,0   */

/* BSET.B Dn,(An) */
uae_u32 REGPARAM2 op_01d0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 24;
	CurrentInstrCycles = 12; 
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	src &= 7;
	SET_ZFLG(1 ^ ((dst >> src) & 1));
	dst |= (1 << src);
	put_byte_000(dsta, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, dst, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (2/1) */
/* 2 0,0   */

/* BSET.B Dn,(An)+ */
uae_u32 REGPARAM2 op_01d8_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 24;
	CurrentInstrCycles = 12; 
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	src &= 7;
	SET_ZFLG(1 ^ ((dst >> src) & 1));
	dst |= (1 << src);
	put_byte_000(dsta, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, dst, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (2/1) */
/* 2 0,0   */

/* BSET.B Dn,-(An) */
uae_u32 REGPARAM2 op_01e0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 24;
	CurrentInstrCycles = 14; 
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, dstreg) = dsta;
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) = dsta;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	src &= 7;
	SET_ZFLG(1 ^ ((dst >> src) & 1));
	dst |= (1 << src);
	put_byte_000(dsta, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, dst, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 14 * CYCLE_UNIT / 2 + count_cycles;
}
/* 14 (2/1) */
/* 2 0,0   */

/* BSET.B Dn,(d16,An) */
uae_u32 REGPARAM2 op_01e8_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 24;
	CurrentInstrCycles = 16; 
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	src &= 7;
	SET_ZFLG(1 ^ ((dst >> src) & 1));
	dst |= (1 << src);
	put_byte_000(dsta, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, dst, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 4 0,0   */

/* BSET.B Dn,(d8,An,Xn) */
uae_u32 REGPARAM2 op_01f0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 24;
	CurrentInstrCycles = 18; 
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	BusCyclePenalty += 2;
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	src &= 7;
	SET_ZFLG(1 ^ ((dst >> src) & 1));
	dst |= (1 << src);
	put_byte_000(dsta, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, dst, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (3/1) */
/* 4 4,0   */

/* BSET.B Dn,(xxx).W */
uae_u32 REGPARAM2 op_01f8_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	OpcodeFamily = 24;
	CurrentInstrCycles = 16; 
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	src &= 7;
	SET_ZFLG(1 ^ ((dst >> src) & 1));
	dst |= (1 << src);
	put_byte_000(dsta, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, dst, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 4 0,0   */

/* BSET.B Dn,(xxx).L */
uae_u32 REGPARAM2 op_01f9_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	OpcodeFamily = 24;
	CurrentInstrCycles = 20; 
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	dsta |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	src &= 7;
	SET_ZFLG(1 ^ ((dst >> src) & 1));
	dst |= (1 << src);
	put_byte_000(dsta, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, dst, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (4/1) */
/* 6 0,0   */

/* AND.B #<data>.B,Dn */
uae_u32 REGPARAM2 op_0200_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 8;  
	uae_s8 src = (uae_u8)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = m68k_dreg(regs, dstreg);
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8 (2/0) */
/* 4 0,0   */

/* AND.B #<data>.B,(An) */
uae_u32 REGPARAM2 op_0210_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 16; 
	uae_s8 src = (uae_u8)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_byte_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 4 0,0   */

/* AND.B #<data>.B,(An)+ */
uae_u32 REGPARAM2 op_0218_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 16; 
	uae_s8 src = (uae_u8)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_byte_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 4 0,0   */

/* AND.B #<data>.B,-(An) */
uae_u32 REGPARAM2 op_0220_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 18; 
	uae_s8 src = (uae_u8)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		m68k_areg(regs, dstreg) = dsta;
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) = dsta;
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_byte_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (3/1) */
/* 4 0,0   */

/* AND.B #<data>.B,(d16,An) */
uae_u32 REGPARAM2 op_0228_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 20; 
	uae_s8 src = (uae_u8)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_byte_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (4/1) */
/* 6 0,0   */

/* AND.B #<data>.B,(d8,An,Xn) */
uae_u32 REGPARAM2 op_0230_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 22; 
	uae_s8 src = (uae_u8)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	BusCyclePenalty += 2;
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_000_prefetch(6));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_byte_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return 22 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 22 * CYCLE_UNIT / 2 + count_cycles;
}
/* 22 (4/1) */
/* 6 4,0   */

/* AND.B #<data>.B,(xxx).W */
uae_u32 REGPARAM2 op_0238_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 2;
	CurrentInstrCycles = 20; 
	uae_s8 src = (uae_u8)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, 0);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_byte_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (4/1) */
/* 6 0,0   */

/* AND.B #<data>.B,(xxx).L */
uae_u32 REGPARAM2 op_0239_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 2;
	CurrentInstrCycles = 24; 
	uae_s8 src = (uae_u8)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = get_word_000_prefetch(6) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	dsta |= get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 8, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(10);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 10, pcoffset);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_byte_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(10);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(8);
	return 24 * CYCLE_UNIT / 2 + count_cycles;
}
/* 24 (5/1) */
/* 8 0,0   */

/* ANDSR.B #<data>.W */
uae_u32 REGPARAM2 op_023c_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 5;
	CurrentInstrCycles = 20; 
	MakeSR();
	int t1 = regs.t1;
	uae_s16 src = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	src &= 0xFF;
	src |= 0xff00;
	regs.sr &= src;
	MakeFromSR();
	m68k_incpci(4);
	get_word_000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, 0);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	if(t1) opcode |= 0x10000;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (3/0) */
/* 4 0,0   */

/* AND.W #<data>.W,Dn */
uae_u32 REGPARAM2 op_0240_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 8;  
	uae_s16 src = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8 (2/0) */
/* 4 0,0   */

/* AND.W #<data>.W,(An) */
uae_u32 REGPARAM2 op_0250_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 16; 
	uae_s16 src = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	if (dsta & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, dsta, 1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = get_word_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_word_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 4 0,0   */

/* AND.W #<data>.W,(An)+ */
uae_u32 REGPARAM2 op_0258_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 16; 
	uae_s16 src = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	if (dsta & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, dsta, 1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = get_word_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, dstreg) += 2 + 0;
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) += 2;
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_word_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 4 0,0   */

/* AND.W #<data>.W,-(An) */
uae_u32 REGPARAM2 op_0260_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 18; 
	uae_s16 src = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - 2;
	if (dsta & 1) {
		m68k_incpci(6);
		m68k_areg(regs, dstreg) = dsta;
		exception3_read_access(opcode, dsta, 1, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = get_word_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		m68k_areg(regs, dstreg) = dsta;
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) = dsta;
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_word_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (3/1) */
/* 4 0,0   */

/* AND.W #<data>.W,(d16,An) */
uae_u32 REGPARAM2 op_0268_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 20; 
	uae_s16 src = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, dsta, 1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = get_word_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_word_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (4/1) */
/* 6 0,0   */

/* AND.W #<data>.W,(d8,An,Xn) */
uae_u32 REGPARAM2 op_0270_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 22; 
	uae_s16 src = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	BusCyclePenalty += 2;
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_000_prefetch(6));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, dsta, 1, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = get_word_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_word_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return 22 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 22 * CYCLE_UNIT / 2 + count_cycles;
}
/* 22 (4/1) */
/* 6 4,0   */

/* AND.W #<data>.W,(xxx).W */
uae_u32 REGPARAM2 op_0278_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 2;
	CurrentInstrCycles = 20; 
	uae_s16 src = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, 0);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, dsta, 1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = get_word_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_word_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (4/1) */
/* 6 0,0   */

/* AND.W #<data>.W,(xxx).L */
uae_u32 REGPARAM2 op_0279_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 2;
	CurrentInstrCycles = 24; 
	uae_s16 src = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = get_word_000_prefetch(6) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	dsta |= get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 8, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(8);
		exception3_read_access(opcode, dsta, 1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = get_word_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(10);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 10, pcoffset);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_word_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(10);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(8);
	return 24 * CYCLE_UNIT / 2 + count_cycles;
}
/* 24 (5/1) */
/* 8 0,0   */

/* ANDSR.W #<data>.W */
uae_u32 REGPARAM2 op_027c_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 5;
	CurrentInstrCycles = 20; 
	if (!regs.s) {
		Exception(8);
		return 0;
	}
	MakeSR();
	int t1 = regs.t1;
	uae_s16 src = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.sr &= src;
	MakeFromSR();
	m68k_incpci(4);
	get_word_000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, 0);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	if(t1) opcode |= 0x10000;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (3/0) */
/* 4 0,0   */

/* AND.L #<data>.L,Dn */
uae_u32 REGPARAM2 op_0280_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 16; 
	uae_s32 src;
	src = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		dreg_68000_long_replace_low(dstreg, src);
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	m68k_dreg(regs, dstreg) = (src);
	m68k_incpci(6);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/0) */
/* 6 0,0   */

/* AND.L #<data>.L,(An) */
uae_u32 REGPARAM2 op_0290_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 28; 
	uae_s32 src;
	src = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	if (dsta & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, dsta, 2, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = get_word_000(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	dst |= get_word_000(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src >> 16); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return 28 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 28 * CYCLE_UNIT / 2 + count_cycles;
}
/* 28 (5/2) */
/* 6 0,0   */

/* AND.L #<data>.L,(An)+ */
uae_u32 REGPARAM2 op_0298_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 28; 
	uae_s32 src;
	src = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	if (dsta & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, dsta, 2, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = get_word_000(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	dst |= get_word_000(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) += 4;
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src >> 16); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return 28 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 28 * CYCLE_UNIT / 2 + count_cycles;
}
/* 28 (5/2) */
/* 6 0,0   */

/* AND.L #<data>.L,-(An) */
uae_u32 REGPARAM2 op_02a0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 30; 
	uae_s32 src;
	src = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - 4;
	if (dsta & 1) {
		m68k_incpci(6);
		m68k_areg(regs, dstreg) = dsta;
		exception3_read_access(opcode, dsta, 2, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = get_word_000(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		m68k_areg(regs, dstreg) = dsta;
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	dst |= get_word_000(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		m68k_areg(regs, dstreg) = dsta;
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) = dsta;
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 22 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return 26 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src >> 16); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return 30 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 30 * CYCLE_UNIT / 2 + count_cycles;
}
/* 30 (5/2) */
/* 6 0,0   */

/* AND.L #<data>.L,(d16,An) */
uae_u32 REGPARAM2 op_02a8_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 32; 
	uae_s32 src;
	src = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 8, -2);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, dsta, 2, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = get_word_000(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	dst |= get_word_000(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(10);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch_opcode(opcode, 10, pcoffset);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(10);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return 28 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src >> 16); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(10);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return 32 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(8);
	return 32 * CYCLE_UNIT / 2 + count_cycles;
}
/* 32 (6/2) */
/* 8 0,0   */

/* AND.L #<data>.L,(d8,An,Xn) */
uae_u32 REGPARAM2 op_02b0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 34; 
	uae_s32 src;
	src = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	BusCyclePenalty += 2;
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_000_prefetch(8));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 8, -2);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, dsta, 2, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = get_word_000(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	dst |= get_word_000(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return 22 * CYCLE_UNIT / 2 + count_cycles;
	}
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(10);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch_opcode(opcode, 10, pcoffset);
		return 26 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(10);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return 30 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src >> 16); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(10);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return 34 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(8);
	return 34 * CYCLE_UNIT / 2 + count_cycles;
}
/* 34 (6/2) */
/* 8 4,0   */

/* AND.L #<data>.L,(xxx).W */
uae_u32 REGPARAM2 op_02b8_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 2;
	CurrentInstrCycles = 32; 
	uae_s32 src;
	src = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 8, 0);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(8);
		exception3_read_access(opcode, dsta, 2, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = get_word_000(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	dst |= get_word_000(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(10);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch_opcode(opcode, 10, pcoffset);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(10);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return 28 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src >> 16); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(10);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return 32 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(8);
	return 32 * CYCLE_UNIT / 2 + count_cycles;
}
/* 32 (6/2) */
/* 8 0,0   */

/* AND.L #<data>.L,(xxx).L */
uae_u32 REGPARAM2 op_02b9_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 2;
	CurrentInstrCycles = 36; 
	uae_s32 src;
	src = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = get_word_000_prefetch(8) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 8, -2);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	dsta |= get_word_000_prefetch(10);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 10, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(10);
		exception3_read_access(opcode, dsta, 2, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = get_word_000(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(10);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	dst |= get_word_000(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(10);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(12);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch_opcode(opcode, 12, pcoffset);
		return 28 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(12);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return 32 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src >> 16); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(12);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return 36 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(10);
	return 36 * CYCLE_UNIT / 2 + count_cycles;
}
/* 36 (7/2) */
/* 10 0,0   */

/* SUB.B #<data>.B,Dn */
uae_u32 REGPARAM2 op_0400_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 8;  
	uae_s8 src = (uae_u8)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8 (2/0) */
/* 4 0,0   */

/* SUB.B #<data>.B,(An) */
uae_u32 REGPARAM2 op_0410_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 16; 
	uae_s8 src = (uae_u8)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_byte_000(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, newv, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 4 0,0   */

/* SUB.B #<data>.B,(An)+ */
uae_u32 REGPARAM2 op_0418_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 16; 
	uae_s8 src = (uae_u8)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
	uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_byte_000(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, newv, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 4 0,0   */

/* SUB.B #<data>.B,-(An) */
uae_u32 REGPARAM2 op_0420_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 18; 
	uae_s8 src = (uae_u8)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		m68k_areg(regs, dstreg) = dsta;
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) = dsta;
	uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_byte_000(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, newv, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (3/1) */
/* 4 0,0   */

/* SUB.B #<data>.B,(d16,An) */
uae_u32 REGPARAM2 op_0428_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 20; 
	uae_s8 src = (uae_u8)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_byte_000(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, newv, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (4/1) */
/* 6 0,0   */

/* SUB.B #<data>.B,(d8,An,Xn) */
uae_u32 REGPARAM2 op_0430_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 22; 
	uae_s8 src = (uae_u8)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	BusCyclePenalty += 2;
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_000_prefetch(6));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_byte_000(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, newv, 1);
		return 22 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 22 * CYCLE_UNIT / 2 + count_cycles;
}
/* 22 (4/1) */
/* 6 4,0   */

/* SUB.B #<data>.B,(xxx).W */
uae_u32 REGPARAM2 op_0438_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 7;
	CurrentInstrCycles = 20; 
	uae_s8 src = (uae_u8)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, 0);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_byte_000(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, newv, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (4/1) */
/* 6 0,0   */

/* SUB.B #<data>.B,(xxx).L */
uae_u32 REGPARAM2 op_0439_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 7;
	CurrentInstrCycles = 24; 
	uae_s8 src = (uae_u8)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = get_word_000_prefetch(6) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	dsta |= get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 8, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(10);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 10, pcoffset);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_byte_000(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(10);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, newv, 1);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(8);
	return 24 * CYCLE_UNIT / 2 + count_cycles;
}
/* 24 (5/1) */
/* 8 0,0   */

/* SUB.W #<data>.W,Dn */
uae_u32 REGPARAM2 op_0440_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 8;  
	uae_s16 src = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8 (2/0) */
/* 4 0,0   */

/* SUB.W #<data>.W,(An) */
uae_u32 REGPARAM2 op_0450_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 16; 
	uae_s16 src = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	if (dsta & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, dsta, 1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = get_word_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_word_000(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x1, newv, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 4 0,0   */

/* SUB.W #<data>.W,(An)+ */
uae_u32 REGPARAM2 op_0458_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 16; 
	uae_s16 src = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	if (dsta & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, dsta, 1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = get_word_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, dstreg) += 2 + 0;
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) += 2;
	uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_word_000(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x1, newv, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 4 0,0   */

/* SUB.W #<data>.W,-(An) */
uae_u32 REGPARAM2 op_0460_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 18; 
	uae_s16 src = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - 2;
	if (dsta & 1) {
		m68k_incpci(6);
		m68k_areg(regs, dstreg) = dsta;
		exception3_read_access(opcode, dsta, 1, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = get_word_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		m68k_areg(regs, dstreg) = dsta;
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) = dsta;
	uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_word_000(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x1, newv, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (3/1) */
/* 4 0,0   */

/* SUB.W #<data>.W,(d16,An) */
uae_u32 REGPARAM2 op_0468_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 20; 
	uae_s16 src = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, dsta, 1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = get_word_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_word_000(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x1, newv, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (4/1) */
/* 6 0,0   */

/* SUB.W #<data>.W,(d8,An,Xn) */
uae_u32 REGPARAM2 op_0470_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 22; 
	uae_s16 src = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	BusCyclePenalty += 2;
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_000_prefetch(6));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, dsta, 1, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = get_word_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_word_000(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x1, newv, 1);
		return 22 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 22 * CYCLE_UNIT / 2 + count_cycles;
}
/* 22 (4/1) */
/* 6 4,0   */

/* SUB.W #<data>.W,(xxx).W */
uae_u32 REGPARAM2 op_0478_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 7;
	CurrentInstrCycles = 20; 
	uae_s16 src = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, 0);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, dsta, 1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = get_word_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_word_000(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x1, newv, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (4/1) */
/* 6 0,0   */

/* SUB.W #<data>.W,(xxx).L */
uae_u32 REGPARAM2 op_0479_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 7;
	CurrentInstrCycles = 24; 
	uae_s16 src = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = get_word_000_prefetch(6) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	dsta |= get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 8, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(8);
		exception3_read_access(opcode, dsta, 1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = get_word_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(10);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 10, pcoffset);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_word_000(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(10);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x1, newv, 1);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(8);
	return 24 * CYCLE_UNIT / 2 + count_cycles;
}
/* 24 (5/1) */
/* 8 0,0   */

/* SUB.L #<data>.L,Dn */
uae_u32 REGPARAM2 op_0480_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 16; 
	uae_s32 src;
	src = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		uae_s16 bnewv = (uae_s16)dst - (uae_s16)src;
		int bflgs = ((uae_s16)(src)) < 0;
		int bflgo = ((uae_s16)(dst)) < 0;
		int bflgn = bnewv < 0;
		ccr_68000_long_move_ae_LZN(bnewv);
		SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
		SET_XFLG(GET_CFLG());
		SET_VFLG((bflgs ^ bflgo) & (bflgn ^ bflgo));
		dreg_68000_long_replace_low(dstreg, bnewv);
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	m68k_dreg(regs, dstreg) = (newv);
	m68k_incpci(6);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/0) */
/* 6 0,0   */

/* SUB.L #<data>.L,(An) */
uae_u32 REGPARAM2 op_0490_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 28; 
	uae_s32 src;
	src = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	if (dsta & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, dsta, 2, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = get_word_000(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	dst |= get_word_000(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		uae_s16 bnewv = (uae_s16)dst - (uae_s16)src;
		int bflgs = ((uae_s16)(src)) < 0;
		int bflgo = ((uae_s16)(dst)) < 0;
		int bflgn = bnewv < 0;
		ccr_68000_long_move_ae_LZN(bnewv);
		SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
		SET_XFLG(GET_CFLG());
		SET_VFLG((bflgs ^ bflgo) & (bflgn ^ bflgo));
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta + 2, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 2, 0x1, newv, 1);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, newv >> 16); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 0, 0x1, newv >> 16, 1);
		return 28 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 28 * CYCLE_UNIT / 2 + count_cycles;
}
/* 28 (5/2) */
/* 6 0,0   */

/* SUB.L #<data>.L,(An)+ */
uae_u32 REGPARAM2 op_0498_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 28; 
	uae_s32 src;
	src = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	if (dsta & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, dsta, 2, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = get_word_000(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	dst |= get_word_000(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) += 4;
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		uae_s16 bnewv = (uae_s16)dst - (uae_s16)src;
		int bflgs = ((uae_s16)(src)) < 0;
		int bflgo = ((uae_s16)(dst)) < 0;
		int bflgn = bnewv < 0;
		ccr_68000_long_move_ae_LZN(bnewv);
		SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
		SET_XFLG(GET_CFLG());
		SET_VFLG((bflgs ^ bflgo) & (bflgn ^ bflgo));
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta + 2, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 2, 0x1, newv, 1);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, newv >> 16); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 0, 0x1, newv >> 16, 1);
		return 28 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 28 * CYCLE_UNIT / 2 + count_cycles;
}
/* 28 (5/2) */
/* 6 0,0   */

/* SUB.L #<data>.L,-(An) */
uae_u32 REGPARAM2 op_04a0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 30; 
	uae_s32 src;
	src = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - 4;
	if (dsta & 1) {
		m68k_incpci(6);
		m68k_areg(regs, dstreg) = dsta;
		exception3_read_access(opcode, dsta, 2, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = get_word_000(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		m68k_areg(regs, dstreg) = dsta;
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	dst |= get_word_000(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		m68k_areg(regs, dstreg) = dsta;
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) = dsta;
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		uae_s16 bnewv = (uae_s16)dst - (uae_s16)src;
		int bflgs = ((uae_s16)(src)) < 0;
		int bflgo = ((uae_s16)(dst)) < 0;
		int bflgn = bnewv < 0;
		ccr_68000_long_move_ae_LZN(bnewv);
		SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
		SET_XFLG(GET_CFLG());
		SET_VFLG((bflgs ^ bflgo) & (bflgn ^ bflgo));
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 22 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta + 2, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 2, 0x1, newv, 1);
		return 26 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, newv >> 16); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 0, 0x1, newv >> 16, 1);
		return 30 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 30 * CYCLE_UNIT / 2 + count_cycles;
}
/* 30 (5/2) */
/* 6 0,0   */

/* SUB.L #<data>.L,(d16,An) */
uae_u32 REGPARAM2 op_04a8_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 32; 
	uae_s32 src;
	src = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 8, -2);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, dsta, 2, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = get_word_000(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	dst |= get_word_000(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(10);
	if(hardware_bus_error) {
		int pcoffset = 0;
		uae_s16 bnewv = (uae_s16)dst - (uae_s16)src;
		int bflgs = ((uae_s16)(src)) < 0;
		int bflgo = ((uae_s16)(dst)) < 0;
		int bflgn = bnewv < 0;
		ccr_68000_long_move_ae_LZN(bnewv);
		SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
		SET_XFLG(GET_CFLG());
		SET_VFLG((bflgs ^ bflgo) & (bflgn ^ bflgo));
		exception2_fetch_opcode(opcode, 10, pcoffset);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta + 2, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(10);
		exception2_write(opcode, dsta + 2, 0x1, newv, 1);
		return 28 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, newv >> 16); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(10);
		exception2_write(opcode, dsta + 0, 0x1, newv >> 16, 1);
		return 32 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(8);
	return 32 * CYCLE_UNIT / 2 + count_cycles;
}
/* 32 (6/2) */
/* 8 0,0   */

/* SUB.L #<data>.L,(d8,An,Xn) */
uae_u32 REGPARAM2 op_04b0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 34; 
	uae_s32 src;
	src = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	BusCyclePenalty += 2;
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_000_prefetch(8));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 8, -2);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, dsta, 2, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = get_word_000(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	dst |= get_word_000(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return 22 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(10);
	if(hardware_bus_error) {
		int pcoffset = 0;
		uae_s16 bnewv = (uae_s16)dst - (uae_s16)src;
		int bflgs = ((uae_s16)(src)) < 0;
		int bflgo = ((uae_s16)(dst)) < 0;
		int bflgn = bnewv < 0;
		ccr_68000_long_move_ae_LZN(bnewv);
		SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
		SET_XFLG(GET_CFLG());
		SET_VFLG((bflgs ^ bflgo) & (bflgn ^ bflgo));
		exception2_fetch_opcode(opcode, 10, pcoffset);
		return 26 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta + 2, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(10);
		exception2_write(opcode, dsta + 2, 0x1, newv, 1);
		return 30 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, newv >> 16); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(10);
		exception2_write(opcode, dsta + 0, 0x1, newv >> 16, 1);
		return 34 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(8);
	return 34 * CYCLE_UNIT / 2 + count_cycles;
}
/* 34 (6/2) */
/* 8 4,0   */

/* SUB.L #<data>.L,(xxx).W */
uae_u32 REGPARAM2 op_04b8_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 7;
	CurrentInstrCycles = 32; 
	uae_s32 src;
	src = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 8, 0);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(8);
		exception3_read_access(opcode, dsta, 2, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = get_word_000(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	dst |= get_word_000(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(10);
	if(hardware_bus_error) {
		int pcoffset = 0;
		uae_s16 bnewv = (uae_s16)dst - (uae_s16)src;
		int bflgs = ((uae_s16)(src)) < 0;
		int bflgo = ((uae_s16)(dst)) < 0;
		int bflgn = bnewv < 0;
		ccr_68000_long_move_ae_LZN(bnewv);
		SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
		SET_XFLG(GET_CFLG());
		SET_VFLG((bflgs ^ bflgo) & (bflgn ^ bflgo));
		exception2_fetch_opcode(opcode, 10, pcoffset);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta + 2, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(10);
		exception2_write(opcode, dsta + 2, 0x1, newv, 1);
		return 28 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, newv >> 16); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(10);
		exception2_write(opcode, dsta + 0, 0x1, newv >> 16, 1);
		return 32 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(8);
	return 32 * CYCLE_UNIT / 2 + count_cycles;
}
/* 32 (6/2) */
/* 8 0,0   */

/* SUB.L #<data>.L,(xxx).L */
uae_u32 REGPARAM2 op_04b9_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 7;
	CurrentInstrCycles = 36; 
	uae_s32 src;
	src = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = get_word_000_prefetch(8) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 8, -2);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	dsta |= get_word_000_prefetch(10);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 10, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(10);
		exception3_read_access(opcode, dsta, 2, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = get_word_000(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(10);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	dst |= get_word_000(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(10);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(12);
	if(hardware_bus_error) {
		int pcoffset = 0;
		uae_s16 bnewv = (uae_s16)dst - (uae_s16)src;
		int bflgs = ((uae_s16)(src)) < 0;
		int bflgo = ((uae_s16)(dst)) < 0;
		int bflgn = bnewv < 0;
		ccr_68000_long_move_ae_LZN(bnewv);
		SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
		SET_XFLG(GET_CFLG());
		SET_VFLG((bflgs ^ bflgo) & (bflgn ^ bflgo));
		exception2_fetch_opcode(opcode, 12, pcoffset);
		return 28 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta + 2, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(12);
		exception2_write(opcode, dsta + 2, 0x1, newv, 1);
		return 32 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, newv >> 16); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(12);
		exception2_write(opcode, dsta + 0, 0x1, newv >> 16, 1);
		return 36 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(10);
	return 36 * CYCLE_UNIT / 2 + count_cycles;
}
/* 36 (7/2) */
/* 10 0,0   */

/* ADD.B #<data>.B,Dn */
uae_u32 REGPARAM2 op_0600_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 8;  
	uae_s8 src = (uae_u8)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u8)(~dst)) < ((uae_u8)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8 (2/0) */
/* 4 0,0   */

/* ADD.B #<data>.B,(An) */
uae_u32 REGPARAM2 op_0610_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 16; 
	uae_s8 src = (uae_u8)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u8)(~dst)) < ((uae_u8)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_byte_000(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, newv, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 4 0,0   */

/* ADD.B #<data>.B,(An)+ */
uae_u32 REGPARAM2 op_0618_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 16; 
	uae_s8 src = (uae_u8)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
	uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u8)(~dst)) < ((uae_u8)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_byte_000(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, newv, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 4 0,0   */

/* ADD.B #<data>.B,-(An) */
uae_u32 REGPARAM2 op_0620_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 18; 
	uae_s8 src = (uae_u8)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		m68k_areg(regs, dstreg) = dsta;
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) = dsta;
	uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u8)(~dst)) < ((uae_u8)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_byte_000(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, newv, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (3/1) */
/* 4 0,0   */

/* ADD.B #<data>.B,(d16,An) */
uae_u32 REGPARAM2 op_0628_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 20; 
	uae_s8 src = (uae_u8)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u8)(~dst)) < ((uae_u8)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_byte_000(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, newv, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (4/1) */
/* 6 0,0   */

/* ADD.B #<data>.B,(d8,An,Xn) */
uae_u32 REGPARAM2 op_0630_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 22; 
	uae_s8 src = (uae_u8)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	BusCyclePenalty += 2;
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_000_prefetch(6));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u8)(~dst)) < ((uae_u8)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_byte_000(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, newv, 1);
		return 22 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 22 * CYCLE_UNIT / 2 + count_cycles;
}
/* 22 (4/1) */
/* 6 4,0   */

/* ADD.B #<data>.B,(xxx).W */
uae_u32 REGPARAM2 op_0638_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 11;
	CurrentInstrCycles = 20; 
	uae_s8 src = (uae_u8)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, 0);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u8)(~dst)) < ((uae_u8)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_byte_000(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, newv, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (4/1) */
/* 6 0,0   */

/* ADD.B #<data>.B,(xxx).L */
uae_u32 REGPARAM2 op_0639_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 11;
	CurrentInstrCycles = 24; 
	uae_s8 src = (uae_u8)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = get_word_000_prefetch(6) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	dsta |= get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 8, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u8)(~dst)) < ((uae_u8)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(10);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 10, pcoffset);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_byte_000(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(10);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, newv, 1);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(8);
	return 24 * CYCLE_UNIT / 2 + count_cycles;
}
/* 24 (5/1) */
/* 8 0,0   */

/* ADD.W #<data>.W,Dn */
uae_u32 REGPARAM2 op_0640_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 8;  
	uae_s16 src = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8 (2/0) */
/* 4 0,0   */

/* ADD.W #<data>.W,(An) */
uae_u32 REGPARAM2 op_0650_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 16; 
	uae_s16 src = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	if (dsta & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, dsta, 1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = get_word_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_word_000(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x1, newv, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 4 0,0   */

/* ADD.W #<data>.W,(An)+ */
uae_u32 REGPARAM2 op_0658_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 16; 
	uae_s16 src = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	if (dsta & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, dsta, 1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = get_word_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, dstreg) += 2 + 0;
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) += 2;
	uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_word_000(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x1, newv, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 4 0,0   */

/* ADD.W #<data>.W,-(An) */
uae_u32 REGPARAM2 op_0660_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 18; 
	uae_s16 src = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - 2;
	if (dsta & 1) {
		m68k_incpci(6);
		m68k_areg(regs, dstreg) = dsta;
		exception3_read_access(opcode, dsta, 1, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = get_word_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		m68k_areg(regs, dstreg) = dsta;
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) = dsta;
	uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_word_000(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x1, newv, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (3/1) */
/* 4 0,0   */

/* ADD.W #<data>.W,(d16,An) */
uae_u32 REGPARAM2 op_0668_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 20; 
	uae_s16 src = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, dsta, 1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = get_word_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_word_000(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x1, newv, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (4/1) */
/* 6 0,0   */

/* ADD.W #<data>.W,(d8,An,Xn) */
uae_u32 REGPARAM2 op_0670_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 22; 
	uae_s16 src = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	BusCyclePenalty += 2;
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_000_prefetch(6));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, dsta, 1, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = get_word_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_word_000(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x1, newv, 1);
		return 22 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 22 * CYCLE_UNIT / 2 + count_cycles;
}
/* 22 (4/1) */
/* 6 4,0   */

/* ADD.W #<data>.W,(xxx).W */
uae_u32 REGPARAM2 op_0678_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 11;
	CurrentInstrCycles = 20; 
	uae_s16 src = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, 0);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, dsta, 1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = get_word_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_word_000(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x1, newv, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (4/1) */
/* 6 0,0   */

/* ADD.W #<data>.W,(xxx).L */
uae_u32 REGPARAM2 op_0679_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 11;
	CurrentInstrCycles = 24; 
	uae_s16 src = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = get_word_000_prefetch(6) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	dsta |= get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 8, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(8);
		exception3_read_access(opcode, dsta, 1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = get_word_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(10);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 10, pcoffset);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_word_000(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(10);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x1, newv, 1);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(8);
	return 24 * CYCLE_UNIT / 2 + count_cycles;
}
/* 24 (5/1) */
/* 8 0,0   */

/* ADD.L #<data>.L,Dn */
uae_u32 REGPARAM2 op_0680_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 16; 
	uae_s32 src;
	src = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u32)(~dst)) < ((uae_u32)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		uae_s16 bnewv = (uae_s16)dst + (uae_s16)src;
		int bflgs = ((uae_s16)(src)) < 0;
		int bflgo = ((uae_s16)(dst)) < 0;
		int bflgn = bnewv < 0;
		ccr_68000_long_move_ae_LZN(bnewv);
		SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
		SET_XFLG(GET_CFLG());
		SET_VFLG((bflgs ^ bflgn) & (bflgo ^ bflgn));
		dreg_68000_long_replace_low(dstreg, bnewv);
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	m68k_dreg(regs, dstreg) = (newv);
	m68k_incpci(6);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/0) */
/* 6 0,0   */

/* ADD.L #<data>.L,(An) */
uae_u32 REGPARAM2 op_0690_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 28; 
	uae_s32 src;
	src = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	if (dsta & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, dsta, 2, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = get_word_000(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	dst |= get_word_000(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u32)(~dst)) < ((uae_u32)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		uae_s16 bnewv = (uae_s16)dst + (uae_s16)src;
		int bflgs = ((uae_s16)(src)) < 0;
		int bflgo = ((uae_s16)(dst)) < 0;
		int bflgn = bnewv < 0;
		ccr_68000_long_move_ae_LZN(bnewv);
		SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
		SET_XFLG(GET_CFLG());
		SET_VFLG((bflgs ^ bflgn) & (bflgo ^ bflgn));
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta + 2, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 2, 0x1, newv, 1);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, newv >> 16); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 0, 0x1, newv >> 16, 1);
		return 28 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 28 * CYCLE_UNIT / 2 + count_cycles;
}
/* 28 (5/2) */
/* 6 0,0   */

/* ADD.L #<data>.L,(An)+ */
uae_u32 REGPARAM2 op_0698_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 28; 
	uae_s32 src;
	src = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	if (dsta & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, dsta, 2, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = get_word_000(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	dst |= get_word_000(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) += 4;
	uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u32)(~dst)) < ((uae_u32)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		uae_s16 bnewv = (uae_s16)dst + (uae_s16)src;
		int bflgs = ((uae_s16)(src)) < 0;
		int bflgo = ((uae_s16)(dst)) < 0;
		int bflgn = bnewv < 0;
		ccr_68000_long_move_ae_LZN(bnewv);
		SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
		SET_XFLG(GET_CFLG());
		SET_VFLG((bflgs ^ bflgn) & (bflgo ^ bflgn));
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta + 2, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 2, 0x1, newv, 1);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, newv >> 16); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 0, 0x1, newv >> 16, 1);
		return 28 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 28 * CYCLE_UNIT / 2 + count_cycles;
}
/* 28 (5/2) */
/* 6 0,0   */

/* ADD.L #<data>.L,-(An) */
uae_u32 REGPARAM2 op_06a0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 30; 
	uae_s32 src;
	src = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - 4;
	if (dsta & 1) {
		m68k_incpci(6);
		m68k_areg(regs, dstreg) = dsta;
		exception3_read_access(opcode, dsta, 2, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = get_word_000(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		m68k_areg(regs, dstreg) = dsta;
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	dst |= get_word_000(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		m68k_areg(regs, dstreg) = dsta;
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) = dsta;
	uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u32)(~dst)) < ((uae_u32)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		uae_s16 bnewv = (uae_s16)dst + (uae_s16)src;
		int bflgs = ((uae_s16)(src)) < 0;
		int bflgo = ((uae_s16)(dst)) < 0;
		int bflgn = bnewv < 0;
		ccr_68000_long_move_ae_LZN(bnewv);
		SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
		SET_XFLG(GET_CFLG());
		SET_VFLG((bflgs ^ bflgn) & (bflgo ^ bflgn));
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 22 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta + 2, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 2, 0x1, newv, 1);
		return 26 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, newv >> 16); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 0, 0x1, newv >> 16, 1);
		return 30 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 30 * CYCLE_UNIT / 2 + count_cycles;
}
/* 30 (5/2) */
/* 6 0,0   */

/* ADD.L #<data>.L,(d16,An) */
uae_u32 REGPARAM2 op_06a8_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 32; 
	uae_s32 src;
	src = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 8, -2);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, dsta, 2, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = get_word_000(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	dst |= get_word_000(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u32)(~dst)) < ((uae_u32)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(10);
	if(hardware_bus_error) {
		int pcoffset = 0;
		uae_s16 bnewv = (uae_s16)dst + (uae_s16)src;
		int bflgs = ((uae_s16)(src)) < 0;
		int bflgo = ((uae_s16)(dst)) < 0;
		int bflgn = bnewv < 0;
		ccr_68000_long_move_ae_LZN(bnewv);
		SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
		SET_XFLG(GET_CFLG());
		SET_VFLG((bflgs ^ bflgn) & (bflgo ^ bflgn));
		exception2_fetch_opcode(opcode, 10, pcoffset);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta + 2, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(10);
		exception2_write(opcode, dsta + 2, 0x1, newv, 1);
		return 28 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, newv >> 16); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(10);
		exception2_write(opcode, dsta + 0, 0x1, newv >> 16, 1);
		return 32 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(8);
	return 32 * CYCLE_UNIT / 2 + count_cycles;
}
/* 32 (6/2) */
/* 8 0,0   */

/* ADD.L #<data>.L,(d8,An,Xn) */
uae_u32 REGPARAM2 op_06b0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 34; 
	uae_s32 src;
	src = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	BusCyclePenalty += 2;
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_000_prefetch(8));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 8, -2);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, dsta, 2, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = get_word_000(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	dst |= get_word_000(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return 22 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u32)(~dst)) < ((uae_u32)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(10);
	if(hardware_bus_error) {
		int pcoffset = 0;
		uae_s16 bnewv = (uae_s16)dst + (uae_s16)src;
		int bflgs = ((uae_s16)(src)) < 0;
		int bflgo = ((uae_s16)(dst)) < 0;
		int bflgn = bnewv < 0;
		ccr_68000_long_move_ae_LZN(bnewv);
		SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
		SET_XFLG(GET_CFLG());
		SET_VFLG((bflgs ^ bflgn) & (bflgo ^ bflgn));
		exception2_fetch_opcode(opcode, 10, pcoffset);
		return 26 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta + 2, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(10);
		exception2_write(opcode, dsta + 2, 0x1, newv, 1);
		return 30 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, newv >> 16); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(10);
		exception2_write(opcode, dsta + 0, 0x1, newv >> 16, 1);
		return 34 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(8);
	return 34 * CYCLE_UNIT / 2 + count_cycles;
}
/* 34 (6/2) */
/* 8 4,0   */

/* ADD.L #<data>.L,(xxx).W */
uae_u32 REGPARAM2 op_06b8_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 11;
	CurrentInstrCycles = 32; 
	uae_s32 src;
	src = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 8, 0);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(8);
		exception3_read_access(opcode, dsta, 2, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = get_word_000(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	dst |= get_word_000(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u32)(~dst)) < ((uae_u32)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(10);
	if(hardware_bus_error) {
		int pcoffset = 0;
		uae_s16 bnewv = (uae_s16)dst + (uae_s16)src;
		int bflgs = ((uae_s16)(src)) < 0;
		int bflgo = ((uae_s16)(dst)) < 0;
		int bflgn = bnewv < 0;
		ccr_68000_long_move_ae_LZN(bnewv);
		SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
		SET_XFLG(GET_CFLG());
		SET_VFLG((bflgs ^ bflgn) & (bflgo ^ bflgn));
		exception2_fetch_opcode(opcode, 10, pcoffset);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta + 2, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(10);
		exception2_write(opcode, dsta + 2, 0x1, newv, 1);
		return 28 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, newv >> 16); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(10);
		exception2_write(opcode, dsta + 0, 0x1, newv >> 16, 1);
		return 32 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(8);
	return 32 * CYCLE_UNIT / 2 + count_cycles;
}
/* 32 (6/2) */
/* 8 0,0   */

/* ADD.L #<data>.L,(xxx).L */
uae_u32 REGPARAM2 op_06b9_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 11;
	CurrentInstrCycles = 36; 
	uae_s32 src;
	src = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = get_word_000_prefetch(8) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 8, -2);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	dsta |= get_word_000_prefetch(10);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 10, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(10);
		exception3_read_access(opcode, dsta, 2, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = get_word_000(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(10);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	dst |= get_word_000(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(10);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u32)(~dst)) < ((uae_u32)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(12);
	if(hardware_bus_error) {
		int pcoffset = 0;
		uae_s16 bnewv = (uae_s16)dst + (uae_s16)src;
		int bflgs = ((uae_s16)(src)) < 0;
		int bflgo = ((uae_s16)(dst)) < 0;
		int bflgn = bnewv < 0;
		ccr_68000_long_move_ae_LZN(bnewv);
		SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
		SET_XFLG(GET_CFLG());
		SET_VFLG((bflgs ^ bflgn) & (bflgo ^ bflgn));
		exception2_fetch_opcode(opcode, 12, pcoffset);
		return 28 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta + 2, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(12);
		exception2_write(opcode, dsta + 2, 0x1, newv, 1);
		return 32 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, newv >> 16); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(12);
		exception2_write(opcode, dsta + 0, 0x1, newv >> 16, 1);
		return 36 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(10);
	return 36 * CYCLE_UNIT / 2 + count_cycles;
}
/* 36 (7/2) */
/* 10 0,0   */

/* BTST.L #<data>.W,Dn */
uae_u32 REGPARAM2 op_0800_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 21;
	CurrentInstrCycles = 10; 
	uae_s16 src = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	src &= 31;
	SET_ZFLG(1 ^ ((dst >> src) & 1));
	m68k_incpci(4);
	return 10 * CYCLE_UNIT / 2 + count_cycles;
}
/* 10 (2/0) */
/* 4 0,0   */

/* BTST.B #<data>.W,(An) */
uae_u32 REGPARAM2 op_0810_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 21;
	CurrentInstrCycles = 12; 
	uae_s16 src = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	src &= 7;
	SET_ZFLG(1 ^ ((dst >> src) & 1));
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (3/0) */
/* 4 0,0   */

/* BTST.B #<data>.W,(An)+ */
uae_u32 REGPARAM2 op_0818_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 21;
	CurrentInstrCycles = 12; 
	uae_s16 src = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
	src &= 7;
	SET_ZFLG(1 ^ ((dst >> src) & 1));
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (3/0) */
/* 4 0,0   */

/* BTST.B #<data>.W,-(An) */
uae_u32 REGPARAM2 op_0820_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 21;
	CurrentInstrCycles = 14; 
	uae_s16 src = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		m68k_areg(regs, dstreg) = dsta;
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) = dsta;
	src &= 7;
	SET_ZFLG(1 ^ ((dst >> src) & 1));
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 14 * CYCLE_UNIT / 2 + count_cycles;
}
/* 14 (3/0) */
/* 4 0,0   */

/* BTST.B #<data>.W,(d16,An) */
uae_u32 REGPARAM2 op_0828_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 21;
	CurrentInstrCycles = 16; 
	uae_s16 src = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	src &= 7;
	SET_ZFLG(1 ^ ((dst >> src) & 1));
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (4/0) */
/* 6 0,0   */

/* BTST.B #<data>.W,(d8,An,Xn) */
uae_u32 REGPARAM2 op_0830_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 21;
	CurrentInstrCycles = 18; 
	uae_s16 src = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	BusCyclePenalty += 2;
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_000_prefetch(6));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	src &= 7;
	SET_ZFLG(1 ^ ((dst >> src) & 1));
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (4/0) */
/* 6 4,0   */

/* BTST.B #<data>.W,(xxx).W */
uae_u32 REGPARAM2 op_0838_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 21;
	CurrentInstrCycles = 16; 
	uae_s16 src = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, 0);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	src &= 7;
	SET_ZFLG(1 ^ ((dst >> src) & 1));
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (4/0) */
/* 6 0,0   */

/* BTST.B #<data>.W,(xxx).L */
uae_u32 REGPARAM2 op_0839_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 21;
	CurrentInstrCycles = 20; 
	uae_s16 src = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = get_word_000_prefetch(6) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	dsta |= get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 8, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	src &= 7;
	SET_ZFLG(1 ^ ((dst >> src) & 1));
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(10);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 10, pcoffset);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(8);
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (5/0) */
/* 8 0,0   */

/* BTST.B #<data>.W,(d16,PC) */
uae_u32 REGPARAM2 op_083a_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 dstreg = 2;
	OpcodeFamily = 21;
	CurrentInstrCycles = 16; 
	uae_s16 src = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_getpci() + 4;
	dsta += (uae_s32)(uae_s16)get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x0, 2);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	src &= 7;
	SET_ZFLG(1 ^ ((dst >> src) & 1));
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (4/0) */
/* 6 0,0   */

/* BTST.B #<data>.W,(d8,PC,Xn) */
uae_u32 REGPARAM2 op_083b_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 dstreg = 3;
	OpcodeFamily = 21;
	CurrentInstrCycles = 18; 
	uae_s16 src = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	uaecptr tmppc = m68k_getpci() + 4;
	BusCyclePenalty += 2;
	dsta = get_disp_ea_000(tmppc, get_word_000_prefetch(6));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x0, 2);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	src &= 7;
	SET_ZFLG(1 ^ ((dst >> src) & 1));
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (4/0) */
/* 6 4,0   */

/* BCHG.L #<data>.W,Dn */
uae_u32 REGPARAM2 op_0840_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 22;
	CurrentInstrCycles = 10; 
	uae_s16 src = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	src &= 31;
	if (src > 15) {
		count_cycles +=  2 * CYCLE_UNIT / 2;
	}
	dst ^= (1 << src);
	SET_ZFLG(((uae_u32)dst & (1 << src)) >> src);
	m68k_dreg(regs, dstreg) = (dst);
	m68k_incpci(4);
	return 10 * CYCLE_UNIT / 2 + count_cycles;
}
/* 10+ (2/0) */
/* 4 0,0   */

/* BCHG.B #<data>.W,(An) */
uae_u32 REGPARAM2 op_0850_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 22;
	CurrentInstrCycles = 16; 
	uae_s16 src = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	src &= 7;
	dst ^= (1 << src);
	SET_ZFLG(((uae_u32)dst & (1 << src)) >> src);
	put_byte_000(dsta, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, dst, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 4 0,0   */

/* BCHG.B #<data>.W,(An)+ */
uae_u32 REGPARAM2 op_0858_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 22;
	CurrentInstrCycles = 16; 
	uae_s16 src = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	src &= 7;
	dst ^= (1 << src);
	SET_ZFLG(((uae_u32)dst & (1 << src)) >> src);
	put_byte_000(dsta, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, dst, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 4 0,0   */

/* BCHG.B #<data>.W,-(An) */
uae_u32 REGPARAM2 op_0860_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 22;
	CurrentInstrCycles = 18; 
	uae_s16 src = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		m68k_areg(regs, dstreg) = dsta;
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) = dsta;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	src &= 7;
	dst ^= (1 << src);
	SET_ZFLG(((uae_u32)dst & (1 << src)) >> src);
	put_byte_000(dsta, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, dst, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (3/1) */
/* 4 0,0   */

/* BCHG.B #<data>.W,(d16,An) */
uae_u32 REGPARAM2 op_0868_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 22;
	CurrentInstrCycles = 20; 
	uae_s16 src = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	src &= 7;
	dst ^= (1 << src);
	SET_ZFLG(((uae_u32)dst & (1 << src)) >> src);
	put_byte_000(dsta, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, dst, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (4/1) */
/* 6 0,0   */

/* BCHG.B #<data>.W,(d8,An,Xn) */
uae_u32 REGPARAM2 op_0870_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 22;
	CurrentInstrCycles = 22; 
	uae_s16 src = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	BusCyclePenalty += 2;
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_000_prefetch(6));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	src &= 7;
	dst ^= (1 << src);
	SET_ZFLG(((uae_u32)dst & (1 << src)) >> src);
	put_byte_000(dsta, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, dst, 1);
		return 22 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 22 * CYCLE_UNIT / 2 + count_cycles;
}
/* 22 (4/1) */
/* 6 4,0   */

/* BCHG.B #<data>.W,(xxx).W */
uae_u32 REGPARAM2 op_0878_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 22;
	CurrentInstrCycles = 20; 
	uae_s16 src = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, 0);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	src &= 7;
	dst ^= (1 << src);
	SET_ZFLG(((uae_u32)dst & (1 << src)) >> src);
	put_byte_000(dsta, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, dst, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (4/1) */
/* 6 0,0   */

/* BCHG.B #<data>.W,(xxx).L */
uae_u32 REGPARAM2 op_0879_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 22;
	CurrentInstrCycles = 24; 
	uae_s16 src = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = get_word_000_prefetch(6) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	dsta |= get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 8, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(10);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 10, pcoffset);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	src &= 7;
	dst ^= (1 << src);
	SET_ZFLG(((uae_u32)dst & (1 << src)) >> src);
	put_byte_000(dsta, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(10);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, dst, 1);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(8);
	return 24 * CYCLE_UNIT / 2 + count_cycles;
}
/* 24 (5/1) */
/* 8 0,0   */

/* BCLR.L #<data>.W,Dn */
uae_u32 REGPARAM2 op_0880_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 23;
	CurrentInstrCycles = 12; 
	uae_s16 src = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	src &= 31;
	if (src > 15) {
		count_cycles +=  2 * CYCLE_UNIT / 2;
	}
	SET_ZFLG(1 ^ ((dst >> src) & 1));
	dst &= ~(1 << src);
	m68k_dreg(regs, dstreg) = (dst);
	m68k_incpci(4);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12+ (2/0) */
/* 4 0,0   */

/* BCLR.B #<data>.W,(An) */
uae_u32 REGPARAM2 op_0890_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 23;
	CurrentInstrCycles = 16; 
	uae_s16 src = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	src &= 7;
	SET_ZFLG(1 ^ ((dst >> src) & 1));
	dst &= ~(1 << src);
	put_byte_000(dsta, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, dst, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 4 0,0   */

/* BCLR.B #<data>.W,(An)+ */
uae_u32 REGPARAM2 op_0898_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 23;
	CurrentInstrCycles = 16; 
	uae_s16 src = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	src &= 7;
	SET_ZFLG(1 ^ ((dst >> src) & 1));
	dst &= ~(1 << src);
	put_byte_000(dsta, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, dst, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 4 0,0   */

/* BCLR.B #<data>.W,-(An) */
uae_u32 REGPARAM2 op_08a0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 23;
	CurrentInstrCycles = 18; 
	uae_s16 src = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		m68k_areg(regs, dstreg) = dsta;
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) = dsta;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	src &= 7;
	SET_ZFLG(1 ^ ((dst >> src) & 1));
	dst &= ~(1 << src);
	put_byte_000(dsta, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, dst, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (3/1) */
/* 4 0,0   */

/* BCLR.B #<data>.W,(d16,An) */
uae_u32 REGPARAM2 op_08a8_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 23;
	CurrentInstrCycles = 20; 
	uae_s16 src = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	src &= 7;
	SET_ZFLG(1 ^ ((dst >> src) & 1));
	dst &= ~(1 << src);
	put_byte_000(dsta, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, dst, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (4/1) */
/* 6 0,0   */

/* BCLR.B #<data>.W,(d8,An,Xn) */
uae_u32 REGPARAM2 op_08b0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 23;
	CurrentInstrCycles = 22; 
	uae_s16 src = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	BusCyclePenalty += 2;
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_000_prefetch(6));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	src &= 7;
	SET_ZFLG(1 ^ ((dst >> src) & 1));
	dst &= ~(1 << src);
	put_byte_000(dsta, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, dst, 1);
		return 22 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 22 * CYCLE_UNIT / 2 + count_cycles;
}
/* 22 (4/1) */
/* 6 4,0   */

/* BCLR.B #<data>.W,(xxx).W */
uae_u32 REGPARAM2 op_08b8_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 23;
	CurrentInstrCycles = 20; 
	uae_s16 src = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, 0);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	src &= 7;
	SET_ZFLG(1 ^ ((dst >> src) & 1));
	dst &= ~(1 << src);
	put_byte_000(dsta, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, dst, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (4/1) */
/* 6 0,0   */

/* BCLR.B #<data>.W,(xxx).L */
uae_u32 REGPARAM2 op_08b9_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 23;
	CurrentInstrCycles = 24; 
	uae_s16 src = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = get_word_000_prefetch(6) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	dsta |= get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 8, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(10);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 10, pcoffset);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	src &= 7;
	SET_ZFLG(1 ^ ((dst >> src) & 1));
	dst &= ~(1 << src);
	put_byte_000(dsta, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(10);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, dst, 1);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(8);
	return 24 * CYCLE_UNIT / 2 + count_cycles;
}
/* 24 (5/1) */
/* 8 0,0   */

/* BSET.L #<data>.W,Dn */
uae_u32 REGPARAM2 op_08c0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 24;
	CurrentInstrCycles = 10; 
	uae_s16 src = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	src &= 31;
	if (src > 15) {
		count_cycles +=  2 * CYCLE_UNIT / 2;
	}
	SET_ZFLG(1 ^ ((dst >> src) & 1));
	dst |= (1 << src);
	m68k_dreg(regs, dstreg) = (dst);
	m68k_incpci(4);
	return 10 * CYCLE_UNIT / 2 + count_cycles;
}
/* 10+ (2/0) */
/* 4 0,0   */

/* BSET.B #<data>.W,(An) */
uae_u32 REGPARAM2 op_08d0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 24;
	CurrentInstrCycles = 16; 
	uae_s16 src = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	src &= 7;
	SET_ZFLG(1 ^ ((dst >> src) & 1));
	dst |= (1 << src);
	put_byte_000(dsta, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, dst, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 4 0,0   */

/* BSET.B #<data>.W,(An)+ */
uae_u32 REGPARAM2 op_08d8_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 24;
	CurrentInstrCycles = 16; 
	uae_s16 src = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	src &= 7;
	SET_ZFLG(1 ^ ((dst >> src) & 1));
	dst |= (1 << src);
	put_byte_000(dsta, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, dst, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 4 0,0   */

/* BSET.B #<data>.W,-(An) */
uae_u32 REGPARAM2 op_08e0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 24;
	CurrentInstrCycles = 18; 
	uae_s16 src = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		m68k_areg(regs, dstreg) = dsta;
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) = dsta;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	src &= 7;
	SET_ZFLG(1 ^ ((dst >> src) & 1));
	dst |= (1 << src);
	put_byte_000(dsta, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, dst, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (3/1) */
/* 4 0,0   */

/* BSET.B #<data>.W,(d16,An) */
uae_u32 REGPARAM2 op_08e8_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 24;
	CurrentInstrCycles = 20; 
	uae_s16 src = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	src &= 7;
	SET_ZFLG(1 ^ ((dst >> src) & 1));
	dst |= (1 << src);
	put_byte_000(dsta, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, dst, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (4/1) */
/* 6 0,0   */

/* BSET.B #<data>.W,(d8,An,Xn) */
uae_u32 REGPARAM2 op_08f0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 24;
	CurrentInstrCycles = 22; 
	uae_s16 src = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	BusCyclePenalty += 2;
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_000_prefetch(6));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	src &= 7;
	SET_ZFLG(1 ^ ((dst >> src) & 1));
	dst |= (1 << src);
	put_byte_000(dsta, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, dst, 1);
		return 22 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 22 * CYCLE_UNIT / 2 + count_cycles;
}
/* 22 (4/1) */
/* 6 4,0   */

/* BSET.B #<data>.W,(xxx).W */
uae_u32 REGPARAM2 op_08f8_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 24;
	CurrentInstrCycles = 20; 
	uae_s16 src = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, 0);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	src &= 7;
	SET_ZFLG(1 ^ ((dst >> src) & 1));
	dst |= (1 << src);
	put_byte_000(dsta, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, dst, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (4/1) */
/* 6 0,0   */

/* BSET.B #<data>.W,(xxx).L */
uae_u32 REGPARAM2 op_08f9_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 24;
	CurrentInstrCycles = 24; 
	uae_s16 src = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = get_word_000_prefetch(6) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	dsta |= get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 8, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(10);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 10, pcoffset);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	src &= 7;
	SET_ZFLG(1 ^ ((dst >> src) & 1));
	dst |= (1 << src);
	put_byte_000(dsta, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(10);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, dst, 1);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(8);
	return 24 * CYCLE_UNIT / 2 + count_cycles;
}
/* 24 (5/1) */
/* 8 0,0   */

/* EOR.B #<data>.B,Dn */
uae_u32 REGPARAM2 op_0a00_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 3;
	CurrentInstrCycles = 8;  
	uae_s8 src = (uae_u8)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = m68k_dreg(regs, dstreg);
	src ^= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8 (2/0) */
/* 4 0,0   */

/* EOR.B #<data>.B,(An) */
uae_u32 REGPARAM2 op_0a10_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 3;
	CurrentInstrCycles = 16; 
	uae_s8 src = (uae_u8)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	src ^= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_byte_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 4 0,0   */

/* EOR.B #<data>.B,(An)+ */
uae_u32 REGPARAM2 op_0a18_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 3;
	CurrentInstrCycles = 16; 
	uae_s8 src = (uae_u8)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
	src ^= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_byte_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 4 0,0   */

/* EOR.B #<data>.B,-(An) */
uae_u32 REGPARAM2 op_0a20_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 3;
	CurrentInstrCycles = 18; 
	uae_s8 src = (uae_u8)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		m68k_areg(regs, dstreg) = dsta;
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) = dsta;
	src ^= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_byte_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (3/1) */
/* 4 0,0   */

/* EOR.B #<data>.B,(d16,An) */
uae_u32 REGPARAM2 op_0a28_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 3;
	CurrentInstrCycles = 20; 
	uae_s8 src = (uae_u8)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	src ^= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_byte_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (4/1) */
/* 6 0,0   */

/* EOR.B #<data>.B,(d8,An,Xn) */
uae_u32 REGPARAM2 op_0a30_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 3;
	CurrentInstrCycles = 22; 
	uae_s8 src = (uae_u8)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	BusCyclePenalty += 2;
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_000_prefetch(6));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	src ^= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_byte_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return 22 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 22 * CYCLE_UNIT / 2 + count_cycles;
}
/* 22 (4/1) */
/* 6 4,0   */

/* EOR.B #<data>.B,(xxx).W */
uae_u32 REGPARAM2 op_0a38_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 3;
	CurrentInstrCycles = 20; 
	uae_s8 src = (uae_u8)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, 0);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	src ^= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_byte_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (4/1) */
/* 6 0,0   */

/* EOR.B #<data>.B,(xxx).L */
uae_u32 REGPARAM2 op_0a39_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 3;
	CurrentInstrCycles = 24; 
	uae_s8 src = (uae_u8)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = get_word_000_prefetch(6) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	dsta |= get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 8, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	src ^= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(10);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 10, pcoffset);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_byte_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(10);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(8);
	return 24 * CYCLE_UNIT / 2 + count_cycles;
}
/* 24 (5/1) */
/* 8 0,0   */

/* EORSR.B #<data>.W */
uae_u32 REGPARAM2 op_0a3c_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 6;
	CurrentInstrCycles = 20; 
	MakeSR();
	int t1 = regs.t1;
	uae_s16 src = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	src &= 0xFF;
	regs.sr ^= src;
	MakeFromSR();
	m68k_incpci(4);
	get_word_000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, 0);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	if(t1) opcode |= 0x10000;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (3/0) */
/* 4 0,0   */

/* EOR.W #<data>.W,Dn */
uae_u32 REGPARAM2 op_0a40_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 3;
	CurrentInstrCycles = 8;  
	uae_s16 src = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	src ^= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8 (2/0) */
/* 4 0,0   */

/* EOR.W #<data>.W,(An) */
uae_u32 REGPARAM2 op_0a50_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 3;
	CurrentInstrCycles = 16; 
	uae_s16 src = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	if (dsta & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, dsta, 1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = get_word_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	src ^= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_word_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 4 0,0   */

/* EOR.W #<data>.W,(An)+ */
uae_u32 REGPARAM2 op_0a58_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 3;
	CurrentInstrCycles = 16; 
	uae_s16 src = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	if (dsta & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, dsta, 1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = get_word_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, dstreg) += 2 + 0;
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) += 2;
	src ^= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_word_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 4 0,0   */

/* EOR.W #<data>.W,-(An) */
uae_u32 REGPARAM2 op_0a60_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 3;
	CurrentInstrCycles = 18; 
	uae_s16 src = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - 2;
	if (dsta & 1) {
		m68k_incpci(6);
		m68k_areg(regs, dstreg) = dsta;
		exception3_read_access(opcode, dsta, 1, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = get_word_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		m68k_areg(regs, dstreg) = dsta;
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) = dsta;
	src ^= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_word_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (3/1) */
/* 4 0,0   */

/* EOR.W #<data>.W,(d16,An) */
uae_u32 REGPARAM2 op_0a68_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 3;
	CurrentInstrCycles = 20; 
	uae_s16 src = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, dsta, 1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = get_word_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	src ^= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_word_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (4/1) */
/* 6 0,0   */

/* EOR.W #<data>.W,(d8,An,Xn) */
uae_u32 REGPARAM2 op_0a70_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 3;
	CurrentInstrCycles = 22; 
	uae_s16 src = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	BusCyclePenalty += 2;
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_000_prefetch(6));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, dsta, 1, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = get_word_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	src ^= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_word_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return 22 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 22 * CYCLE_UNIT / 2 + count_cycles;
}
/* 22 (4/1) */
/* 6 4,0   */

/* EOR.W #<data>.W,(xxx).W */
uae_u32 REGPARAM2 op_0a78_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 3;
	CurrentInstrCycles = 20; 
	uae_s16 src = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, 0);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, dsta, 1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = get_word_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	src ^= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_word_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (4/1) */
/* 6 0,0   */

/* EOR.W #<data>.W,(xxx).L */
uae_u32 REGPARAM2 op_0a79_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 3;
	CurrentInstrCycles = 24; 
	uae_s16 src = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = get_word_000_prefetch(6) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	dsta |= get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 8, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(8);
		exception3_read_access(opcode, dsta, 1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = get_word_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	src ^= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(10);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 10, pcoffset);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_word_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(10);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(8);
	return 24 * CYCLE_UNIT / 2 + count_cycles;
}
/* 24 (5/1) */
/* 8 0,0   */

/* EORSR.W #<data>.W */
uae_u32 REGPARAM2 op_0a7c_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 6;
	CurrentInstrCycles = 20; 
	if (!regs.s) {
		Exception(8);
		return 0;
	}
	MakeSR();
	int t1 = regs.t1;
	uae_s16 src = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.sr ^= src;
	MakeFromSR();
	m68k_incpci(4);
	get_word_000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, 0);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	if(t1) opcode |= 0x10000;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (3/0) */
/* 4 0,0   */

/* EOR.L #<data>.L,Dn */
uae_u32 REGPARAM2 op_0a80_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 3;
	CurrentInstrCycles = 16; 
	uae_s32 src;
	src = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	src ^= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		dreg_68000_long_replace_low(dstreg, src);
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	m68k_dreg(regs, dstreg) = (src);
	m68k_incpci(6);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/0) */
/* 6 0,0   */

/* EOR.L #<data>.L,(An) */
uae_u32 REGPARAM2 op_0a90_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 3;
	CurrentInstrCycles = 28; 
	uae_s32 src;
	src = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	if (dsta & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, dsta, 2, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = get_word_000(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	dst |= get_word_000(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	src ^= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src >> 16); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return 28 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 28 * CYCLE_UNIT / 2 + count_cycles;
}
/* 28 (5/2) */
/* 6 0,0   */

/* EOR.L #<data>.L,(An)+ */
uae_u32 REGPARAM2 op_0a98_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 3;
	CurrentInstrCycles = 28; 
	uae_s32 src;
	src = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	if (dsta & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, dsta, 2, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = get_word_000(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	dst |= get_word_000(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) += 4;
	src ^= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src >> 16); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return 28 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 28 * CYCLE_UNIT / 2 + count_cycles;
}
/* 28 (5/2) */
/* 6 0,0   */

/* EOR.L #<data>.L,-(An) */
uae_u32 REGPARAM2 op_0aa0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 3;
	CurrentInstrCycles = 30; 
	uae_s32 src;
	src = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - 4;
	if (dsta & 1) {
		m68k_incpci(6);
		m68k_areg(regs, dstreg) = dsta;
		exception3_read_access(opcode, dsta, 2, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = get_word_000(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		m68k_areg(regs, dstreg) = dsta;
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	dst |= get_word_000(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		m68k_areg(regs, dstreg) = dsta;
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) = dsta;
	src ^= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 22 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return 26 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src >> 16); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return 30 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 30 * CYCLE_UNIT / 2 + count_cycles;
}
/* 30 (5/2) */
/* 6 0,0   */

/* EOR.L #<data>.L,(d16,An) */
uae_u32 REGPARAM2 op_0aa8_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 3;
	CurrentInstrCycles = 32; 
	uae_s32 src;
	src = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 8, -2);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, dsta, 2, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = get_word_000(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	dst |= get_word_000(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	src ^= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(10);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch_opcode(opcode, 10, pcoffset);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(10);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return 28 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src >> 16); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(10);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return 32 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(8);
	return 32 * CYCLE_UNIT / 2 + count_cycles;
}
/* 32 (6/2) */
/* 8 0,0   */

/* EOR.L #<data>.L,(d8,An,Xn) */
uae_u32 REGPARAM2 op_0ab0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 3;
	CurrentInstrCycles = 34; 
	uae_s32 src;
	src = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	BusCyclePenalty += 2;
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_000_prefetch(8));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 8, -2);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, dsta, 2, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = get_word_000(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	dst |= get_word_000(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return 22 * CYCLE_UNIT / 2 + count_cycles;
	}
	src ^= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(10);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch_opcode(opcode, 10, pcoffset);
		return 26 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(10);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return 30 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src >> 16); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(10);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return 34 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(8);
	return 34 * CYCLE_UNIT / 2 + count_cycles;
}
/* 34 (6/2) */
/* 8 4,0   */

/* EOR.L #<data>.L,(xxx).W */
uae_u32 REGPARAM2 op_0ab8_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 3;
	CurrentInstrCycles = 32; 
	uae_s32 src;
	src = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 8, 0);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(8);
		exception3_read_access(opcode, dsta, 2, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = get_word_000(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	dst |= get_word_000(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	src ^= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(10);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch_opcode(opcode, 10, pcoffset);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(10);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return 28 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src >> 16); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(10);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return 32 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(8);
	return 32 * CYCLE_UNIT / 2 + count_cycles;
}
/* 32 (6/2) */
/* 8 0,0   */

/* EOR.L #<data>.L,(xxx).L */
uae_u32 REGPARAM2 op_0ab9_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 3;
	CurrentInstrCycles = 36; 
	uae_s32 src;
	src = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = get_word_000_prefetch(8) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 8, -2);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	dsta |= get_word_000_prefetch(10);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 10, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(10);
		exception3_read_access(opcode, dsta, 2, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = get_word_000(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(10);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	dst |= get_word_000(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(10);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	src ^= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(12);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch_opcode(opcode, 12, pcoffset);
		return 28 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(12);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return 32 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src >> 16); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(12);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return 36 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(10);
	return 36 * CYCLE_UNIT / 2 + count_cycles;
}
/* 36 (7/2) */
/* 10 0,0   */

/* CMP.B #<data>.B,Dn */
uae_u32 REGPARAM2 op_0c00_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 25;
	CurrentInstrCycles = 8;  
	uae_s8 src = (uae_u8)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8 (2/0) */
/* 4 0,0   */

/* CMP.B #<data>.B,(An) */
uae_u32 REGPARAM2 op_0c10_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 25;
	CurrentInstrCycles = 12; 
	uae_s8 src = (uae_u8)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (3/0) */
/* 4 0,0   */

/* CMP.B #<data>.B,(An)+ */
uae_u32 REGPARAM2 op_0c18_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 25;
	CurrentInstrCycles = 12; 
	uae_s8 src = (uae_u8)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
	uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (3/0) */
/* 4 0,0   */

/* CMP.B #<data>.B,-(An) */
uae_u32 REGPARAM2 op_0c20_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 25;
	CurrentInstrCycles = 14; 
	uae_s8 src = (uae_u8)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		m68k_areg(regs, dstreg) = dsta;
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) = dsta;
	uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 14 * CYCLE_UNIT / 2 + count_cycles;
}
/* 14 (3/0) */
/* 4 0,0   */

/* CMP.B #<data>.B,(d16,An) */
uae_u32 REGPARAM2 op_0c28_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 25;
	CurrentInstrCycles = 16; 
	uae_s8 src = (uae_u8)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (4/0) */
/* 6 0,0   */

/* CMP.B #<data>.B,(d8,An,Xn) */
uae_u32 REGPARAM2 op_0c30_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 25;
	CurrentInstrCycles = 18; 
	uae_s8 src = (uae_u8)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	BusCyclePenalty += 2;
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_000_prefetch(6));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (4/0) */
/* 6 4,0   */

/* CMP.B #<data>.B,(xxx).W */
uae_u32 REGPARAM2 op_0c38_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 25;
	CurrentInstrCycles = 16; 
	uae_s8 src = (uae_u8)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, 0);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (4/0) */
/* 6 0,0   */

/* CMP.B #<data>.B,(xxx).L */
uae_u32 REGPARAM2 op_0c39_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 25;
	CurrentInstrCycles = 20; 
	uae_s8 src = (uae_u8)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = get_word_000_prefetch(6) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	dsta |= get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 8, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(10);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 10, pcoffset);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(8);
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (5/0) */
/* 8 0,0   */

/* CMP.W #<data>.W,Dn */
uae_u32 REGPARAM2 op_0c40_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 25;
	CurrentInstrCycles = 8;  
	uae_s16 src = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8 (2/0) */
/* 4 0,0   */

/* CMP.W #<data>.W,(An) */
uae_u32 REGPARAM2 op_0c50_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 25;
	CurrentInstrCycles = 12; 
	uae_s16 src = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	if (dsta & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, dsta, 1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = get_word_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (3/0) */
/* 4 0,0   */

/* CMP.W #<data>.W,(An)+ */
uae_u32 REGPARAM2 op_0c58_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 25;
	CurrentInstrCycles = 12; 
	uae_s16 src = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	if (dsta & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, dsta, 1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = get_word_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, dstreg) += 2 + 0;
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) += 2;
	uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (3/0) */
/* 4 0,0   */

/* CMP.W #<data>.W,-(An) */
uae_u32 REGPARAM2 op_0c60_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 25;
	CurrentInstrCycles = 14; 
	uae_s16 src = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - 2;
	if (dsta & 1) {
		m68k_incpci(6);
		m68k_areg(regs, dstreg) = dsta;
		exception3_read_access(opcode, dsta, 1, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = get_word_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		m68k_areg(regs, dstreg) = dsta;
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) = dsta;
	uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 14 * CYCLE_UNIT / 2 + count_cycles;
}
/* 14 (3/0) */
/* 4 0,0   */

/* CMP.W #<data>.W,(d16,An) */
uae_u32 REGPARAM2 op_0c68_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 25;
	CurrentInstrCycles = 16; 
	uae_s16 src = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, dsta, 1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = get_word_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (4/0) */
/* 6 0,0   */

/* CMP.W #<data>.W,(d8,An,Xn) */
uae_u32 REGPARAM2 op_0c70_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 25;
	CurrentInstrCycles = 18; 
	uae_s16 src = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	BusCyclePenalty += 2;
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_000_prefetch(6));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, dsta, 1, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = get_word_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (4/0) */
/* 6 4,0   */

/* CMP.W #<data>.W,(xxx).W */
uae_u32 REGPARAM2 op_0c78_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 25;
	CurrentInstrCycles = 16; 
	uae_s16 src = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, 0);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, dsta, 1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = get_word_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (4/0) */
/* 6 0,0   */

/* CMP.W #<data>.W,(xxx).L */
uae_u32 REGPARAM2 op_0c79_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 25;
	CurrentInstrCycles = 20; 
	uae_s16 src = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = get_word_000_prefetch(6) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	dsta |= get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 8, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(8);
		exception3_read_access(opcode, dsta, 1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = get_word_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(10);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 10, pcoffset);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(8);
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (5/0) */
/* 8 0,0   */

/* CMP.L #<data>.L,Dn */
uae_u32 REGPARAM2 op_0c80_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 25;
	CurrentInstrCycles = 14; 
	uae_s32 src;
	src = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	m68k_incpci(6);
	return 14 * CYCLE_UNIT / 2 + count_cycles;
}
/* 14 (3/0) */
/* 6 0,0   */

/* CMP.L #<data>.L,(An) */
uae_u32 REGPARAM2 op_0c90_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 25;
	CurrentInstrCycles = 20; 
	uae_s32 src;
	src = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	if (dsta & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, dsta, 2, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = get_word_000(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	dst |= get_word_000(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (5/0) */
/* 6 0,0   */

/* CMP.L #<data>.L,(An)+ */
uae_u32 REGPARAM2 op_0c98_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 25;
	CurrentInstrCycles = 20; 
	uae_s32 src;
	src = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	if (dsta & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, dsta, 2, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = get_word_000(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	dst |= get_word_000(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) += 4;
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (5/0) */
/* 6 0,0   */

/* CMP.L #<data>.L,-(An) */
uae_u32 REGPARAM2 op_0ca0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 25;
	CurrentInstrCycles = 22; 
	uae_s32 src;
	src = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - 4;
	if (dsta & 1) {
		m68k_incpci(6);
		m68k_areg(regs, dstreg) = dsta;
		exception3_read_access(opcode, dsta, 2, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = get_word_000(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		m68k_areg(regs, dstreg) = dsta;
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	dst |= get_word_000(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		m68k_areg(regs, dstreg) = dsta;
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) = dsta;
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 22 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 22 * CYCLE_UNIT / 2 + count_cycles;
}
/* 22 (5/0) */
/* 6 0,0   */

/* CMP.L #<data>.L,(d16,An) */
uae_u32 REGPARAM2 op_0ca8_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 25;
	CurrentInstrCycles = 24; 
	uae_s32 src;
	src = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 8, -2);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, dsta, 2, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = get_word_000(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	dst |= get_word_000(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(10);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 10, pcoffset);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(8);
	return 24 * CYCLE_UNIT / 2 + count_cycles;
}
/* 24 (6/0) */
/* 8 0,0   */

/* CMP.L #<data>.L,(d8,An,Xn) */
uae_u32 REGPARAM2 op_0cb0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 25;
	CurrentInstrCycles = 26; 
	uae_s32 src;
	src = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	BusCyclePenalty += 2;
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_000_prefetch(8));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 8, -2);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, dsta, 2, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = get_word_000(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	dst |= get_word_000(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return 22 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(10);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 10, pcoffset);
		return 26 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(8);
	return 26 * CYCLE_UNIT / 2 + count_cycles;
}
/* 26 (6/0) */
/* 8 4,0   */

/* CMP.L #<data>.L,(xxx).W */
uae_u32 REGPARAM2 op_0cb8_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 25;
	CurrentInstrCycles = 24; 
	uae_s32 src;
	src = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 8, 0);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(8);
		exception3_read_access(opcode, dsta, 2, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = get_word_000(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	dst |= get_word_000(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(10);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 10, pcoffset);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(8);
	return 24 * CYCLE_UNIT / 2 + count_cycles;
}
/* 24 (6/0) */
/* 8 0,0   */

/* CMP.L #<data>.L,(xxx).L */
uae_u32 REGPARAM2 op_0cb9_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 25;
	CurrentInstrCycles = 28; 
	uae_s32 src;
	src = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = get_word_000_prefetch(8) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 8, -2);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	dsta |= get_word_000_prefetch(10);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 10, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(10);
		exception3_read_access(opcode, dsta, 2, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = get_word_000(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(10);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	dst |= get_word_000(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(10);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(12);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 12, pcoffset);
		return 28 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(10);
	return 28 * CYCLE_UNIT / 2 + count_cycles;
}
/* 28 (7/0) */
/* 10 0,0   */

/* MOVE.B Dn,Dn */
uae_u32 REGPARAM2 op_1000_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 4;  
	uae_s8 src = m68k_dreg(regs, srcreg);
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
	m68k_incpci(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 4 * CYCLE_UNIT / 2 + count_cycles;
}
/* 4 (1/0) */
/* 2 0,0   */

/* MOVE.B (An),Dn */
uae_u32 REGPARAM2 op_1010_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 8;  
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
	m68k_incpci(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8 (2/0) */
/* 2 0,0   */

/* MOVE.B (An)+,Dn */
uae_u32 REGPARAM2 op_1018_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 8;  
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
	m68k_incpci(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8 (2/0) */
/* 2 0,0   */

/* MOVE.B -(An),Dn */
uae_u32 REGPARAM2 op_1020_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 10; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) = srca;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
	m68k_incpci(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 10 * CYCLE_UNIT / 2 + count_cycles;
}
/* 10 (2/0) */
/* 2 0,0   */

/* MOVE.B (d16,An),Dn */
uae_u32 REGPARAM2 op_1028_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (3/0) */
/* 4 0,0   */

/* MOVE.B (d8,An,Xn),Dn */
uae_u32 REGPARAM2 op_1030_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	BusCyclePenalty += 2;
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 14 * CYCLE_UNIT / 2 + count_cycles;
}
/* 14 (3/0) */
/* 4 4,0   */

/* MOVE.B (xxx).W,Dn */
uae_u32 REGPARAM2 op_1038_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (3/0) */
/* 4 0,0   */

/* MOVE.B (xxx).L,Dn */
uae_u32 REGPARAM2 op_1039_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	srca |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (4/0) */
/* 6 0,0   */

/* MOVE.B (d16,PC),Dn */
uae_u32 REGPARAM2 op_103a_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_getpci() + 2;
	srca += (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 2);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (3/0) */
/* 4 0,0   */

/* MOVE.B (d8,PC,Xn),Dn */
uae_u32 REGPARAM2 op_103b_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	uaecptr tmppc = m68k_getpci() + 2;
	BusCyclePenalty += 2;
	srca = get_disp_ea_000(tmppc, get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 2);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 14 * CYCLE_UNIT / 2 + count_cycles;
}
/* 14 (3/0) */
/* 4 4,0   */

/* MOVE.B #<data>.B,Dn */
uae_u32 REGPARAM2 op_103c_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 8;  
	uae_s8 src = (uae_u8)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8 (2/0) */
/* 4 0,0   */

/* MOVE.B Dn,(An) */
uae_u32 REGPARAM2 op_1080_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 8;  
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	put_byte_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8 (1/1) */
/* 2 0,0   */

/* MOVE.B (An),(An) */
uae_u32 REGPARAM2 op_1090_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	put_byte_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (2/1) */
/* 2 0,0   */

/* MOVE.B (An)+,(An) */
uae_u32 REGPARAM2 op_1098_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	put_byte_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (2/1) */
/* 2 0,0   */

/* MOVE.B -(An),(An) */
uae_u32 REGPARAM2 op_10a0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) = srca;
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	put_byte_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 14 * CYCLE_UNIT / 2 + count_cycles;
}
/* 14 (2/1) */
/* 2 0,0   */

/* MOVE.B (d16,An),(An) */
uae_u32 REGPARAM2 op_10a8_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	put_byte_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 4 0,0   */

/* MOVE.B (d8,An,Xn),(An) */
uae_u32 REGPARAM2 op_10b0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	BusCyclePenalty += 2;
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	put_byte_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (3/1) */
/* 4 4,0   */

/* MOVE.B (xxx).W,(An) */
uae_u32 REGPARAM2 op_10b8_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	put_byte_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 4 0,0   */

/* MOVE.B (xxx).L,(An) */
uae_u32 REGPARAM2 op_10b9_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	srca = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	srca |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	put_byte_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (4/1) */
/* 6 0,0   */

/* MOVE.B (d16,PC),(An) */
uae_u32 REGPARAM2 op_10ba_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = m68k_getpci() + 2;
	srca += (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 2);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	put_byte_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 4 0,0   */

/* MOVE.B (d8,PC,Xn),(An) */
uae_u32 REGPARAM2 op_10bb_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	uaecptr tmppc = m68k_getpci() + 2;
	BusCyclePenalty += 2;
	srca = get_disp_ea_000(tmppc, get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 2);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	put_byte_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (3/1) */
/* 4 4,0   */

/* MOVE.B #<data>.B,(An) */
uae_u32 REGPARAM2 op_10bc_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 12; 
	uae_s8 src = (uae_u8)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	put_byte_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (2/1) */
/* 4 0,0   */

/* MOVE.B Dn,(An)+ */
uae_u32 REGPARAM2 op_10c0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 8;  
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	put_byte_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, dstreg) -= areg_byteinc[dstreg];
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8 (1/1) */
/* 2 0,0   */

/* MOVE.B (An),(An)+ */
uae_u32 REGPARAM2 op_10d0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	put_byte_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, dstreg) -= areg_byteinc[dstreg];
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (2/1) */
/* 2 0,0   */

/* MOVE.B (An)+,(An)+ */
uae_u32 REGPARAM2 op_10d8_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	put_byte_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, dstreg) -= areg_byteinc[dstreg];
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (2/1) */
/* 2 0,0   */

/* MOVE.B -(An),(An)+ */
uae_u32 REGPARAM2 op_10e0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) = srca;
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	put_byte_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, dstreg) -= areg_byteinc[dstreg];
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 14 * CYCLE_UNIT / 2 + count_cycles;
}
/* 14 (2/1) */
/* 2 0,0   */

/* MOVE.B (d16,An),(An)+ */
uae_u32 REGPARAM2 op_10e8_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	put_byte_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, dstreg) -= areg_byteinc[dstreg];
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 4 0,0   */

/* MOVE.B (d8,An,Xn),(An)+ */
uae_u32 REGPARAM2 op_10f0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	BusCyclePenalty += 2;
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	put_byte_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, dstreg) -= areg_byteinc[dstreg];
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (3/1) */
/* 4 4,0   */

/* MOVE.B (xxx).W,(An)+ */
uae_u32 REGPARAM2 op_10f8_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	put_byte_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, dstreg) -= areg_byteinc[dstreg];
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 4 0,0   */

/* MOVE.B (xxx).L,(An)+ */
uae_u32 REGPARAM2 op_10f9_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	srca = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	srca |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	put_byte_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		m68k_areg(regs, dstreg) -= areg_byteinc[dstreg];
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (4/1) */
/* 6 0,0   */

/* MOVE.B (d16,PC),(An)+ */
uae_u32 REGPARAM2 op_10fa_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = m68k_getpci() + 2;
	srca += (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 2);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	put_byte_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, dstreg) -= areg_byteinc[dstreg];
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 4 0,0   */

/* MOVE.B (d8,PC,Xn),(An)+ */
uae_u32 REGPARAM2 op_10fb_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	uaecptr tmppc = m68k_getpci() + 2;
	BusCyclePenalty += 2;
	srca = get_disp_ea_000(tmppc, get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 2);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	put_byte_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, dstreg) -= areg_byteinc[dstreg];
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (3/1) */
/* 4 4,0   */

/* MOVE.B #<data>.B,(An)+ */
uae_u32 REGPARAM2 op_10fc_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 12; 
	uae_s8 src = (uae_u8)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	put_byte_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, dstreg) -= areg_byteinc[dstreg];
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (2/1) */
/* 4 0,0   */

/* MOVE.B Dn,-(An) */
uae_u32 REGPARAM2 op_1100_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 8;  
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
	m68k_areg(regs, dstreg) = dsta;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	put_byte_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8 (1/1) */
/* 2 0,0   */

/* MOVE.B (An),-(An) */
uae_u32 REGPARAM2 op_1110_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
	m68k_areg(regs, dstreg) = dsta;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	put_byte_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (2/1) */
/* 2 0,0   */

/* MOVE.B (An)+,-(An) */
uae_u32 REGPARAM2 op_1118_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
	m68k_areg(regs, dstreg) = dsta;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	put_byte_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (2/1) */
/* 2 0,0   */

/* MOVE.B -(An),-(An) */
uae_u32 REGPARAM2 op_1120_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) = srca;
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
	m68k_areg(regs, dstreg) = dsta;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	put_byte_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 14 * CYCLE_UNIT / 2 + count_cycles;
}
/* 14 (2/1) */
/* 2 0,0   */

/* MOVE.B (d16,An),-(An) */
uae_u32 REGPARAM2 op_1128_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
	m68k_areg(regs, dstreg) = dsta;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	put_byte_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 4 0,0   */

/* MOVE.B (d8,An,Xn),-(An) */
uae_u32 REGPARAM2 op_1130_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	BusCyclePenalty += 2;
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
	m68k_areg(regs, dstreg) = dsta;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	put_byte_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (3/1) */
/* 4 4,0   */

/* MOVE.B (xxx).W,-(An) */
uae_u32 REGPARAM2 op_1138_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
	m68k_areg(regs, dstreg) = dsta;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	put_byte_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 4 0,0   */

/* MOVE.B (xxx).L,-(An) */
uae_u32 REGPARAM2 op_1139_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	srca = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	srca |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
	m68k_areg(regs, dstreg) = dsta;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	put_byte_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (4/1) */
/* 6 0,0   */

/* MOVE.B (d16,PC),-(An) */
uae_u32 REGPARAM2 op_113a_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = m68k_getpci() + 2;
	srca += (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 2);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
	m68k_areg(regs, dstreg) = dsta;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	put_byte_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 4 0,0   */

/* MOVE.B (d8,PC,Xn),-(An) */
uae_u32 REGPARAM2 op_113b_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	uaecptr tmppc = m68k_getpci() + 2;
	BusCyclePenalty += 2;
	srca = get_disp_ea_000(tmppc, get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 2);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
	m68k_areg(regs, dstreg) = dsta;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	put_byte_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (3/1) */
/* 4 4,0   */

/* MOVE.B #<data>.B,-(An) */
uae_u32 REGPARAM2 op_113c_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 12; 
	uae_s8 src = (uae_u8)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
	m68k_areg(regs, dstreg) = dsta;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	put_byte_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (2/1) */
/* 4 0,0   */

/* MOVE.B Dn,(d16,An) */
uae_u32 REGPARAM2 op_1140_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 12; 
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	put_byte_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (2/1) */
/* 4 0,0   */

/* MOVE.B (An),(d16,An) */
uae_u32 REGPARAM2 op_1150_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 4, 0);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	put_byte_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 4 0,0   */

/* MOVE.B (An)+,(d16,An) */
uae_u32 REGPARAM2 op_1158_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 4, 0);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	put_byte_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 4 0,0   */

/* MOVE.B -(An),(d16,An) */
uae_u32 REGPARAM2 op_1160_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) = srca;
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 4, 0);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	put_byte_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (3/1) */
/* 4 0,0   */

/* MOVE.B (d16,An),(d16,An) */
uae_u32 REGPARAM2 op_1168_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 6, 0);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	put_byte_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (4/1) */
/* 6 0,0   */

/* MOVE.B (d8,An,Xn),(d16,An) */
uae_u32 REGPARAM2 op_1170_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 22; 
	uaecptr srca;
	BusCyclePenalty += 2;
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 6, 0);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	put_byte_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 22 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 22 * CYCLE_UNIT / 2 + count_cycles;
}
/* 22 (4/1) */
/* 6 6,0   */

/* MOVE.B (xxx).W,(d16,An) */
uae_u32 REGPARAM2 op_1178_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 6, 0);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	put_byte_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (4/1) */
/* 6 0,0   */

/* MOVE.B (xxx).L,(d16,An) */
uae_u32 REGPARAM2 op_1179_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 24; 
	uaecptr srca;
	srca = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	srca |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 8, 0);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	put_byte_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(8);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 24 * CYCLE_UNIT / 2 + count_cycles;
}
/* 24 (5/1) */
/* 8 0,0   */

/* MOVE.B (d16,PC),(d16,An) */
uae_u32 REGPARAM2 op_117a_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	srca = m68k_getpci() + 2;
	srca += (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 2);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 6, 0);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	put_byte_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (4/1) */
/* 6 0,0   */

/* MOVE.B (d8,PC,Xn),(d16,An) */
uae_u32 REGPARAM2 op_117b_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 22; 
	uaecptr srca;
	uaecptr tmppc = m68k_getpci() + 2;
	BusCyclePenalty += 2;
	srca = get_disp_ea_000(tmppc, get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 2);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 6, 0);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	put_byte_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 22 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 22 * CYCLE_UNIT / 2 + count_cycles;
}
/* 22 (4/1) */
/* 6 6,0   */

/* MOVE.B #<data>.B,(d16,An) */
uae_u32 REGPARAM2 op_117c_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 16; 
	uae_s8 src = (uae_u8)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, 0);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	put_byte_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 6 0,0   */

/* MOVE.B Dn,(d8,An,Xn) */
uae_u32 REGPARAM2 op_1180_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 14; 
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	BusCyclePenalty += 2;
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	put_byte_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 14 * CYCLE_UNIT / 2 + count_cycles;
}
/* 14 (2/1) */
/* 4 4,0   */

/* MOVE.B (An),(d8,An,Xn) */
uae_u32 REGPARAM2 op_1190_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	BusCyclePenalty += 2;
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 4, 0);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	put_byte_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (3/1) */
/* 4 4,0   */

/* MOVE.B (An)+,(d8,An,Xn) */
uae_u32 REGPARAM2 op_1198_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
	uaecptr dsta;
	BusCyclePenalty += 2;
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 4, 0);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	put_byte_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (3/1) */
/* 4 4,0   */

/* MOVE.B -(An),(d8,An,Xn) */
uae_u32 REGPARAM2 op_11a0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) = srca;
	uaecptr dsta;
	BusCyclePenalty += 2;
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 4, 0);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	put_byte_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (3/1) */
/* 4 4,0   */

/* MOVE.B (d16,An),(d8,An,Xn) */
uae_u32 REGPARAM2 op_11a8_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 22; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	BusCyclePenalty += 2;
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_000_prefetch(6));
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 6, 0);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	put_byte_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 22 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 22 * CYCLE_UNIT / 2 + count_cycles;
}
/* 22 (4/1) */
/* 6 4,0   */

/* MOVE.B (d8,An,Xn),(d8,An,Xn) */
uae_u32 REGPARAM2 op_11b0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 24; 
	uaecptr srca;
	BusCyclePenalty += 2;
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	BusCyclePenalty += 2;
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_000_prefetch(6));
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 6, 0);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	put_byte_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 24 * CYCLE_UNIT / 2 + count_cycles;
}
/* 24 (4/1) */
/* 6 6,4   */

/* MOVE.B (xxx).W,(d8,An,Xn) */
uae_u32 REGPARAM2 op_11b8_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 22; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	BusCyclePenalty += 2;
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_000_prefetch(6));
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 6, 0);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	put_byte_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 22 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 22 * CYCLE_UNIT / 2 + count_cycles;
}
/* 22 (4/1) */
/* 6 4,0   */

/* MOVE.B (xxx).L,(d8,An,Xn) */
uae_u32 REGPARAM2 op_11b9_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 26; 
	uaecptr srca;
	srca = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	srca |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	BusCyclePenalty += 2;
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_000_prefetch(8));
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 8, 0);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	put_byte_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return 22 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(8);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 26 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 26 * CYCLE_UNIT / 2 + count_cycles;
}
/* 26 (5/1) */
/* 8 4,0   */

/* MOVE.B (d16,PC),(d8,An,Xn) */
uae_u32 REGPARAM2 op_11ba_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 22; 
	uaecptr srca;
	srca = m68k_getpci() + 2;
	srca += (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 2);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	BusCyclePenalty += 2;
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_000_prefetch(6));
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 6, 0);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	put_byte_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 22 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 22 * CYCLE_UNIT / 2 + count_cycles;
}
/* 22 (4/1) */
/* 6 4,0   */

/* MOVE.B (d8,PC,Xn),(d8,An,Xn) */
uae_u32 REGPARAM2 op_11bb_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 24; 
	uaecptr srca;
	uaecptr tmppc = m68k_getpci() + 2;
	BusCyclePenalty += 2;
	srca = get_disp_ea_000(tmppc, get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 2);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	BusCyclePenalty += 2;
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_000_prefetch(6));
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 6, 0);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	put_byte_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 24 * CYCLE_UNIT / 2 + count_cycles;
}
/* 24 (4/1) */
/* 6 6,4   */

/* MOVE.B #<data>.B,(d8,An,Xn) */
uae_u32 REGPARAM2 op_11bc_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 18; 
	uae_s8 src = (uae_u8)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	BusCyclePenalty += 2;
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_000_prefetch(6));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, 0);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	put_byte_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (3/1) */
/* 6 4,0   */

/* MOVE.B Dn,(xxx).W */
uae_u32 REGPARAM2 op_11c0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 30;
	CurrentInstrCycles = 12; 
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	put_byte_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (2/1) */
/* 4 0,0   */

/* MOVE.B (An),(xxx).W */
uae_u32 REGPARAM2 op_11d0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 30;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 4, 0);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	put_byte_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 4 0,0   */

/* MOVE.B (An)+,(xxx).W */
uae_u32 REGPARAM2 op_11d8_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 30;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 4, 0);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	put_byte_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 4 0,0   */

/* MOVE.B -(An),(xxx).W */
uae_u32 REGPARAM2 op_11e0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 30;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) = srca;
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 4, 0);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	put_byte_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (3/1) */
/* 4 0,0   */

/* MOVE.B (d16,An),(xxx).W */
uae_u32 REGPARAM2 op_11e8_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 30;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 6, 0);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	put_byte_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (4/1) */
/* 6 0,0   */

/* MOVE.B (d8,An,Xn),(xxx).W */
uae_u32 REGPARAM2 op_11f0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 30;
	CurrentInstrCycles = 22; 
	uaecptr srca;
	BusCyclePenalty += 2;
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 6, 0);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	put_byte_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 22 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 22 * CYCLE_UNIT / 2 + count_cycles;
}
/* 22 (4/1) */
/* 6 6,0   */

/* MOVE.B (xxx).W,(xxx).W */
uae_u32 REGPARAM2 op_11f8_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 30;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 6, 0);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	put_byte_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (4/1) */
/* 6 0,0   */

/* MOVE.B (xxx).L,(xxx).W */
uae_u32 REGPARAM2 op_11f9_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 30;
	CurrentInstrCycles = 24; 
	uaecptr srca;
	srca = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	srca |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 8, 0);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	put_byte_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(8);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 24 * CYCLE_UNIT / 2 + count_cycles;
}
/* 24 (5/1) */
/* 8 0,0   */

/* MOVE.B (d16,PC),(xxx).W */
uae_u32 REGPARAM2 op_11fa_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 30;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	srca = m68k_getpci() + 2;
	srca += (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 2);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 6, 0);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	put_byte_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (4/1) */
/* 6 0,0   */

/* MOVE.B (d8,PC,Xn),(xxx).W */
uae_u32 REGPARAM2 op_11fb_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 30;
	CurrentInstrCycles = 22; 
	uaecptr srca;
	uaecptr tmppc = m68k_getpci() + 2;
	BusCyclePenalty += 2;
	srca = get_disp_ea_000(tmppc, get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 2);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 6, 0);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	put_byte_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 22 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 22 * CYCLE_UNIT / 2 + count_cycles;
}
/* 22 (4/1) */
/* 6 6,0   */

/* MOVE.B #<data>.B,(xxx).W */
uae_u32 REGPARAM2 op_11fc_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 30;
	CurrentInstrCycles = 16; 
	uae_s8 src = (uae_u8)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 6, 0);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	put_byte_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 6 0,0   */

/* MOVE.B Dn,(xxx).L */
uae_u32 REGPARAM2 op_13c0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 30;
	CurrentInstrCycles = 16; 
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	dsta |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	put_byte_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 6 0,0   */

/* MOVE.B (An),(xxx).L */
uae_u32 REGPARAM2 op_13d0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 30;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = get_word_000_prefetch(4) << 16;
	dsta |= regs.irc;
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 4, 0);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	put_byte_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	get_word_000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, 0);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	if(regs.t1) opcode |= 0x10000;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (4/1) */
/* 6 0,0   */

/* MOVE.B (An)+,(xxx).L */
uae_u32 REGPARAM2 op_13d8_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 30;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
	uaecptr dsta;
	dsta = get_word_000_prefetch(4) << 16;
	dsta |= regs.irc;
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 4, 0);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	put_byte_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	get_word_000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, 0);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	if(regs.t1) opcode |= 0x10000;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (4/1) */
/* 6 0,0   */

/* MOVE.B -(An),(xxx).L */
uae_u32 REGPARAM2 op_13e0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 30;
	CurrentInstrCycles = 22; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) = srca;
	uaecptr dsta;
	dsta = get_word_000_prefetch(4) << 16;
	dsta |= regs.irc;
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 4, 0);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	put_byte_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	get_word_000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, 0);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	if(regs.t1) opcode |= 0x10000;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 22 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 22 * CYCLE_UNIT / 2 + count_cycles;
}
/* 22 (4/1) */
/* 6 0,0   */

/* MOVE.B (d16,An),(xxx).L */
uae_u32 REGPARAM2 op_13e8_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 30;
	CurrentInstrCycles = 24; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = get_word_000_prefetch(6) << 16;
	dsta |= regs.irc;
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 6, 0);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	put_byte_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(8);
	get_word_000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, 0);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	if(regs.t1) opcode |= 0x10000;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 24 * CYCLE_UNIT / 2 + count_cycles;
}
/* 24 (5/1) */
/* 8 0,0   */

/* MOVE.B (d8,An,Xn),(xxx).L */
uae_u32 REGPARAM2 op_13f0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 30;
	CurrentInstrCycles = 26; 
	uaecptr srca;
	BusCyclePenalty += 2;
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = get_word_000_prefetch(6) << 16;
	dsta |= regs.irc;
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 6, 0);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	put_byte_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(8);
	get_word_000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, 0);
		return 22 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	if(regs.t1) opcode |= 0x10000;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 26 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 26 * CYCLE_UNIT / 2 + count_cycles;
}
/* 26 (5/1) */
/* 8 8,0   */

/* MOVE.B (xxx).W,(xxx).L */
uae_u32 REGPARAM2 op_13f8_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 30;
	CurrentInstrCycles = 24; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = get_word_000_prefetch(6) << 16;
	dsta |= regs.irc;
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 6, 0);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	put_byte_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(8);
	get_word_000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, 0);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	if(regs.t1) opcode |= 0x10000;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 24 * CYCLE_UNIT / 2 + count_cycles;
}
/* 24 (5/1) */
/* 8 0,0   */

/* MOVE.B (xxx).L,(xxx).L */
uae_u32 REGPARAM2 op_13f9_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 30;
	CurrentInstrCycles = 28; 
	uaecptr srca;
	srca = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	srca |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = get_word_000_prefetch(8) << 16;
	dsta |= regs.irc;
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 8, 0);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	put_byte_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(10);
	get_word_000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, 0);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	if(regs.t1) opcode |= 0x10000;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 28 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 28 * CYCLE_UNIT / 2 + count_cycles;
}
/* 28 (6/1) */
/* 10 0,0   */

/* MOVE.B (d16,PC),(xxx).L */
uae_u32 REGPARAM2 op_13fa_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 30;
	CurrentInstrCycles = 24; 
	uaecptr srca;
	srca = m68k_getpci() + 2;
	srca += (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 2);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = get_word_000_prefetch(6) << 16;
	dsta |= regs.irc;
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 6, 0);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	put_byte_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(8);
	get_word_000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, 0);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	if(regs.t1) opcode |= 0x10000;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 24 * CYCLE_UNIT / 2 + count_cycles;
}
/* 24 (5/1) */
/* 8 0,0   */

/* MOVE.B (d8,PC,Xn),(xxx).L */
uae_u32 REGPARAM2 op_13fb_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 30;
	CurrentInstrCycles = 26; 
	uaecptr srca;
	uaecptr tmppc = m68k_getpci() + 2;
	BusCyclePenalty += 2;
	srca = get_disp_ea_000(tmppc, get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 2);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = get_word_000_prefetch(6) << 16;
	dsta |= regs.irc;
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 6, 0);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	put_byte_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(8);
	get_word_000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, 0);
		return 22 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	if(regs.t1) opcode |= 0x10000;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 26 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 26 * CYCLE_UNIT / 2 + count_cycles;
}
/* 26 (5/1) */
/* 8 8,0   */

/* MOVE.B #<data>.B,(xxx).L */
uae_u32 REGPARAM2 op_13fc_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 30;
	CurrentInstrCycles = 20; 
	uae_s8 src = (uae_u8)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = get_word_000_prefetch(6) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	dsta |= get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 8, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	put_byte_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(8);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (4/1) */
/* 8 0,0   */

/* MOVE.L Dn,Dn */
uae_u32 REGPARAM2 op_2000_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 4;  
	uae_s32 src = m68k_dreg(regs, srcreg);
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	m68k_dreg(regs, dstreg) = (src);
	m68k_incpci(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 4 * CYCLE_UNIT / 2 + count_cycles;
}
/* 4 (1/0) */
/* 2 0,0   */

/* MOVE.L An,Dn */
uae_u32 REGPARAM2 op_2008_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 4;  
	uae_s32 src = m68k_areg(regs, srcreg);
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	m68k_dreg(regs, dstreg) = (src);
	m68k_incpci(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 4 * CYCLE_UNIT / 2 + count_cycles;
}
/* 4 (1/0) */
/* 2 0,0   */

/* MOVE.L (An),Dn */
uae_u32 REGPARAM2 op_2010_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	m68k_dreg(regs, dstreg) = (src);
	m68k_incpci(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (3/0) */
/* 2 0,0   */

/* MOVE.L (An)+,Dn */
uae_u32 REGPARAM2 op_2018_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) += 4;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	m68k_dreg(regs, dstreg) = (src);
	m68k_incpci(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (3/0) */
/* 2 0,0   */

/* MOVE.L -(An),Dn */
uae_u32 REGPARAM2 op_2020_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - 4;
	if (srca & 1) {
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception3_read_access(opcode, srca, 2, 1);
		return 2 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) = srca;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	m68k_dreg(regs, dstreg) = (src);
	m68k_incpci(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 14 * CYCLE_UNIT / 2 + count_cycles;
}
/* 14 (3/0) */
/* 2 0,0   */

/* MOVE.L (d16,An),Dn */
uae_u32 REGPARAM2 op_2028_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	m68k_dreg(regs, dstreg) = (src);
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (4/0) */
/* 4 0,0   */

/* MOVE.L (d8,An,Xn),Dn */
uae_u32 REGPARAM2 op_2030_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	BusCyclePenalty += 2;
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	m68k_dreg(regs, dstreg) = (src);
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (4/0) */
/* 4 4,0   */

/* MOVE.L (xxx).W,Dn */
uae_u32 REGPARAM2 op_2038_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, srca, 2, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	m68k_dreg(regs, dstreg) = (src);
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (4/0) */
/* 4 0,0   */

/* MOVE.L (xxx).L,Dn */
uae_u32 REGPARAM2 op_2039_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	srca = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	srca |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, srca, 2, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	m68k_dreg(regs, dstreg) = (src);
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (5/0) */
/* 6 0,0   */

/* MOVE.L (d16,PC),Dn */
uae_u32 REGPARAM2 op_203a_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = m68k_getpci() + 2;
	srca += (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 2);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	m68k_dreg(regs, dstreg) = (src);
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (4/0) */
/* 4 0,0   */

/* MOVE.L (d8,PC,Xn),Dn */
uae_u32 REGPARAM2 op_203b_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	uaecptr tmppc = m68k_getpci() + 2;
	BusCyclePenalty += 2;
	srca = get_disp_ea_000(tmppc, get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 2);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	m68k_dreg(regs, dstreg) = (src);
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (4/0) */
/* 4 4,0   */

/* MOVE.L #<data>.L,Dn */
uae_u32 REGPARAM2 op_203c_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 12; 
	uae_s32 src;
	src = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	m68k_dreg(regs, dstreg) = (src);
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (3/0) */
/* 6 0,0   */

/* MOVEA.L Dn,An */
uae_u32 REGPARAM2 op_2040_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 31;
	CurrentInstrCycles = 4;  
	uae_s32 src = m68k_dreg(regs, srcreg);
	m68k_areg(regs, dstreg) = (src);
	m68k_incpci(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 4 * CYCLE_UNIT / 2 + count_cycles;
}
/* 4 (1/0) */
/* 2 0,0   */

/* MOVEA.L An,An */
uae_u32 REGPARAM2 op_2048_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 31;
	CurrentInstrCycles = 4;  
	uae_s32 src = m68k_areg(regs, srcreg);
	m68k_areg(regs, dstreg) = (src);
	m68k_incpci(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 4 * CYCLE_UNIT / 2 + count_cycles;
}
/* 4 (1/0) */
/* 2 0,0   */

/* MOVEA.L (An),An */
uae_u32 REGPARAM2 op_2050_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 31;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) = (src);
	m68k_incpci(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (3/0) */
/* 2 0,0   */

/* MOVEA.L (An)+,An */
uae_u32 REGPARAM2 op_2058_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 31;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) += 4;
	m68k_areg(regs, dstreg) = (src);
	m68k_incpci(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (3/0) */
/* 2 0,0   */

/* MOVEA.L -(An),An */
uae_u32 REGPARAM2 op_2060_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 31;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - 4;
	if (srca & 1) {
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception3_read_access(opcode, srca, 2, 1);
		return 2 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) = srca;
	m68k_areg(regs, dstreg) = (src);
	m68k_incpci(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 14 * CYCLE_UNIT / 2 + count_cycles;
}
/* 14 (3/0) */
/* 2 0,0   */

/* MOVEA.L (d16,An),An */
uae_u32 REGPARAM2 op_2068_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 31;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) = (src);
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (4/0) */
/* 4 0,0   */

/* MOVEA.L (d8,An,Xn),An */
uae_u32 REGPARAM2 op_2070_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 31;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	BusCyclePenalty += 2;
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) = (src);
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (4/0) */
/* 4 4,0   */

/* MOVEA.L (xxx).W,An */
uae_u32 REGPARAM2 op_2078_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 31;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, srca, 2, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) = (src);
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (4/0) */
/* 4 0,0   */

/* MOVEA.L (xxx).L,An */
uae_u32 REGPARAM2 op_2079_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 31;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	srca = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	srca |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, srca, 2, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) = (src);
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (5/0) */
/* 6 0,0   */

/* MOVEA.L (d16,PC),An */
uae_u32 REGPARAM2 op_207a_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 31;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = m68k_getpci() + 2;
	srca += (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 2);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) = (src);
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (4/0) */
/* 4 0,0   */

/* MOVEA.L (d8,PC,Xn),An */
uae_u32 REGPARAM2 op_207b_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 31;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	uaecptr tmppc = m68k_getpci() + 2;
	BusCyclePenalty += 2;
	srca = get_disp_ea_000(tmppc, get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 2);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) = (src);
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (4/0) */
/* 4 4,0   */

/* MOVEA.L #<data>.L,An */
uae_u32 REGPARAM2 op_207c_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 31;
	CurrentInstrCycles = 12; 
	uae_s32 src;
	src = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) = (src);
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (3/0) */
/* 6 0,0   */

/* MOVE.L Dn,(An) */
uae_u32 REGPARAM2 op_2080_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 12; 
	uae_s32 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	if (dsta & 1) {
		m68k_incpci(4);
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	put_word_000(dsta + 2, src); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		ccr_68000_long_move_ae_LZN(src);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (1/2) */
/* 2 0,0   */

/* MOVE.L An,(An) */
uae_u32 REGPARAM2 op_2088_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 12; 
	uae_s32 src = m68k_areg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	if (dsta & 1) {
		m68k_incpci(4);
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	put_word_000(dsta + 2, src); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		ccr_68000_long_move_ae_LZN(src);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (1/2) */
/* 2 0,0   */

/* MOVE.L (An),(An) */
uae_u32 REGPARAM2 op_2090_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	if (dsta & 1) {
		m68k_incpci(4);
		ccr_68000_long_move_ae_LZN(src);
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		ccr_68000_long_move_ae_LZN(src);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	put_word_000(dsta + 2, src); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (3/2) */
/* 2 0,0   */

/* MOVE.L (An)+,(An) */
uae_u32 REGPARAM2 op_2098_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) += 4;
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	if (dsta & 1) {
		m68k_incpci(4);
		ccr_68000_long_move_ae_LZN(src);
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		ccr_68000_long_move_ae_LZN(src);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	put_word_000(dsta + 2, src); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (3/2) */
/* 2 0,0   */

/* MOVE.L -(An),(An) */
uae_u32 REGPARAM2 op_20a0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 22; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - 4;
	if (srca & 1) {
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception3_read_access(opcode, srca, 2, 1);
		return 2 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) = srca;
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	if (dsta & 1) {
		m68k_incpci(4);
		ccr_68000_long_move_ae_LZN(src);
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		ccr_68000_long_move_ae_LZN(src);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	put_word_000(dsta + 2, src); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 22 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 22 * CYCLE_UNIT / 2 + count_cycles;
}
/* 22 (3/2) */
/* 2 0,0   */

/* MOVE.L (d16,An),(An) */
uae_u32 REGPARAM2 op_20a8_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 24; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	if (dsta & 1) {
		m68k_incpci(6);
		ccr_68000_long_move_ae_LZN(src);
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		ccr_68000_long_move_ae_LZN(src);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	put_word_000(dsta + 2, src); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 24 * CYCLE_UNIT / 2 + count_cycles;
}
/* 24 (4/2) */
/* 4 0,0   */

/* MOVE.L (d8,An,Xn),(An) */
uae_u32 REGPARAM2 op_20b0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 26; 
	uaecptr srca;
	BusCyclePenalty += 2;
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	if (dsta & 1) {
		m68k_incpci(6);
		ccr_68000_long_move_ae_LZN(src);
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		ccr_68000_long_move_ae_LZN(src);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	put_word_000(dsta + 2, src); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return 22 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 26 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 26 * CYCLE_UNIT / 2 + count_cycles;
}
/* 26 (4/2) */
/* 4 4,0   */

/* MOVE.L (xxx).W,(An) */
uae_u32 REGPARAM2 op_20b8_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 24; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, srca, 2, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	if (dsta & 1) {
		m68k_incpci(6);
		ccr_68000_long_move_ae_LZN(src);
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		ccr_68000_long_move_ae_LZN(src);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	put_word_000(dsta + 2, src); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 24 * CYCLE_UNIT / 2 + count_cycles;
}
/* 24 (4/2) */
/* 4 0,0   */

/* MOVE.L (xxx).L,(An) */
uae_u32 REGPARAM2 op_20b9_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 28; 
	uaecptr srca;
	srca = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	srca |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, srca, 2, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	if (dsta & 1) {
		m68k_incpci(8);
		ccr_68000_long_move_ae_LZN(src);
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		ccr_68000_long_move_ae_LZN(src);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	put_word_000(dsta + 2, src); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 28 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 28 * CYCLE_UNIT / 2 + count_cycles;
}
/* 28 (5/2) */
/* 6 0,0   */

/* MOVE.L (d16,PC),(An) */
uae_u32 REGPARAM2 op_20ba_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 24; 
	uaecptr srca;
	srca = m68k_getpci() + 2;
	srca += (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 2);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	if (dsta & 1) {
		m68k_incpci(6);
		ccr_68000_long_move_ae_LZN(src);
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		ccr_68000_long_move_ae_LZN(src);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	put_word_000(dsta + 2, src); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 24 * CYCLE_UNIT / 2 + count_cycles;
}
/* 24 (4/2) */
/* 4 0,0   */

/* MOVE.L (d8,PC,Xn),(An) */
uae_u32 REGPARAM2 op_20bb_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 26; 
	uaecptr srca;
	uaecptr tmppc = m68k_getpci() + 2;
	BusCyclePenalty += 2;
	srca = get_disp_ea_000(tmppc, get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 2);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	if (dsta & 1) {
		m68k_incpci(6);
		ccr_68000_long_move_ae_LZN(src);
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		ccr_68000_long_move_ae_LZN(src);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	put_word_000(dsta + 2, src); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return 22 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 26 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 26 * CYCLE_UNIT / 2 + count_cycles;
}
/* 26 (4/2) */
/* 4 4,0   */

/* MOVE.L #<data>.L,(An) */
uae_u32 REGPARAM2 op_20bc_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 20; 
	uae_s32 src;
	src = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	if (dsta & 1) {
		m68k_incpci(8);
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	put_word_000(dsta + 2, src); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		ccr_68000_long_move_ae_LZN(src);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (3/2) */
/* 6 0,0   */

/* MOVE.L Dn,(An)+ */
uae_u32 REGPARAM2 op_20c0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 12; 
	uae_s32 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	m68k_areg(regs, dstreg) += 4;
	if (dsta & 1) {
		m68k_incpci(4);
		m68k_areg(regs, dstreg) -= 4;
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, dstreg) -= 4;
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	put_word_000(dsta + 2, src); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		ccr_68000_long_move_ae_LZN(src);
		m68k_areg(regs, dstreg) -= 4;
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (1/2) */
/* 2 0,0   */

/* MOVE.L An,(An)+ */
uae_u32 REGPARAM2 op_20c8_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 12; 
	uae_s32 src = m68k_areg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	m68k_areg(regs, dstreg) += 4;
	if (dsta & 1) {
		m68k_incpci(4);
		m68k_areg(regs, dstreg) -= 4;
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, dstreg) -= 4;
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	put_word_000(dsta + 2, src); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		ccr_68000_long_move_ae_LZN(src);
		m68k_areg(regs, dstreg) -= 4;
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (1/2) */
/* 2 0,0   */

/* MOVE.L (An),(An)+ */
uae_u32 REGPARAM2 op_20d0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	m68k_areg(regs, dstreg) += 4;
	if (dsta & 1) {
		m68k_incpci(4);
		m68k_areg(regs, dstreg) -= 4;
		ccr_68000_long_move_ae_LZN(src);
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		ccr_68000_long_move_ae_LZN(src);
		m68k_areg(regs, dstreg) -= 4;
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	put_word_000(dsta + 2, src); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		ccr_68000_long_move_ae_normal(src);
		m68k_areg(regs, dstreg) -= 4;
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (3/2) */
/* 2 0,0   */

/* MOVE.L (An)+,(An)+ */
uae_u32 REGPARAM2 op_20d8_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) += 4;
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	m68k_areg(regs, dstreg) += 4;
	if (dsta & 1) {
		m68k_incpci(4);
		m68k_areg(regs, dstreg) -= 4;
		ccr_68000_long_move_ae_LZN(src);
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		ccr_68000_long_move_ae_LZN(src);
		m68k_areg(regs, dstreg) -= 4;
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	put_word_000(dsta + 2, src); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		ccr_68000_long_move_ae_normal(src);
		m68k_areg(regs, dstreg) -= 4;
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (3/2) */
/* 2 0,0   */

/* MOVE.L -(An),(An)+ */
uae_u32 REGPARAM2 op_20e0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 22; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - 4;
	if (srca & 1) {
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception3_read_access(opcode, srca, 2, 1);
		return 2 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) = srca;
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	m68k_areg(regs, dstreg) += 4;
	if (dsta & 1) {
		m68k_incpci(4);
		m68k_areg(regs, dstreg) -= 4;
		ccr_68000_long_move_ae_LZN(src);
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		ccr_68000_long_move_ae_LZN(src);
		m68k_areg(regs, dstreg) -= 4;
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	put_word_000(dsta + 2, src); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		ccr_68000_long_move_ae_normal(src);
		m68k_areg(regs, dstreg) -= 4;
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 22 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 22 * CYCLE_UNIT / 2 + count_cycles;
}
/* 22 (3/2) */
/* 2 0,0   */

/* MOVE.L (d16,An),(An)+ */
uae_u32 REGPARAM2 op_20e8_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 24; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	m68k_areg(regs, dstreg) += 4;
	if (dsta & 1) {
		m68k_incpci(6);
		m68k_areg(regs, dstreg) -= 4;
		ccr_68000_long_move_ae_LZN(src);
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		ccr_68000_long_move_ae_LZN(src);
		m68k_areg(regs, dstreg) -= 4;
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	put_word_000(dsta + 2, src); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		ccr_68000_long_move_ae_normal(src);
		m68k_areg(regs, dstreg) -= 4;
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 24 * CYCLE_UNIT / 2 + count_cycles;
}
/* 24 (4/2) */
/* 4 0,0   */

/* MOVE.L (d8,An,Xn),(An)+ */
uae_u32 REGPARAM2 op_20f0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 26; 
	uaecptr srca;
	BusCyclePenalty += 2;
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	m68k_areg(regs, dstreg) += 4;
	if (dsta & 1) {
		m68k_incpci(6);
		m68k_areg(regs, dstreg) -= 4;
		ccr_68000_long_move_ae_LZN(src);
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		ccr_68000_long_move_ae_LZN(src);
		m68k_areg(regs, dstreg) -= 4;
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	put_word_000(dsta + 2, src); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		ccr_68000_long_move_ae_normal(src);
		m68k_areg(regs, dstreg) -= 4;
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return 22 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 26 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 26 * CYCLE_UNIT / 2 + count_cycles;
}
/* 26 (4/2) */
/* 4 4,0   */

/* MOVE.L (xxx).W,(An)+ */
uae_u32 REGPARAM2 op_20f8_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 24; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, srca, 2, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	m68k_areg(regs, dstreg) += 4;
	if (dsta & 1) {
		m68k_incpci(6);
		m68k_areg(regs, dstreg) -= 4;
		ccr_68000_long_move_ae_LZN(src);
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		ccr_68000_long_move_ae_LZN(src);
		m68k_areg(regs, dstreg) -= 4;
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	put_word_000(dsta + 2, src); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		ccr_68000_long_move_ae_normal(src);
		m68k_areg(regs, dstreg) -= 4;
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 24 * CYCLE_UNIT / 2 + count_cycles;
}
/* 24 (4/2) */
/* 4 0,0   */

/* MOVE.L (xxx).L,(An)+ */
uae_u32 REGPARAM2 op_20f9_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 28; 
	uaecptr srca;
	srca = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	srca |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, srca, 2, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	m68k_areg(regs, dstreg) += 4;
	if (dsta & 1) {
		m68k_incpci(8);
		m68k_areg(regs, dstreg) -= 4;
		ccr_68000_long_move_ae_LZN(src);
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		ccr_68000_long_move_ae_LZN(src);
		m68k_areg(regs, dstreg) -= 4;
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	put_word_000(dsta + 2, src); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		ccr_68000_long_move_ae_normal(src);
		m68k_areg(regs, dstreg) -= 4;
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 28 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 28 * CYCLE_UNIT / 2 + count_cycles;
}
/* 28 (5/2) */
/* 6 0,0   */

/* MOVE.L (d16,PC),(An)+ */
uae_u32 REGPARAM2 op_20fa_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 24; 
	uaecptr srca;
	srca = m68k_getpci() + 2;
	srca += (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 2);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	m68k_areg(regs, dstreg) += 4;
	if (dsta & 1) {
		m68k_incpci(6);
		m68k_areg(regs, dstreg) -= 4;
		ccr_68000_long_move_ae_LZN(src);
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		ccr_68000_long_move_ae_LZN(src);
		m68k_areg(regs, dstreg) -= 4;
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	put_word_000(dsta + 2, src); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		ccr_68000_long_move_ae_normal(src);
		m68k_areg(regs, dstreg) -= 4;
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 24 * CYCLE_UNIT / 2 + count_cycles;
}
/* 24 (4/2) */
/* 4 0,0   */

/* MOVE.L (d8,PC,Xn),(An)+ */
uae_u32 REGPARAM2 op_20fb_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 26; 
	uaecptr srca;
	uaecptr tmppc = m68k_getpci() + 2;
	BusCyclePenalty += 2;
	srca = get_disp_ea_000(tmppc, get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 2);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	m68k_areg(regs, dstreg) += 4;
	if (dsta & 1) {
		m68k_incpci(6);
		m68k_areg(regs, dstreg) -= 4;
		ccr_68000_long_move_ae_LZN(src);
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		ccr_68000_long_move_ae_LZN(src);
		m68k_areg(regs, dstreg) -= 4;
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	put_word_000(dsta + 2, src); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		ccr_68000_long_move_ae_normal(src);
		m68k_areg(regs, dstreg) -= 4;
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return 22 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 26 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 26 * CYCLE_UNIT / 2 + count_cycles;
}
/* 26 (4/2) */
/* 4 4,0   */

/* MOVE.L #<data>.L,(An)+ */
uae_u32 REGPARAM2 op_20fc_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 20; 
	uae_s32 src;
	src = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	m68k_areg(regs, dstreg) += 4;
	if (dsta & 1) {
		m68k_incpci(8);
		m68k_areg(regs, dstreg) -= 4;
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		m68k_areg(regs, dstreg) -= 4;
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	put_word_000(dsta + 2, src); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		ccr_68000_long_move_ae_LZN(src);
		m68k_areg(regs, dstreg) -= 4;
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (3/2) */
/* 6 0,0   */

/* MOVE.L Dn,-(An) */
uae_u32 REGPARAM2 op_2100_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 12; 
	uae_s32 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - 4;
	m68k_areg(regs, dstreg) = dsta;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		m68k_areg(regs, dstreg) += 4;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(4);
		count_cycles += 2 * CYCLE_UNIT / 2;
		m68k_areg(regs, dstreg) += 4;
		regs.ir = opcode;
		ccr_68000_long_move_ae_normal(src);
		dsta += 2;
		exception3_write_access(opcode, dsta, 2, src, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		ccr_68000_long_move_ae_normal(src);
		m68k_areg(regs, dstreg) += 4;
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	put_word_000(dsta, src >> 16); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		ccr_68000_long_move_ae_normal(src);
		m68k_areg(regs, dstreg) += 4;
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12+ (1/2) */
/* 2 0,0   */

/* MOVE.L An,-(An) */
uae_u32 REGPARAM2 op_2108_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 12; 
	uae_s32 src = m68k_areg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - 4;
	m68k_areg(regs, dstreg) = dsta;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		m68k_areg(regs, dstreg) += 4;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(4);
		count_cycles += 2 * CYCLE_UNIT / 2;
		m68k_areg(regs, dstreg) += 4;
		regs.ir = opcode;
		ccr_68000_long_move_ae_normal(src);
		dsta += 2;
		exception3_write_access(opcode, dsta, 2, src, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		ccr_68000_long_move_ae_normal(src);
		m68k_areg(regs, dstreg) += 4;
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	put_word_000(dsta, src >> 16); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		ccr_68000_long_move_ae_normal(src);
		m68k_areg(regs, dstreg) += 4;
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12+ (1/2) */
/* 2 0,0   */

/* MOVE.L (An),-(An) */
uae_u32 REGPARAM2 op_2110_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - 4;
	m68k_areg(regs, dstreg) = dsta;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		m68k_areg(regs, dstreg) += 4;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(4);
		count_cycles += 2 * CYCLE_UNIT / 2;
		m68k_areg(regs, dstreg) += 4;
		regs.ir = opcode;
		ccr_68000_long_move_ae_normal(src);
		dsta += 2;
		exception3_write_access(opcode, dsta, 2, src, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		ccr_68000_long_move_ae_normal(src);
		m68k_areg(regs, dstreg) += 4;
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	put_word_000(dsta, src >> 16); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		ccr_68000_long_move_ae_normal(src);
		m68k_areg(regs, dstreg) += 4;
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20+ (3/2) */
/* 2 0,0   */

/* MOVE.L (An)+,-(An) */
uae_u32 REGPARAM2 op_2118_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) += 4;
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - 4;
	m68k_areg(regs, dstreg) = dsta;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		m68k_areg(regs, dstreg) += 4;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(4);
		count_cycles += 2 * CYCLE_UNIT / 2;
		m68k_areg(regs, dstreg) += 4;
		regs.ir = opcode;
		ccr_68000_long_move_ae_normal(src);
		dsta += 2;
		exception3_write_access(opcode, dsta, 2, src, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		ccr_68000_long_move_ae_normal(src);
		m68k_areg(regs, dstreg) += 4;
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	put_word_000(dsta, src >> 16); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		ccr_68000_long_move_ae_normal(src);
		m68k_areg(regs, dstreg) += 4;
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20+ (3/2) */
/* 2 0,0   */

/* MOVE.L -(An),-(An) */
uae_u32 REGPARAM2 op_2120_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 22; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - 4;
	if (srca & 1) {
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception3_read_access(opcode, srca, 2, 1);
		return 2 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) = srca;
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - 4;
	m68k_areg(regs, dstreg) = dsta;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		m68k_areg(regs, dstreg) += 4;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(4);
		count_cycles += 2 * CYCLE_UNIT / 2;
		m68k_areg(regs, dstreg) += 4;
		regs.ir = opcode;
		ccr_68000_long_move_ae_normal(src);
		dsta += 2;
		exception3_write_access(opcode, dsta, 2, src, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		ccr_68000_long_move_ae_normal(src);
		m68k_areg(regs, dstreg) += 4;
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	put_word_000(dsta, src >> 16); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		ccr_68000_long_move_ae_normal(src);
		m68k_areg(regs, dstreg) += 4;
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return 22 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 22 * CYCLE_UNIT / 2 + count_cycles;
}
/* 22+ (3/2) */
/* 2 0,0   */

/* MOVE.L (d16,An),-(An) */
uae_u32 REGPARAM2 op_2128_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 24; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - 4;
	m68k_areg(regs, dstreg) = dsta;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		m68k_areg(regs, dstreg) += 4;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(6);
		count_cycles += 2 * CYCLE_UNIT / 2;
		m68k_areg(regs, dstreg) += 4;
		regs.ir = opcode;
		ccr_68000_long_move_ae_normal(src);
		dsta += 2;
		exception3_write_access(opcode, dsta, 2, src, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		ccr_68000_long_move_ae_normal(src);
		m68k_areg(regs, dstreg) += 4;
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	put_word_000(dsta, src >> 16); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		ccr_68000_long_move_ae_normal(src);
		m68k_areg(regs, dstreg) += 4;
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 24 * CYCLE_UNIT / 2 + count_cycles;
}
/* 24+ (4/2) */
/* 4 0,0   */

/* MOVE.L (d8,An,Xn),-(An) */
uae_u32 REGPARAM2 op_2130_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 26; 
	uaecptr srca;
	BusCyclePenalty += 2;
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - 4;
	m68k_areg(regs, dstreg) = dsta;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		m68k_areg(regs, dstreg) += 4;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(6);
		count_cycles += 2 * CYCLE_UNIT / 2;
		m68k_areg(regs, dstreg) += 4;
		regs.ir = opcode;
		ccr_68000_long_move_ae_normal(src);
		dsta += 2;
		exception3_write_access(opcode, dsta, 2, src, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		ccr_68000_long_move_ae_normal(src);
		m68k_areg(regs, dstreg) += 4;
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return 22 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	put_word_000(dsta, src >> 16); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		ccr_68000_long_move_ae_normal(src);
		m68k_areg(regs, dstreg) += 4;
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return 26 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 26 * CYCLE_UNIT / 2 + count_cycles;
}
/* 26+ (4/2) */
/* 4 4,0   */

/* MOVE.L (xxx).W,-(An) */
uae_u32 REGPARAM2 op_2138_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 24; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, srca, 2, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - 4;
	m68k_areg(regs, dstreg) = dsta;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		m68k_areg(regs, dstreg) += 4;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(6);
		count_cycles += 2 * CYCLE_UNIT / 2;
		m68k_areg(regs, dstreg) += 4;
		regs.ir = opcode;
		ccr_68000_long_move_ae_normal(src);
		dsta += 2;
		exception3_write_access(opcode, dsta, 2, src, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		ccr_68000_long_move_ae_normal(src);
		m68k_areg(regs, dstreg) += 4;
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	put_word_000(dsta, src >> 16); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		ccr_68000_long_move_ae_normal(src);
		m68k_areg(regs, dstreg) += 4;
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 24 * CYCLE_UNIT / 2 + count_cycles;
}
/* 24+ (4/2) */
/* 4 0,0   */

/* MOVE.L (xxx).L,-(An) */
uae_u32 REGPARAM2 op_2139_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 28; 
	uaecptr srca;
	srca = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	srca |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, srca, 2, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - 4;
	m68k_areg(regs, dstreg) = dsta;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		m68k_areg(regs, dstreg) += 4;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(8);
		count_cycles += 2 * CYCLE_UNIT / 2;
		m68k_areg(regs, dstreg) += 4;
		regs.ir = opcode;
		ccr_68000_long_move_ae_normal(src);
		dsta += 2;
		exception3_write_access(opcode, dsta, 2, src, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		ccr_68000_long_move_ae_normal(src);
		m68k_areg(regs, dstreg) += 4;
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	put_word_000(dsta, src >> 16); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		ccr_68000_long_move_ae_normal(src);
		m68k_areg(regs, dstreg) += 4;
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return 28 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 28 * CYCLE_UNIT / 2 + count_cycles;
}
/* 28+ (5/2) */
/* 6 0,0   */

/* MOVE.L (d16,PC),-(An) */
uae_u32 REGPARAM2 op_213a_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 24; 
	uaecptr srca;
	srca = m68k_getpci() + 2;
	srca += (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 2);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - 4;
	m68k_areg(regs, dstreg) = dsta;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		m68k_areg(regs, dstreg) += 4;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(6);
		count_cycles += 2 * CYCLE_UNIT / 2;
		m68k_areg(regs, dstreg) += 4;
		regs.ir = opcode;
		ccr_68000_long_move_ae_normal(src);
		dsta += 2;
		exception3_write_access(opcode, dsta, 2, src, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		ccr_68000_long_move_ae_normal(src);
		m68k_areg(regs, dstreg) += 4;
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	put_word_000(dsta, src >> 16); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		ccr_68000_long_move_ae_normal(src);
		m68k_areg(regs, dstreg) += 4;
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 24 * CYCLE_UNIT / 2 + count_cycles;
}
/* 24+ (4/2) */
/* 4 0,0   */

/* MOVE.L (d8,PC,Xn),-(An) */
uae_u32 REGPARAM2 op_213b_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 26; 
	uaecptr srca;
	uaecptr tmppc = m68k_getpci() + 2;
	BusCyclePenalty += 2;
	srca = get_disp_ea_000(tmppc, get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 2);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - 4;
	m68k_areg(regs, dstreg) = dsta;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		m68k_areg(regs, dstreg) += 4;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(6);
		count_cycles += 2 * CYCLE_UNIT / 2;
		m68k_areg(regs, dstreg) += 4;
		regs.ir = opcode;
		ccr_68000_long_move_ae_normal(src);
		dsta += 2;
		exception3_write_access(opcode, dsta, 2, src, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		ccr_68000_long_move_ae_normal(src);
		m68k_areg(regs, dstreg) += 4;
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return 22 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	put_word_000(dsta, src >> 16); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		ccr_68000_long_move_ae_normal(src);
		m68k_areg(regs, dstreg) += 4;
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return 26 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 26 * CYCLE_UNIT / 2 + count_cycles;
}
/* 26+ (4/2) */
/* 4 4,0   */

/* MOVE.L #<data>.L,-(An) */
uae_u32 REGPARAM2 op_213c_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 20; 
	uae_s32 src;
	src = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - 4;
	m68k_areg(regs, dstreg) = dsta;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		m68k_areg(regs, dstreg) += 4;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(8);
		count_cycles += 2 * CYCLE_UNIT / 2;
		m68k_areg(regs, dstreg) += 4;
		regs.ir = opcode;
		ccr_68000_long_move_ae_normal(src);
		dsta += 2;
		exception3_write_access(opcode, dsta, 2, src, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		ccr_68000_long_move_ae_normal(src);
		m68k_areg(regs, dstreg) += 4;
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	put_word_000(dsta, src >> 16); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		ccr_68000_long_move_ae_normal(src);
		m68k_areg(regs, dstreg) += 4;
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20+ (3/2) */
/* 6 0,0   */

/* MOVE.L Dn,(d16,An) */
uae_u32 REGPARAM2 op_2140_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 16; 
	uae_s32 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(4);
		ccr_68000_long_move_ae_HNZ(src);
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		SET_NFLG(src < 0);
		if((src & 0xffff0000)) SET_ZFLG(0);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	put_word_000(dsta + 2, src); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		ccr_68000_long_move_ae_LZN(src);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (2/2) */
/* 4 0,0   */

/* MOVE.L An,(d16,An) */
uae_u32 REGPARAM2 op_2148_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 16; 
	uae_s32 src = m68k_areg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(4);
		ccr_68000_long_move_ae_HNZ(src);
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		SET_NFLG(src < 0);
		if((src & 0xffff0000)) SET_ZFLG(0);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	put_word_000(dsta + 2, src); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		ccr_68000_long_move_ae_LZN(src);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (2/2) */
/* 4 0,0   */

/* MOVE.L (An),(d16,An) */
uae_u32 REGPARAM2 op_2150_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 24; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch(opcode, 4, 0);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(4);
		ccr_68000_long_move_ae_normal(src);
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	put_word_000(dsta + 2, src); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 24 * CYCLE_UNIT / 2 + count_cycles;
}
/* 24 (4/2) */
/* 4 0,0   */

/* MOVE.L (An)+,(d16,An) */
uae_u32 REGPARAM2 op_2158_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 24; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) += 4;
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch(opcode, 4, 0);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(4);
		ccr_68000_long_move_ae_normal(src);
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	put_word_000(dsta + 2, src); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 24 * CYCLE_UNIT / 2 + count_cycles;
}
/* 24 (4/2) */
/* 4 0,0   */

/* MOVE.L -(An),(d16,An) */
uae_u32 REGPARAM2 op_2160_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 26; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - 4;
	if (srca & 1) {
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception3_read_access(opcode, srca, 2, 1);
		return 2 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) = srca;
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch(opcode, 4, 0);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(4);
		ccr_68000_long_move_ae_normal(src);
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	put_word_000(dsta + 2, src); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return 22 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 26 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 26 * CYCLE_UNIT / 2 + count_cycles;
}
/* 26 (4/2) */
/* 4 0,0   */

/* MOVE.L (d16,An),(d16,An) */
uae_u32 REGPARAM2 op_2168_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 28; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch(opcode, 6, 0);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(6);
		ccr_68000_long_move_ae_normal(src);
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	put_word_000(dsta + 2, src); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 28 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 28 * CYCLE_UNIT / 2 + count_cycles;
}
/* 28 (5/2) */
/* 6 0,0   */

/* MOVE.L (d8,An,Xn),(d16,An) */
uae_u32 REGPARAM2 op_2170_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 30; 
	uaecptr srca;
	BusCyclePenalty += 2;
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch(opcode, 6, 0);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(6);
		ccr_68000_long_move_ae_normal(src);
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return 22 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	put_word_000(dsta + 2, src); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return 26 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 30 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 30 * CYCLE_UNIT / 2 + count_cycles;
}
/* 30 (5/2) */
/* 6 6,0   */

/* MOVE.L (xxx).W,(d16,An) */
uae_u32 REGPARAM2 op_2178_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 28; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, srca, 2, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch(opcode, 6, 0);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(6);
		ccr_68000_long_move_ae_normal(src);
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	put_word_000(dsta + 2, src); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 28 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 28 * CYCLE_UNIT / 2 + count_cycles;
}
/* 28 (5/2) */
/* 6 0,0   */

/* MOVE.L (xxx).L,(d16,An) */
uae_u32 REGPARAM2 op_2179_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 32; 
	uaecptr srca;
	srca = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	srca |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, srca, 2, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch(opcode, 8, 0);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(8);
		ccr_68000_long_move_ae_normal(src);
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	put_word_000(dsta + 2, src); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return 28 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(8);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 32 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 32 * CYCLE_UNIT / 2 + count_cycles;
}
/* 32 (6/2) */
/* 8 0,0   */

/* MOVE.L (d16,PC),(d16,An) */
uae_u32 REGPARAM2 op_217a_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 28; 
	uaecptr srca;
	srca = m68k_getpci() + 2;
	srca += (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 2);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch(opcode, 6, 0);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(6);
		ccr_68000_long_move_ae_normal(src);
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	put_word_000(dsta + 2, src); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 28 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 28 * CYCLE_UNIT / 2 + count_cycles;
}
/* 28 (5/2) */
/* 6 0,0   */

/* MOVE.L (d8,PC,Xn),(d16,An) */
uae_u32 REGPARAM2 op_217b_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 30; 
	uaecptr srca;
	uaecptr tmppc = m68k_getpci() + 2;
	BusCyclePenalty += 2;
	srca = get_disp_ea_000(tmppc, get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 2);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch(opcode, 6, 0);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(6);
		ccr_68000_long_move_ae_normal(src);
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return 22 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	put_word_000(dsta + 2, src); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return 26 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 30 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 30 * CYCLE_UNIT / 2 + count_cycles;
}
/* 30 (5/2) */
/* 6 6,0   */

/* MOVE.L #<data>.L,(d16,An) */
uae_u32 REGPARAM2 op_217c_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 24; 
	uae_s32 src;
	src = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 8, 0);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(8);
		ccr_68000_long_move_ae_HNZ(src);
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		ccr_68000_long_move_ae_HNZ(src);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	put_word_000(dsta + 2, src); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		ccr_68000_long_move_ae_LZN(src);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(8);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 24 * CYCLE_UNIT / 2 + count_cycles;
}
/* 24 (4/2) */
/* 8 0,0   */

/* MOVE.L Dn,(d8,An,Xn) */
uae_u32 REGPARAM2 op_2180_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 18; 
	uae_s32 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	BusCyclePenalty += 2;
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(4);
		ccr_68000_long_move_ae_HNZ(src);
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		SET_NFLG(src < 0);
		if((src & 0xffff0000)) SET_ZFLG(0);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	put_word_000(dsta + 2, src); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		ccr_68000_long_move_ae_LZN(src);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (2/2) */
/* 4 4,0   */

/* MOVE.L An,(d8,An,Xn) */
uae_u32 REGPARAM2 op_2188_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 18; 
	uae_s32 src = m68k_areg(regs, srcreg);
	uaecptr dsta;
	BusCyclePenalty += 2;
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(4);
		ccr_68000_long_move_ae_HNZ(src);
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		SET_NFLG(src < 0);
		if((src & 0xffff0000)) SET_ZFLG(0);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	put_word_000(dsta + 2, src); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		ccr_68000_long_move_ae_LZN(src);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (2/2) */
/* 4 4,0   */

/* MOVE.L (An),(d8,An,Xn) */
uae_u32 REGPARAM2 op_2190_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 26; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	BusCyclePenalty += 2;
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch(opcode, 4, 0);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(4);
		ccr_68000_long_move_ae_normal(src);
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	put_word_000(dsta + 2, src); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return 22 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 26 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 26 * CYCLE_UNIT / 2 + count_cycles;
}
/* 26 (4/2) */
/* 4 4,0   */

/* MOVE.L (An)+,(d8,An,Xn) */
uae_u32 REGPARAM2 op_2198_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 26; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) += 4;
	uaecptr dsta;
	BusCyclePenalty += 2;
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch(opcode, 4, 0);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(4);
		ccr_68000_long_move_ae_normal(src);
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	put_word_000(dsta + 2, src); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return 22 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 26 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 26 * CYCLE_UNIT / 2 + count_cycles;
}
/* 26 (4/2) */
/* 4 4,0   */

/* MOVE.L -(An),(d8,An,Xn) */
uae_u32 REGPARAM2 op_21a0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 28; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - 4;
	if (srca & 1) {
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception3_read_access(opcode, srca, 2, 1);
		return 2 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) = srca;
	uaecptr dsta;
	BusCyclePenalty += 2;
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch(opcode, 4, 0);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(4);
		ccr_68000_long_move_ae_normal(src);
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	put_word_000(dsta + 2, src); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 28 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 28 * CYCLE_UNIT / 2 + count_cycles;
}
/* 28 (4/2) */
/* 4 4,0   */

/* MOVE.L (d16,An),(d8,An,Xn) */
uae_u32 REGPARAM2 op_21a8_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 30; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	BusCyclePenalty += 2;
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_000_prefetch(6));
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch(opcode, 6, 0);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(6);
		ccr_68000_long_move_ae_normal(src);
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return 22 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	put_word_000(dsta + 2, src); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return 26 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 30 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 30 * CYCLE_UNIT / 2 + count_cycles;
}
/* 30 (5/2) */
/* 6 4,0   */

/* MOVE.L (d8,An,Xn),(d8,An,Xn) */
uae_u32 REGPARAM2 op_21b0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 32; 
	uaecptr srca;
	BusCyclePenalty += 2;
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	BusCyclePenalty += 2;
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_000_prefetch(6));
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch(opcode, 6, 0);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(6);
		ccr_68000_long_move_ae_normal(src);
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	put_word_000(dsta + 2, src); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return 28 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 32 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 32 * CYCLE_UNIT / 2 + count_cycles;
}
/* 32 (5/2) */
/* 6 6,4   */

/* MOVE.L (xxx).W,(d8,An,Xn) */
uae_u32 REGPARAM2 op_21b8_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 30; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, srca, 2, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	BusCyclePenalty += 2;
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_000_prefetch(6));
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch(opcode, 6, 0);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(6);
		ccr_68000_long_move_ae_normal(src);
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return 22 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	put_word_000(dsta + 2, src); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return 26 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 30 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 30 * CYCLE_UNIT / 2 + count_cycles;
}
/* 30 (5/2) */
/* 6 4,0   */

/* MOVE.L (xxx).L,(d8,An,Xn) */
uae_u32 REGPARAM2 op_21b9_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 34; 
	uaecptr srca;
	srca = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	srca |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, srca, 2, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	BusCyclePenalty += 2;
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_000_prefetch(8));
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch(opcode, 8, 0);
		return 22 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(8);
		ccr_68000_long_move_ae_normal(src);
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return 22 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return 26 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	put_word_000(dsta + 2, src); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return 30 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(8);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 34 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 34 * CYCLE_UNIT / 2 + count_cycles;
}
/* 34 (6/2) */
/* 8 4,0   */

/* MOVE.L (d16,PC),(d8,An,Xn) */
uae_u32 REGPARAM2 op_21ba_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 30; 
	uaecptr srca;
	srca = m68k_getpci() + 2;
	srca += (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 2);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	BusCyclePenalty += 2;
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_000_prefetch(6));
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch(opcode, 6, 0);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(6);
		ccr_68000_long_move_ae_normal(src);
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return 22 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	put_word_000(dsta + 2, src); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return 26 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 30 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 30 * CYCLE_UNIT / 2 + count_cycles;
}
/* 30 (5/2) */
/* 6 4,0   */

/* MOVE.L (d8,PC,Xn),(d8,An,Xn) */
uae_u32 REGPARAM2 op_21bb_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 32; 
	uaecptr srca;
	uaecptr tmppc = m68k_getpci() + 2;
	BusCyclePenalty += 2;
	srca = get_disp_ea_000(tmppc, get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 2);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	BusCyclePenalty += 2;
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_000_prefetch(6));
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch(opcode, 6, 0);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(6);
		ccr_68000_long_move_ae_normal(src);
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	put_word_000(dsta + 2, src); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return 28 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 32 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 32 * CYCLE_UNIT / 2 + count_cycles;
}
/* 32 (5/2) */
/* 6 6,4   */

/* MOVE.L #<data>.L,(d8,An,Xn) */
uae_u32 REGPARAM2 op_21bc_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 26; 
	uae_s32 src;
	src = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	BusCyclePenalty += 2;
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_000_prefetch(8));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 8, 0);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(8);
		ccr_68000_long_move_ae_HNZ(src);
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		ccr_68000_long_move_ae_HNZ(src);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	put_word_000(dsta + 2, src); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		ccr_68000_long_move_ae_LZN(src);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return 22 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(8);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 26 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 26 * CYCLE_UNIT / 2 + count_cycles;
}
/* 26 (4/2) */
/* 8 4,0   */

/* MOVE.L Dn,(xxx).W */
uae_u32 REGPARAM2 op_21c0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 30;
	CurrentInstrCycles = 16; 
	uae_s32 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(4);
		ccr_68000_long_move_ae_normal(src);
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	put_word_000(dsta + 2, src); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (2/2) */
/* 4 0,0   */

/* MOVE.L An,(xxx).W */
uae_u32 REGPARAM2 op_21c8_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 30;
	CurrentInstrCycles = 16; 
	uae_s32 src = m68k_areg(regs, srcreg);
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(4);
		ccr_68000_long_move_ae_normal(src);
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	put_word_000(dsta + 2, src); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (2/2) */
/* 4 0,0   */

/* MOVE.L (An),(xxx).W */
uae_u32 REGPARAM2 op_21d0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 30;
	CurrentInstrCycles = 24; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch(opcode, 4, 0);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(4);
		ccr_68000_long_move_ae_normal(src);
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		ccr_68000_long_move_ae_LZN(src);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	put_word_000(dsta + 2, src); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 24 * CYCLE_UNIT / 2 + count_cycles;
}
/* 24 (4/2) */
/* 4 0,0   */

/* MOVE.L (An)+,(xxx).W */
uae_u32 REGPARAM2 op_21d8_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 30;
	CurrentInstrCycles = 24; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) += 4;
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch(opcode, 4, 0);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(4);
		ccr_68000_long_move_ae_normal(src);
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		ccr_68000_long_move_ae_LZN(src);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	put_word_000(dsta + 2, src); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 24 * CYCLE_UNIT / 2 + count_cycles;
}
/* 24 (4/2) */
/* 4 0,0   */

/* MOVE.L -(An),(xxx).W */
uae_u32 REGPARAM2 op_21e0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 30;
	CurrentInstrCycles = 26; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - 4;
	if (srca & 1) {
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception3_read_access(opcode, srca, 2, 1);
		return 2 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) = srca;
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch(opcode, 4, 0);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(4);
		ccr_68000_long_move_ae_normal(src);
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		ccr_68000_long_move_ae_LZN(src);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	put_word_000(dsta + 2, src); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return 22 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 26 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 26 * CYCLE_UNIT / 2 + count_cycles;
}
/* 26 (4/2) */
/* 4 0,0   */

/* MOVE.L (d16,An),(xxx).W */
uae_u32 REGPARAM2 op_21e8_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 30;
	CurrentInstrCycles = 28; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch(opcode, 6, 0);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(6);
		ccr_68000_long_move_ae_normal(src);
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		ccr_68000_long_move_ae_LZN(src);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	put_word_000(dsta + 2, src); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 28 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 28 * CYCLE_UNIT / 2 + count_cycles;
}
/* 28 (5/2) */
/* 6 0,0   */

/* MOVE.L (d8,An,Xn),(xxx).W */
uae_u32 REGPARAM2 op_21f0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 30;
	CurrentInstrCycles = 30; 
	uaecptr srca;
	BusCyclePenalty += 2;
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch(opcode, 6, 0);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(6);
		ccr_68000_long_move_ae_normal(src);
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		ccr_68000_long_move_ae_LZN(src);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return 22 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	put_word_000(dsta + 2, src); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return 26 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 30 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 30 * CYCLE_UNIT / 2 + count_cycles;
}
/* 30 (5/2) */
/* 6 6,0   */

/* MOVE.L (xxx).W,(xxx).W */
uae_u32 REGPARAM2 op_21f8_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 30;
	CurrentInstrCycles = 28; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, srca, 2, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch(opcode, 6, 0);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(6);
		ccr_68000_long_move_ae_normal(src);
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		ccr_68000_long_move_ae_LZN(src);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	put_word_000(dsta + 2, src); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 28 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 28 * CYCLE_UNIT / 2 + count_cycles;
}
/* 28 (5/2) */
/* 6 0,0   */

/* MOVE.L (xxx).L,(xxx).W */
uae_u32 REGPARAM2 op_21f9_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 30;
	CurrentInstrCycles = 32; 
	uaecptr srca;
	srca = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	srca |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, srca, 2, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch(opcode, 8, 0);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(8);
		ccr_68000_long_move_ae_normal(src);
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		ccr_68000_long_move_ae_LZN(src);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	put_word_000(dsta + 2, src); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return 28 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(8);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 32 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 32 * CYCLE_UNIT / 2 + count_cycles;
}
/* 32 (6/2) */
/* 8 0,0   */

/* MOVE.L (d16,PC),(xxx).W */
uae_u32 REGPARAM2 op_21fa_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 30;
	CurrentInstrCycles = 28; 
	uaecptr srca;
	srca = m68k_getpci() + 2;
	srca += (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 2);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch(opcode, 6, 0);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(6);
		ccr_68000_long_move_ae_normal(src);
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		ccr_68000_long_move_ae_LZN(src);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	put_word_000(dsta + 2, src); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 28 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 28 * CYCLE_UNIT / 2 + count_cycles;
}
/* 28 (5/2) */
/* 6 0,0   */

/* MOVE.L (d8,PC,Xn),(xxx).W */
uae_u32 REGPARAM2 op_21fb_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 30;
	CurrentInstrCycles = 30; 
	uaecptr srca;
	uaecptr tmppc = m68k_getpci() + 2;
	BusCyclePenalty += 2;
	srca = get_disp_ea_000(tmppc, get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 2);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch(opcode, 6, 0);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(6);
		ccr_68000_long_move_ae_normal(src);
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		ccr_68000_long_move_ae_LZN(src);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return 22 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	put_word_000(dsta + 2, src); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return 26 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 30 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 30 * CYCLE_UNIT / 2 + count_cycles;
}
/* 30 (5/2) */
/* 6 6,0   */

/* MOVE.L #<data>.L,(xxx).W */
uae_u32 REGPARAM2 op_21fc_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 30;
	CurrentInstrCycles = 24; 
	uae_s32 src;
	src = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch(opcode, 8, 0);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(8);
		ccr_68000_long_move_ae_normal(src);
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	put_word_000(dsta + 2, src); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(8);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 24 * CYCLE_UNIT / 2 + count_cycles;
}
/* 24 (4/2) */
/* 8 0,0   */

/* MOVE.L Dn,(xxx).L */
uae_u32 REGPARAM2 op_23c0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 30;
	CurrentInstrCycles = 20; 
	uae_s32 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		// nothing;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	dsta |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(6);
		ccr_68000_long_move_ae_normal(src);
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	put_word_000(dsta + 2, src); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (3/2) */
/* 6 0,0   */

/* MOVE.L An,(xxx).L */
uae_u32 REGPARAM2 op_23c8_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 30;
	CurrentInstrCycles = 20; 
	uae_s32 src = m68k_areg(regs, srcreg);
	uaecptr dsta;
	dsta = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		// nothing;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	dsta |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(6);
		ccr_68000_long_move_ae_normal(src);
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	put_word_000(dsta + 2, src); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (3/2) */
/* 6 0,0   */

/* MOVE.L (An),(xxx).L */
uae_u32 REGPARAM2 op_23d0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 30;
	CurrentInstrCycles = 28; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = get_word_000_prefetch(4) << 16;
	dsta |= regs.irc;
	if(hardware_bus_error) {
		int pcoffset = 0;
		// nothing;
		exception2_fetch(opcode, 4, 0);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(4);
		ccr_68000_long_move_ae_LZN(src);
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		ccr_68000_long_move_ae_LZN(src);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	put_word_000(dsta + 2, src); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	get_word_000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, 0);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	if(regs.t1) opcode |= 0x10000;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 28 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 28 * CYCLE_UNIT / 2 + count_cycles;
}
/* 28 (5/2) */
/* 6 0,0   */

/* MOVE.L (An)+,(xxx).L */
uae_u32 REGPARAM2 op_23d8_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 30;
	CurrentInstrCycles = 28; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) += 4;
	uaecptr dsta;
	dsta = get_word_000_prefetch(4) << 16;
	dsta |= regs.irc;
	if(hardware_bus_error) {
		int pcoffset = 0;
		// nothing;
		exception2_fetch(opcode, 4, 0);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(4);
		ccr_68000_long_move_ae_LZN(src);
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		ccr_68000_long_move_ae_LZN(src);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	put_word_000(dsta + 2, src); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	get_word_000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, 0);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	if(regs.t1) opcode |= 0x10000;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 28 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 28 * CYCLE_UNIT / 2 + count_cycles;
}
/* 28 (5/2) */
/* 6 0,0   */

/* MOVE.L -(An),(xxx).L */
uae_u32 REGPARAM2 op_23e0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 30;
	CurrentInstrCycles = 30; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - 4;
	if (srca & 1) {
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception3_read_access(opcode, srca, 2, 1);
		return 2 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) = srca;
	uaecptr dsta;
	dsta = get_word_000_prefetch(4) << 16;
	dsta |= regs.irc;
	if(hardware_bus_error) {
		int pcoffset = 0;
		// nothing;
		exception2_fetch(opcode, 4, 0);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(4);
		ccr_68000_long_move_ae_LZN(src);
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		ccr_68000_long_move_ae_LZN(src);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	put_word_000(dsta + 2, src); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return 22 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	get_word_000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, 0);
		return 26 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	if(regs.t1) opcode |= 0x10000;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 30 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 30 * CYCLE_UNIT / 2 + count_cycles;
}
/* 30 (5/2) */
/* 6 0,0   */

/* MOVE.L (d16,An),(xxx).L */
uae_u32 REGPARAM2 op_23e8_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 30;
	CurrentInstrCycles = 32; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = get_word_000_prefetch(6) << 16;
	dsta |= regs.irc;
	if(hardware_bus_error) {
		int pcoffset = 0;
		// nothing;
		exception2_fetch(opcode, 6, 0);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(6);
		ccr_68000_long_move_ae_LZN(src);
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		ccr_68000_long_move_ae_LZN(src);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	put_word_000(dsta + 2, src); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(8);
	get_word_000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, 0);
		return 28 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	if(regs.t1) opcode |= 0x10000;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 32 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 32 * CYCLE_UNIT / 2 + count_cycles;
}
/* 32 (6/2) */
/* 8 0,0   */

/* MOVE.L (d8,An,Xn),(xxx).L */
uae_u32 REGPARAM2 op_23f0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 30;
	CurrentInstrCycles = 34; 
	uaecptr srca;
	BusCyclePenalty += 2;
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = get_word_000_prefetch(6) << 16;
	dsta |= regs.irc;
	if(hardware_bus_error) {
		int pcoffset = 0;
		// nothing;
		exception2_fetch(opcode, 6, 0);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(6);
		ccr_68000_long_move_ae_LZN(src);
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		ccr_68000_long_move_ae_LZN(src);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return 22 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	put_word_000(dsta + 2, src); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return 26 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(8);
	get_word_000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, 0);
		return 30 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	if(regs.t1) opcode |= 0x10000;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 34 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 34 * CYCLE_UNIT / 2 + count_cycles;
}
/* 34 (6/2) */
/* 8 8,0   */

/* MOVE.L (xxx).W,(xxx).L */
uae_u32 REGPARAM2 op_23f8_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 30;
	CurrentInstrCycles = 32; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, srca, 2, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = get_word_000_prefetch(6) << 16;
	dsta |= regs.irc;
	if(hardware_bus_error) {
		int pcoffset = 0;
		// nothing;
		exception2_fetch(opcode, 6, 0);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(6);
		ccr_68000_long_move_ae_LZN(src);
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		ccr_68000_long_move_ae_LZN(src);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	put_word_000(dsta + 2, src); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(8);
	get_word_000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, 0);
		return 28 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	if(regs.t1) opcode |= 0x10000;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 32 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 32 * CYCLE_UNIT / 2 + count_cycles;
}
/* 32 (6/2) */
/* 8 0,0   */

/* MOVE.L (xxx).L,(xxx).L */
uae_u32 REGPARAM2 op_23f9_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 30;
	CurrentInstrCycles = 36; 
	uaecptr srca;
	srca = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	srca |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, srca, 2, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = get_word_000_prefetch(8) << 16;
	dsta |= regs.irc;
	if(hardware_bus_error) {
		int pcoffset = 0;
		// nothing;
		exception2_fetch(opcode, 8, 0);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(8);
		ccr_68000_long_move_ae_LZN(src);
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		ccr_68000_long_move_ae_LZN(src);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	put_word_000(dsta + 2, src); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return 28 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(10);
	get_word_000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, 0);
		return 32 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	if(regs.t1) opcode |= 0x10000;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 36 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 36 * CYCLE_UNIT / 2 + count_cycles;
}
/* 36 (7/2) */
/* 10 0,0   */

/* MOVE.L (d16,PC),(xxx).L */
uae_u32 REGPARAM2 op_23fa_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 30;
	CurrentInstrCycles = 32; 
	uaecptr srca;
	srca = m68k_getpci() + 2;
	srca += (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 2);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = get_word_000_prefetch(6) << 16;
	dsta |= regs.irc;
	if(hardware_bus_error) {
		int pcoffset = 0;
		// nothing;
		exception2_fetch(opcode, 6, 0);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(6);
		ccr_68000_long_move_ae_LZN(src);
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		ccr_68000_long_move_ae_LZN(src);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	put_word_000(dsta + 2, src); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(8);
	get_word_000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, 0);
		return 28 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	if(regs.t1) opcode |= 0x10000;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 32 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 32 * CYCLE_UNIT / 2 + count_cycles;
}
/* 32 (6/2) */
/* 8 0,0   */

/* MOVE.L (d8,PC,Xn),(xxx).L */
uae_u32 REGPARAM2 op_23fb_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 30;
	CurrentInstrCycles = 34; 
	uaecptr srca;
	uaecptr tmppc = m68k_getpci() + 2;
	BusCyclePenalty += 2;
	srca = get_disp_ea_000(tmppc, get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 2);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = get_word_000_prefetch(6) << 16;
	dsta |= regs.irc;
	if(hardware_bus_error) {
		int pcoffset = 0;
		// nothing;
		exception2_fetch(opcode, 6, 0);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(6);
		ccr_68000_long_move_ae_LZN(src);
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		ccr_68000_long_move_ae_LZN(src);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return 22 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	put_word_000(dsta + 2, src); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return 26 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(8);
	get_word_000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, 0);
		return 30 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	if(regs.t1) opcode |= 0x10000;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 34 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 34 * CYCLE_UNIT / 2 + count_cycles;
}
/* 34 (6/2) */
/* 8 8,0   */

/* MOVE.L #<data>.L,(xxx).L */
uae_u32 REGPARAM2 op_23fc_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 30;
	CurrentInstrCycles = 28; 
	uae_s32 src;
	src = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = get_word_000_prefetch(8) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 8, -2);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	dsta |= get_word_000_prefetch(10);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch(opcode, 10, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(10);
		ccr_68000_long_move_ae_normal(src);
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(10);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	put_word_000(dsta + 2, src); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(10);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(10);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 28 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 28 * CYCLE_UNIT / 2 + count_cycles;
}
/* 28 (5/2) */
/* 10 0,0   */

/* MOVE.W Dn,Dn */
uae_u32 REGPARAM2 op_3000_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 4;  
	uae_s16 src = m68k_dreg(regs, srcreg);
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
	m68k_incpci(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 4 * CYCLE_UNIT / 2 + count_cycles;
}
/* 4 (1/0) */
/* 2 0,0   */

/* MOVE.W An,Dn */
uae_u32 REGPARAM2 op_3008_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 4;  
	uae_s16 src = m68k_areg(regs, srcreg);
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
	m68k_incpci(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 4 * CYCLE_UNIT / 2 + count_cycles;
}
/* 4 (1/0) */
/* 2 0,0   */

/* MOVE.W (An),Dn */
uae_u32 REGPARAM2 op_3010_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 8;  
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
	m68k_incpci(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8 (2/0) */
/* 2 0,0   */

/* MOVE.W (An)+,Dn */
uae_u32 REGPARAM2 op_3018_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 8;  
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) += 2 + 0;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) += 2;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
	m68k_incpci(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8 (2/0) */
/* 2 0,0   */

/* MOVE.W -(An),Dn */
uae_u32 REGPARAM2 op_3020_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 10; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - 2;
	if (srca & 1) {
		m68k_incpci(4);
		m68k_areg(regs, srcreg) = srca;
		exception3_read_access(opcode, srca, 1, 1);
		return 2 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) = srca;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
	m68k_incpci(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 10 * CYCLE_UNIT / 2 + count_cycles;
}
/* 10 (2/0) */
/* 2 0,0   */

/* MOVE.W (d16,An),Dn */
uae_u32 REGPARAM2 op_3028_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (3/0) */
/* 4 0,0   */

/* MOVE.W (d8,An,Xn),Dn */
uae_u32 REGPARAM2 op_3030_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	BusCyclePenalty += 2;
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 14 * CYCLE_UNIT / 2 + count_cycles;
}
/* 14 (3/0) */
/* 4 4,0   */

/* MOVE.W (xxx).W,Dn */
uae_u32 REGPARAM2 op_3038_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, srca, 1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (3/0) */
/* 4 0,0   */

/* MOVE.W (xxx).L,Dn */
uae_u32 REGPARAM2 op_3039_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	srca |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, srca, 1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (4/0) */
/* 6 0,0   */

/* MOVE.W (d16,PC),Dn */
uae_u32 REGPARAM2 op_303a_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_getpci() + 2;
	srca += (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (3/0) */
/* 4 0,0   */

/* MOVE.W (d8,PC,Xn),Dn */
uae_u32 REGPARAM2 op_303b_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	uaecptr tmppc = m68k_getpci() + 2;
	BusCyclePenalty += 2;
	srca = get_disp_ea_000(tmppc, get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 14 * CYCLE_UNIT / 2 + count_cycles;
}
/* 14 (3/0) */
/* 4 4,0   */

/* MOVE.W #<data>.W,Dn */
uae_u32 REGPARAM2 op_303c_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 8;  
	uae_s16 src = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8 (2/0) */
/* 4 0,0   */

/* MOVEA.W Dn,An */
uae_u32 REGPARAM2 op_3040_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 31;
	CurrentInstrCycles = 4;  
	uae_s16 src = m68k_dreg(regs, srcreg);
	src = (uae_s32)(uae_s16)src;
	m68k_areg(regs, dstreg) = (uae_s32)(uae_s16)(src);
	m68k_incpci(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 4 * CYCLE_UNIT / 2 + count_cycles;
}
/* 4 (1/0) */
/* 2 0,0   */

/* MOVEA.W An,An */
uae_u32 REGPARAM2 op_3048_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 31;
	CurrentInstrCycles = 4;  
	uae_s16 src = m68k_areg(regs, srcreg);
	src = (uae_s32)(uae_s16)src;
	m68k_areg(regs, dstreg) = (uae_s32)(uae_s16)(src);
	m68k_incpci(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 4 * CYCLE_UNIT / 2 + count_cycles;
}
/* 4 (1/0) */
/* 2 0,0   */

/* MOVEA.W (An),An */
uae_u32 REGPARAM2 op_3050_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 31;
	CurrentInstrCycles = 8;  
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	src = (uae_s32)(uae_s16)src;
	m68k_areg(regs, dstreg) = (uae_s32)(uae_s16)(src);
	m68k_incpci(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8 (2/0) */
/* 2 0,0   */

/* MOVEA.W (An)+,An */
uae_u32 REGPARAM2 op_3058_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 31;
	CurrentInstrCycles = 8;  
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) += 2 + 0;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) += 2;
	src = (uae_s32)(uae_s16)src;
	m68k_areg(regs, dstreg) = (uae_s32)(uae_s16)(src);
	m68k_incpci(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8 (2/0) */
/* 2 0,0   */

/* MOVEA.W -(An),An */
uae_u32 REGPARAM2 op_3060_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 31;
	CurrentInstrCycles = 10; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - 2;
	if (srca & 1) {
		m68k_incpci(4);
		m68k_areg(regs, srcreg) = srca;
		exception3_read_access(opcode, srca, 1, 1);
		return 2 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) = srca;
	src = (uae_s32)(uae_s16)src;
	m68k_areg(regs, dstreg) = (uae_s32)(uae_s16)(src);
	m68k_incpci(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 10 * CYCLE_UNIT / 2 + count_cycles;
}
/* 10 (2/0) */
/* 2 0,0   */

/* MOVEA.W (d16,An),An */
uae_u32 REGPARAM2 op_3068_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 31;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	src = (uae_s32)(uae_s16)src;
	m68k_areg(regs, dstreg) = (uae_s32)(uae_s16)(src);
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (3/0) */
/* 4 0,0   */

/* MOVEA.W (d8,An,Xn),An */
uae_u32 REGPARAM2 op_3070_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 31;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	BusCyclePenalty += 2;
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	src = (uae_s32)(uae_s16)src;
	m68k_areg(regs, dstreg) = (uae_s32)(uae_s16)(src);
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 14 * CYCLE_UNIT / 2 + count_cycles;
}
/* 14 (3/0) */
/* 4 4,0   */

/* MOVEA.W (xxx).W,An */
uae_u32 REGPARAM2 op_3078_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 31;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, srca, 1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	src = (uae_s32)(uae_s16)src;
	m68k_areg(regs, dstreg) = (uae_s32)(uae_s16)(src);
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (3/0) */
/* 4 0,0   */

/* MOVEA.W (xxx).L,An */
uae_u32 REGPARAM2 op_3079_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 31;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	srca |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, srca, 1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	src = (uae_s32)(uae_s16)src;
	m68k_areg(regs, dstreg) = (uae_s32)(uae_s16)(src);
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (4/0) */
/* 6 0,0   */

/* MOVEA.W (d16,PC),An */
uae_u32 REGPARAM2 op_307a_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 31;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_getpci() + 2;
	srca += (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	src = (uae_s32)(uae_s16)src;
	m68k_areg(regs, dstreg) = (uae_s32)(uae_s16)(src);
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (3/0) */
/* 4 0,0   */

/* MOVEA.W (d8,PC,Xn),An */
uae_u32 REGPARAM2 op_307b_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 31;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	uaecptr tmppc = m68k_getpci() + 2;
	BusCyclePenalty += 2;
	srca = get_disp_ea_000(tmppc, get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	src = (uae_s32)(uae_s16)src;
	m68k_areg(regs, dstreg) = (uae_s32)(uae_s16)(src);
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 14 * CYCLE_UNIT / 2 + count_cycles;
}
/* 14 (3/0) */
/* 4 4,0   */

/* MOVEA.W #<data>.W,An */
uae_u32 REGPARAM2 op_307c_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 31;
	CurrentInstrCycles = 8;  
	uae_s16 src = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	src = (uae_s32)(uae_s16)src;
	m68k_areg(regs, dstreg) = (uae_s32)(uae_s16)(src);
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8 (2/0) */
/* 4 0,0   */

/* MOVE.W Dn,(An) */
uae_u32 REGPARAM2 op_3080_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 8;  
	uae_s16 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(4);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		exception3_write_access(opcode, dsta, 1, src, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8 (1/1) */
/* 2 0,0   */

/* MOVE.W An,(An) */
uae_u32 REGPARAM2 op_3088_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 8;  
	uae_s16 src = m68k_areg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(4);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		exception3_write_access(opcode, dsta, 1, src, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8 (1/1) */
/* 2 0,0   */

/* MOVE.W (An),(An) */
uae_u32 REGPARAM2 op_3090_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(4);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		exception3_write_access(opcode, dsta, 1, src, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (2/1) */
/* 2 0,0   */

/* MOVE.W (An)+,(An) */
uae_u32 REGPARAM2 op_3098_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) += 2 + 0;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) += 2;
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(4);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		exception3_write_access(opcode, dsta, 1, src, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (2/1) */
/* 2 0,0   */

/* MOVE.W -(An),(An) */
uae_u32 REGPARAM2 op_30a0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - 2;
	if (srca & 1) {
		m68k_incpci(4);
		m68k_areg(regs, srcreg) = srca;
		exception3_read_access(opcode, srca, 1, 1);
		return 2 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) = srca;
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(4);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		exception3_write_access(opcode, dsta, 1, src, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 14 * CYCLE_UNIT / 2 + count_cycles;
}
/* 14 (2/1) */
/* 2 0,0   */

/* MOVE.W (d16,An),(An) */
uae_u32 REGPARAM2 op_30a8_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(6);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		exception3_write_access(opcode, dsta, 1, src, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 4 0,0   */

/* MOVE.W (d8,An,Xn),(An) */
uae_u32 REGPARAM2 op_30b0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	BusCyclePenalty += 2;
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(6);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		exception3_write_access(opcode, dsta, 1, src, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (3/1) */
/* 4 4,0   */

/* MOVE.W (xxx).W,(An) */
uae_u32 REGPARAM2 op_30b8_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, srca, 1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(6);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		exception3_write_access(opcode, dsta, 1, src, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 4 0,0   */

/* MOVE.W (xxx).L,(An) */
uae_u32 REGPARAM2 op_30b9_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	srca = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	srca |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, srca, 1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(8);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		exception3_write_access(opcode, dsta, 1, src, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (4/1) */
/* 6 0,0   */

/* MOVE.W (d16,PC),(An) */
uae_u32 REGPARAM2 op_30ba_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = m68k_getpci() + 2;
	srca += (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(6);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		exception3_write_access(opcode, dsta, 1, src, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 4 0,0   */

/* MOVE.W (d8,PC,Xn),(An) */
uae_u32 REGPARAM2 op_30bb_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	uaecptr tmppc = m68k_getpci() + 2;
	BusCyclePenalty += 2;
	srca = get_disp_ea_000(tmppc, get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(6);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		exception3_write_access(opcode, dsta, 1, src, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (3/1) */
/* 4 4,0   */

/* MOVE.W #<data>.W,(An) */
uae_u32 REGPARAM2 op_30bc_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 12; 
	uae_s16 src = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(6);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		exception3_write_access(opcode, dsta, 1, src, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (2/1) */
/* 4 0,0   */

/* MOVE.W Dn,(An)+ */
uae_u32 REGPARAM2 op_30c0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 8;  
	uae_s16 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	m68k_areg(regs, dstreg) += 2;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(4);
		m68k_areg(regs, dstreg) -= 2;
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		exception3_write_access(opcode, dsta, 1, src, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, dstreg) -= 2;
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8 (1/1) */
/* 2 0,0   */

/* MOVE.W An,(An)+ */
uae_u32 REGPARAM2 op_30c8_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 8;  
	uae_s16 src = m68k_areg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	m68k_areg(regs, dstreg) += 2;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(4);
		m68k_areg(regs, dstreg) -= 2;
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		exception3_write_access(opcode, dsta, 1, src, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, dstreg) -= 2;
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8 (1/1) */
/* 2 0,0   */

/* MOVE.W (An),(An)+ */
uae_u32 REGPARAM2 op_30d0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	m68k_areg(regs, dstreg) += 2;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(4);
		m68k_areg(regs, dstreg) -= 2;
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		exception3_write_access(opcode, dsta, 1, src, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, dstreg) -= 2;
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (2/1) */
/* 2 0,0   */

/* MOVE.W (An)+,(An)+ */
uae_u32 REGPARAM2 op_30d8_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) += 2 + 0;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) += 2;
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	m68k_areg(regs, dstreg) += 2;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(4);
		m68k_areg(regs, dstreg) -= 2;
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		exception3_write_access(opcode, dsta, 1, src, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, dstreg) -= 2;
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (2/1) */
/* 2 0,0   */

/* MOVE.W -(An),(An)+ */
uae_u32 REGPARAM2 op_30e0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - 2;
	if (srca & 1) {
		m68k_incpci(4);
		m68k_areg(regs, srcreg) = srca;
		exception3_read_access(opcode, srca, 1, 1);
		return 2 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) = srca;
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	m68k_areg(regs, dstreg) += 2;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(4);
		m68k_areg(regs, dstreg) -= 2;
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		exception3_write_access(opcode, dsta, 1, src, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, dstreg) -= 2;
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 14 * CYCLE_UNIT / 2 + count_cycles;
}
/* 14 (2/1) */
/* 2 0,0   */

/* MOVE.W (d16,An),(An)+ */
uae_u32 REGPARAM2 op_30e8_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	m68k_areg(regs, dstreg) += 2;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(6);
		m68k_areg(regs, dstreg) -= 2;
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		exception3_write_access(opcode, dsta, 1, src, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, dstreg) -= 2;
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 4 0,0   */

/* MOVE.W (d8,An,Xn),(An)+ */
uae_u32 REGPARAM2 op_30f0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	BusCyclePenalty += 2;
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	m68k_areg(regs, dstreg) += 2;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(6);
		m68k_areg(regs, dstreg) -= 2;
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		exception3_write_access(opcode, dsta, 1, src, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, dstreg) -= 2;
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (3/1) */
/* 4 4,0   */

/* MOVE.W (xxx).W,(An)+ */
uae_u32 REGPARAM2 op_30f8_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, srca, 1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	m68k_areg(regs, dstreg) += 2;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(6);
		m68k_areg(regs, dstreg) -= 2;
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		exception3_write_access(opcode, dsta, 1, src, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, dstreg) -= 2;
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 4 0,0   */

/* MOVE.W (xxx).L,(An)+ */
uae_u32 REGPARAM2 op_30f9_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	srca = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	srca |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, srca, 1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	m68k_areg(regs, dstreg) += 2;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(8);
		m68k_areg(regs, dstreg) -= 2;
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		exception3_write_access(opcode, dsta, 1, src, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		m68k_areg(regs, dstreg) -= 2;
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (4/1) */
/* 6 0,0   */

/* MOVE.W (d16,PC),(An)+ */
uae_u32 REGPARAM2 op_30fa_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = m68k_getpci() + 2;
	srca += (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	m68k_areg(regs, dstreg) += 2;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(6);
		m68k_areg(regs, dstreg) -= 2;
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		exception3_write_access(opcode, dsta, 1, src, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, dstreg) -= 2;
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 4 0,0   */

/* MOVE.W (d8,PC,Xn),(An)+ */
uae_u32 REGPARAM2 op_30fb_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	uaecptr tmppc = m68k_getpci() + 2;
	BusCyclePenalty += 2;
	srca = get_disp_ea_000(tmppc, get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	m68k_areg(regs, dstreg) += 2;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(6);
		m68k_areg(regs, dstreg) -= 2;
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		exception3_write_access(opcode, dsta, 1, src, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, dstreg) -= 2;
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (3/1) */
/* 4 4,0   */

/* MOVE.W #<data>.W,(An)+ */
uae_u32 REGPARAM2 op_30fc_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 12; 
	uae_s16 src = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	m68k_areg(regs, dstreg) += 2;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(6);
		m68k_areg(regs, dstreg) -= 2;
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		exception3_write_access(opcode, dsta, 1, src, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, dstreg) -= 2;
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (2/1) */
/* 4 0,0   */

/* MOVE.W Dn,-(An) */
uae_u32 REGPARAM2 op_3100_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 8;  
	uae_s16 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - 2;
	m68k_areg(regs, dstreg) = dsta;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		m68k_areg(regs, dstreg) += 2;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(4);
		count_cycles += 2 * CYCLE_UNIT / 2;
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		m68k_areg(regs, dstreg) = dsta;
		exception3_write_access(opcode, dsta, 1, src, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8+ (1/1) */
/* 2 0,0   */

/* MOVE.W An,-(An) */
uae_u32 REGPARAM2 op_3108_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 8;  
	uae_s16 src = m68k_areg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - 2;
	m68k_areg(regs, dstreg) = dsta;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		m68k_areg(regs, dstreg) += 2;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(4);
		count_cycles += 2 * CYCLE_UNIT / 2;
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		m68k_areg(regs, dstreg) = dsta;
		exception3_write_access(opcode, dsta, 1, src, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8+ (1/1) */
/* 2 0,0   */

/* MOVE.W (An),-(An) */
uae_u32 REGPARAM2 op_3110_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - 2;
	m68k_areg(regs, dstreg) = dsta;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		m68k_areg(regs, dstreg) += 2;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(4);
		count_cycles += 2 * CYCLE_UNIT / 2;
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		m68k_areg(regs, dstreg) = dsta;
		exception3_write_access(opcode, dsta, 1, src, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12+ (2/1) */
/* 2 0,0   */

/* MOVE.W (An)+,-(An) */
uae_u32 REGPARAM2 op_3118_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) += 2 + 0;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) += 2;
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - 2;
	m68k_areg(regs, dstreg) = dsta;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		m68k_areg(regs, dstreg) += 2;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(4);
		count_cycles += 2 * CYCLE_UNIT / 2;
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		m68k_areg(regs, dstreg) = dsta;
		exception3_write_access(opcode, dsta, 1, src, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12+ (2/1) */
/* 2 0,0   */

/* MOVE.W -(An),-(An) */
uae_u32 REGPARAM2 op_3120_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - 2;
	if (srca & 1) {
		m68k_incpci(4);
		m68k_areg(regs, srcreg) = srca;
		exception3_read_access(opcode, srca, 1, 1);
		return 2 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) = srca;
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - 2;
	m68k_areg(regs, dstreg) = dsta;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		m68k_areg(regs, dstreg) += 2;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(4);
		count_cycles += 2 * CYCLE_UNIT / 2;
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		m68k_areg(regs, dstreg) = dsta;
		exception3_write_access(opcode, dsta, 1, src, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 14 * CYCLE_UNIT / 2 + count_cycles;
}
/* 14+ (2/1) */
/* 2 0,0   */

/* MOVE.W (d16,An),-(An) */
uae_u32 REGPARAM2 op_3128_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - 2;
	m68k_areg(regs, dstreg) = dsta;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		m68k_areg(regs, dstreg) += 2;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(6);
		count_cycles += 2 * CYCLE_UNIT / 2;
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		m68k_areg(regs, dstreg) = dsta;
		exception3_write_access(opcode, dsta, 1, src, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16+ (3/1) */
/* 4 0,0   */

/* MOVE.W (d8,An,Xn),-(An) */
uae_u32 REGPARAM2 op_3130_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	BusCyclePenalty += 2;
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - 2;
	m68k_areg(regs, dstreg) = dsta;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		m68k_areg(regs, dstreg) += 2;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(6);
		count_cycles += 2 * CYCLE_UNIT / 2;
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		m68k_areg(regs, dstreg) = dsta;
		exception3_write_access(opcode, dsta, 1, src, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18+ (3/1) */
/* 4 4,0   */

/* MOVE.W (xxx).W,-(An) */
uae_u32 REGPARAM2 op_3138_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, srca, 1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - 2;
	m68k_areg(regs, dstreg) = dsta;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		m68k_areg(regs, dstreg) += 2;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(6);
		count_cycles += 2 * CYCLE_UNIT / 2;
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		m68k_areg(regs, dstreg) = dsta;
		exception3_write_access(opcode, dsta, 1, src, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16+ (3/1) */
/* 4 0,0   */

/* MOVE.W (xxx).L,-(An) */
uae_u32 REGPARAM2 op_3139_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	srca = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	srca |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, srca, 1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - 2;
	m68k_areg(regs, dstreg) = dsta;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		m68k_areg(regs, dstreg) += 2;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(8);
		count_cycles += 2 * CYCLE_UNIT / 2;
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		m68k_areg(regs, dstreg) = dsta;
		exception3_write_access(opcode, dsta, 1, src, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20+ (4/1) */
/* 6 0,0   */

/* MOVE.W (d16,PC),-(An) */
uae_u32 REGPARAM2 op_313a_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = m68k_getpci() + 2;
	srca += (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - 2;
	m68k_areg(regs, dstreg) = dsta;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		m68k_areg(regs, dstreg) += 2;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(6);
		count_cycles += 2 * CYCLE_UNIT / 2;
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		m68k_areg(regs, dstreg) = dsta;
		exception3_write_access(opcode, dsta, 1, src, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16+ (3/1) */
/* 4 0,0   */

/* MOVE.W (d8,PC,Xn),-(An) */
uae_u32 REGPARAM2 op_313b_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	uaecptr tmppc = m68k_getpci() + 2;
	BusCyclePenalty += 2;
	srca = get_disp_ea_000(tmppc, get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - 2;
	m68k_areg(regs, dstreg) = dsta;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		m68k_areg(regs, dstreg) += 2;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(6);
		count_cycles += 2 * CYCLE_UNIT / 2;
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		m68k_areg(regs, dstreg) = dsta;
		exception3_write_access(opcode, dsta, 1, src, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18+ (3/1) */
/* 4 4,0   */

/* MOVE.W #<data>.W,-(An) */
uae_u32 REGPARAM2 op_313c_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 12; 
	uae_s16 src = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - 2;
	m68k_areg(regs, dstreg) = dsta;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		m68k_areg(regs, dstreg) += 2;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(6);
		count_cycles += 2 * CYCLE_UNIT / 2;
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		m68k_areg(regs, dstreg) = dsta;
		exception3_write_access(opcode, dsta, 1, src, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12+ (2/1) */
/* 4 0,0   */

/* MOVE.W Dn,(d16,An) */
uae_u32 REGPARAM2 op_3140_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 12; 
	uae_s16 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(4);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		exception3_write_access(opcode, dsta, 1, src, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (2/1) */
/* 4 0,0   */

/* MOVE.W An,(d16,An) */
uae_u32 REGPARAM2 op_3148_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 12; 
	uae_s16 src = m68k_areg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(4);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		exception3_write_access(opcode, dsta, 1, src, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (2/1) */
/* 4 0,0   */

/* MOVE.W (An),(d16,An) */
uae_u32 REGPARAM2 op_3150_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 4, 0);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(4);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		exception3_write_access(opcode, dsta, 1, src, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 4 0,0   */

/* MOVE.W (An)+,(d16,An) */
uae_u32 REGPARAM2 op_3158_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) += 2 + 0;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) += 2;
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 4, 0);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(4);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		exception3_write_access(opcode, dsta, 1, src, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 4 0,0   */

/* MOVE.W -(An),(d16,An) */
uae_u32 REGPARAM2 op_3160_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - 2;
	if (srca & 1) {
		m68k_incpci(4);
		m68k_areg(regs, srcreg) = srca;
		exception3_read_access(opcode, srca, 1, 1);
		return 2 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) = srca;
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 4, 0);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(4);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		exception3_write_access(opcode, dsta, 1, src, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (3/1) */
/* 4 0,0   */

/* MOVE.W (d16,An),(d16,An) */
uae_u32 REGPARAM2 op_3168_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 6, 0);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(6);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		exception3_write_access(opcode, dsta, 1, src, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (4/1) */
/* 6 0,0   */

/* MOVE.W (d8,An,Xn),(d16,An) */
uae_u32 REGPARAM2 op_3170_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 22; 
	uaecptr srca;
	BusCyclePenalty += 2;
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 6, 0);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(6);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		exception3_write_access(opcode, dsta, 1, src, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 22 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 22 * CYCLE_UNIT / 2 + count_cycles;
}
/* 22 (4/1) */
/* 6 6,0   */

/* MOVE.W (xxx).W,(d16,An) */
uae_u32 REGPARAM2 op_3178_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, srca, 1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 6, 0);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(6);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		exception3_write_access(opcode, dsta, 1, src, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (4/1) */
/* 6 0,0   */

/* MOVE.W (xxx).L,(d16,An) */
uae_u32 REGPARAM2 op_3179_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 24; 
	uaecptr srca;
	srca = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	srca |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, srca, 1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 8, 0);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(8);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		exception3_write_access(opcode, dsta, 1, src, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(8);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 24 * CYCLE_UNIT / 2 + count_cycles;
}
/* 24 (5/1) */
/* 8 0,0   */

/* MOVE.W (d16,PC),(d16,An) */
uae_u32 REGPARAM2 op_317a_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	srca = m68k_getpci() + 2;
	srca += (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 6, 0);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(6);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		exception3_write_access(opcode, dsta, 1, src, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (4/1) */
/* 6 0,0   */

/* MOVE.W (d8,PC,Xn),(d16,An) */
uae_u32 REGPARAM2 op_317b_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 22; 
	uaecptr srca;
	uaecptr tmppc = m68k_getpci() + 2;
	BusCyclePenalty += 2;
	srca = get_disp_ea_000(tmppc, get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 6, 0);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(6);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		exception3_write_access(opcode, dsta, 1, src, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 22 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 22 * CYCLE_UNIT / 2 + count_cycles;
}
/* 22 (4/1) */
/* 6 6,0   */

/* MOVE.W #<data>.W,(d16,An) */
uae_u32 REGPARAM2 op_317c_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 16; 
	uae_s16 src = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, 0);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(6);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		exception3_write_access(opcode, dsta, 1, src, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 6 0,0   */

/* MOVE.W Dn,(d8,An,Xn) */
uae_u32 REGPARAM2 op_3180_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 14; 
	uae_s16 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	BusCyclePenalty += 2;
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(4);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		exception3_write_access(opcode, dsta, 1, src, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 14 * CYCLE_UNIT / 2 + count_cycles;
}
/* 14 (2/1) */
/* 4 4,0   */

/* MOVE.W An,(d8,An,Xn) */
uae_u32 REGPARAM2 op_3188_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 14; 
	uae_s16 src = m68k_areg(regs, srcreg);
	uaecptr dsta;
	BusCyclePenalty += 2;
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(4);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		exception3_write_access(opcode, dsta, 1, src, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 14 * CYCLE_UNIT / 2 + count_cycles;
}
/* 14 (2/1) */
/* 4 4,0   */

/* MOVE.W (An),(d8,An,Xn) */
uae_u32 REGPARAM2 op_3190_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	BusCyclePenalty += 2;
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 4, 0);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(4);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		exception3_write_access(opcode, dsta, 1, src, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (3/1) */
/* 4 4,0   */

/* MOVE.W (An)+,(d8,An,Xn) */
uae_u32 REGPARAM2 op_3198_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) += 2 + 0;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) += 2;
	uaecptr dsta;
	BusCyclePenalty += 2;
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 4, 0);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(4);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		exception3_write_access(opcode, dsta, 1, src, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (3/1) */
/* 4 4,0   */

/* MOVE.W -(An),(d8,An,Xn) */
uae_u32 REGPARAM2 op_31a0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - 2;
	if (srca & 1) {
		m68k_incpci(4);
		m68k_areg(regs, srcreg) = srca;
		exception3_read_access(opcode, srca, 1, 1);
		return 2 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) = srca;
	uaecptr dsta;
	BusCyclePenalty += 2;
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 4, 0);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(4);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		exception3_write_access(opcode, dsta, 1, src, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (3/1) */
/* 4 4,0   */

/* MOVE.W (d16,An),(d8,An,Xn) */
uae_u32 REGPARAM2 op_31a8_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 22; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	BusCyclePenalty += 2;
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_000_prefetch(6));
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 6, 0);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(6);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		exception3_write_access(opcode, dsta, 1, src, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 22 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 22 * CYCLE_UNIT / 2 + count_cycles;
}
/* 22 (4/1) */
/* 6 4,0   */

/* MOVE.W (d8,An,Xn),(d8,An,Xn) */
uae_u32 REGPARAM2 op_31b0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 24; 
	uaecptr srca;
	BusCyclePenalty += 2;
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	BusCyclePenalty += 2;
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_000_prefetch(6));
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 6, 0);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(6);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		exception3_write_access(opcode, dsta, 1, src, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 24 * CYCLE_UNIT / 2 + count_cycles;
}
/* 24 (4/1) */
/* 6 6,4   */

/* MOVE.W (xxx).W,(d8,An,Xn) */
uae_u32 REGPARAM2 op_31b8_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 22; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, srca, 1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	BusCyclePenalty += 2;
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_000_prefetch(6));
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 6, 0);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(6);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		exception3_write_access(opcode, dsta, 1, src, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 22 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 22 * CYCLE_UNIT / 2 + count_cycles;
}
/* 22 (4/1) */
/* 6 4,0   */

/* MOVE.W (xxx).L,(d8,An,Xn) */
uae_u32 REGPARAM2 op_31b9_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 26; 
	uaecptr srca;
	srca = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	srca |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, srca, 1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	BusCyclePenalty += 2;
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_000_prefetch(8));
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 8, 0);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(8);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		exception3_write_access(opcode, dsta, 1, src, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return 22 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(8);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 26 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 26 * CYCLE_UNIT / 2 + count_cycles;
}
/* 26 (5/1) */
/* 8 4,0   */

/* MOVE.W (d16,PC),(d8,An,Xn) */
uae_u32 REGPARAM2 op_31ba_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 22; 
	uaecptr srca;
	srca = m68k_getpci() + 2;
	srca += (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	BusCyclePenalty += 2;
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_000_prefetch(6));
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 6, 0);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(6);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		exception3_write_access(opcode, dsta, 1, src, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 22 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 22 * CYCLE_UNIT / 2 + count_cycles;
}
/* 22 (4/1) */
/* 6 4,0   */

/* MOVE.W (d8,PC,Xn),(d8,An,Xn) */
uae_u32 REGPARAM2 op_31bb_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 24; 
	uaecptr srca;
	uaecptr tmppc = m68k_getpci() + 2;
	BusCyclePenalty += 2;
	srca = get_disp_ea_000(tmppc, get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	BusCyclePenalty += 2;
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_000_prefetch(6));
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 6, 0);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(6);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		exception3_write_access(opcode, dsta, 1, src, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 24 * CYCLE_UNIT / 2 + count_cycles;
}
/* 24 (4/1) */
/* 6 6,4   */

/* MOVE.W #<data>.W,(d8,An,Xn) */
uae_u32 REGPARAM2 op_31bc_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 18; 
	uae_s16 src = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	BusCyclePenalty += 2;
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_000_prefetch(6));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, 0);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(6);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		exception3_write_access(opcode, dsta, 1, src, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (3/1) */
/* 6 4,0   */

/* MOVE.W Dn,(xxx).W */
uae_u32 REGPARAM2 op_31c0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 30;
	CurrentInstrCycles = 12; 
	uae_s16 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(4);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		exception3_write_access(opcode, dsta, 1, src, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (2/1) */
/* 4 0,0   */

/* MOVE.W An,(xxx).W */
uae_u32 REGPARAM2 op_31c8_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 30;
	CurrentInstrCycles = 12; 
	uae_s16 src = m68k_areg(regs, srcreg);
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(4);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		exception3_write_access(opcode, dsta, 1, src, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (2/1) */
/* 4 0,0   */

/* MOVE.W (An),(xxx).W */
uae_u32 REGPARAM2 op_31d0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 30;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 4, 0);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(4);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		exception3_write_access(opcode, dsta, 1, src, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 4 0,0   */

/* MOVE.W (An)+,(xxx).W */
uae_u32 REGPARAM2 op_31d8_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 30;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) += 2 + 0;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) += 2;
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 4, 0);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(4);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		exception3_write_access(opcode, dsta, 1, src, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 4 0,0   */

/* MOVE.W -(An),(xxx).W */
uae_u32 REGPARAM2 op_31e0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 30;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - 2;
	if (srca & 1) {
		m68k_incpci(4);
		m68k_areg(regs, srcreg) = srca;
		exception3_read_access(opcode, srca, 1, 1);
		return 2 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) = srca;
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 4, 0);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(4);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		exception3_write_access(opcode, dsta, 1, src, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (3/1) */
/* 4 0,0   */

/* MOVE.W (d16,An),(xxx).W */
uae_u32 REGPARAM2 op_31e8_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 30;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 6, 0);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(6);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		exception3_write_access(opcode, dsta, 1, src, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (4/1) */
/* 6 0,0   */

/* MOVE.W (d8,An,Xn),(xxx).W */
uae_u32 REGPARAM2 op_31f0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 30;
	CurrentInstrCycles = 22; 
	uaecptr srca;
	BusCyclePenalty += 2;
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 6, 0);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(6);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		exception3_write_access(opcode, dsta, 1, src, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 22 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 22 * CYCLE_UNIT / 2 + count_cycles;
}
/* 22 (4/1) */
/* 6 6,0   */

/* MOVE.W (xxx).W,(xxx).W */
uae_u32 REGPARAM2 op_31f8_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 30;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, srca, 1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 6, 0);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(6);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		exception3_write_access(opcode, dsta, 1, src, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (4/1) */
/* 6 0,0   */

/* MOVE.W (xxx).L,(xxx).W */
uae_u32 REGPARAM2 op_31f9_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 30;
	CurrentInstrCycles = 24; 
	uaecptr srca;
	srca = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	srca |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, srca, 1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 8, 0);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(8);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		exception3_write_access(opcode, dsta, 1, src, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(8);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 24 * CYCLE_UNIT / 2 + count_cycles;
}
/* 24 (5/1) */
/* 8 0,0   */

/* MOVE.W (d16,PC),(xxx).W */
uae_u32 REGPARAM2 op_31fa_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 30;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	srca = m68k_getpci() + 2;
	srca += (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 6, 0);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(6);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		exception3_write_access(opcode, dsta, 1, src, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (4/1) */
/* 6 0,0   */

/* MOVE.W (d8,PC,Xn),(xxx).W */
uae_u32 REGPARAM2 op_31fb_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 30;
	CurrentInstrCycles = 22; 
	uaecptr srca;
	uaecptr tmppc = m68k_getpci() + 2;
	BusCyclePenalty += 2;
	srca = get_disp_ea_000(tmppc, get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 6, 0);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(6);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		exception3_write_access(opcode, dsta, 1, src, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 22 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 22 * CYCLE_UNIT / 2 + count_cycles;
}
/* 22 (4/1) */
/* 6 6,0   */

/* MOVE.W #<data>.W,(xxx).W */
uae_u32 REGPARAM2 op_31fc_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 30;
	CurrentInstrCycles = 16; 
	uae_s16 src = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 6, 0);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(6);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		exception3_write_access(opcode, dsta, 1, src, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 6 0,0   */

/* MOVE.W Dn,(xxx).L */
uae_u32 REGPARAM2 op_33c0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 30;
	CurrentInstrCycles = 16; 
	uae_s16 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	dsta |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(6);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		exception3_write_access(opcode, dsta, 1, src, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 6 0,0   */

/* MOVE.W An,(xxx).L */
uae_u32 REGPARAM2 op_33c8_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 30;
	CurrentInstrCycles = 16; 
	uae_s16 src = m68k_areg(regs, srcreg);
	uaecptr dsta;
	dsta = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	dsta |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(6);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		exception3_write_access(opcode, dsta, 1, src, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 6 0,0   */

/* MOVE.W (An),(xxx).L */
uae_u32 REGPARAM2 op_33d0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 30;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = get_word_000_prefetch(4) << 16;
	dsta |= regs.irc;
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 4, 0);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(4);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		exception3_write_access(opcode, dsta, 1, src, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	get_word_000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, 0);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	if(regs.t1) opcode |= 0x10000;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (4/1) */
/* 6 0,0   */

/* MOVE.W (An)+,(xxx).L */
uae_u32 REGPARAM2 op_33d8_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 30;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) += 2 + 0;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) += 2;
	uaecptr dsta;
	dsta = get_word_000_prefetch(4) << 16;
	dsta |= regs.irc;
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 4, 0);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(4);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		exception3_write_access(opcode, dsta, 1, src, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	get_word_000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, 0);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	if(regs.t1) opcode |= 0x10000;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (4/1) */
/* 6 0,0   */

/* MOVE.W -(An),(xxx).L */
uae_u32 REGPARAM2 op_33e0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 30;
	CurrentInstrCycles = 22; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - 2;
	if (srca & 1) {
		m68k_incpci(4);
		m68k_areg(regs, srcreg) = srca;
		exception3_read_access(opcode, srca, 1, 1);
		return 2 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) = srca;
	uaecptr dsta;
	dsta = get_word_000_prefetch(4) << 16;
	dsta |= regs.irc;
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 4, 0);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(4);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		exception3_write_access(opcode, dsta, 1, src, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	get_word_000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, 0);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	if(regs.t1) opcode |= 0x10000;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 22 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 22 * CYCLE_UNIT / 2 + count_cycles;
}
/* 22 (4/1) */
/* 6 0,0   */

/* MOVE.W (d16,An),(xxx).L */
uae_u32 REGPARAM2 op_33e8_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 30;
	CurrentInstrCycles = 24; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = get_word_000_prefetch(6) << 16;
	dsta |= regs.irc;
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 6, 0);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(6);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		exception3_write_access(opcode, dsta, 1, src, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(8);
	get_word_000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, 0);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	if(regs.t1) opcode |= 0x10000;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 24 * CYCLE_UNIT / 2 + count_cycles;
}
/* 24 (5/1) */
/* 8 0,0   */

/* MOVE.W (d8,An,Xn),(xxx).L */
uae_u32 REGPARAM2 op_33f0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 30;
	CurrentInstrCycles = 26; 
	uaecptr srca;
	BusCyclePenalty += 2;
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = get_word_000_prefetch(6) << 16;
	dsta |= regs.irc;
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 6, 0);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(6);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		exception3_write_access(opcode, dsta, 1, src, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(8);
	get_word_000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, 0);
		return 22 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	if(regs.t1) opcode |= 0x10000;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 26 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 26 * CYCLE_UNIT / 2 + count_cycles;
}
/* 26 (5/1) */
/* 8 8,0   */

/* MOVE.W (xxx).W,(xxx).L */
uae_u32 REGPARAM2 op_33f8_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 30;
	CurrentInstrCycles = 24; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, srca, 1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = get_word_000_prefetch(6) << 16;
	dsta |= regs.irc;
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 6, 0);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(6);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		exception3_write_access(opcode, dsta, 1, src, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(8);
	get_word_000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, 0);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	if(regs.t1) opcode |= 0x10000;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 24 * CYCLE_UNIT / 2 + count_cycles;
}
/* 24 (5/1) */
/* 8 0,0   */

/* MOVE.W (xxx).L,(xxx).L */
uae_u32 REGPARAM2 op_33f9_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 30;
	CurrentInstrCycles = 28; 
	uaecptr srca;
	srca = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	srca |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, srca, 1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = get_word_000_prefetch(8) << 16;
	dsta |= regs.irc;
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 8, 0);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(8);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		exception3_write_access(opcode, dsta, 1, src, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(10);
	get_word_000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, 0);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	if(regs.t1) opcode |= 0x10000;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 28 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 28 * CYCLE_UNIT / 2 + count_cycles;
}
/* 28 (6/1) */
/* 10 0,0   */

/* MOVE.W (d16,PC),(xxx).L */
uae_u32 REGPARAM2 op_33fa_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 30;
	CurrentInstrCycles = 24; 
	uaecptr srca;
	srca = m68k_getpci() + 2;
	srca += (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = get_word_000_prefetch(6) << 16;
	dsta |= regs.irc;
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 6, 0);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(6);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		exception3_write_access(opcode, dsta, 1, src, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(8);
	get_word_000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, 0);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	if(regs.t1) opcode |= 0x10000;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 24 * CYCLE_UNIT / 2 + count_cycles;
}
/* 24 (5/1) */
/* 8 0,0   */

/* MOVE.W (d8,PC,Xn),(xxx).L */
uae_u32 REGPARAM2 op_33fb_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 30;
	CurrentInstrCycles = 26; 
	uaecptr srca;
	uaecptr tmppc = m68k_getpci() + 2;
	BusCyclePenalty += 2;
	srca = get_disp_ea_000(tmppc, get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = get_word_000_prefetch(6) << 16;
	dsta |= regs.irc;
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 6, 0);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(6);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		exception3_write_access(opcode, dsta, 1, src, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(8);
	get_word_000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, 0);
		return 22 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	if(regs.t1) opcode |= 0x10000;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 26 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 26 * CYCLE_UNIT / 2 + count_cycles;
}
/* 26 (5/1) */
/* 8 8,0   */

/* MOVE.W #<data>.W,(xxx).L */
uae_u32 REGPARAM2 op_33fc_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 30;
	CurrentInstrCycles = 20; 
	uae_s16 src = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = get_word_000_prefetch(6) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	dsta |= get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 8, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(8);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		exception3_write_access(opcode, dsta, 1, src, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(8);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (4/1) */
/* 8 0,0   */

/* NEGX.B Dn */
uae_u32 REGPARAM2 op_4000_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 16;
	CurrentInstrCycles = 4;  
	uae_s8 src = m68k_dreg(regs, srcreg);
	uae_u32 newv = 0 - src - (GET_XFLG() ? 1 : 0);
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(0)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_VFLG((flgs ^ flgo) & (flgo ^ flgn));
	SET_CFLG(flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
	COPY_CARRY();
	SET_ZFLG(GET_ZFLG() & (((uae_s8)(newv)) == 0));
	SET_NFLG(((uae_s8)(newv)) < 0);
	m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((newv) & 0xff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 4 * CYCLE_UNIT / 2 + count_cycles;
}
/* 4 (1/0) */
/* 2 0,0   */

/* NEGX.B (An) */
uae_u32 REGPARAM2 op_4010_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 16;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 newv = 0 - src - (GET_XFLG() ? 1 : 0);
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(0)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_VFLG((flgs ^ flgo) & (flgo ^ flgn));
	SET_CFLG(flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
	COPY_CARRY();
	SET_ZFLG(GET_ZFLG() & (((uae_s8)(newv)) == 0));
	SET_NFLG(((uae_s8)(newv)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_byte_000(srca, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, newv, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (2/1) */
/* 2 0,0   */

/* NEGX.B (An)+ */
uae_u32 REGPARAM2 op_4018_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 16;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
	uae_u32 newv = 0 - src - (GET_XFLG() ? 1 : 0);
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(0)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_VFLG((flgs ^ flgo) & (flgo ^ flgn));
	SET_CFLG(flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
	COPY_CARRY();
	SET_ZFLG(GET_ZFLG() & (((uae_s8)(newv)) == 0));
	SET_NFLG(((uae_s8)(newv)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_byte_000(srca, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, newv, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (2/1) */
/* 2 0,0   */

/* NEGX.B -(An) */
uae_u32 REGPARAM2 op_4020_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 16;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) = srca;
	uae_u32 newv = 0 - src - (GET_XFLG() ? 1 : 0);
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(0)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_VFLG((flgs ^ flgo) & (flgo ^ flgn));
	SET_CFLG(flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
	COPY_CARRY();
	SET_ZFLG(GET_ZFLG() & (((uae_s8)(newv)) == 0));
	SET_NFLG(((uae_s8)(newv)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_byte_000(srca, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, newv, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 14 * CYCLE_UNIT / 2 + count_cycles;
}
/* 14 (2/1) */
/* 2 0,0   */

/* NEGX.B (d16,An) */
uae_u32 REGPARAM2 op_4028_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 16;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 newv = 0 - src - (GET_XFLG() ? 1 : 0);
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(0)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_VFLG((flgs ^ flgo) & (flgo ^ flgn));
	SET_CFLG(flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
	COPY_CARRY();
	SET_ZFLG(GET_ZFLG() & (((uae_s8)(newv)) == 0));
	SET_NFLG(((uae_s8)(newv)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_byte_000(srca, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, newv, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 4 0,0   */

/* NEGX.B (d8,An,Xn) */
uae_u32 REGPARAM2 op_4030_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 16;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	BusCyclePenalty += 2;
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 newv = 0 - src - (GET_XFLG() ? 1 : 0);
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(0)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_VFLG((flgs ^ flgo) & (flgo ^ flgn));
	SET_CFLG(flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
	COPY_CARRY();
	SET_ZFLG(GET_ZFLG() & (((uae_s8)(newv)) == 0));
	SET_NFLG(((uae_s8)(newv)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_byte_000(srca, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, newv, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (3/1) */
/* 4 4,0   */

/* NEGX.B (xxx).W */
uae_u32 REGPARAM2 op_4038_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 16;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 newv = 0 - src - (GET_XFLG() ? 1 : 0);
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(0)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_VFLG((flgs ^ flgo) & (flgo ^ flgn));
	SET_CFLG(flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
	COPY_CARRY();
	SET_ZFLG(GET_ZFLG() & (((uae_s8)(newv)) == 0));
	SET_NFLG(((uae_s8)(newv)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_byte_000(srca, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, newv, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 4 0,0   */

/* NEGX.B (xxx).L */
uae_u32 REGPARAM2 op_4039_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 16;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	srca = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	srca |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 newv = 0 - src - (GET_XFLG() ? 1 : 0);
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(0)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_VFLG((flgs ^ flgo) & (flgo ^ flgn));
	SET_CFLG(flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
	COPY_CARRY();
	SET_ZFLG(GET_ZFLG() & (((uae_s8)(newv)) == 0));
	SET_NFLG(((uae_s8)(newv)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_byte_000(srca, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, newv, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (4/1) */
/* 6 0,0   */

/* NEGX.W Dn */
uae_u32 REGPARAM2 op_4040_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 16;
	CurrentInstrCycles = 4;  
	uae_s16 src = m68k_dreg(regs, srcreg);
	uae_u32 newv = 0 - src - (GET_XFLG() ? 1 : 0);
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(0)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_VFLG((flgs ^ flgo) & (flgo ^ flgn));
	SET_CFLG(flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
	COPY_CARRY();
	SET_ZFLG(GET_ZFLG() & (((uae_s16)(newv)) == 0));
	SET_NFLG(((uae_s16)(newv)) < 0);
	m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | ((newv) & 0xffff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 4 * CYCLE_UNIT / 2 + count_cycles;
}
/* 4 (1/0) */
/* 2 0,0   */

/* NEGX.W (An) */
uae_u32 REGPARAM2 op_4050_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 16;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 newv = 0 - src - (GET_XFLG() ? 1 : 0);
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(0)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_VFLG((flgs ^ flgo) & (flgo ^ flgn));
	SET_CFLG(flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
	COPY_CARRY();
	SET_ZFLG(GET_ZFLG() & (((uae_s16)(newv)) == 0));
	SET_NFLG(((uae_s16)(newv)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_word_000(srca, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x1, newv, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (2/1) */
/* 2 0,0   */

/* NEGX.W (An)+ */
uae_u32 REGPARAM2 op_4058_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 16;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) += 2 + 0;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) += 2;
	uae_u32 newv = 0 - src - (GET_XFLG() ? 1 : 0);
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(0)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_VFLG((flgs ^ flgo) & (flgo ^ flgn));
	SET_CFLG(flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
	COPY_CARRY();
	SET_ZFLG(GET_ZFLG() & (((uae_s16)(newv)) == 0));
	SET_NFLG(((uae_s16)(newv)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_word_000(srca, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x1, newv, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (2/1) */
/* 2 0,0   */

/* NEGX.W -(An) */
uae_u32 REGPARAM2 op_4060_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 16;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - 2;
	if (srca & 1) {
		m68k_incpci(4);
		m68k_areg(regs, srcreg) = srca;
		exception3_read_access(opcode, srca, 1, 1);
		return 2 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) = srca;
	uae_u32 newv = 0 - src - (GET_XFLG() ? 1 : 0);
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(0)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_VFLG((flgs ^ flgo) & (flgo ^ flgn));
	SET_CFLG(flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
	COPY_CARRY();
	SET_ZFLG(GET_ZFLG() & (((uae_s16)(newv)) == 0));
	SET_NFLG(((uae_s16)(newv)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_word_000(srca, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x1, newv, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 14 * CYCLE_UNIT / 2 + count_cycles;
}
/* 14 (2/1) */
/* 2 0,0   */

/* NEGX.W (d16,An) */
uae_u32 REGPARAM2 op_4068_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 16;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 newv = 0 - src - (GET_XFLG() ? 1 : 0);
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(0)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_VFLG((flgs ^ flgo) & (flgo ^ flgn));
	SET_CFLG(flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
	COPY_CARRY();
	SET_ZFLG(GET_ZFLG() & (((uae_s16)(newv)) == 0));
	SET_NFLG(((uae_s16)(newv)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_word_000(srca, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x1, newv, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 4 0,0   */

/* NEGX.W (d8,An,Xn) */
uae_u32 REGPARAM2 op_4070_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 16;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	BusCyclePenalty += 2;
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 newv = 0 - src - (GET_XFLG() ? 1 : 0);
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(0)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_VFLG((flgs ^ flgo) & (flgo ^ flgn));
	SET_CFLG(flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
	COPY_CARRY();
	SET_ZFLG(GET_ZFLG() & (((uae_s16)(newv)) == 0));
	SET_NFLG(((uae_s16)(newv)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_word_000(srca, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x1, newv, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (3/1) */
/* 4 4,0   */

/* NEGX.W (xxx).W */
uae_u32 REGPARAM2 op_4078_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 16;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, srca, 1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 newv = 0 - src - (GET_XFLG() ? 1 : 0);
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(0)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_VFLG((flgs ^ flgo) & (flgo ^ flgn));
	SET_CFLG(flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
	COPY_CARRY();
	SET_ZFLG(GET_ZFLG() & (((uae_s16)(newv)) == 0));
	SET_NFLG(((uae_s16)(newv)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_word_000(srca, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x1, newv, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 4 0,0   */

/* NEGX.W (xxx).L */
uae_u32 REGPARAM2 op_4079_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 16;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	srca = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	srca |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, srca, 1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 newv = 0 - src - (GET_XFLG() ? 1 : 0);
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(0)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_VFLG((flgs ^ flgo) & (flgo ^ flgn));
	SET_CFLG(flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
	COPY_CARRY();
	SET_ZFLG(GET_ZFLG() & (((uae_s16)(newv)) == 0));
	SET_NFLG(((uae_s16)(newv)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_word_000(srca, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x1, newv, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (4/1) */
/* 6 0,0   */

/* NEGX.L Dn */
uae_u32 REGPARAM2 op_4080_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 16;
	CurrentInstrCycles = 6;  
	uae_s32 src = m68k_dreg(regs, srcreg);
	uae_u32 newv = 0 - src - (GET_XFLG() ? 1 : 0);
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(0)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_VFLG((flgs ^ flgo) & (flgo ^ flgn));
	SET_CFLG(flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
	COPY_CARRY();
	SET_ZFLG(GET_ZFLG() & (((uae_s32)(newv)) == 0));
	SET_NFLG(((uae_s32)(newv)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		dreg_68000_long_replace_low(srcreg, newv);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	m68k_dreg(regs, srcreg) = (newv);
	m68k_incpci(2);
	return 6 * CYCLE_UNIT / 2 + count_cycles;
}
/* 6 (1/0) */
/* 2 0,0   */

/* NEGX.L (An) */
uae_u32 REGPARAM2 op_4090_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 16;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 newv = 0 - src - (GET_XFLG() ? 1 : 0);
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(0)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_VFLG((flgs ^ flgo) & (flgo ^ flgn));
	SET_CFLG(flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
	COPY_CARRY();
	SET_ZFLG(GET_ZFLG() & (((uae_s32)(newv)) == 0));
	SET_NFLG(((uae_s32)(newv)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		int bflgs = ((uae_s16)(src)) < 0;
		int bflgo = ((uae_s16)(0)) < 0;
		int bflgn = ((uae_s16)(newv)) < 0;
		SET_VFLG((bflgs ^ bflgo) & (bflgo ^ bflgn));
		SET_CFLG(bflgs ^ ((bflgs ^ bflgn) & (bflgo ^ bflgn)));
		SET_ZFLG(GET_ZFLG() & (((uae_s16)(newv)) == 0));
		SET_NFLG(((uae_s16)(newv)) < 0);
		SET_XFLG(GET_CFLG());
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(srca + 2, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, srca + 2, 0x1, newv, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(srca, newv >> 16); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, srca + 0, 0x1, newv >> 16, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (3/2) */
/* 2 0,0   */

/* NEGX.L (An)+ */
uae_u32 REGPARAM2 op_4098_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 16;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) += 4;
	uae_u32 newv = 0 - src - (GET_XFLG() ? 1 : 0);
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(0)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_VFLG((flgs ^ flgo) & (flgo ^ flgn));
	SET_CFLG(flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
	COPY_CARRY();
	SET_ZFLG(GET_ZFLG() & (((uae_s32)(newv)) == 0));
	SET_NFLG(((uae_s32)(newv)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		int bflgs = ((uae_s16)(src)) < 0;
		int bflgo = ((uae_s16)(0)) < 0;
		int bflgn = ((uae_s16)(newv)) < 0;
		SET_VFLG((bflgs ^ bflgo) & (bflgo ^ bflgn));
		SET_CFLG(bflgs ^ ((bflgs ^ bflgn) & (bflgo ^ bflgn)));
		SET_ZFLG(GET_ZFLG() & (((uae_s16)(newv)) == 0));
		SET_NFLG(((uae_s16)(newv)) < 0);
		SET_XFLG(GET_CFLG());
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(srca + 2, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, srca + 2, 0x1, newv, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(srca, newv >> 16); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, srca + 0, 0x1, newv >> 16, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (3/2) */
/* 2 0,0   */

/* NEGX.L -(An) */
uae_u32 REGPARAM2 op_40a0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 16;
	CurrentInstrCycles = 22; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - 4;
	if (srca & 1) {
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception3_read_access(opcode, srca, 2, 1);
		return 2 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) = srca;
	uae_u32 newv = 0 - src - (GET_XFLG() ? 1 : 0);
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(0)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_VFLG((flgs ^ flgo) & (flgo ^ flgn));
	SET_CFLG(flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
	COPY_CARRY();
	SET_ZFLG(GET_ZFLG() & (((uae_s32)(newv)) == 0));
	SET_NFLG(((uae_s32)(newv)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		int bflgs = ((uae_s16)(src)) < 0;
		int bflgo = ((uae_s16)(0)) < 0;
		int bflgn = ((uae_s16)(newv)) < 0;
		SET_VFLG((bflgs ^ bflgo) & (bflgo ^ bflgn));
		SET_CFLG(bflgs ^ ((bflgs ^ bflgn) & (bflgo ^ bflgn)));
		SET_ZFLG(GET_ZFLG() & (((uae_s16)(newv)) == 0));
		SET_NFLG(((uae_s16)(newv)) < 0);
		SET_XFLG(GET_CFLG());
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(srca + 2, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, srca + 2, 0x1, newv, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(srca, newv >> 16); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, srca + 0, 0x1, newv >> 16, 1);
		return 22 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 22 * CYCLE_UNIT / 2 + count_cycles;
}
/* 22 (3/2) */
/* 2 0,0   */

/* NEGX.L (d16,An) */
uae_u32 REGPARAM2 op_40a8_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 16;
	CurrentInstrCycles = 24; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 newv = 0 - src - (GET_XFLG() ? 1 : 0);
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(0)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_VFLG((flgs ^ flgo) & (flgo ^ flgn));
	SET_CFLG(flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
	COPY_CARRY();
	SET_ZFLG(GET_ZFLG() & (((uae_s32)(newv)) == 0));
	SET_NFLG(((uae_s32)(newv)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		int bflgs = ((uae_s16)(src)) < 0;
		int bflgo = ((uae_s16)(0)) < 0;
		int bflgn = ((uae_s16)(newv)) < 0;
		SET_VFLG((bflgs ^ bflgo) & (bflgo ^ bflgn));
		SET_CFLG(bflgs ^ ((bflgs ^ bflgn) & (bflgo ^ bflgn)));
		SET_ZFLG(GET_ZFLG() & (((uae_s16)(newv)) == 0));
		SET_NFLG(((uae_s16)(newv)) < 0);
		SET_XFLG(GET_CFLG());
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(srca + 2, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, srca + 2, 0x1, newv, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(srca, newv >> 16); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, srca + 0, 0x1, newv >> 16, 1);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 24 * CYCLE_UNIT / 2 + count_cycles;
}
/* 24 (4/2) */
/* 4 0,0   */

/* NEGX.L (d8,An,Xn) */
uae_u32 REGPARAM2 op_40b0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 16;
	CurrentInstrCycles = 26; 
	uaecptr srca;
	BusCyclePenalty += 2;
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 newv = 0 - src - (GET_XFLG() ? 1 : 0);
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(0)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_VFLG((flgs ^ flgo) & (flgo ^ flgn));
	SET_CFLG(flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
	COPY_CARRY();
	SET_ZFLG(GET_ZFLG() & (((uae_s32)(newv)) == 0));
	SET_NFLG(((uae_s32)(newv)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		int bflgs = ((uae_s16)(src)) < 0;
		int bflgo = ((uae_s16)(0)) < 0;
		int bflgn = ((uae_s16)(newv)) < 0;
		SET_VFLG((bflgs ^ bflgo) & (bflgo ^ bflgn));
		SET_CFLG(bflgs ^ ((bflgs ^ bflgn) & (bflgo ^ bflgn)));
		SET_ZFLG(GET_ZFLG() & (((uae_s16)(newv)) == 0));
		SET_NFLG(((uae_s16)(newv)) < 0);
		SET_XFLG(GET_CFLG());
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(srca + 2, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, srca + 2, 0x1, newv, 1);
		return 22 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(srca, newv >> 16); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, srca + 0, 0x1, newv >> 16, 1);
		return 26 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 26 * CYCLE_UNIT / 2 + count_cycles;
}
/* 26 (4/2) */
/* 4 4,0   */

/* NEGX.L (xxx).W */
uae_u32 REGPARAM2 op_40b8_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 16;
	CurrentInstrCycles = 24; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, srca, 2, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 newv = 0 - src - (GET_XFLG() ? 1 : 0);
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(0)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_VFLG((flgs ^ flgo) & (flgo ^ flgn));
	SET_CFLG(flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
	COPY_CARRY();
	SET_ZFLG(GET_ZFLG() & (((uae_s32)(newv)) == 0));
	SET_NFLG(((uae_s32)(newv)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		int bflgs = ((uae_s16)(src)) < 0;
		int bflgo = ((uae_s16)(0)) < 0;
		int bflgn = ((uae_s16)(newv)) < 0;
		SET_VFLG((bflgs ^ bflgo) & (bflgo ^ bflgn));
		SET_CFLG(bflgs ^ ((bflgs ^ bflgn) & (bflgo ^ bflgn)));
		SET_ZFLG(GET_ZFLG() & (((uae_s16)(newv)) == 0));
		SET_NFLG(((uae_s16)(newv)) < 0);
		SET_XFLG(GET_CFLG());
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(srca + 2, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, srca + 2, 0x1, newv, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(srca, newv >> 16); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, srca + 0, 0x1, newv >> 16, 1);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 24 * CYCLE_UNIT / 2 + count_cycles;
}
/* 24 (4/2) */
/* 4 0,0   */

/* NEGX.L (xxx).L */
uae_u32 REGPARAM2 op_40b9_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 16;
	CurrentInstrCycles = 28; 
	uaecptr srca;
	srca = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	srca |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, srca, 2, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 newv = 0 - src - (GET_XFLG() ? 1 : 0);
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(0)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_VFLG((flgs ^ flgo) & (flgo ^ flgn));
	SET_CFLG(flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
	COPY_CARRY();
	SET_ZFLG(GET_ZFLG() & (((uae_s32)(newv)) == 0));
	SET_NFLG(((uae_s32)(newv)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		int bflgs = ((uae_s16)(src)) < 0;
		int bflgo = ((uae_s16)(0)) < 0;
		int bflgn = ((uae_s16)(newv)) < 0;
		SET_VFLG((bflgs ^ bflgo) & (bflgo ^ bflgn));
		SET_CFLG(bflgs ^ ((bflgs ^ bflgn) & (bflgo ^ bflgn)));
		SET_ZFLG(GET_ZFLG() & (((uae_s16)(newv)) == 0));
		SET_NFLG(((uae_s16)(newv)) < 0);
		SET_XFLG(GET_CFLG());
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(srca + 2, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, srca + 2, 0x1, newv, 1);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(srca, newv >> 16); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, srca + 0, 0x1, newv >> 16, 1);
		return 28 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 28 * CYCLE_UNIT / 2 + count_cycles;
}
/* 28 (5/2) */
/* 6 0,0   */

/* MVSR2.W Dn */
uae_u32 REGPARAM2 op_40c0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 32;
	CurrentInstrCycles = 6;  
	MakeSR();
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		MakeSR();
		m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | ((regs.sr) & 0xffff);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | ((regs.sr) & 0xffff);
	m68k_incpci(2);
	return 6 * CYCLE_UNIT / 2 + count_cycles;
}
/* 6 (1/0) */
/* 2 0,0   */

/* MVSR2.W (An) */
uae_u32 REGPARAM2 op_40d0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 32;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	MakeSR();
	get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_word_000(srca, regs.sr);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x1, regs.sr, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (1/2) */
/* 2 0,0   */

/* MVSR2.W (An)+ */
uae_u32 REGPARAM2 op_40d8_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 32;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) += 2;
	MakeSR();
	get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_word_000(srca, regs.sr);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x1, regs.sr, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (1/2) */
/* 2 0,0   */

/* MVSR2.W -(An) */
uae_u32 REGPARAM2 op_40e0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 32;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - 2;
	if (srca & 1) {
		m68k_incpci(4);
		m68k_areg(regs, srcreg) = srca;
		exception3_read_access(opcode, srca, 1, 1);
		return 2 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) = srca;
	MakeSR();
	get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_word_000(srca, regs.sr);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x1, regs.sr, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 14 * CYCLE_UNIT / 2 + count_cycles;
}
/* 14 (1/2) */
/* 2 0,0   */

/* MVSR2.W (d16,An) */
uae_u32 REGPARAM2 op_40e8_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 32;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	MakeSR();
	get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_word_000(srca, regs.sr);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x1, regs.sr, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (2/2) */
/* 4 0,0   */

/* MVSR2.W (d8,An,Xn) */
uae_u32 REGPARAM2 op_40f0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 32;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	BusCyclePenalty += 2;
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	MakeSR();
	get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_word_000(srca, regs.sr);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x1, regs.sr, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (2/2) */
/* 4 4,0   */

/* MVSR2.W (xxx).W */
uae_u32 REGPARAM2 op_40f8_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 32;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, srca, 1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	MakeSR();
	get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_word_000(srca, regs.sr);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x1, regs.sr, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (2/2) */
/* 4 0,0   */

/* MVSR2.W (xxx).L */
uae_u32 REGPARAM2 op_40f9_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 32;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	srca = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	srca |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, srca, 1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	MakeSR();
	get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_word_000(srca, regs.sr);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x1, regs.sr, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (3/2) */
/* 6 0,0   */

/* CHK.W Dn,Dn */
uae_u32 REGPARAM2 op_4180_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 80;
	CurrentInstrCycles = 10; 
	uae_s16 src = m68k_dreg(regs, srcreg);
	uae_s16 dst = m68k_dreg(regs, dstreg);
	m68k_incpci(2);
	if (dst > src) {
		setchkundefinedflags(src, dst, 1);
		Exception_cpu(6);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if ((uae_s32)dst < 0) {
		setchkundefinedflags(src, dst, 1);
		Exception_cpu(6);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	setchkundefinedflags(src, dst, 1);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 10 * CYCLE_UNIT / 2 + count_cycles;
}
/* 10 (1/0) */
/* 2 0,0   */

/* CHK.W (An),Dn */
uae_u32 REGPARAM2 op_4190_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 80;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	m68k_incpci(2);
	if (dst > src) {
		setchkundefinedflags(src, dst, 1);
		Exception_cpu(6);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	if ((uae_s32)dst < 0) {
		setchkundefinedflags(src, dst, 1);
		Exception_cpu(6);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	setchkundefinedflags(src, dst, 1);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 14 * CYCLE_UNIT / 2 + count_cycles;
}
/* 14 (2/0) */
/* 2 0,0   */

/* CHK.W (An)+,Dn */
uae_u32 REGPARAM2 op_4198_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 80;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) += 2 + 0;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) += 2;
	uae_s16 dst = m68k_dreg(regs, dstreg);
	m68k_incpci(2);
	if (dst > src) {
		setchkundefinedflags(src, dst, 1);
		Exception_cpu(6);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	if ((uae_s32)dst < 0) {
		setchkundefinedflags(src, dst, 1);
		Exception_cpu(6);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	setchkundefinedflags(src, dst, 1);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 14 * CYCLE_UNIT / 2 + count_cycles;
}
/* 14 (2/0) */
/* 2 0,0   */

/* CHK.W -(An),Dn */
uae_u32 REGPARAM2 op_41a0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 80;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - 2;
	if (srca & 1) {
		m68k_incpci(4);
		m68k_areg(regs, srcreg) = srca;
		exception3_read_access(opcode, srca, 1, 1);
		return 2 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) = srca;
	uae_s16 dst = m68k_dreg(regs, dstreg);
	m68k_incpci(2);
	if (dst > src) {
		setchkundefinedflags(src, dst, 1);
		Exception_cpu(6);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	if ((uae_s32)dst < 0) {
		setchkundefinedflags(src, dst, 1);
		Exception_cpu(6);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	setchkundefinedflags(src, dst, 1);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (2/0) */
/* 2 0,0   */

/* CHK.W (d16,An),Dn */
uae_u32 REGPARAM2 op_41a8_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 80;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	m68k_incpci(4);
	if (dst > src) {
		setchkundefinedflags(src, dst, 1);
		Exception_cpu(6);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	if ((uae_s32)dst < 0) {
		setchkundefinedflags(src, dst, 1);
		Exception_cpu(6);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	setchkundefinedflags(src, dst, 1);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (3/0) */
/* 4 0,0   */

/* CHK.W (d8,An,Xn),Dn */
uae_u32 REGPARAM2 op_41b0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 80;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	BusCyclePenalty += 2;
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	m68k_incpci(4);
	if (dst > src) {
		setchkundefinedflags(src, dst, 1);
		Exception_cpu(6);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	if ((uae_s32)dst < 0) {
		setchkundefinedflags(src, dst, 1);
		Exception_cpu(6);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	setchkundefinedflags(src, dst, 1);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (3/0) */
/* 4 4,0   */

/* CHK.W (xxx).W,Dn */
uae_u32 REGPARAM2 op_41b8_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 80;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, srca, 1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	m68k_incpci(4);
	if (dst > src) {
		setchkundefinedflags(src, dst, 1);
		Exception_cpu(6);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	if ((uae_s32)dst < 0) {
		setchkundefinedflags(src, dst, 1);
		Exception_cpu(6);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	setchkundefinedflags(src, dst, 1);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (3/0) */
/* 4 0,0   */

/* CHK.W (xxx).L,Dn */
uae_u32 REGPARAM2 op_41b9_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 80;
	CurrentInstrCycles = 22; 
	uaecptr srca;
	srca = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	srca |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, srca, 1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	m68k_incpci(6);
	if (dst > src) {
		setchkundefinedflags(src, dst, 1);
		Exception_cpu(6);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	if ((uae_s32)dst < 0) {
		setchkundefinedflags(src, dst, 1);
		Exception_cpu(6);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	setchkundefinedflags(src, dst, 1);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 22 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 22 * CYCLE_UNIT / 2 + count_cycles;
}
/* 22 (4/0) */
/* 6 0,0   */

/* CHK.W (d16,PC),Dn */
uae_u32 REGPARAM2 op_41ba_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 80;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	srca = m68k_getpci() + 2;
	srca += (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	m68k_incpci(4);
	if (dst > src) {
		setchkundefinedflags(src, dst, 1);
		Exception_cpu(6);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	if ((uae_s32)dst < 0) {
		setchkundefinedflags(src, dst, 1);
		Exception_cpu(6);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	setchkundefinedflags(src, dst, 1);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (3/0) */
/* 4 0,0   */

/* CHK.W (d8,PC,Xn),Dn */
uae_u32 REGPARAM2 op_41bb_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 80;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	uaecptr tmppc = m68k_getpci() + 2;
	BusCyclePenalty += 2;
	srca = get_disp_ea_000(tmppc, get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	m68k_incpci(4);
	if (dst > src) {
		setchkundefinedflags(src, dst, 1);
		Exception_cpu(6);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	if ((uae_s32)dst < 0) {
		setchkundefinedflags(src, dst, 1);
		Exception_cpu(6);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	setchkundefinedflags(src, dst, 1);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (3/0) */
/* 4 4,0   */

/* CHK.W #<data>.W,Dn */
uae_u32 REGPARAM2 op_41bc_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 80;
	CurrentInstrCycles = 14; 
	uae_s16 src = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	m68k_incpci(4);
	if (dst > src) {
		setchkundefinedflags(src, dst, 1);
		Exception_cpu(6);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	if ((uae_s32)dst < 0) {
		setchkundefinedflags(src, dst, 1);
		Exception_cpu(6);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	setchkundefinedflags(src, dst, 1);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 14 * CYCLE_UNIT / 2 + count_cycles;
}
/* 14 (2/0) */
/* 4 0,0   */

/* LEA.L (An),An */
uae_u32 REGPARAM2 op_41d0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 56;
	CurrentInstrCycles = 4;  
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	m68k_areg(regs, dstreg) = (srca);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		m68k_areg(regs, dstreg) = (srca);
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 4 * CYCLE_UNIT / 2 + count_cycles;
}
/* 4 (1/0) */
/* 2 0,0   */

/* LEA.L (d16,An),An */
uae_u32 REGPARAM2 op_41e8_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 56;
	CurrentInstrCycles = 8;  
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		m68k_areg(regs, dstreg) = (srca);
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) = (srca);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8 (2/0) */
/* 4 0,0   */

/* LEA.L (d8,An,Xn),An */
uae_u32 REGPARAM2 op_41f0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 56;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) = (srca);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 14 * CYCLE_UNIT / 2 + count_cycles;
}
/* 14 (2/0) */
/* 4 4,0   */

/* LEA.L (xxx).W,An */
uae_u32 REGPARAM2 op_41f8_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 56;
	CurrentInstrCycles = 8;  
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		m68k_areg(regs, dstreg) = (srca);
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) = (srca);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8 (2/0) */
/* 4 0,0   */

/* LEA.L (xxx).L,An */
uae_u32 REGPARAM2 op_41f9_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 56;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		m68k_areg(regs, dstreg) = (m68k_areg(regs, dstreg) & 0x0000ffff) | (srca & 0xffff0000);
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	srca |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		m68k_areg(regs, dstreg) = (srca);
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) = (srca);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (3/0) */
/* 6 0,0   */

/* LEA.L (d16,PC),An */
uae_u32 REGPARAM2 op_41fa_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 56;
	CurrentInstrCycles = 8;  
	uaecptr srca;
	srca = m68k_getpci() + 2;
	srca += (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		m68k_areg(regs, dstreg) = (srca);
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) = (srca);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8 (2/0) */
/* 4 0,0   */

/* LEA.L (d8,PC,Xn),An */
uae_u32 REGPARAM2 op_41fb_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 56;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	uaecptr tmppc = m68k_getpci() + 2;
	srca = get_disp_ea_000(tmppc, get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) = (srca);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 14 * CYCLE_UNIT / 2 + count_cycles;
}
/* 14 (2/0) */
/* 4 4,0   */

/* CLR.B Dn */
uae_u32 REGPARAM2 op_4200_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 18;
	CurrentInstrCycles = 4;  
	uae_s8 src = m68k_dreg(regs, srcreg);
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(0)) == 0);
	SET_NFLG(((uae_s8)(0)) < 0);
	m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((0) & 0xff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 4 * CYCLE_UNIT / 2 + count_cycles;
}
/* 4 (1/0) */
/* 2 0,0   */

/* CLR.B (An) */
uae_u32 REGPARAM2 op_4210_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 18;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(0)) == 0);
	SET_NFLG(((uae_s8)(0)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_byte_000(srca, 0);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, 0, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (2/1) */
/* 2 0,0   */

/* CLR.B (An)+ */
uae_u32 REGPARAM2 op_4218_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 18;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(0)) == 0);
	SET_NFLG(((uae_s8)(0)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_byte_000(srca, 0);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, 0, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (2/1) */
/* 2 0,0   */

/* CLR.B -(An) */
uae_u32 REGPARAM2 op_4220_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 18;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) = srca;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(0)) == 0);
	SET_NFLG(((uae_s8)(0)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_byte_000(srca, 0);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, 0, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 14 * CYCLE_UNIT / 2 + count_cycles;
}
/* 14 (2/1) */
/* 2 0,0   */

/* CLR.B (d16,An) */
uae_u32 REGPARAM2 op_4228_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 18;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(0)) == 0);
	SET_NFLG(((uae_s8)(0)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_byte_000(srca, 0);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, 0, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 4 0,0   */

/* CLR.B (d8,An,Xn) */
uae_u32 REGPARAM2 op_4230_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 18;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	BusCyclePenalty += 2;
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(0)) == 0);
	SET_NFLG(((uae_s8)(0)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_byte_000(srca, 0);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, 0, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (3/1) */
/* 4 4,0   */

/* CLR.B (xxx).W */
uae_u32 REGPARAM2 op_4238_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 18;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(0)) == 0);
	SET_NFLG(((uae_s8)(0)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_byte_000(srca, 0);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, 0, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 4 0,0   */

/* CLR.B (xxx).L */
uae_u32 REGPARAM2 op_4239_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 18;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	srca = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	srca |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(0)) == 0);
	SET_NFLG(((uae_s8)(0)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_byte_000(srca, 0);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, 0, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (4/1) */
/* 6 0,0   */

/* CLR.W Dn */
uae_u32 REGPARAM2 op_4240_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 18;
	CurrentInstrCycles = 4;  
	uae_s16 src = m68k_dreg(regs, srcreg);
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(0)) == 0);
	SET_NFLG(((uae_s16)(0)) < 0);
	m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | ((0) & 0xffff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 4 * CYCLE_UNIT / 2 + count_cycles;
}
/* 4 (1/0) */
/* 2 0,0   */

/* CLR.W (An) */
uae_u32 REGPARAM2 op_4250_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 18;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(0)) == 0);
	SET_NFLG(((uae_s16)(0)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_word_000(srca, 0);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x1, 0, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (2/1) */
/* 2 0,0   */

/* CLR.W (An)+ */
uae_u32 REGPARAM2 op_4258_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 18;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) += 2 + 0;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) += 2;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(0)) == 0);
	SET_NFLG(((uae_s16)(0)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_word_000(srca, 0);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x1, 0, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (2/1) */
/* 2 0,0   */

/* CLR.W -(An) */
uae_u32 REGPARAM2 op_4260_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 18;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - 2;
	if (srca & 1) {
		m68k_incpci(4);
		m68k_areg(regs, srcreg) = srca;
		exception3_read_access(opcode, srca, 1, 1);
		return 2 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) = srca;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(0)) == 0);
	SET_NFLG(((uae_s16)(0)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_word_000(srca, 0);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x1, 0, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 14 * CYCLE_UNIT / 2 + count_cycles;
}
/* 14 (2/1) */
/* 2 0,0   */

/* CLR.W (d16,An) */
uae_u32 REGPARAM2 op_4268_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 18;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(0)) == 0);
	SET_NFLG(((uae_s16)(0)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_word_000(srca, 0);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x1, 0, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 4 0,0   */

/* CLR.W (d8,An,Xn) */
uae_u32 REGPARAM2 op_4270_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 18;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	BusCyclePenalty += 2;
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(0)) == 0);
	SET_NFLG(((uae_s16)(0)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_word_000(srca, 0);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x1, 0, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (3/1) */
/* 4 4,0   */

/* CLR.W (xxx).W */
uae_u32 REGPARAM2 op_4278_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 18;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, srca, 1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(0)) == 0);
	SET_NFLG(((uae_s16)(0)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_word_000(srca, 0);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x1, 0, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 4 0,0   */

/* CLR.W (xxx).L */
uae_u32 REGPARAM2 op_4279_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 18;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	srca = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	srca |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, srca, 1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(0)) == 0);
	SET_NFLG(((uae_s16)(0)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_word_000(srca, 0);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x1, 0, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (4/1) */
/* 6 0,0   */

/* CLR.L Dn */
uae_u32 REGPARAM2 op_4280_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 18;
	CurrentInstrCycles = 6;  
	uae_s32 src = m68k_dreg(regs, srcreg);
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(0)) == 0);
	SET_NFLG(((uae_s32)(0)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		m68k_dreg(regs, srcreg) = (src & 0xffff0000);
		SET_VFLG(0);SET_ZFLG(1);SET_NFLG(0);SET_CFLG(0);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	m68k_dreg(regs, srcreg) = (0);
	m68k_incpci(2);
	return 6 * CYCLE_UNIT / 2 + count_cycles;
}
/* 6 (1/0) */
/* 2 0,0   */

/* CLR.L (An) */
uae_u32 REGPARAM2 op_4290_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 18;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(0)) == 0);
	SET_NFLG(((uae_s32)(0)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		SET_VFLG(0);SET_ZFLG(1);SET_NFLG(0);SET_CFLG(0);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(srca + 2, 0);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, srca + 2, 0x1, 0, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(srca, 0 >> 16); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, srca + 0, 0x1, 0 >> 16, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (3/2) */
/* 2 0,0   */

/* CLR.L (An)+ */
uae_u32 REGPARAM2 op_4298_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 18;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) += 4;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(0)) == 0);
	SET_NFLG(((uae_s32)(0)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		SET_VFLG(0);SET_ZFLG(1);SET_NFLG(0);SET_CFLG(0);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(srca + 2, 0);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, srca + 2, 0x1, 0, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(srca, 0 >> 16); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, srca + 0, 0x1, 0 >> 16, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (3/2) */
/* 2 0,0   */

/* CLR.L -(An) */
uae_u32 REGPARAM2 op_42a0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 18;
	CurrentInstrCycles = 22; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - 4;
	if (srca & 1) {
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception3_read_access(opcode, srca, 2, 1);
		return 2 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) = srca;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(0)) == 0);
	SET_NFLG(((uae_s32)(0)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		SET_VFLG(0);SET_ZFLG(1);SET_NFLG(0);SET_CFLG(0);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(srca + 2, 0);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, srca + 2, 0x1, 0, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(srca, 0 >> 16); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, srca + 0, 0x1, 0 >> 16, 1);
		return 22 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 22 * CYCLE_UNIT / 2 + count_cycles;
}
/* 22 (3/2) */
/* 2 0,0   */

/* CLR.L (d16,An) */
uae_u32 REGPARAM2 op_42a8_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 18;
	CurrentInstrCycles = 24; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(0)) == 0);
	SET_NFLG(((uae_s32)(0)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		SET_VFLG(0);SET_ZFLG(1);SET_NFLG(0);SET_CFLG(0);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(srca + 2, 0);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, srca + 2, 0x1, 0, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(srca, 0 >> 16); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, srca + 0, 0x1, 0 >> 16, 1);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 24 * CYCLE_UNIT / 2 + count_cycles;
}
/* 24 (4/2) */
/* 4 0,0   */

/* CLR.L (d8,An,Xn) */
uae_u32 REGPARAM2 op_42b0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 18;
	CurrentInstrCycles = 26; 
	uaecptr srca;
	BusCyclePenalty += 2;
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(0)) == 0);
	SET_NFLG(((uae_s32)(0)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		SET_VFLG(0);SET_ZFLG(1);SET_NFLG(0);SET_CFLG(0);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(srca + 2, 0);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, srca + 2, 0x1, 0, 1);
		return 22 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(srca, 0 >> 16); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, srca + 0, 0x1, 0 >> 16, 1);
		return 26 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 26 * CYCLE_UNIT / 2 + count_cycles;
}
/* 26 (4/2) */
/* 4 4,0   */

/* CLR.L (xxx).W */
uae_u32 REGPARAM2 op_42b8_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 18;
	CurrentInstrCycles = 24; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, srca, 2, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(0)) == 0);
	SET_NFLG(((uae_s32)(0)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		SET_VFLG(0);SET_ZFLG(1);SET_NFLG(0);SET_CFLG(0);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(srca + 2, 0);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, srca + 2, 0x1, 0, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(srca, 0 >> 16); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, srca + 0, 0x1, 0 >> 16, 1);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 24 * CYCLE_UNIT / 2 + count_cycles;
}
/* 24 (4/2) */
/* 4 0,0   */

/* CLR.L (xxx).L */
uae_u32 REGPARAM2 op_42b9_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 18;
	CurrentInstrCycles = 28; 
	uaecptr srca;
	srca = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	srca |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, srca, 2, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(0)) == 0);
	SET_NFLG(((uae_s32)(0)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		SET_VFLG(0);SET_ZFLG(1);SET_NFLG(0);SET_CFLG(0);
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(srca + 2, 0);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, srca + 2, 0x1, 0, 1);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(srca, 0 >> 16); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, srca + 0, 0x1, 0 >> 16, 1);
		return 28 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 28 * CYCLE_UNIT / 2 + count_cycles;
}
/* 28 (5/2) */
/* 6 0,0   */

/* NEG.B Dn */
uae_u32 REGPARAM2 op_4400_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 15;
	CurrentInstrCycles = 4;  
	uae_s8 src = m68k_dreg(regs, srcreg);
	uae_u32 dst = ((uae_u8)(0)) - ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(0)) < 0;
	int flgn = ((uae_s8)(dst)) < 0;
	SET_ZFLG(((uae_s8)(dst)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u8)(src)) > ((uae_u8)(0)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((dst) & 0xff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 4 * CYCLE_UNIT / 2 + count_cycles;
}
/* 4 (1/0) */
/* 2 0,0   */

/* NEG.B (An) */
uae_u32 REGPARAM2 op_4410_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 15;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 dst = ((uae_u8)(0)) - ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(0)) < 0;
	int flgn = ((uae_s8)(dst)) < 0;
	SET_ZFLG(((uae_s8)(dst)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u8)(src)) > ((uae_u8)(0)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_byte_000(srca, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, dst, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (2/1) */
/* 2 0,0   */

/* NEG.B (An)+ */
uae_u32 REGPARAM2 op_4418_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 15;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
	uae_u32 dst = ((uae_u8)(0)) - ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(0)) < 0;
	int flgn = ((uae_s8)(dst)) < 0;
	SET_ZFLG(((uae_s8)(dst)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u8)(src)) > ((uae_u8)(0)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_byte_000(srca, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, dst, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (2/1) */
/* 2 0,0   */

/* NEG.B -(An) */
uae_u32 REGPARAM2 op_4420_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 15;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) = srca;
	uae_u32 dst = ((uae_u8)(0)) - ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(0)) < 0;
	int flgn = ((uae_s8)(dst)) < 0;
	SET_ZFLG(((uae_s8)(dst)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u8)(src)) > ((uae_u8)(0)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_byte_000(srca, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, dst, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 14 * CYCLE_UNIT / 2 + count_cycles;
}
/* 14 (2/1) */
/* 2 0,0   */

/* NEG.B (d16,An) */
uae_u32 REGPARAM2 op_4428_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 15;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 dst = ((uae_u8)(0)) - ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(0)) < 0;
	int flgn = ((uae_s8)(dst)) < 0;
	SET_ZFLG(((uae_s8)(dst)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u8)(src)) > ((uae_u8)(0)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_byte_000(srca, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, dst, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 4 0,0   */

/* NEG.B (d8,An,Xn) */
uae_u32 REGPARAM2 op_4430_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 15;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	BusCyclePenalty += 2;
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 dst = ((uae_u8)(0)) - ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(0)) < 0;
	int flgn = ((uae_s8)(dst)) < 0;
	SET_ZFLG(((uae_s8)(dst)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u8)(src)) > ((uae_u8)(0)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_byte_000(srca, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, dst, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (3/1) */
/* 4 4,0   */

/* NEG.B (xxx).W */
uae_u32 REGPARAM2 op_4438_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 15;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 dst = ((uae_u8)(0)) - ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(0)) < 0;
	int flgn = ((uae_s8)(dst)) < 0;
	SET_ZFLG(((uae_s8)(dst)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u8)(src)) > ((uae_u8)(0)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_byte_000(srca, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, dst, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 4 0,0   */

/* NEG.B (xxx).L */
uae_u32 REGPARAM2 op_4439_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 15;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	srca = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	srca |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 dst = ((uae_u8)(0)) - ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(0)) < 0;
	int flgn = ((uae_s8)(dst)) < 0;
	SET_ZFLG(((uae_s8)(dst)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u8)(src)) > ((uae_u8)(0)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_byte_000(srca, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, dst, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (4/1) */
/* 6 0,0   */

/* NEG.W Dn */
uae_u32 REGPARAM2 op_4440_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 15;
	CurrentInstrCycles = 4;  
	uae_s16 src = m68k_dreg(regs, srcreg);
	uae_u32 dst = ((uae_u16)(0)) - ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(0)) < 0;
	int flgn = ((uae_s16)(dst)) < 0;
	SET_ZFLG(((uae_s16)(dst)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u16)(src)) > ((uae_u16)(0)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | ((dst) & 0xffff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 4 * CYCLE_UNIT / 2 + count_cycles;
}
/* 4 (1/0) */
/* 2 0,0   */

/* NEG.W (An) */
uae_u32 REGPARAM2 op_4450_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 15;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 dst = ((uae_u16)(0)) - ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(0)) < 0;
	int flgn = ((uae_s16)(dst)) < 0;
	SET_ZFLG(((uae_s16)(dst)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u16)(src)) > ((uae_u16)(0)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_word_000(srca, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x1, dst, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (2/1) */
/* 2 0,0   */

/* NEG.W (An)+ */
uae_u32 REGPARAM2 op_4458_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 15;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) += 2 + 0;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) += 2;
	uae_u32 dst = ((uae_u16)(0)) - ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(0)) < 0;
	int flgn = ((uae_s16)(dst)) < 0;
	SET_ZFLG(((uae_s16)(dst)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u16)(src)) > ((uae_u16)(0)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_word_000(srca, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x1, dst, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (2/1) */
/* 2 0,0   */

/* NEG.W -(An) */
uae_u32 REGPARAM2 op_4460_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 15;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - 2;
	if (srca & 1) {
		m68k_incpci(4);
		m68k_areg(regs, srcreg) = srca;
		exception3_read_access(opcode, srca, 1, 1);
		return 2 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) = srca;
	uae_u32 dst = ((uae_u16)(0)) - ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(0)) < 0;
	int flgn = ((uae_s16)(dst)) < 0;
	SET_ZFLG(((uae_s16)(dst)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u16)(src)) > ((uae_u16)(0)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_word_000(srca, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x1, dst, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 14 * CYCLE_UNIT / 2 + count_cycles;
}
/* 14 (2/1) */
/* 2 0,0   */

/* NEG.W (d16,An) */
uae_u32 REGPARAM2 op_4468_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 15;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 dst = ((uae_u16)(0)) - ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(0)) < 0;
	int flgn = ((uae_s16)(dst)) < 0;
	SET_ZFLG(((uae_s16)(dst)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u16)(src)) > ((uae_u16)(0)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_word_000(srca, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x1, dst, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 4 0,0   */

/* NEG.W (d8,An,Xn) */
uae_u32 REGPARAM2 op_4470_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 15;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	BusCyclePenalty += 2;
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 dst = ((uae_u16)(0)) - ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(0)) < 0;
	int flgn = ((uae_s16)(dst)) < 0;
	SET_ZFLG(((uae_s16)(dst)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u16)(src)) > ((uae_u16)(0)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_word_000(srca, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x1, dst, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (3/1) */
/* 4 4,0   */

/* NEG.W (xxx).W */
uae_u32 REGPARAM2 op_4478_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 15;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, srca, 1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 dst = ((uae_u16)(0)) - ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(0)) < 0;
	int flgn = ((uae_s16)(dst)) < 0;
	SET_ZFLG(((uae_s16)(dst)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u16)(src)) > ((uae_u16)(0)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_word_000(srca, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x1, dst, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 4 0,0   */

/* NEG.W (xxx).L */
uae_u32 REGPARAM2 op_4479_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 15;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	srca = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	srca |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, srca, 1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 dst = ((uae_u16)(0)) - ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(0)) < 0;
	int flgn = ((uae_s16)(dst)) < 0;
	SET_ZFLG(((uae_s16)(dst)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u16)(src)) > ((uae_u16)(0)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_word_000(srca, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x1, dst, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (4/1) */
/* 6 0,0   */

/* NEG.L Dn */
uae_u32 REGPARAM2 op_4480_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 15;
	CurrentInstrCycles = 6;  
	uae_s32 src = m68k_dreg(regs, srcreg);
	uae_u32 dst = ((uae_u32)(0)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(0)) < 0;
	int flgn = ((uae_s32)(dst)) < 0;
	SET_ZFLG(((uae_s32)(dst)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(0)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		dreg_68000_long_replace_low(srcreg, dst);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	m68k_dreg(regs, srcreg) = (dst);
	m68k_incpci(2);
	return 6 * CYCLE_UNIT / 2 + count_cycles;
}
/* 6 (1/0) */
/* 2 0,0   */

/* NEG.L (An) */
uae_u32 REGPARAM2 op_4490_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 15;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 dst = ((uae_u32)(0)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(0)) < 0;
	int flgn = ((uae_s32)(dst)) < 0;
	SET_ZFLG(((uae_s32)(dst)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(0)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		int bflgs = ((uae_s16)(src)) < 0;
		int bflgo = ((uae_s16)(0)) < 0;
		int bflgn = ((uae_s16)(dst)) < 0;
		SET_ZFLG(((uae_s16)(dst)) == 0);
		SET_VFLG((bflgs ^ bflgo) & (bflgn ^ bflgo));
		SET_CFLG(((uae_u16)(src)) > ((uae_u16)(0)));
		SET_NFLG(bflgn != 0);
		SET_XFLG(GET_CFLG());
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(srca + 2, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, srca + 2, 0x1, dst, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(srca, dst >> 16); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, srca + 0, 0x1, dst >> 16, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (3/2) */
/* 2 0,0   */

/* NEG.L (An)+ */
uae_u32 REGPARAM2 op_4498_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 15;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) += 4;
	uae_u32 dst = ((uae_u32)(0)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(0)) < 0;
	int flgn = ((uae_s32)(dst)) < 0;
	SET_ZFLG(((uae_s32)(dst)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(0)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		int bflgs = ((uae_s16)(src)) < 0;
		int bflgo = ((uae_s16)(0)) < 0;
		int bflgn = ((uae_s16)(dst)) < 0;
		SET_ZFLG(((uae_s16)(dst)) == 0);
		SET_VFLG((bflgs ^ bflgo) & (bflgn ^ bflgo));
		SET_CFLG(((uae_u16)(src)) > ((uae_u16)(0)));
		SET_NFLG(bflgn != 0);
		SET_XFLG(GET_CFLG());
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(srca + 2, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, srca + 2, 0x1, dst, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(srca, dst >> 16); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, srca + 0, 0x1, dst >> 16, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (3/2) */
/* 2 0,0   */

/* NEG.L -(An) */
uae_u32 REGPARAM2 op_44a0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 15;
	CurrentInstrCycles = 22; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - 4;
	if (srca & 1) {
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception3_read_access(opcode, srca, 2, 1);
		return 2 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) = srca;
	uae_u32 dst = ((uae_u32)(0)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(0)) < 0;
	int flgn = ((uae_s32)(dst)) < 0;
	SET_ZFLG(((uae_s32)(dst)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(0)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		int bflgs = ((uae_s16)(src)) < 0;
		int bflgo = ((uae_s16)(0)) < 0;
		int bflgn = ((uae_s16)(dst)) < 0;
		SET_ZFLG(((uae_s16)(dst)) == 0);
		SET_VFLG((bflgs ^ bflgo) & (bflgn ^ bflgo));
		SET_CFLG(((uae_u16)(src)) > ((uae_u16)(0)));
		SET_NFLG(bflgn != 0);
		SET_XFLG(GET_CFLG());
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(srca + 2, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, srca + 2, 0x1, dst, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(srca, dst >> 16); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, srca + 0, 0x1, dst >> 16, 1);
		return 22 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 22 * CYCLE_UNIT / 2 + count_cycles;
}
/* 22 (3/2) */
/* 2 0,0   */

/* NEG.L (d16,An) */
uae_u32 REGPARAM2 op_44a8_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 15;
	CurrentInstrCycles = 24; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 dst = ((uae_u32)(0)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(0)) < 0;
	int flgn = ((uae_s32)(dst)) < 0;
	SET_ZFLG(((uae_s32)(dst)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(0)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		int bflgs = ((uae_s16)(src)) < 0;
		int bflgo = ((uae_s16)(0)) < 0;
		int bflgn = ((uae_s16)(dst)) < 0;
		SET_ZFLG(((uae_s16)(dst)) == 0);
		SET_VFLG((bflgs ^ bflgo) & (bflgn ^ bflgo));
		SET_CFLG(((uae_u16)(src)) > ((uae_u16)(0)));
		SET_NFLG(bflgn != 0);
		SET_XFLG(GET_CFLG());
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(srca + 2, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, srca + 2, 0x1, dst, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(srca, dst >> 16); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, srca + 0, 0x1, dst >> 16, 1);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 24 * CYCLE_UNIT / 2 + count_cycles;
}
/* 24 (4/2) */
/* 4 0,0   */

/* NEG.L (d8,An,Xn) */
uae_u32 REGPARAM2 op_44b0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 15;
	CurrentInstrCycles = 26; 
	uaecptr srca;
	BusCyclePenalty += 2;
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 dst = ((uae_u32)(0)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(0)) < 0;
	int flgn = ((uae_s32)(dst)) < 0;
	SET_ZFLG(((uae_s32)(dst)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(0)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		int bflgs = ((uae_s16)(src)) < 0;
		int bflgo = ((uae_s16)(0)) < 0;
		int bflgn = ((uae_s16)(dst)) < 0;
		SET_ZFLG(((uae_s16)(dst)) == 0);
		SET_VFLG((bflgs ^ bflgo) & (bflgn ^ bflgo));
		SET_CFLG(((uae_u16)(src)) > ((uae_u16)(0)));
		SET_NFLG(bflgn != 0);
		SET_XFLG(GET_CFLG());
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(srca + 2, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, srca + 2, 0x1, dst, 1);
		return 22 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(srca, dst >> 16); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, srca + 0, 0x1, dst >> 16, 1);
		return 26 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 26 * CYCLE_UNIT / 2 + count_cycles;
}
/* 26 (4/2) */
/* 4 4,0   */

/* NEG.L (xxx).W */
uae_u32 REGPARAM2 op_44b8_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 15;
	CurrentInstrCycles = 24; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, srca, 2, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 dst = ((uae_u32)(0)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(0)) < 0;
	int flgn = ((uae_s32)(dst)) < 0;
	SET_ZFLG(((uae_s32)(dst)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(0)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		int bflgs = ((uae_s16)(src)) < 0;
		int bflgo = ((uae_s16)(0)) < 0;
		int bflgn = ((uae_s16)(dst)) < 0;
		SET_ZFLG(((uae_s16)(dst)) == 0);
		SET_VFLG((bflgs ^ bflgo) & (bflgn ^ bflgo));
		SET_CFLG(((uae_u16)(src)) > ((uae_u16)(0)));
		SET_NFLG(bflgn != 0);
		SET_XFLG(GET_CFLG());
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(srca + 2, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, srca + 2, 0x1, dst, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(srca, dst >> 16); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, srca + 0, 0x1, dst >> 16, 1);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 24 * CYCLE_UNIT / 2 + count_cycles;
}
/* 24 (4/2) */
/* 4 0,0   */

/* NEG.L (xxx).L */
uae_u32 REGPARAM2 op_44b9_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 15;
	CurrentInstrCycles = 28; 
	uaecptr srca;
	srca = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	srca |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, srca, 2, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 dst = ((uae_u32)(0)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(0)) < 0;
	int flgn = ((uae_s32)(dst)) < 0;
	SET_ZFLG(((uae_s32)(dst)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(0)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		int bflgs = ((uae_s16)(src)) < 0;
		int bflgo = ((uae_s16)(0)) < 0;
		int bflgn = ((uae_s16)(dst)) < 0;
		SET_ZFLG(((uae_s16)(dst)) == 0);
		SET_VFLG((bflgs ^ bflgo) & (bflgn ^ bflgo));
		SET_CFLG(((uae_u16)(src)) > ((uae_u16)(0)));
		SET_NFLG(bflgn != 0);
		SET_XFLG(GET_CFLG());
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(srca + 2, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, srca + 2, 0x1, dst, 1);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(srca, dst >> 16); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, srca + 0, 0x1, dst >> 16, 1);
		return 28 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 28 * CYCLE_UNIT / 2 + count_cycles;
}
/* 28 (5/2) */
/* 6 0,0   */

/* MV2SR.B Dn */
uae_u32 REGPARAM2 op_44c0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 33;
	CurrentInstrCycles = 12; 
	uae_s16 src = m68k_dreg(regs, srcreg);
	int t1 = regs.t1;
	MakeSR();
	regs.sr &= 0xFF00;
	regs.sr |= src & 0xFF;
	MakeFromSR();
	m68k_incpci(2);
	get_word_000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, 0);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	if(t1) opcode |= 0x10000;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (2/0) */
/* 2 0,0   */

/* MV2SR.B (An) */
uae_u32 REGPARAM2 op_44d0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 33;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	int t1 = regs.t1;
	MakeSR();
	regs.sr &= 0xFF00;
	regs.sr |= src & 0xFF;
	MakeFromSR();
	m68k_incpci(2);
	get_word_000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, 0);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	if(t1) opcode |= 0x10000;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/0) */
/* 2 0,0   */

/* MV2SR.B (An)+ */
uae_u32 REGPARAM2 op_44d8_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 33;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) += 2 + 0;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) += 2;
	int t1 = regs.t1;
	MakeSR();
	regs.sr &= 0xFF00;
	regs.sr |= src & 0xFF;
	MakeFromSR();
	m68k_incpci(2);
	get_word_000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, 0);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	if(t1) opcode |= 0x10000;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/0) */
/* 2 0,0   */

/* MV2SR.B -(An) */
uae_u32 REGPARAM2 op_44e0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 33;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - 2;
	if (srca & 1) {
		m68k_incpci(4);
		m68k_areg(regs, srcreg) = srca;
		exception3_read_access(opcode, srca, 1, 1);
		return 2 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) = srca;
	int t1 = regs.t1;
	MakeSR();
	regs.sr &= 0xFF00;
	regs.sr |= src & 0xFF;
	MakeFromSR();
	m68k_incpci(2);
	get_word_000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, 0);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	if(t1) opcode |= 0x10000;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (3/0) */
/* 2 0,0   */

/* MV2SR.B (d16,An) */
uae_u32 REGPARAM2 op_44e8_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 33;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	int t1 = regs.t1;
	MakeSR();
	regs.sr &= 0xFF00;
	regs.sr |= src & 0xFF;
	MakeFromSR();
	m68k_incpci(4);
	get_word_000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, 0);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	if(t1) opcode |= 0x10000;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (4/0) */
/* 4 0,0   */

/* MV2SR.B (d8,An,Xn) */
uae_u32 REGPARAM2 op_44f0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 33;
	CurrentInstrCycles = 22; 
	uaecptr srca;
	BusCyclePenalty += 2;
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	int t1 = regs.t1;
	MakeSR();
	regs.sr &= 0xFF00;
	regs.sr |= src & 0xFF;
	MakeFromSR();
	m68k_incpci(4);
	get_word_000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, 0);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	if(t1) opcode |= 0x10000;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 22 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 22 * CYCLE_UNIT / 2 + count_cycles;
}
/* 22 (4/0) */
/* 4 4,0   */

/* MV2SR.B (xxx).W */
uae_u32 REGPARAM2 op_44f8_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 33;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, srca, 1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	int t1 = regs.t1;
	MakeSR();
	regs.sr &= 0xFF00;
	regs.sr |= src & 0xFF;
	MakeFromSR();
	m68k_incpci(4);
	get_word_000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, 0);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	if(t1) opcode |= 0x10000;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (4/0) */
/* 4 0,0   */

/* MV2SR.B (xxx).L */
uae_u32 REGPARAM2 op_44f9_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 33;
	CurrentInstrCycles = 24; 
	uaecptr srca;
	srca = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	srca |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, srca, 1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	int t1 = regs.t1;
	MakeSR();
	regs.sr &= 0xFF00;
	regs.sr |= src & 0xFF;
	MakeFromSR();
	m68k_incpci(6);
	get_word_000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, 0);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	if(t1) opcode |= 0x10000;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 24 * CYCLE_UNIT / 2 + count_cycles;
}
/* 24 (5/0) */
/* 6 0,0   */

/* MV2SR.B (d16,PC) */
uae_u32 REGPARAM2 op_44fa_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 33;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	srca = m68k_getpci() + 2;
	srca += (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	int t1 = regs.t1;
	MakeSR();
	regs.sr &= 0xFF00;
	regs.sr |= src & 0xFF;
	MakeFromSR();
	m68k_incpci(4);
	get_word_000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, 0);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	if(t1) opcode |= 0x10000;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (4/0) */
/* 4 0,0   */

/* MV2SR.B (d8,PC,Xn) */
uae_u32 REGPARAM2 op_44fb_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 33;
	CurrentInstrCycles = 22; 
	uaecptr srca;
	uaecptr tmppc = m68k_getpci() + 2;
	BusCyclePenalty += 2;
	srca = get_disp_ea_000(tmppc, get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	int t1 = regs.t1;
	MakeSR();
	regs.sr &= 0xFF00;
	regs.sr |= src & 0xFF;
	MakeFromSR();
	m68k_incpci(4);
	get_word_000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, 0);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	if(t1) opcode |= 0x10000;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 22 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 22 * CYCLE_UNIT / 2 + count_cycles;
}
/* 22 (4/0) */
/* 4 4,0   */

/* MV2SR.B #<data>.B */
uae_u32 REGPARAM2 op_44fc_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 33;
	CurrentInstrCycles = 16; 
	uae_s16 src = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	int t1 = regs.t1;
	MakeSR();
	regs.sr &= 0xFF00;
	regs.sr |= src & 0xFF;
	MakeFromSR();
	m68k_incpci(4);
	get_word_000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, 0);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	if(t1) opcode |= 0x10000;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/0) */
/* 4 0,0   */

/* NOT.B Dn */
uae_u32 REGPARAM2 op_4600_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 19;
	CurrentInstrCycles = 4;  
	uae_s8 src = m68k_dreg(regs, srcreg);
	uae_u32 dst = ~src;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(dst)) == 0);
	SET_NFLG(((uae_s8)(dst)) < 0);
	m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((dst) & 0xff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 4 * CYCLE_UNIT / 2 + count_cycles;
}
/* 4 (1/0) */
/* 2 0,0   */

/* NOT.B (An) */
uae_u32 REGPARAM2 op_4610_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 19;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 dst = ~src;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(dst)) == 0);
	SET_NFLG(((uae_s8)(dst)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_byte_000(srca, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, dst, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (2/1) */
/* 2 0,0   */

/* NOT.B (An)+ */
uae_u32 REGPARAM2 op_4618_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 19;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
	uae_u32 dst = ~src;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(dst)) == 0);
	SET_NFLG(((uae_s8)(dst)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_byte_000(srca, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, dst, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (2/1) */
/* 2 0,0   */

/* NOT.B -(An) */
uae_u32 REGPARAM2 op_4620_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 19;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) = srca;
	uae_u32 dst = ~src;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(dst)) == 0);
	SET_NFLG(((uae_s8)(dst)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_byte_000(srca, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, dst, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 14 * CYCLE_UNIT / 2 + count_cycles;
}
/* 14 (2/1) */
/* 2 0,0   */

/* NOT.B (d16,An) */
uae_u32 REGPARAM2 op_4628_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 19;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 dst = ~src;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(dst)) == 0);
	SET_NFLG(((uae_s8)(dst)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_byte_000(srca, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, dst, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 4 0,0   */

/* NOT.B (d8,An,Xn) */
uae_u32 REGPARAM2 op_4630_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 19;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	BusCyclePenalty += 2;
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 dst = ~src;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(dst)) == 0);
	SET_NFLG(((uae_s8)(dst)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_byte_000(srca, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, dst, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (3/1) */
/* 4 4,0   */

/* NOT.B (xxx).W */
uae_u32 REGPARAM2 op_4638_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 19;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 dst = ~src;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(dst)) == 0);
	SET_NFLG(((uae_s8)(dst)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_byte_000(srca, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, dst, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 4 0,0   */

/* NOT.B (xxx).L */
uae_u32 REGPARAM2 op_4639_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 19;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	srca = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	srca |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 dst = ~src;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(dst)) == 0);
	SET_NFLG(((uae_s8)(dst)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_byte_000(srca, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, dst, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (4/1) */
/* 6 0,0   */

/* NOT.W Dn */
uae_u32 REGPARAM2 op_4640_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 19;
	CurrentInstrCycles = 4;  
	uae_s16 src = m68k_dreg(regs, srcreg);
	uae_u32 dst = ~src;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(dst)) == 0);
	SET_NFLG(((uae_s16)(dst)) < 0);
	m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | ((dst) & 0xffff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 4 * CYCLE_UNIT / 2 + count_cycles;
}
/* 4 (1/0) */
/* 2 0,0   */

/* NOT.W (An) */
uae_u32 REGPARAM2 op_4650_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 19;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 dst = ~src;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(dst)) == 0);
	SET_NFLG(((uae_s16)(dst)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_word_000(srca, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x1, dst, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (2/1) */
/* 2 0,0   */

/* NOT.W (An)+ */
uae_u32 REGPARAM2 op_4658_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 19;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) += 2 + 0;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) += 2;
	uae_u32 dst = ~src;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(dst)) == 0);
	SET_NFLG(((uae_s16)(dst)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_word_000(srca, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x1, dst, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (2/1) */
/* 2 0,0   */

/* NOT.W -(An) */
uae_u32 REGPARAM2 op_4660_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 19;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - 2;
	if (srca & 1) {
		m68k_incpci(4);
		m68k_areg(regs, srcreg) = srca;
		exception3_read_access(opcode, srca, 1, 1);
		return 2 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) = srca;
	uae_u32 dst = ~src;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(dst)) == 0);
	SET_NFLG(((uae_s16)(dst)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_word_000(srca, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x1, dst, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 14 * CYCLE_UNIT / 2 + count_cycles;
}
/* 14 (2/1) */
/* 2 0,0   */

/* NOT.W (d16,An) */
uae_u32 REGPARAM2 op_4668_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 19;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 dst = ~src;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(dst)) == 0);
	SET_NFLG(((uae_s16)(dst)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_word_000(srca, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x1, dst, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 4 0,0   */

/* NOT.W (d8,An,Xn) */
uae_u32 REGPARAM2 op_4670_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 19;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	BusCyclePenalty += 2;
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 dst = ~src;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(dst)) == 0);
	SET_NFLG(((uae_s16)(dst)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_word_000(srca, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x1, dst, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (3/1) */
/* 4 4,0   */

/* NOT.W (xxx).W */
uae_u32 REGPARAM2 op_4678_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 19;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, srca, 1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 dst = ~src;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(dst)) == 0);
	SET_NFLG(((uae_s16)(dst)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_word_000(srca, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x1, dst, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 4 0,0   */

/* NOT.W (xxx).L */
uae_u32 REGPARAM2 op_4679_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 19;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	srca = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	srca |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, srca, 1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 dst = ~src;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(dst)) == 0);
	SET_NFLG(((uae_s16)(dst)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_word_000(srca, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x1, dst, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (4/1) */
/* 6 0,0   */

/* NOT.L Dn */
uae_u32 REGPARAM2 op_4680_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 19;
	CurrentInstrCycles = 6;  
	uae_s32 src = m68k_dreg(regs, srcreg);
	uae_u32 dst = ~src;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(dst)) == 0);
	SET_NFLG(((uae_s32)(dst)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		dreg_68000_long_replace_low(srcreg, dst);
		SET_VFLG(0);SET_ZFLG(!dst);
		SET_NFLG(dst & 0x80000000);
		SET_CFLG(0);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	m68k_dreg(regs, srcreg) = (dst);
	m68k_incpci(2);
	return 6 * CYCLE_UNIT / 2 + count_cycles;
}
/* 6 (1/0) */
/* 2 0,0   */

/* NOT.L (An) */
uae_u32 REGPARAM2 op_4690_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 19;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 dst = ~src;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(dst)) == 0);
	SET_NFLG(((uae_s32)(dst)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		SET_VFLG(0);
		SET_ZFLG(!(dst & 0xffff));
		SET_NFLG(dst & 0x8000);
		SET_CFLG(0);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(srca + 2, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, srca + 2, 0x1, dst, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(srca, dst >> 16); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, srca + 0, 0x1, dst >> 16, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (3/2) */
/* 2 0,0   */

/* NOT.L (An)+ */
uae_u32 REGPARAM2 op_4698_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 19;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) += 4;
	uae_u32 dst = ~src;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(dst)) == 0);
	SET_NFLG(((uae_s32)(dst)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		SET_VFLG(0);
		SET_ZFLG(!(dst & 0xffff));
		SET_NFLG(dst & 0x8000);
		SET_CFLG(0);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(srca + 2, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, srca + 2, 0x1, dst, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(srca, dst >> 16); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, srca + 0, 0x1, dst >> 16, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (3/2) */
/* 2 0,0   */

/* NOT.L -(An) */
uae_u32 REGPARAM2 op_46a0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 19;
	CurrentInstrCycles = 22; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - 4;
	if (srca & 1) {
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception3_read_access(opcode, srca, 2, 1);
		return 2 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) = srca;
	uae_u32 dst = ~src;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(dst)) == 0);
	SET_NFLG(((uae_s32)(dst)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		SET_VFLG(0);
		SET_ZFLG(!(dst & 0xffff));
		SET_NFLG(dst & 0x8000);
		SET_CFLG(0);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(srca + 2, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, srca + 2, 0x1, dst, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(srca, dst >> 16); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, srca + 0, 0x1, dst >> 16, 1);
		return 22 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 22 * CYCLE_UNIT / 2 + count_cycles;
}
/* 22 (3/2) */
/* 2 0,0   */

/* NOT.L (d16,An) */
uae_u32 REGPARAM2 op_46a8_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 19;
	CurrentInstrCycles = 24; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 dst = ~src;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(dst)) == 0);
	SET_NFLG(((uae_s32)(dst)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		SET_VFLG(0);
		SET_ZFLG(!(dst & 0xffff));
		SET_NFLG(dst & 0x8000);
		SET_CFLG(0);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(srca + 2, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, srca + 2, 0x1, dst, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(srca, dst >> 16); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, srca + 0, 0x1, dst >> 16, 1);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 24 * CYCLE_UNIT / 2 + count_cycles;
}
/* 24 (4/2) */
/* 4 0,0   */

/* NOT.L (d8,An,Xn) */
uae_u32 REGPARAM2 op_46b0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 19;
	CurrentInstrCycles = 26; 
	uaecptr srca;
	BusCyclePenalty += 2;
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 dst = ~src;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(dst)) == 0);
	SET_NFLG(((uae_s32)(dst)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		SET_VFLG(0);
		SET_ZFLG(!(dst & 0xffff));
		SET_NFLG(dst & 0x8000);
		SET_CFLG(0);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(srca + 2, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, srca + 2, 0x1, dst, 1);
		return 22 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(srca, dst >> 16); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, srca + 0, 0x1, dst >> 16, 1);
		return 26 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 26 * CYCLE_UNIT / 2 + count_cycles;
}
/* 26 (4/2) */
/* 4 4,0   */

/* NOT.L (xxx).W */
uae_u32 REGPARAM2 op_46b8_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 19;
	CurrentInstrCycles = 24; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, srca, 2, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 dst = ~src;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(dst)) == 0);
	SET_NFLG(((uae_s32)(dst)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		SET_VFLG(0);
		SET_ZFLG(!(dst & 0xffff));
		SET_NFLG(dst & 0x8000);
		SET_CFLG(0);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(srca + 2, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, srca + 2, 0x1, dst, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(srca, dst >> 16); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, srca + 0, 0x1, dst >> 16, 1);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 24 * CYCLE_UNIT / 2 + count_cycles;
}
/* 24 (4/2) */
/* 4 0,0   */

/* NOT.L (xxx).L */
uae_u32 REGPARAM2 op_46b9_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 19;
	CurrentInstrCycles = 28; 
	uaecptr srca;
	srca = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	srca |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, srca, 2, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 dst = ~src;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(dst)) == 0);
	SET_NFLG(((uae_s32)(dst)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		SET_VFLG(0);
		SET_ZFLG(!(dst & 0xffff));
		SET_NFLG(dst & 0x8000);
		SET_CFLG(0);
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(srca + 2, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, srca + 2, 0x1, dst, 1);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(srca, dst >> 16); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, srca + 0, 0x1, dst >> 16, 1);
		return 28 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 28 * CYCLE_UNIT / 2 + count_cycles;
}
/* 28 (5/2) */
/* 6 0,0   */

/* MV2SR.W Dn */
uae_u32 REGPARAM2 op_46c0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 33;
	CurrentInstrCycles = 12; 
	if (!regs.s) {
		Exception(8);
		return 0;
	}
	uae_s16 src = m68k_dreg(regs, srcreg);
	int t1 = regs.t1;
	regs.sr = src;
	MakeFromSR();
	m68k_incpci(2);
	get_word_000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, 0);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	if(t1) opcode |= 0x10000;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (2/0) */
/* 2 0,0   */

/* MV2SR.W (An) */
uae_u32 REGPARAM2 op_46d0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 33;
	CurrentInstrCycles = 16; 
	if (!regs.s) {
		Exception(8);
		return 0;
	}
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	int t1 = regs.t1;
	regs.sr = src;
	MakeFromSR();
	m68k_incpci(2);
	get_word_000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, 0);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	if(t1) opcode |= 0x10000;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/0) */
/* 2 0,0   */

/* MV2SR.W (An)+ */
uae_u32 REGPARAM2 op_46d8_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 33;
	CurrentInstrCycles = 16; 
	if (!regs.s) {
		Exception(8);
		return 0;
	}
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) += 2 + 0;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) += 2;
	int t1 = regs.t1;
	regs.sr = src;
	MakeFromSR();
	m68k_incpci(2);
	get_word_000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, 0);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	if(t1) opcode |= 0x10000;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/0) */
/* 2 0,0   */

/* MV2SR.W -(An) */
uae_u32 REGPARAM2 op_46e0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 33;
	CurrentInstrCycles = 18; 
	if (!regs.s) {
		Exception(8);
		return 0;
	}
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - 2;
	if (srca & 1) {
		m68k_incpci(4);
		m68k_areg(regs, srcreg) = srca;
		exception3_read_access(opcode, srca, 1, 1);
		return 2 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) = srca;
	int t1 = regs.t1;
	regs.sr = src;
	MakeFromSR();
	m68k_incpci(2);
	get_word_000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, 0);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	if(t1) opcode |= 0x10000;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (3/0) */
/* 2 0,0   */

/* MV2SR.W (d16,An) */
uae_u32 REGPARAM2 op_46e8_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 33;
	CurrentInstrCycles = 20; 
	if (!regs.s) {
		Exception(8);
		return 0;
	}
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	int t1 = regs.t1;
	regs.sr = src;
	MakeFromSR();
	m68k_incpci(4);
	get_word_000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, 0);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	if(t1) opcode |= 0x10000;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (4/0) */
/* 4 0,0   */

/* MV2SR.W (d8,An,Xn) */
uae_u32 REGPARAM2 op_46f0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 33;
	CurrentInstrCycles = 22; 
	if (!regs.s) {
		Exception(8);
		return 0;
	}
	uaecptr srca;
	BusCyclePenalty += 2;
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	int t1 = regs.t1;
	regs.sr = src;
	MakeFromSR();
	m68k_incpci(4);
	get_word_000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, 0);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	if(t1) opcode |= 0x10000;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 22 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 22 * CYCLE_UNIT / 2 + count_cycles;
}
/* 22 (4/0) */
/* 4 4,0   */

/* MV2SR.W (xxx).W */
uae_u32 REGPARAM2 op_46f8_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 33;
	CurrentInstrCycles = 20; 
	if (!regs.s) {
		Exception(8);
		return 0;
	}
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, srca, 1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	int t1 = regs.t1;
	regs.sr = src;
	MakeFromSR();
	m68k_incpci(4);
	get_word_000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, 0);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	if(t1) opcode |= 0x10000;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (4/0) */
/* 4 0,0   */

/* MV2SR.W (xxx).L */
uae_u32 REGPARAM2 op_46f9_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 33;
	CurrentInstrCycles = 24; 
	if (!regs.s) {
		Exception(8);
		return 0;
	}
	uaecptr srca;
	srca = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	srca |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, srca, 1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	int t1 = regs.t1;
	regs.sr = src;
	MakeFromSR();
	m68k_incpci(6);
	get_word_000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, 0);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	if(t1) opcode |= 0x10000;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 24 * CYCLE_UNIT / 2 + count_cycles;
}
/* 24 (5/0) */
/* 6 0,0   */

/* MV2SR.W (d16,PC) */
uae_u32 REGPARAM2 op_46fa_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 33;
	CurrentInstrCycles = 20; 
	if (!regs.s) {
		Exception(8);
		return 0;
	}
	uaecptr srca;
	srca = m68k_getpci() + 2;
	srca += (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	int t1 = regs.t1;
	regs.sr = src;
	MakeFromSR();
	m68k_incpci(4);
	get_word_000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, 0);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	if(t1) opcode |= 0x10000;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (4/0) */
/* 4 0,0   */

/* MV2SR.W (d8,PC,Xn) */
uae_u32 REGPARAM2 op_46fb_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 33;
	CurrentInstrCycles = 22; 
	if (!regs.s) {
		Exception(8);
		return 0;
	}
	uaecptr srca;
	uaecptr tmppc = m68k_getpci() + 2;
	BusCyclePenalty += 2;
	srca = get_disp_ea_000(tmppc, get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	int t1 = regs.t1;
	regs.sr = src;
	MakeFromSR();
	m68k_incpci(4);
	get_word_000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, 0);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	if(t1) opcode |= 0x10000;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 22 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 22 * CYCLE_UNIT / 2 + count_cycles;
}
/* 22 (4/0) */
/* 4 4,0   */

/* MV2SR.W #<data>.W */
uae_u32 REGPARAM2 op_46fc_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 33;
	CurrentInstrCycles = 16; 
	if (!regs.s) {
		Exception(8);
		return 0;
	}
	uae_s16 src = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	int t1 = regs.t1;
	regs.sr = src;
	MakeFromSR();
	m68k_incpci(4);
	get_word_000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, 0);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	if(t1) opcode |= 0x10000;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/0) */
/* 4 0,0   */

/* NBCD.B Dn */
uae_u32 REGPARAM2 op_4800_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 17;
	CurrentInstrCycles = 6;  
	uae_s8 src = m68k_dreg(regs, srcreg);
	uae_u16 newv_lo = - (src & 0xF) - (GET_XFLG() ? 1 : 0);
	uae_u16 newv_hi = - (src & 0xF0);
	uae_u16 newv;
	int cflg, tmp_newv;
	tmp_newv = newv_hi + newv_lo;
	if (newv_lo > 9) newv_lo -= 6;
	newv = newv_hi + newv_lo;
	cflg = (newv & 0x1F0) > 0x90;
	if (cflg) newv -= 0x60;
	SET_CFLG(cflg);
	COPY_CARRY();
	SET_ZFLG(GET_ZFLG() & (((uae_s8)(newv)) == 0));
	SET_NFLG(((uae_s8)(newv)) < 0);
	SET_VFLG((tmp_newv & 0x80) != 0 && (newv & 0x80) == 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((newv) & 0xff);
	m68k_incpci(2);
	return 6 * CYCLE_UNIT / 2 + count_cycles;
}
/* 6 (1/0) */
/* 2 0,0   */

/* NBCD.B (An) */
uae_u32 REGPARAM2 op_4810_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 17;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u16 newv_lo = - (src & 0xF) - (GET_XFLG() ? 1 : 0);
	uae_u16 newv_hi = - (src & 0xF0);
	uae_u16 newv;
	int cflg, tmp_newv;
	tmp_newv = newv_hi + newv_lo;
	if (newv_lo > 9) newv_lo -= 6;
	newv = newv_hi + newv_lo;
	cflg = (newv & 0x1F0) > 0x90;
	if (cflg) newv -= 0x60;
	SET_CFLG(cflg);
	COPY_CARRY();
	SET_ZFLG(GET_ZFLG() & (((uae_s8)(newv)) == 0));
	SET_NFLG(((uae_s8)(newv)) < 0);
	SET_VFLG((tmp_newv & 0x80) != 0 && (newv & 0x80) == 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_byte_000(srca, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, newv, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (2/1) */
/* 2 0,0   */

/* NBCD.B (An)+ */
uae_u32 REGPARAM2 op_4818_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 17;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
	uae_u16 newv_lo = - (src & 0xF) - (GET_XFLG() ? 1 : 0);
	uae_u16 newv_hi = - (src & 0xF0);
	uae_u16 newv;
	int cflg, tmp_newv;
	tmp_newv = newv_hi + newv_lo;
	if (newv_lo > 9) newv_lo -= 6;
	newv = newv_hi + newv_lo;
	cflg = (newv & 0x1F0) > 0x90;
	if (cflg) newv -= 0x60;
	SET_CFLG(cflg);
	COPY_CARRY();
	SET_ZFLG(GET_ZFLG() & (((uae_s8)(newv)) == 0));
	SET_NFLG(((uae_s8)(newv)) < 0);
	SET_VFLG((tmp_newv & 0x80) != 0 && (newv & 0x80) == 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_byte_000(srca, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, newv, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (2/1) */
/* 2 0,0   */

/* NBCD.B -(An) */
uae_u32 REGPARAM2 op_4820_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 17;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) = srca;
	uae_u16 newv_lo = - (src & 0xF) - (GET_XFLG() ? 1 : 0);
	uae_u16 newv_hi = - (src & 0xF0);
	uae_u16 newv;
	int cflg, tmp_newv;
	tmp_newv = newv_hi + newv_lo;
	if (newv_lo > 9) newv_lo -= 6;
	newv = newv_hi + newv_lo;
	cflg = (newv & 0x1F0) > 0x90;
	if (cflg) newv -= 0x60;
	SET_CFLG(cflg);
	COPY_CARRY();
	SET_ZFLG(GET_ZFLG() & (((uae_s8)(newv)) == 0));
	SET_NFLG(((uae_s8)(newv)) < 0);
	SET_VFLG((tmp_newv & 0x80) != 0 && (newv & 0x80) == 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_byte_000(srca, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, newv, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 14 * CYCLE_UNIT / 2 + count_cycles;
}
/* 14 (2/1) */
/* 2 0,0   */

/* NBCD.B (d16,An) */
uae_u32 REGPARAM2 op_4828_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 17;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u16 newv_lo = - (src & 0xF) - (GET_XFLG() ? 1 : 0);
	uae_u16 newv_hi = - (src & 0xF0);
	uae_u16 newv;
	int cflg, tmp_newv;
	tmp_newv = newv_hi + newv_lo;
	if (newv_lo > 9) newv_lo -= 6;
	newv = newv_hi + newv_lo;
	cflg = (newv & 0x1F0) > 0x90;
	if (cflg) newv -= 0x60;
	SET_CFLG(cflg);
	COPY_CARRY();
	SET_ZFLG(GET_ZFLG() & (((uae_s8)(newv)) == 0));
	SET_NFLG(((uae_s8)(newv)) < 0);
	SET_VFLG((tmp_newv & 0x80) != 0 && (newv & 0x80) == 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_byte_000(srca, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, newv, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 4 0,0   */

/* NBCD.B (d8,An,Xn) */
uae_u32 REGPARAM2 op_4830_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 17;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	BusCyclePenalty += 2;
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u16 newv_lo = - (src & 0xF) - (GET_XFLG() ? 1 : 0);
	uae_u16 newv_hi = - (src & 0xF0);
	uae_u16 newv;
	int cflg, tmp_newv;
	tmp_newv = newv_hi + newv_lo;
	if (newv_lo > 9) newv_lo -= 6;
	newv = newv_hi + newv_lo;
	cflg = (newv & 0x1F0) > 0x90;
	if (cflg) newv -= 0x60;
	SET_CFLG(cflg);
	COPY_CARRY();
	SET_ZFLG(GET_ZFLG() & (((uae_s8)(newv)) == 0));
	SET_NFLG(((uae_s8)(newv)) < 0);
	SET_VFLG((tmp_newv & 0x80) != 0 && (newv & 0x80) == 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_byte_000(srca, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, newv, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (3/1) */
/* 4 4,0   */

/* NBCD.B (xxx).W */
uae_u32 REGPARAM2 op_4838_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 17;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u16 newv_lo = - (src & 0xF) - (GET_XFLG() ? 1 : 0);
	uae_u16 newv_hi = - (src & 0xF0);
	uae_u16 newv;
	int cflg, tmp_newv;
	tmp_newv = newv_hi + newv_lo;
	if (newv_lo > 9) newv_lo -= 6;
	newv = newv_hi + newv_lo;
	cflg = (newv & 0x1F0) > 0x90;
	if (cflg) newv -= 0x60;
	SET_CFLG(cflg);
	COPY_CARRY();
	SET_ZFLG(GET_ZFLG() & (((uae_s8)(newv)) == 0));
	SET_NFLG(((uae_s8)(newv)) < 0);
	SET_VFLG((tmp_newv & 0x80) != 0 && (newv & 0x80) == 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_byte_000(srca, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, newv, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 4 0,0   */

/* NBCD.B (xxx).L */
uae_u32 REGPARAM2 op_4839_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 17;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	srca = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	srca |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u16 newv_lo = - (src & 0xF) - (GET_XFLG() ? 1 : 0);
	uae_u16 newv_hi = - (src & 0xF0);
	uae_u16 newv;
	int cflg, tmp_newv;
	tmp_newv = newv_hi + newv_lo;
	if (newv_lo > 9) newv_lo -= 6;
	newv = newv_hi + newv_lo;
	cflg = (newv & 0x1F0) > 0x90;
	if (cflg) newv -= 0x60;
	SET_CFLG(cflg);
	COPY_CARRY();
	SET_ZFLG(GET_ZFLG() & (((uae_s8)(newv)) == 0));
	SET_NFLG(((uae_s8)(newv)) < 0);
	SET_VFLG((tmp_newv & 0x80) != 0 && (newv & 0x80) == 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_byte_000(srca, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, newv, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (4/1) */
/* 6 0,0   */

/* SWAP.W Dn */
uae_u32 REGPARAM2 op_4840_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 34;
	CurrentInstrCycles = 4;  
	uae_s32 src = m68k_dreg(regs, srcreg);
	uae_u32 dst = ((src >> 16)&0xFFFF) | ((src&0xFFFF)<<16);
	m68k_dreg(regs, srcreg) = (dst);
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(dst)) == 0);
	SET_NFLG(((uae_s32)(dst)) < 0);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 4 * CYCLE_UNIT / 2 + count_cycles;
}
/* 4 (1/0) */
/* 2 0,0   */

/* PEA.L (An) */
uae_u32 REGPARAM2 op_4850_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 57;
	CurrentInstrCycles = 12; 
	uae_u16 old_opcode = opcode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, 7) - 4;
	m68k_areg(regs, 7) = dsta;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		m68k_areg(regs, 7) += 4;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		regs.ir = old_opcode;
		m68k_incpci(4);
		exception3_write_access(old_opcode, dsta, sz_word, srca >> 16, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, srca >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x1, srca >> 16, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta + 2, srca); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 2, 0x1, srca, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (1/2) */
/* 2 0,0   */

/* PEA.L (d16,An) */
uae_u32 REGPARAM2 op_4868_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 57;
	CurrentInstrCycles = 16; 
	uae_u16 old_opcode = opcode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, 7) - 4;
	m68k_areg(regs, 7) = dsta;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		m68k_areg(regs, 7) += 4;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		regs.ir = old_opcode;
		m68k_incpci(6);
		exception3_write_access(old_opcode, dsta, sz_word, srca >> 16, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, srca >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, srca >> 16, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta + 2, srca); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 2, 0x1, srca, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (2/2) */
/* 4 0,0   */

/* PEA.L (d8,An,Xn) */
uae_u32 REGPARAM2 op_4870_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 57;
	CurrentInstrCycles = 22; 
	uae_u16 old_opcode = opcode;
	uaecptr srca;
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, 7) - 4;
	m68k_areg(regs, 7) = dsta;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		m68k_areg(regs, 7) += 4;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		regs.ir = old_opcode;
		m68k_incpci(6);
		exception3_write_access(old_opcode, dsta, sz_word, srca >> 16, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, srca >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, srca >> 16, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta + 2, srca); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 2, 0x1, srca, 1);
		return 22 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 22 * CYCLE_UNIT / 2 + count_cycles;
}
/* 22 (2/2) */
/* 4 4,0   */

/* PEA.L (xxx).W */
uae_u32 REGPARAM2 op_4878_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 57;
	CurrentInstrCycles = 16; 
	uae_u16 old_opcode = opcode;
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, 7) - 4;
	m68k_areg(regs, 7) = dsta;
	if (dsta & 1) {
		regs.ir = old_opcode;
		m68k_incpci(4);
		exception3_write_access(old_opcode, dsta, sz_word, srca >> 16, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, srca >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, srca >> 16, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta + 2, srca); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 2, 0x1, srca, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (2/2) */
/* 4 0,0   */

/* PEA.L (xxx).L */
uae_u32 REGPARAM2 op_4879_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 57;
	CurrentInstrCycles = 20; 
	uae_u16 old_opcode = opcode;
	uaecptr srca;
	srca = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	srca |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, 7) - 4;
	m68k_areg(regs, 7) = dsta;
	if (dsta & 1) {
		regs.ir = old_opcode;
		m68k_incpci(6);
		exception3_write_access(old_opcode, dsta, sz_word, srca >> 16, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, srca >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 0, 0x1, srca >> 16, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta + 2, srca); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 2, 0x1, srca, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (3/2) */
/* 6 0,0   */

/* PEA.L (d16,PC) */
uae_u32 REGPARAM2 op_487a_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 57;
	CurrentInstrCycles = 16; 
	uae_u16 old_opcode = opcode;
	uaecptr srca;
	srca = m68k_getpci() + 2;
	srca += (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, 7) - 4;
	m68k_areg(regs, 7) = dsta;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		m68k_areg(regs, 7) += 4;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		regs.ir = old_opcode;
		m68k_incpci(6);
		exception3_write_access(old_opcode, dsta, sz_word, srca >> 16, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, srca >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, srca >> 16, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta + 2, srca); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 2, 0x1, srca, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (2/2) */
/* 4 0,0   */

/* PEA.L (d8,PC,Xn) */
uae_u32 REGPARAM2 op_487b_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 57;
	CurrentInstrCycles = 22; 
	uae_u16 old_opcode = opcode;
	uaecptr srca;
	uaecptr tmppc = m68k_getpci() + 2;
	srca = get_disp_ea_000(tmppc, get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, 7) - 4;
	m68k_areg(regs, 7) = dsta;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		m68k_areg(regs, 7) += 4;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		regs.ir = old_opcode;
		m68k_incpci(6);
		exception3_write_access(old_opcode, dsta, sz_word, srca >> 16, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, srca >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, srca >> 16, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta + 2, srca); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 2, 0x1, srca, 1);
		return 22 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 22 * CYCLE_UNIT / 2 + count_cycles;
}
/* 22 (2/2) */
/* 4 4,0   */

/* EXT.W Dn */
uae_u32 REGPARAM2 op_4880_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 36;
	CurrentInstrCycles = 4;  
	uae_s32 src = m68k_dreg(regs, srcreg);
	uae_u16 dst = (uae_s16)(uae_s8)src;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(dst)) == 0);
	SET_NFLG(((uae_s16)(dst)) < 0);
	m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | ((dst) & 0xffff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 4 * CYCLE_UNIT / 2 + count_cycles;
}
/* 4 (1/0) */
/* 2 0,0   */

/* MVMLE.W #<data>.W,(An) */
uae_u32 REGPARAM2 op_4890_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 38;
	CurrentInstrCycles = 8;  
	uae_u16 mask = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr srca;
	srca = m68k_areg(regs, dstreg);
	uae_u16 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
	if ((amask || dmask) && (srca & 1)) {
		uaecptr srcav = srca;
		m68k_incpci(6);
		exception3_write_access(opcode, srca, 1, srcav, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	while (dmask) {
		put_word_000(srca, m68k_dreg(regs, movem_index1[dmask]));
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(6);
			exception2_write(opcode, srca + 0, 0x1, m68k_dreg(regs, movem_index1[dmask]), 1);
			return 4 * CYCLE_UNIT / 2 + count_cycles;
		}
		srca += 2;
		dmask = movem_next[dmask];
	}
	while (amask) {
		put_word_000(srca, m68k_areg(regs, movem_index1[amask]));
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(6);
			exception2_write(opcode, srca + 0, 0x1, m68k_areg(regs, movem_index1[amask]), 1);
			return 4 * CYCLE_UNIT / 2 + count_cycles;
		}
		srca += 2;
		amask = movem_next[amask];
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8+ (2/0) */
/* 4 0,0   */

/* MVMLE.W #<data>.W,-(An) */
uae_u32 REGPARAM2 op_48a0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 38;
	CurrentInstrCycles = 8;  
	uae_u16 mask = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr srca;
	srca = m68k_areg(regs, dstreg) - 0;
	uae_u16 amask = mask & 0xff, dmask = (mask >> 8) & 0xff;
	if ((amask || dmask) && (srca & 1)) {
		srca -= 2;
		uaecptr srcav = srca;
		m68k_incpci(6);
		exception3_write_access(opcode, srca, 1, srcav, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	while (amask) {
		srca -= 2;
		put_word_000(srca, m68k_areg(regs, movem_index2[amask]));
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(6);
			exception2_write(opcode, srca + 0, 0x1, m68k_areg(regs, movem_index2[amask]), 1);
			return 4 * CYCLE_UNIT / 2 + count_cycles;
		}
		amask = movem_next[amask];
	}
	while (dmask) {
		srca -= 2;
		put_word_000(srca, m68k_dreg(regs, movem_index2[dmask]));
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(6);
			exception2_write(opcode, srca + 0, 0x1, m68k_dreg(regs, movem_index2[dmask]), 1);
			return 4 * CYCLE_UNIT / 2 + count_cycles;
		}
		dmask = movem_next[dmask];
	}
	m68k_areg(regs, dstreg) = srca;
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8+ (2/0) */
/* 4 0,0   */

/* MVMLE.W #<data>.W,(d16,An) */
uae_u32 REGPARAM2 op_48a8_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 38;
	CurrentInstrCycles = 12; 
	uae_u16 mask = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr srca;
	srca = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, 2);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u16 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
	if ((amask || dmask) && (srca & 1)) {
		uaecptr srcav = srca;
		m68k_incpci(8);
		exception3_write_access(opcode, srca, 1, srcav, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	while (dmask) {
		put_word_000(srca, m68k_dreg(regs, movem_index1[dmask]));
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(8);
			exception2_write(opcode, srca + 0, 0x1, m68k_dreg(regs, movem_index1[dmask]), 1);
			return 8 * CYCLE_UNIT / 2 + count_cycles;
		}
		srca += 2;
		dmask = movem_next[dmask];
	}
	while (amask) {
		put_word_000(srca, m68k_areg(regs, movem_index1[amask]));
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(8);
			exception2_write(opcode, srca + 0, 0x1, m68k_areg(regs, movem_index1[amask]), 1);
			return 8 * CYCLE_UNIT / 2 + count_cycles;
		}
		srca += 2;
		amask = movem_next[amask];
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12+ (3/0) */
/* 6 0,0   */

/* MVMLE.W #<data>.W,(d8,An,Xn) */
uae_u32 REGPARAM2 op_48b0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 38;
	CurrentInstrCycles = 14; 
	uae_u16 mask = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr srca;
	srca = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_000_prefetch(6));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, 2);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u16 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
	if ((amask || dmask) && (srca & 1)) {
		uaecptr srcav = srca;
		m68k_incpci(8);
		exception3_write_access(opcode, srca, 1, srcav, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	while (dmask) {
		put_word_000(srca, m68k_dreg(regs, movem_index1[dmask]));
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(8);
			exception2_write(opcode, srca + 0, 0x1, m68k_dreg(regs, movem_index1[dmask]), 1);
			return 10 * CYCLE_UNIT / 2 + count_cycles;
		}
		srca += 2;
		dmask = movem_next[dmask];
	}
	while (amask) {
		put_word_000(srca, m68k_areg(regs, movem_index1[amask]));
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(8);
			exception2_write(opcode, srca + 0, 0x1, m68k_areg(regs, movem_index1[amask]), 1);
			return 10 * CYCLE_UNIT / 2 + count_cycles;
		}
		srca += 2;
		amask = movem_next[amask];
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 14 * CYCLE_UNIT / 2 + count_cycles;
}
/* 14+ (3/0) */
/* 6 4,0   */

/* MVMLE.W #<data>.W,(xxx).W */
uae_u32 REGPARAM2 op_48b8_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 38;
	CurrentInstrCycles = 12; 
	uae_u16 mask = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, 2);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u16 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
	if ((amask || dmask) && (srca & 1)) {
		uaecptr srcav = srca;
		m68k_incpci(8);
		exception3_write_access(opcode, srca, 1, srcav, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	while (dmask) {
		put_word_000(srca, m68k_dreg(regs, movem_index1[dmask]));
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(8);
			exception2_write(opcode, srca + 0, 0x1, m68k_dreg(regs, movem_index1[dmask]), 1);
			return 8 * CYCLE_UNIT / 2 + count_cycles;
		}
		srca += 2;
		dmask = movem_next[dmask];
	}
	while (amask) {
		put_word_000(srca, m68k_areg(regs, movem_index1[amask]));
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(8);
			exception2_write(opcode, srca + 0, 0x1, m68k_areg(regs, movem_index1[amask]), 1);
			return 8 * CYCLE_UNIT / 2 + count_cycles;
		}
		srca += 2;
		amask = movem_next[amask];
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12+ (3/0) */
/* 6 0,0   */

/* MVMLE.W #<data>.W,(xxx).L */
uae_u32 REGPARAM2 op_48b9_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 38;
	CurrentInstrCycles = 16; 
	uae_u16 mask = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr srca;
	srca = get_word_000_prefetch(6) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	srca |= get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		pcoffset += 2;
		exception2_fetch(opcode, 8, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u16 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
	if ((amask || dmask) && (srca & 1)) {
		uaecptr srcav = srca;
		m68k_incpci(10);
		exception3_write_access(opcode, srca, 1, srcav, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	while (dmask) {
		put_word_000(srca, m68k_dreg(regs, movem_index1[dmask]));
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(10);
			exception2_write(opcode, srca + 0, 0x1, m68k_dreg(regs, movem_index1[dmask]), 1);
			return 12 * CYCLE_UNIT / 2 + count_cycles;
		}
		srca += 2;
		dmask = movem_next[dmask];
	}
	while (amask) {
		put_word_000(srca, m68k_areg(regs, movem_index1[amask]));
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(10);
			exception2_write(opcode, srca + 0, 0x1, m68k_areg(regs, movem_index1[amask]), 1);
			return 12 * CYCLE_UNIT / 2 + count_cycles;
		}
		srca += 2;
		amask = movem_next[amask];
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(10);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 10, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(8);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16+ (4/0) */
/* 8 0,0   */

/* EXT.L Dn */
uae_u32 REGPARAM2 op_48c0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 36;
	CurrentInstrCycles = 4;  
	uae_s32 src = m68k_dreg(regs, srcreg);
	uae_u32 dst = (uae_s32)(uae_s16)src;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(dst)) == 0);
	SET_NFLG(((uae_s32)(dst)) < 0);
	m68k_dreg(regs, srcreg) = (dst);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 4 * CYCLE_UNIT / 2 + count_cycles;
}
/* 4 (1/0) */
/* 2 0,0   */

/* MVMLE.L #<data>.W,(An) */
uae_u32 REGPARAM2 op_48d0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 38;
	CurrentInstrCycles = 8;  
	uae_u16 mask = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr srca;
	srca = m68k_areg(regs, dstreg);
	uae_u16 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
	if ((amask || dmask) && (srca & 1)) {
		uaecptr srcav = srca;
		m68k_incpci(6);
		exception3_write_access(opcode, srca, 2, srcav, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	while (dmask) {
		put_word_000(srca, m68k_dreg(regs, movem_index1[dmask]) >> 16);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(6);
			exception2_write(opcode, srca + 0, 0x1, m68k_dreg(regs, movem_index1[dmask]) >> 16, 1);
			return 4 * CYCLE_UNIT / 2 + count_cycles;
		}
		put_word_000(srca + 2, m68k_dreg(regs, movem_index1[dmask]));
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(6);
			exception2_write(opcode, srca + 2, 0x1, m68k_dreg(regs, movem_index1[dmask]), 1);
			return 4 * CYCLE_UNIT / 2 + count_cycles;
		}
		srca += 4;
		dmask = movem_next[dmask];
	}
	while (amask) {
		put_word_000(srca, m68k_areg(regs, movem_index1[amask]) >> 16);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(6);
			exception2_write(opcode, srca + 0, 0x1, m68k_areg(regs, movem_index1[amask]) >> 16, 1);
			return 4 * CYCLE_UNIT / 2 + count_cycles;
		}
		put_word_000(srca + 2, m68k_areg(regs, movem_index1[amask]));
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(6);
			exception2_write(opcode, srca + 2, 0x1, m68k_areg(regs, movem_index1[amask]), 1);
			return 4 * CYCLE_UNIT / 2 + count_cycles;
		}
		srca += 4;
		amask = movem_next[amask];
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8+ (2/0) */
/* 4 0,0   */

/* MVMLE.L #<data>.W,-(An) */
uae_u32 REGPARAM2 op_48e0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 38;
	CurrentInstrCycles = 8;  
	uae_u16 mask = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr srca;
	srca = m68k_areg(regs, dstreg) - 0;
	uae_u16 amask = mask & 0xff, dmask = (mask >> 8) & 0xff;
	if ((amask || dmask) && (srca & 1)) {
		srca -= 2;
		uaecptr srcav = srca;
		m68k_incpci(6);
		exception3_write_access(opcode, srca, 2, srcav, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	while (amask) {
		put_word_000(srca - 2, m68k_areg(regs, movem_index2[amask]));
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(6);
			exception2_write(opcode, srca + -2, 0x1, m68k_areg(regs, movem_index2[amask]), 1);
			return 4 * CYCLE_UNIT / 2 + count_cycles;
		}
		put_word_000(srca - 4, m68k_areg(regs, movem_index2[amask]) >> 16);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(6);
			exception2_write(opcode, srca + -4, 0x1, m68k_areg(regs, movem_index2[amask]) >> 16, 1);
			return 4 * CYCLE_UNIT / 2 + count_cycles;
		}
		srca -= 4;
		amask = movem_next[amask];
	}
	while (dmask) {
		put_word_000(srca - 2, m68k_dreg(regs, movem_index2[dmask]));
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(6);
			exception2_write(opcode, srca + -2, 0x1, m68k_dreg(regs, movem_index2[dmask]), 1);
			return 4 * CYCLE_UNIT / 2 + count_cycles;
		}
		put_word_000(srca - 4, m68k_dreg(regs, movem_index2[dmask]) >> 16);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(6);
			exception2_write(opcode, srca + -4, 0x1, m68k_dreg(regs, movem_index2[dmask]) >> 16, 1);
			return 4 * CYCLE_UNIT / 2 + count_cycles;
		}
		srca -= 4;
		dmask = movem_next[dmask];
	}
	m68k_areg(regs, dstreg) = srca;
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8+ (2/0) */
/* 4 0,0   */

/* MVMLE.L #<data>.W,(d16,An) */
uae_u32 REGPARAM2 op_48e8_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 38;
	CurrentInstrCycles = 12; 
	uae_u16 mask = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr srca;
	srca = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, 2);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u16 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
	if ((amask || dmask) && (srca & 1)) {
		uaecptr srcav = srca;
		m68k_incpci(8);
		exception3_write_access(opcode, srca, 2, srcav, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	while (dmask) {
		put_word_000(srca, m68k_dreg(regs, movem_index1[dmask]) >> 16);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(8);
			exception2_write(opcode, srca + 0, 0x1, m68k_dreg(regs, movem_index1[dmask]) >> 16, 1);
			return 8 * CYCLE_UNIT / 2 + count_cycles;
		}
		put_word_000(srca + 2, m68k_dreg(regs, movem_index1[dmask]));
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(8);
			exception2_write(opcode, srca + 2, 0x1, m68k_dreg(regs, movem_index1[dmask]), 1);
			return 8 * CYCLE_UNIT / 2 + count_cycles;
		}
		srca += 4;
		dmask = movem_next[dmask];
	}
	while (amask) {
		put_word_000(srca, m68k_areg(regs, movem_index1[amask]) >> 16);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(8);
			exception2_write(opcode, srca + 0, 0x1, m68k_areg(regs, movem_index1[amask]) >> 16, 1);
			return 8 * CYCLE_UNIT / 2 + count_cycles;
		}
		put_word_000(srca + 2, m68k_areg(regs, movem_index1[amask]));
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(8);
			exception2_write(opcode, srca + 2, 0x1, m68k_areg(regs, movem_index1[amask]), 1);
			return 8 * CYCLE_UNIT / 2 + count_cycles;
		}
		srca += 4;
		amask = movem_next[amask];
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12+ (3/0) */
/* 6 0,0   */

/* MVMLE.L #<data>.W,(d8,An,Xn) */
uae_u32 REGPARAM2 op_48f0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 38;
	CurrentInstrCycles = 14; 
	uae_u16 mask = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr srca;
	srca = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_000_prefetch(6));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, 2);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u16 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
	if ((amask || dmask) && (srca & 1)) {
		uaecptr srcav = srca;
		m68k_incpci(8);
		exception3_write_access(opcode, srca, 2, srcav, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	while (dmask) {
		put_word_000(srca, m68k_dreg(regs, movem_index1[dmask]) >> 16);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(8);
			exception2_write(opcode, srca + 0, 0x1, m68k_dreg(regs, movem_index1[dmask]) >> 16, 1);
			return 10 * CYCLE_UNIT / 2 + count_cycles;
		}
		put_word_000(srca + 2, m68k_dreg(regs, movem_index1[dmask]));
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(8);
			exception2_write(opcode, srca + 2, 0x1, m68k_dreg(regs, movem_index1[dmask]), 1);
			return 10 * CYCLE_UNIT / 2 + count_cycles;
		}
		srca += 4;
		dmask = movem_next[dmask];
	}
	while (amask) {
		put_word_000(srca, m68k_areg(regs, movem_index1[amask]) >> 16);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(8);
			exception2_write(opcode, srca + 0, 0x1, m68k_areg(regs, movem_index1[amask]) >> 16, 1);
			return 10 * CYCLE_UNIT / 2 + count_cycles;
		}
		put_word_000(srca + 2, m68k_areg(regs, movem_index1[amask]));
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(8);
			exception2_write(opcode, srca + 2, 0x1, m68k_areg(regs, movem_index1[amask]), 1);
			return 10 * CYCLE_UNIT / 2 + count_cycles;
		}
		srca += 4;
		amask = movem_next[amask];
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 14 * CYCLE_UNIT / 2 + count_cycles;
}
/* 14+ (3/0) */
/* 6 4,0   */

/* MVMLE.L #<data>.W,(xxx).W */
uae_u32 REGPARAM2 op_48f8_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 38;
	CurrentInstrCycles = 12; 
	uae_u16 mask = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, 2);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u16 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
	if ((amask || dmask) && (srca & 1)) {
		uaecptr srcav = srca;
		m68k_incpci(8);
		exception3_write_access(opcode, srca, 2, srcav, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	while (dmask) {
		put_word_000(srca, m68k_dreg(regs, movem_index1[dmask]) >> 16);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(8);
			exception2_write(opcode, srca + 0, 0x1, m68k_dreg(regs, movem_index1[dmask]) >> 16, 1);
			return 8 * CYCLE_UNIT / 2 + count_cycles;
		}
		put_word_000(srca + 2, m68k_dreg(regs, movem_index1[dmask]));
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(8);
			exception2_write(opcode, srca + 2, 0x1, m68k_dreg(regs, movem_index1[dmask]), 1);
			return 8 * CYCLE_UNIT / 2 + count_cycles;
		}
		srca += 4;
		dmask = movem_next[dmask];
	}
	while (amask) {
		put_word_000(srca, m68k_areg(regs, movem_index1[amask]) >> 16);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(8);
			exception2_write(opcode, srca + 0, 0x1, m68k_areg(regs, movem_index1[amask]) >> 16, 1);
			return 8 * CYCLE_UNIT / 2 + count_cycles;
		}
		put_word_000(srca + 2, m68k_areg(regs, movem_index1[amask]));
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(8);
			exception2_write(opcode, srca + 2, 0x1, m68k_areg(regs, movem_index1[amask]), 1);
			return 8 * CYCLE_UNIT / 2 + count_cycles;
		}
		srca += 4;
		amask = movem_next[amask];
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12+ (3/0) */
/* 6 0,0   */

/* MVMLE.L #<data>.W,(xxx).L */
uae_u32 REGPARAM2 op_48f9_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 38;
	CurrentInstrCycles = 16; 
	uae_u16 mask = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr srca;
	srca = get_word_000_prefetch(6) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	srca |= get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		pcoffset += 2;
		exception2_fetch(opcode, 8, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u16 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
	if ((amask || dmask) && (srca & 1)) {
		uaecptr srcav = srca;
		m68k_incpci(10);
		exception3_write_access(opcode, srca, 2, srcav, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	while (dmask) {
		put_word_000(srca, m68k_dreg(regs, movem_index1[dmask]) >> 16);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(10);
			exception2_write(opcode, srca + 0, 0x1, m68k_dreg(regs, movem_index1[dmask]) >> 16, 1);
			return 12 * CYCLE_UNIT / 2 + count_cycles;
		}
		put_word_000(srca + 2, m68k_dreg(regs, movem_index1[dmask]));
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(10);
			exception2_write(opcode, srca + 2, 0x1, m68k_dreg(regs, movem_index1[dmask]), 1);
			return 12 * CYCLE_UNIT / 2 + count_cycles;
		}
		srca += 4;
		dmask = movem_next[dmask];
	}
	while (amask) {
		put_word_000(srca, m68k_areg(regs, movem_index1[amask]) >> 16);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(10);
			exception2_write(opcode, srca + 0, 0x1, m68k_areg(regs, movem_index1[amask]) >> 16, 1);
			return 12 * CYCLE_UNIT / 2 + count_cycles;
		}
		put_word_000(srca + 2, m68k_areg(regs, movem_index1[amask]));
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(10);
			exception2_write(opcode, srca + 2, 0x1, m68k_areg(regs, movem_index1[amask]), 1);
			return 12 * CYCLE_UNIT / 2 + count_cycles;
		}
		srca += 4;
		amask = movem_next[amask];
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(10);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 10, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(8);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16+ (4/0) */
/* 8 0,0   */

/* TST.B Dn */
uae_u32 REGPARAM2 op_4a00_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 20;
	CurrentInstrCycles = 4;  
	uae_s8 src = m68k_dreg(regs, srcreg);
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 4 * CYCLE_UNIT / 2 + count_cycles;
}
/* 4 (1/0) */
/* 2 0,0   */

/* TST.B (An) */
uae_u32 REGPARAM2 op_4a10_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 20;
	CurrentInstrCycles = 8;  
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8 (2/0) */
/* 2 0,0   */

/* TST.B (An)+ */
uae_u32 REGPARAM2 op_4a18_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 20;
	CurrentInstrCycles = 8;  
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8 (2/0) */
/* 2 0,0   */

/* TST.B -(An) */
uae_u32 REGPARAM2 op_4a20_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 20;
	CurrentInstrCycles = 10; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) = srca;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 10 * CYCLE_UNIT / 2 + count_cycles;
}
/* 10 (2/0) */
/* 2 0,0   */

/* TST.B (d16,An) */
uae_u32 REGPARAM2 op_4a28_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 20;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (3/0) */
/* 4 0,0   */

/* TST.B (d8,An,Xn) */
uae_u32 REGPARAM2 op_4a30_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 20;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	BusCyclePenalty += 2;
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 14 * CYCLE_UNIT / 2 + count_cycles;
}
/* 14 (3/0) */
/* 4 4,0   */

/* TST.B (xxx).W */
uae_u32 REGPARAM2 op_4a38_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 20;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (3/0) */
/* 4 0,0   */

/* TST.B (xxx).L */
uae_u32 REGPARAM2 op_4a39_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 20;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	srca |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (4/0) */
/* 6 0,0   */

/* TST.W Dn */
uae_u32 REGPARAM2 op_4a40_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 20;
	CurrentInstrCycles = 4;  
	uae_s16 src = m68k_dreg(regs, srcreg);
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 4 * CYCLE_UNIT / 2 + count_cycles;
}
/* 4 (1/0) */
/* 2 0,0   */

/* TST.W (An) */
uae_u32 REGPARAM2 op_4a50_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 20;
	CurrentInstrCycles = 8;  
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8 (2/0) */
/* 2 0,0   */

/* TST.W (An)+ */
uae_u32 REGPARAM2 op_4a58_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 20;
	CurrentInstrCycles = 8;  
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) += 2 + 0;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) += 2;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8 (2/0) */
/* 2 0,0   */

/* TST.W -(An) */
uae_u32 REGPARAM2 op_4a60_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 20;
	CurrentInstrCycles = 10; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - 2;
	if (srca & 1) {
		m68k_incpci(4);
		m68k_areg(regs, srcreg) = srca;
		exception3_read_access(opcode, srca, 1, 1);
		return 2 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) = srca;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 10 * CYCLE_UNIT / 2 + count_cycles;
}
/* 10 (2/0) */
/* 2 0,0   */

/* TST.W (d16,An) */
uae_u32 REGPARAM2 op_4a68_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 20;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (3/0) */
/* 4 0,0   */

/* TST.W (d8,An,Xn) */
uae_u32 REGPARAM2 op_4a70_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 20;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	BusCyclePenalty += 2;
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 14 * CYCLE_UNIT / 2 + count_cycles;
}
/* 14 (3/0) */
/* 4 4,0   */

/* TST.W (xxx).W */
uae_u32 REGPARAM2 op_4a78_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 20;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, srca, 1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (3/0) */
/* 4 0,0   */

/* TST.W (xxx).L */
uae_u32 REGPARAM2 op_4a79_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 20;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	srca |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, srca, 1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (4/0) */
/* 6 0,0   */

/* TST.L Dn */
uae_u32 REGPARAM2 op_4a80_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 20;
	CurrentInstrCycles = 4;  
	uae_s32 src = m68k_dreg(regs, srcreg);
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 4 * CYCLE_UNIT / 2 + count_cycles;
}
/* 4 (1/0) */
/* 2 0,0   */

/* TST.L (An) */
uae_u32 REGPARAM2 op_4a90_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 20;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (3/0) */
/* 2 0,0   */

/* TST.L (An)+ */
uae_u32 REGPARAM2 op_4a98_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 20;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) += 4;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (3/0) */
/* 2 0,0   */

/* TST.L -(An) */
uae_u32 REGPARAM2 op_4aa0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 20;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - 4;
	if (srca & 1) {
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception3_read_access(opcode, srca, 2, 1);
		return 2 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) = srca;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 14 * CYCLE_UNIT / 2 + count_cycles;
}
/* 14 (3/0) */
/* 2 0,0   */

/* TST.L (d16,An) */
uae_u32 REGPARAM2 op_4aa8_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 20;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (4/0) */
/* 4 0,0   */

/* TST.L (d8,An,Xn) */
uae_u32 REGPARAM2 op_4ab0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 20;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	BusCyclePenalty += 2;
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (4/0) */
/* 4 4,0   */

/* TST.L (xxx).W */
uae_u32 REGPARAM2 op_4ab8_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 20;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, srca, 2, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (4/0) */
/* 4 0,0   */

/* TST.L (xxx).L */
uae_u32 REGPARAM2 op_4ab9_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 20;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	srca = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	srca |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, srca, 2, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (5/0) */
/* 6 0,0   */

/* TAS.B Dn */
uae_u32 REGPARAM2 op_4ac0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 98;
	CurrentInstrCycles = 4;  
	cpu_bus_rmw=true;
	uae_s8 src = m68k_dreg(regs, srcreg);
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	uae_u8 old_src = src;
	src |= 0x80;
	m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((src) & 0xff);
	cpu_bus_rmw=false;
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 4 * CYCLE_UNIT / 2 + count_cycles;
}
/* 4 (1/0) */
/* 2 0,0   */

/* TAS.B (An) */
uae_u32 REGPARAM2 op_4ad0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 98;
	CurrentInstrCycles = 14; 
	cpu_bus_rmw=true;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		do_cycles(2);
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	uae_u8 old_src = src;
	src |= 0x80;
	put_byte_000(srca, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, src, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	cpu_bus_rmw=false;
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 14 * CYCLE_UNIT / 2 + count_cycles;
}
/* 14 (2/1) */
/* 2 0,0   */

/* TAS.B (An)+ */
uae_u32 REGPARAM2 op_4ad8_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 98;
	CurrentInstrCycles = 14; 
	cpu_bus_rmw=true;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		do_cycles(2);
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	uae_u8 old_src = src;
	src |= 0x80;
	put_byte_000(srca, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, src, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	cpu_bus_rmw=false;
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 14 * CYCLE_UNIT / 2 + count_cycles;
}
/* 14 (2/1) */
/* 2 0,0   */

/* TAS.B -(An) */
uae_u32 REGPARAM2 op_4ae0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 98;
	CurrentInstrCycles = 16; 
	cpu_bus_rmw=true;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		do_cycles(2);
		m68k_incpci(4);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) = srca;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	uae_u8 old_src = src;
	src |= 0x80;
	put_byte_000(srca, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, src, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	cpu_bus_rmw=false;
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (2/1) */
/* 2 0,0   */

/* TAS.B (d16,An) */
uae_u32 REGPARAM2 op_4ae8_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 98;
	CurrentInstrCycles = 18; 
	cpu_bus_rmw=true;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		do_cycles(2);
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	uae_u8 old_src = src;
	src |= 0x80;
	put_byte_000(srca, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, src, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	cpu_bus_rmw=false;
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (3/1) */
/* 4 0,0   */

/* TAS.B (d8,An,Xn) */
uae_u32 REGPARAM2 op_4af0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 98;
	CurrentInstrCycles = 20; 
	cpu_bus_rmw=true;
	uaecptr srca;
	BusCyclePenalty += 2;
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		do_cycles(2);
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	uae_u8 old_src = src;
	src |= 0x80;
	put_byte_000(srca, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, src, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	cpu_bus_rmw=false;
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (3/1) */
/* 4 4,0   */

/* TAS.B (xxx).W */
uae_u32 REGPARAM2 op_4af8_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 98;
	CurrentInstrCycles = 18; 
	cpu_bus_rmw=true;
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		do_cycles(2);
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	uae_u8 old_src = src;
	src |= 0x80;
	put_byte_000(srca, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, src, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	cpu_bus_rmw=false;
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (3/1) */
/* 4 0,0   */

/* TAS.B (xxx).L */
uae_u32 REGPARAM2 op_4af9_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 98;
	CurrentInstrCycles = 22; 
	cpu_bus_rmw=true;
	uaecptr srca;
	srca = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	srca |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		do_cycles(2);
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	uae_u8 old_src = src;
	src |= 0x80;
	put_byte_000(srca, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, src, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	cpu_bus_rmw=false;
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 22 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 22 * CYCLE_UNIT / 2 + count_cycles;
}
/* 22 (4/1) */
/* 6 0,0   */

/* MVMEL.W #<data>.W,(An) */
uae_u32 REGPARAM2 op_4c90_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 37;
	CurrentInstrCycles = 12; 
	uae_u16 mask = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
	uaecptr srca;
	srca = m68k_areg(regs, dstreg);
	if (srca & 1) {
		uaecptr srcav = srca;
		m68k_incpci(6);
		exception3_read_access(opcode, srca, 1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	while (dmask) {
		uae_u32 v = (uae_s32)(uae_s16)get_word_000(srca);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(6);
			exception2_read(opcode, srca + 0, 0x1, 1);
			return 4 * CYCLE_UNIT / 2 + count_cycles;
		}
		m68k_dreg(regs, movem_index1[dmask]) = v;
		srca += 2;
		dmask = movem_next[dmask];
	}
	while (amask) {
		uae_u32 v = (uae_s32)(uae_s16)get_word_000(srca);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(6);
			exception2_read(opcode, srca + 0, 0x1, 1);
			return 4 * CYCLE_UNIT / 2 + count_cycles;
		}
		m68k_areg(regs, movem_index1[amask]) = v;
		srca += 2;
		amask = movem_next[amask];
	}
	get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12+ (3/0) */
/* 4 0,0   */

/* MVMEL.W #<data>.W,(An)+ */
uae_u32 REGPARAM2 op_4c98_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 37;
	CurrentInstrCycles = 12; 
	uae_u16 mask = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
	uaecptr srca;
	srca = m68k_areg(regs, dstreg);
	if (srca & 1) {
		uaecptr srcav = srca;
		m68k_incpci(6);
		exception3_read_access(opcode, srca, 1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	while (dmask) {
		uae_u32 v = (uae_s32)(uae_s16)get_word_000(srca);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(6);
			exception2_read(opcode, srca + 0, 0x1, 1);
			return 4 * CYCLE_UNIT / 2 + count_cycles;
		}
		m68k_dreg(regs, movem_index1[dmask]) = v;
		srca += 2;
		dmask = movem_next[dmask];
	}
	while (amask) {
		uae_u32 v = (uae_s32)(uae_s16)get_word_000(srca);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(6);
			exception2_read(opcode, srca + 0, 0x1, 1);
			return 4 * CYCLE_UNIT / 2 + count_cycles;
		}
		m68k_areg(regs, movem_index1[amask]) = v;
		srca += 2;
		amask = movem_next[amask];
	}
	get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) = srca;
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12+ (3/0) */
/* 4 0,0   */

/* MVMEL.W #<data>.W,(d16,An) */
uae_u32 REGPARAM2 op_4ca8_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 37;
	CurrentInstrCycles = 16; 
	uae_u16 mask = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
	uaecptr srca;
	srca = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		uaecptr srcav = srca;
		m68k_incpci(8);
		exception3_read_access(opcode, srca, 1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	while (dmask) {
		uae_u32 v = (uae_s32)(uae_s16)get_word_000(srca);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(8);
			exception2_read(opcode, srca + 0, 0x1, 1);
			return 8 * CYCLE_UNIT / 2 + count_cycles;
		}
		m68k_dreg(regs, movem_index1[dmask]) = v;
		srca += 2;
		dmask = movem_next[dmask];
	}
	while (amask) {
		uae_u32 v = (uae_s32)(uae_s16)get_word_000(srca);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(8);
			exception2_read(opcode, srca + 0, 0x1, 1);
			return 8 * CYCLE_UNIT / 2 + count_cycles;
		}
		m68k_areg(regs, movem_index1[amask]) = v;
		srca += 2;
		amask = movem_next[amask];
	}
	get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16+ (4/0) */
/* 6 0,0   */

/* MVMEL.W #<data>.W,(d8,An,Xn) */
uae_u32 REGPARAM2 op_4cb0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 37;
	CurrentInstrCycles = 18; 
	uae_u16 mask = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
	uaecptr srca;
	srca = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_000_prefetch(6));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		uaecptr srcav = srca;
		m68k_incpci(4);
		exception3_read_access(opcode, srca, 1, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	while (dmask) {
		uae_u32 v = (uae_s32)(uae_s16)get_word_000(srca);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(8);
			exception2_read(opcode, srca + 0, 0x1, 1);
			return 10 * CYCLE_UNIT / 2 + count_cycles;
		}
		m68k_dreg(regs, movem_index1[dmask]) = v;
		srca += 2;
		dmask = movem_next[dmask];
	}
	while (amask) {
		uae_u32 v = (uae_s32)(uae_s16)get_word_000(srca);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(8);
			exception2_read(opcode, srca + 0, 0x1, 1);
			return 10 * CYCLE_UNIT / 2 + count_cycles;
		}
		m68k_areg(regs, movem_index1[amask]) = v;
		srca += 2;
		amask = movem_next[amask];
	}
	get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18+ (4/0) */
/* 6 4,0   */

/* MVMEL.W #<data>.W,(xxx).W */
uae_u32 REGPARAM2 op_4cb8_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 37;
	CurrentInstrCycles = 16; 
	uae_u16 mask = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		uaecptr srcav = srca;
		m68k_incpci(8);
		exception3_read_access(opcode, srca, 1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	while (dmask) {
		uae_u32 v = (uae_s32)(uae_s16)get_word_000(srca);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(8);
			exception2_read(opcode, srca + 0, 0x1, 1);
			return 8 * CYCLE_UNIT / 2 + count_cycles;
		}
		m68k_dreg(regs, movem_index1[dmask]) = v;
		srca += 2;
		dmask = movem_next[dmask];
	}
	while (amask) {
		uae_u32 v = (uae_s32)(uae_s16)get_word_000(srca);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(8);
			exception2_read(opcode, srca + 0, 0x1, 1);
			return 8 * CYCLE_UNIT / 2 + count_cycles;
		}
		m68k_areg(regs, movem_index1[amask]) = v;
		srca += 2;
		amask = movem_next[amask];
	}
	get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16+ (4/0) */
/* 6 0,0   */

/* MVMEL.W #<data>.W,(xxx).L */
uae_u32 REGPARAM2 op_4cb9_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 37;
	CurrentInstrCycles = 20; 
	uae_u16 mask = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
	uaecptr srca;
	srca = get_word_000_prefetch(6) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	srca |= get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 8, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		uaecptr srcav = srca;
		m68k_incpci(10);
		exception3_read_access(opcode, srca, 1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	while (dmask) {
		uae_u32 v = (uae_s32)(uae_s16)get_word_000(srca);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(10);
			exception2_read(opcode, srca + 0, 0x1, 1);
			return 12 * CYCLE_UNIT / 2 + count_cycles;
		}
		m68k_dreg(regs, movem_index1[dmask]) = v;
		srca += 2;
		dmask = movem_next[dmask];
	}
	while (amask) {
		uae_u32 v = (uae_s32)(uae_s16)get_word_000(srca);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(10);
			exception2_read(opcode, srca + 0, 0x1, 1);
			return 12 * CYCLE_UNIT / 2 + count_cycles;
		}
		m68k_areg(regs, movem_index1[amask]) = v;
		srca += 2;
		amask = movem_next[amask];
	}
	get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(10);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(10);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 10, pcoffset);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(8);
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20+ (5/0) */
/* 8 0,0   */

/* MVMEL.W #<data>.W,(d16,PC) */
uae_u32 REGPARAM2 op_4cba_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 dstreg = 2;
	OpcodeFamily = 37;
	CurrentInstrCycles = 16; 
	uae_u16 mask = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
	uaecptr srca;
	srca = m68k_getpci() + 4;
	srca += (uae_s32)(uae_s16)get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		opcode |= 0x00020000;
		uaecptr srcav = srca;
		m68k_incpci(8);
		exception3_read_access(opcode, srca, 1, 2);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	while (dmask) {
		uae_u32 v = (uae_s32)(uae_s16)get_word_000(srca);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(8);
			exception2_read(opcode, srca + 0, 0x1, 2);
			return 8 * CYCLE_UNIT / 2 + count_cycles;
		}
		m68k_dreg(regs, movem_index1[dmask]) = v;
		srca += 2;
		dmask = movem_next[dmask];
	}
	while (amask) {
		uae_u32 v = (uae_s32)(uae_s16)get_word_000(srca);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(8);
			exception2_read(opcode, srca + 0, 0x1, 2);
			return 8 * CYCLE_UNIT / 2 + count_cycles;
		}
		m68k_areg(regs, movem_index1[amask]) = v;
		srca += 2;
		amask = movem_next[amask];
	}
	get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16+ (4/0) */
/* 6 0,0   */

/* MVMEL.W #<data>.W,(d8,PC,Xn) */
uae_u32 REGPARAM2 op_4cbb_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 dstreg = 3;
	OpcodeFamily = 37;
	CurrentInstrCycles = 18; 
	uae_u16 mask = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
	uaecptr srca;
	uaecptr tmppc = m68k_getpci() + 4;
	srca = get_disp_ea_000(tmppc, get_word_000_prefetch(6));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		opcode |= 0x00020000;
		uaecptr srcav = srca;
		m68k_incpci(4);
		exception3_read_access(opcode, srca, 1, 2);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	while (dmask) {
		uae_u32 v = (uae_s32)(uae_s16)get_word_000(srca);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(8);
			exception2_read(opcode, srca + 0, 0x1, 2);
			return 10 * CYCLE_UNIT / 2 + count_cycles;
		}
		m68k_dreg(regs, movem_index1[dmask]) = v;
		srca += 2;
		dmask = movem_next[dmask];
	}
	while (amask) {
		uae_u32 v = (uae_s32)(uae_s16)get_word_000(srca);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(8);
			exception2_read(opcode, srca + 0, 0x1, 2);
			return 10 * CYCLE_UNIT / 2 + count_cycles;
		}
		m68k_areg(regs, movem_index1[amask]) = v;
		srca += 2;
		amask = movem_next[amask];
	}
	get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18+ (4/0) */
/* 6 4,0   */

/* MVMEL.L #<data>.W,(An) */
uae_u32 REGPARAM2 op_4cd0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 37;
	CurrentInstrCycles = 12; 
	uae_u16 mask = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
	uaecptr srca;
	srca = m68k_areg(regs, dstreg);
	if (srca & 1) {
		uaecptr srcav = srca;
		m68k_incpci(6);
		exception3_read_access(opcode, srca, 2, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	while (dmask) {
		uae_u32 v = (get_word_000(srca) << 16) | (m68k_dreg(regs, movem_index1[dmask]) & 0xffff);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(6);
			exception2_read(opcode, srca + 0, 0x1, 1);
			return 4 * CYCLE_UNIT / 2 + count_cycles;
		}
		m68k_dreg(regs, movem_index1[dmask]) = v;
		v &= 0xffff0000;
		v |= get_word_000(srca + 2); 
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(6);
			exception2_read(opcode, srca + 2, 0x1, 1);
			return 4 * CYCLE_UNIT / 2 + count_cycles;
		}
		m68k_dreg(regs, movem_index1[dmask]) = v;
		srca += 4;
		dmask = movem_next[dmask];
	}
	while (amask) {
		uae_u32 v = (get_word_000(srca) << 16) | (m68k_areg(regs, movem_index1[amask]) & 0xffff);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(6);
			exception2_read(opcode, srca + 0, 0x1, 1);
			return 4 * CYCLE_UNIT / 2 + count_cycles;
		}
		m68k_areg(regs, movem_index1[amask]) = v;
		v &= 0xffff0000;
		v |= get_word_000(srca + 2);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(6);
			exception2_read(opcode, srca + 2, 0x1, 1);
			return 4 * CYCLE_UNIT / 2 + count_cycles;
		}
		m68k_areg(regs, movem_index1[amask]) = v;
		srca += 4;
		amask = movem_next[amask];
	}
	get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12+ (3/0) */
/* 4 0,0   */

/* MVMEL.L #<data>.W,(An)+ */
uae_u32 REGPARAM2 op_4cd8_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 37;
	CurrentInstrCycles = 12; 
	uae_u16 mask = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
	uaecptr srca;
	srca = m68k_areg(regs, dstreg);
	if (srca & 1) {
		uaecptr srcav = srca;
		m68k_incpci(6);
		exception3_read_access(opcode, srca, 2, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	while (dmask) {
		uae_u32 v = (get_word_000(srca) << 16) | (m68k_dreg(regs, movem_index1[dmask]) & 0xffff);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(6);
			exception2_read(opcode, srca + 0, 0x1, 1);
			return 4 * CYCLE_UNIT / 2 + count_cycles;
		}
		m68k_dreg(regs, movem_index1[dmask]) = v;
		v &= 0xffff0000;
		v |= get_word_000(srca + 2); 
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(6);
			exception2_read(opcode, srca + 2, 0x1, 1);
			return 4 * CYCLE_UNIT / 2 + count_cycles;
		}
		m68k_dreg(regs, movem_index1[dmask]) = v;
		srca += 4;
		dmask = movem_next[dmask];
	}
	while (amask) {
		uae_u32 v = (get_word_000(srca) << 16) | (m68k_areg(regs, movem_index1[amask]) & 0xffff);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(6);
			exception2_read(opcode, srca + 0, 0x1, 1);
			return 4 * CYCLE_UNIT / 2 + count_cycles;
		}
		m68k_areg(regs, movem_index1[amask]) = v;
		v &= 0xffff0000;
		v |= get_word_000(srca + 2);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(6);
			exception2_read(opcode, srca + 2, 0x1, 1);
			return 4 * CYCLE_UNIT / 2 + count_cycles;
		}
		m68k_areg(regs, movem_index1[amask]) = v;
		srca += 4;
		amask = movem_next[amask];
	}
	get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) = srca;
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12+ (3/0) */
/* 4 0,0   */

/* MVMEL.L #<data>.W,(d16,An) */
uae_u32 REGPARAM2 op_4ce8_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 37;
	CurrentInstrCycles = 16; 
	uae_u16 mask = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
	uaecptr srca;
	srca = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		uaecptr srcav = srca;
		m68k_incpci(8);
		exception3_read_access(opcode, srca, 2, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	while (dmask) {
		uae_u32 v = (get_word_000(srca) << 16) | (m68k_dreg(regs, movem_index1[dmask]) & 0xffff);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(8);
			exception2_read(opcode, srca + 0, 0x1, 1);
			return 8 * CYCLE_UNIT / 2 + count_cycles;
		}
		m68k_dreg(regs, movem_index1[dmask]) = v;
		v &= 0xffff0000;
		v |= get_word_000(srca + 2); 
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(8);
			exception2_read(opcode, srca + 2, 0x1, 1);
			return 8 * CYCLE_UNIT / 2 + count_cycles;
		}
		m68k_dreg(regs, movem_index1[dmask]) = v;
		srca += 4;
		dmask = movem_next[dmask];
	}
	while (amask) {
		uae_u32 v = (get_word_000(srca) << 16) | (m68k_areg(regs, movem_index1[amask]) & 0xffff);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(8);
			exception2_read(opcode, srca + 0, 0x1, 1);
			return 8 * CYCLE_UNIT / 2 + count_cycles;
		}
		m68k_areg(regs, movem_index1[amask]) = v;
		v &= 0xffff0000;
		v |= get_word_000(srca + 2);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(8);
			exception2_read(opcode, srca + 2, 0x1, 1);
			return 8 * CYCLE_UNIT / 2 + count_cycles;
		}
		m68k_areg(regs, movem_index1[amask]) = v;
		srca += 4;
		amask = movem_next[amask];
	}
	get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16+ (4/0) */
/* 6 0,0   */

/* MVMEL.L #<data>.W,(d8,An,Xn) */
uae_u32 REGPARAM2 op_4cf0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 37;
	CurrentInstrCycles = 18; 
	uae_u16 mask = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
	uaecptr srca;
	srca = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_000_prefetch(6));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		uaecptr srcav = srca;
		m68k_incpci(4);
		exception3_read_access(opcode, srca, 2, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	while (dmask) {
		uae_u32 v = (get_word_000(srca) << 16) | (m68k_dreg(regs, movem_index1[dmask]) & 0xffff);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(8);
			exception2_read(opcode, srca + 0, 0x1, 1);
			return 10 * CYCLE_UNIT / 2 + count_cycles;
		}
		m68k_dreg(regs, movem_index1[dmask]) = v;
		v &= 0xffff0000;
		v |= get_word_000(srca + 2); 
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(8);
			exception2_read(opcode, srca + 2, 0x1, 1);
			return 10 * CYCLE_UNIT / 2 + count_cycles;
		}
		m68k_dreg(regs, movem_index1[dmask]) = v;
		srca += 4;
		dmask = movem_next[dmask];
	}
	while (amask) {
		uae_u32 v = (get_word_000(srca) << 16) | (m68k_areg(regs, movem_index1[amask]) & 0xffff);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(8);
			exception2_read(opcode, srca + 0, 0x1, 1);
			return 10 * CYCLE_UNIT / 2 + count_cycles;
		}
		m68k_areg(regs, movem_index1[amask]) = v;
		v &= 0xffff0000;
		v |= get_word_000(srca + 2);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(8);
			exception2_read(opcode, srca + 2, 0x1, 1);
			return 10 * CYCLE_UNIT / 2 + count_cycles;
		}
		m68k_areg(regs, movem_index1[amask]) = v;
		srca += 4;
		amask = movem_next[amask];
	}
	get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18+ (4/0) */
/* 6 4,0   */

/* MVMEL.L #<data>.W,(xxx).W */
uae_u32 REGPARAM2 op_4cf8_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 37;
	CurrentInstrCycles = 16; 
	uae_u16 mask = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		uaecptr srcav = srca;
		m68k_incpci(8);
		exception3_read_access(opcode, srca, 2, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	while (dmask) {
		uae_u32 v = (get_word_000(srca) << 16) | (m68k_dreg(regs, movem_index1[dmask]) & 0xffff);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(8);
			exception2_read(opcode, srca + 0, 0x1, 1);
			return 8 * CYCLE_UNIT / 2 + count_cycles;
		}
		m68k_dreg(regs, movem_index1[dmask]) = v;
		v &= 0xffff0000;
		v |= get_word_000(srca + 2); 
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(8);
			exception2_read(opcode, srca + 2, 0x1, 1);
			return 8 * CYCLE_UNIT / 2 + count_cycles;
		}
		m68k_dreg(regs, movem_index1[dmask]) = v;
		srca += 4;
		dmask = movem_next[dmask];
	}
	while (amask) {
		uae_u32 v = (get_word_000(srca) << 16) | (m68k_areg(regs, movem_index1[amask]) & 0xffff);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(8);
			exception2_read(opcode, srca + 0, 0x1, 1);
			return 8 * CYCLE_UNIT / 2 + count_cycles;
		}
		m68k_areg(regs, movem_index1[amask]) = v;
		v &= 0xffff0000;
		v |= get_word_000(srca + 2);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(8);
			exception2_read(opcode, srca + 2, 0x1, 1);
			return 8 * CYCLE_UNIT / 2 + count_cycles;
		}
		m68k_areg(regs, movem_index1[amask]) = v;
		srca += 4;
		amask = movem_next[amask];
	}
	get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16+ (4/0) */
/* 6 0,0   */

/* MVMEL.L #<data>.W,(xxx).L */
uae_u32 REGPARAM2 op_4cf9_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 37;
	CurrentInstrCycles = 20; 
	uae_u16 mask = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
	uaecptr srca;
	srca = get_word_000_prefetch(6) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	srca |= get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 8, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		uaecptr srcav = srca;
		m68k_incpci(10);
		exception3_read_access(opcode, srca, 2, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	while (dmask) {
		uae_u32 v = (get_word_000(srca) << 16) | (m68k_dreg(regs, movem_index1[dmask]) & 0xffff);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(10);
			exception2_read(opcode, srca + 0, 0x1, 1);
			return 12 * CYCLE_UNIT / 2 + count_cycles;
		}
		m68k_dreg(regs, movem_index1[dmask]) = v;
		v &= 0xffff0000;
		v |= get_word_000(srca + 2); 
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(10);
			exception2_read(opcode, srca + 2, 0x1, 1);
			return 12 * CYCLE_UNIT / 2 + count_cycles;
		}
		m68k_dreg(regs, movem_index1[dmask]) = v;
		srca += 4;
		dmask = movem_next[dmask];
	}
	while (amask) {
		uae_u32 v = (get_word_000(srca) << 16) | (m68k_areg(regs, movem_index1[amask]) & 0xffff);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(10);
			exception2_read(opcode, srca + 0, 0x1, 1);
			return 12 * CYCLE_UNIT / 2 + count_cycles;
		}
		m68k_areg(regs, movem_index1[amask]) = v;
		v &= 0xffff0000;
		v |= get_word_000(srca + 2);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(10);
			exception2_read(opcode, srca + 2, 0x1, 1);
			return 12 * CYCLE_UNIT / 2 + count_cycles;
		}
		m68k_areg(regs, movem_index1[amask]) = v;
		srca += 4;
		amask = movem_next[amask];
	}
	get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(10);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(10);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 10, pcoffset);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(8);
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20+ (5/0) */
/* 8 0,0   */

/* MVMEL.L #<data>.W,(d16,PC) */
uae_u32 REGPARAM2 op_4cfa_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 dstreg = 2;
	OpcodeFamily = 37;
	CurrentInstrCycles = 16; 
	uae_u16 mask = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
	uaecptr srca;
	srca = m68k_getpci() + 4;
	srca += (uae_s32)(uae_s16)get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		opcode |= 0x00020000;
		uaecptr srcav = srca;
		m68k_incpci(8);
		exception3_read_access(opcode, srca, 2, 2);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	while (dmask) {
		uae_u32 v = (get_word_000(srca) << 16) | (m68k_dreg(regs, movem_index1[dmask]) & 0xffff);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(8);
			exception2_read(opcode, srca + 0, 0x1, 2);
			return 8 * CYCLE_UNIT / 2 + count_cycles;
		}
		m68k_dreg(regs, movem_index1[dmask]) = v;
		v &= 0xffff0000;
		v |= get_word_000(srca + 2); 
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(8);
			exception2_read(opcode, srca + 2, 0x1, 2);
			return 8 * CYCLE_UNIT / 2 + count_cycles;
		}
		m68k_dreg(regs, movem_index1[dmask]) = v;
		srca += 4;
		dmask = movem_next[dmask];
	}
	while (amask) {
		uae_u32 v = (get_word_000(srca) << 16) | (m68k_areg(regs, movem_index1[amask]) & 0xffff);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(8);
			exception2_read(opcode, srca + 0, 0x1, 2);
			return 8 * CYCLE_UNIT / 2 + count_cycles;
		}
		m68k_areg(regs, movem_index1[amask]) = v;
		v &= 0xffff0000;
		v |= get_word_000(srca + 2);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(8);
			exception2_read(opcode, srca + 2, 0x1, 2);
			return 8 * CYCLE_UNIT / 2 + count_cycles;
		}
		m68k_areg(regs, movem_index1[amask]) = v;
		srca += 4;
		amask = movem_next[amask];
	}
	get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16+ (4/0) */
/* 6 0,0   */

/* MVMEL.L #<data>.W,(d8,PC,Xn) */
uae_u32 REGPARAM2 op_4cfb_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 dstreg = 3;
	OpcodeFamily = 37;
	CurrentInstrCycles = 18; 
	uae_u16 mask = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
	uaecptr srca;
	uaecptr tmppc = m68k_getpci() + 4;
	srca = get_disp_ea_000(tmppc, get_word_000_prefetch(6));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		opcode |= 0x00020000;
		uaecptr srcav = srca;
		m68k_incpci(4);
		exception3_read_access(opcode, srca, 2, 2);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	while (dmask) {
		uae_u32 v = (get_word_000(srca) << 16) | (m68k_dreg(regs, movem_index1[dmask]) & 0xffff);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(8);
			exception2_read(opcode, srca + 0, 0x1, 2);
			return 10 * CYCLE_UNIT / 2 + count_cycles;
		}
		m68k_dreg(regs, movem_index1[dmask]) = v;
		v &= 0xffff0000;
		v |= get_word_000(srca + 2); 
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(8);
			exception2_read(opcode, srca + 2, 0x1, 2);
			return 10 * CYCLE_UNIT / 2 + count_cycles;
		}
		m68k_dreg(regs, movem_index1[dmask]) = v;
		srca += 4;
		dmask = movem_next[dmask];
	}
	while (amask) {
		uae_u32 v = (get_word_000(srca) << 16) | (m68k_areg(regs, movem_index1[amask]) & 0xffff);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(8);
			exception2_read(opcode, srca + 0, 0x1, 2);
			return 10 * CYCLE_UNIT / 2 + count_cycles;
		}
		m68k_areg(regs, movem_index1[amask]) = v;
		v &= 0xffff0000;
		v |= get_word_000(srca + 2);
		count_cycles += 4 * CYCLE_UNIT / 2;
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(8);
			exception2_read(opcode, srca + 2, 0x1, 2);
			return 10 * CYCLE_UNIT / 2 + count_cycles;
		}
		m68k_areg(regs, movem_index1[amask]) = v;
		srca += 4;
		amask = movem_next[amask];
	}
	get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18+ (4/0) */
/* 6 4,0   */

/* LINK.W An,#<data>.W */
uae_u32 REGPARAM2 op_4e50_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 47;
	CurrentInstrCycles = 16; 
	uae_s32 src = m68k_areg(regs, srcreg);
	uaecptr olda;
	olda = m68k_areg(regs, 7) - 4;
	m68k_areg(regs, 7) = olda;
	uae_s16 offs = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		m68k_areg(regs, 7) += 4;
		exception2_fetch(opcode, 4, 2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (olda & 1) {
		m68k_areg(regs, 7) += 4;
		m68k_areg(regs, srcreg) = olda;
		m68k_incpci(6);
		exception3_write_access(opcode, olda, sz_word, src >> 16, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(olda, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		m68k_areg(regs, 7) += 4;
		m68k_areg(regs, srcreg) = olda;
		exception2_write(opcode, olda + 0, 0x1, src >> 16, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(olda + 2, src); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		m68k_areg(regs, 7) += 4;
		m68k_areg(regs, srcreg) = olda;
		exception2_write(opcode, olda + 2, 0x1, src, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) = (m68k_areg(regs, 7));
	m68k_areg(regs, 7) += offs;
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (2/2) */
/* 4 0,0   */

/* UNLK.L An */
uae_u32 REGPARAM2 op_4e58_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 48;
	CurrentInstrCycles = 12; 
	uae_s32 src = m68k_areg(regs, srcreg);
	uae_u32 olda = src;
	if (olda & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, olda, 2, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 old = get_word_000(olda) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, olda + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	old |= get_word_000(olda + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, olda + 2, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, 7) = src + 4;
	m68k_areg(regs, srcreg) = (old);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (3/0) */
/* 2 0,0   */

/* MVR2USP.L An */
uae_u32 REGPARAM2 op_4e60_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 40;
	CurrentInstrCycles = 4;  
	if (!regs.s) {
		Exception(8);
		return 0;
	}
	uae_s32 src = m68k_areg(regs, srcreg);
	regs.usp = src;
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 4 * CYCLE_UNIT / 2 + count_cycles;
}
/* 4 (1/0) */
/* 2 0,0   */

/* MVUSP2R.L An */
uae_u32 REGPARAM2 op_4e68_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 41;
	CurrentInstrCycles = 4;  
	if (!regs.s) {
		Exception(8);
		return 0;
	}
	m68k_areg(regs, srcreg) = (regs.usp);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 4 * CYCLE_UNIT / 2 + count_cycles;
}
/* 4 (1/0) */
/* 2 0,0   */

/* RESET.L  */
uae_u32 REGPARAM2 op_4e70_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 42;
	CurrentInstrCycles = 132;
	if (!regs.s) {
		Exception(8);
		return 0;
	}
	bool r = cpureset();
	if (r) {
		return 128 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 132 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 132 * CYCLE_UNIT / 2 + count_cycles;
}
/* 132 (1/0) */
/* 2 0,0   */

/* NOP.L  */
uae_u32 REGPARAM2 op_4e71_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 43;
	CurrentInstrCycles = 4;  
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 4 * CYCLE_UNIT / 2 + count_cycles;
}
/* 4 (1/0) */
/* 2 0,0   */

/* STOP.L #<data>.W */
uae_u32 REGPARAM2 op_4e72_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 44;
	CurrentInstrCycles = 4;  
	if (!regs.s) {
		Exception(8);
		return 0;
	}
	if (!regs.stopped) {
		uae_u16 src = regs.irc;
		regs.irc = src;
	}
	uae_u16 sr = regs.irc;
	checkint();
	regs.sr = sr;
	MakeFromSR_STOP();
	do_cycles_stop(4);
	m68k_setstopped(1);
	return 4 * CYCLE_UNIT / 2 + count_cycles;
}
/* 4 (0/0) */

/* RTE.L  */
uae_u32 REGPARAM2 op_4e73_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 45;
	CurrentInstrCycles = 20; 
	if (!regs.s) {
		Exception(8);
		return 0;
	}
	if (m68k_areg(regs, 7) & 1) {
		exception3_read_access(opcode, m68k_areg(regs, 7), 1, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr oldpc = m68k_getpci();
	uaecptr a = m68k_areg(regs, 7);
	uae_u16 sr = get_word_000(a);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		exception2_read(opcode, a + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, 7) += 6;
	uae_u32 pc = get_word_000(a + 2) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		exception2_read(opcode, a + 2, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	pc |= get_word_000(a + 2 + 2); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		exception2_read(opcode, a + 4, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u16 oldt1 = regs.t1;
	regs.sr = sr;
	MakeFromSR();
	if (pc & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode | 0x20000, pc, 1, 2);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_setpci_j(pc);
	opcode |= 0x20000;
	#ifdef DEBUGGER
	branch_stack_pop_rte(oldpc);
	#endif
	int pcadjust = oldpc - m68k_getpci() + 2;
	get_word_000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		pcoffset += pcadjust;
		exception2_fetch_opcode(opcode, 0, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	if(oldt1) opcode |= 0x10000;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (5/0) */
/* 2 0,0 B */

/* RTS.L  */
uae_u32 REGPARAM2 op_4e75_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 49;
	CurrentInstrCycles = 16; 
	uaecptr oldpc = m68k_getpci();
	if (m68k_areg(regs, 7) & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, m68k_areg(regs, 7), 1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr newpc, dsta = m68k_areg(regs, 7);
	newpc = get_word_000(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	newpc |= get_word_000(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, 7) += 4;
	m68k_setpci_j(newpc);
	#ifdef DEBUGGER
	if (debugmem_trace) {
		branch_stack_pop_rts(oldpc);
	}
	#endif
	if (m68k_getpci() & 1) {
		uaecptr faultpc = m68k_getpci();
		m68k_setpci_j(oldpc);
		m68k_incpci(2);
		exception3_read_prefetch_only(opcode, faultpc);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	int pcadjust = oldpc - m68k_getpci() + 2;
	get_word_000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		pcoffset += pcadjust;
		exception2_fetch_opcode(opcode, 0, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	if(regs.t1) opcode |= 0x10000;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (4/0) */
/* 2 0,0 B */

/* TRAPV.L  */
uae_u32 REGPARAM2 op_4e76_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 50;
	CurrentInstrCycles = 4;  
	m68k_incpci(2);
	uae_u16 opcode_v = opcode;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (GET_VFLG()) {
			MakeSR();
			regs.sr |= 0x2000;
			regs.sr &= ~0x8000;
			MakeFromSR();
			pcoffset -= 2;
		} else {
			opcode = regs.ir | 0x20000;
			if(regs.t1) opcode |= 0x10000;
		}
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	if (GET_VFLG()) {
		regs.ir = opcode_v;
		Exception_cpu(7);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 4 * CYCLE_UNIT / 2 + count_cycles;
}
/* 4 (1/0) */
/* 2 0,0   */

/* RTR.L  */
uae_u32 REGPARAM2 op_4e77_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 51;
	CurrentInstrCycles = 20; 
	if (m68k_areg(regs, 7) & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, m68k_areg(regs, 7), 1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr oldpc = m68k_getpci();
	MakeSR();
	uaecptr sra;
	sra = m68k_areg(regs, 7);
	if (sra & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, sra, 1, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 sr = get_word_000(sra);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, sra + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, 7) += 2;
	uaecptr pca;
	pca = m68k_areg(regs, 7);
	if (pca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, pca, 2, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 pc = get_word_000(pca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, pca + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	pc |= get_word_000(pca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, pca + 2, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, 7) += 4;
	regs.sr &= 0xFF00; sr &= 0xFF;
	regs.sr |= sr;
	MakeFromSR();
	m68k_setpci_j(pc);
	if (m68k_getpci() & 1) {
		uaecptr faultpc = m68k_getpci();
		m68k_setpci_j(oldpc + 2);
		exception3_read_prefetch_only(opcode, faultpc);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	int pcadjust = oldpc - m68k_getpci() + 2;
	get_word_000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		pcoffset += pcadjust;
		exception2_fetch_opcode(opcode, 0, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	if(regs.t1) opcode |= 0x10000;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (5/0) */
/* 2 0,0 B */

/* JSR.L (An) */
uae_u32 REGPARAM2 op_4e90_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 52;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	uaecptr oldpc = m68k_getpci();
	uaecptr nextpc = oldpc + 2;
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_prefetch_only(opcode, srca);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_setpci_j(srca);
	get_word_000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		pcoffset = (oldpc - srca) + 2;
		exception2_fetch_opcode(opcode, 0, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, 7) -= 4;
	if (m68k_areg(regs, 7) & 1) {
		m68k_setpci_j(oldpc);
		m68k_incpci(2);
		exception3_write_access(opcode, m68k_areg(regs, 7), 1, m68k_areg(regs, 7) >> 16, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta = m68k_areg(regs, 7);
	put_word_000(dsta, nextpc >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_write(opcode, dsta + 0, 0x1, nextpc >> 16, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta + 2, nextpc);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_write(opcode, dsta + 2, 0x1, nextpc, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	#ifdef DEBUGGER
	if (debugmem_trace) {
		branch_stack_push(oldpc, nextpc);
	}
	#endif
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, 0);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (2/2) */
/* 2 0,0 B */

/* JSR.L (d16,An) */
uae_u32 REGPARAM2 op_4ea8_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 52;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)regs.irc;
	uaecptr oldpc = m68k_getpci();
	uaecptr nextpc = oldpc + 4;
	if (srca & 1) {
		count_cycles += 2 * CYCLE_UNIT / 2;
		m68k_incpci(2);
		exception3_read_prefetch_only(opcode, srca);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_setpci_j(srca);
	get_word_000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		pcoffset = (oldpc - srca) + 4;
		exception2_fetch_opcode(opcode, 0, pcoffset);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, 7) -= 4;
	if (m68k_areg(regs, 7) & 1) {
		m68k_setpci_j(oldpc);
		m68k_incpci(4);
		exception3_write_access(opcode, m68k_areg(regs, 7), 1, m68k_areg(regs, 7) >> 16, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta = m68k_areg(regs, 7);
	put_word_000(dsta, nextpc >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_write(opcode, dsta + 0, 0x1, nextpc >> 16, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta + 2, nextpc);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_write(opcode, dsta + 2, 0x1, nextpc, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	#ifdef DEBUGGER
	if (debugmem_trace) {
		branch_stack_push(oldpc, nextpc);
	}
	#endif
	regs.ir = regs.irc;
	opcode = regs.ir;
	if(regs.t1) opcode |= 0x10000;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, 0);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (2/2) */
/* 4 0,0 B */

/* JSR.L (d8,An,Xn) */
uae_u32 REGPARAM2 op_4eb0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 52;
	CurrentInstrCycles = 24; 
	uaecptr srca;
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), regs.irc);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr oldpc = m68k_getpci();
	uaecptr nextpc = oldpc + 2;
	if (srca & 1) {
		count_cycles += 6 * CYCLE_UNIT / 2;
		m68k_incpci(2);
		exception3_read_prefetch_only(opcode, srca);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	nextpc += 2;
	m68k_setpci_j(srca);
	get_word_000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		pcoffset = (oldpc - srca) + 4;
		exception2_fetch_opcode(opcode, 0, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, 7) -= 4;
	if (m68k_areg(regs, 7) & 1) {
		m68k_setpci_j(oldpc);
		m68k_incpci(4);
		exception3_write_access(opcode, m68k_areg(regs, 7), 1, m68k_areg(regs, 7) >> 16, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta = m68k_areg(regs, 7);
	put_word_000(dsta, nextpc >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_write(opcode, dsta + 0, 0x1, nextpc >> 16, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta + 2, nextpc);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_write(opcode, dsta + 2, 0x1, nextpc, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	#ifdef DEBUGGER
	if (debugmem_trace) {
		branch_stack_push(oldpc, nextpc);
	}
	#endif
	regs.ir = regs.irc;
	opcode = regs.ir;
	if(regs.t1) opcode |= 0x10000;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, 0);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 24 * CYCLE_UNIT / 2 + count_cycles;
}
/* 24 (2/2) */
/* 2 2,0 B */

/* JSR.L (xxx).W */
uae_u32 REGPARAM2 op_4eb8_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 52;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)regs.irc;
	uaecptr oldpc = m68k_getpci();
	uaecptr nextpc = oldpc + 4;
	if (srca & 1) {
		count_cycles += 2 * CYCLE_UNIT / 2;
		m68k_incpci(4);
		exception3_read_prefetch_only(opcode, srca);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_setpci_j(srca);
	get_word_000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		pcoffset = (oldpc - srca) + 4;
		exception2_fetch_opcode(opcode, 0, pcoffset);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, 7) -= 4;
	if (m68k_areg(regs, 7) & 1) {
		m68k_setpci_j(oldpc);
		m68k_incpci(4);
		exception3_write_access(opcode, m68k_areg(regs, 7), 1, m68k_areg(regs, 7) >> 16, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta = m68k_areg(regs, 7);
	put_word_000(dsta, nextpc >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x1, nextpc >> 16, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta + 2, nextpc);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 2, 0x1, nextpc, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	#ifdef DEBUGGER
	if (debugmem_trace) {
		branch_stack_push(oldpc, nextpc);
	}
	#endif
	regs.ir = regs.irc;
	opcode = regs.ir;
	if(regs.t1) opcode |= 0x10000;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, 0);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (2/2) */
/* 4 0,0 B */

/* JSR.L (xxx).L */
uae_u32 REGPARAM2 op_4eb9_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 52;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	srca = get_word_000_prefetch(4) << 16;
	srca |= regs.irc;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr oldpc = m68k_getpci();
	uaecptr nextpc = oldpc + 6;
	if (srca & 1) {
		m68k_incpci(6);
		exception3_read_prefetch_only(opcode, srca);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_setpci_j(srca);
	get_word_000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		pcoffset = (oldpc - srca) + 6;
		exception2_fetch_opcode(opcode, 0, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, 7) -= 4;
	if (m68k_areg(regs, 7) & 1) {
		m68k_setpci_j(oldpc);
		m68k_incpci(6);
		exception3_write_access(opcode, m68k_areg(regs, 7), 1, m68k_areg(regs, 7) >> 16, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta = m68k_areg(regs, 7);
	put_word_000(dsta, nextpc >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, nextpc >> 16, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta + 2, nextpc);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 2, 0x1, nextpc, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	#ifdef DEBUGGER
	if (debugmem_trace) {
		branch_stack_push(oldpc, nextpc);
	}
	#endif
	regs.ir = regs.irc;
	opcode = regs.ir;
	if(regs.t1) opcode |= 0x10000;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, 0);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (3/2) */
/* 6 0,0 B */

/* JSR.L (d16,PC) */
uae_u32 REGPARAM2 op_4eba_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 52;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	srca = m68k_getpci() + 2;
	srca += (uae_s32)(uae_s16)regs.irc;
	uaecptr oldpc = m68k_getpci();
	uaecptr nextpc = oldpc + 4;
	if (srca & 1) {
		count_cycles += 2 * CYCLE_UNIT / 2;
		m68k_incpci(2);
		exception3_read_prefetch_only(opcode, srca);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_setpci_j(srca);
	get_word_000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		pcoffset = (oldpc - srca) + 4;
		exception2_fetch_opcode(opcode, 0, pcoffset);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, 7) -= 4;
	if (m68k_areg(regs, 7) & 1) {
		m68k_setpci_j(oldpc);
		m68k_incpci(4);
		exception3_write_access(opcode, m68k_areg(regs, 7), 1, m68k_areg(regs, 7) >> 16, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta = m68k_areg(regs, 7);
	put_word_000(dsta, nextpc >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_write(opcode, dsta + 0, 0x1, nextpc >> 16, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta + 2, nextpc);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_write(opcode, dsta + 2, 0x1, nextpc, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	#ifdef DEBUGGER
	if (debugmem_trace) {
		branch_stack_push(oldpc, nextpc);
	}
	#endif
	regs.ir = regs.irc;
	opcode = regs.ir;
	if(regs.t1) opcode |= 0x10000;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, 0);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (2/2) */
/* 4 0,0 B */

/* JSR.L (d8,PC,Xn) */
uae_u32 REGPARAM2 op_4ebb_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 52;
	CurrentInstrCycles = 24; 
	uaecptr srca;
	uaecptr tmppc = m68k_getpci() + 2;
	srca = get_disp_ea_000(tmppc, regs.irc);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr oldpc = m68k_getpci();
	uaecptr nextpc = oldpc + 2;
	if (srca & 1) {
		count_cycles += 6 * CYCLE_UNIT / 2;
		m68k_incpci(2);
		exception3_read_prefetch_only(opcode, srca);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	nextpc += 2;
	m68k_setpci_j(srca);
	get_word_000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		pcoffset = (oldpc - srca) + 4;
		exception2_fetch_opcode(opcode, 0, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, 7) -= 4;
	if (m68k_areg(regs, 7) & 1) {
		m68k_setpci_j(oldpc);
		m68k_incpci(4);
		exception3_write_access(opcode, m68k_areg(regs, 7), 1, m68k_areg(regs, 7) >> 16, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr dsta = m68k_areg(regs, 7);
	put_word_000(dsta, nextpc >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_write(opcode, dsta + 0, 0x1, nextpc >> 16, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta + 2, nextpc);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_write(opcode, dsta + 2, 0x1, nextpc, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	#ifdef DEBUGGER
	if (debugmem_trace) {
		branch_stack_push(oldpc, nextpc);
	}
	#endif
	regs.ir = regs.irc;
	opcode = regs.ir;
	if(regs.t1) opcode |= 0x10000;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, 0);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 24 * CYCLE_UNIT / 2 + count_cycles;
}
/* 24 (2/2) */
/* 2 2,0 B */

/* JMP.L (An) */
uae_u32 REGPARAM2 op_4ed0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 53;
	CurrentInstrCycles = 8;  
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	uaecptr oldpc = m68k_getpci();
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_prefetch_only(opcode, srca);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_setpci_j(srca);
	get_word_000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		pcoffset = (oldpc - srca) + 2;
		exception2_fetch_opcode(opcode, 0, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	get_word_000_prefetch(2);
	opcode = regs.ir;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, 0);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8 (2/0) */
/* 2 0,0 B */

/* JMP.L (d16,An) */
uae_u32 REGPARAM2 op_4ee8_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 53;
	CurrentInstrCycles = 10; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)regs.irc;
	uaecptr oldpc = m68k_getpci();
	if (srca & 1) {
		count_cycles += 2 * CYCLE_UNIT / 2;
		m68k_incpci(2);
		exception3_read_prefetch_only(opcode, srca);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_setpci_j(srca);
	get_word_000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		pcoffset = (oldpc - srca) + 2;
		exception2_fetch_opcode(opcode, 0, pcoffset);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	get_word_000_prefetch(2);
	opcode = regs.ir;
	if(regs.t1) opcode |= 0x10000;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, 0);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 10 * CYCLE_UNIT / 2 + count_cycles;
}
/* 10 (2/0) */
/* 4 0,0 B */

/* JMP.L (d8,An,Xn) */
uae_u32 REGPARAM2 op_4ef0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 53;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), regs.irc);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr oldpc = m68k_getpci();
	if (srca & 1) {
		count_cycles += 6 * CYCLE_UNIT / 2;
		m68k_incpci(2);
		exception3_read_prefetch_only(opcode, srca);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_setpci_j(srca);
	get_word_000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		pcoffset = (oldpc - srca) + 2;
		exception2_fetch_opcode(opcode, 0, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	get_word_000_prefetch(2);
	opcode = regs.ir;
	if(regs.t1) opcode |= 0x10000;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, 0);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (2/0) */
/* 2 2,0 B */

/* JMP.L (xxx).W */
uae_u32 REGPARAM2 op_4ef8_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 53;
	CurrentInstrCycles = 10; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)regs.irc;
	uaecptr oldpc = m68k_getpci();
	if (srca & 1) {
		count_cycles += 2 * CYCLE_UNIT / 2;
		m68k_incpci(2);
		exception3_read_prefetch_only(opcode, srca);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_setpci_j(srca);
	get_word_000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		pcoffset = (oldpc - srca) + 2;
		exception2_fetch_opcode(opcode, 0, pcoffset);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	get_word_000_prefetch(2);
	opcode = regs.ir;
	if(regs.t1) opcode |= 0x10000;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, 0);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 10 * CYCLE_UNIT / 2 + count_cycles;
}
/* 10 (2/0) */
/* 4 0,0 B */

/* JMP.L (xxx).L */
uae_u32 REGPARAM2 op_4ef9_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 53;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = get_word_000_prefetch(4) << 16;
	srca |= regs.irc;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr oldpc = m68k_getpci();
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_prefetch_only(opcode, srca);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_setpci_j(srca);
	get_word_000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		pcoffset = (oldpc - srca) + 2;
		exception2_fetch_opcode(opcode, 0, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	get_word_000_prefetch(2);
	opcode = regs.ir;
	if(regs.t1) opcode |= 0x10000;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, 0);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (3/0) */
/* 6 0,0 B */

/* JMP.L (d16,PC) */
uae_u32 REGPARAM2 op_4efa_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 53;
	CurrentInstrCycles = 10; 
	uaecptr srca;
	srca = m68k_getpci() + 2;
	srca += (uae_s32)(uae_s16)regs.irc;
	uaecptr oldpc = m68k_getpci();
	if (srca & 1) {
		count_cycles += 2 * CYCLE_UNIT / 2;
		m68k_incpci(2);
		exception3_read_prefetch_only(opcode, srca);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_setpci_j(srca);
	get_word_000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		pcoffset = (oldpc - srca) + 2;
		exception2_fetch_opcode(opcode, 0, pcoffset);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	get_word_000_prefetch(2);
	opcode = regs.ir;
	if(regs.t1) opcode |= 0x10000;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, 0);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 10 * CYCLE_UNIT / 2 + count_cycles;
}
/* 10 (2/0) */
/* 4 0,0 B */

/* JMP.L (d8,PC,Xn) */
uae_u32 REGPARAM2 op_4efb_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 53;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	uaecptr tmppc = m68k_getpci() + 2;
	srca = get_disp_ea_000(tmppc, regs.irc);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uaecptr oldpc = m68k_getpci();
	if (srca & 1) {
		count_cycles += 6 * CYCLE_UNIT / 2;
		m68k_incpci(2);
		exception3_read_prefetch_only(opcode, srca);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_setpci_j(srca);
	get_word_000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		pcoffset = (oldpc - srca) + 2;
		exception2_fetch_opcode(opcode, 0, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	get_word_000_prefetch(2);
	opcode = regs.ir;
	if(regs.t1) opcode |= 0x10000;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, 0);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (2/0) */
/* 2 2,0 B */

/* ADDQ.B #<data>,Dn */
uae_u32 REGPARAM2 op_5000_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 4;  
	uae_u32 src = srcreg;
	uae_s8 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u8)(~dst)) < ((uae_u8)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 4 * CYCLE_UNIT / 2 + count_cycles;
}
/* 4 (1/0) */
/* 2 0,0   */

/* ADDQ.B #<data>,(An) */
uae_u32 REGPARAM2 op_5010_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 12; 
	uae_u32 src = srcreg;
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u8)(~dst)) < ((uae_u8)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_byte_000(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, newv, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (2/1) */
/* 2 0,0   */

/* ADDQ.B #<data>,(An)+ */
uae_u32 REGPARAM2 op_5018_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 12; 
	uae_u32 src = srcreg;
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
	uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u8)(~dst)) < ((uae_u8)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_byte_000(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, newv, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (2/1) */
/* 2 0,0   */

/* ADDQ.B #<data>,-(An) */
uae_u32 REGPARAM2 op_5020_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 14; 
	uae_u32 src = srcreg;
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, dstreg) = dsta;
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) = dsta;
	uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u8)(~dst)) < ((uae_u8)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_byte_000(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, newv, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 14 * CYCLE_UNIT / 2 + count_cycles;
}
/* 14 (2/1) */
/* 2 0,0   */

/* ADDQ.B #<data>,(d16,An) */
uae_u32 REGPARAM2 op_5028_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 16; 
	uae_u32 src = srcreg;
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u8)(~dst)) < ((uae_u8)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_byte_000(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, newv, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 4 0,0   */

/* ADDQ.B #<data>,(d8,An,Xn) */
uae_u32 REGPARAM2 op_5030_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 18; 
	uae_u32 src = srcreg;
	uaecptr dsta;
	BusCyclePenalty += 2;
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u8)(~dst)) < ((uae_u8)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_byte_000(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, newv, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (3/1) */
/* 4 4,0   */

/* ADDQ.B #<data>,(xxx).W */
uae_u32 REGPARAM2 op_5038_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	OpcodeFamily = 11;
	CurrentInstrCycles = 16; 
	uae_u32 src = srcreg;
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u8)(~dst)) < ((uae_u8)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_byte_000(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, newv, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 4 0,0   */

/* ADDQ.B #<data>,(xxx).L */
uae_u32 REGPARAM2 op_5039_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	OpcodeFamily = 11;
	CurrentInstrCycles = 20; 
	uae_u32 src = srcreg;
	uaecptr dsta;
	dsta = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	dsta |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u8)(~dst)) < ((uae_u8)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_byte_000(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, newv, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (4/1) */
/* 6 0,0   */

/* ADDQ.W #<data>,Dn */
uae_u32 REGPARAM2 op_5040_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 4;  
	uae_u32 src = srcreg;
	uae_s16 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 4 * CYCLE_UNIT / 2 + count_cycles;
}
/* 4 (1/0) */
/* 2 0,0   */

/* ADDAQ.W #<data>,An */
uae_u32 REGPARAM2 op_5048_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 12;
	CurrentInstrCycles = 8;  
	uae_u32 src = srcreg;
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = dst + src;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		areg_68000_long_replace_low(dstreg, newv);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	m68k_areg(regs, dstreg) = (newv);
	m68k_incpci(2);
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8 (1/0) */
/* 2 0,0   */

/* ADDQ.W #<data>,(An) */
uae_u32 REGPARAM2 op_5050_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 12; 
	uae_u32 src = srcreg;
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	if (dsta & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dsta, 1, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = get_word_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_word_000(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x1, newv, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (2/1) */
/* 2 0,0   */

/* ADDQ.W #<data>,(An)+ */
uae_u32 REGPARAM2 op_5058_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 12; 
	uae_u32 src = srcreg;
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	if (dsta & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dsta, 1, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = get_word_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, dstreg) += 2 + 0;
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) += 2;
	uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_word_000(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x1, newv, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (2/1) */
/* 2 0,0   */

/* ADDQ.W #<data>,-(An) */
uae_u32 REGPARAM2 op_5060_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 14; 
	uae_u32 src = srcreg;
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - 2;
	if (dsta & 1) {
		m68k_incpci(4);
		m68k_areg(regs, dstreg) = dsta;
		exception3_read_access(opcode, dsta, 1, 1);
		return 2 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = get_word_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, dstreg) = dsta;
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) = dsta;
	uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_word_000(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x1, newv, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 14 * CYCLE_UNIT / 2 + count_cycles;
}
/* 14 (2/1) */
/* 2 0,0   */

/* ADDQ.W #<data>,(d16,An) */
uae_u32 REGPARAM2 op_5068_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 16; 
	uae_u32 src = srcreg;
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dsta, 1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = get_word_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_word_000(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x1, newv, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 4 0,0   */

/* ADDQ.W #<data>,(d8,An,Xn) */
uae_u32 REGPARAM2 op_5070_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 18; 
	uae_u32 src = srcreg;
	uaecptr dsta;
	BusCyclePenalty += 2;
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dsta, 1, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = get_word_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_word_000(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x1, newv, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (3/1) */
/* 4 4,0   */

/* ADDQ.W #<data>,(xxx).W */
uae_u32 REGPARAM2 op_5078_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	OpcodeFamily = 11;
	CurrentInstrCycles = 16; 
	uae_u32 src = srcreg;
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, dsta, 1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = get_word_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_word_000(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x1, newv, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 4 0,0   */

/* ADDQ.W #<data>,(xxx).L */
uae_u32 REGPARAM2 op_5079_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	OpcodeFamily = 11;
	CurrentInstrCycles = 20; 
	uae_u32 src = srcreg;
	uaecptr dsta;
	dsta = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	dsta |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, dsta, 1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = get_word_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_word_000(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x1, newv, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (4/1) */
/* 6 0,0   */

/* ADDQ.L #<data>,Dn */
uae_u32 REGPARAM2 op_5080_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 8;  
	uae_u32 src = srcreg;
	uae_s32 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u32)(~dst)) < ((uae_u32)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		uae_s16 bnewv = (uae_s16)dst + (uae_s16)src;
		int bflgs = ((uae_s16)(src)) < 0;
		int bflgo = ((uae_s16)(dst)) < 0;
		int bflgn = bnewv < 0;
		ccr_68000_long_move_ae_LZN(bnewv);
		SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
		SET_XFLG(GET_CFLG());
		SET_VFLG((bflgs ^ bflgn) & (bflgo ^ bflgn));
		dreg_68000_long_replace_low(dstreg, bnewv);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	m68k_dreg(regs, dstreg) = (newv);
	m68k_incpci(2);
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8 (1/0) */
/* 2 0,0   */

/* ADDAQ.L #<data>,An */
uae_u32 REGPARAM2 op_5088_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 12;
	CurrentInstrCycles = 8;  
	uae_u32 src = srcreg;
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = dst + src;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		areg_68000_long_replace_low(dstreg, newv);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	m68k_areg(regs, dstreg) = (newv);
	m68k_incpci(2);
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8 (1/0) */
/* 2 0,0   */

/* ADDQ.L #<data>,(An) */
uae_u32 REGPARAM2 op_5090_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 20; 
	uae_u32 src = srcreg;
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	if (dsta & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dsta, 2, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = get_word_000(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	dst |= get_word_000(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u32)(~dst)) < ((uae_u32)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		uae_s16 bnewv = (uae_s16)dst + (uae_s16)src;
		int bflgs = ((uae_s16)(src)) < 0;
		int bflgo = ((uae_s16)(dst)) < 0;
		int bflgn = bnewv < 0;
		ccr_68000_long_move_ae_LZN(bnewv);
		SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
		SET_XFLG(GET_CFLG());
		SET_VFLG((bflgs ^ bflgn) & (bflgo ^ bflgn));
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta + 2, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 2, 0x1, newv, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, newv >> 16); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x1, newv >> 16, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (3/2) */
/* 2 0,0   */

/* ADDQ.L #<data>,(An)+ */
uae_u32 REGPARAM2 op_5098_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 20; 
	uae_u32 src = srcreg;
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	if (dsta & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dsta, 2, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = get_word_000(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	dst |= get_word_000(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) += 4;
	uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u32)(~dst)) < ((uae_u32)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		uae_s16 bnewv = (uae_s16)dst + (uae_s16)src;
		int bflgs = ((uae_s16)(src)) < 0;
		int bflgo = ((uae_s16)(dst)) < 0;
		int bflgn = bnewv < 0;
		ccr_68000_long_move_ae_LZN(bnewv);
		SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
		SET_XFLG(GET_CFLG());
		SET_VFLG((bflgs ^ bflgn) & (bflgo ^ bflgn));
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta + 2, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 2, 0x1, newv, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, newv >> 16); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x1, newv >> 16, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (3/2) */
/* 2 0,0   */

/* ADDQ.L #<data>,-(An) */
uae_u32 REGPARAM2 op_50a0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 22; 
	uae_u32 src = srcreg;
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - 4;
	if (dsta & 1) {
		m68k_incpci(2);
		m68k_areg(regs, dstreg) = dsta;
		exception3_read_access(opcode, dsta, 2, 1);
		return 2 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = get_word_000(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, dstreg) = dsta;
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	dst |= get_word_000(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, dstreg) = dsta;
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) = dsta;
	uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u32)(~dst)) < ((uae_u32)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		uae_s16 bnewv = (uae_s16)dst + (uae_s16)src;
		int bflgs = ((uae_s16)(src)) < 0;
		int bflgo = ((uae_s16)(dst)) < 0;
		int bflgn = bnewv < 0;
		ccr_68000_long_move_ae_LZN(bnewv);
		SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
		SET_XFLG(GET_CFLG());
		SET_VFLG((bflgs ^ bflgn) & (bflgo ^ bflgn));
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta + 2, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 2, 0x1, newv, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, newv >> 16); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x1, newv >> 16, 1);
		return 22 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 22 * CYCLE_UNIT / 2 + count_cycles;
}
/* 22 (3/2) */
/* 2 0,0   */

/* ADDQ.L #<data>,(d16,An) */
uae_u32 REGPARAM2 op_50a8_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 24; 
	uae_u32 src = srcreg;
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dsta, 2, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = get_word_000(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	dst |= get_word_000(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u32)(~dst)) < ((uae_u32)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		uae_s16 bnewv = (uae_s16)dst + (uae_s16)src;
		int bflgs = ((uae_s16)(src)) < 0;
		int bflgo = ((uae_s16)(dst)) < 0;
		int bflgn = bnewv < 0;
		ccr_68000_long_move_ae_LZN(bnewv);
		SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
		SET_XFLG(GET_CFLG());
		SET_VFLG((bflgs ^ bflgn) & (bflgo ^ bflgn));
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta + 2, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 2, 0x1, newv, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, newv >> 16); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, newv >> 16, 1);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 24 * CYCLE_UNIT / 2 + count_cycles;
}
/* 24 (4/2) */
/* 4 0,0   */

/* ADDQ.L #<data>,(d8,An,Xn) */
uae_u32 REGPARAM2 op_50b0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 26; 
	uae_u32 src = srcreg;
	uaecptr dsta;
	BusCyclePenalty += 2;
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dsta, 2, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = get_word_000(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	dst |= get_word_000(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u32)(~dst)) < ((uae_u32)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		uae_s16 bnewv = (uae_s16)dst + (uae_s16)src;
		int bflgs = ((uae_s16)(src)) < 0;
		int bflgo = ((uae_s16)(dst)) < 0;
		int bflgn = bnewv < 0;
		ccr_68000_long_move_ae_LZN(bnewv);
		SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
		SET_XFLG(GET_CFLG());
		SET_VFLG((bflgs ^ bflgn) & (bflgo ^ bflgn));
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta + 2, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 2, 0x1, newv, 1);
		return 22 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, newv >> 16); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, newv >> 16, 1);
		return 26 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 26 * CYCLE_UNIT / 2 + count_cycles;
}
/* 26 (4/2) */
/* 4 4,0   */

/* ADDQ.L #<data>,(xxx).W */
uae_u32 REGPARAM2 op_50b8_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	OpcodeFamily = 11;
	CurrentInstrCycles = 24; 
	uae_u32 src = srcreg;
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, dsta, 2, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = get_word_000(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	dst |= get_word_000(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u32)(~dst)) < ((uae_u32)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		uae_s16 bnewv = (uae_s16)dst + (uae_s16)src;
		int bflgs = ((uae_s16)(src)) < 0;
		int bflgo = ((uae_s16)(dst)) < 0;
		int bflgn = bnewv < 0;
		ccr_68000_long_move_ae_LZN(bnewv);
		SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
		SET_XFLG(GET_CFLG());
		SET_VFLG((bflgs ^ bflgn) & (bflgo ^ bflgn));
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta + 2, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 2, 0x1, newv, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, newv >> 16); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, newv >> 16, 1);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 24 * CYCLE_UNIT / 2 + count_cycles;
}
/* 24 (4/2) */
/* 4 0,0   */

/* ADDQ.L #<data>,(xxx).L */
uae_u32 REGPARAM2 op_50b9_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	OpcodeFamily = 11;
	CurrentInstrCycles = 28; 
	uae_u32 src = srcreg;
	uaecptr dsta;
	dsta = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	dsta |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, dsta, 2, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = get_word_000(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	dst |= get_word_000(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u32)(~dst)) < ((uae_u32)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		uae_s16 bnewv = (uae_s16)dst + (uae_s16)src;
		int bflgs = ((uae_s16)(src)) < 0;
		int bflgo = ((uae_s16)(dst)) < 0;
		int bflgn = bnewv < 0;
		ccr_68000_long_move_ae_LZN(bnewv);
		SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
		SET_XFLG(GET_CFLG());
		SET_VFLG((bflgs ^ bflgn) & (bflgo ^ bflgn));
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta + 2, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 2, 0x1, newv, 1);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, newv >> 16); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 0, 0x1, newv >> 16, 1);
		return 28 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 28 * CYCLE_UNIT / 2 + count_cycles;
}
/* 28 (5/2) */
/* 6 0,0   */

/* Scc.B Dn (T) */
uae_u32 REGPARAM2 op_50c0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 4;  
	uae_s8 src = m68k_dreg(regs, srcreg);
	int val = cctrue(0) ? 0xff : 0x00;
	if (!val) {
		m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff);
	}
	opcode |= 0x20000;
	regs.ir = regs.irc;
	if (!val)
	opcode = regs.ir;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if(!val && regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff);
	count_cycles += ((val ? 2 : 0)) * CYCLE_UNIT / 2;
	m68k_incpci(2);
	return 4 * CYCLE_UNIT / 2 + count_cycles;
}
/* 4+ (1/0) */
/* 2 0,0   */

/* DBcc.W Dn,#<data>.W (T) */
uae_u32 REGPARAM2 op_50c8_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 58;
	CurrentInstrCycles = 12; 
	int pcadjust = -2;
	uae_s16 src = m68k_dreg(regs, srcreg);
	uae_s16 offs = regs.irc;
	uaecptr oldpc = m68k_getpci();
	if (!cctrue(0)) {
		m68k_incpci((uae_s32)offs + 2);
		if (offs & 1) {
			exception3_read_prefetch(opcode, m68k_getpci());
			return 2 * CYCLE_UNIT / 2 + count_cycles;
		}
		get_word_000_prefetch(0);
		if(hardware_bus_error) {
			int pcoffset = 0;
			pcoffset = oldpc - m68k_getpci() + 4;
			exception2_fetch_opcode(opcode, 0, pcoffset);
			return 6 * CYCLE_UNIT / 2 + count_cycles;
		}
		if (src) {
			m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
			regs.ir = regs.irc;
			opcode = regs.ir;
			if(regs.t1) opcode |= 0x10000;
			get_word_000_prefetch(2);
			if(hardware_bus_error) {
				int pcoffset = 0;
				exception2_fetch_opcode(opcode, 2, 0);
				return 6 * CYCLE_UNIT / 2 + count_cycles;
			}
			return 10 * CYCLE_UNIT / 2 + count_cycles;
		}
		count_cycles += 2 * CYCLE_UNIT / 2;
		pcadjust = 0;
	}
	m68k_setpci_j(oldpc + 4);
	get_word_000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		pcoffset += pcadjust;
		exception2_fetch_opcode(opcode, 0, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	if(regs.t1) opcode |= 0x10000;
	if (!cctrue(0)) {
		m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
	}
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (2/0) */
/* 4 0,0 B */

/* Scc.B (An) (T) */
uae_u32 REGPARAM2 op_50d0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int val = cctrue(0) ? 0xff : 0x00;
	put_byte_000(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (2/1) */
/* 2 0,0   */

/* Scc.B (An)+ (T) */
uae_u32 REGPARAM2 op_50d8_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int val = cctrue(0) ? 0xff : 0x00;
	put_byte_000(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (2/1) */
/* 2 0,0   */

/* Scc.B -(An) (T) */
uae_u32 REGPARAM2 op_50e0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) = srca;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int val = cctrue(0) ? 0xff : 0x00;
	put_byte_000(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 14 * CYCLE_UNIT / 2 + count_cycles;
}
/* 14 (2/1) */
/* 2 0,0   */

/* Scc.B (d16,An) (T) */
uae_u32 REGPARAM2 op_50e8_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int val = cctrue(0) ? 0xff : 0x00;
	put_byte_000(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 4 0,0   */

/* Scc.B (d8,An,Xn) (T) */
uae_u32 REGPARAM2 op_50f0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	BusCyclePenalty += 2;
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int val = cctrue(0) ? 0xff : 0x00;
	put_byte_000(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (3/1) */
/* 4 4,0   */

/* Scc.B (xxx).W (T) */
uae_u32 REGPARAM2 op_50f8_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 59;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int val = cctrue(0) ? 0xff : 0x00;
	put_byte_000(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 4 0,0   */

/* Scc.B (xxx).L (T) */
uae_u32 REGPARAM2 op_50f9_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 59;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	srca = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	srca |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int val = cctrue(0) ? 0xff : 0x00;
	put_byte_000(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (4/1) */
/* 6 0,0   */

/* SUBQ.B #<data>,Dn */
uae_u32 REGPARAM2 op_5100_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 4;  
	uae_u32 src = srcreg;
	uae_s8 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 4 * CYCLE_UNIT / 2 + count_cycles;
}
/* 4 (1/0) */
/* 2 0,0   */

/* SUBQ.B #<data>,(An) */
uae_u32 REGPARAM2 op_5110_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 12; 
	uae_u32 src = srcreg;
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_byte_000(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, newv, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (2/1) */
/* 2 0,0   */

/* SUBQ.B #<data>,(An)+ */
uae_u32 REGPARAM2 op_5118_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 12; 
	uae_u32 src = srcreg;
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
	uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_byte_000(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, newv, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (2/1) */
/* 2 0,0   */

/* SUBQ.B #<data>,-(An) */
uae_u32 REGPARAM2 op_5120_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 14; 
	uae_u32 src = srcreg;
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, dstreg) = dsta;
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) = dsta;
	uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_byte_000(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, newv, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 14 * CYCLE_UNIT / 2 + count_cycles;
}
/* 14 (2/1) */
/* 2 0,0   */

/* SUBQ.B #<data>,(d16,An) */
uae_u32 REGPARAM2 op_5128_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 16; 
	uae_u32 src = srcreg;
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_byte_000(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, newv, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 4 0,0   */

/* SUBQ.B #<data>,(d8,An,Xn) */
uae_u32 REGPARAM2 op_5130_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 18; 
	uae_u32 src = srcreg;
	uaecptr dsta;
	BusCyclePenalty += 2;
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_byte_000(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, newv, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (3/1) */
/* 4 4,0   */

/* SUBQ.B #<data>,(xxx).W */
uae_u32 REGPARAM2 op_5138_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	OpcodeFamily = 7;
	CurrentInstrCycles = 16; 
	uae_u32 src = srcreg;
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_byte_000(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, newv, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 4 0,0   */

/* SUBQ.B #<data>,(xxx).L */
uae_u32 REGPARAM2 op_5139_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	OpcodeFamily = 7;
	CurrentInstrCycles = 20; 
	uae_u32 src = srcreg;
	uaecptr dsta;
	dsta = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	dsta |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_byte_000(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, newv, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (4/1) */
/* 6 0,0   */

/* SUBQ.W #<data>,Dn */
uae_u32 REGPARAM2 op_5140_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 4;  
	uae_u32 src = srcreg;
	uae_s16 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 4 * CYCLE_UNIT / 2 + count_cycles;
}
/* 4 (1/0) */
/* 2 0,0   */

/* SUBAQ.W #<data>,An */
uae_u32 REGPARAM2 op_5148_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 8;
	CurrentInstrCycles = 8;  
	uae_u32 src = srcreg;
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = dst - src;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		areg_68000_long_replace_low(dstreg, newv);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) = (newv);
	m68k_incpci(2);
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8 (1/0) */
/* 2 0,0   */

/* SUBQ.W #<data>,(An) */
uae_u32 REGPARAM2 op_5150_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 12; 
	uae_u32 src = srcreg;
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	if (dsta & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dsta, 1, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = get_word_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_word_000(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x1, newv, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (2/1) */
/* 2 0,0   */

/* SUBQ.W #<data>,(An)+ */
uae_u32 REGPARAM2 op_5158_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 12; 
	uae_u32 src = srcreg;
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	if (dsta & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dsta, 1, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = get_word_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, dstreg) += 2 + 0;
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) += 2;
	uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_word_000(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x1, newv, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (2/1) */
/* 2 0,0   */

/* SUBQ.W #<data>,-(An) */
uae_u32 REGPARAM2 op_5160_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 14; 
	uae_u32 src = srcreg;
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - 2;
	if (dsta & 1) {
		m68k_incpci(4);
		m68k_areg(regs, dstreg) = dsta;
		exception3_read_access(opcode, dsta, 1, 1);
		return 2 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = get_word_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, dstreg) = dsta;
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) = dsta;
	uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_word_000(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x1, newv, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 14 * CYCLE_UNIT / 2 + count_cycles;
}
/* 14 (2/1) */
/* 2 0,0   */

/* SUBQ.W #<data>,(d16,An) */
uae_u32 REGPARAM2 op_5168_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 16; 
	uae_u32 src = srcreg;
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dsta, 1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = get_word_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_word_000(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x1, newv, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 4 0,0   */

/* SUBQ.W #<data>,(d8,An,Xn) */
uae_u32 REGPARAM2 op_5170_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 18; 
	uae_u32 src = srcreg;
	uaecptr dsta;
	BusCyclePenalty += 2;
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dsta, 1, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = get_word_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_word_000(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x1, newv, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (3/1) */
/* 4 4,0   */

/* SUBQ.W #<data>,(xxx).W */
uae_u32 REGPARAM2 op_5178_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	OpcodeFamily = 7;
	CurrentInstrCycles = 16; 
	uae_u32 src = srcreg;
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, dsta, 1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = get_word_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_word_000(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x1, newv, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 4 0,0   */

/* SUBQ.W #<data>,(xxx).L */
uae_u32 REGPARAM2 op_5179_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	OpcodeFamily = 7;
	CurrentInstrCycles = 20; 
	uae_u32 src = srcreg;
	uaecptr dsta;
	dsta = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	dsta |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, dsta, 1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = get_word_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_word_000(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x1, newv, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (4/1) */
/* 6 0,0   */

/* SUBQ.L #<data>,Dn */
uae_u32 REGPARAM2 op_5180_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 8;  
	uae_u32 src = srcreg;
	uae_s32 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		uae_s16 bnewv = (uae_s16)dst - (uae_s16)src;
		int bflgs = ((uae_s16)(src)) < 0;
		int bflgo = ((uae_s16)(dst)) < 0;
		int bflgn = bnewv < 0;
		ccr_68000_long_move_ae_LZN(bnewv);
		SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
		SET_XFLG(GET_CFLG());
		SET_VFLG((bflgs ^ bflgo) & (bflgn ^ bflgo));
		dreg_68000_long_replace_low(dstreg, bnewv);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	m68k_dreg(regs, dstreg) = (newv);
	m68k_incpci(2);
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8 (1/0) */
/* 2 0,0   */

/* SUBAQ.L #<data>,An */
uae_u32 REGPARAM2 op_5188_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 8;
	CurrentInstrCycles = 8;  
	uae_u32 src = srcreg;
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = dst - src;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		areg_68000_long_replace_low(dstreg, newv);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) = (newv);
	m68k_incpci(2);
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8 (1/0) */
/* 2 0,0   */

/* SUBQ.L #<data>,(An) */
uae_u32 REGPARAM2 op_5190_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 20; 
	uae_u32 src = srcreg;
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	if (dsta & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dsta, 2, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = get_word_000(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	dst |= get_word_000(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		uae_s16 bnewv = (uae_s16)dst - (uae_s16)src;
		int bflgs = ((uae_s16)(src)) < 0;
		int bflgo = ((uae_s16)(dst)) < 0;
		int bflgn = bnewv < 0;
		ccr_68000_long_move_ae_LZN(bnewv);
		SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
		SET_XFLG(GET_CFLG());
		SET_VFLG((bflgs ^ bflgo) & (bflgn ^ bflgo));
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta + 2, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 2, 0x1, newv, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, newv >> 16); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x1, newv >> 16, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (3/2) */
/* 2 0,0   */

/* SUBQ.L #<data>,(An)+ */
uae_u32 REGPARAM2 op_5198_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 20; 
	uae_u32 src = srcreg;
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	if (dsta & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dsta, 2, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = get_word_000(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	dst |= get_word_000(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) += 4;
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		uae_s16 bnewv = (uae_s16)dst - (uae_s16)src;
		int bflgs = ((uae_s16)(src)) < 0;
		int bflgo = ((uae_s16)(dst)) < 0;
		int bflgn = bnewv < 0;
		ccr_68000_long_move_ae_LZN(bnewv);
		SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
		SET_XFLG(GET_CFLG());
		SET_VFLG((bflgs ^ bflgo) & (bflgn ^ bflgo));
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta + 2, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 2, 0x1, newv, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, newv >> 16); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x1, newv >> 16, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (3/2) */
/* 2 0,0   */

/* SUBQ.L #<data>,-(An) */
uae_u32 REGPARAM2 op_51a0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 22; 
	uae_u32 src = srcreg;
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - 4;
	if (dsta & 1) {
		m68k_incpci(2);
		m68k_areg(regs, dstreg) = dsta;
		exception3_read_access(opcode, dsta, 2, 1);
		return 2 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = get_word_000(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, dstreg) = dsta;
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	dst |= get_word_000(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, dstreg) = dsta;
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) = dsta;
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		uae_s16 bnewv = (uae_s16)dst - (uae_s16)src;
		int bflgs = ((uae_s16)(src)) < 0;
		int bflgo = ((uae_s16)(dst)) < 0;
		int bflgn = bnewv < 0;
		ccr_68000_long_move_ae_LZN(bnewv);
		SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
		SET_XFLG(GET_CFLG());
		SET_VFLG((bflgs ^ bflgo) & (bflgn ^ bflgo));
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta + 2, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 2, 0x1, newv, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, newv >> 16); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x1, newv >> 16, 1);
		return 22 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 22 * CYCLE_UNIT / 2 + count_cycles;
}
/* 22 (3/2) */
/* 2 0,0   */

/* SUBQ.L #<data>,(d16,An) */
uae_u32 REGPARAM2 op_51a8_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 24; 
	uae_u32 src = srcreg;
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dsta, 2, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = get_word_000(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	dst |= get_word_000(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		uae_s16 bnewv = (uae_s16)dst - (uae_s16)src;
		int bflgs = ((uae_s16)(src)) < 0;
		int bflgo = ((uae_s16)(dst)) < 0;
		int bflgn = bnewv < 0;
		ccr_68000_long_move_ae_LZN(bnewv);
		SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
		SET_XFLG(GET_CFLG());
		SET_VFLG((bflgs ^ bflgo) & (bflgn ^ bflgo));
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta + 2, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 2, 0x1, newv, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, newv >> 16); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, newv >> 16, 1);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 24 * CYCLE_UNIT / 2 + count_cycles;
}
/* 24 (4/2) */
/* 4 0,0   */

/* SUBQ.L #<data>,(d8,An,Xn) */
uae_u32 REGPARAM2 op_51b0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 26; 
	uae_u32 src = srcreg;
	uaecptr dsta;
	BusCyclePenalty += 2;
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dsta, 2, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = get_word_000(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	dst |= get_word_000(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		uae_s16 bnewv = (uae_s16)dst - (uae_s16)src;
		int bflgs = ((uae_s16)(src)) < 0;
		int bflgo = ((uae_s16)(dst)) < 0;
		int bflgn = bnewv < 0;
		ccr_68000_long_move_ae_LZN(bnewv);
		SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
		SET_XFLG(GET_CFLG());
		SET_VFLG((bflgs ^ bflgo) & (bflgn ^ bflgo));
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta + 2, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 2, 0x1, newv, 1);
		return 22 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, newv >> 16); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, newv >> 16, 1);
		return 26 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 26 * CYCLE_UNIT / 2 + count_cycles;
}
/* 26 (4/2) */
/* 4 4,0   */

/* SUBQ.L #<data>,(xxx).W */
uae_u32 REGPARAM2 op_51b8_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	OpcodeFamily = 7;
	CurrentInstrCycles = 24; 
	uae_u32 src = srcreg;
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, dsta, 2, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = get_word_000(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	dst |= get_word_000(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		uae_s16 bnewv = (uae_s16)dst - (uae_s16)src;
		int bflgs = ((uae_s16)(src)) < 0;
		int bflgo = ((uae_s16)(dst)) < 0;
		int bflgn = bnewv < 0;
		ccr_68000_long_move_ae_LZN(bnewv);
		SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
		SET_XFLG(GET_CFLG());
		SET_VFLG((bflgs ^ bflgo) & (bflgn ^ bflgo));
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta + 2, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 2, 0x1, newv, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, newv >> 16); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, newv >> 16, 1);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 24 * CYCLE_UNIT / 2 + count_cycles;
}
/* 24 (4/2) */
/* 4 0,0   */

/* SUBQ.L #<data>,(xxx).L */
uae_u32 REGPARAM2 op_51b9_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	OpcodeFamily = 7;
	CurrentInstrCycles = 28; 
	uae_u32 src = srcreg;
	uaecptr dsta;
	dsta = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	dsta |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, dsta, 2, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = get_word_000(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	dst |= get_word_000(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		uae_s16 bnewv = (uae_s16)dst - (uae_s16)src;
		int bflgs = ((uae_s16)(src)) < 0;
		int bflgo = ((uae_s16)(dst)) < 0;
		int bflgn = bnewv < 0;
		ccr_68000_long_move_ae_LZN(bnewv);
		SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
		SET_XFLG(GET_CFLG());
		SET_VFLG((bflgs ^ bflgo) & (bflgn ^ bflgo));
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta + 2, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 2, 0x1, newv, 1);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, newv >> 16); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 0, 0x1, newv >> 16, 1);
		return 28 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 28 * CYCLE_UNIT / 2 + count_cycles;
}
/* 28 (5/2) */
/* 6 0,0   */

/* Scc.B Dn (F) */
uae_u32 REGPARAM2 op_51c0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 4;  
	uae_s8 src = m68k_dreg(regs, srcreg);
	int val = cctrue(1) ? 0xff : 0x00;
	if (!val) {
		m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff);
	}
	opcode |= 0x20000;
	regs.ir = regs.irc;
	if (!val)
	opcode = regs.ir;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if(!val && regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff);
	count_cycles += ((val ? 2 : 0)) * CYCLE_UNIT / 2;
	m68k_incpci(2);
	return 4 * CYCLE_UNIT / 2 + count_cycles;
}
/* 4+ (1/0) */
/* 2 0,0   */

/* DBcc.W Dn,#<data>.W (F) */
uae_u32 REGPARAM2 op_51c8_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 58;
	CurrentInstrCycles = 12; 
	int pcadjust = -2;
	uae_s16 src = m68k_dreg(regs, srcreg);
	uae_s16 offs = regs.irc;
	uaecptr oldpc = m68k_getpci();
	if (!cctrue(1)) {
		m68k_incpci((uae_s32)offs + 2);
		if (offs & 1) {
			exception3_read_prefetch(opcode, m68k_getpci());
			return 2 * CYCLE_UNIT / 2 + count_cycles;
		}
		get_word_000_prefetch(0);
		if(hardware_bus_error) {
			int pcoffset = 0;
			pcoffset = oldpc - m68k_getpci() + 4;
			exception2_fetch_opcode(opcode, 0, pcoffset);
			return 6 * CYCLE_UNIT / 2 + count_cycles;
		}
		if (src) {
			m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
			regs.ir = regs.irc;
			opcode = regs.ir;
			if(regs.t1) opcode |= 0x10000;
			get_word_000_prefetch(2);
			if(hardware_bus_error) {
				int pcoffset = 0;
				exception2_fetch_opcode(opcode, 2, 0);
				return 6 * CYCLE_UNIT / 2 + count_cycles;
			}
			return 10 * CYCLE_UNIT / 2 + count_cycles;
		}
		count_cycles += 2 * CYCLE_UNIT / 2;
		pcadjust = 0;
	}
	m68k_setpci_j(oldpc + 4);
	get_word_000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		pcoffset += pcadjust;
		exception2_fetch_opcode(opcode, 0, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	if(regs.t1) opcode |= 0x10000;
	if (!cctrue(1)) {
		m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
	}
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (2/0) */
/* 4 0,0 B */

/* Scc.B (An) (F) */
uae_u32 REGPARAM2 op_51d0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int val = cctrue(1) ? 0xff : 0x00;
	put_byte_000(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (2/1) */
/* 2 0,0   */

/* Scc.B (An)+ (F) */
uae_u32 REGPARAM2 op_51d8_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int val = cctrue(1) ? 0xff : 0x00;
	put_byte_000(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (2/1) */
/* 2 0,0   */

/* Scc.B -(An) (F) */
uae_u32 REGPARAM2 op_51e0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) = srca;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int val = cctrue(1) ? 0xff : 0x00;
	put_byte_000(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 14 * CYCLE_UNIT / 2 + count_cycles;
}
/* 14 (2/1) */
/* 2 0,0   */

/* Scc.B (d16,An) (F) */
uae_u32 REGPARAM2 op_51e8_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int val = cctrue(1) ? 0xff : 0x00;
	put_byte_000(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 4 0,0   */

/* Scc.B (d8,An,Xn) (F) */
uae_u32 REGPARAM2 op_51f0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	BusCyclePenalty += 2;
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int val = cctrue(1) ? 0xff : 0x00;
	put_byte_000(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (3/1) */
/* 4 4,0   */

/* Scc.B (xxx).W (F) */
uae_u32 REGPARAM2 op_51f8_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 59;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int val = cctrue(1) ? 0xff : 0x00;
	put_byte_000(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 4 0,0   */

/* Scc.B (xxx).L (F) */
uae_u32 REGPARAM2 op_51f9_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 59;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	srca = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	srca |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int val = cctrue(1) ? 0xff : 0x00;
	put_byte_000(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (4/1) */
/* 6 0,0   */

/* Scc.B Dn (HI) */
uae_u32 REGPARAM2 op_52c0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 4;  
	uae_s8 src = m68k_dreg(regs, srcreg);
	int val = cctrue(2) ? 0xff : 0x00;
	if (!val) {
		m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff);
	}
	opcode |= 0x20000;
	regs.ir = regs.irc;
	if (!val)
	opcode = regs.ir;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if(!val && regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff);
	count_cycles += ((val ? 2 : 0)) * CYCLE_UNIT / 2;
	m68k_incpci(2);
	return 4 * CYCLE_UNIT / 2 + count_cycles;
}
/* 4+ (1/0) */
/* 2 0,0   */

/* DBcc.W Dn,#<data>.W (HI) */
uae_u32 REGPARAM2 op_52c8_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 58;
	CurrentInstrCycles = 12; 
	int pcadjust = -2;
	uae_s16 src = m68k_dreg(regs, srcreg);
	uae_s16 offs = regs.irc;
	uaecptr oldpc = m68k_getpci();
	if (!cctrue(2)) {
		m68k_incpci((uae_s32)offs + 2);
		if (offs & 1) {
			exception3_read_prefetch(opcode, m68k_getpci());
			return 2 * CYCLE_UNIT / 2 + count_cycles;
		}
		get_word_000_prefetch(0);
		if(hardware_bus_error) {
			int pcoffset = 0;
			pcoffset = oldpc - m68k_getpci() + 4;
			exception2_fetch_opcode(opcode, 0, pcoffset);
			return 6 * CYCLE_UNIT / 2 + count_cycles;
		}
		if (src) {
			m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
			regs.ir = regs.irc;
			opcode = regs.ir;
			if(regs.t1) opcode |= 0x10000;
			get_word_000_prefetch(2);
			if(hardware_bus_error) {
				int pcoffset = 0;
				exception2_fetch_opcode(opcode, 2, 0);
				return 6 * CYCLE_UNIT / 2 + count_cycles;
			}
			return 10 * CYCLE_UNIT / 2 + count_cycles;
		}
		count_cycles += 2 * CYCLE_UNIT / 2;
		pcadjust = 0;
	}
	m68k_setpci_j(oldpc + 4);
	get_word_000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		pcoffset += pcadjust;
		exception2_fetch_opcode(opcode, 0, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	if(regs.t1) opcode |= 0x10000;
	if (!cctrue(2)) {
		m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
	}
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (2/0) */
/* 4 0,0 B */

/* Scc.B (An) (HI) */
uae_u32 REGPARAM2 op_52d0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int val = cctrue(2) ? 0xff : 0x00;
	put_byte_000(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (2/1) */
/* 2 0,0   */

/* Scc.B (An)+ (HI) */
uae_u32 REGPARAM2 op_52d8_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int val = cctrue(2) ? 0xff : 0x00;
	put_byte_000(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (2/1) */
/* 2 0,0   */

/* Scc.B -(An) (HI) */
uae_u32 REGPARAM2 op_52e0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) = srca;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int val = cctrue(2) ? 0xff : 0x00;
	put_byte_000(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 14 * CYCLE_UNIT / 2 + count_cycles;
}
/* 14 (2/1) */
/* 2 0,0   */

/* Scc.B (d16,An) (HI) */
uae_u32 REGPARAM2 op_52e8_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int val = cctrue(2) ? 0xff : 0x00;
	put_byte_000(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 4 0,0   */

/* Scc.B (d8,An,Xn) (HI) */
uae_u32 REGPARAM2 op_52f0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	BusCyclePenalty += 2;
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int val = cctrue(2) ? 0xff : 0x00;
	put_byte_000(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (3/1) */
/* 4 4,0   */

/* Scc.B (xxx).W (HI) */
uae_u32 REGPARAM2 op_52f8_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 59;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int val = cctrue(2) ? 0xff : 0x00;
	put_byte_000(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 4 0,0   */

/* Scc.B (xxx).L (HI) */
uae_u32 REGPARAM2 op_52f9_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 59;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	srca = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	srca |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int val = cctrue(2) ? 0xff : 0x00;
	put_byte_000(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (4/1) */
/* 6 0,0   */

/* Scc.B Dn (LS) */
uae_u32 REGPARAM2 op_53c0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 4;  
	uae_s8 src = m68k_dreg(regs, srcreg);
	int val = cctrue(3) ? 0xff : 0x00;
	if (!val) {
		m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff);
	}
	opcode |= 0x20000;
	regs.ir = regs.irc;
	if (!val)
	opcode = regs.ir;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if(!val && regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff);
	count_cycles += ((val ? 2 : 0)) * CYCLE_UNIT / 2;
	m68k_incpci(2);
	return 4 * CYCLE_UNIT / 2 + count_cycles;
}
/* 4+ (1/0) */
/* 2 0,0   */

/* DBcc.W Dn,#<data>.W (LS) */
uae_u32 REGPARAM2 op_53c8_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 58;
	CurrentInstrCycles = 12; 
	int pcadjust = -2;
	uae_s16 src = m68k_dreg(regs, srcreg);
	uae_s16 offs = regs.irc;
	uaecptr oldpc = m68k_getpci();
	if (!cctrue(3)) {
		m68k_incpci((uae_s32)offs + 2);
		if (offs & 1) {
			exception3_read_prefetch(opcode, m68k_getpci());
			return 2 * CYCLE_UNIT / 2 + count_cycles;
		}
		get_word_000_prefetch(0);
		if(hardware_bus_error) {
			int pcoffset = 0;
			pcoffset = oldpc - m68k_getpci() + 4;
			exception2_fetch_opcode(opcode, 0, pcoffset);
			return 6 * CYCLE_UNIT / 2 + count_cycles;
		}
		if (src) {
			m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
			regs.ir = regs.irc;
			opcode = regs.ir;
			if(regs.t1) opcode |= 0x10000;
			get_word_000_prefetch(2);
			if(hardware_bus_error) {
				int pcoffset = 0;
				exception2_fetch_opcode(opcode, 2, 0);
				return 6 * CYCLE_UNIT / 2 + count_cycles;
			}
			return 10 * CYCLE_UNIT / 2 + count_cycles;
		}
		count_cycles += 2 * CYCLE_UNIT / 2;
		pcadjust = 0;
	}
	m68k_setpci_j(oldpc + 4);
	get_word_000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		pcoffset += pcadjust;
		exception2_fetch_opcode(opcode, 0, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	if(regs.t1) opcode |= 0x10000;
	if (!cctrue(3)) {
		m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
	}
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (2/0) */
/* 4 0,0 B */

/* Scc.B (An) (LS) */
uae_u32 REGPARAM2 op_53d0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int val = cctrue(3) ? 0xff : 0x00;
	put_byte_000(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (2/1) */
/* 2 0,0   */

/* Scc.B (An)+ (LS) */
uae_u32 REGPARAM2 op_53d8_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int val = cctrue(3) ? 0xff : 0x00;
	put_byte_000(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (2/1) */
/* 2 0,0   */

/* Scc.B -(An) (LS) */
uae_u32 REGPARAM2 op_53e0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) = srca;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int val = cctrue(3) ? 0xff : 0x00;
	put_byte_000(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 14 * CYCLE_UNIT / 2 + count_cycles;
}
/* 14 (2/1) */
/* 2 0,0   */

/* Scc.B (d16,An) (LS) */
uae_u32 REGPARAM2 op_53e8_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int val = cctrue(3) ? 0xff : 0x00;
	put_byte_000(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 4 0,0   */

/* Scc.B (d8,An,Xn) (LS) */
uae_u32 REGPARAM2 op_53f0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	BusCyclePenalty += 2;
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int val = cctrue(3) ? 0xff : 0x00;
	put_byte_000(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (3/1) */
/* 4 4,0   */

/* Scc.B (xxx).W (LS) */
uae_u32 REGPARAM2 op_53f8_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 59;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int val = cctrue(3) ? 0xff : 0x00;
	put_byte_000(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 4 0,0   */

/* Scc.B (xxx).L (LS) */
uae_u32 REGPARAM2 op_53f9_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 59;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	srca = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	srca |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int val = cctrue(3) ? 0xff : 0x00;
	put_byte_000(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (4/1) */
/* 6 0,0   */

/* Scc.B Dn (CC) */
uae_u32 REGPARAM2 op_54c0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 4;  
	uae_s8 src = m68k_dreg(regs, srcreg);
	int val = cctrue(4) ? 0xff : 0x00;
	if (!val) {
		m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff);
	}
	opcode |= 0x20000;
	regs.ir = regs.irc;
	if (!val)
	opcode = regs.ir;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if(!val && regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff);
	count_cycles += ((val ? 2 : 0)) * CYCLE_UNIT / 2;
	m68k_incpci(2);
	return 4 * CYCLE_UNIT / 2 + count_cycles;
}
/* 4+ (1/0) */
/* 2 0,0   */

/* DBcc.W Dn,#<data>.W (CC) */
uae_u32 REGPARAM2 op_54c8_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 58;
	CurrentInstrCycles = 12; 
	int pcadjust = -2;
	uae_s16 src = m68k_dreg(regs, srcreg);
	uae_s16 offs = regs.irc;
	uaecptr oldpc = m68k_getpci();
	if (!cctrue(4)) {
		m68k_incpci((uae_s32)offs + 2);
		if (offs & 1) {
			exception3_read_prefetch(opcode, m68k_getpci());
			return 2 * CYCLE_UNIT / 2 + count_cycles;
		}
		get_word_000_prefetch(0);
		if(hardware_bus_error) {
			int pcoffset = 0;
			pcoffset = oldpc - m68k_getpci() + 4;
			exception2_fetch_opcode(opcode, 0, pcoffset);
			return 6 * CYCLE_UNIT / 2 + count_cycles;
		}
		if (src) {
			m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
			regs.ir = regs.irc;
			opcode = regs.ir;
			if(regs.t1) opcode |= 0x10000;
			get_word_000_prefetch(2);
			if(hardware_bus_error) {
				int pcoffset = 0;
				exception2_fetch_opcode(opcode, 2, 0);
				return 6 * CYCLE_UNIT / 2 + count_cycles;
			}
			return 10 * CYCLE_UNIT / 2 + count_cycles;
		}
		count_cycles += 2 * CYCLE_UNIT / 2;
		pcadjust = 0;
	}
	m68k_setpci_j(oldpc + 4);
	get_word_000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		pcoffset += pcadjust;
		exception2_fetch_opcode(opcode, 0, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	if(regs.t1) opcode |= 0x10000;
	if (!cctrue(4)) {
		m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
	}
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (2/0) */
/* 4 0,0 B */

/* Scc.B (An) (CC) */
uae_u32 REGPARAM2 op_54d0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int val = cctrue(4) ? 0xff : 0x00;
	put_byte_000(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (2/1) */
/* 2 0,0   */

/* Scc.B (An)+ (CC) */
uae_u32 REGPARAM2 op_54d8_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int val = cctrue(4) ? 0xff : 0x00;
	put_byte_000(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (2/1) */
/* 2 0,0   */

/* Scc.B -(An) (CC) */
uae_u32 REGPARAM2 op_54e0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) = srca;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int val = cctrue(4) ? 0xff : 0x00;
	put_byte_000(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 14 * CYCLE_UNIT / 2 + count_cycles;
}
/* 14 (2/1) */
/* 2 0,0   */

/* Scc.B (d16,An) (CC) */
uae_u32 REGPARAM2 op_54e8_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int val = cctrue(4) ? 0xff : 0x00;
	put_byte_000(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 4 0,0   */

/* Scc.B (d8,An,Xn) (CC) */
uae_u32 REGPARAM2 op_54f0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	BusCyclePenalty += 2;
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int val = cctrue(4) ? 0xff : 0x00;
	put_byte_000(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (3/1) */
/* 4 4,0   */

/* Scc.B (xxx).W (CC) */
uae_u32 REGPARAM2 op_54f8_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 59;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int val = cctrue(4) ? 0xff : 0x00;
	put_byte_000(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 4 0,0   */

/* Scc.B (xxx).L (CC) */
uae_u32 REGPARAM2 op_54f9_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 59;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	srca = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	srca |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int val = cctrue(4) ? 0xff : 0x00;
	put_byte_000(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (4/1) */
/* 6 0,0   */

/* Scc.B Dn (CS) */
uae_u32 REGPARAM2 op_55c0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 4;  
	uae_s8 src = m68k_dreg(regs, srcreg);
	int val = cctrue(5) ? 0xff : 0x00;
	if (!val) {
		m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff);
	}
	opcode |= 0x20000;
	regs.ir = regs.irc;
	if (!val)
	opcode = regs.ir;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if(!val && regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff);
	count_cycles += ((val ? 2 : 0)) * CYCLE_UNIT / 2;
	m68k_incpci(2);
	return 4 * CYCLE_UNIT / 2 + count_cycles;
}
/* 4+ (1/0) */
/* 2 0,0   */

/* DBcc.W Dn,#<data>.W (CS) */
uae_u32 REGPARAM2 op_55c8_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 58;
	CurrentInstrCycles = 12; 
	int pcadjust = -2;
	uae_s16 src = m68k_dreg(regs, srcreg);
	uae_s16 offs = regs.irc;
	uaecptr oldpc = m68k_getpci();
	if (!cctrue(5)) {
		m68k_incpci((uae_s32)offs + 2);
		if (offs & 1) {
			exception3_read_prefetch(opcode, m68k_getpci());
			return 2 * CYCLE_UNIT / 2 + count_cycles;
		}
		get_word_000_prefetch(0);
		if(hardware_bus_error) {
			int pcoffset = 0;
			pcoffset = oldpc - m68k_getpci() + 4;
			exception2_fetch_opcode(opcode, 0, pcoffset);
			return 6 * CYCLE_UNIT / 2 + count_cycles;
		}
		if (src) {
			m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
			regs.ir = regs.irc;
			opcode = regs.ir;
			if(regs.t1) opcode |= 0x10000;
			get_word_000_prefetch(2);
			if(hardware_bus_error) {
				int pcoffset = 0;
				exception2_fetch_opcode(opcode, 2, 0);
				return 6 * CYCLE_UNIT / 2 + count_cycles;
			}
			return 10 * CYCLE_UNIT / 2 + count_cycles;
		}
		count_cycles += 2 * CYCLE_UNIT / 2;
		pcadjust = 0;
	}
	m68k_setpci_j(oldpc + 4);
	get_word_000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		pcoffset += pcadjust;
		exception2_fetch_opcode(opcode, 0, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	if(regs.t1) opcode |= 0x10000;
	if (!cctrue(5)) {
		m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
	}
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (2/0) */
/* 4 0,0 B */

/* Scc.B (An) (CS) */
uae_u32 REGPARAM2 op_55d0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int val = cctrue(5) ? 0xff : 0x00;
	put_byte_000(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (2/1) */
/* 2 0,0   */

/* Scc.B (An)+ (CS) */
uae_u32 REGPARAM2 op_55d8_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int val = cctrue(5) ? 0xff : 0x00;
	put_byte_000(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (2/1) */
/* 2 0,0   */

/* Scc.B -(An) (CS) */
uae_u32 REGPARAM2 op_55e0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) = srca;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int val = cctrue(5) ? 0xff : 0x00;
	put_byte_000(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 14 * CYCLE_UNIT / 2 + count_cycles;
}
/* 14 (2/1) */
/* 2 0,0   */

/* Scc.B (d16,An) (CS) */
uae_u32 REGPARAM2 op_55e8_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int val = cctrue(5) ? 0xff : 0x00;
	put_byte_000(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 4 0,0   */

/* Scc.B (d8,An,Xn) (CS) */
uae_u32 REGPARAM2 op_55f0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	BusCyclePenalty += 2;
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int val = cctrue(5) ? 0xff : 0x00;
	put_byte_000(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (3/1) */
/* 4 4,0   */

/* Scc.B (xxx).W (CS) */
uae_u32 REGPARAM2 op_55f8_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 59;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int val = cctrue(5) ? 0xff : 0x00;
	put_byte_000(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 4 0,0   */

/* Scc.B (xxx).L (CS) */
uae_u32 REGPARAM2 op_55f9_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 59;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	srca = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	srca |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int val = cctrue(5) ? 0xff : 0x00;
	put_byte_000(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (4/1) */
/* 6 0,0   */

/* Scc.B Dn (NE) */
uae_u32 REGPARAM2 op_56c0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 4;  
	uae_s8 src = m68k_dreg(regs, srcreg);
	int val = cctrue(6) ? 0xff : 0x00;
	if (!val) {
		m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff);
	}
	opcode |= 0x20000;
	regs.ir = regs.irc;
	if (!val)
	opcode = regs.ir;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if(!val && regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff);
	count_cycles += ((val ? 2 : 0)) * CYCLE_UNIT / 2;
	m68k_incpci(2);
	return 4 * CYCLE_UNIT / 2 + count_cycles;
}
/* 4+ (1/0) */
/* 2 0,0   */

/* DBcc.W Dn,#<data>.W (NE) */
uae_u32 REGPARAM2 op_56c8_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 58;
	CurrentInstrCycles = 12; 
	int pcadjust = -2;
	uae_s16 src = m68k_dreg(regs, srcreg);
	uae_s16 offs = regs.irc;
	uaecptr oldpc = m68k_getpci();
	if (!cctrue(6)) {
		m68k_incpci((uae_s32)offs + 2);
		if (offs & 1) {
			exception3_read_prefetch(opcode, m68k_getpci());
			return 2 * CYCLE_UNIT / 2 + count_cycles;
		}
		get_word_000_prefetch(0);
		if(hardware_bus_error) {
			int pcoffset = 0;
			pcoffset = oldpc - m68k_getpci() + 4;
			exception2_fetch_opcode(opcode, 0, pcoffset);
			return 6 * CYCLE_UNIT / 2 + count_cycles;
		}
		if (src) {
			m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
			regs.ir = regs.irc;
			opcode = regs.ir;
			if(regs.t1) opcode |= 0x10000;
			get_word_000_prefetch(2);
			if(hardware_bus_error) {
				int pcoffset = 0;
				exception2_fetch_opcode(opcode, 2, 0);
				return 6 * CYCLE_UNIT / 2 + count_cycles;
			}
			return 10 * CYCLE_UNIT / 2 + count_cycles;
		}
		count_cycles += 2 * CYCLE_UNIT / 2;
		pcadjust = 0;
	}
	m68k_setpci_j(oldpc + 4);
	get_word_000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		pcoffset += pcadjust;
		exception2_fetch_opcode(opcode, 0, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	if(regs.t1) opcode |= 0x10000;
	if (!cctrue(6)) {
		m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
	}
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (2/0) */
/* 4 0,0 B */

/* Scc.B (An) (NE) */
uae_u32 REGPARAM2 op_56d0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int val = cctrue(6) ? 0xff : 0x00;
	put_byte_000(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (2/1) */
/* 2 0,0   */

/* Scc.B (An)+ (NE) */
uae_u32 REGPARAM2 op_56d8_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int val = cctrue(6) ? 0xff : 0x00;
	put_byte_000(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (2/1) */
/* 2 0,0   */

/* Scc.B -(An) (NE) */
uae_u32 REGPARAM2 op_56e0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) = srca;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int val = cctrue(6) ? 0xff : 0x00;
	put_byte_000(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 14 * CYCLE_UNIT / 2 + count_cycles;
}
/* 14 (2/1) */
/* 2 0,0   */

/* Scc.B (d16,An) (NE) */
uae_u32 REGPARAM2 op_56e8_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int val = cctrue(6) ? 0xff : 0x00;
	put_byte_000(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 4 0,0   */

/* Scc.B (d8,An,Xn) (NE) */
uae_u32 REGPARAM2 op_56f0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	BusCyclePenalty += 2;
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int val = cctrue(6) ? 0xff : 0x00;
	put_byte_000(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (3/1) */
/* 4 4,0   */

/* Scc.B (xxx).W (NE) */
uae_u32 REGPARAM2 op_56f8_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 59;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int val = cctrue(6) ? 0xff : 0x00;
	put_byte_000(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 4 0,0   */

/* Scc.B (xxx).L (NE) */
uae_u32 REGPARAM2 op_56f9_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 59;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	srca = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	srca |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int val = cctrue(6) ? 0xff : 0x00;
	put_byte_000(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (4/1) */
/* 6 0,0   */

/* Scc.B Dn (EQ) */
uae_u32 REGPARAM2 op_57c0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 4;  
	uae_s8 src = m68k_dreg(regs, srcreg);
	int val = cctrue(7) ? 0xff : 0x00;
	if (!val) {
		m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff);
	}
	opcode |= 0x20000;
	regs.ir = regs.irc;
	if (!val)
	opcode = regs.ir;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if(!val && regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff);
	count_cycles += ((val ? 2 : 0)) * CYCLE_UNIT / 2;
	m68k_incpci(2);
	return 4 * CYCLE_UNIT / 2 + count_cycles;
}
/* 4+ (1/0) */
/* 2 0,0   */

/* DBcc.W Dn,#<data>.W (EQ) */
uae_u32 REGPARAM2 op_57c8_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 58;
	CurrentInstrCycles = 12; 
	int pcadjust = -2;
	uae_s16 src = m68k_dreg(regs, srcreg);
	uae_s16 offs = regs.irc;
	uaecptr oldpc = m68k_getpci();
	if (!cctrue(7)) {
		m68k_incpci((uae_s32)offs + 2);
		if (offs & 1) {
			exception3_read_prefetch(opcode, m68k_getpci());
			return 2 * CYCLE_UNIT / 2 + count_cycles;
		}
		get_word_000_prefetch(0);
		if(hardware_bus_error) {
			int pcoffset = 0;
			pcoffset = oldpc - m68k_getpci() + 4;
			exception2_fetch_opcode(opcode, 0, pcoffset);
			return 6 * CYCLE_UNIT / 2 + count_cycles;
		}
		if (src) {
			m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
			regs.ir = regs.irc;
			opcode = regs.ir;
			if(regs.t1) opcode |= 0x10000;
			get_word_000_prefetch(2);
			if(hardware_bus_error) {
				int pcoffset = 0;
				exception2_fetch_opcode(opcode, 2, 0);
				return 6 * CYCLE_UNIT / 2 + count_cycles;
			}
			return 10 * CYCLE_UNIT / 2 + count_cycles;
		}
		count_cycles += 2 * CYCLE_UNIT / 2;
		pcadjust = 0;
	}
	m68k_setpci_j(oldpc + 4);
	get_word_000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		pcoffset += pcadjust;
		exception2_fetch_opcode(opcode, 0, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	if(regs.t1) opcode |= 0x10000;
	if (!cctrue(7)) {
		m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
	}
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (2/0) */
/* 4 0,0 B */

/* Scc.B (An) (EQ) */
uae_u32 REGPARAM2 op_57d0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int val = cctrue(7) ? 0xff : 0x00;
	put_byte_000(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (2/1) */
/* 2 0,0   */

/* Scc.B (An)+ (EQ) */
uae_u32 REGPARAM2 op_57d8_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int val = cctrue(7) ? 0xff : 0x00;
	put_byte_000(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (2/1) */
/* 2 0,0   */

/* Scc.B -(An) (EQ) */
uae_u32 REGPARAM2 op_57e0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) = srca;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int val = cctrue(7) ? 0xff : 0x00;
	put_byte_000(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 14 * CYCLE_UNIT / 2 + count_cycles;
}
/* 14 (2/1) */
/* 2 0,0   */

/* Scc.B (d16,An) (EQ) */
uae_u32 REGPARAM2 op_57e8_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int val = cctrue(7) ? 0xff : 0x00;
	put_byte_000(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 4 0,0   */

/* Scc.B (d8,An,Xn) (EQ) */
uae_u32 REGPARAM2 op_57f0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	BusCyclePenalty += 2;
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int val = cctrue(7) ? 0xff : 0x00;
	put_byte_000(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (3/1) */
/* 4 4,0   */

/* Scc.B (xxx).W (EQ) */
uae_u32 REGPARAM2 op_57f8_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 59;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int val = cctrue(7) ? 0xff : 0x00;
	put_byte_000(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 4 0,0   */

/* Scc.B (xxx).L (EQ) */
uae_u32 REGPARAM2 op_57f9_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 59;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	srca = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	srca |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int val = cctrue(7) ? 0xff : 0x00;
	put_byte_000(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (4/1) */
/* 6 0,0   */

/* Scc.B Dn (VC) */
uae_u32 REGPARAM2 op_58c0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 4;  
	uae_s8 src = m68k_dreg(regs, srcreg);
	int val = cctrue(8) ? 0xff : 0x00;
	if (!val) {
		m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff);
	}
	opcode |= 0x20000;
	regs.ir = regs.irc;
	if (!val)
	opcode = regs.ir;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if(!val && regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff);
	count_cycles += ((val ? 2 : 0)) * CYCLE_UNIT / 2;
	m68k_incpci(2);
	return 4 * CYCLE_UNIT / 2 + count_cycles;
}
/* 4+ (1/0) */
/* 2 0,0   */

/* DBcc.W Dn,#<data>.W (VC) */
uae_u32 REGPARAM2 op_58c8_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 58;
	CurrentInstrCycles = 12; 
	int pcadjust = -2;
	uae_s16 src = m68k_dreg(regs, srcreg);
	uae_s16 offs = regs.irc;
	uaecptr oldpc = m68k_getpci();
	if (!cctrue(8)) {
		m68k_incpci((uae_s32)offs + 2);
		if (offs & 1) {
			exception3_read_prefetch(opcode, m68k_getpci());
			return 2 * CYCLE_UNIT / 2 + count_cycles;
		}
		get_word_000_prefetch(0);
		if(hardware_bus_error) {
			int pcoffset = 0;
			pcoffset = oldpc - m68k_getpci() + 4;
			exception2_fetch_opcode(opcode, 0, pcoffset);
			return 6 * CYCLE_UNIT / 2 + count_cycles;
		}
		if (src) {
			m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
			regs.ir = regs.irc;
			opcode = regs.ir;
			if(regs.t1) opcode |= 0x10000;
			get_word_000_prefetch(2);
			if(hardware_bus_error) {
				int pcoffset = 0;
				exception2_fetch_opcode(opcode, 2, 0);
				return 6 * CYCLE_UNIT / 2 + count_cycles;
			}
			return 10 * CYCLE_UNIT / 2 + count_cycles;
		}
		count_cycles += 2 * CYCLE_UNIT / 2;
		pcadjust = 0;
	}
	m68k_setpci_j(oldpc + 4);
	get_word_000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		pcoffset += pcadjust;
		exception2_fetch_opcode(opcode, 0, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	if(regs.t1) opcode |= 0x10000;
	if (!cctrue(8)) {
		m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
	}
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (2/0) */
/* 4 0,0 B */

/* Scc.B (An) (VC) */
uae_u32 REGPARAM2 op_58d0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int val = cctrue(8) ? 0xff : 0x00;
	put_byte_000(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (2/1) */
/* 2 0,0   */

/* Scc.B (An)+ (VC) */
uae_u32 REGPARAM2 op_58d8_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int val = cctrue(8) ? 0xff : 0x00;
	put_byte_000(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (2/1) */
/* 2 0,0   */

/* Scc.B -(An) (VC) */
uae_u32 REGPARAM2 op_58e0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) = srca;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int val = cctrue(8) ? 0xff : 0x00;
	put_byte_000(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 14 * CYCLE_UNIT / 2 + count_cycles;
}
/* 14 (2/1) */
/* 2 0,0   */

/* Scc.B (d16,An) (VC) */
uae_u32 REGPARAM2 op_58e8_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int val = cctrue(8) ? 0xff : 0x00;
	put_byte_000(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 4 0,0   */

/* Scc.B (d8,An,Xn) (VC) */
uae_u32 REGPARAM2 op_58f0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	BusCyclePenalty += 2;
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int val = cctrue(8) ? 0xff : 0x00;
	put_byte_000(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (3/1) */
/* 4 4,0   */

/* Scc.B (xxx).W (VC) */
uae_u32 REGPARAM2 op_58f8_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 59;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int val = cctrue(8) ? 0xff : 0x00;
	put_byte_000(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 4 0,0   */

/* Scc.B (xxx).L (VC) */
uae_u32 REGPARAM2 op_58f9_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 59;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	srca = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	srca |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int val = cctrue(8) ? 0xff : 0x00;
	put_byte_000(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (4/1) */
/* 6 0,0   */

/* Scc.B Dn (VS) */
uae_u32 REGPARAM2 op_59c0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 4;  
	uae_s8 src = m68k_dreg(regs, srcreg);
	int val = cctrue(9) ? 0xff : 0x00;
	if (!val) {
		m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff);
	}
	opcode |= 0x20000;
	regs.ir = regs.irc;
	if (!val)
	opcode = regs.ir;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if(!val && regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff);
	count_cycles += ((val ? 2 : 0)) * CYCLE_UNIT / 2;
	m68k_incpci(2);
	return 4 * CYCLE_UNIT / 2 + count_cycles;
}
/* 4+ (1/0) */
/* 2 0,0   */

/* DBcc.W Dn,#<data>.W (VS) */
uae_u32 REGPARAM2 op_59c8_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 58;
	CurrentInstrCycles = 12; 
	int pcadjust = -2;
	uae_s16 src = m68k_dreg(regs, srcreg);
	uae_s16 offs = regs.irc;
	uaecptr oldpc = m68k_getpci();
	if (!cctrue(9)) {
		m68k_incpci((uae_s32)offs + 2);
		if (offs & 1) {
			exception3_read_prefetch(opcode, m68k_getpci());
			return 2 * CYCLE_UNIT / 2 + count_cycles;
		}
		get_word_000_prefetch(0);
		if(hardware_bus_error) {
			int pcoffset = 0;
			pcoffset = oldpc - m68k_getpci() + 4;
			exception2_fetch_opcode(opcode, 0, pcoffset);
			return 6 * CYCLE_UNIT / 2 + count_cycles;
		}
		if (src) {
			m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
			regs.ir = regs.irc;
			opcode = regs.ir;
			if(regs.t1) opcode |= 0x10000;
			get_word_000_prefetch(2);
			if(hardware_bus_error) {
				int pcoffset = 0;
				exception2_fetch_opcode(opcode, 2, 0);
				return 6 * CYCLE_UNIT / 2 + count_cycles;
			}
			return 10 * CYCLE_UNIT / 2 + count_cycles;
		}
		count_cycles += 2 * CYCLE_UNIT / 2;
		pcadjust = 0;
	}
	m68k_setpci_j(oldpc + 4);
	get_word_000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		pcoffset += pcadjust;
		exception2_fetch_opcode(opcode, 0, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	if(regs.t1) opcode |= 0x10000;
	if (!cctrue(9)) {
		m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
	}
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (2/0) */
/* 4 0,0 B */

/* Scc.B (An) (VS) */
uae_u32 REGPARAM2 op_59d0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int val = cctrue(9) ? 0xff : 0x00;
	put_byte_000(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (2/1) */
/* 2 0,0   */

/* Scc.B (An)+ (VS) */
uae_u32 REGPARAM2 op_59d8_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int val = cctrue(9) ? 0xff : 0x00;
	put_byte_000(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (2/1) */
/* 2 0,0   */

/* Scc.B -(An) (VS) */
uae_u32 REGPARAM2 op_59e0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) = srca;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int val = cctrue(9) ? 0xff : 0x00;
	put_byte_000(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 14 * CYCLE_UNIT / 2 + count_cycles;
}
/* 14 (2/1) */
/* 2 0,0   */

/* Scc.B (d16,An) (VS) */
uae_u32 REGPARAM2 op_59e8_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int val = cctrue(9) ? 0xff : 0x00;
	put_byte_000(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 4 0,0   */

/* Scc.B (d8,An,Xn) (VS) */
uae_u32 REGPARAM2 op_59f0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	BusCyclePenalty += 2;
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int val = cctrue(9) ? 0xff : 0x00;
	put_byte_000(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (3/1) */
/* 4 4,0   */

/* Scc.B (xxx).W (VS) */
uae_u32 REGPARAM2 op_59f8_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 59;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int val = cctrue(9) ? 0xff : 0x00;
	put_byte_000(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 4 0,0   */

/* Scc.B (xxx).L (VS) */
uae_u32 REGPARAM2 op_59f9_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 59;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	srca = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	srca |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int val = cctrue(9) ? 0xff : 0x00;
	put_byte_000(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (4/1) */
/* 6 0,0   */

/* Scc.B Dn (PL) */
uae_u32 REGPARAM2 op_5ac0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 4;  
	uae_s8 src = m68k_dreg(regs, srcreg);
	int val = cctrue(10) ? 0xff : 0x00;
	if (!val) {
		m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff);
	}
	opcode |= 0x20000;
	regs.ir = regs.irc;
	if (!val)
	opcode = regs.ir;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if(!val && regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff);
	count_cycles += ((val ? 2 : 0)) * CYCLE_UNIT / 2;
	m68k_incpci(2);
	return 4 * CYCLE_UNIT / 2 + count_cycles;
}
/* 4+ (1/0) */
/* 2 0,0   */

/* DBcc.W Dn,#<data>.W (PL) */
uae_u32 REGPARAM2 op_5ac8_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 58;
	CurrentInstrCycles = 12; 
	int pcadjust = -2;
	uae_s16 src = m68k_dreg(regs, srcreg);
	uae_s16 offs = regs.irc;
	uaecptr oldpc = m68k_getpci();
	if (!cctrue(10)) {
		m68k_incpci((uae_s32)offs + 2);
		if (offs & 1) {
			exception3_read_prefetch(opcode, m68k_getpci());
			return 2 * CYCLE_UNIT / 2 + count_cycles;
		}
		get_word_000_prefetch(0);
		if(hardware_bus_error) {
			int pcoffset = 0;
			pcoffset = oldpc - m68k_getpci() + 4;
			exception2_fetch_opcode(opcode, 0, pcoffset);
			return 6 * CYCLE_UNIT / 2 + count_cycles;
		}
		if (src) {
			m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
			regs.ir = regs.irc;
			opcode = regs.ir;
			if(regs.t1) opcode |= 0x10000;
			get_word_000_prefetch(2);
			if(hardware_bus_error) {
				int pcoffset = 0;
				exception2_fetch_opcode(opcode, 2, 0);
				return 6 * CYCLE_UNIT / 2 + count_cycles;
			}
			return 10 * CYCLE_UNIT / 2 + count_cycles;
		}
		count_cycles += 2 * CYCLE_UNIT / 2;
		pcadjust = 0;
	}
	m68k_setpci_j(oldpc + 4);
	get_word_000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		pcoffset += pcadjust;
		exception2_fetch_opcode(opcode, 0, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	if(regs.t1) opcode |= 0x10000;
	if (!cctrue(10)) {
		m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
	}
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (2/0) */
/* 4 0,0 B */

/* Scc.B (An) (PL) */
uae_u32 REGPARAM2 op_5ad0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int val = cctrue(10) ? 0xff : 0x00;
	put_byte_000(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (2/1) */
/* 2 0,0   */

/* Scc.B (An)+ (PL) */
uae_u32 REGPARAM2 op_5ad8_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int val = cctrue(10) ? 0xff : 0x00;
	put_byte_000(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (2/1) */
/* 2 0,0   */

/* Scc.B -(An) (PL) */
uae_u32 REGPARAM2 op_5ae0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) = srca;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int val = cctrue(10) ? 0xff : 0x00;
	put_byte_000(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 14 * CYCLE_UNIT / 2 + count_cycles;
}
/* 14 (2/1) */
/* 2 0,0   */

/* Scc.B (d16,An) (PL) */
uae_u32 REGPARAM2 op_5ae8_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int val = cctrue(10) ? 0xff : 0x00;
	put_byte_000(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 4 0,0   */

/* Scc.B (d8,An,Xn) (PL) */
uae_u32 REGPARAM2 op_5af0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	BusCyclePenalty += 2;
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int val = cctrue(10) ? 0xff : 0x00;
	put_byte_000(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (3/1) */
/* 4 4,0   */

/* Scc.B (xxx).W (PL) */
uae_u32 REGPARAM2 op_5af8_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 59;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int val = cctrue(10) ? 0xff : 0x00;
	put_byte_000(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 4 0,0   */

/* Scc.B (xxx).L (PL) */
uae_u32 REGPARAM2 op_5af9_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 59;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	srca = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	srca |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int val = cctrue(10) ? 0xff : 0x00;
	put_byte_000(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (4/1) */
/* 6 0,0   */

/* Scc.B Dn (MI) */
uae_u32 REGPARAM2 op_5bc0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 4;  
	uae_s8 src = m68k_dreg(regs, srcreg);
	int val = cctrue(11) ? 0xff : 0x00;
	if (!val) {
		m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff);
	}
	opcode |= 0x20000;
	regs.ir = regs.irc;
	if (!val)
	opcode = regs.ir;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if(!val && regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff);
	count_cycles += ((val ? 2 : 0)) * CYCLE_UNIT / 2;
	m68k_incpci(2);
	return 4 * CYCLE_UNIT / 2 + count_cycles;
}
/* 4+ (1/0) */
/* 2 0,0   */

/* DBcc.W Dn,#<data>.W (MI) */
uae_u32 REGPARAM2 op_5bc8_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 58;
	CurrentInstrCycles = 12; 
	int pcadjust = -2;
	uae_s16 src = m68k_dreg(regs, srcreg);
	uae_s16 offs = regs.irc;
	uaecptr oldpc = m68k_getpci();
	if (!cctrue(11)) {
		m68k_incpci((uae_s32)offs + 2);
		if (offs & 1) {
			exception3_read_prefetch(opcode, m68k_getpci());
			return 2 * CYCLE_UNIT / 2 + count_cycles;
		}
		get_word_000_prefetch(0);
		if(hardware_bus_error) {
			int pcoffset = 0;
			pcoffset = oldpc - m68k_getpci() + 4;
			exception2_fetch_opcode(opcode, 0, pcoffset);
			return 6 * CYCLE_UNIT / 2 + count_cycles;
		}
		if (src) {
			m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
			regs.ir = regs.irc;
			opcode = regs.ir;
			if(regs.t1) opcode |= 0x10000;
			get_word_000_prefetch(2);
			if(hardware_bus_error) {
				int pcoffset = 0;
				exception2_fetch_opcode(opcode, 2, 0);
				return 6 * CYCLE_UNIT / 2 + count_cycles;
			}
			return 10 * CYCLE_UNIT / 2 + count_cycles;
		}
		count_cycles += 2 * CYCLE_UNIT / 2;
		pcadjust = 0;
	}
	m68k_setpci_j(oldpc + 4);
	get_word_000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		pcoffset += pcadjust;
		exception2_fetch_opcode(opcode, 0, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	if(regs.t1) opcode |= 0x10000;
	if (!cctrue(11)) {
		m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
	}
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (2/0) */
/* 4 0,0 B */

/* Scc.B (An) (MI) */
uae_u32 REGPARAM2 op_5bd0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int val = cctrue(11) ? 0xff : 0x00;
	put_byte_000(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (2/1) */
/* 2 0,0   */

/* Scc.B (An)+ (MI) */
uae_u32 REGPARAM2 op_5bd8_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int val = cctrue(11) ? 0xff : 0x00;
	put_byte_000(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (2/1) */
/* 2 0,0   */

/* Scc.B -(An) (MI) */
uae_u32 REGPARAM2 op_5be0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) = srca;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int val = cctrue(11) ? 0xff : 0x00;
	put_byte_000(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 14 * CYCLE_UNIT / 2 + count_cycles;
}
/* 14 (2/1) */
/* 2 0,0   */

/* Scc.B (d16,An) (MI) */
uae_u32 REGPARAM2 op_5be8_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int val = cctrue(11) ? 0xff : 0x00;
	put_byte_000(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 4 0,0   */

/* Scc.B (d8,An,Xn) (MI) */
uae_u32 REGPARAM2 op_5bf0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	BusCyclePenalty += 2;
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int val = cctrue(11) ? 0xff : 0x00;
	put_byte_000(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (3/1) */
/* 4 4,0   */

/* Scc.B (xxx).W (MI) */
uae_u32 REGPARAM2 op_5bf8_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 59;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int val = cctrue(11) ? 0xff : 0x00;
	put_byte_000(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 4 0,0   */

/* Scc.B (xxx).L (MI) */
uae_u32 REGPARAM2 op_5bf9_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 59;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	srca = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	srca |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int val = cctrue(11) ? 0xff : 0x00;
	put_byte_000(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (4/1) */
/* 6 0,0   */

/* Scc.B Dn (GE) */
uae_u32 REGPARAM2 op_5cc0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 4;  
	uae_s8 src = m68k_dreg(regs, srcreg);
	int val = cctrue(12) ? 0xff : 0x00;
	if (!val) {
		m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff);
	}
	opcode |= 0x20000;
	regs.ir = regs.irc;
	if (!val)
	opcode = regs.ir;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if(!val && regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff);
	count_cycles += ((val ? 2 : 0)) * CYCLE_UNIT / 2;
	m68k_incpci(2);
	return 4 * CYCLE_UNIT / 2 + count_cycles;
}
/* 4+ (1/0) */
/* 2 0,0   */

/* DBcc.W Dn,#<data>.W (GE) */
uae_u32 REGPARAM2 op_5cc8_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 58;
	CurrentInstrCycles = 12; 
	int pcadjust = -2;
	uae_s16 src = m68k_dreg(regs, srcreg);
	uae_s16 offs = regs.irc;
	uaecptr oldpc = m68k_getpci();
	if (!cctrue(12)) {
		m68k_incpci((uae_s32)offs + 2);
		if (offs & 1) {
			exception3_read_prefetch(opcode, m68k_getpci());
			return 2 * CYCLE_UNIT / 2 + count_cycles;
		}
		get_word_000_prefetch(0);
		if(hardware_bus_error) {
			int pcoffset = 0;
			pcoffset = oldpc - m68k_getpci() + 4;
			exception2_fetch_opcode(opcode, 0, pcoffset);
			return 6 * CYCLE_UNIT / 2 + count_cycles;
		}
		if (src) {
			m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
			regs.ir = regs.irc;
			opcode = regs.ir;
			if(regs.t1) opcode |= 0x10000;
			get_word_000_prefetch(2);
			if(hardware_bus_error) {
				int pcoffset = 0;
				exception2_fetch_opcode(opcode, 2, 0);
				return 6 * CYCLE_UNIT / 2 + count_cycles;
			}
			return 10 * CYCLE_UNIT / 2 + count_cycles;
		}
		count_cycles += 2 * CYCLE_UNIT / 2;
		pcadjust = 0;
	}
	m68k_setpci_j(oldpc + 4);
	get_word_000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		pcoffset += pcadjust;
		exception2_fetch_opcode(opcode, 0, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	if(regs.t1) opcode |= 0x10000;
	if (!cctrue(12)) {
		m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
	}
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (2/0) */
/* 4 0,0 B */

/* Scc.B (An) (GE) */
uae_u32 REGPARAM2 op_5cd0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int val = cctrue(12) ? 0xff : 0x00;
	put_byte_000(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (2/1) */
/* 2 0,0   */

/* Scc.B (An)+ (GE) */
uae_u32 REGPARAM2 op_5cd8_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int val = cctrue(12) ? 0xff : 0x00;
	put_byte_000(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (2/1) */
/* 2 0,0   */

/* Scc.B -(An) (GE) */
uae_u32 REGPARAM2 op_5ce0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) = srca;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int val = cctrue(12) ? 0xff : 0x00;
	put_byte_000(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 14 * CYCLE_UNIT / 2 + count_cycles;
}
/* 14 (2/1) */
/* 2 0,0   */

/* Scc.B (d16,An) (GE) */
uae_u32 REGPARAM2 op_5ce8_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int val = cctrue(12) ? 0xff : 0x00;
	put_byte_000(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 4 0,0   */

/* Scc.B (d8,An,Xn) (GE) */
uae_u32 REGPARAM2 op_5cf0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	BusCyclePenalty += 2;
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int val = cctrue(12) ? 0xff : 0x00;
	put_byte_000(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (3/1) */
/* 4 4,0   */

/* Scc.B (xxx).W (GE) */
uae_u32 REGPARAM2 op_5cf8_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 59;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int val = cctrue(12) ? 0xff : 0x00;
	put_byte_000(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 4 0,0   */

/* Scc.B (xxx).L (GE) */
uae_u32 REGPARAM2 op_5cf9_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 59;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	srca = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	srca |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int val = cctrue(12) ? 0xff : 0x00;
	put_byte_000(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (4/1) */
/* 6 0,0   */

/* Scc.B Dn (LT) */
uae_u32 REGPARAM2 op_5dc0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 4;  
	uae_s8 src = m68k_dreg(regs, srcreg);
	int val = cctrue(13) ? 0xff : 0x00;
	if (!val) {
		m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff);
	}
	opcode |= 0x20000;
	regs.ir = regs.irc;
	if (!val)
	opcode = regs.ir;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if(!val && regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff);
	count_cycles += ((val ? 2 : 0)) * CYCLE_UNIT / 2;
	m68k_incpci(2);
	return 4 * CYCLE_UNIT / 2 + count_cycles;
}
/* 4+ (1/0) */
/* 2 0,0   */

/* DBcc.W Dn,#<data>.W (LT) */
uae_u32 REGPARAM2 op_5dc8_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 58;
	CurrentInstrCycles = 12; 
	int pcadjust = -2;
	uae_s16 src = m68k_dreg(regs, srcreg);
	uae_s16 offs = regs.irc;
	uaecptr oldpc = m68k_getpci();
	if (!cctrue(13)) {
		m68k_incpci((uae_s32)offs + 2);
		if (offs & 1) {
			exception3_read_prefetch(opcode, m68k_getpci());
			return 2 * CYCLE_UNIT / 2 + count_cycles;
		}
		get_word_000_prefetch(0);
		if(hardware_bus_error) {
			int pcoffset = 0;
			pcoffset = oldpc - m68k_getpci() + 4;
			exception2_fetch_opcode(opcode, 0, pcoffset);
			return 6 * CYCLE_UNIT / 2 + count_cycles;
		}
		if (src) {
			m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
			regs.ir = regs.irc;
			opcode = regs.ir;
			if(regs.t1) opcode |= 0x10000;
			get_word_000_prefetch(2);
			if(hardware_bus_error) {
				int pcoffset = 0;
				exception2_fetch_opcode(opcode, 2, 0);
				return 6 * CYCLE_UNIT / 2 + count_cycles;
			}
			return 10 * CYCLE_UNIT / 2 + count_cycles;
		}
		count_cycles += 2 * CYCLE_UNIT / 2;
		pcadjust = 0;
	}
	m68k_setpci_j(oldpc + 4);
	get_word_000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		pcoffset += pcadjust;
		exception2_fetch_opcode(opcode, 0, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	if(regs.t1) opcode |= 0x10000;
	if (!cctrue(13)) {
		m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
	}
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (2/0) */
/* 4 0,0 B */

/* Scc.B (An) (LT) */
uae_u32 REGPARAM2 op_5dd0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int val = cctrue(13) ? 0xff : 0x00;
	put_byte_000(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (2/1) */
/* 2 0,0   */

/* Scc.B (An)+ (LT) */
uae_u32 REGPARAM2 op_5dd8_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int val = cctrue(13) ? 0xff : 0x00;
	put_byte_000(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (2/1) */
/* 2 0,0   */

/* Scc.B -(An) (LT) */
uae_u32 REGPARAM2 op_5de0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) = srca;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int val = cctrue(13) ? 0xff : 0x00;
	put_byte_000(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 14 * CYCLE_UNIT / 2 + count_cycles;
}
/* 14 (2/1) */
/* 2 0,0   */

/* Scc.B (d16,An) (LT) */
uae_u32 REGPARAM2 op_5de8_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int val = cctrue(13) ? 0xff : 0x00;
	put_byte_000(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 4 0,0   */

/* Scc.B (d8,An,Xn) (LT) */
uae_u32 REGPARAM2 op_5df0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	BusCyclePenalty += 2;
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int val = cctrue(13) ? 0xff : 0x00;
	put_byte_000(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (3/1) */
/* 4 4,0   */

/* Scc.B (xxx).W (LT) */
uae_u32 REGPARAM2 op_5df8_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 59;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int val = cctrue(13) ? 0xff : 0x00;
	put_byte_000(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 4 0,0   */

/* Scc.B (xxx).L (LT) */
uae_u32 REGPARAM2 op_5df9_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 59;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	srca = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	srca |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int val = cctrue(13) ? 0xff : 0x00;
	put_byte_000(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (4/1) */
/* 6 0,0   */

/* Scc.B Dn (GT) */
uae_u32 REGPARAM2 op_5ec0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 4;  
	uae_s8 src = m68k_dreg(regs, srcreg);
	int val = cctrue(14) ? 0xff : 0x00;
	if (!val) {
		m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff);
	}
	opcode |= 0x20000;
	regs.ir = regs.irc;
	if (!val)
	opcode = regs.ir;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if(!val && regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff);
	count_cycles += ((val ? 2 : 0)) * CYCLE_UNIT / 2;
	m68k_incpci(2);
	return 4 * CYCLE_UNIT / 2 + count_cycles;
}
/* 4+ (1/0) */
/* 2 0,0   */

/* DBcc.W Dn,#<data>.W (GT) */
uae_u32 REGPARAM2 op_5ec8_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 58;
	CurrentInstrCycles = 12; 
	int pcadjust = -2;
	uae_s16 src = m68k_dreg(regs, srcreg);
	uae_s16 offs = regs.irc;
	uaecptr oldpc = m68k_getpci();
	if (!cctrue(14)) {
		m68k_incpci((uae_s32)offs + 2);
		if (offs & 1) {
			exception3_read_prefetch(opcode, m68k_getpci());
			return 2 * CYCLE_UNIT / 2 + count_cycles;
		}
		get_word_000_prefetch(0);
		if(hardware_bus_error) {
			int pcoffset = 0;
			pcoffset = oldpc - m68k_getpci() + 4;
			exception2_fetch_opcode(opcode, 0, pcoffset);
			return 6 * CYCLE_UNIT / 2 + count_cycles;
		}
		if (src) {
			m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
			regs.ir = regs.irc;
			opcode = regs.ir;
			if(regs.t1) opcode |= 0x10000;
			get_word_000_prefetch(2);
			if(hardware_bus_error) {
				int pcoffset = 0;
				exception2_fetch_opcode(opcode, 2, 0);
				return 6 * CYCLE_UNIT / 2 + count_cycles;
			}
			return 10 * CYCLE_UNIT / 2 + count_cycles;
		}
		count_cycles += 2 * CYCLE_UNIT / 2;
		pcadjust = 0;
	}
	m68k_setpci_j(oldpc + 4);
	get_word_000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		pcoffset += pcadjust;
		exception2_fetch_opcode(opcode, 0, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	if(regs.t1) opcode |= 0x10000;
	if (!cctrue(14)) {
		m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
	}
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (2/0) */
/* 4 0,0 B */

/* Scc.B (An) (GT) */
uae_u32 REGPARAM2 op_5ed0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int val = cctrue(14) ? 0xff : 0x00;
	put_byte_000(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (2/1) */
/* 2 0,0   */

/* Scc.B (An)+ (GT) */
uae_u32 REGPARAM2 op_5ed8_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int val = cctrue(14) ? 0xff : 0x00;
	put_byte_000(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (2/1) */
/* 2 0,0   */

/* Scc.B -(An) (GT) */
uae_u32 REGPARAM2 op_5ee0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) = srca;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int val = cctrue(14) ? 0xff : 0x00;
	put_byte_000(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 14 * CYCLE_UNIT / 2 + count_cycles;
}
/* 14 (2/1) */
/* 2 0,0   */

/* Scc.B (d16,An) (GT) */
uae_u32 REGPARAM2 op_5ee8_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int val = cctrue(14) ? 0xff : 0x00;
	put_byte_000(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 4 0,0   */

/* Scc.B (d8,An,Xn) (GT) */
uae_u32 REGPARAM2 op_5ef0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	BusCyclePenalty += 2;
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int val = cctrue(14) ? 0xff : 0x00;
	put_byte_000(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (3/1) */
/* 4 4,0   */

/* Scc.B (xxx).W (GT) */
uae_u32 REGPARAM2 op_5ef8_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 59;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int val = cctrue(14) ? 0xff : 0x00;
	put_byte_000(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 4 0,0   */

/* Scc.B (xxx).L (GT) */
uae_u32 REGPARAM2 op_5ef9_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 59;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	srca = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	srca |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int val = cctrue(14) ? 0xff : 0x00;
	put_byte_000(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (4/1) */
/* 6 0,0   */

/* Scc.B Dn (LE) */
uae_u32 REGPARAM2 op_5fc0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 4;  
	uae_s8 src = m68k_dreg(regs, srcreg);
	int val = cctrue(15) ? 0xff : 0x00;
	if (!val) {
		m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff);
	}
	opcode |= 0x20000;
	regs.ir = regs.irc;
	if (!val)
	opcode = regs.ir;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if(!val && regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff);
	count_cycles += ((val ? 2 : 0)) * CYCLE_UNIT / 2;
	m68k_incpci(2);
	return 4 * CYCLE_UNIT / 2 + count_cycles;
}
/* 4+ (1/0) */
/* 2 0,0   */

/* DBcc.W Dn,#<data>.W (LE) */
uae_u32 REGPARAM2 op_5fc8_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 58;
	CurrentInstrCycles = 12; 
	int pcadjust = -2;
	uae_s16 src = m68k_dreg(regs, srcreg);
	uae_s16 offs = regs.irc;
	uaecptr oldpc = m68k_getpci();
	if (!cctrue(15)) {
		m68k_incpci((uae_s32)offs + 2);
		if (offs & 1) {
			exception3_read_prefetch(opcode, m68k_getpci());
			return 2 * CYCLE_UNIT / 2 + count_cycles;
		}
		get_word_000_prefetch(0);
		if(hardware_bus_error) {
			int pcoffset = 0;
			pcoffset = oldpc - m68k_getpci() + 4;
			exception2_fetch_opcode(opcode, 0, pcoffset);
			return 6 * CYCLE_UNIT / 2 + count_cycles;
		}
		if (src) {
			m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
			regs.ir = regs.irc;
			opcode = regs.ir;
			if(regs.t1) opcode |= 0x10000;
			get_word_000_prefetch(2);
			if(hardware_bus_error) {
				int pcoffset = 0;
				exception2_fetch_opcode(opcode, 2, 0);
				return 6 * CYCLE_UNIT / 2 + count_cycles;
			}
			return 10 * CYCLE_UNIT / 2 + count_cycles;
		}
		count_cycles += 2 * CYCLE_UNIT / 2;
		pcadjust = 0;
	}
	m68k_setpci_j(oldpc + 4);
	get_word_000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		pcoffset += pcadjust;
		exception2_fetch_opcode(opcode, 0, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	if(regs.t1) opcode |= 0x10000;
	if (!cctrue(15)) {
		m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
	}
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (2/0) */
/* 4 0,0 B */

/* Scc.B (An) (LE) */
uae_u32 REGPARAM2 op_5fd0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int val = cctrue(15) ? 0xff : 0x00;
	put_byte_000(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (2/1) */
/* 2 0,0   */

/* Scc.B (An)+ (LE) */
uae_u32 REGPARAM2 op_5fd8_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int val = cctrue(15) ? 0xff : 0x00;
	put_byte_000(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (2/1) */
/* 2 0,0   */

/* Scc.B -(An) (LE) */
uae_u32 REGPARAM2 op_5fe0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) = srca;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int val = cctrue(15) ? 0xff : 0x00;
	put_byte_000(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 14 * CYCLE_UNIT / 2 + count_cycles;
}
/* 14 (2/1) */
/* 2 0,0   */

/* Scc.B (d16,An) (LE) */
uae_u32 REGPARAM2 op_5fe8_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int val = cctrue(15) ? 0xff : 0x00;
	put_byte_000(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 4 0,0   */

/* Scc.B (d8,An,Xn) (LE) */
uae_u32 REGPARAM2 op_5ff0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	BusCyclePenalty += 2;
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int val = cctrue(15) ? 0xff : 0x00;
	put_byte_000(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (3/1) */
/* 4 4,0   */

/* Scc.B (xxx).W (LE) */
uae_u32 REGPARAM2 op_5ff8_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 59;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int val = cctrue(15) ? 0xff : 0x00;
	put_byte_000(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 4 0,0   */

/* Scc.B (xxx).L (LE) */
uae_u32 REGPARAM2 op_5ff9_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 59;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	srca = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	srca |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int val = cctrue(15) ? 0xff : 0x00;
	put_byte_000(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (4/1) */
/* 6 0,0   */

/* Bcc.W #<data>.W (T) */
uae_u32 REGPARAM2 op_6000_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 55;
	CurrentInstrCycles = 12; 
	uaecptr oldpc = m68k_getpci();
	uae_s16 src = regs.irc;
	if (cctrue(0)) {
		if (src & 1) {
			uaecptr addr = m68k_getpci() + (uae_s32)src + 2;
			exception3_read_prefetch(opcode, addr);
			return 2 * CYCLE_UNIT / 2 + count_cycles;
		}
		m68k_incpci((uae_s32)src + 2);
		int pcadjust = oldpc - m68k_getpci() + 2;
		get_word_000_prefetch(0);
		if(hardware_bus_error) {
			int pcoffset = 0;
			pcoffset += pcadjust;
			exception2_fetch_opcode(opcode, 0, pcoffset);
			return 6 * CYCLE_UNIT / 2 + count_cycles;
		}
		regs.ir = regs.irc;
		opcode = regs.ir;
		if(regs.t1) opcode |= 0x10000;
		get_word_000_prefetch(2);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 2, pcoffset);
			return 10 * CYCLE_UNIT / 2 + count_cycles;
		}
		return 10 * CYCLE_UNIT / 2;
	}
	m68k_incpci(4);
	get_word_000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	if(regs.t1) opcode |= 0x10000;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (2/0) */
/* 4 0,0 B */

/* BccQ.B #<data> (T) */
uae_u32 REGPARAM2 op_6001_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (uae_s32)(uae_s8)(real_opcode & 255);
	OpcodeFamily = 55;
	CurrentInstrCycles = 8;  
	uaecptr oldpc = m68k_getpci();
	uae_u32 src = srcreg;
	if (cctrue(0)) {
		if (src & 1) {
			uaecptr addr = m68k_getpci() + (uae_s32)src + 2;
			exception3_read_prefetch(opcode, addr);
			return 2 * CYCLE_UNIT / 2 + count_cycles;
		}
		m68k_incpci((uae_s32)src + 2);
		int pcadjust = oldpc - m68k_getpci() + 2;
		get_word_000_prefetch(0);
		if(hardware_bus_error) {
			int pcoffset = 0;
			pcoffset += pcadjust;
			exception2_fetch_opcode(opcode, 0, pcoffset);
			return 6 * CYCLE_UNIT / 2 + count_cycles;
		}
		regs.ir = regs.irc;
		opcode = regs.ir;
		if(regs.t1) opcode |= 0x10000;
		get_word_000_prefetch(2);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 2, pcoffset);
			return 10 * CYCLE_UNIT / 2 + count_cycles;
		}
		return 10 * CYCLE_UNIT / 2;
	}
	m68k_incpci(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	if(regs.t1) opcode |= 0x10000;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8 (1/0) */
/* 2 0,0 B */

/* Bcc.L #<data>.L (T) */
uae_u32 REGPARAM2 op_60ff_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 55;
	CurrentInstrCycles = 8;  
	uaecptr oldpc = m68k_getpci();
	if (cctrue(0)) {
		exception3_read_prefetch(opcode, m68k_getpci() + 1);
		return 2 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	if(regs.t1) opcode |= 0x10000;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8 (1/0) */
/* 2 0,0   */

/* BSR.W #<data>.W */
uae_u32 REGPARAM2 op_6100_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 54;
	CurrentInstrCycles = 18; 
	uae_s32 s;
	uae_s16 src = regs.irc;
	s = (uae_s32)src + 2;
	uaecptr oldpc = m68k_getpci();
	uaecptr nextpc = oldpc + 4;
	if (m68k_areg(regs, 7) & 1) {
		m68k_areg(regs, 7) -= 4;
		m68k_incpci(2);
		exception3_write_access(opcode, m68k_areg(regs, 7), sz_word, oldpc, 1);
		return 2 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, 7) -= 4;
	uaecptr dsta = m68k_areg(regs, 7);
	put_word_000(dsta, nextpc >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		exception2_write(opcode, dsta + 0, 0x1, nextpc >> 16, 1);
		return 2 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta + 2, nextpc);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		exception2_write(opcode, dsta + 2, 0x1, nextpc, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(s);
	if (m68k_getpci() & 1) {
		uaecptr addr = m68k_getpci();
		m68k_incpci(-2);
		exception3_read_prefetch(opcode, addr);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	#ifdef DEBUGGER
	if (debugmem_trace) {
		branch_stack_push(oldpc, nextpc);
	}
	#endif
	get_word_000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	if(regs.t1) opcode |= 0x10000;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (2/2) */
/* 4 0,0 B */

/* BSRQ.B #<data> */
uae_u32 REGPARAM2 op_6101_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (uae_s32)(uae_s8)(real_opcode & 255);
	OpcodeFamily = 54;
	CurrentInstrCycles = 18; 
	uae_s32 s;
	uae_u32 src = srcreg;
	s = (uae_s32)src + 2;
	uaecptr oldpc = m68k_getpci();
	uaecptr nextpc = oldpc + 2;
	if (m68k_areg(regs, 7) & 1) {
		m68k_areg(regs, 7) -= 4;
		m68k_incpci(2);
		exception3_write_access(opcode, m68k_areg(regs, 7), sz_word, oldpc, 1);
		return 2 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, 7) -= 4;
	uaecptr dsta = m68k_areg(regs, 7);
	put_word_000(dsta, nextpc >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		exception2_write(opcode, dsta + 0, 0x1, nextpc >> 16, 1);
		return 2 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta + 2, nextpc);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		exception2_write(opcode, dsta + 2, 0x1, nextpc, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(s);
	if (m68k_getpci() & 1) {
		uaecptr addr = m68k_getpci();
		m68k_incpci(-2);
		exception3_read_prefetch(opcode, addr);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	#ifdef DEBUGGER
	if (debugmem_trace) {
		branch_stack_push(oldpc, nextpc);
	}
	#endif
	get_word_000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	if(regs.t1) opcode |= 0x10000;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (2/2) */
/* 2 0,0 B */

/* BSR.L #<data>.L */
uae_u32 REGPARAM2 op_61ff_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 54;
	CurrentInstrCycles = 18; 
	uae_s32 s;
	uae_u32 src = 0xffffffff;
	s = (uae_s32)src + 2;
	uaecptr oldpc = m68k_getpci();
	uaecptr nextpc = oldpc + 2;
	if (m68k_areg(regs, 7) & 1) {
		m68k_areg(regs, 7) -= 4;
		m68k_incpci(2);
		exception3_write_access(opcode, m68k_areg(regs, 7), sz_word, oldpc, 1);
		return 2 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, 7) -= 4;
	uaecptr dsta = m68k_areg(regs, 7);
	put_word_000(dsta, nextpc >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		exception2_write(opcode, dsta + 0, 0x1, nextpc >> 16, 1);
		return 2 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta + 2, nextpc);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		exception2_write(opcode, dsta + 2, 0x1, nextpc, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(s);
	if (m68k_getpci() & 1) {
		uaecptr addr = m68k_getpci();
		m68k_incpci(-2);
		exception3_read_prefetch(opcode, addr);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	#ifdef DEBUGGER
	if (debugmem_trace) {
		branch_stack_push(oldpc, nextpc);
	}
	#endif
	get_word_000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	if(regs.t1) opcode |= 0x10000;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (2/2) */
/* 2 0,0 B */

/* Bcc.W #<data>.W (HI) */
uae_u32 REGPARAM2 op_6200_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 55;
	CurrentInstrCycles = 12; 
	uaecptr oldpc = m68k_getpci();
	uae_s16 src = regs.irc;
	if (cctrue(2)) {
		if (src & 1) {
			uaecptr addr = m68k_getpci() + (uae_s32)src + 2;
			exception3_read_prefetch(opcode, addr);
			return 2 * CYCLE_UNIT / 2 + count_cycles;
		}
		m68k_incpci((uae_s32)src + 2);
		int pcadjust = oldpc - m68k_getpci() + 2;
		get_word_000_prefetch(0);
		if(hardware_bus_error) {
			int pcoffset = 0;
			pcoffset += pcadjust;
			exception2_fetch_opcode(opcode, 0, pcoffset);
			return 6 * CYCLE_UNIT / 2 + count_cycles;
		}
		regs.ir = regs.irc;
		opcode = regs.ir;
		if(regs.t1) opcode |= 0x10000;
		get_word_000_prefetch(2);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 2, pcoffset);
			return 10 * CYCLE_UNIT / 2 + count_cycles;
		}
		return 10 * CYCLE_UNIT / 2;
	}
	m68k_incpci(4);
	get_word_000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	if(regs.t1) opcode |= 0x10000;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (2/0) */
/* 4 0,0 B */

/* BccQ.B #<data> (HI) */
uae_u32 REGPARAM2 op_6201_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (uae_s32)(uae_s8)(real_opcode & 255);
	OpcodeFamily = 55;
	CurrentInstrCycles = 8;  
	uaecptr oldpc = m68k_getpci();
	uae_u32 src = srcreg;
	if (cctrue(2)) {
		if (src & 1) {
			uaecptr addr = m68k_getpci() + (uae_s32)src + 2;
			exception3_read_prefetch(opcode, addr);
			return 2 * CYCLE_UNIT / 2 + count_cycles;
		}
		m68k_incpci((uae_s32)src + 2);
		int pcadjust = oldpc - m68k_getpci() + 2;
		get_word_000_prefetch(0);
		if(hardware_bus_error) {
			int pcoffset = 0;
			pcoffset += pcadjust;
			exception2_fetch_opcode(opcode, 0, pcoffset);
			return 6 * CYCLE_UNIT / 2 + count_cycles;
		}
		regs.ir = regs.irc;
		opcode = regs.ir;
		if(regs.t1) opcode |= 0x10000;
		get_word_000_prefetch(2);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 2, pcoffset);
			return 10 * CYCLE_UNIT / 2 + count_cycles;
		}
		return 10 * CYCLE_UNIT / 2;
	}
	m68k_incpci(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	if(regs.t1) opcode |= 0x10000;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8 (1/0) */
/* 2 0,0 B */

/* Bcc.L #<data>.L (HI) */
uae_u32 REGPARAM2 op_62ff_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 55;
	CurrentInstrCycles = 8;  
	uaecptr oldpc = m68k_getpci();
	if (cctrue(2)) {
		exception3_read_prefetch(opcode, m68k_getpci() + 1);
		return 2 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	if(regs.t1) opcode |= 0x10000;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8 (1/0) */
/* 2 0,0   */

/* Bcc.W #<data>.W (LS) */
uae_u32 REGPARAM2 op_6300_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 55;
	CurrentInstrCycles = 12; 
	uaecptr oldpc = m68k_getpci();
	uae_s16 src = regs.irc;
	if (cctrue(3)) {
		if (src & 1) {
			uaecptr addr = m68k_getpci() + (uae_s32)src + 2;
			exception3_read_prefetch(opcode, addr);
			return 2 * CYCLE_UNIT / 2 + count_cycles;
		}
		m68k_incpci((uae_s32)src + 2);
		int pcadjust = oldpc - m68k_getpci() + 2;
		get_word_000_prefetch(0);
		if(hardware_bus_error) {
			int pcoffset = 0;
			pcoffset += pcadjust;
			exception2_fetch_opcode(opcode, 0, pcoffset);
			return 6 * CYCLE_UNIT / 2 + count_cycles;
		}
		regs.ir = regs.irc;
		opcode = regs.ir;
		if(regs.t1) opcode |= 0x10000;
		get_word_000_prefetch(2);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 2, pcoffset);
			return 10 * CYCLE_UNIT / 2 + count_cycles;
		}
		return 10 * CYCLE_UNIT / 2;
	}
	m68k_incpci(4);
	get_word_000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	if(regs.t1) opcode |= 0x10000;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (2/0) */
/* 4 0,0 B */

/* BccQ.B #<data> (LS) */
uae_u32 REGPARAM2 op_6301_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (uae_s32)(uae_s8)(real_opcode & 255);
	OpcodeFamily = 55;
	CurrentInstrCycles = 8;  
	uaecptr oldpc = m68k_getpci();
	uae_u32 src = srcreg;
	if (cctrue(3)) {
		if (src & 1) {
			uaecptr addr = m68k_getpci() + (uae_s32)src + 2;
			exception3_read_prefetch(opcode, addr);
			return 2 * CYCLE_UNIT / 2 + count_cycles;
		}
		m68k_incpci((uae_s32)src + 2);
		int pcadjust = oldpc - m68k_getpci() + 2;
		get_word_000_prefetch(0);
		if(hardware_bus_error) {
			int pcoffset = 0;
			pcoffset += pcadjust;
			exception2_fetch_opcode(opcode, 0, pcoffset);
			return 6 * CYCLE_UNIT / 2 + count_cycles;
		}
		regs.ir = regs.irc;
		opcode = regs.ir;
		if(regs.t1) opcode |= 0x10000;
		get_word_000_prefetch(2);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 2, pcoffset);
			return 10 * CYCLE_UNIT / 2 + count_cycles;
		}
		return 10 * CYCLE_UNIT / 2;
	}
	m68k_incpci(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	if(regs.t1) opcode |= 0x10000;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8 (1/0) */
/* 2 0,0 B */

/* Bcc.L #<data>.L (LS) */
uae_u32 REGPARAM2 op_63ff_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 55;
	CurrentInstrCycles = 8;  
	uaecptr oldpc = m68k_getpci();
	if (cctrue(3)) {
		exception3_read_prefetch(opcode, m68k_getpci() + 1);
		return 2 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	if(regs.t1) opcode |= 0x10000;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8 (1/0) */
/* 2 0,0   */

/* Bcc.W #<data>.W (CC) */
uae_u32 REGPARAM2 op_6400_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 55;
	CurrentInstrCycles = 12; 
	uaecptr oldpc = m68k_getpci();
	uae_s16 src = regs.irc;
	if (cctrue(4)) {
		if (src & 1) {
			uaecptr addr = m68k_getpci() + (uae_s32)src + 2;
			exception3_read_prefetch(opcode, addr);
			return 2 * CYCLE_UNIT / 2 + count_cycles;
		}
		m68k_incpci((uae_s32)src + 2);
		int pcadjust = oldpc - m68k_getpci() + 2;
		get_word_000_prefetch(0);
		if(hardware_bus_error) {
			int pcoffset = 0;
			pcoffset += pcadjust;
			exception2_fetch_opcode(opcode, 0, pcoffset);
			return 6 * CYCLE_UNIT / 2 + count_cycles;
		}
		regs.ir = regs.irc;
		opcode = regs.ir;
		if(regs.t1) opcode |= 0x10000;
		get_word_000_prefetch(2);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 2, pcoffset);
			return 10 * CYCLE_UNIT / 2 + count_cycles;
		}
		return 10 * CYCLE_UNIT / 2;
	}
	m68k_incpci(4);
	get_word_000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	if(regs.t1) opcode |= 0x10000;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (2/0) */
/* 4 0,0 B */

/* BccQ.B #<data> (CC) */
uae_u32 REGPARAM2 op_6401_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (uae_s32)(uae_s8)(real_opcode & 255);
	OpcodeFamily = 55;
	CurrentInstrCycles = 8;  
	uaecptr oldpc = m68k_getpci();
	uae_u32 src = srcreg;
	if (cctrue(4)) {
		if (src & 1) {
			uaecptr addr = m68k_getpci() + (uae_s32)src + 2;
			exception3_read_prefetch(opcode, addr);
			return 2 * CYCLE_UNIT / 2 + count_cycles;
		}
		m68k_incpci((uae_s32)src + 2);
		int pcadjust = oldpc - m68k_getpci() + 2;
		get_word_000_prefetch(0);
		if(hardware_bus_error) {
			int pcoffset = 0;
			pcoffset += pcadjust;
			exception2_fetch_opcode(opcode, 0, pcoffset);
			return 6 * CYCLE_UNIT / 2 + count_cycles;
		}
		regs.ir = regs.irc;
		opcode = regs.ir;
		if(regs.t1) opcode |= 0x10000;
		get_word_000_prefetch(2);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 2, pcoffset);
			return 10 * CYCLE_UNIT / 2 + count_cycles;
		}
		return 10 * CYCLE_UNIT / 2;
	}
	m68k_incpci(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	if(regs.t1) opcode |= 0x10000;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8 (1/0) */
/* 2 0,0 B */

/* Bcc.L #<data>.L (CC) */
uae_u32 REGPARAM2 op_64ff_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 55;
	CurrentInstrCycles = 8;  
	uaecptr oldpc = m68k_getpci();
	if (cctrue(4)) {
		exception3_read_prefetch(opcode, m68k_getpci() + 1);
		return 2 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	if(regs.t1) opcode |= 0x10000;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8 (1/0) */
/* 2 0,0   */

/* Bcc.W #<data>.W (CS) */
uae_u32 REGPARAM2 op_6500_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 55;
	CurrentInstrCycles = 12; 
	uaecptr oldpc = m68k_getpci();
	uae_s16 src = regs.irc;
	if (cctrue(5)) {
		if (src & 1) {
			uaecptr addr = m68k_getpci() + (uae_s32)src + 2;
			exception3_read_prefetch(opcode, addr);
			return 2 * CYCLE_UNIT / 2 + count_cycles;
		}
		m68k_incpci((uae_s32)src + 2);
		int pcadjust = oldpc - m68k_getpci() + 2;
		get_word_000_prefetch(0);
		if(hardware_bus_error) {
			int pcoffset = 0;
			pcoffset += pcadjust;
			exception2_fetch_opcode(opcode, 0, pcoffset);
			return 6 * CYCLE_UNIT / 2 + count_cycles;
		}
		regs.ir = regs.irc;
		opcode = regs.ir;
		if(regs.t1) opcode |= 0x10000;
		get_word_000_prefetch(2);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 2, pcoffset);
			return 10 * CYCLE_UNIT / 2 + count_cycles;
		}
		return 10 * CYCLE_UNIT / 2;
	}
	m68k_incpci(4);
	get_word_000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	if(regs.t1) opcode |= 0x10000;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (2/0) */
/* 4 0,0 B */

/* BccQ.B #<data> (CS) */
uae_u32 REGPARAM2 op_6501_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (uae_s32)(uae_s8)(real_opcode & 255);
	OpcodeFamily = 55;
	CurrentInstrCycles = 8;  
	uaecptr oldpc = m68k_getpci();
	uae_u32 src = srcreg;
	if (cctrue(5)) {
		if (src & 1) {
			uaecptr addr = m68k_getpci() + (uae_s32)src + 2;
			exception3_read_prefetch(opcode, addr);
			return 2 * CYCLE_UNIT / 2 + count_cycles;
		}
		m68k_incpci((uae_s32)src + 2);
		int pcadjust = oldpc - m68k_getpci() + 2;
		get_word_000_prefetch(0);
		if(hardware_bus_error) {
			int pcoffset = 0;
			pcoffset += pcadjust;
			exception2_fetch_opcode(opcode, 0, pcoffset);
			return 6 * CYCLE_UNIT / 2 + count_cycles;
		}
		regs.ir = regs.irc;
		opcode = regs.ir;
		if(regs.t1) opcode |= 0x10000;
		get_word_000_prefetch(2);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 2, pcoffset);
			return 10 * CYCLE_UNIT / 2 + count_cycles;
		}
		return 10 * CYCLE_UNIT / 2;
	}
	m68k_incpci(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	if(regs.t1) opcode |= 0x10000;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8 (1/0) */
/* 2 0,0 B */

/* Bcc.L #<data>.L (CS) */
uae_u32 REGPARAM2 op_65ff_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 55;
	CurrentInstrCycles = 8;  
	uaecptr oldpc = m68k_getpci();
	if (cctrue(5)) {
		exception3_read_prefetch(opcode, m68k_getpci() + 1);
		return 2 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	if(regs.t1) opcode |= 0x10000;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8 (1/0) */
/* 2 0,0   */

/* Bcc.W #<data>.W (NE) */
uae_u32 REGPARAM2 op_6600_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 55;
	CurrentInstrCycles = 12; 
	uaecptr oldpc = m68k_getpci();
	uae_s16 src = regs.irc;
	if (cctrue(6)) {
		if (src & 1) {
			uaecptr addr = m68k_getpci() + (uae_s32)src + 2;
			exception3_read_prefetch(opcode, addr);
			return 2 * CYCLE_UNIT / 2 + count_cycles;
		}
		m68k_incpci((uae_s32)src + 2);
		int pcadjust = oldpc - m68k_getpci() + 2;
		get_word_000_prefetch(0);
		if(hardware_bus_error) {
			int pcoffset = 0;
			pcoffset += pcadjust;
			exception2_fetch_opcode(opcode, 0, pcoffset);
			return 6 * CYCLE_UNIT / 2 + count_cycles;
		}
		regs.ir = regs.irc;
		opcode = regs.ir;
		if(regs.t1) opcode |= 0x10000;
		get_word_000_prefetch(2);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 2, pcoffset);
			return 10 * CYCLE_UNIT / 2 + count_cycles;
		}
		return 10 * CYCLE_UNIT / 2;
	}
	m68k_incpci(4);
	get_word_000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	if(regs.t1) opcode |= 0x10000;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (2/0) */
/* 4 0,0 B */

/* BccQ.B #<data> (NE) */
uae_u32 REGPARAM2 op_6601_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (uae_s32)(uae_s8)(real_opcode & 255);
	OpcodeFamily = 55;
	CurrentInstrCycles = 8;  
	uaecptr oldpc = m68k_getpci();
	uae_u32 src = srcreg;
	if (cctrue(6)) {
		if (src & 1) {
			uaecptr addr = m68k_getpci() + (uae_s32)src + 2;
			exception3_read_prefetch(opcode, addr);
			return 2 * CYCLE_UNIT / 2 + count_cycles;
		}
		m68k_incpci((uae_s32)src + 2);
		int pcadjust = oldpc - m68k_getpci() + 2;
		get_word_000_prefetch(0);
		if(hardware_bus_error) {
			int pcoffset = 0;
			pcoffset += pcadjust;
			exception2_fetch_opcode(opcode, 0, pcoffset);
			return 6 * CYCLE_UNIT / 2 + count_cycles;
		}
		regs.ir = regs.irc;
		opcode = regs.ir;
		if(regs.t1) opcode |= 0x10000;
		get_word_000_prefetch(2);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 2, pcoffset);
			return 10 * CYCLE_UNIT / 2 + count_cycles;
		}
		return 10 * CYCLE_UNIT / 2;
	}
	m68k_incpci(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	if(regs.t1) opcode |= 0x10000;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8 (1/0) */
/* 2 0,0 B */

/* Bcc.L #<data>.L (NE) */
uae_u32 REGPARAM2 op_66ff_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 55;
	CurrentInstrCycles = 8;  
	uaecptr oldpc = m68k_getpci();
	if (cctrue(6)) {
		exception3_read_prefetch(opcode, m68k_getpci() + 1);
		return 2 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	if(regs.t1) opcode |= 0x10000;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8 (1/0) */
/* 2 0,0   */

/* Bcc.W #<data>.W (EQ) */
uae_u32 REGPARAM2 op_6700_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 55;
	CurrentInstrCycles = 12; 
	uaecptr oldpc = m68k_getpci();
	uae_s16 src = regs.irc;
	if (cctrue(7)) {
		if (src & 1) {
			uaecptr addr = m68k_getpci() + (uae_s32)src + 2;
			exception3_read_prefetch(opcode, addr);
			return 2 * CYCLE_UNIT / 2 + count_cycles;
		}
		m68k_incpci((uae_s32)src + 2);
		int pcadjust = oldpc - m68k_getpci() + 2;
		get_word_000_prefetch(0);
		if(hardware_bus_error) {
			int pcoffset = 0;
			pcoffset += pcadjust;
			exception2_fetch_opcode(opcode, 0, pcoffset);
			return 6 * CYCLE_UNIT / 2 + count_cycles;
		}
		regs.ir = regs.irc;
		opcode = regs.ir;
		if(regs.t1) opcode |= 0x10000;
		get_word_000_prefetch(2);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 2, pcoffset);
			return 10 * CYCLE_UNIT / 2 + count_cycles;
		}
		return 10 * CYCLE_UNIT / 2;
	}
	m68k_incpci(4);
	get_word_000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	if(regs.t1) opcode |= 0x10000;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (2/0) */
/* 4 0,0 B */

/* BccQ.B #<data> (EQ) */
uae_u32 REGPARAM2 op_6701_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (uae_s32)(uae_s8)(real_opcode & 255);
	OpcodeFamily = 55;
	CurrentInstrCycles = 8;  
	uaecptr oldpc = m68k_getpci();
	uae_u32 src = srcreg;
	if (cctrue(7)) {
		if (src & 1) {
			uaecptr addr = m68k_getpci() + (uae_s32)src + 2;
			exception3_read_prefetch(opcode, addr);
			return 2 * CYCLE_UNIT / 2 + count_cycles;
		}
		m68k_incpci((uae_s32)src + 2);
		int pcadjust = oldpc - m68k_getpci() + 2;
		get_word_000_prefetch(0);
		if(hardware_bus_error) {
			int pcoffset = 0;
			pcoffset += pcadjust;
			exception2_fetch_opcode(opcode, 0, pcoffset);
			return 6 * CYCLE_UNIT / 2 + count_cycles;
		}
		regs.ir = regs.irc;
		opcode = regs.ir;
		if(regs.t1) opcode |= 0x10000;
		get_word_000_prefetch(2);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 2, pcoffset);
			return 10 * CYCLE_UNIT / 2 + count_cycles;
		}
		return 10 * CYCLE_UNIT / 2;
	}
	m68k_incpci(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	if(regs.t1) opcode |= 0x10000;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8 (1/0) */
/* 2 0,0 B */

/* Bcc.L #<data>.L (EQ) */
uae_u32 REGPARAM2 op_67ff_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 55;
	CurrentInstrCycles = 8;  
	uaecptr oldpc = m68k_getpci();
	if (cctrue(7)) {
		exception3_read_prefetch(opcode, m68k_getpci() + 1);
		return 2 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	if(regs.t1) opcode |= 0x10000;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8 (1/0) */
/* 2 0,0   */

/* Bcc.W #<data>.W (VC) */
uae_u32 REGPARAM2 op_6800_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 55;
	CurrentInstrCycles = 12; 
	uaecptr oldpc = m68k_getpci();
	uae_s16 src = regs.irc;
	if (cctrue(8)) {
		if (src & 1) {
			uaecptr addr = m68k_getpci() + (uae_s32)src + 2;
			exception3_read_prefetch(opcode, addr);
			return 2 * CYCLE_UNIT / 2 + count_cycles;
		}
		m68k_incpci((uae_s32)src + 2);
		int pcadjust = oldpc - m68k_getpci() + 2;
		get_word_000_prefetch(0);
		if(hardware_bus_error) {
			int pcoffset = 0;
			pcoffset += pcadjust;
			exception2_fetch_opcode(opcode, 0, pcoffset);
			return 6 * CYCLE_UNIT / 2 + count_cycles;
		}
		regs.ir = regs.irc;
		opcode = regs.ir;
		if(regs.t1) opcode |= 0x10000;
		get_word_000_prefetch(2);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 2, pcoffset);
			return 10 * CYCLE_UNIT / 2 + count_cycles;
		}
		return 10 * CYCLE_UNIT / 2;
	}
	m68k_incpci(4);
	get_word_000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	if(regs.t1) opcode |= 0x10000;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (2/0) */
/* 4 0,0 B */

/* BccQ.B #<data> (VC) */
uae_u32 REGPARAM2 op_6801_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (uae_s32)(uae_s8)(real_opcode & 255);
	OpcodeFamily = 55;
	CurrentInstrCycles = 8;  
	uaecptr oldpc = m68k_getpci();
	uae_u32 src = srcreg;
	if (cctrue(8)) {
		if (src & 1) {
			uaecptr addr = m68k_getpci() + (uae_s32)src + 2;
			exception3_read_prefetch(opcode, addr);
			return 2 * CYCLE_UNIT / 2 + count_cycles;
		}
		m68k_incpci((uae_s32)src + 2);
		int pcadjust = oldpc - m68k_getpci() + 2;
		get_word_000_prefetch(0);
		if(hardware_bus_error) {
			int pcoffset = 0;
			pcoffset += pcadjust;
			exception2_fetch_opcode(opcode, 0, pcoffset);
			return 6 * CYCLE_UNIT / 2 + count_cycles;
		}
		regs.ir = regs.irc;
		opcode = regs.ir;
		if(regs.t1) opcode |= 0x10000;
		get_word_000_prefetch(2);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 2, pcoffset);
			return 10 * CYCLE_UNIT / 2 + count_cycles;
		}
		return 10 * CYCLE_UNIT / 2;
	}
	m68k_incpci(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	if(regs.t1) opcode |= 0x10000;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8 (1/0) */
/* 2 0,0 B */

/* Bcc.L #<data>.L (VC) */
uae_u32 REGPARAM2 op_68ff_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 55;
	CurrentInstrCycles = 8;  
	uaecptr oldpc = m68k_getpci();
	if (cctrue(8)) {
		exception3_read_prefetch(opcode, m68k_getpci() + 1);
		return 2 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	if(regs.t1) opcode |= 0x10000;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8 (1/0) */
/* 2 0,0   */

/* Bcc.W #<data>.W (VS) */
uae_u32 REGPARAM2 op_6900_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 55;
	CurrentInstrCycles = 12; 
	uaecptr oldpc = m68k_getpci();
	uae_s16 src = regs.irc;
	if (cctrue(9)) {
		if (src & 1) {
			uaecptr addr = m68k_getpci() + (uae_s32)src + 2;
			exception3_read_prefetch(opcode, addr);
			return 2 * CYCLE_UNIT / 2 + count_cycles;
		}
		m68k_incpci((uae_s32)src + 2);
		int pcadjust = oldpc - m68k_getpci() + 2;
		get_word_000_prefetch(0);
		if(hardware_bus_error) {
			int pcoffset = 0;
			pcoffset += pcadjust;
			exception2_fetch_opcode(opcode, 0, pcoffset);
			return 6 * CYCLE_UNIT / 2 + count_cycles;
		}
		regs.ir = regs.irc;
		opcode = regs.ir;
		if(regs.t1) opcode |= 0x10000;
		get_word_000_prefetch(2);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 2, pcoffset);
			return 10 * CYCLE_UNIT / 2 + count_cycles;
		}
		return 10 * CYCLE_UNIT / 2;
	}
	m68k_incpci(4);
	get_word_000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	if(regs.t1) opcode |= 0x10000;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (2/0) */
/* 4 0,0 B */

/* BccQ.B #<data> (VS) */
uae_u32 REGPARAM2 op_6901_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (uae_s32)(uae_s8)(real_opcode & 255);
	OpcodeFamily = 55;
	CurrentInstrCycles = 8;  
	uaecptr oldpc = m68k_getpci();
	uae_u32 src = srcreg;
	if (cctrue(9)) {
		if (src & 1) {
			uaecptr addr = m68k_getpci() + (uae_s32)src + 2;
			exception3_read_prefetch(opcode, addr);
			return 2 * CYCLE_UNIT / 2 + count_cycles;
		}
		m68k_incpci((uae_s32)src + 2);
		int pcadjust = oldpc - m68k_getpci() + 2;
		get_word_000_prefetch(0);
		if(hardware_bus_error) {
			int pcoffset = 0;
			pcoffset += pcadjust;
			exception2_fetch_opcode(opcode, 0, pcoffset);
			return 6 * CYCLE_UNIT / 2 + count_cycles;
		}
		regs.ir = regs.irc;
		opcode = regs.ir;
		if(regs.t1) opcode |= 0x10000;
		get_word_000_prefetch(2);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 2, pcoffset);
			return 10 * CYCLE_UNIT / 2 + count_cycles;
		}
		return 10 * CYCLE_UNIT / 2;
	}
	m68k_incpci(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	if(regs.t1) opcode |= 0x10000;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8 (1/0) */
/* 2 0,0 B */

/* Bcc.L #<data>.L (VS) */
uae_u32 REGPARAM2 op_69ff_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 55;
	CurrentInstrCycles = 8;  
	uaecptr oldpc = m68k_getpci();
	if (cctrue(9)) {
		exception3_read_prefetch(opcode, m68k_getpci() + 1);
		return 2 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	if(regs.t1) opcode |= 0x10000;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8 (1/0) */
/* 2 0,0   */

/* Bcc.W #<data>.W (PL) */
uae_u32 REGPARAM2 op_6a00_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 55;
	CurrentInstrCycles = 12; 
	uaecptr oldpc = m68k_getpci();
	uae_s16 src = regs.irc;
	if (cctrue(10)) {
		if (src & 1) {
			uaecptr addr = m68k_getpci() + (uae_s32)src + 2;
			exception3_read_prefetch(opcode, addr);
			return 2 * CYCLE_UNIT / 2 + count_cycles;
		}
		m68k_incpci((uae_s32)src + 2);
		int pcadjust = oldpc - m68k_getpci() + 2;
		get_word_000_prefetch(0);
		if(hardware_bus_error) {
			int pcoffset = 0;
			pcoffset += pcadjust;
			exception2_fetch_opcode(opcode, 0, pcoffset);
			return 6 * CYCLE_UNIT / 2 + count_cycles;
		}
		regs.ir = regs.irc;
		opcode = regs.ir;
		if(regs.t1) opcode |= 0x10000;
		get_word_000_prefetch(2);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 2, pcoffset);
			return 10 * CYCLE_UNIT / 2 + count_cycles;
		}
		return 10 * CYCLE_UNIT / 2;
	}
	m68k_incpci(4);
	get_word_000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	if(regs.t1) opcode |= 0x10000;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (2/0) */
/* 4 0,0 B */

/* BccQ.B #<data> (PL) */
uae_u32 REGPARAM2 op_6a01_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (uae_s32)(uae_s8)(real_opcode & 255);
	OpcodeFamily = 55;
	CurrentInstrCycles = 8;  
	uaecptr oldpc = m68k_getpci();
	uae_u32 src = srcreg;
	if (cctrue(10)) {
		if (src & 1) {
			uaecptr addr = m68k_getpci() + (uae_s32)src + 2;
			exception3_read_prefetch(opcode, addr);
			return 2 * CYCLE_UNIT / 2 + count_cycles;
		}
		m68k_incpci((uae_s32)src + 2);
		int pcadjust = oldpc - m68k_getpci() + 2;
		get_word_000_prefetch(0);
		if(hardware_bus_error) {
			int pcoffset = 0;
			pcoffset += pcadjust;
			exception2_fetch_opcode(opcode, 0, pcoffset);
			return 6 * CYCLE_UNIT / 2 + count_cycles;
		}
		regs.ir = regs.irc;
		opcode = regs.ir;
		if(regs.t1) opcode |= 0x10000;
		get_word_000_prefetch(2);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 2, pcoffset);
			return 10 * CYCLE_UNIT / 2 + count_cycles;
		}
		return 10 * CYCLE_UNIT / 2;
	}
	m68k_incpci(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	if(regs.t1) opcode |= 0x10000;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8 (1/0) */
/* 2 0,0 B */

/* Bcc.L #<data>.L (PL) */
uae_u32 REGPARAM2 op_6aff_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 55;
	CurrentInstrCycles = 8;  
	uaecptr oldpc = m68k_getpci();
	if (cctrue(10)) {
		exception3_read_prefetch(opcode, m68k_getpci() + 1);
		return 2 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	if(regs.t1) opcode |= 0x10000;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8 (1/0) */
/* 2 0,0   */

/* Bcc.W #<data>.W (MI) */
uae_u32 REGPARAM2 op_6b00_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 55;
	CurrentInstrCycles = 12; 
	uaecptr oldpc = m68k_getpci();
	uae_s16 src = regs.irc;
	if (cctrue(11)) {
		if (src & 1) {
			uaecptr addr = m68k_getpci() + (uae_s32)src + 2;
			exception3_read_prefetch(opcode, addr);
			return 2 * CYCLE_UNIT / 2 + count_cycles;
		}
		m68k_incpci((uae_s32)src + 2);
		int pcadjust = oldpc - m68k_getpci() + 2;
		get_word_000_prefetch(0);
		if(hardware_bus_error) {
			int pcoffset = 0;
			pcoffset += pcadjust;
			exception2_fetch_opcode(opcode, 0, pcoffset);
			return 6 * CYCLE_UNIT / 2 + count_cycles;
		}
		regs.ir = regs.irc;
		opcode = regs.ir;
		if(regs.t1) opcode |= 0x10000;
		get_word_000_prefetch(2);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 2, pcoffset);
			return 10 * CYCLE_UNIT / 2 + count_cycles;
		}
		return 10 * CYCLE_UNIT / 2;
	}
	m68k_incpci(4);
	get_word_000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	if(regs.t1) opcode |= 0x10000;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (2/0) */
/* 4 0,0 B */

/* BccQ.B #<data> (MI) */
uae_u32 REGPARAM2 op_6b01_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (uae_s32)(uae_s8)(real_opcode & 255);
	OpcodeFamily = 55;
	CurrentInstrCycles = 8;  
	uaecptr oldpc = m68k_getpci();
	uae_u32 src = srcreg;
	if (cctrue(11)) {
		if (src & 1) {
			uaecptr addr = m68k_getpci() + (uae_s32)src + 2;
			exception3_read_prefetch(opcode, addr);
			return 2 * CYCLE_UNIT / 2 + count_cycles;
		}
		m68k_incpci((uae_s32)src + 2);
		int pcadjust = oldpc - m68k_getpci() + 2;
		get_word_000_prefetch(0);
		if(hardware_bus_error) {
			int pcoffset = 0;
			pcoffset += pcadjust;
			exception2_fetch_opcode(opcode, 0, pcoffset);
			return 6 * CYCLE_UNIT / 2 + count_cycles;
		}
		regs.ir = regs.irc;
		opcode = regs.ir;
		if(regs.t1) opcode |= 0x10000;
		get_word_000_prefetch(2);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 2, pcoffset);
			return 10 * CYCLE_UNIT / 2 + count_cycles;
		}
		return 10 * CYCLE_UNIT / 2;
	}
	m68k_incpci(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	if(regs.t1) opcode |= 0x10000;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8 (1/0) */
/* 2 0,0 B */

/* Bcc.L #<data>.L (MI) */
uae_u32 REGPARAM2 op_6bff_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 55;
	CurrentInstrCycles = 8;  
	uaecptr oldpc = m68k_getpci();
	if (cctrue(11)) {
		exception3_read_prefetch(opcode, m68k_getpci() + 1);
		return 2 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	if(regs.t1) opcode |= 0x10000;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8 (1/0) */
/* 2 0,0   */

/* Bcc.W #<data>.W (GE) */
uae_u32 REGPARAM2 op_6c00_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 55;
	CurrentInstrCycles = 12; 
	uaecptr oldpc = m68k_getpci();
	uae_s16 src = regs.irc;
	if (cctrue(12)) {
		if (src & 1) {
			uaecptr addr = m68k_getpci() + (uae_s32)src + 2;
			exception3_read_prefetch(opcode, addr);
			return 2 * CYCLE_UNIT / 2 + count_cycles;
		}
		m68k_incpci((uae_s32)src + 2);
		int pcadjust = oldpc - m68k_getpci() + 2;
		get_word_000_prefetch(0);
		if(hardware_bus_error) {
			int pcoffset = 0;
			pcoffset += pcadjust;
			exception2_fetch_opcode(opcode, 0, pcoffset);
			return 6 * CYCLE_UNIT / 2 + count_cycles;
		}
		regs.ir = regs.irc;
		opcode = regs.ir;
		if(regs.t1) opcode |= 0x10000;
		get_word_000_prefetch(2);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 2, pcoffset);
			return 10 * CYCLE_UNIT / 2 + count_cycles;
		}
		return 10 * CYCLE_UNIT / 2;
	}
	m68k_incpci(4);
	get_word_000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	if(regs.t1) opcode |= 0x10000;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (2/0) */
/* 4 0,0 B */

/* BccQ.B #<data> (GE) */
uae_u32 REGPARAM2 op_6c01_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (uae_s32)(uae_s8)(real_opcode & 255);
	OpcodeFamily = 55;
	CurrentInstrCycles = 8;  
	uaecptr oldpc = m68k_getpci();
	uae_u32 src = srcreg;
	if (cctrue(12)) {
		if (src & 1) {
			uaecptr addr = m68k_getpci() + (uae_s32)src + 2;
			exception3_read_prefetch(opcode, addr);
			return 2 * CYCLE_UNIT / 2 + count_cycles;
		}
		m68k_incpci((uae_s32)src + 2);
		int pcadjust = oldpc - m68k_getpci() + 2;
		get_word_000_prefetch(0);
		if(hardware_bus_error) {
			int pcoffset = 0;
			pcoffset += pcadjust;
			exception2_fetch_opcode(opcode, 0, pcoffset);
			return 6 * CYCLE_UNIT / 2 + count_cycles;
		}
		regs.ir = regs.irc;
		opcode = regs.ir;
		if(regs.t1) opcode |= 0x10000;
		get_word_000_prefetch(2);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 2, pcoffset);
			return 10 * CYCLE_UNIT / 2 + count_cycles;
		}
		return 10 * CYCLE_UNIT / 2;
	}
	m68k_incpci(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	if(regs.t1) opcode |= 0x10000;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8 (1/0) */
/* 2 0,0 B */

/* Bcc.L #<data>.L (GE) */
uae_u32 REGPARAM2 op_6cff_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 55;
	CurrentInstrCycles = 8;  
	uaecptr oldpc = m68k_getpci();
	if (cctrue(12)) {
		exception3_read_prefetch(opcode, m68k_getpci() + 1);
		return 2 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	if(regs.t1) opcode |= 0x10000;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8 (1/0) */
/* 2 0,0   */

/* Bcc.W #<data>.W (LT) */
uae_u32 REGPARAM2 op_6d00_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 55;
	CurrentInstrCycles = 12; 
	uaecptr oldpc = m68k_getpci();
	uae_s16 src = regs.irc;
	if (cctrue(13)) {
		if (src & 1) {
			uaecptr addr = m68k_getpci() + (uae_s32)src + 2;
			exception3_read_prefetch(opcode, addr);
			return 2 * CYCLE_UNIT / 2 + count_cycles;
		}
		m68k_incpci((uae_s32)src + 2);
		int pcadjust = oldpc - m68k_getpci() + 2;
		get_word_000_prefetch(0);
		if(hardware_bus_error) {
			int pcoffset = 0;
			pcoffset += pcadjust;
			exception2_fetch_opcode(opcode, 0, pcoffset);
			return 6 * CYCLE_UNIT / 2 + count_cycles;
		}
		regs.ir = regs.irc;
		opcode = regs.ir;
		if(regs.t1) opcode |= 0x10000;
		get_word_000_prefetch(2);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 2, pcoffset);
			return 10 * CYCLE_UNIT / 2 + count_cycles;
		}
		return 10 * CYCLE_UNIT / 2;
	}
	m68k_incpci(4);
	get_word_000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	if(regs.t1) opcode |= 0x10000;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (2/0) */
/* 4 0,0 B */

/* BccQ.B #<data> (LT) */
uae_u32 REGPARAM2 op_6d01_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (uae_s32)(uae_s8)(real_opcode & 255);
	OpcodeFamily = 55;
	CurrentInstrCycles = 8;  
	uaecptr oldpc = m68k_getpci();
	uae_u32 src = srcreg;
	if (cctrue(13)) {
		if (src & 1) {
			uaecptr addr = m68k_getpci() + (uae_s32)src + 2;
			exception3_read_prefetch(opcode, addr);
			return 2 * CYCLE_UNIT / 2 + count_cycles;
		}
		m68k_incpci((uae_s32)src + 2);
		int pcadjust = oldpc - m68k_getpci() + 2;
		get_word_000_prefetch(0);
		if(hardware_bus_error) {
			int pcoffset = 0;
			pcoffset += pcadjust;
			exception2_fetch_opcode(opcode, 0, pcoffset);
			return 6 * CYCLE_UNIT / 2 + count_cycles;
		}
		regs.ir = regs.irc;
		opcode = regs.ir;
		if(regs.t1) opcode |= 0x10000;
		get_word_000_prefetch(2);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 2, pcoffset);
			return 10 * CYCLE_UNIT / 2 + count_cycles;
		}
		return 10 * CYCLE_UNIT / 2;
	}
	m68k_incpci(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	if(regs.t1) opcode |= 0x10000;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8 (1/0) */
/* 2 0,0 B */

/* Bcc.L #<data>.L (LT) */
uae_u32 REGPARAM2 op_6dff_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 55;
	CurrentInstrCycles = 8;  
	uaecptr oldpc = m68k_getpci();
	if (cctrue(13)) {
		exception3_read_prefetch(opcode, m68k_getpci() + 1);
		return 2 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	if(regs.t1) opcode |= 0x10000;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8 (1/0) */
/* 2 0,0   */

/* Bcc.W #<data>.W (GT) */
uae_u32 REGPARAM2 op_6e00_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 55;
	CurrentInstrCycles = 12; 
	uaecptr oldpc = m68k_getpci();
	uae_s16 src = regs.irc;
	if (cctrue(14)) {
		if (src & 1) {
			uaecptr addr = m68k_getpci() + (uae_s32)src + 2;
			exception3_read_prefetch(opcode, addr);
			return 2 * CYCLE_UNIT / 2 + count_cycles;
		}
		m68k_incpci((uae_s32)src + 2);
		int pcadjust = oldpc - m68k_getpci() + 2;
		get_word_000_prefetch(0);
		if(hardware_bus_error) {
			int pcoffset = 0;
			pcoffset += pcadjust;
			exception2_fetch_opcode(opcode, 0, pcoffset);
			return 6 * CYCLE_UNIT / 2 + count_cycles;
		}
		regs.ir = regs.irc;
		opcode = regs.ir;
		if(regs.t1) opcode |= 0x10000;
		get_word_000_prefetch(2);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 2, pcoffset);
			return 10 * CYCLE_UNIT / 2 + count_cycles;
		}
		return 10 * CYCLE_UNIT / 2;
	}
	m68k_incpci(4);
	get_word_000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	if(regs.t1) opcode |= 0x10000;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (2/0) */
/* 4 0,0 B */

/* BccQ.B #<data> (GT) */
uae_u32 REGPARAM2 op_6e01_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (uae_s32)(uae_s8)(real_opcode & 255);
	OpcodeFamily = 55;
	CurrentInstrCycles = 8;  
	uaecptr oldpc = m68k_getpci();
	uae_u32 src = srcreg;
	if (cctrue(14)) {
		if (src & 1) {
			uaecptr addr = m68k_getpci() + (uae_s32)src + 2;
			exception3_read_prefetch(opcode, addr);
			return 2 * CYCLE_UNIT / 2 + count_cycles;
		}
		m68k_incpci((uae_s32)src + 2);
		int pcadjust = oldpc - m68k_getpci() + 2;
		get_word_000_prefetch(0);
		if(hardware_bus_error) {
			int pcoffset = 0;
			pcoffset += pcadjust;
			exception2_fetch_opcode(opcode, 0, pcoffset);
			return 6 * CYCLE_UNIT / 2 + count_cycles;
		}
		regs.ir = regs.irc;
		opcode = regs.ir;
		if(regs.t1) opcode |= 0x10000;
		get_word_000_prefetch(2);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 2, pcoffset);
			return 10 * CYCLE_UNIT / 2 + count_cycles;
		}
		return 10 * CYCLE_UNIT / 2;
	}
	m68k_incpci(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	if(regs.t1) opcode |= 0x10000;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8 (1/0) */
/* 2 0,0 B */

/* Bcc.L #<data>.L (GT) */
uae_u32 REGPARAM2 op_6eff_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 55;
	CurrentInstrCycles = 8;  
	uaecptr oldpc = m68k_getpci();
	if (cctrue(14)) {
		exception3_read_prefetch(opcode, m68k_getpci() + 1);
		return 2 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	if(regs.t1) opcode |= 0x10000;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8 (1/0) */
/* 2 0,0   */

/* Bcc.W #<data>.W (LE) */
uae_u32 REGPARAM2 op_6f00_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 55;
	CurrentInstrCycles = 12; 
	uaecptr oldpc = m68k_getpci();
	uae_s16 src = regs.irc;
	if (cctrue(15)) {
		if (src & 1) {
			uaecptr addr = m68k_getpci() + (uae_s32)src + 2;
			exception3_read_prefetch(opcode, addr);
			return 2 * CYCLE_UNIT / 2 + count_cycles;
		}
		m68k_incpci((uae_s32)src + 2);
		int pcadjust = oldpc - m68k_getpci() + 2;
		get_word_000_prefetch(0);
		if(hardware_bus_error) {
			int pcoffset = 0;
			pcoffset += pcadjust;
			exception2_fetch_opcode(opcode, 0, pcoffset);
			return 6 * CYCLE_UNIT / 2 + count_cycles;
		}
		regs.ir = regs.irc;
		opcode = regs.ir;
		if(regs.t1) opcode |= 0x10000;
		get_word_000_prefetch(2);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 2, pcoffset);
			return 10 * CYCLE_UNIT / 2 + count_cycles;
		}
		return 10 * CYCLE_UNIT / 2;
	}
	m68k_incpci(4);
	get_word_000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	if(regs.t1) opcode |= 0x10000;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (2/0) */
/* 4 0,0 B */

/* BccQ.B #<data> (LE) */
uae_u32 REGPARAM2 op_6f01_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (uae_s32)(uae_s8)(real_opcode & 255);
	OpcodeFamily = 55;
	CurrentInstrCycles = 8;  
	uaecptr oldpc = m68k_getpci();
	uae_u32 src = srcreg;
	if (cctrue(15)) {
		if (src & 1) {
			uaecptr addr = m68k_getpci() + (uae_s32)src + 2;
			exception3_read_prefetch(opcode, addr);
			return 2 * CYCLE_UNIT / 2 + count_cycles;
		}
		m68k_incpci((uae_s32)src + 2);
		int pcadjust = oldpc - m68k_getpci() + 2;
		get_word_000_prefetch(0);
		if(hardware_bus_error) {
			int pcoffset = 0;
			pcoffset += pcadjust;
			exception2_fetch_opcode(opcode, 0, pcoffset);
			return 6 * CYCLE_UNIT / 2 + count_cycles;
		}
		regs.ir = regs.irc;
		opcode = regs.ir;
		if(regs.t1) opcode |= 0x10000;
		get_word_000_prefetch(2);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 2, pcoffset);
			return 10 * CYCLE_UNIT / 2 + count_cycles;
		}
		return 10 * CYCLE_UNIT / 2;
	}
	m68k_incpci(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	if(regs.t1) opcode |= 0x10000;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8 (1/0) */
/* 2 0,0 B */

/* Bcc.L #<data>.L (LE) */
uae_u32 REGPARAM2 op_6fff_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 55;
	CurrentInstrCycles = 8;  
	uaecptr oldpc = m68k_getpci();
	if (cctrue(15)) {
		exception3_read_prefetch(opcode, m68k_getpci() + 1);
		return 2 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	if(regs.t1) opcode |= 0x10000;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8 (1/0) */
/* 2 0,0   */

/* MOVEQ.L #<data>,Dn */
uae_u32 REGPARAM2 op_7000_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (uae_s32)(uae_s8)(real_opcode & 255);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 4;  
	uae_u32 src = srcreg;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	m68k_dreg(regs, dstreg) = (src);
	m68k_incpci(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	return 4 * CYCLE_UNIT / 2 + count_cycles;
}
/* 4 (1/0) */
/* 2 0,0   */

/* OR.B Dn,Dn */
uae_u32 REGPARAM2 op_8000_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 4;  
	uae_s8 src = m68k_dreg(regs, srcreg);
	uae_s8 dst = m68k_dreg(regs, dstreg);
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 4 * CYCLE_UNIT / 2 + count_cycles;
}
/* 4 (1/0) */
/* 2 0,0   */

/* OR.B (An),Dn */
uae_u32 REGPARAM2 op_8010_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 8;  
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = m68k_dreg(regs, dstreg);
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8 (2/0) */
/* 2 0,0   */

/* OR.B (An)+,Dn */
uae_u32 REGPARAM2 op_8018_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 8;  
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
	uae_s8 dst = m68k_dreg(regs, dstreg);
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8 (2/0) */
/* 2 0,0   */

/* OR.B -(An),Dn */
uae_u32 REGPARAM2 op_8020_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 10; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) = srca;
	uae_s8 dst = m68k_dreg(regs, dstreg);
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 10 * CYCLE_UNIT / 2 + count_cycles;
}
/* 10 (2/0) */
/* 2 0,0   */

/* OR.B (d16,An),Dn */
uae_u32 REGPARAM2 op_8028_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = m68k_dreg(regs, dstreg);
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (3/0) */
/* 4 0,0   */

/* OR.B (d8,An,Xn),Dn */
uae_u32 REGPARAM2 op_8030_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	BusCyclePenalty += 2;
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = m68k_dreg(regs, dstreg);
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 14 * CYCLE_UNIT / 2 + count_cycles;
}
/* 14 (3/0) */
/* 4 4,0   */

/* OR.B (xxx).W,Dn */
uae_u32 REGPARAM2 op_8038_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = m68k_dreg(regs, dstreg);
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (3/0) */
/* 4 0,0   */

/* OR.B (xxx).L,Dn */
uae_u32 REGPARAM2 op_8039_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	srca |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = m68k_dreg(regs, dstreg);
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (4/0) */
/* 6 0,0   */

/* OR.B (d16,PC),Dn */
uae_u32 REGPARAM2 op_803a_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_getpci() + 2;
	srca += (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 2);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = m68k_dreg(regs, dstreg);
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (3/0) */
/* 4 0,0   */

/* OR.B (d8,PC,Xn),Dn */
uae_u32 REGPARAM2 op_803b_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	uaecptr tmppc = m68k_getpci() + 2;
	BusCyclePenalty += 2;
	srca = get_disp_ea_000(tmppc, get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 2);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = m68k_dreg(regs, dstreg);
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 14 * CYCLE_UNIT / 2 + count_cycles;
}
/* 14 (3/0) */
/* 4 4,0   */

/* OR.B #<data>.B,Dn */
uae_u32 REGPARAM2 op_803c_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 8;  
	uae_s8 src = (uae_u8)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = m68k_dreg(regs, dstreg);
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8 (2/0) */
/* 4 0,0   */

/* OR.W Dn,Dn */
uae_u32 REGPARAM2 op_8040_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 4;  
	uae_s16 src = m68k_dreg(regs, srcreg);
	uae_s16 dst = m68k_dreg(regs, dstreg);
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 4 * CYCLE_UNIT / 2 + count_cycles;
}
/* 4 (1/0) */
/* 2 0,0   */

/* OR.W (An),Dn */
uae_u32 REGPARAM2 op_8050_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 8;  
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8 (2/0) */
/* 2 0,0   */

/* OR.W (An)+,Dn */
uae_u32 REGPARAM2 op_8058_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 8;  
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) += 2 + 0;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) += 2;
	uae_s16 dst = m68k_dreg(regs, dstreg);
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8 (2/0) */
/* 2 0,0   */

/* OR.W -(An),Dn */
uae_u32 REGPARAM2 op_8060_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 10; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - 2;
	if (srca & 1) {
		m68k_incpci(4);
		m68k_areg(regs, srcreg) = srca;
		exception3_read_access(opcode, srca, 1, 1);
		return 2 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) = srca;
	uae_s16 dst = m68k_dreg(regs, dstreg);
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 10 * CYCLE_UNIT / 2 + count_cycles;
}
/* 10 (2/0) */
/* 2 0,0   */

/* OR.W (d16,An),Dn */
uae_u32 REGPARAM2 op_8068_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (3/0) */
/* 4 0,0   */

/* OR.W (d8,An,Xn),Dn */
uae_u32 REGPARAM2 op_8070_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	BusCyclePenalty += 2;
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 14 * CYCLE_UNIT / 2 + count_cycles;
}
/* 14 (3/0) */
/* 4 4,0   */

/* OR.W (xxx).W,Dn */
uae_u32 REGPARAM2 op_8078_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, srca, 1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (3/0) */
/* 4 0,0   */

/* OR.W (xxx).L,Dn */
uae_u32 REGPARAM2 op_8079_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	srca |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, srca, 1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (4/0) */
/* 6 0,0   */

/* OR.W (d16,PC),Dn */
uae_u32 REGPARAM2 op_807a_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_getpci() + 2;
	srca += (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (3/0) */
/* 4 0,0   */

/* OR.W (d8,PC,Xn),Dn */
uae_u32 REGPARAM2 op_807b_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	uaecptr tmppc = m68k_getpci() + 2;
	BusCyclePenalty += 2;
	srca = get_disp_ea_000(tmppc, get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 14 * CYCLE_UNIT / 2 + count_cycles;
}
/* 14 (3/0) */
/* 4 4,0   */

/* OR.W #<data>.W,Dn */
uae_u32 REGPARAM2 op_807c_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 8;  
	uae_s16 src = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8 (2/0) */
/* 4 0,0   */

/* OR.L Dn,Dn */
uae_u32 REGPARAM2 op_8080_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 8;  
	uae_s32 src = m68k_dreg(regs, srcreg);
	uae_s32 dst = m68k_dreg(regs, dstreg);
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		dreg_68000_long_replace_low(dstreg, src);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	m68k_dreg(regs, dstreg) = (src);
	m68k_incpci(2);
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8 (1/0) */
/* 2 0,0   */

/* OR.L (An),Dn */
uae_u32 REGPARAM2 op_8090_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		dreg_68000_long_replace_low(dstreg, src);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	m68k_dreg(regs, dstreg) = (src);
	m68k_incpci(2);
	return 14 * CYCLE_UNIT / 2 + count_cycles;
}
/* 14 (3/0) */
/* 2 0,0   */

/* OR.L (An)+,Dn */
uae_u32 REGPARAM2 op_8098_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) += 4;
	uae_s32 dst = m68k_dreg(regs, dstreg);
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		dreg_68000_long_replace_low(dstreg, src);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	m68k_dreg(regs, dstreg) = (src);
	m68k_incpci(2);
	return 14 * CYCLE_UNIT / 2 + count_cycles;
}
/* 14 (3/0) */
/* 2 0,0   */

/* OR.L -(An),Dn */
uae_u32 REGPARAM2 op_80a0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - 4;
	if (srca & 1) {
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception3_read_access(opcode, srca, 2, 1);
		return 2 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) = srca;
	uae_s32 dst = m68k_dreg(regs, dstreg);
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		dreg_68000_long_replace_low(dstreg, src);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	m68k_dreg(regs, dstreg) = (src);
	m68k_incpci(2);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/0) */
/* 2 0,0   */

/* OR.L (d16,An),Dn */
uae_u32 REGPARAM2 op_80a8_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		dreg_68000_long_replace_low(dstreg, src);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	m68k_dreg(regs, dstreg) = (src);
	m68k_incpci(4);
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (4/0) */
/* 4 0,0   */

/* OR.L (d8,An,Xn),Dn */
uae_u32 REGPARAM2 op_80b0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	BusCyclePenalty += 2;
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		dreg_68000_long_replace_low(dstreg, src);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	m68k_dreg(regs, dstreg) = (src);
	m68k_incpci(4);
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (4/0) */
/* 4 4,0   */

/* OR.L (xxx).W,Dn */
uae_u32 REGPARAM2 op_80b8_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, srca, 2, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		dreg_68000_long_replace_low(dstreg, src);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	m68k_dreg(regs, dstreg) = (src);
	m68k_incpci(4);
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (4/0) */
/* 4 0,0   */

/* OR.L (xxx).L,Dn */
uae_u32 REGPARAM2 op_80b9_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 22; 
	uaecptr srca;
	srca = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	srca |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, srca, 2, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		dreg_68000_long_replace_low(dstreg, src);
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	m68k_dreg(regs, dstreg) = (src);
	m68k_incpci(6);
	return 22 * CYCLE_UNIT / 2 + count_cycles;
}
/* 22 (5/0) */
/* 6 0,0   */

/* OR.L (d16,PC),Dn */
uae_u32 REGPARAM2 op_80ba_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	srca = m68k_getpci() + 2;
	srca += (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 2);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		dreg_68000_long_replace_low(dstreg, src);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	m68k_dreg(regs, dstreg) = (src);
	m68k_incpci(4);
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (4/0) */
/* 4 0,0   */

/* OR.L (d8,PC,Xn),Dn */
uae_u32 REGPARAM2 op_80bb_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	uaecptr tmppc = m68k_getpci() + 2;
	BusCyclePenalty += 2;
	srca = get_disp_ea_000(tmppc, get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 2);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		dreg_68000_long_replace_low(dstreg, src);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	m68k_dreg(regs, dstreg) = (src);
	m68k_incpci(4);
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (4/0) */
/* 4 4,0   */

/* OR.L #<data>.L,Dn */
uae_u32 REGPARAM2 op_80bc_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 16; 
	uae_s32 src;
	src = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		dreg_68000_long_replace_low(dstreg, src);
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	m68k_dreg(regs, dstreg) = (src);
	m68k_incpci(6);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/0) */
/* 6 0,0   */

/* DIVU.W Dn,Dn */
uae_u32 REGPARAM2 op_80c0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 60;
	CurrentInstrCycles = 4;  
	uae_s16 src = m68k_dreg(regs, srcreg);
	uae_s32 dst = m68k_dreg(regs, dstreg);
	if (src == 0) {
		divbyzero_special(0, dst);
		m68k_incpci(2);
		Exception_cpu(5);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 newv = (uae_u32)dst / (uae_u32)(uae_u16)src;
	uae_u32 rem = (uae_u32)dst % (uae_u32)(uae_u16)src;
	count_cycles += (getDivu68kCycles((uae_u32)dst, (uae_u16)src)) * CYCLE_UNIT / 2;
	if (newv > 0xffff) {
		setdivuflags((uae_u32)dst, (uae_u16)src);
	} else {
		CLEAR_CZNV();
		SET_ZFLG(((uae_s16)(newv)) == 0);
		SET_NFLG(((uae_s16)(newv)) < 0);
		newv = (newv & 0xffff) | ((uae_u32)rem << 16);
		m68k_dreg(regs, dstreg) = (newv);
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 4 * CYCLE_UNIT / 2 + count_cycles;
}
/* 4+ (1/0) */
/* 2 0,0   */

/* DIVU.W (An),Dn */
uae_u32 REGPARAM2 op_80d0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 60;
	CurrentInstrCycles = 8;  
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	if (src == 0) {
		divbyzero_special(0, dst);
		m68k_incpci(2);
		Exception_cpu(5);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 newv = (uae_u32)dst / (uae_u32)(uae_u16)src;
	uae_u32 rem = (uae_u32)dst % (uae_u32)(uae_u16)src;
	count_cycles += (getDivu68kCycles((uae_u32)dst, (uae_u16)src)) * CYCLE_UNIT / 2;
	if (newv > 0xffff) {
		setdivuflags((uae_u32)dst, (uae_u16)src);
	} else {
		CLEAR_CZNV();
		SET_ZFLG(((uae_s16)(newv)) == 0);
		SET_NFLG(((uae_s16)(newv)) < 0);
		newv = (newv & 0xffff) | ((uae_u32)rem << 16);
		m68k_dreg(regs, dstreg) = (newv);
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8+ (2/0) */
/* 2 0,0   */

/* DIVU.W (An)+,Dn */
uae_u32 REGPARAM2 op_80d8_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 60;
	CurrentInstrCycles = 8;  
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) += 2 + 0;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) += 2;
	uae_s32 dst = m68k_dreg(regs, dstreg);
	if (src == 0) {
		divbyzero_special(0, dst);
		m68k_incpci(2);
		Exception_cpu(5);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 newv = (uae_u32)dst / (uae_u32)(uae_u16)src;
	uae_u32 rem = (uae_u32)dst % (uae_u32)(uae_u16)src;
	count_cycles += (getDivu68kCycles((uae_u32)dst, (uae_u16)src)) * CYCLE_UNIT / 2;
	if (newv > 0xffff) {
		setdivuflags((uae_u32)dst, (uae_u16)src);
	} else {
		CLEAR_CZNV();
		SET_ZFLG(((uae_s16)(newv)) == 0);
		SET_NFLG(((uae_s16)(newv)) < 0);
		newv = (newv & 0xffff) | ((uae_u32)rem << 16);
		m68k_dreg(regs, dstreg) = (newv);
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8+ (2/0) */
/* 2 0,0   */

/* DIVU.W -(An),Dn */
uae_u32 REGPARAM2 op_80e0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 60;
	CurrentInstrCycles = 10; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - 2;
	if (srca & 1) {
		m68k_incpci(4);
		m68k_areg(regs, srcreg) = srca;
		exception3_read_access(opcode, srca, 1, 1);
		return 2 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) = srca;
	uae_s32 dst = m68k_dreg(regs, dstreg);
	if (src == 0) {
		divbyzero_special(0, dst);
		m68k_incpci(2);
		Exception_cpu(5);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 newv = (uae_u32)dst / (uae_u32)(uae_u16)src;
	uae_u32 rem = (uae_u32)dst % (uae_u32)(uae_u16)src;
	count_cycles += (getDivu68kCycles((uae_u32)dst, (uae_u16)src)) * CYCLE_UNIT / 2;
	if (newv > 0xffff) {
		setdivuflags((uae_u32)dst, (uae_u16)src);
	} else {
		CLEAR_CZNV();
		SET_ZFLG(((uae_s16)(newv)) == 0);
		SET_NFLG(((uae_s16)(newv)) < 0);
		newv = (newv & 0xffff) | ((uae_u32)rem << 16);
		m68k_dreg(regs, dstreg) = (newv);
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 10 * CYCLE_UNIT / 2 + count_cycles;
}
/* 10+ (2/0) */
/* 2 0,0   */

/* DIVU.W (d16,An),Dn */
uae_u32 REGPARAM2 op_80e8_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 60;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	if (src == 0) {
		divbyzero_special(0, dst);
		m68k_incpci(4);
		Exception_cpu(5);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 newv = (uae_u32)dst / (uae_u32)(uae_u16)src;
	uae_u32 rem = (uae_u32)dst % (uae_u32)(uae_u16)src;
	count_cycles += (getDivu68kCycles((uae_u32)dst, (uae_u16)src)) * CYCLE_UNIT / 2;
	if (newv > 0xffff) {
		setdivuflags((uae_u32)dst, (uae_u16)src);
	} else {
		CLEAR_CZNV();
		SET_ZFLG(((uae_s16)(newv)) == 0);
		SET_NFLG(((uae_s16)(newv)) < 0);
		newv = (newv & 0xffff) | ((uae_u32)rem << 16);
		m68k_dreg(regs, dstreg) = (newv);
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12+ (3/0) */
/* 4 0,0   */

/* DIVU.W (d8,An,Xn),Dn */
uae_u32 REGPARAM2 op_80f0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 60;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	BusCyclePenalty += 2;
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	if (src == 0) {
		divbyzero_special(0, dst);
		m68k_incpci(4);
		Exception_cpu(5);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 newv = (uae_u32)dst / (uae_u32)(uae_u16)src;
	uae_u32 rem = (uae_u32)dst % (uae_u32)(uae_u16)src;
	count_cycles += (getDivu68kCycles((uae_u32)dst, (uae_u16)src)) * CYCLE_UNIT / 2;
	if (newv > 0xffff) {
		setdivuflags((uae_u32)dst, (uae_u16)src);
	} else {
		CLEAR_CZNV();
		SET_ZFLG(((uae_s16)(newv)) == 0);
		SET_NFLG(((uae_s16)(newv)) < 0);
		newv = (newv & 0xffff) | ((uae_u32)rem << 16);
		m68k_dreg(regs, dstreg) = (newv);
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 14 * CYCLE_UNIT / 2 + count_cycles;
}
/* 14+ (3/0) */
/* 4 4,0   */

/* DIVU.W (xxx).W,Dn */
uae_u32 REGPARAM2 op_80f8_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 60;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, srca, 1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	if (src == 0) {
		divbyzero_special(0, dst);
		m68k_incpci(4);
		Exception_cpu(5);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 newv = (uae_u32)dst / (uae_u32)(uae_u16)src;
	uae_u32 rem = (uae_u32)dst % (uae_u32)(uae_u16)src;
	count_cycles += (getDivu68kCycles((uae_u32)dst, (uae_u16)src)) * CYCLE_UNIT / 2;
	if (newv > 0xffff) {
		setdivuflags((uae_u32)dst, (uae_u16)src);
	} else {
		CLEAR_CZNV();
		SET_ZFLG(((uae_s16)(newv)) == 0);
		SET_NFLG(((uae_s16)(newv)) < 0);
		newv = (newv & 0xffff) | ((uae_u32)rem << 16);
		m68k_dreg(regs, dstreg) = (newv);
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12+ (3/0) */
/* 4 0,0   */

/* DIVU.W (xxx).L,Dn */
uae_u32 REGPARAM2 op_80f9_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 60;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	srca |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, srca, 1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	if (src == 0) {
		divbyzero_special(0, dst);
		m68k_incpci(6);
		Exception_cpu(5);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 newv = (uae_u32)dst / (uae_u32)(uae_u16)src;
	uae_u32 rem = (uae_u32)dst % (uae_u32)(uae_u16)src;
	count_cycles += (getDivu68kCycles((uae_u32)dst, (uae_u16)src)) * CYCLE_UNIT / 2;
	if (newv > 0xffff) {
		setdivuflags((uae_u32)dst, (uae_u16)src);
	} else {
		CLEAR_CZNV();
		SET_ZFLG(((uae_s16)(newv)) == 0);
		SET_NFLG(((uae_s16)(newv)) < 0);
		newv = (newv & 0xffff) | ((uae_u32)rem << 16);
		m68k_dreg(regs, dstreg) = (newv);
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16+ (4/0) */
/* 6 0,0   */

/* DIVU.W (d16,PC),Dn */
uae_u32 REGPARAM2 op_80fa_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 60;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_getpci() + 2;
	srca += (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	if (src == 0) {
		divbyzero_special(0, dst);
		m68k_incpci(4);
		Exception_cpu(5);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 newv = (uae_u32)dst / (uae_u32)(uae_u16)src;
	uae_u32 rem = (uae_u32)dst % (uae_u32)(uae_u16)src;
	count_cycles += (getDivu68kCycles((uae_u32)dst, (uae_u16)src)) * CYCLE_UNIT / 2;
	if (newv > 0xffff) {
		setdivuflags((uae_u32)dst, (uae_u16)src);
	} else {
		CLEAR_CZNV();
		SET_ZFLG(((uae_s16)(newv)) == 0);
		SET_NFLG(((uae_s16)(newv)) < 0);
		newv = (newv & 0xffff) | ((uae_u32)rem << 16);
		m68k_dreg(regs, dstreg) = (newv);
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12+ (3/0) */
/* 4 0,0   */

/* DIVU.W (d8,PC,Xn),Dn */
uae_u32 REGPARAM2 op_80fb_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 60;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	uaecptr tmppc = m68k_getpci() + 2;
	BusCyclePenalty += 2;
	srca = get_disp_ea_000(tmppc, get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	if (src == 0) {
		divbyzero_special(0, dst);
		m68k_incpci(4);
		Exception_cpu(5);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 newv = (uae_u32)dst / (uae_u32)(uae_u16)src;
	uae_u32 rem = (uae_u32)dst % (uae_u32)(uae_u16)src;
	count_cycles += (getDivu68kCycles((uae_u32)dst, (uae_u16)src)) * CYCLE_UNIT / 2;
	if (newv > 0xffff) {
		setdivuflags((uae_u32)dst, (uae_u16)src);
	} else {
		CLEAR_CZNV();
		SET_ZFLG(((uae_s16)(newv)) == 0);
		SET_NFLG(((uae_s16)(newv)) < 0);
		newv = (newv & 0xffff) | ((uae_u32)rem << 16);
		m68k_dreg(regs, dstreg) = (newv);
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 14 * CYCLE_UNIT / 2 + count_cycles;
}
/* 14+ (3/0) */
/* 4 4,0   */

/* DIVU.W #<data>.W,Dn */
uae_u32 REGPARAM2 op_80fc_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 60;
	CurrentInstrCycles = 8;  
	uae_s16 src = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	if (src == 0) {
		divbyzero_special(0, dst);
		m68k_incpci(4);
		Exception_cpu(5);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 newv = (uae_u32)dst / (uae_u32)(uae_u16)src;
	uae_u32 rem = (uae_u32)dst % (uae_u32)(uae_u16)src;
	count_cycles += (getDivu68kCycles((uae_u32)dst, (uae_u16)src)) * CYCLE_UNIT / 2;
	if (newv > 0xffff) {
		setdivuflags((uae_u32)dst, (uae_u16)src);
	} else {
		CLEAR_CZNV();
		SET_ZFLG(((uae_s16)(newv)) == 0);
		SET_NFLG(((uae_s16)(newv)) < 0);
		newv = (newv & 0xffff) | ((uae_u32)rem << 16);
		m68k_dreg(regs, dstreg) = (newv);
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8+ (2/0) */
/* 4 0,0   */

/* SBCD.B Dn,Dn */
uae_u32 REGPARAM2 op_8100_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 10;
	CurrentInstrCycles = 6;  
	uae_s8 src = m68k_dreg(regs, srcreg);
	uae_s8 dst = m68k_dreg(regs, dstreg);
	uae_u16 newv_lo = (dst & 0xF) - (src & 0xF) - (GET_XFLG() ? 1 : 0);
	uae_u16 newv_hi = (dst & 0xF0) - (src & 0xF0);
	uae_u16 newv, tmp_newv;
	int bcd = 0;
	newv = tmp_newv = newv_hi + newv_lo;
if (newv_lo & 0xF0) { newv -= 6; bcd = 6; };
if ((((dst & 0xFF) - (src & 0xFF) - (GET_XFLG() ? 1 : 0)) & 0x100) > 0xFF) { newv -= 0x60; }
	SET_CFLG((((dst & 0xFF) - (src & 0xFF) - bcd - (GET_XFLG() ? 1 : 0)) & 0x300) > 0xFF);
	COPY_CARRY();
	SET_ZFLG(GET_ZFLG() & (((uae_s8)(newv)) == 0));
	SET_NFLG(((uae_s8)(newv)) < 0);
	SET_VFLG((tmp_newv & 0x80) != 0 && (newv & 0x80) == 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
	m68k_incpci(2);
	return 6 * CYCLE_UNIT / 2 + count_cycles;
}
/* 6 (1/0) */
/* 2 0,0   */

/* SBCD.B -(An),-(An) */
uae_u32 REGPARAM2 op_8108_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 10;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) = srca;
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, dstreg) = dsta;
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) = dsta;
	uae_u16 newv_lo = (dst & 0xF) - (src & 0xF) - (GET_XFLG() ? 1 : 0);
	uae_u16 newv_hi = (dst & 0xF0) - (src & 0xF0);
	uae_u16 newv, tmp_newv;
	int bcd = 0;
	newv = tmp_newv = newv_hi + newv_lo;
if (newv_lo & 0xF0) { newv -= 6; bcd = 6; };
if ((((dst & 0xFF) - (src & 0xFF) - (GET_XFLG() ? 1 : 0)) & 0x100) > 0xFF) { newv -= 0x60; }
	SET_CFLG((((dst & 0xFF) - (src & 0xFF) - bcd - (GET_XFLG() ? 1 : 0)) & 0x300) > 0xFF);
	COPY_CARRY();
	SET_ZFLG(GET_ZFLG() & (((uae_s8)(newv)) == 0));
	SET_NFLG(((uae_s8)(newv)) < 0);
	SET_VFLG((tmp_newv & 0x80) != 0 && (newv & 0x80) == 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_byte_000(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, newv, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (3/1) */
/* 2 0,0   */

/* OR.B Dn,(An) */
uae_u32 REGPARAM2 op_8110_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 12; 
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_byte_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (2/1) */
/* 2 0,0   */

/* OR.B Dn,(An)+ */
uae_u32 REGPARAM2 op_8118_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 12; 
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_byte_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (2/1) */
/* 2 0,0   */

/* OR.B Dn,-(An) */
uae_u32 REGPARAM2 op_8120_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 14; 
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, dstreg) = dsta;
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) = dsta;
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_byte_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 14 * CYCLE_UNIT / 2 + count_cycles;
}
/* 14 (2/1) */
/* 2 0,0   */

/* OR.B Dn,(d16,An) */
uae_u32 REGPARAM2 op_8128_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 16; 
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_byte_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 4 0,0   */

/* OR.B Dn,(d8,An,Xn) */
uae_u32 REGPARAM2 op_8130_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 18; 
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	BusCyclePenalty += 2;
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_byte_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (3/1) */
/* 4 4,0   */

/* OR.B Dn,(xxx).W */
uae_u32 REGPARAM2 op_8138_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	OpcodeFamily = 1;
	CurrentInstrCycles = 16; 
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_byte_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 4 0,0   */

/* OR.B Dn,(xxx).L */
uae_u32 REGPARAM2 op_8139_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	OpcodeFamily = 1;
	CurrentInstrCycles = 20; 
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	dsta |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_byte_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (4/1) */
/* 6 0,0   */

/* OR.W Dn,(An) */
uae_u32 REGPARAM2 op_8150_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 12; 
	uae_s16 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	if (dsta & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dsta, 1, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = get_word_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_word_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (2/1) */
/* 2 0,0   */

/* OR.W Dn,(An)+ */
uae_u32 REGPARAM2 op_8158_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 12; 
	uae_s16 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	if (dsta & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dsta, 1, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = get_word_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, dstreg) += 2 + 0;
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) += 2;
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_word_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (2/1) */
/* 2 0,0   */

/* OR.W Dn,-(An) */
uae_u32 REGPARAM2 op_8160_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 14; 
	uae_s16 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - 2;
	if (dsta & 1) {
		m68k_incpci(4);
		m68k_areg(regs, dstreg) = dsta;
		exception3_read_access(opcode, dsta, 1, 1);
		return 2 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = get_word_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, dstreg) = dsta;
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) = dsta;
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_word_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 14 * CYCLE_UNIT / 2 + count_cycles;
}
/* 14 (2/1) */
/* 2 0,0   */

/* OR.W Dn,(d16,An) */
uae_u32 REGPARAM2 op_8168_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 16; 
	uae_s16 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dsta, 1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = get_word_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_word_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 4 0,0   */

/* OR.W Dn,(d8,An,Xn) */
uae_u32 REGPARAM2 op_8170_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 18; 
	uae_s16 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	BusCyclePenalty += 2;
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dsta, 1, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = get_word_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_word_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (3/1) */
/* 4 4,0   */

/* OR.W Dn,(xxx).W */
uae_u32 REGPARAM2 op_8178_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	OpcodeFamily = 1;
	CurrentInstrCycles = 16; 
	uae_s16 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, dsta, 1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = get_word_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_word_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 4 0,0   */

/* OR.W Dn,(xxx).L */
uae_u32 REGPARAM2 op_8179_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	OpcodeFamily = 1;
	CurrentInstrCycles = 20; 
	uae_s16 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	dsta |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, dsta, 1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = get_word_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_word_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (4/1) */
/* 6 0,0   */

/* OR.L Dn,(An) */
uae_u32 REGPARAM2 op_8190_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 20; 
	uae_s32 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	if (dsta & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dsta, 2, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = get_word_000(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	dst |= get_word_000(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src >> 16); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (3/2) */
/* 2 0,0   */

/* OR.L Dn,(An)+ */
uae_u32 REGPARAM2 op_8198_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 20; 
	uae_s32 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	if (dsta & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dsta, 2, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = get_word_000(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	dst |= get_word_000(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) += 4;
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src >> 16); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (3/2) */
/* 2 0,0   */

/* OR.L Dn,-(An) */
uae_u32 REGPARAM2 op_81a0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 22; 
	uae_s32 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - 4;
	if (dsta & 1) {
		m68k_incpci(2);
		m68k_areg(regs, dstreg) = dsta;
		exception3_read_access(opcode, dsta, 2, 1);
		return 2 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = get_word_000(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, dstreg) = dsta;
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	dst |= get_word_000(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, dstreg) = dsta;
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) = dsta;
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src >> 16); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return 22 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 22 * CYCLE_UNIT / 2 + count_cycles;
}
/* 22 (3/2) */
/* 2 0,0   */

/* OR.L Dn,(d16,An) */
uae_u32 REGPARAM2 op_81a8_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 24; 
	uae_s32 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dsta, 2, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = get_word_000(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	dst |= get_word_000(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src >> 16); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 24 * CYCLE_UNIT / 2 + count_cycles;
}
/* 24 (4/2) */
/* 4 0,0   */

/* OR.L Dn,(d8,An,Xn) */
uae_u32 REGPARAM2 op_81b0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 26; 
	uae_s32 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	BusCyclePenalty += 2;
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dsta, 2, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = get_word_000(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	dst |= get_word_000(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return 22 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src >> 16); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return 26 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 26 * CYCLE_UNIT / 2 + count_cycles;
}
/* 26 (4/2) */
/* 4 4,0   */

/* OR.L Dn,(xxx).W */
uae_u32 REGPARAM2 op_81b8_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	OpcodeFamily = 1;
	CurrentInstrCycles = 24; 
	uae_s32 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, dsta, 2, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = get_word_000(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	dst |= get_word_000(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src >> 16); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 24 * CYCLE_UNIT / 2 + count_cycles;
}
/* 24 (4/2) */
/* 4 0,0   */

/* OR.L Dn,(xxx).L */
uae_u32 REGPARAM2 op_81b9_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	OpcodeFamily = 1;
	CurrentInstrCycles = 28; 
	uae_s32 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	dsta |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, dsta, 2, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = get_word_000(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	dst |= get_word_000(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src >> 16); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return 28 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 28 * CYCLE_UNIT / 2 + count_cycles;
}
/* 28 (5/2) */
/* 6 0,0   */

/* DIVS.W Dn,Dn */
uae_u32 REGPARAM2 op_81c0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 61;
	CurrentInstrCycles = 4;  
	uae_s16 src = m68k_dreg(regs, srcreg);
	uae_s32 dst = m68k_dreg(regs, dstreg);
	if (src == 0) {
		divbyzero_special(1, dst);
		m68k_incpci(2);
		Exception_cpu(5);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	int extra = 0;
	count_cycles += (getDivs68kCycles((uae_s32)dst, (uae_s16)src, &extra)) * CYCLE_UNIT / 2;
	if (dst == 0x80000000 && src == -1) {
		setdivsflags((uae_s32)dst, (uae_s16)src);
	} else {
		uae_s32 newv = (uae_s32)dst / (uae_s32)(uae_s16)src;
		uae_u16 rem = (uae_s32)dst % (uae_s32)(uae_s16)src;
		if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) {
			setdivsflags((uae_s32)dst, (uae_s16)src);
		} else {
			if (((uae_s16)rem < 0) != ((uae_s32)dst < 0)) rem = -rem;
			CLEAR_CZNV();
			SET_ZFLG(((uae_s16)(newv)) == 0);
			SET_NFLG(((uae_s16)(newv)) < 0);
			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
			m68k_dreg(regs, dstreg) = (newv);
		}
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 4 * CYCLE_UNIT / 2 + count_cycles;
}
/* 4+ (1/0) */
/* 2 0,0   */

/* DIVS.W (An),Dn */
uae_u32 REGPARAM2 op_81d0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 61;
	CurrentInstrCycles = 8;  
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	if (src == 0) {
		divbyzero_special(1, dst);
		m68k_incpci(2);
		Exception_cpu(5);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	int extra = 0;
	count_cycles += (getDivs68kCycles((uae_s32)dst, (uae_s16)src, &extra)) * CYCLE_UNIT / 2;
	if (dst == 0x80000000 && src == -1) {
		setdivsflags((uae_s32)dst, (uae_s16)src);
	} else {
		uae_s32 newv = (uae_s32)dst / (uae_s32)(uae_s16)src;
		uae_u16 rem = (uae_s32)dst % (uae_s32)(uae_s16)src;
		if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) {
			setdivsflags((uae_s32)dst, (uae_s16)src);
		} else {
			if (((uae_s16)rem < 0) != ((uae_s32)dst < 0)) rem = -rem;
			CLEAR_CZNV();
			SET_ZFLG(((uae_s16)(newv)) == 0);
			SET_NFLG(((uae_s16)(newv)) < 0);
			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
			m68k_dreg(regs, dstreg) = (newv);
		}
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8+ (2/0) */
/* 2 0,0   */

/* DIVS.W (An)+,Dn */
uae_u32 REGPARAM2 op_81d8_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 61;
	CurrentInstrCycles = 8;  
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) += 2 + 0;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) += 2;
	uae_s32 dst = m68k_dreg(regs, dstreg);
	if (src == 0) {
		divbyzero_special(1, dst);
		m68k_incpci(2);
		Exception_cpu(5);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	int extra = 0;
	count_cycles += (getDivs68kCycles((uae_s32)dst, (uae_s16)src, &extra)) * CYCLE_UNIT / 2;
	if (dst == 0x80000000 && src == -1) {
		setdivsflags((uae_s32)dst, (uae_s16)src);
	} else {
		uae_s32 newv = (uae_s32)dst / (uae_s32)(uae_s16)src;
		uae_u16 rem = (uae_s32)dst % (uae_s32)(uae_s16)src;
		if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) {
			setdivsflags((uae_s32)dst, (uae_s16)src);
		} else {
			if (((uae_s16)rem < 0) != ((uae_s32)dst < 0)) rem = -rem;
			CLEAR_CZNV();
			SET_ZFLG(((uae_s16)(newv)) == 0);
			SET_NFLG(((uae_s16)(newv)) < 0);
			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
			m68k_dreg(regs, dstreg) = (newv);
		}
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8+ (2/0) */
/* 2 0,0   */

/* DIVS.W -(An),Dn */
uae_u32 REGPARAM2 op_81e0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 61;
	CurrentInstrCycles = 10; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - 2;
	if (srca & 1) {
		m68k_incpci(4);
		m68k_areg(regs, srcreg) = srca;
		exception3_read_access(opcode, srca, 1, 1);
		return 2 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) = srca;
	uae_s32 dst = m68k_dreg(regs, dstreg);
	if (src == 0) {
		divbyzero_special(1, dst);
		m68k_incpci(2);
		Exception_cpu(5);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	int extra = 0;
	count_cycles += (getDivs68kCycles((uae_s32)dst, (uae_s16)src, &extra)) * CYCLE_UNIT / 2;
	if (dst == 0x80000000 && src == -1) {
		setdivsflags((uae_s32)dst, (uae_s16)src);
	} else {
		uae_s32 newv = (uae_s32)dst / (uae_s32)(uae_s16)src;
		uae_u16 rem = (uae_s32)dst % (uae_s32)(uae_s16)src;
		if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) {
			setdivsflags((uae_s32)dst, (uae_s16)src);
		} else {
			if (((uae_s16)rem < 0) != ((uae_s32)dst < 0)) rem = -rem;
			CLEAR_CZNV();
			SET_ZFLG(((uae_s16)(newv)) == 0);
			SET_NFLG(((uae_s16)(newv)) < 0);
			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
			m68k_dreg(regs, dstreg) = (newv);
		}
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 10 * CYCLE_UNIT / 2 + count_cycles;
}
/* 10+ (2/0) */
/* 2 0,0   */

/* DIVS.W (d16,An),Dn */
uae_u32 REGPARAM2 op_81e8_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 61;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	if (src == 0) {
		divbyzero_special(1, dst);
		m68k_incpci(4);
		Exception_cpu(5);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	int extra = 0;
	count_cycles += (getDivs68kCycles((uae_s32)dst, (uae_s16)src, &extra)) * CYCLE_UNIT / 2;
	if (dst == 0x80000000 && src == -1) {
		setdivsflags((uae_s32)dst, (uae_s16)src);
	} else {
		uae_s32 newv = (uae_s32)dst / (uae_s32)(uae_s16)src;
		uae_u16 rem = (uae_s32)dst % (uae_s32)(uae_s16)src;
		if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) {
			setdivsflags((uae_s32)dst, (uae_s16)src);
		} else {
			if (((uae_s16)rem < 0) != ((uae_s32)dst < 0)) rem = -rem;
			CLEAR_CZNV();
			SET_ZFLG(((uae_s16)(newv)) == 0);
			SET_NFLG(((uae_s16)(newv)) < 0);
			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
			m68k_dreg(regs, dstreg) = (newv);
		}
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12+ (3/0) */
/* 4 0,0   */

/* DIVS.W (d8,An,Xn),Dn */
uae_u32 REGPARAM2 op_81f0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 61;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	BusCyclePenalty += 2;
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	if (src == 0) {
		divbyzero_special(1, dst);
		m68k_incpci(4);
		Exception_cpu(5);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	int extra = 0;
	count_cycles += (getDivs68kCycles((uae_s32)dst, (uae_s16)src, &extra)) * CYCLE_UNIT / 2;
	if (dst == 0x80000000 && src == -1) {
		setdivsflags((uae_s32)dst, (uae_s16)src);
	} else {
		uae_s32 newv = (uae_s32)dst / (uae_s32)(uae_s16)src;
		uae_u16 rem = (uae_s32)dst % (uae_s32)(uae_s16)src;
		if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) {
			setdivsflags((uae_s32)dst, (uae_s16)src);
		} else {
			if (((uae_s16)rem < 0) != ((uae_s32)dst < 0)) rem = -rem;
			CLEAR_CZNV();
			SET_ZFLG(((uae_s16)(newv)) == 0);
			SET_NFLG(((uae_s16)(newv)) < 0);
			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
			m68k_dreg(regs, dstreg) = (newv);
		}
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 14 * CYCLE_UNIT / 2 + count_cycles;
}
/* 14+ (3/0) */
/* 4 4,0   */

/* DIVS.W (xxx).W,Dn */
uae_u32 REGPARAM2 op_81f8_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 61;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, srca, 1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	if (src == 0) {
		divbyzero_special(1, dst);
		m68k_incpci(4);
		Exception_cpu(5);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	int extra = 0;
	count_cycles += (getDivs68kCycles((uae_s32)dst, (uae_s16)src, &extra)) * CYCLE_UNIT / 2;
	if (dst == 0x80000000 && src == -1) {
		setdivsflags((uae_s32)dst, (uae_s16)src);
	} else {
		uae_s32 newv = (uae_s32)dst / (uae_s32)(uae_s16)src;
		uae_u16 rem = (uae_s32)dst % (uae_s32)(uae_s16)src;
		if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) {
			setdivsflags((uae_s32)dst, (uae_s16)src);
		} else {
			if (((uae_s16)rem < 0) != ((uae_s32)dst < 0)) rem = -rem;
			CLEAR_CZNV();
			SET_ZFLG(((uae_s16)(newv)) == 0);
			SET_NFLG(((uae_s16)(newv)) < 0);
			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
			m68k_dreg(regs, dstreg) = (newv);
		}
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12+ (3/0) */
/* 4 0,0   */

/* DIVS.W (xxx).L,Dn */
uae_u32 REGPARAM2 op_81f9_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 61;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	srca |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, srca, 1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	if (src == 0) {
		divbyzero_special(1, dst);
		m68k_incpci(6);
		Exception_cpu(5);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	int extra = 0;
	count_cycles += (getDivs68kCycles((uae_s32)dst, (uae_s16)src, &extra)) * CYCLE_UNIT / 2;
	if (dst == 0x80000000 && src == -1) {
		setdivsflags((uae_s32)dst, (uae_s16)src);
	} else {
		uae_s32 newv = (uae_s32)dst / (uae_s32)(uae_s16)src;
		uae_u16 rem = (uae_s32)dst % (uae_s32)(uae_s16)src;
		if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) {
			setdivsflags((uae_s32)dst, (uae_s16)src);
		} else {
			if (((uae_s16)rem < 0) != ((uae_s32)dst < 0)) rem = -rem;
			CLEAR_CZNV();
			SET_ZFLG(((uae_s16)(newv)) == 0);
			SET_NFLG(((uae_s16)(newv)) < 0);
			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
			m68k_dreg(regs, dstreg) = (newv);
		}
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16+ (4/0) */
/* 6 0,0   */

/* DIVS.W (d16,PC),Dn */
uae_u32 REGPARAM2 op_81fa_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 61;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_getpci() + 2;
	srca += (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	if (src == 0) {
		divbyzero_special(1, dst);
		m68k_incpci(4);
		Exception_cpu(5);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	int extra = 0;
	count_cycles += (getDivs68kCycles((uae_s32)dst, (uae_s16)src, &extra)) * CYCLE_UNIT / 2;
	if (dst == 0x80000000 && src == -1) {
		setdivsflags((uae_s32)dst, (uae_s16)src);
	} else {
		uae_s32 newv = (uae_s32)dst / (uae_s32)(uae_s16)src;
		uae_u16 rem = (uae_s32)dst % (uae_s32)(uae_s16)src;
		if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) {
			setdivsflags((uae_s32)dst, (uae_s16)src);
		} else {
			if (((uae_s16)rem < 0) != ((uae_s32)dst < 0)) rem = -rem;
			CLEAR_CZNV();
			SET_ZFLG(((uae_s16)(newv)) == 0);
			SET_NFLG(((uae_s16)(newv)) < 0);
			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
			m68k_dreg(regs, dstreg) = (newv);
		}
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12+ (3/0) */
/* 4 0,0   */

/* DIVS.W (d8,PC,Xn),Dn */
uae_u32 REGPARAM2 op_81fb_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 61;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	uaecptr tmppc = m68k_getpci() + 2;
	BusCyclePenalty += 2;
	srca = get_disp_ea_000(tmppc, get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	if (src == 0) {
		divbyzero_special(1, dst);
		m68k_incpci(4);
		Exception_cpu(5);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	int extra = 0;
	count_cycles += (getDivs68kCycles((uae_s32)dst, (uae_s16)src, &extra)) * CYCLE_UNIT / 2;
	if (dst == 0x80000000 && src == -1) {
		setdivsflags((uae_s32)dst, (uae_s16)src);
	} else {
		uae_s32 newv = (uae_s32)dst / (uae_s32)(uae_s16)src;
		uae_u16 rem = (uae_s32)dst % (uae_s32)(uae_s16)src;
		if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) {
			setdivsflags((uae_s32)dst, (uae_s16)src);
		} else {
			if (((uae_s16)rem < 0) != ((uae_s32)dst < 0)) rem = -rem;
			CLEAR_CZNV();
			SET_ZFLG(((uae_s16)(newv)) == 0);
			SET_NFLG(((uae_s16)(newv)) < 0);
			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
			m68k_dreg(regs, dstreg) = (newv);
		}
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 14 * CYCLE_UNIT / 2 + count_cycles;
}
/* 14+ (3/0) */
/* 4 4,0   */

/* DIVS.W #<data>.W,Dn */
uae_u32 REGPARAM2 op_81fc_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 61;
	CurrentInstrCycles = 8;  
	uae_s16 src = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	if (src == 0) {
		divbyzero_special(1, dst);
		m68k_incpci(4);
		Exception_cpu(5);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	int extra = 0;
	count_cycles += (getDivs68kCycles((uae_s32)dst, (uae_s16)src, &extra)) * CYCLE_UNIT / 2;
	if (dst == 0x80000000 && src == -1) {
		setdivsflags((uae_s32)dst, (uae_s16)src);
	} else {
		uae_s32 newv = (uae_s32)dst / (uae_s32)(uae_s16)src;
		uae_u16 rem = (uae_s32)dst % (uae_s32)(uae_s16)src;
		if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) {
			setdivsflags((uae_s32)dst, (uae_s16)src);
		} else {
			if (((uae_s16)rem < 0) != ((uae_s32)dst < 0)) rem = -rem;
			CLEAR_CZNV();
			SET_ZFLG(((uae_s16)(newv)) == 0);
			SET_NFLG(((uae_s16)(newv)) < 0);
			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
			m68k_dreg(regs, dstreg) = (newv);
		}
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8+ (2/0) */
/* 4 0,0   */

/* SUB.B Dn,Dn */
uae_u32 REGPARAM2 op_9000_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 4;  
	uae_s8 src = m68k_dreg(regs, srcreg);
	uae_s8 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 4 * CYCLE_UNIT / 2 + count_cycles;
}
/* 4 (1/0) */
/* 2 0,0   */

/* SUB.B (An),Dn */
uae_u32 REGPARAM2 op_9010_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 8;  
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8 (2/0) */
/* 2 0,0   */

/* SUB.B (An)+,Dn */
uae_u32 REGPARAM2 op_9018_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 8;  
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
	uae_s8 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8 (2/0) */
/* 2 0,0   */

/* SUB.B -(An),Dn */
uae_u32 REGPARAM2 op_9020_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 10; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) = srca;
	uae_s8 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 10 * CYCLE_UNIT / 2 + count_cycles;
}
/* 10 (2/0) */
/* 2 0,0   */

/* SUB.B (d16,An),Dn */
uae_u32 REGPARAM2 op_9028_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (3/0) */
/* 4 0,0   */

/* SUB.B (d8,An,Xn),Dn */
uae_u32 REGPARAM2 op_9030_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	BusCyclePenalty += 2;
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 14 * CYCLE_UNIT / 2 + count_cycles;
}
/* 14 (3/0) */
/* 4 4,0   */

/* SUB.B (xxx).W,Dn */
uae_u32 REGPARAM2 op_9038_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (3/0) */
/* 4 0,0   */

/* SUB.B (xxx).L,Dn */
uae_u32 REGPARAM2 op_9039_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	srca |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (4/0) */
/* 6 0,0   */

/* SUB.B (d16,PC),Dn */
uae_u32 REGPARAM2 op_903a_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_getpci() + 2;
	srca += (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 2);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (3/0) */
/* 4 0,0   */

/* SUB.B (d8,PC,Xn),Dn */
uae_u32 REGPARAM2 op_903b_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	uaecptr tmppc = m68k_getpci() + 2;
	BusCyclePenalty += 2;
	srca = get_disp_ea_000(tmppc, get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 2);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 14 * CYCLE_UNIT / 2 + count_cycles;
}
/* 14 (3/0) */
/* 4 4,0   */

/* SUB.B #<data>.B,Dn */
uae_u32 REGPARAM2 op_903c_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 8;  
	uae_s8 src = (uae_u8)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8 (2/0) */
/* 4 0,0   */

/* SUB.W Dn,Dn */
uae_u32 REGPARAM2 op_9040_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 4;  
	uae_s16 src = m68k_dreg(regs, srcreg);
	uae_s16 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 4 * CYCLE_UNIT / 2 + count_cycles;
}
/* 4 (1/0) */
/* 2 0,0   */

/* SUB.W An,Dn */
uae_u32 REGPARAM2 op_9048_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 4;  
	uae_s16 src = m68k_areg(regs, srcreg);
	uae_s16 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 4 * CYCLE_UNIT / 2 + count_cycles;
}
/* 4 (1/0) */
/* 2 0,0   */

/* SUB.W (An),Dn */
uae_u32 REGPARAM2 op_9050_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 8;  
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8 (2/0) */
/* 2 0,0   */

/* SUB.W (An)+,Dn */
uae_u32 REGPARAM2 op_9058_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 8;  
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) += 2 + 0;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) += 2;
	uae_s16 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8 (2/0) */
/* 2 0,0   */

/* SUB.W -(An),Dn */
uae_u32 REGPARAM2 op_9060_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 10; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - 2;
	if (srca & 1) {
		m68k_incpci(4);
		m68k_areg(regs, srcreg) = srca;
		exception3_read_access(opcode, srca, 1, 1);
		return 2 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) = srca;
	uae_s16 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 10 * CYCLE_UNIT / 2 + count_cycles;
}
/* 10 (2/0) */
/* 2 0,0   */

/* SUB.W (d16,An),Dn */
uae_u32 REGPARAM2 op_9068_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (3/0) */
/* 4 0,0   */

/* SUB.W (d8,An,Xn),Dn */
uae_u32 REGPARAM2 op_9070_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	BusCyclePenalty += 2;
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 14 * CYCLE_UNIT / 2 + count_cycles;
}
/* 14 (3/0) */
/* 4 4,0   */

/* SUB.W (xxx).W,Dn */
uae_u32 REGPARAM2 op_9078_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, srca, 1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (3/0) */
/* 4 0,0   */

/* SUB.W (xxx).L,Dn */
uae_u32 REGPARAM2 op_9079_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	srca |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, srca, 1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (4/0) */
/* 6 0,0   */

/* SUB.W (d16,PC),Dn */
uae_u32 REGPARAM2 op_907a_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_getpci() + 2;
	srca += (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (3/0) */
/* 4 0,0   */

/* SUB.W (d8,PC,Xn),Dn */
uae_u32 REGPARAM2 op_907b_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	uaecptr tmppc = m68k_getpci() + 2;
	BusCyclePenalty += 2;
	srca = get_disp_ea_000(tmppc, get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 14 * CYCLE_UNIT / 2 + count_cycles;
}
/* 14 (3/0) */
/* 4 4,0   */

/* SUB.W #<data>.W,Dn */
uae_u32 REGPARAM2 op_907c_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 8;  
	uae_s16 src = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8 (2/0) */
/* 4 0,0   */

/* SUB.L Dn,Dn */
uae_u32 REGPARAM2 op_9080_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 8;  
	uae_s32 src = m68k_dreg(regs, srcreg);
	uae_s32 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		uae_s16 bnewv = (uae_s16)dst - (uae_s16)src;
		int bflgs = ((uae_s16)(src)) < 0;
		int bflgo = ((uae_s16)(dst)) < 0;
		int bflgn = bnewv < 0;
		ccr_68000_long_move_ae_LZN(bnewv);
		SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
		SET_XFLG(GET_CFLG());
		SET_VFLG((bflgs ^ bflgo) & (bflgn ^ bflgo));
		dreg_68000_long_replace_low(dstreg, bnewv);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	m68k_dreg(regs, dstreg) = (newv);
	m68k_incpci(2);
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8 (1/0) */
/* 2 0,0   */

/* SUB.L An,Dn */
uae_u32 REGPARAM2 op_9088_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 8;  
	uae_s32 src = m68k_areg(regs, srcreg);
	uae_s32 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		uae_s16 bnewv = (uae_s16)dst - (uae_s16)src;
		int bflgs = ((uae_s16)(src)) < 0;
		int bflgo = ((uae_s16)(dst)) < 0;
		int bflgn = bnewv < 0;
		ccr_68000_long_move_ae_LZN(bnewv);
		SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
		SET_XFLG(GET_CFLG());
		SET_VFLG((bflgs ^ bflgo) & (bflgn ^ bflgo));
		dreg_68000_long_replace_low(dstreg, bnewv);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	m68k_dreg(regs, dstreg) = (newv);
	m68k_incpci(2);
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8 (1/0) */
/* 2 0,0   */

/* SUB.L (An),Dn */
uae_u32 REGPARAM2 op_9090_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		dreg_68000_long_replace_low(dstreg, newv);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	m68k_dreg(regs, dstreg) = (newv);
	m68k_incpci(2);
	return 14 * CYCLE_UNIT / 2 + count_cycles;
}
/* 14 (3/0) */
/* 2 0,0   */

/* SUB.L (An)+,Dn */
uae_u32 REGPARAM2 op_9098_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) += 4;
	uae_s32 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		dreg_68000_long_replace_low(dstreg, newv);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	m68k_dreg(regs, dstreg) = (newv);
	m68k_incpci(2);
	return 14 * CYCLE_UNIT / 2 + count_cycles;
}
/* 14 (3/0) */
/* 2 0,0   */

/* SUB.L -(An),Dn */
uae_u32 REGPARAM2 op_90a0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - 4;
	if (srca & 1) {
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception3_read_access(opcode, srca, 2, 1);
		return 2 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) = srca;
	uae_s32 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		dreg_68000_long_replace_low(dstreg, newv);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	m68k_dreg(regs, dstreg) = (newv);
	m68k_incpci(2);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/0) */
/* 2 0,0   */

/* SUB.L (d16,An),Dn */
uae_u32 REGPARAM2 op_90a8_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		dreg_68000_long_replace_low(dstreg, newv);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	m68k_dreg(regs, dstreg) = (newv);
	m68k_incpci(4);
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (4/0) */
/* 4 0,0   */

/* SUB.L (d8,An,Xn),Dn */
uae_u32 REGPARAM2 op_90b0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	BusCyclePenalty += 2;
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		dreg_68000_long_replace_low(dstreg, newv);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	m68k_dreg(regs, dstreg) = (newv);
	m68k_incpci(4);
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (4/0) */
/* 4 4,0   */

/* SUB.L (xxx).W,Dn */
uae_u32 REGPARAM2 op_90b8_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, srca, 2, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		dreg_68000_long_replace_low(dstreg, newv);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	m68k_dreg(regs, dstreg) = (newv);
	m68k_incpci(4);
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (4/0) */
/* 4 0,0   */

/* SUB.L (xxx).L,Dn */
uae_u32 REGPARAM2 op_90b9_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 22; 
	uaecptr srca;
	srca = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	srca |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, srca, 2, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		dreg_68000_long_replace_low(dstreg, newv);
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	m68k_dreg(regs, dstreg) = (newv);
	m68k_incpci(6);
	return 22 * CYCLE_UNIT / 2 + count_cycles;
}
/* 22 (5/0) */
/* 6 0,0   */

/* SUB.L (d16,PC),Dn */
uae_u32 REGPARAM2 op_90ba_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	srca = m68k_getpci() + 2;
	srca += (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 2);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		dreg_68000_long_replace_low(dstreg, newv);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	m68k_dreg(regs, dstreg) = (newv);
	m68k_incpci(4);
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (4/0) */
/* 4 0,0   */

/* SUB.L (d8,PC,Xn),Dn */
uae_u32 REGPARAM2 op_90bb_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	uaecptr tmppc = m68k_getpci() + 2;
	BusCyclePenalty += 2;
	srca = get_disp_ea_000(tmppc, get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 2);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		dreg_68000_long_replace_low(dstreg, newv);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	m68k_dreg(regs, dstreg) = (newv);
	m68k_incpci(4);
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (4/0) */
/* 4 4,0   */

/* SUB.L #<data>.L,Dn */
uae_u32 REGPARAM2 op_90bc_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 16; 
	uae_s32 src;
	src = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		uae_s16 bnewv = (uae_s16)dst - (uae_s16)src;
		int bflgs = ((uae_s16)(src)) < 0;
		int bflgo = ((uae_s16)(dst)) < 0;
		int bflgn = bnewv < 0;
		ccr_68000_long_move_ae_LZN(bnewv);
		SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
		SET_XFLG(GET_CFLG());
		SET_VFLG((bflgs ^ bflgo) & (bflgn ^ bflgo));
		dreg_68000_long_replace_low(dstreg, bnewv);
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	m68k_dreg(regs, dstreg) = (newv);
	m68k_incpci(6);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/0) */
/* 6 0,0   */

/* SUBA.W Dn,An */
uae_u32 REGPARAM2 op_90c0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 8;
	CurrentInstrCycles = 8;  
	uae_s16 src = m68k_dreg(regs, srcreg);
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = dst - src;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		areg_68000_long_replace_low(dstreg, newv);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) = (newv);
	m68k_incpci(2);
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8 (1/0) */
/* 2 0,0   */

/* SUBA.W An,An */
uae_u32 REGPARAM2 op_90c8_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 8;
	CurrentInstrCycles = 8;  
	uae_s16 src = m68k_areg(regs, srcreg);
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = dst - src;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		areg_68000_long_replace_low(dstreg, newv);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) = (newv);
	m68k_incpci(2);
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8 (1/0) */
/* 2 0,0   */

/* SUBA.W (An),An */
uae_u32 REGPARAM2 op_90d0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 8;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = dst - src;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		areg_68000_long_replace_low(dstreg, newv);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) = (newv);
	m68k_incpci(2);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (2/0) */
/* 2 0,0   */

/* SUBA.W (An)+,An */
uae_u32 REGPARAM2 op_90d8_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 8;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) += 2 + 0;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) += 2;
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = dst - src;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		areg_68000_long_replace_low(dstreg, newv);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) = (newv);
	m68k_incpci(2);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (2/0) */
/* 2 0,0   */

/* SUBA.W -(An),An */
uae_u32 REGPARAM2 op_90e0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 8;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - 2;
	if (srca & 1) {
		m68k_incpci(4);
		m68k_areg(regs, srcreg) = srca;
		exception3_read_access(opcode, srca, 1, 1);
		return 2 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) = srca;
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = dst - src;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		areg_68000_long_replace_low(dstreg, newv);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) = (newv);
	m68k_incpci(2);
	return 14 * CYCLE_UNIT / 2 + count_cycles;
}
/* 14 (2/0) */
/* 2 0,0   */

/* SUBA.W (d16,An),An */
uae_u32 REGPARAM2 op_90e8_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 8;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = dst - src;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		areg_68000_long_replace_low(dstreg, newv);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) = (newv);
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/0) */
/* 4 0,0   */

/* SUBA.W (d8,An,Xn),An */
uae_u32 REGPARAM2 op_90f0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 8;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	BusCyclePenalty += 2;
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = dst - src;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		areg_68000_long_replace_low(dstreg, newv);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) = (newv);
	m68k_incpci(4);
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (3/0) */
/* 4 4,0   */

/* SUBA.W (xxx).W,An */
uae_u32 REGPARAM2 op_90f8_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 8;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, srca, 1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = dst - src;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		areg_68000_long_replace_low(dstreg, newv);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) = (newv);
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/0) */
/* 4 0,0   */

/* SUBA.W (xxx).L,An */
uae_u32 REGPARAM2 op_90f9_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 8;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	srca = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	srca |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, srca, 1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = dst - src;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		areg_68000_long_replace_low(dstreg, newv);
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) = (newv);
	m68k_incpci(6);
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (4/0) */
/* 6 0,0   */

/* SUBA.W (d16,PC),An */
uae_u32 REGPARAM2 op_90fa_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 8;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = m68k_getpci() + 2;
	srca += (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = dst - src;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		areg_68000_long_replace_low(dstreg, newv);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) = (newv);
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/0) */
/* 4 0,0   */

/* SUBA.W (d8,PC,Xn),An */
uae_u32 REGPARAM2 op_90fb_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 8;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	uaecptr tmppc = m68k_getpci() + 2;
	BusCyclePenalty += 2;
	srca = get_disp_ea_000(tmppc, get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = dst - src;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		areg_68000_long_replace_low(dstreg, newv);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) = (newv);
	m68k_incpci(4);
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (3/0) */
/* 4 4,0   */

/* SUBA.W #<data>.W,An */
uae_u32 REGPARAM2 op_90fc_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 8;
	CurrentInstrCycles = 12; 
	uae_s16 src = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = dst - src;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		areg_68000_long_replace_low(dstreg, newv);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) = (newv);
	m68k_incpci(4);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (2/0) */
/* 4 0,0   */

/* SUBX.B Dn,Dn */
uae_u32 REGPARAM2 op_9100_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 9;
	CurrentInstrCycles = 4;  
	uae_s8 src = m68k_dreg(regs, srcreg);
	uae_s8 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = dst - src - (GET_XFLG() ? 1 : 0);
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_VFLG((flgs ^ flgo) & (flgo ^ flgn));
	SET_CFLG(flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
	COPY_CARRY();
	SET_ZFLG(GET_ZFLG() & (((uae_s8)(newv)) == 0));
	SET_NFLG(((uae_s8)(newv)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
	m68k_incpci(2);
	return 4 * CYCLE_UNIT / 2 + count_cycles;
}
/* 4 (1/0) */
/* 2 0,0   */

/* SUBX.B -(An),-(An) */
uae_u32 REGPARAM2 op_9108_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 9;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) = srca;
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, dstreg) = dsta;
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) = dsta;
	uae_u32 newv = dst - src - (GET_XFLG() ? 1 : 0);
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_VFLG((flgs ^ flgo) & (flgo ^ flgn));
	SET_CFLG(flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
	COPY_CARRY();
	SET_ZFLG(GET_ZFLG() & (((uae_s8)(newv)) == 0));
	SET_NFLG(((uae_s8)(newv)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_byte_000(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, newv, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (3/1) */
/* 2 0,0   */

/* SUB.B Dn,(An) */
uae_u32 REGPARAM2 op_9110_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 12; 
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_byte_000(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, newv, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (2/1) */
/* 2 0,0   */

/* SUB.B Dn,(An)+ */
uae_u32 REGPARAM2 op_9118_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 12; 
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
	uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_byte_000(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, newv, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (2/1) */
/* 2 0,0   */

/* SUB.B Dn,-(An) */
uae_u32 REGPARAM2 op_9120_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 14; 
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, dstreg) = dsta;
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) = dsta;
	uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_byte_000(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, newv, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 14 * CYCLE_UNIT / 2 + count_cycles;
}
/* 14 (2/1) */
/* 2 0,0   */

/* SUB.B Dn,(d16,An) */
uae_u32 REGPARAM2 op_9128_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 16; 
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_byte_000(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, newv, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 4 0,0   */

/* SUB.B Dn,(d8,An,Xn) */
uae_u32 REGPARAM2 op_9130_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 18; 
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	BusCyclePenalty += 2;
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_byte_000(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, newv, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (3/1) */
/* 4 4,0   */

/* SUB.B Dn,(xxx).W */
uae_u32 REGPARAM2 op_9138_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	OpcodeFamily = 7;
	CurrentInstrCycles = 16; 
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_byte_000(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, newv, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 4 0,0   */

/* SUB.B Dn,(xxx).L */
uae_u32 REGPARAM2 op_9139_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	OpcodeFamily = 7;
	CurrentInstrCycles = 20; 
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	dsta |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_byte_000(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, newv, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (4/1) */
/* 6 0,0   */

/* SUBX.W Dn,Dn */
uae_u32 REGPARAM2 op_9140_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 9;
	CurrentInstrCycles = 4;  
	uae_s16 src = m68k_dreg(regs, srcreg);
	uae_s16 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = dst - src - (GET_XFLG() ? 1 : 0);
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_VFLG((flgs ^ flgo) & (flgo ^ flgn));
	SET_CFLG(flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
	COPY_CARRY();
	SET_ZFLG(GET_ZFLG() & (((uae_s16)(newv)) == 0));
	SET_NFLG(((uae_s16)(newv)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
	m68k_incpci(2);
	return 4 * CYCLE_UNIT / 2 + count_cycles;
}
/* 4 (1/0) */
/* 2 0,0   */

/* SUBX.W -(An),-(An) */
uae_u32 REGPARAM2 op_9148_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 9;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - 2;
	if (srca & 1) {
		m68k_areg(regs, srcreg) = srca;
		m68k_incpci(4);
		exception3_read_access(opcode, srca, 1, 1);
		return 2 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) = srca;
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - 2;
	if (dsta & 1) {
		m68k_areg(regs, dstreg) = dsta;
		m68k_incpci(4);
		exception3_read_access(opcode, dsta, 1, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = get_word_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, dstreg) = dsta;
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) = dsta;
	uae_u32 newv = dst - src - (GET_XFLG() ? 1 : 0);
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_VFLG((flgs ^ flgo) & (flgo ^ flgn));
	SET_CFLG(flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
	COPY_CARRY();
	SET_ZFLG(GET_ZFLG() & (((uae_s16)(newv)) == 0));
	SET_NFLG(((uae_s16)(newv)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_word_000(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x1, newv, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (3/1) */
/* 2 0,0   */

/* SUB.W Dn,(An) */
uae_u32 REGPARAM2 op_9150_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 12; 
	uae_s16 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	if (dsta & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dsta, 1, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = get_word_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_word_000(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x1, newv, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (2/1) */
/* 2 0,0   */

/* SUB.W Dn,(An)+ */
uae_u32 REGPARAM2 op_9158_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 12; 
	uae_s16 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	if (dsta & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dsta, 1, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = get_word_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, dstreg) += 2 + 0;
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) += 2;
	uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_word_000(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x1, newv, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (2/1) */
/* 2 0,0   */

/* SUB.W Dn,-(An) */
uae_u32 REGPARAM2 op_9160_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 14; 
	uae_s16 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - 2;
	if (dsta & 1) {
		m68k_incpci(4);
		m68k_areg(regs, dstreg) = dsta;
		exception3_read_access(opcode, dsta, 1, 1);
		return 2 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = get_word_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, dstreg) = dsta;
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) = dsta;
	uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_word_000(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x1, newv, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 14 * CYCLE_UNIT / 2 + count_cycles;
}
/* 14 (2/1) */
/* 2 0,0   */

/* SUB.W Dn,(d16,An) */
uae_u32 REGPARAM2 op_9168_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 16; 
	uae_s16 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dsta, 1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = get_word_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_word_000(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x1, newv, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 4 0,0   */

/* SUB.W Dn,(d8,An,Xn) */
uae_u32 REGPARAM2 op_9170_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 18; 
	uae_s16 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	BusCyclePenalty += 2;
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dsta, 1, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = get_word_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_word_000(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x1, newv, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (3/1) */
/* 4 4,0   */

/* SUB.W Dn,(xxx).W */
uae_u32 REGPARAM2 op_9178_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	OpcodeFamily = 7;
	CurrentInstrCycles = 16; 
	uae_s16 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, dsta, 1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = get_word_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_word_000(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x1, newv, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 4 0,0   */

/* SUB.W Dn,(xxx).L */
uae_u32 REGPARAM2 op_9179_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	OpcodeFamily = 7;
	CurrentInstrCycles = 20; 
	uae_s16 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	dsta |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, dsta, 1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = get_word_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_word_000(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x1, newv, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (4/1) */
/* 6 0,0   */

/* SUBX.L Dn,Dn */
uae_u32 REGPARAM2 op_9180_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 9;
	CurrentInstrCycles = 8;  
	uae_s32 src = m68k_dreg(regs, srcreg);
	uae_s32 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = dst - src - (GET_XFLG() ? 1 : 0);
	int oldz = GET_ZFLG();
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_VFLG((flgs ^ flgo) & (flgo ^ flgn));
	SET_CFLG(flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
	COPY_CARRY();
	SET_ZFLG(GET_ZFLG() & (((uae_s32)(newv)) == 0));
	SET_NFLG(((uae_s32)(newv)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		int bflgs = ((uae_s16)(src)) < 0;
		int bflgo = ((uae_s16)(dst)) < 0;
		int bflgn = ((uae_s16)(newv)) < 0;
		SET_VFLG((bflgs ^ bflgo) & (bflgo ^ bflgn));
		SET_CFLG(bflgs ^ ((bflgs ^ bflgn) & (bflgo ^ bflgn)));
		SET_XFLG(GET_CFLG());
		SET_ZFLG(oldz);
		if (newv & 0xffff) SET_ZFLG(0);
		SET_NFLG(newv & 0x8000); 
		dreg_68000_long_replace_low(dstreg, newv);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	m68k_dreg(regs, dstreg) = (newv);
	m68k_incpci(2);
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8 (1/0) */
/* 2 0,0   */

/* SUBX.L -(An),-(An) */
uae_u32 REGPARAM2 op_9188_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 9;
	CurrentInstrCycles = 30; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - 4;
	if (srca & 1) {
		m68k_incpci(4);
		srca += 2;
		exception3_read_access(opcode, srca, 2, 1);
		return 2 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) = srca;
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - 4;
	if (dsta & 1) {
		m68k_incpci(4);
		dsta += 2;
		exception3_read_access(opcode, dsta, 2, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = get_word_000(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	dst |= get_word_000(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) = dsta;
	uae_u32 newv = dst - src - (GET_XFLG() ? 1 : 0);
	int oldz = GET_ZFLG();
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_VFLG((flgs ^ flgo) & (flgo ^ flgn));
	SET_CFLG(flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
	COPY_CARRY();
	SET_ZFLG(GET_ZFLG() & (((uae_s32)(newv)) == 0));
	SET_NFLG(((uae_s32)(newv)) < 0);
	put_word_000(dsta + 2, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		int bflgs = ((uae_s16)(src)) < 0;
		int bflgo = ((uae_s16)(dst)) < 0;
		int bflgn = ((uae_s16)(newv)) < 0;
		SET_VFLG((bflgs ^ bflgo) & (bflgo ^ bflgn));
		SET_CFLG(bflgs ^ ((bflgs ^ bflgn) & (bflgo ^ bflgn)));
		COPY_CARRY();
		SET_ZFLG(GET_ZFLG() & (((uae_s16)(newv)) == 0));
		SET_NFLG(((uae_s16)(newv)) < 0);
		exception2_write(opcode, dsta + 2, 0x1, newv, 1);
		return 22 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 26 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, newv >> 16); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x1, newv >> 16, 1);
		return 30 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 30 * CYCLE_UNIT / 2 + count_cycles;
}
/* 30 (5/2) */
/* 2 0,0   */

/* SUB.L Dn,(An) */
uae_u32 REGPARAM2 op_9190_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 20; 
	uae_s32 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	if (dsta & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dsta, 2, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = get_word_000(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	dst |= get_word_000(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		uae_s16 bnewv = (uae_s16)dst - (uae_s16)src;
		int bflgs = ((uae_s16)(src)) < 0;
		int bflgo = ((uae_s16)(dst)) < 0;
		int bflgn = bnewv < 0;
		ccr_68000_long_move_ae_LZN(bnewv);
		SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
		SET_XFLG(GET_CFLG());
		SET_VFLG((bflgs ^ bflgo) & (bflgn ^ bflgo));
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta + 2, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 2, 0x1, newv, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, newv >> 16); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x1, newv >> 16, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (3/2) */
/* 2 0,0   */

/* SUB.L Dn,(An)+ */
uae_u32 REGPARAM2 op_9198_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 20; 
	uae_s32 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	if (dsta & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dsta, 2, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = get_word_000(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	dst |= get_word_000(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) += 4;
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		uae_s16 bnewv = (uae_s16)dst - (uae_s16)src;
		int bflgs = ((uae_s16)(src)) < 0;
		int bflgo = ((uae_s16)(dst)) < 0;
		int bflgn = bnewv < 0;
		ccr_68000_long_move_ae_LZN(bnewv);
		SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
		SET_XFLG(GET_CFLG());
		SET_VFLG((bflgs ^ bflgo) & (bflgn ^ bflgo));
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta + 2, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 2, 0x1, newv, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, newv >> 16); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x1, newv >> 16, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (3/2) */
/* 2 0,0   */

/* SUB.L Dn,-(An) */
uae_u32 REGPARAM2 op_91a0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 22; 
	uae_s32 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - 4;
	if (dsta & 1) {
		m68k_incpci(2);
		m68k_areg(regs, dstreg) = dsta;
		exception3_read_access(opcode, dsta, 2, 1);
		return 2 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = get_word_000(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, dstreg) = dsta;
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	dst |= get_word_000(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, dstreg) = dsta;
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) = dsta;
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		uae_s16 bnewv = (uae_s16)dst - (uae_s16)src;
		int bflgs = ((uae_s16)(src)) < 0;
		int bflgo = ((uae_s16)(dst)) < 0;
		int bflgn = bnewv < 0;
		ccr_68000_long_move_ae_LZN(bnewv);
		SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
		SET_XFLG(GET_CFLG());
		SET_VFLG((bflgs ^ bflgo) & (bflgn ^ bflgo));
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta + 2, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 2, 0x1, newv, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, newv >> 16); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x1, newv >> 16, 1);
		return 22 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 22 * CYCLE_UNIT / 2 + count_cycles;
}
/* 22 (3/2) */
/* 2 0,0   */

/* SUB.L Dn,(d16,An) */
uae_u32 REGPARAM2 op_91a8_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 24; 
	uae_s32 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dsta, 2, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = get_word_000(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	dst |= get_word_000(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		uae_s16 bnewv = (uae_s16)dst - (uae_s16)src;
		int bflgs = ((uae_s16)(src)) < 0;
		int bflgo = ((uae_s16)(dst)) < 0;
		int bflgn = bnewv < 0;
		ccr_68000_long_move_ae_LZN(bnewv);
		SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
		SET_XFLG(GET_CFLG());
		SET_VFLG((bflgs ^ bflgo) & (bflgn ^ bflgo));
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta + 2, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 2, 0x1, newv, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, newv >> 16); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, newv >> 16, 1);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 24 * CYCLE_UNIT / 2 + count_cycles;
}
/* 24 (4/2) */
/* 4 0,0   */

/* SUB.L Dn,(d8,An,Xn) */
uae_u32 REGPARAM2 op_91b0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 26; 
	uae_s32 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	BusCyclePenalty += 2;
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dsta, 2, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = get_word_000(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	dst |= get_word_000(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		uae_s16 bnewv = (uae_s16)dst - (uae_s16)src;
		int bflgs = ((uae_s16)(src)) < 0;
		int bflgo = ((uae_s16)(dst)) < 0;
		int bflgn = bnewv < 0;
		ccr_68000_long_move_ae_LZN(bnewv);
		SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
		SET_XFLG(GET_CFLG());
		SET_VFLG((bflgs ^ bflgo) & (bflgn ^ bflgo));
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta + 2, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 2, 0x1, newv, 1);
		return 22 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, newv >> 16); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, newv >> 16, 1);
		return 26 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 26 * CYCLE_UNIT / 2 + count_cycles;
}
/* 26 (4/2) */
/* 4 4,0   */

/* SUB.L Dn,(xxx).W */
uae_u32 REGPARAM2 op_91b8_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	OpcodeFamily = 7;
	CurrentInstrCycles = 24; 
	uae_s32 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, dsta, 2, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = get_word_000(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	dst |= get_word_000(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		uae_s16 bnewv = (uae_s16)dst - (uae_s16)src;
		int bflgs = ((uae_s16)(src)) < 0;
		int bflgo = ((uae_s16)(dst)) < 0;
		int bflgn = bnewv < 0;
		ccr_68000_long_move_ae_LZN(bnewv);
		SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
		SET_XFLG(GET_CFLG());
		SET_VFLG((bflgs ^ bflgo) & (bflgn ^ bflgo));
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta + 2, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 2, 0x1, newv, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, newv >> 16); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, newv >> 16, 1);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 24 * CYCLE_UNIT / 2 + count_cycles;
}
/* 24 (4/2) */
/* 4 0,0   */

/* SUB.L Dn,(xxx).L */
uae_u32 REGPARAM2 op_91b9_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	OpcodeFamily = 7;
	CurrentInstrCycles = 28; 
	uae_s32 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	dsta |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, dsta, 2, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = get_word_000(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	dst |= get_word_000(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		uae_s16 bnewv = (uae_s16)dst - (uae_s16)src;
		int bflgs = ((uae_s16)(src)) < 0;
		int bflgo = ((uae_s16)(dst)) < 0;
		int bflgn = bnewv < 0;
		ccr_68000_long_move_ae_LZN(bnewv);
		SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
		SET_XFLG(GET_CFLG());
		SET_VFLG((bflgs ^ bflgo) & (bflgn ^ bflgo));
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta + 2, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 2, 0x1, newv, 1);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, newv >> 16); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 0, 0x1, newv >> 16, 1);
		return 28 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 28 * CYCLE_UNIT / 2 + count_cycles;
}
/* 28 (5/2) */
/* 6 0,0   */

/* SUBA.L Dn,An */
uae_u32 REGPARAM2 op_91c0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 8;
	CurrentInstrCycles = 8;  
	uae_s32 src = m68k_dreg(regs, srcreg);
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = dst - src;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		areg_68000_long_replace_low(dstreg, newv);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) = (newv);
	m68k_incpci(2);
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8 (1/0) */
/* 2 0,0   */

/* SUBA.L An,An */
uae_u32 REGPARAM2 op_91c8_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 8;
	CurrentInstrCycles = 8;  
	uae_s32 src = m68k_areg(regs, srcreg);
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = dst - src;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		areg_68000_long_replace_low(dstreg, newv);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) = (newv);
	m68k_incpci(2);
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8 (1/0) */
/* 2 0,0   */

/* SUBA.L (An),An */
uae_u32 REGPARAM2 op_91d0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 8;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = dst - src;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		areg_68000_long_replace_low(dstreg, newv);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) = (newv);
	m68k_incpci(2);
	return 14 * CYCLE_UNIT / 2 + count_cycles;
}
/* 14 (3/0) */
/* 2 0,0   */

/* SUBA.L (An)+,An */
uae_u32 REGPARAM2 op_91d8_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 8;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) += 4;
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = dst - src;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		areg_68000_long_replace_low(dstreg, newv);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) = (newv);
	m68k_incpci(2);
	return 14 * CYCLE_UNIT / 2 + count_cycles;
}
/* 14 (3/0) */
/* 2 0,0   */

/* SUBA.L -(An),An */
uae_u32 REGPARAM2 op_91e0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 8;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - 4;
	if (srca & 1) {
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception3_read_access(opcode, srca, 2, 1);
		return 2 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) = srca;
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = dst - src;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		areg_68000_long_replace_low(dstreg, newv);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) = (newv);
	m68k_incpci(2);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/0) */
/* 2 0,0   */

/* SUBA.L (d16,An),An */
uae_u32 REGPARAM2 op_91e8_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 8;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = dst - src;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		areg_68000_long_replace_low(dstreg, newv);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) = (newv);
	m68k_incpci(4);
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (4/0) */
/* 4 0,0   */

/* SUBA.L (d8,An,Xn),An */
uae_u32 REGPARAM2 op_91f0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 8;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	BusCyclePenalty += 2;
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = dst - src;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		areg_68000_long_replace_low(dstreg, newv);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) = (newv);
	m68k_incpci(4);
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (4/0) */
/* 4 4,0   */

/* SUBA.L (xxx).W,An */
uae_u32 REGPARAM2 op_91f8_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 8;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, srca, 2, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = dst - src;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		areg_68000_long_replace_low(dstreg, newv);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) = (newv);
	m68k_incpci(4);
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (4/0) */
/* 4 0,0   */

/* SUBA.L (xxx).L,An */
uae_u32 REGPARAM2 op_91f9_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 8;
	CurrentInstrCycles = 22; 
	uaecptr srca;
	srca = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	srca |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, srca, 2, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = dst - src;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		areg_68000_long_replace_low(dstreg, newv);
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) = (newv);
	m68k_incpci(6);
	return 22 * CYCLE_UNIT / 2 + count_cycles;
}
/* 22 (5/0) */
/* 6 0,0   */

/* SUBA.L (d16,PC),An */
uae_u32 REGPARAM2 op_91fa_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 8;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	srca = m68k_getpci() + 2;
	srca += (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 2);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = dst - src;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		areg_68000_long_replace_low(dstreg, newv);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) = (newv);
	m68k_incpci(4);
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (4/0) */
/* 4 0,0   */

/* SUBA.L (d8,PC,Xn),An */
uae_u32 REGPARAM2 op_91fb_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 8;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	uaecptr tmppc = m68k_getpci() + 2;
	BusCyclePenalty += 2;
	srca = get_disp_ea_000(tmppc, get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 2);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = dst - src;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		areg_68000_long_replace_low(dstreg, newv);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) = (newv);
	m68k_incpci(4);
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (4/0) */
/* 4 4,0   */

/* SUBA.L #<data>.L,An */
uae_u32 REGPARAM2 op_91fc_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 8;
	CurrentInstrCycles = 16; 
	uae_s32 src;
	src = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = dst - src;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		areg_68000_long_replace_low(dstreg, newv);
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) = (newv);
	m68k_incpci(6);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/0) */
/* 6 0,0   */

/* CMP.B Dn,Dn */
uae_u32 REGPARAM2 op_b000_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 25;
	CurrentInstrCycles = 4;  
	uae_s8 src = m68k_dreg(regs, srcreg);
	uae_s8 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 4 * CYCLE_UNIT / 2 + count_cycles;
}
/* 4 (1/0) */
/* 2 0,0   */

/* CMP.B (An),Dn */
uae_u32 REGPARAM2 op_b010_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 25;
	CurrentInstrCycles = 8;  
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8 (2/0) */
/* 2 0,0   */

/* CMP.B (An)+,Dn */
uae_u32 REGPARAM2 op_b018_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 25;
	CurrentInstrCycles = 8;  
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
	uae_s8 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8 (2/0) */
/* 2 0,0   */

/* CMP.B -(An),Dn */
uae_u32 REGPARAM2 op_b020_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 25;
	CurrentInstrCycles = 10; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) = srca;
	uae_s8 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 10 * CYCLE_UNIT / 2 + count_cycles;
}
/* 10 (2/0) */
/* 2 0,0   */

/* CMP.B (d16,An),Dn */
uae_u32 REGPARAM2 op_b028_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 25;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (3/0) */
/* 4 0,0   */

/* CMP.B (d8,An,Xn),Dn */
uae_u32 REGPARAM2 op_b030_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 25;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	BusCyclePenalty += 2;
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 14 * CYCLE_UNIT / 2 + count_cycles;
}
/* 14 (3/0) */
/* 4 4,0   */

/* CMP.B (xxx).W,Dn */
uae_u32 REGPARAM2 op_b038_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 25;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (3/0) */
/* 4 0,0   */

/* CMP.B (xxx).L,Dn */
uae_u32 REGPARAM2 op_b039_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 25;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	srca |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (4/0) */
/* 6 0,0   */

/* CMP.B (d16,PC),Dn */
uae_u32 REGPARAM2 op_b03a_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 25;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_getpci() + 2;
	srca += (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 2);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (3/0) */
/* 4 0,0   */

/* CMP.B (d8,PC,Xn),Dn */
uae_u32 REGPARAM2 op_b03b_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 25;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	uaecptr tmppc = m68k_getpci() + 2;
	BusCyclePenalty += 2;
	srca = get_disp_ea_000(tmppc, get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 2);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 14 * CYCLE_UNIT / 2 + count_cycles;
}
/* 14 (3/0) */
/* 4 4,0   */

/* CMP.B #<data>.B,Dn */
uae_u32 REGPARAM2 op_b03c_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 25;
	CurrentInstrCycles = 8;  
	uae_s8 src = (uae_u8)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8 (2/0) */
/* 4 0,0   */

/* CMP.W Dn,Dn */
uae_u32 REGPARAM2 op_b040_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 25;
	CurrentInstrCycles = 4;  
	uae_s16 src = m68k_dreg(regs, srcreg);
	uae_s16 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 4 * CYCLE_UNIT / 2 + count_cycles;
}
/* 4 (1/0) */
/* 2 0,0   */

/* CMP.W An,Dn */
uae_u32 REGPARAM2 op_b048_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 25;
	CurrentInstrCycles = 4;  
	uae_s16 src = m68k_areg(regs, srcreg);
	uae_s16 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 4 * CYCLE_UNIT / 2 + count_cycles;
}
/* 4 (1/0) */
/* 2 0,0   */

/* CMP.W (An),Dn */
uae_u32 REGPARAM2 op_b050_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 25;
	CurrentInstrCycles = 8;  
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8 (2/0) */
/* 2 0,0   */

/* CMP.W (An)+,Dn */
uae_u32 REGPARAM2 op_b058_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 25;
	CurrentInstrCycles = 8;  
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) += 2 + 0;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) += 2;
	uae_s16 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8 (2/0) */
/* 2 0,0   */

/* CMP.W -(An),Dn */
uae_u32 REGPARAM2 op_b060_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 25;
	CurrentInstrCycles = 10; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - 2;
	if (srca & 1) {
		m68k_incpci(4);
		m68k_areg(regs, srcreg) = srca;
		exception3_read_access(opcode, srca, 1, 1);
		return 2 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) = srca;
	uae_s16 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 10 * CYCLE_UNIT / 2 + count_cycles;
}
/* 10 (2/0) */
/* 2 0,0   */

/* CMP.W (d16,An),Dn */
uae_u32 REGPARAM2 op_b068_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 25;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (3/0) */
/* 4 0,0   */

/* CMP.W (d8,An,Xn),Dn */
uae_u32 REGPARAM2 op_b070_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 25;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	BusCyclePenalty += 2;
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 14 * CYCLE_UNIT / 2 + count_cycles;
}
/* 14 (3/0) */
/* 4 4,0   */

/* CMP.W (xxx).W,Dn */
uae_u32 REGPARAM2 op_b078_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 25;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, srca, 1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (3/0) */
/* 4 0,0   */

/* CMP.W (xxx).L,Dn */
uae_u32 REGPARAM2 op_b079_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 25;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	srca |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, srca, 1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (4/0) */
/* 6 0,0   */

/* CMP.W (d16,PC),Dn */
uae_u32 REGPARAM2 op_b07a_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 25;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_getpci() + 2;
	srca += (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (3/0) */
/* 4 0,0   */

/* CMP.W (d8,PC,Xn),Dn */
uae_u32 REGPARAM2 op_b07b_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 25;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	uaecptr tmppc = m68k_getpci() + 2;
	BusCyclePenalty += 2;
	srca = get_disp_ea_000(tmppc, get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 14 * CYCLE_UNIT / 2 + count_cycles;
}
/* 14 (3/0) */
/* 4 4,0   */

/* CMP.W #<data>.W,Dn */
uae_u32 REGPARAM2 op_b07c_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 25;
	CurrentInstrCycles = 8;  
	uae_s16 src = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8 (2/0) */
/* 4 0,0   */

/* CMP.L Dn,Dn */
uae_u32 REGPARAM2 op_b080_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 25;
	CurrentInstrCycles = 6;  
	uae_s32 src = m68k_dreg(regs, srcreg);
	uae_s32 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	m68k_incpci(2);
	return 6 * CYCLE_UNIT / 2 + count_cycles;
}
/* 6 (1/0) */
/* 2 0,0   */

/* CMP.L An,Dn */
uae_u32 REGPARAM2 op_b088_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 25;
	CurrentInstrCycles = 6;  
	uae_s32 src = m68k_areg(regs, srcreg);
	uae_s32 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	m68k_incpci(2);
	return 6 * CYCLE_UNIT / 2 + count_cycles;
}
/* 6 (1/0) */
/* 2 0,0   */

/* CMP.L (An),Dn */
uae_u32 REGPARAM2 op_b090_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 25;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	m68k_incpci(2);
	return 14 * CYCLE_UNIT / 2 + count_cycles;
}
/* 14 (3/0) */
/* 2 0,0   */

/* CMP.L (An)+,Dn */
uae_u32 REGPARAM2 op_b098_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 25;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) += 4;
	uae_s32 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	m68k_incpci(2);
	return 14 * CYCLE_UNIT / 2 + count_cycles;
}
/* 14 (3/0) */
/* 2 0,0   */

/* CMP.L -(An),Dn */
uae_u32 REGPARAM2 op_b0a0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 25;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - 4;
	if (srca & 1) {
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception3_read_access(opcode, srca, 2, 1);
		return 2 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) = srca;
	uae_s32 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	m68k_incpci(2);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/0) */
/* 2 0,0   */

/* CMP.L (d16,An),Dn */
uae_u32 REGPARAM2 op_b0a8_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 25;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	m68k_incpci(4);
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (4/0) */
/* 4 0,0   */

/* CMP.L (d8,An,Xn),Dn */
uae_u32 REGPARAM2 op_b0b0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 25;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	BusCyclePenalty += 2;
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	m68k_incpci(4);
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (4/0) */
/* 4 4,0   */

/* CMP.L (xxx).W,Dn */
uae_u32 REGPARAM2 op_b0b8_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 25;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, srca, 2, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	m68k_incpci(4);
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (4/0) */
/* 4 0,0   */

/* CMP.L (xxx).L,Dn */
uae_u32 REGPARAM2 op_b0b9_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 25;
	CurrentInstrCycles = 22; 
	uaecptr srca;
	srca = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	srca |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, srca, 2, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	m68k_incpci(6);
	return 22 * CYCLE_UNIT / 2 + count_cycles;
}
/* 22 (5/0) */
/* 6 0,0   */

/* CMP.L (d16,PC),Dn */
uae_u32 REGPARAM2 op_b0ba_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 25;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	srca = m68k_getpci() + 2;
	srca += (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 2);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	m68k_incpci(4);
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (4/0) */
/* 4 0,0   */

/* CMP.L (d8,PC,Xn),Dn */
uae_u32 REGPARAM2 op_b0bb_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 25;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	uaecptr tmppc = m68k_getpci() + 2;
	BusCyclePenalty += 2;
	srca = get_disp_ea_000(tmppc, get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 2);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	m68k_incpci(4);
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (4/0) */
/* 4 4,0   */

/* CMP.L #<data>.L,Dn */
uae_u32 REGPARAM2 op_b0bc_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 25;
	CurrentInstrCycles = 14; 
	uae_s32 src;
	src = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	m68k_incpci(6);
	return 14 * CYCLE_UNIT / 2 + count_cycles;
}
/* 14 (3/0) */
/* 6 0,0   */

/* CMPA.W Dn,An */
uae_u32 REGPARAM2 op_b0c0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 27;
	CurrentInstrCycles = 6;  
	uae_s16 src = m68k_dreg(regs, srcreg);
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	m68k_incpci(2);
	return 6 * CYCLE_UNIT / 2 + count_cycles;
}
/* 6 (1/0) */
/* 2 0,0   */

/* CMPA.W An,An */
uae_u32 REGPARAM2 op_b0c8_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 27;
	CurrentInstrCycles = 6;  
	uae_s16 src = m68k_areg(regs, srcreg);
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	m68k_incpci(2);
	return 6 * CYCLE_UNIT / 2 + count_cycles;
}
/* 6 (1/0) */
/* 2 0,0   */

/* CMPA.W (An),An */
uae_u32 REGPARAM2 op_b0d0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 27;
	CurrentInstrCycles = 10; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	m68k_incpci(2);
	return 10 * CYCLE_UNIT / 2 + count_cycles;
}
/* 10 (2/0) */
/* 2 0,0   */

/* CMPA.W (An)+,An */
uae_u32 REGPARAM2 op_b0d8_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 27;
	CurrentInstrCycles = 10; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) += 2 + 0;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) += 2;
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	m68k_incpci(2);
	return 10 * CYCLE_UNIT / 2 + count_cycles;
}
/* 10 (2/0) */
/* 2 0,0   */

/* CMPA.W -(An),An */
uae_u32 REGPARAM2 op_b0e0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 27;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - 2;
	if (srca & 1) {
		m68k_incpci(4);
		m68k_areg(regs, srcreg) = srca;
		exception3_read_access(opcode, srca, 1, 1);
		return 2 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) = srca;
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	m68k_incpci(2);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (2/0) */
/* 2 0,0   */

/* CMPA.W (d16,An),An */
uae_u32 REGPARAM2 op_b0e8_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 27;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	m68k_incpci(4);
	return 14 * CYCLE_UNIT / 2 + count_cycles;
}
/* 14 (3/0) */
/* 4 0,0   */

/* CMPA.W (d8,An,Xn),An */
uae_u32 REGPARAM2 op_b0f0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 27;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	BusCyclePenalty += 2;
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/0) */
/* 4 4,0   */

/* CMPA.W (xxx).W,An */
uae_u32 REGPARAM2 op_b0f8_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 27;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, srca, 1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	m68k_incpci(4);
	return 14 * CYCLE_UNIT / 2 + count_cycles;
}
/* 14 (3/0) */
/* 4 0,0   */

/* CMPA.W (xxx).L,An */
uae_u32 REGPARAM2 op_b0f9_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 27;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	srca = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	srca |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, srca, 1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	m68k_incpci(6);
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (4/0) */
/* 6 0,0   */

/* CMPA.W (d16,PC),An */
uae_u32 REGPARAM2 op_b0fa_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 27;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	srca = m68k_getpci() + 2;
	srca += (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	m68k_incpci(4);
	return 14 * CYCLE_UNIT / 2 + count_cycles;
}
/* 14 (3/0) */
/* 4 0,0   */

/* CMPA.W (d8,PC,Xn),An */
uae_u32 REGPARAM2 op_b0fb_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 27;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	uaecptr tmppc = m68k_getpci() + 2;
	BusCyclePenalty += 2;
	srca = get_disp_ea_000(tmppc, get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/0) */
/* 4 4,0   */

/* CMPA.W #<data>.W,An */
uae_u32 REGPARAM2 op_b0fc_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 27;
	CurrentInstrCycles = 10; 
	uae_s16 src = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	m68k_incpci(4);
	return 10 * CYCLE_UNIT / 2 + count_cycles;
}
/* 10 (2/0) */
/* 4 0,0   */

/* EOR.B Dn,Dn */
uae_u32 REGPARAM2 op_b100_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 3;
	CurrentInstrCycles = 4;  
	uae_s8 src = m68k_dreg(regs, srcreg);
	uae_s8 dst = m68k_dreg(regs, dstreg);
	src ^= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 4 * CYCLE_UNIT / 2 + count_cycles;
}
/* 4 (1/0) */
/* 2 0,0   */

/* CMPM.B (An)+,(An)+ */
uae_u32 REGPARAM2 op_b108_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 26;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, srcreg) += areg_byteinc[srcreg] + 0;
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
	uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (3/0) */
/* 2 0,0   */

/* EOR.B Dn,(An) */
uae_u32 REGPARAM2 op_b110_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 3;
	CurrentInstrCycles = 12; 
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	src ^= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_byte_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (2/1) */
/* 2 0,0   */

/* EOR.B Dn,(An)+ */
uae_u32 REGPARAM2 op_b118_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 3;
	CurrentInstrCycles = 12; 
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
	src ^= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_byte_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (2/1) */
/* 2 0,0   */

/* EOR.B Dn,-(An) */
uae_u32 REGPARAM2 op_b120_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 3;
	CurrentInstrCycles = 14; 
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, dstreg) = dsta;
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) = dsta;
	src ^= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_byte_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 14 * CYCLE_UNIT / 2 + count_cycles;
}
/* 14 (2/1) */
/* 2 0,0   */

/* EOR.B Dn,(d16,An) */
uae_u32 REGPARAM2 op_b128_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 3;
	CurrentInstrCycles = 16; 
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	src ^= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_byte_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 4 0,0   */

/* EOR.B Dn,(d8,An,Xn) */
uae_u32 REGPARAM2 op_b130_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 3;
	CurrentInstrCycles = 18; 
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	BusCyclePenalty += 2;
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	src ^= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_byte_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (3/1) */
/* 4 4,0   */

/* EOR.B Dn,(xxx).W */
uae_u32 REGPARAM2 op_b138_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	OpcodeFamily = 3;
	CurrentInstrCycles = 16; 
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	src ^= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_byte_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 4 0,0   */

/* EOR.B Dn,(xxx).L */
uae_u32 REGPARAM2 op_b139_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	OpcodeFamily = 3;
	CurrentInstrCycles = 20; 
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	dsta |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	src ^= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_byte_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (4/1) */
/* 6 0,0   */

/* EOR.W Dn,Dn */
uae_u32 REGPARAM2 op_b140_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 3;
	CurrentInstrCycles = 4;  
	uae_s16 src = m68k_dreg(regs, srcreg);
	uae_s16 dst = m68k_dreg(regs, dstreg);
	src ^= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 4 * CYCLE_UNIT / 2 + count_cycles;
}
/* 4 (1/0) */
/* 2 0,0   */

/* CMPM.W (An)+,(An)+ */
uae_u32 REGPARAM2 op_b148_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 26;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, srca, 1, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, srcreg) += 2 + 0;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) += 2;
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	if (dsta & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, dsta, 1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = get_word_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, dstreg) += 2 + 0;
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) += 2;
	uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (3/0) */
/* 2 0,0   */

/* EOR.W Dn,(An) */
uae_u32 REGPARAM2 op_b150_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 3;
	CurrentInstrCycles = 12; 
	uae_s16 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	if (dsta & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dsta, 1, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = get_word_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	src ^= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_word_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (2/1) */
/* 2 0,0   */

/* EOR.W Dn,(An)+ */
uae_u32 REGPARAM2 op_b158_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 3;
	CurrentInstrCycles = 12; 
	uae_s16 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	if (dsta & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dsta, 1, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = get_word_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, dstreg) += 2 + 0;
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) += 2;
	src ^= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_word_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (2/1) */
/* 2 0,0   */

/* EOR.W Dn,-(An) */
uae_u32 REGPARAM2 op_b160_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 3;
	CurrentInstrCycles = 14; 
	uae_s16 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - 2;
	if (dsta & 1) {
		m68k_incpci(4);
		m68k_areg(regs, dstreg) = dsta;
		exception3_read_access(opcode, dsta, 1, 1);
		return 2 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = get_word_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, dstreg) = dsta;
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) = dsta;
	src ^= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_word_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 14 * CYCLE_UNIT / 2 + count_cycles;
}
/* 14 (2/1) */
/* 2 0,0   */

/* EOR.W Dn,(d16,An) */
uae_u32 REGPARAM2 op_b168_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 3;
	CurrentInstrCycles = 16; 
	uae_s16 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dsta, 1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = get_word_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	src ^= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_word_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 4 0,0   */

/* EOR.W Dn,(d8,An,Xn) */
uae_u32 REGPARAM2 op_b170_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 3;
	CurrentInstrCycles = 18; 
	uae_s16 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	BusCyclePenalty += 2;
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dsta, 1, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = get_word_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	src ^= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_word_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (3/1) */
/* 4 4,0   */

/* EOR.W Dn,(xxx).W */
uae_u32 REGPARAM2 op_b178_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	OpcodeFamily = 3;
	CurrentInstrCycles = 16; 
	uae_s16 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, dsta, 1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = get_word_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	src ^= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_word_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 4 0,0   */

/* EOR.W Dn,(xxx).L */
uae_u32 REGPARAM2 op_b179_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	OpcodeFamily = 3;
	CurrentInstrCycles = 20; 
	uae_s16 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	dsta |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, dsta, 1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = get_word_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	src ^= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_word_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (4/1) */
/* 6 0,0   */

/* EOR.L Dn,Dn */
uae_u32 REGPARAM2 op_b180_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 3;
	CurrentInstrCycles = 8;  
	uae_s32 src = m68k_dreg(regs, srcreg);
	uae_s32 dst = m68k_dreg(regs, dstreg);
	src ^= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		dreg_68000_long_replace_low(dstreg, src);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	m68k_dreg(regs, dstreg) = (src);
	m68k_incpci(2);
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8 (1/0) */
/* 2 0,0   */

/* CMPM.L (An)+,(An)+ */
uae_u32 REGPARAM2 op_b188_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 26;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, srca, 2, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, srcreg) += 2 + 0;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, srcreg) += 2 + 2;
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) += 4;
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	if (dsta & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, dsta, 2, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = get_word_000(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	dst |= get_word_000(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) += 4;
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (5/0) */
/* 2 0,0   */

/* EOR.L Dn,(An) */
uae_u32 REGPARAM2 op_b190_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 3;
	CurrentInstrCycles = 20; 
	uae_s32 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	if (dsta & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dsta, 2, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = get_word_000(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	dst |= get_word_000(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	src ^= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src >> 16); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (3/2) */
/* 2 0,0   */

/* EOR.L Dn,(An)+ */
uae_u32 REGPARAM2 op_b198_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 3;
	CurrentInstrCycles = 20; 
	uae_s32 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	if (dsta & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dsta, 2, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = get_word_000(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	dst |= get_word_000(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) += 4;
	src ^= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src >> 16); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (3/2) */
/* 2 0,0   */

/* EOR.L Dn,-(An) */
uae_u32 REGPARAM2 op_b1a0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 3;
	CurrentInstrCycles = 22; 
	uae_s32 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - 4;
	if (dsta & 1) {
		m68k_incpci(2);
		m68k_areg(regs, dstreg) = dsta;
		exception3_read_access(opcode, dsta, 2, 1);
		return 2 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = get_word_000(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, dstreg) = dsta;
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	dst |= get_word_000(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, dstreg) = dsta;
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) = dsta;
	src ^= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src >> 16); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return 22 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 22 * CYCLE_UNIT / 2 + count_cycles;
}
/* 22 (3/2) */
/* 2 0,0   */

/* EOR.L Dn,(d16,An) */
uae_u32 REGPARAM2 op_b1a8_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 3;
	CurrentInstrCycles = 24; 
	uae_s32 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dsta, 2, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = get_word_000(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	dst |= get_word_000(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	src ^= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src >> 16); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 24 * CYCLE_UNIT / 2 + count_cycles;
}
/* 24 (4/2) */
/* 4 0,0   */

/* EOR.L Dn,(d8,An,Xn) */
uae_u32 REGPARAM2 op_b1b0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 3;
	CurrentInstrCycles = 26; 
	uae_s32 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	BusCyclePenalty += 2;
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dsta, 2, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = get_word_000(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	dst |= get_word_000(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	src ^= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return 22 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src >> 16); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return 26 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 26 * CYCLE_UNIT / 2 + count_cycles;
}
/* 26 (4/2) */
/* 4 4,0   */

/* EOR.L Dn,(xxx).W */
uae_u32 REGPARAM2 op_b1b8_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	OpcodeFamily = 3;
	CurrentInstrCycles = 24; 
	uae_s32 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, dsta, 2, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = get_word_000(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	dst |= get_word_000(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	src ^= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src >> 16); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 24 * CYCLE_UNIT / 2 + count_cycles;
}
/* 24 (4/2) */
/* 4 0,0   */

/* EOR.L Dn,(xxx).L */
uae_u32 REGPARAM2 op_b1b9_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	OpcodeFamily = 3;
	CurrentInstrCycles = 28; 
	uae_s32 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	dsta |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, dsta, 2, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = get_word_000(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	dst |= get_word_000(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	src ^= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src >> 16); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return 28 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 28 * CYCLE_UNIT / 2 + count_cycles;
}
/* 28 (5/2) */
/* 6 0,0   */

/* CMPA.L Dn,An */
uae_u32 REGPARAM2 op_b1c0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 27;
	CurrentInstrCycles = 6;  
	uae_s32 src = m68k_dreg(regs, srcreg);
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	m68k_incpci(2);
	return 6 * CYCLE_UNIT / 2 + count_cycles;
}
/* 6 (1/0) */
/* 2 0,0   */

/* CMPA.L An,An */
uae_u32 REGPARAM2 op_b1c8_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 27;
	CurrentInstrCycles = 6;  
	uae_s32 src = m68k_areg(regs, srcreg);
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	m68k_incpci(2);
	return 6 * CYCLE_UNIT / 2 + count_cycles;
}
/* 6 (1/0) */
/* 2 0,0   */

/* CMPA.L (An),An */
uae_u32 REGPARAM2 op_b1d0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 27;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	m68k_incpci(2);
	return 14 * CYCLE_UNIT / 2 + count_cycles;
}
/* 14 (3/0) */
/* 2 0,0   */

/* CMPA.L (An)+,An */
uae_u32 REGPARAM2 op_b1d8_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 27;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) += 4;
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	m68k_incpci(2);
	return 14 * CYCLE_UNIT / 2 + count_cycles;
}
/* 14 (3/0) */
/* 2 0,0   */

/* CMPA.L -(An),An */
uae_u32 REGPARAM2 op_b1e0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 27;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - 4;
	if (srca & 1) {
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception3_read_access(opcode, srca, 2, 1);
		return 2 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) = srca;
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	m68k_incpci(2);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/0) */
/* 2 0,0   */

/* CMPA.L (d16,An),An */
uae_u32 REGPARAM2 op_b1e8_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 27;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	m68k_incpci(4);
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (4/0) */
/* 4 0,0   */

/* CMPA.L (d8,An,Xn),An */
uae_u32 REGPARAM2 op_b1f0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 27;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	BusCyclePenalty += 2;
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	m68k_incpci(4);
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (4/0) */
/* 4 4,0   */

/* CMPA.L (xxx).W,An */
uae_u32 REGPARAM2 op_b1f8_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 27;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, srca, 2, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	m68k_incpci(4);
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (4/0) */
/* 4 0,0   */

/* CMPA.L (xxx).L,An */
uae_u32 REGPARAM2 op_b1f9_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 27;
	CurrentInstrCycles = 22; 
	uaecptr srca;
	srca = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	srca |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, srca, 2, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	m68k_incpci(6);
	return 22 * CYCLE_UNIT / 2 + count_cycles;
}
/* 22 (5/0) */
/* 6 0,0   */

/* CMPA.L (d16,PC),An */
uae_u32 REGPARAM2 op_b1fa_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 27;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	srca = m68k_getpci() + 2;
	srca += (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 2);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	m68k_incpci(4);
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (4/0) */
/* 4 0,0   */

/* CMPA.L (d8,PC,Xn),An */
uae_u32 REGPARAM2 op_b1fb_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 27;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	uaecptr tmppc = m68k_getpci() + 2;
	BusCyclePenalty += 2;
	srca = get_disp_ea_000(tmppc, get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 2);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	m68k_incpci(4);
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (4/0) */
/* 4 4,0   */

/* CMPA.L #<data>.L,An */
uae_u32 REGPARAM2 op_b1fc_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 27;
	CurrentInstrCycles = 14; 
	uae_s32 src;
	src = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	m68k_incpci(6);
	return 14 * CYCLE_UNIT / 2 + count_cycles;
}
/* 14 (3/0) */
/* 6 0,0   */

/* AND.B Dn,Dn */
uae_u32 REGPARAM2 op_c000_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 4;  
	uae_s8 src = m68k_dreg(regs, srcreg);
	uae_s8 dst = m68k_dreg(regs, dstreg);
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 4 * CYCLE_UNIT / 2 + count_cycles;
}
/* 4 (1/0) */
/* 2 0,0   */

/* AND.B (An),Dn */
uae_u32 REGPARAM2 op_c010_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 8;  
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = m68k_dreg(regs, dstreg);
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8 (2/0) */
/* 2 0,0   */

/* AND.B (An)+,Dn */
uae_u32 REGPARAM2 op_c018_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 8;  
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
	uae_s8 dst = m68k_dreg(regs, dstreg);
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8 (2/0) */
/* 2 0,0   */

/* AND.B -(An),Dn */
uae_u32 REGPARAM2 op_c020_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 10; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) = srca;
	uae_s8 dst = m68k_dreg(regs, dstreg);
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 10 * CYCLE_UNIT / 2 + count_cycles;
}
/* 10 (2/0) */
/* 2 0,0   */

/* AND.B (d16,An),Dn */
uae_u32 REGPARAM2 op_c028_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = m68k_dreg(regs, dstreg);
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (3/0) */
/* 4 0,0   */

/* AND.B (d8,An,Xn),Dn */
uae_u32 REGPARAM2 op_c030_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	BusCyclePenalty += 2;
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = m68k_dreg(regs, dstreg);
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 14 * CYCLE_UNIT / 2 + count_cycles;
}
/* 14 (3/0) */
/* 4 4,0   */

/* AND.B (xxx).W,Dn */
uae_u32 REGPARAM2 op_c038_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = m68k_dreg(regs, dstreg);
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (3/0) */
/* 4 0,0   */

/* AND.B (xxx).L,Dn */
uae_u32 REGPARAM2 op_c039_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	srca |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = m68k_dreg(regs, dstreg);
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (4/0) */
/* 6 0,0   */

/* AND.B (d16,PC),Dn */
uae_u32 REGPARAM2 op_c03a_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_getpci() + 2;
	srca += (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 2);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = m68k_dreg(regs, dstreg);
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (3/0) */
/* 4 0,0   */

/* AND.B (d8,PC,Xn),Dn */
uae_u32 REGPARAM2 op_c03b_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	uaecptr tmppc = m68k_getpci() + 2;
	BusCyclePenalty += 2;
	srca = get_disp_ea_000(tmppc, get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 2);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = m68k_dreg(regs, dstreg);
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 14 * CYCLE_UNIT / 2 + count_cycles;
}
/* 14 (3/0) */
/* 4 4,0   */

/* AND.B #<data>.B,Dn */
uae_u32 REGPARAM2 op_c03c_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 8;  
	uae_s8 src = (uae_u8)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = m68k_dreg(regs, dstreg);
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8 (2/0) */
/* 4 0,0   */

/* AND.W Dn,Dn */
uae_u32 REGPARAM2 op_c040_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 4;  
	uae_s16 src = m68k_dreg(regs, srcreg);
	uae_s16 dst = m68k_dreg(regs, dstreg);
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 4 * CYCLE_UNIT / 2 + count_cycles;
}
/* 4 (1/0) */
/* 2 0,0   */

/* AND.W (An),Dn */
uae_u32 REGPARAM2 op_c050_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 8;  
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8 (2/0) */
/* 2 0,0   */

/* AND.W (An)+,Dn */
uae_u32 REGPARAM2 op_c058_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 8;  
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) += 2 + 0;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) += 2;
	uae_s16 dst = m68k_dreg(regs, dstreg);
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8 (2/0) */
/* 2 0,0   */

/* AND.W -(An),Dn */
uae_u32 REGPARAM2 op_c060_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 10; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - 2;
	if (srca & 1) {
		m68k_incpci(4);
		m68k_areg(regs, srcreg) = srca;
		exception3_read_access(opcode, srca, 1, 1);
		return 2 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) = srca;
	uae_s16 dst = m68k_dreg(regs, dstreg);
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 10 * CYCLE_UNIT / 2 + count_cycles;
}
/* 10 (2/0) */
/* 2 0,0   */

/* AND.W (d16,An),Dn */
uae_u32 REGPARAM2 op_c068_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (3/0) */
/* 4 0,0   */

/* AND.W (d8,An,Xn),Dn */
uae_u32 REGPARAM2 op_c070_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	BusCyclePenalty += 2;
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 14 * CYCLE_UNIT / 2 + count_cycles;
}
/* 14 (3/0) */
/* 4 4,0   */

/* AND.W (xxx).W,Dn */
uae_u32 REGPARAM2 op_c078_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, srca, 1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (3/0) */
/* 4 0,0   */

/* AND.W (xxx).L,Dn */
uae_u32 REGPARAM2 op_c079_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	srca |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, srca, 1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (4/0) */
/* 6 0,0   */

/* AND.W (d16,PC),Dn */
uae_u32 REGPARAM2 op_c07a_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_getpci() + 2;
	srca += (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (3/0) */
/* 4 0,0   */

/* AND.W (d8,PC,Xn),Dn */
uae_u32 REGPARAM2 op_c07b_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	uaecptr tmppc = m68k_getpci() + 2;
	BusCyclePenalty += 2;
	srca = get_disp_ea_000(tmppc, get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 14 * CYCLE_UNIT / 2 + count_cycles;
}
/* 14 (3/0) */
/* 4 4,0   */

/* AND.W #<data>.W,Dn */
uae_u32 REGPARAM2 op_c07c_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 8;  
	uae_s16 src = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8 (2/0) */
/* 4 0,0   */

/* AND.L Dn,Dn */
uae_u32 REGPARAM2 op_c080_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 8;  
	uae_s32 src = m68k_dreg(regs, srcreg);
	uae_s32 dst = m68k_dreg(regs, dstreg);
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		dreg_68000_long_replace_low(dstreg, src);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	m68k_dreg(regs, dstreg) = (src);
	m68k_incpci(2);
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8 (1/0) */
/* 2 0,0   */

/* AND.L (An),Dn */
uae_u32 REGPARAM2 op_c090_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		dreg_68000_long_replace_low(dstreg, src);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	m68k_dreg(regs, dstreg) = (src);
	m68k_incpci(2);
	return 14 * CYCLE_UNIT / 2 + count_cycles;
}
/* 14 (3/0) */
/* 2 0,0   */

/* AND.L (An)+,Dn */
uae_u32 REGPARAM2 op_c098_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) += 4;
	uae_s32 dst = m68k_dreg(regs, dstreg);
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		dreg_68000_long_replace_low(dstreg, src);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	m68k_dreg(regs, dstreg) = (src);
	m68k_incpci(2);
	return 14 * CYCLE_UNIT / 2 + count_cycles;
}
/* 14 (3/0) */
/* 2 0,0   */

/* AND.L -(An),Dn */
uae_u32 REGPARAM2 op_c0a0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - 4;
	if (srca & 1) {
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception3_read_access(opcode, srca, 2, 1);
		return 2 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) = srca;
	uae_s32 dst = m68k_dreg(regs, dstreg);
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		dreg_68000_long_replace_low(dstreg, src);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	m68k_dreg(regs, dstreg) = (src);
	m68k_incpci(2);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/0) */
/* 2 0,0   */

/* AND.L (d16,An),Dn */
uae_u32 REGPARAM2 op_c0a8_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		dreg_68000_long_replace_low(dstreg, src);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	m68k_dreg(regs, dstreg) = (src);
	m68k_incpci(4);
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (4/0) */
/* 4 0,0   */

/* AND.L (d8,An,Xn),Dn */
uae_u32 REGPARAM2 op_c0b0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	BusCyclePenalty += 2;
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		dreg_68000_long_replace_low(dstreg, src);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	m68k_dreg(regs, dstreg) = (src);
	m68k_incpci(4);
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (4/0) */
/* 4 4,0   */

/* AND.L (xxx).W,Dn */
uae_u32 REGPARAM2 op_c0b8_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, srca, 2, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		dreg_68000_long_replace_low(dstreg, src);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	m68k_dreg(regs, dstreg) = (src);
	m68k_incpci(4);
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (4/0) */
/* 4 0,0   */

/* AND.L (xxx).L,Dn */
uae_u32 REGPARAM2 op_c0b9_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 22; 
	uaecptr srca;
	srca = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	srca |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, srca, 2, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		dreg_68000_long_replace_low(dstreg, src);
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	m68k_dreg(regs, dstreg) = (src);
	m68k_incpci(6);
	return 22 * CYCLE_UNIT / 2 + count_cycles;
}
/* 22 (5/0) */
/* 6 0,0   */

/* AND.L (d16,PC),Dn */
uae_u32 REGPARAM2 op_c0ba_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	srca = m68k_getpci() + 2;
	srca += (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 2);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		dreg_68000_long_replace_low(dstreg, src);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	m68k_dreg(regs, dstreg) = (src);
	m68k_incpci(4);
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (4/0) */
/* 4 0,0   */

/* AND.L (d8,PC,Xn),Dn */
uae_u32 REGPARAM2 op_c0bb_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	uaecptr tmppc = m68k_getpci() + 2;
	BusCyclePenalty += 2;
	srca = get_disp_ea_000(tmppc, get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 2);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		dreg_68000_long_replace_low(dstreg, src);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	m68k_dreg(regs, dstreg) = (src);
	m68k_incpci(4);
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (4/0) */
/* 4 4,0   */

/* AND.L #<data>.L,Dn */
uae_u32 REGPARAM2 op_c0bc_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 16; 
	uae_s32 src;
	src = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		dreg_68000_long_replace_low(dstreg, src);
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	m68k_dreg(regs, dstreg) = (src);
	m68k_incpci(6);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/0) */
/* 6 0,0   */

/* MULU.W Dn,Dn */
uae_u32 REGPARAM2 op_c0c0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 62;
	CurrentInstrCycles = 4;  
	uae_s16 src = m68k_dreg(regs, srcreg);
	uae_s16 dst = m68k_dreg(regs, dstreg);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();
		SET_ZFLG(1);
		pcoffset -= 2;
		m68k_dreg(regs, dstreg) &= 0xffff0000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	uae_u32 newv = (uae_u32)(uae_u16)dst * (uae_u32)(uae_u16)src;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_NFLG(((uae_s32)(newv)) < 0);
	count_cycles += (getMulu68kCycles(src)) * CYCLE_UNIT / 2;
	m68k_dreg(regs, dstreg) = (newv);
	m68k_incpci(2);
	return 4 * CYCLE_UNIT / 2 + count_cycles;
}
/* 4+ (1/0) */
/* 2 0,0   */

/* MULU.W (An),Dn */
uae_u32 REGPARAM2 op_c0d0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 62;
	CurrentInstrCycles = 8;  
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();
		SET_ZFLG(1);
		pcoffset -= 2;
		m68k_dreg(regs, dstreg) &= 0xffff0000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	uae_u32 newv = (uae_u32)(uae_u16)dst * (uae_u32)(uae_u16)src;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_NFLG(((uae_s32)(newv)) < 0);
	count_cycles += (getMulu68kCycles(src)) * CYCLE_UNIT / 2;
	m68k_dreg(regs, dstreg) = (newv);
	m68k_incpci(2);
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8+ (2/0) */
/* 2 0,0   */

/* MULU.W (An)+,Dn */
uae_u32 REGPARAM2 op_c0d8_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 62;
	CurrentInstrCycles = 8;  
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) += 2 + 0;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) += 2;
	uae_s16 dst = m68k_dreg(regs, dstreg);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();
		SET_ZFLG(1);
		pcoffset -= 2;
		m68k_dreg(regs, dstreg) &= 0xffff0000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	uae_u32 newv = (uae_u32)(uae_u16)dst * (uae_u32)(uae_u16)src;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_NFLG(((uae_s32)(newv)) < 0);
	count_cycles += (getMulu68kCycles(src)) * CYCLE_UNIT / 2;
	m68k_dreg(regs, dstreg) = (newv);
	m68k_incpci(2);
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8+ (2/0) */
/* 2 0,0   */

/* MULU.W -(An),Dn */
uae_u32 REGPARAM2 op_c0e0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 62;
	CurrentInstrCycles = 10; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - 2;
	if (srca & 1) {
		m68k_incpci(4);
		m68k_areg(regs, srcreg) = srca;
		exception3_read_access(opcode, srca, 1, 1);
		return 2 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) = srca;
	uae_s16 dst = m68k_dreg(regs, dstreg);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();
		SET_ZFLG(1);
		pcoffset -= 0;
		m68k_dreg(regs, dstreg) &= 0xffff0000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	uae_u32 newv = (uae_u32)(uae_u16)dst * (uae_u32)(uae_u16)src;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_NFLG(((uae_s32)(newv)) < 0);
	count_cycles += (getMulu68kCycles(src)) * CYCLE_UNIT / 2;
	m68k_dreg(regs, dstreg) = (newv);
	m68k_incpci(2);
	return 10 * CYCLE_UNIT / 2 + count_cycles;
}
/* 10+ (2/0) */
/* 2 0,0   */

/* MULU.W (d16,An),Dn */
uae_u32 REGPARAM2 op_c0e8_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 62;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();
		SET_ZFLG(1);
		pcoffset -= 4;
		m68k_dreg(regs, dstreg) &= 0xffff0000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	uae_u32 newv = (uae_u32)(uae_u16)dst * (uae_u32)(uae_u16)src;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_NFLG(((uae_s32)(newv)) < 0);
	count_cycles += (getMulu68kCycles(src)) * CYCLE_UNIT / 2;
	m68k_dreg(regs, dstreg) = (newv);
	m68k_incpci(4);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12+ (3/0) */
/* 4 0,0   */

/* MULU.W (d8,An,Xn),Dn */
uae_u32 REGPARAM2 op_c0f0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 62;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	BusCyclePenalty += 2;
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();
		SET_ZFLG(1);
		pcoffset -= 4;
		m68k_dreg(regs, dstreg) &= 0xffff0000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	uae_u32 newv = (uae_u32)(uae_u16)dst * (uae_u32)(uae_u16)src;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_NFLG(((uae_s32)(newv)) < 0);
	count_cycles += (getMulu68kCycles(src)) * CYCLE_UNIT / 2;
	m68k_dreg(regs, dstreg) = (newv);
	m68k_incpci(4);
	return 14 * CYCLE_UNIT / 2 + count_cycles;
}
/* 14+ (3/0) */
/* 4 4,0   */

/* MULU.W (xxx).W,Dn */
uae_u32 REGPARAM2 op_c0f8_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 62;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, srca, 1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();
		SET_ZFLG(1);
		pcoffset -= 2;
		m68k_dreg(regs, dstreg) &= 0xffff0000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	uae_u32 newv = (uae_u32)(uae_u16)dst * (uae_u32)(uae_u16)src;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_NFLG(((uae_s32)(newv)) < 0);
	count_cycles += (getMulu68kCycles(src)) * CYCLE_UNIT / 2;
	m68k_dreg(regs, dstreg) = (newv);
	m68k_incpci(4);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12+ (3/0) */
/* 4 0,0   */

/* MULU.W (xxx).L,Dn */
uae_u32 REGPARAM2 op_c0f9_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 62;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	srca |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, srca, 1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();
		SET_ZFLG(1);
		pcoffset -= 2;
		m68k_dreg(regs, dstreg) &= 0xffff0000;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	uae_u32 newv = (uae_u32)(uae_u16)dst * (uae_u32)(uae_u16)src;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_NFLG(((uae_s32)(newv)) < 0);
	count_cycles += (getMulu68kCycles(src)) * CYCLE_UNIT / 2;
	m68k_dreg(regs, dstreg) = (newv);
	m68k_incpci(6);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16+ (4/0) */
/* 6 0,0   */

/* MULU.W (d16,PC),Dn */
uae_u32 REGPARAM2 op_c0fa_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 62;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_getpci() + 2;
	srca += (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();
		SET_ZFLG(1);
		pcoffset -= 4;
		m68k_dreg(regs, dstreg) &= 0xffff0000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	uae_u32 newv = (uae_u32)(uae_u16)dst * (uae_u32)(uae_u16)src;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_NFLG(((uae_s32)(newv)) < 0);
	count_cycles += (getMulu68kCycles(src)) * CYCLE_UNIT / 2;
	m68k_dreg(regs, dstreg) = (newv);
	m68k_incpci(4);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12+ (3/0) */
/* 4 0,0   */

/* MULU.W (d8,PC,Xn),Dn */
uae_u32 REGPARAM2 op_c0fb_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 62;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	uaecptr tmppc = m68k_getpci() + 2;
	BusCyclePenalty += 2;
	srca = get_disp_ea_000(tmppc, get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();
		SET_ZFLG(1);
		pcoffset -= 4;
		m68k_dreg(regs, dstreg) &= 0xffff0000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	uae_u32 newv = (uae_u32)(uae_u16)dst * (uae_u32)(uae_u16)src;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_NFLG(((uae_s32)(newv)) < 0);
	count_cycles += (getMulu68kCycles(src)) * CYCLE_UNIT / 2;
	m68k_dreg(regs, dstreg) = (newv);
	m68k_incpci(4);
	return 14 * CYCLE_UNIT / 2 + count_cycles;
}
/* 14+ (3/0) */
/* 4 4,0   */

/* MULU.W #<data>.W,Dn */
uae_u32 REGPARAM2 op_c0fc_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 62;
	CurrentInstrCycles = 8;  
	uae_s16 src = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();
		SET_ZFLG(1);
		pcoffset -= 2;
		m68k_dreg(regs, dstreg) &= 0xffff0000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	uae_u32 newv = (uae_u32)(uae_u16)dst * (uae_u32)(uae_u16)src;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_NFLG(((uae_s32)(newv)) < 0);
	count_cycles += (getMulu68kCycles(src)) * CYCLE_UNIT / 2;
	m68k_dreg(regs, dstreg) = (newv);
	m68k_incpci(4);
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8+ (2/0) */
/* 4 0,0   */

/* ABCD.B Dn,Dn */
uae_u32 REGPARAM2 op_c100_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 14;
	CurrentInstrCycles = 6;  
	uae_s8 src = m68k_dreg(regs, srcreg);
	uae_s8 dst = m68k_dreg(regs, dstreg);
	uae_u16 newv_lo = (src & 0xF) + (dst & 0xF) + (GET_XFLG() ? 1 : 0);
	uae_u16 newv_hi = (src & 0xF0) + (dst & 0xF0);
	uae_u16 newv, tmp_newv;
	int cflg;
	newv = tmp_newv = newv_hi + newv_lo;if (newv_lo > 9) { newv += 6; }
	cflg = (newv & 0x3F0) > 0x90;
	if (cflg) newv += 0x60;
	SET_CFLG(cflg);
	COPY_CARRY();
	SET_ZFLG(GET_ZFLG() & (((uae_s8)(newv)) == 0));
	SET_NFLG(((uae_s8)(newv)) < 0);
	SET_VFLG((tmp_newv & 0x80) == 0 && (newv & 0x80) != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
	m68k_incpci(2);
	return 6 * CYCLE_UNIT / 2 + count_cycles;
}
/* 6 (1/0) */
/* 2 0,0   */

/* ABCD.B -(An),-(An) */
uae_u32 REGPARAM2 op_c108_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 14;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) = srca;
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, dstreg) = dsta;
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) = dsta;
	uae_u16 newv_lo = (src & 0xF) + (dst & 0xF) + (GET_XFLG() ? 1 : 0);
	uae_u16 newv_hi = (src & 0xF0) + (dst & 0xF0);
	uae_u16 newv, tmp_newv;
	int cflg;
	newv = tmp_newv = newv_hi + newv_lo;if (newv_lo > 9) { newv += 6; }
	cflg = (newv & 0x3F0) > 0x90;
	if (cflg) newv += 0x60;
	SET_CFLG(cflg);
	COPY_CARRY();
	SET_ZFLG(GET_ZFLG() & (((uae_s8)(newv)) == 0));
	SET_NFLG(((uae_s8)(newv)) < 0);
	SET_VFLG((tmp_newv & 0x80) == 0 && (newv & 0x80) != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_byte_000(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, newv, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (3/1) */
/* 2 0,0   */

/* AND.B Dn,(An) */
uae_u32 REGPARAM2 op_c110_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 12; 
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_byte_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (2/1) */
/* 2 0,0   */

/* AND.B Dn,(An)+ */
uae_u32 REGPARAM2 op_c118_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 12; 
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_byte_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (2/1) */
/* 2 0,0   */

/* AND.B Dn,-(An) */
uae_u32 REGPARAM2 op_c120_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 14; 
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, dstreg) = dsta;
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) = dsta;
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_byte_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 14 * CYCLE_UNIT / 2 + count_cycles;
}
/* 14 (2/1) */
/* 2 0,0   */

/* AND.B Dn,(d16,An) */
uae_u32 REGPARAM2 op_c128_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 16; 
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_byte_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 4 0,0   */

/* AND.B Dn,(d8,An,Xn) */
uae_u32 REGPARAM2 op_c130_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 18; 
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	BusCyclePenalty += 2;
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_byte_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (3/1) */
/* 4 4,0   */

/* AND.B Dn,(xxx).W */
uae_u32 REGPARAM2 op_c138_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	OpcodeFamily = 2;
	CurrentInstrCycles = 16; 
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_byte_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 4 0,0   */

/* AND.B Dn,(xxx).L */
uae_u32 REGPARAM2 op_c139_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	OpcodeFamily = 2;
	CurrentInstrCycles = 20; 
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	dsta |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_byte_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (4/1) */
/* 6 0,0   */

/* EXG.L Dn,Dn */
uae_u32 REGPARAM2 op_c140_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 35;
	CurrentInstrCycles = 6;  
	uae_s32 src = m68k_dreg(regs, srcreg);
	uae_s32 dst = m68k_dreg(regs, dstreg);
	m68k_dreg(regs, srcreg) = (dst);
	m68k_dreg(regs, dstreg) = (src);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	m68k_incpci(2);
	return 6 * CYCLE_UNIT / 2 + count_cycles;
}
/* 6 (1/0) */
/* 2 0,0   */

/* EXG.L An,An */
uae_u32 REGPARAM2 op_c148_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 35;
	CurrentInstrCycles = 6;  
	uae_s32 src = m68k_areg(regs, srcreg);
	uae_s32 dst = m68k_areg(regs, dstreg);
	m68k_areg(regs, srcreg) = (dst);
	m68k_areg(regs, dstreg) = (src);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	m68k_incpci(2);
	return 6 * CYCLE_UNIT / 2 + count_cycles;
}
/* 6 (1/0) */
/* 2 0,0   */

/* AND.W Dn,(An) */
uae_u32 REGPARAM2 op_c150_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 12; 
	uae_s16 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	if (dsta & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dsta, 1, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = get_word_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_word_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (2/1) */
/* 2 0,0   */

/* AND.W Dn,(An)+ */
uae_u32 REGPARAM2 op_c158_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 12; 
	uae_s16 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	if (dsta & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dsta, 1, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = get_word_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, dstreg) += 2 + 0;
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) += 2;
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_word_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (2/1) */
/* 2 0,0   */

/* AND.W Dn,-(An) */
uae_u32 REGPARAM2 op_c160_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 14; 
	uae_s16 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - 2;
	if (dsta & 1) {
		m68k_incpci(4);
		m68k_areg(regs, dstreg) = dsta;
		exception3_read_access(opcode, dsta, 1, 1);
		return 2 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = get_word_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, dstreg) = dsta;
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) = dsta;
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_word_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 14 * CYCLE_UNIT / 2 + count_cycles;
}
/* 14 (2/1) */
/* 2 0,0   */

/* AND.W Dn,(d16,An) */
uae_u32 REGPARAM2 op_c168_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 16; 
	uae_s16 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dsta, 1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = get_word_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_word_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 4 0,0   */

/* AND.W Dn,(d8,An,Xn) */
uae_u32 REGPARAM2 op_c170_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 18; 
	uae_s16 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	BusCyclePenalty += 2;
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dsta, 1, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = get_word_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_word_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (3/1) */
/* 4 4,0   */

/* AND.W Dn,(xxx).W */
uae_u32 REGPARAM2 op_c178_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	OpcodeFamily = 2;
	CurrentInstrCycles = 16; 
	uae_s16 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, dsta, 1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = get_word_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_word_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 4 0,0   */

/* AND.W Dn,(xxx).L */
uae_u32 REGPARAM2 op_c179_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	OpcodeFamily = 2;
	CurrentInstrCycles = 20; 
	uae_s16 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	dsta |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, dsta, 1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = get_word_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_word_000(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (4/1) */
/* 6 0,0   */

/* EXG.L Dn,An */
uae_u32 REGPARAM2 op_c188_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 35;
	CurrentInstrCycles = 6;  
	uae_s32 src = m68k_dreg(regs, srcreg);
	uae_s32 dst = m68k_areg(regs, dstreg);
	m68k_dreg(regs, srcreg) = (dst);
	m68k_areg(regs, dstreg) = (src);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	m68k_incpci(2);
	return 6 * CYCLE_UNIT / 2 + count_cycles;
}
/* 6 (1/0) */
/* 2 0,0   */

/* AND.L Dn,(An) */
uae_u32 REGPARAM2 op_c190_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 20; 
	uae_s32 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	if (dsta & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dsta, 2, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = get_word_000(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	dst |= get_word_000(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src >> 16); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (3/2) */
/* 2 0,0   */

/* AND.L Dn,(An)+ */
uae_u32 REGPARAM2 op_c198_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 20; 
	uae_s32 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	if (dsta & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dsta, 2, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = get_word_000(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	dst |= get_word_000(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) += 4;
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src >> 16); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (3/2) */
/* 2 0,0   */

/* AND.L Dn,-(An) */
uae_u32 REGPARAM2 op_c1a0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 22; 
	uae_s32 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - 4;
	if (dsta & 1) {
		m68k_incpci(2);
		m68k_areg(regs, dstreg) = dsta;
		exception3_read_access(opcode, dsta, 2, 1);
		return 2 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = get_word_000(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, dstreg) = dsta;
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	dst |= get_word_000(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, dstreg) = dsta;
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) = dsta;
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src >> 16); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return 22 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 22 * CYCLE_UNIT / 2 + count_cycles;
}
/* 22 (3/2) */
/* 2 0,0   */

/* AND.L Dn,(d16,An) */
uae_u32 REGPARAM2 op_c1a8_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 24; 
	uae_s32 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dsta, 2, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = get_word_000(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	dst |= get_word_000(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src >> 16); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 24 * CYCLE_UNIT / 2 + count_cycles;
}
/* 24 (4/2) */
/* 4 0,0   */

/* AND.L Dn,(d8,An,Xn) */
uae_u32 REGPARAM2 op_c1b0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 26; 
	uae_s32 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	BusCyclePenalty += 2;
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dsta, 2, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = get_word_000(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	dst |= get_word_000(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return 22 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src >> 16); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return 26 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 26 * CYCLE_UNIT / 2 + count_cycles;
}
/* 26 (4/2) */
/* 4 4,0   */

/* AND.L Dn,(xxx).W */
uae_u32 REGPARAM2 op_c1b8_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	OpcodeFamily = 2;
	CurrentInstrCycles = 24; 
	uae_s32 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, dsta, 2, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = get_word_000(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	dst |= get_word_000(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src >> 16); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 24 * CYCLE_UNIT / 2 + count_cycles;
}
/* 24 (4/2) */
/* 4 0,0   */

/* AND.L Dn,(xxx).L */
uae_u32 REGPARAM2 op_c1b9_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	OpcodeFamily = 2;
	CurrentInstrCycles = 28; 
	uae_s32 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	dsta |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, dsta, 2, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = get_word_000(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	dst |= get_word_000(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, src >> 16); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return 28 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 28 * CYCLE_UNIT / 2 + count_cycles;
}
/* 28 (5/2) */
/* 6 0,0   */

/* MULS.W Dn,Dn */
uae_u32 REGPARAM2 op_c1c0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 63;
	CurrentInstrCycles = 4;  
	uae_s16 src = m68k_dreg(regs, srcreg);
	uae_s16 dst = m68k_dreg(regs, dstreg);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();
		SET_ZFLG(1);
		pcoffset -= 2;
		m68k_dreg(regs, dstreg) &= 0xffff0000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	uae_u32 newv = (uae_s32)(uae_s16)dst * (uae_s32)(uae_s16)src;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_NFLG(((uae_s32)(newv)) < 0);
	count_cycles += (getMuls68kCycles(src)) * CYCLE_UNIT / 2;
	m68k_dreg(regs, dstreg) = (newv);
	m68k_incpci(2);
	return 4 * CYCLE_UNIT / 2 + count_cycles;
}
/* 4+ (1/0) */
/* 2 0,0   */

/* MULS.W (An),Dn */
uae_u32 REGPARAM2 op_c1d0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 63;
	CurrentInstrCycles = 8;  
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();
		SET_ZFLG(1);
		pcoffset -= 2;
		m68k_dreg(regs, dstreg) &= 0xffff0000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	uae_u32 newv = (uae_s32)(uae_s16)dst * (uae_s32)(uae_s16)src;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_NFLG(((uae_s32)(newv)) < 0);
	count_cycles += (getMuls68kCycles(src)) * CYCLE_UNIT / 2;
	m68k_dreg(regs, dstreg) = (newv);
	m68k_incpci(2);
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8+ (2/0) */
/* 2 0,0   */

/* MULS.W (An)+,Dn */
uae_u32 REGPARAM2 op_c1d8_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 63;
	CurrentInstrCycles = 8;  
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) += 2 + 0;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) += 2;
	uae_s16 dst = m68k_dreg(regs, dstreg);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();
		SET_ZFLG(1);
		pcoffset -= 2;
		m68k_dreg(regs, dstreg) &= 0xffff0000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	uae_u32 newv = (uae_s32)(uae_s16)dst * (uae_s32)(uae_s16)src;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_NFLG(((uae_s32)(newv)) < 0);
	count_cycles += (getMuls68kCycles(src)) * CYCLE_UNIT / 2;
	m68k_dreg(regs, dstreg) = (newv);
	m68k_incpci(2);
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8+ (2/0) */
/* 2 0,0   */

/* MULS.W -(An),Dn */
uae_u32 REGPARAM2 op_c1e0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 63;
	CurrentInstrCycles = 10; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - 2;
	if (srca & 1) {
		m68k_incpci(4);
		m68k_areg(regs, srcreg) = srca;
		exception3_read_access(opcode, srca, 1, 1);
		return 2 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) = srca;
	uae_s16 dst = m68k_dreg(regs, dstreg);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();
		SET_ZFLG(1);
		pcoffset -= 0;
		m68k_dreg(regs, dstreg) &= 0xffff0000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	uae_u32 newv = (uae_s32)(uae_s16)dst * (uae_s32)(uae_s16)src;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_NFLG(((uae_s32)(newv)) < 0);
	count_cycles += (getMuls68kCycles(src)) * CYCLE_UNIT / 2;
	m68k_dreg(regs, dstreg) = (newv);
	m68k_incpci(2);
	return 10 * CYCLE_UNIT / 2 + count_cycles;
}
/* 10+ (2/0) */
/* 2 0,0   */

/* MULS.W (d16,An),Dn */
uae_u32 REGPARAM2 op_c1e8_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 63;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();
		SET_ZFLG(1);
		pcoffset -= 4;
		m68k_dreg(regs, dstreg) &= 0xffff0000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	uae_u32 newv = (uae_s32)(uae_s16)dst * (uae_s32)(uae_s16)src;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_NFLG(((uae_s32)(newv)) < 0);
	count_cycles += (getMuls68kCycles(src)) * CYCLE_UNIT / 2;
	m68k_dreg(regs, dstreg) = (newv);
	m68k_incpci(4);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12+ (3/0) */
/* 4 0,0   */

/* MULS.W (d8,An,Xn),Dn */
uae_u32 REGPARAM2 op_c1f0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 63;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	BusCyclePenalty += 2;
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();
		SET_ZFLG(1);
		pcoffset -= 4;
		m68k_dreg(regs, dstreg) &= 0xffff0000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	uae_u32 newv = (uae_s32)(uae_s16)dst * (uae_s32)(uae_s16)src;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_NFLG(((uae_s32)(newv)) < 0);
	count_cycles += (getMuls68kCycles(src)) * CYCLE_UNIT / 2;
	m68k_dreg(regs, dstreg) = (newv);
	m68k_incpci(4);
	return 14 * CYCLE_UNIT / 2 + count_cycles;
}
/* 14+ (3/0) */
/* 4 4,0   */

/* MULS.W (xxx).W,Dn */
uae_u32 REGPARAM2 op_c1f8_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 63;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, srca, 1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();
		SET_ZFLG(1);
		pcoffset -= 2;
		m68k_dreg(regs, dstreg) &= 0xffff0000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	uae_u32 newv = (uae_s32)(uae_s16)dst * (uae_s32)(uae_s16)src;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_NFLG(((uae_s32)(newv)) < 0);
	count_cycles += (getMuls68kCycles(src)) * CYCLE_UNIT / 2;
	m68k_dreg(regs, dstreg) = (newv);
	m68k_incpci(4);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12+ (3/0) */
/* 4 0,0   */

/* MULS.W (xxx).L,Dn */
uae_u32 REGPARAM2 op_c1f9_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 63;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	srca |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, srca, 1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();
		SET_ZFLG(1);
		pcoffset -= 2;
		m68k_dreg(regs, dstreg) &= 0xffff0000;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	uae_u32 newv = (uae_s32)(uae_s16)dst * (uae_s32)(uae_s16)src;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_NFLG(((uae_s32)(newv)) < 0);
	count_cycles += (getMuls68kCycles(src)) * CYCLE_UNIT / 2;
	m68k_dreg(regs, dstreg) = (newv);
	m68k_incpci(6);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16+ (4/0) */
/* 6 0,0   */

/* MULS.W (d16,PC),Dn */
uae_u32 REGPARAM2 op_c1fa_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 63;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_getpci() + 2;
	srca += (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();
		SET_ZFLG(1);
		pcoffset -= 4;
		m68k_dreg(regs, dstreg) &= 0xffff0000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	uae_u32 newv = (uae_s32)(uae_s16)dst * (uae_s32)(uae_s16)src;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_NFLG(((uae_s32)(newv)) < 0);
	count_cycles += (getMuls68kCycles(src)) * CYCLE_UNIT / 2;
	m68k_dreg(regs, dstreg) = (newv);
	m68k_incpci(4);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12+ (3/0) */
/* 4 0,0   */

/* MULS.W (d8,PC,Xn),Dn */
uae_u32 REGPARAM2 op_c1fb_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 63;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	uaecptr tmppc = m68k_getpci() + 2;
	BusCyclePenalty += 2;
	srca = get_disp_ea_000(tmppc, get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();
		SET_ZFLG(1);
		pcoffset -= 4;
		m68k_dreg(regs, dstreg) &= 0xffff0000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	uae_u32 newv = (uae_s32)(uae_s16)dst * (uae_s32)(uae_s16)src;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_NFLG(((uae_s32)(newv)) < 0);
	count_cycles += (getMuls68kCycles(src)) * CYCLE_UNIT / 2;
	m68k_dreg(regs, dstreg) = (newv);
	m68k_incpci(4);
	return 14 * CYCLE_UNIT / 2 + count_cycles;
}
/* 14+ (3/0) */
/* 4 4,0   */

/* MULS.W #<data>.W,Dn */
uae_u32 REGPARAM2 op_c1fc_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 63;
	CurrentInstrCycles = 8;  
	uae_s16 src = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();
		SET_ZFLG(1);
		pcoffset -= 2;
		m68k_dreg(regs, dstreg) &= 0xffff0000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	uae_u32 newv = (uae_s32)(uae_s16)dst * (uae_s32)(uae_s16)src;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_NFLG(((uae_s32)(newv)) < 0);
	count_cycles += (getMuls68kCycles(src)) * CYCLE_UNIT / 2;
	m68k_dreg(regs, dstreg) = (newv);
	m68k_incpci(4);
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8+ (2/0) */
/* 4 0,0   */

/* ADD.B Dn,Dn */
uae_u32 REGPARAM2 op_d000_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 4;  
	uae_s8 src = m68k_dreg(regs, srcreg);
	uae_s8 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u8)(~dst)) < ((uae_u8)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 4 * CYCLE_UNIT / 2 + count_cycles;
}
/* 4 (1/0) */
/* 2 0,0   */

/* ADD.B (An),Dn */
uae_u32 REGPARAM2 op_d010_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 8;  
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u8)(~dst)) < ((uae_u8)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8 (2/0) */
/* 2 0,0   */

/* ADD.B (An)+,Dn */
uae_u32 REGPARAM2 op_d018_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 8;  
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
	uae_s8 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u8)(~dst)) < ((uae_u8)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8 (2/0) */
/* 2 0,0   */

/* ADD.B -(An),Dn */
uae_u32 REGPARAM2 op_d020_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 10; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) = srca;
	uae_s8 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u8)(~dst)) < ((uae_u8)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 10 * CYCLE_UNIT / 2 + count_cycles;
}
/* 10 (2/0) */
/* 2 0,0   */

/* ADD.B (d16,An),Dn */
uae_u32 REGPARAM2 op_d028_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u8)(~dst)) < ((uae_u8)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (3/0) */
/* 4 0,0   */

/* ADD.B (d8,An,Xn),Dn */
uae_u32 REGPARAM2 op_d030_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	BusCyclePenalty += 2;
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u8)(~dst)) < ((uae_u8)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 14 * CYCLE_UNIT / 2 + count_cycles;
}
/* 14 (3/0) */
/* 4 4,0   */

/* ADD.B (xxx).W,Dn */
uae_u32 REGPARAM2 op_d038_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u8)(~dst)) < ((uae_u8)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (3/0) */
/* 4 0,0   */

/* ADD.B (xxx).L,Dn */
uae_u32 REGPARAM2 op_d039_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	srca |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u8)(~dst)) < ((uae_u8)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (4/0) */
/* 6 0,0   */

/* ADD.B (d16,PC),Dn */
uae_u32 REGPARAM2 op_d03a_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_getpci() + 2;
	srca += (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 2);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u8)(~dst)) < ((uae_u8)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (3/0) */
/* 4 0,0   */

/* ADD.B (d8,PC,Xn),Dn */
uae_u32 REGPARAM2 op_d03b_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	uaecptr tmppc = m68k_getpci() + 2;
	BusCyclePenalty += 2;
	srca = get_disp_ea_000(tmppc, get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 2);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u8)(~dst)) < ((uae_u8)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 14 * CYCLE_UNIT / 2 + count_cycles;
}
/* 14 (3/0) */
/* 4 4,0   */

/* ADD.B #<data>.B,Dn */
uae_u32 REGPARAM2 op_d03c_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 8;  
	uae_s8 src = (uae_u8)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u8)(~dst)) < ((uae_u8)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8 (2/0) */
/* 4 0,0   */

/* ADD.W Dn,Dn */
uae_u32 REGPARAM2 op_d040_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 4;  
	uae_s16 src = m68k_dreg(regs, srcreg);
	uae_s16 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 4 * CYCLE_UNIT / 2 + count_cycles;
}
/* 4 (1/0) */
/* 2 0,0   */

/* ADD.W An,Dn */
uae_u32 REGPARAM2 op_d048_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 4;  
	uae_s16 src = m68k_areg(regs, srcreg);
	uae_s16 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 4 * CYCLE_UNIT / 2 + count_cycles;
}
/* 4 (1/0) */
/* 2 0,0   */

/* ADD.W (An),Dn */
uae_u32 REGPARAM2 op_d050_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 8;  
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8 (2/0) */
/* 2 0,0   */

/* ADD.W (An)+,Dn */
uae_u32 REGPARAM2 op_d058_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 8;  
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) += 2 + 0;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) += 2;
	uae_s16 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8 (2/0) */
/* 2 0,0   */

/* ADD.W -(An),Dn */
uae_u32 REGPARAM2 op_d060_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 10; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - 2;
	if (srca & 1) {
		m68k_incpci(4);
		m68k_areg(regs, srcreg) = srca;
		exception3_read_access(opcode, srca, 1, 1);
		return 2 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) = srca;
	uae_s16 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 10 * CYCLE_UNIT / 2 + count_cycles;
}
/* 10 (2/0) */
/* 2 0,0   */

/* ADD.W (d16,An),Dn */
uae_u32 REGPARAM2 op_d068_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (3/0) */
/* 4 0,0   */

/* ADD.W (d8,An,Xn),Dn */
uae_u32 REGPARAM2 op_d070_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	BusCyclePenalty += 2;
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 14 * CYCLE_UNIT / 2 + count_cycles;
}
/* 14 (3/0) */
/* 4 4,0   */

/* ADD.W (xxx).W,Dn */
uae_u32 REGPARAM2 op_d078_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, srca, 1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (3/0) */
/* 4 0,0   */

/* ADD.W (xxx).L,Dn */
uae_u32 REGPARAM2 op_d079_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	srca |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, srca, 1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (4/0) */
/* 6 0,0   */

/* ADD.W (d16,PC),Dn */
uae_u32 REGPARAM2 op_d07a_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_getpci() + 2;
	srca += (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (3/0) */
/* 4 0,0   */

/* ADD.W (d8,PC,Xn),Dn */
uae_u32 REGPARAM2 op_d07b_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	uaecptr tmppc = m68k_getpci() + 2;
	BusCyclePenalty += 2;
	srca = get_disp_ea_000(tmppc, get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 14 * CYCLE_UNIT / 2 + count_cycles;
}
/* 14 (3/0) */
/* 4 4,0   */

/* ADD.W #<data>.W,Dn */
uae_u32 REGPARAM2 op_d07c_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 8;  
	uae_s16 src = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8 (2/0) */
/* 4 0,0   */

/* ADD.L Dn,Dn */
uae_u32 REGPARAM2 op_d080_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 8;  
	uae_s32 src = m68k_dreg(regs, srcreg);
	uae_s32 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u32)(~dst)) < ((uae_u32)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		uae_s16 bnewv = (uae_s16)dst + (uae_s16)src;
		int bflgs = ((uae_s16)(src)) < 0;
		int bflgo = ((uae_s16)(dst)) < 0;
		int bflgn = bnewv < 0;
		ccr_68000_long_move_ae_LZN(bnewv);
		SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
		SET_XFLG(GET_CFLG());
		SET_VFLG((bflgs ^ bflgn) & (bflgo ^ bflgn));
		dreg_68000_long_replace_low(dstreg, bnewv);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	m68k_dreg(regs, dstreg) = (newv);
	m68k_incpci(2);
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8 (1/0) */
/* 2 0,0   */

/* ADD.L An,Dn */
uae_u32 REGPARAM2 op_d088_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 8;  
	uae_s32 src = m68k_areg(regs, srcreg);
	uae_s32 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u32)(~dst)) < ((uae_u32)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		uae_s16 bnewv = (uae_s16)dst + (uae_s16)src;
		int bflgs = ((uae_s16)(src)) < 0;
		int bflgo = ((uae_s16)(dst)) < 0;
		int bflgn = bnewv < 0;
		ccr_68000_long_move_ae_LZN(bnewv);
		SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
		SET_XFLG(GET_CFLG());
		SET_VFLG((bflgs ^ bflgn) & (bflgo ^ bflgn));
		dreg_68000_long_replace_low(dstreg, bnewv);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	m68k_dreg(regs, dstreg) = (newv);
	m68k_incpci(2);
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8 (1/0) */
/* 2 0,0   */

/* ADD.L (An),Dn */
uae_u32 REGPARAM2 op_d090_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u32)(~dst)) < ((uae_u32)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		dreg_68000_long_replace_low(dstreg, newv);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	m68k_dreg(regs, dstreg) = (newv);
	m68k_incpci(2);
	return 14 * CYCLE_UNIT / 2 + count_cycles;
}
/* 14 (3/0) */
/* 2 0,0   */

/* ADD.L (An)+,Dn */
uae_u32 REGPARAM2 op_d098_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) += 4;
	uae_s32 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u32)(~dst)) < ((uae_u32)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		dreg_68000_long_replace_low(dstreg, newv);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	m68k_dreg(regs, dstreg) = (newv);
	m68k_incpci(2);
	return 14 * CYCLE_UNIT / 2 + count_cycles;
}
/* 14 (3/0) */
/* 2 0,0   */

/* ADD.L -(An),Dn */
uae_u32 REGPARAM2 op_d0a0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - 4;
	if (srca & 1) {
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception3_read_access(opcode, srca, 2, 1);
		return 2 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) = srca;
	uae_s32 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u32)(~dst)) < ((uae_u32)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		dreg_68000_long_replace_low(dstreg, newv);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	m68k_dreg(regs, dstreg) = (newv);
	m68k_incpci(2);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/0) */
/* 2 0,0   */

/* ADD.L (d16,An),Dn */
uae_u32 REGPARAM2 op_d0a8_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u32)(~dst)) < ((uae_u32)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		dreg_68000_long_replace_low(dstreg, newv);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	m68k_dreg(regs, dstreg) = (newv);
	m68k_incpci(4);
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (4/0) */
/* 4 0,0   */

/* ADD.L (d8,An,Xn),Dn */
uae_u32 REGPARAM2 op_d0b0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	BusCyclePenalty += 2;
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u32)(~dst)) < ((uae_u32)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		dreg_68000_long_replace_low(dstreg, newv);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	m68k_dreg(regs, dstreg) = (newv);
	m68k_incpci(4);
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (4/0) */
/* 4 4,0   */

/* ADD.L (xxx).W,Dn */
uae_u32 REGPARAM2 op_d0b8_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, srca, 2, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u32)(~dst)) < ((uae_u32)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		dreg_68000_long_replace_low(dstreg, newv);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	m68k_dreg(regs, dstreg) = (newv);
	m68k_incpci(4);
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (4/0) */
/* 4 0,0   */

/* ADD.L (xxx).L,Dn */
uae_u32 REGPARAM2 op_d0b9_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 22; 
	uaecptr srca;
	srca = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	srca |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, srca, 2, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u32)(~dst)) < ((uae_u32)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		dreg_68000_long_replace_low(dstreg, newv);
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	m68k_dreg(regs, dstreg) = (newv);
	m68k_incpci(6);
	return 22 * CYCLE_UNIT / 2 + count_cycles;
}
/* 22 (5/0) */
/* 6 0,0   */

/* ADD.L (d16,PC),Dn */
uae_u32 REGPARAM2 op_d0ba_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	srca = m68k_getpci() + 2;
	srca += (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 2);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u32)(~dst)) < ((uae_u32)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		dreg_68000_long_replace_low(dstreg, newv);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	m68k_dreg(regs, dstreg) = (newv);
	m68k_incpci(4);
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (4/0) */
/* 4 0,0   */

/* ADD.L (d8,PC,Xn),Dn */
uae_u32 REGPARAM2 op_d0bb_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	uaecptr tmppc = m68k_getpci() + 2;
	BusCyclePenalty += 2;
	srca = get_disp_ea_000(tmppc, get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 2);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u32)(~dst)) < ((uae_u32)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		dreg_68000_long_replace_low(dstreg, newv);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	m68k_dreg(regs, dstreg) = (newv);
	m68k_incpci(4);
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (4/0) */
/* 4 4,0   */

/* ADD.L #<data>.L,Dn */
uae_u32 REGPARAM2 op_d0bc_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 16; 
	uae_s32 src;
	src = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u32)(~dst)) < ((uae_u32)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		uae_s16 bnewv = (uae_s16)dst + (uae_s16)src;
		int bflgs = ((uae_s16)(src)) < 0;
		int bflgo = ((uae_s16)(dst)) < 0;
		int bflgn = bnewv < 0;
		ccr_68000_long_move_ae_LZN(bnewv);
		SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
		SET_XFLG(GET_CFLG());
		SET_VFLG((bflgs ^ bflgn) & (bflgo ^ bflgn));
		dreg_68000_long_replace_low(dstreg, bnewv);
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	m68k_dreg(regs, dstreg) = (newv);
	m68k_incpci(6);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/0) */
/* 6 0,0   */

/* ADDA.W Dn,An */
uae_u32 REGPARAM2 op_d0c0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 12;
	CurrentInstrCycles = 8;  
	uae_s16 src = m68k_dreg(regs, srcreg);
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = dst + src;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		areg_68000_long_replace_low(dstreg, newv);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	m68k_areg(regs, dstreg) = (newv);
	m68k_incpci(2);
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8 (1/0) */
/* 2 0,0   */

/* ADDA.W An,An */
uae_u32 REGPARAM2 op_d0c8_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 12;
	CurrentInstrCycles = 8;  
	uae_s16 src = m68k_areg(regs, srcreg);
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = dst + src;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		areg_68000_long_replace_low(dstreg, newv);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	m68k_areg(regs, dstreg) = (newv);
	m68k_incpci(2);
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8 (1/0) */
/* 2 0,0   */

/* ADDA.W (An),An */
uae_u32 REGPARAM2 op_d0d0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 12;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = dst + src;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		areg_68000_long_replace_low(dstreg, newv);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	m68k_areg(regs, dstreg) = (newv);
	m68k_incpci(2);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (2/0) */
/* 2 0,0   */

/* ADDA.W (An)+,An */
uae_u32 REGPARAM2 op_d0d8_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 12;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) += 2 + 0;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) += 2;
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = dst + src;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		areg_68000_long_replace_low(dstreg, newv);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	m68k_areg(regs, dstreg) = (newv);
	m68k_incpci(2);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (2/0) */
/* 2 0,0   */

/* ADDA.W -(An),An */
uae_u32 REGPARAM2 op_d0e0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 12;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - 2;
	if (srca & 1) {
		m68k_incpci(4);
		m68k_areg(regs, srcreg) = srca;
		exception3_read_access(opcode, srca, 1, 1);
		return 2 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) = srca;
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = dst + src;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		areg_68000_long_replace_low(dstreg, newv);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	m68k_areg(regs, dstreg) = (newv);
	m68k_incpci(2);
	return 14 * CYCLE_UNIT / 2 + count_cycles;
}
/* 14 (2/0) */
/* 2 0,0   */

/* ADDA.W (d16,An),An */
uae_u32 REGPARAM2 op_d0e8_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 12;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = dst + src;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		areg_68000_long_replace_low(dstreg, newv);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	m68k_areg(regs, dstreg) = (newv);
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/0) */
/* 4 0,0   */

/* ADDA.W (d8,An,Xn),An */
uae_u32 REGPARAM2 op_d0f0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 12;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	BusCyclePenalty += 2;
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = dst + src;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		areg_68000_long_replace_low(dstreg, newv);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	m68k_areg(regs, dstreg) = (newv);
	m68k_incpci(4);
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (3/0) */
/* 4 4,0   */

/* ADDA.W (xxx).W,An */
uae_u32 REGPARAM2 op_d0f8_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 12;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, srca, 1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = dst + src;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		areg_68000_long_replace_low(dstreg, newv);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	m68k_areg(regs, dstreg) = (newv);
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/0) */
/* 4 0,0   */

/* ADDA.W (xxx).L,An */
uae_u32 REGPARAM2 op_d0f9_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 12;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	srca = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	srca |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, srca, 1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = dst + src;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		areg_68000_long_replace_low(dstreg, newv);
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	m68k_areg(regs, dstreg) = (newv);
	m68k_incpci(6);
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (4/0) */
/* 6 0,0   */

/* ADDA.W (d16,PC),An */
uae_u32 REGPARAM2 op_d0fa_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 12;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = m68k_getpci() + 2;
	srca += (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = dst + src;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		areg_68000_long_replace_low(dstreg, newv);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	m68k_areg(regs, dstreg) = (newv);
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/0) */
/* 4 0,0   */

/* ADDA.W (d8,PC,Xn),An */
uae_u32 REGPARAM2 op_d0fb_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 12;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	uaecptr tmppc = m68k_getpci() + 2;
	BusCyclePenalty += 2;
	srca = get_disp_ea_000(tmppc, get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = dst + src;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		areg_68000_long_replace_low(dstreg, newv);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	m68k_areg(regs, dstreg) = (newv);
	m68k_incpci(4);
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (3/0) */
/* 4 4,0   */

/* ADDA.W #<data>.W,An */
uae_u32 REGPARAM2 op_d0fc_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 12;
	CurrentInstrCycles = 12; 
	uae_s16 src = get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = dst + src;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		areg_68000_long_replace_low(dstreg, newv);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	m68k_areg(regs, dstreg) = (newv);
	m68k_incpci(4);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (2/0) */
/* 4 0,0   */

/* ADDX.B Dn,Dn */
uae_u32 REGPARAM2 op_d100_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 13;
	CurrentInstrCycles = 4;  
	uae_s8 src = m68k_dreg(regs, srcreg);
	uae_s8 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = dst + src + (GET_XFLG() ? 1 : 0);
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(flgs ^ ((flgs ^ flgo) & (flgo ^ flgn)));
	COPY_CARRY();
	SET_ZFLG(GET_ZFLG() & (((uae_s8)(newv)) == 0));
	SET_NFLG(((uae_s8)(newv)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
	m68k_incpci(2);
	return 4 * CYCLE_UNIT / 2 + count_cycles;
}
/* 4 (1/0) */
/* 2 0,0   */

/* ADDX.B -(An),-(An) */
uae_u32 REGPARAM2 op_d108_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 13;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
	uae_s8 src = get_byte_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x0, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) = srca;
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, dstreg) = dsta;
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) = dsta;
	uae_u32 newv = dst + src + (GET_XFLG() ? 1 : 0);
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(flgs ^ ((flgs ^ flgo) & (flgo ^ flgn)));
	COPY_CARRY();
	SET_ZFLG(GET_ZFLG() & (((uae_s8)(newv)) == 0));
	SET_NFLG(((uae_s8)(newv)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_byte_000(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, newv, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (3/1) */
/* 2 0,0   */

/* ADD.B Dn,(An) */
uae_u32 REGPARAM2 op_d110_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 12; 
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u8)(~dst)) < ((uae_u8)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_byte_000(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, newv, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (2/1) */
/* 2 0,0   */

/* ADD.B Dn,(An)+ */
uae_u32 REGPARAM2 op_d118_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 12; 
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
	uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u8)(~dst)) < ((uae_u8)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_byte_000(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, newv, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (2/1) */
/* 2 0,0   */

/* ADD.B Dn,-(An) */
uae_u32 REGPARAM2 op_d120_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 14; 
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, dstreg) = dsta;
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) = dsta;
	uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u8)(~dst)) < ((uae_u8)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_byte_000(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, newv, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 14 * CYCLE_UNIT / 2 + count_cycles;
}
/* 14 (2/1) */
/* 2 0,0   */

/* ADD.B Dn,(d16,An) */
uae_u32 REGPARAM2 op_d128_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 16; 
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u8)(~dst)) < ((uae_u8)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_byte_000(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, newv, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 4 0,0   */

/* ADD.B Dn,(d8,An,Xn) */
uae_u32 REGPARAM2 op_d130_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 18; 
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	BusCyclePenalty += 2;
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u8)(~dst)) < ((uae_u8)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_byte_000(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, newv, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (3/1) */
/* 4 4,0   */

/* ADD.B Dn,(xxx).W */
uae_u32 REGPARAM2 op_d138_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	OpcodeFamily = 11;
	CurrentInstrCycles = 16; 
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u8)(~dst)) < ((uae_u8)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_byte_000(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, newv, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 4 0,0   */

/* ADD.B Dn,(xxx).L */
uae_u32 REGPARAM2 op_d139_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	OpcodeFamily = 11;
	CurrentInstrCycles = 20; 
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	dsta |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s8 dst = get_byte_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u8)(~dst)) < ((uae_u8)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_byte_000(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, newv, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (4/1) */
/* 6 0,0   */

/* ADDX.W Dn,Dn */
uae_u32 REGPARAM2 op_d140_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 13;
	CurrentInstrCycles = 4;  
	uae_s16 src = m68k_dreg(regs, srcreg);
	uae_s16 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = dst + src + (GET_XFLG() ? 1 : 0);
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(flgs ^ ((flgs ^ flgo) & (flgo ^ flgn)));
	COPY_CARRY();
	SET_ZFLG(GET_ZFLG() & (((uae_s16)(newv)) == 0));
	SET_NFLG(((uae_s16)(newv)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
	m68k_incpci(2);
	return 4 * CYCLE_UNIT / 2 + count_cycles;
}
/* 4 (1/0) */
/* 2 0,0   */

/* ADDX.W -(An),-(An) */
uae_u32 REGPARAM2 op_d148_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 13;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - 2;
	if (srca & 1) {
		m68k_areg(regs, srcreg) = srca;
		m68k_incpci(4);
		exception3_read_access(opcode, srca, 1, 1);
		return 2 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 src = get_word_000(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) = srca;
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - 2;
	if (dsta & 1) {
		m68k_areg(regs, dstreg) = dsta;
		m68k_incpci(4);
		exception3_read_access(opcode, dsta, 1, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = get_word_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, dstreg) = dsta;
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) = dsta;
	uae_u32 newv = dst + src + (GET_XFLG() ? 1 : 0);
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(flgs ^ ((flgs ^ flgo) & (flgo ^ flgn)));
	COPY_CARRY();
	SET_ZFLG(GET_ZFLG() & (((uae_s16)(newv)) == 0));
	SET_NFLG(((uae_s16)(newv)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_word_000(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x1, newv, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (3/1) */
/* 2 0,0   */

/* ADD.W Dn,(An) */
uae_u32 REGPARAM2 op_d150_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 12; 
	uae_s16 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	if (dsta & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dsta, 1, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = get_word_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_word_000(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x1, newv, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (2/1) */
/* 2 0,0   */

/* ADD.W Dn,(An)+ */
uae_u32 REGPARAM2 op_d158_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 12; 
	uae_s16 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	if (dsta & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dsta, 1, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = get_word_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, dstreg) += 2 + 0;
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) += 2;
	uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_word_000(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x1, newv, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (2/1) */
/* 2 0,0   */

/* ADD.W Dn,-(An) */
uae_u32 REGPARAM2 op_d160_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 14; 
	uae_s16 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - 2;
	if (dsta & 1) {
		m68k_incpci(4);
		m68k_areg(regs, dstreg) = dsta;
		exception3_read_access(opcode, dsta, 1, 1);
		return 2 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = get_word_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, dstreg) = dsta;
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) = dsta;
	uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_word_000(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x1, newv, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 14 * CYCLE_UNIT / 2 + count_cycles;
}
/* 14 (2/1) */
/* 2 0,0   */

/* ADD.W Dn,(d16,An) */
uae_u32 REGPARAM2 op_d168_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 16; 
	uae_s16 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dsta, 1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = get_word_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_word_000(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x1, newv, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 4 0,0   */

/* ADD.W Dn,(d8,An,Xn) */
uae_u32 REGPARAM2 op_d170_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 18; 
	uae_s16 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	BusCyclePenalty += 2;
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dsta, 1, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = get_word_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_word_000(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x1, newv, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (3/1) */
/* 4 4,0   */

/* ADD.W Dn,(xxx).W */
uae_u32 REGPARAM2 op_d178_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	OpcodeFamily = 11;
	CurrentInstrCycles = 16; 
	uae_s16 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, dsta, 1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = get_word_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_word_000(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x1, newv, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 4 0,0   */

/* ADD.W Dn,(xxx).L */
uae_u32 REGPARAM2 op_d179_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	OpcodeFamily = 11;
	CurrentInstrCycles = 20; 
	uae_s16 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	dsta |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, dsta, 1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 dst = get_word_000(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	put_word_000(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x1, newv, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (4/1) */
/* 6 0,0   */

/* ADDX.L Dn,Dn */
uae_u32 REGPARAM2 op_d180_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 13;
	CurrentInstrCycles = 8;  
	uae_s32 src = m68k_dreg(regs, srcreg);
	uae_s32 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = dst + src + (GET_XFLG() ? 1 : 0);
	int oldz = GET_ZFLG();
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(flgs ^ ((flgs ^ flgo) & (flgo ^ flgn)));
	COPY_CARRY();
	SET_ZFLG(GET_ZFLG() & (((uae_s32)(newv)) == 0));
	SET_NFLG(((uae_s32)(newv)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		int bflgs = ((uae_s16)(src)) < 0;
		int bflgo = ((uae_s16)(dst)) < 0;
		int bflgn = ((uae_s16)(newv)) < 0;
		SET_VFLG((bflgs ^ bflgn) & (bflgo ^ bflgn));
		SET_CFLG(bflgs ^ ((bflgs ^ bflgo) & (bflgo ^ bflgn)));
		SET_XFLG(GET_CFLG());
		SET_ZFLG(oldz);
		if (newv & 0xffff) SET_ZFLG(0);
		SET_NFLG(newv & 0x8000); 
		dreg_68000_long_replace_low(dstreg, newv);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	m68k_dreg(regs, dstreg) = (newv);
	m68k_incpci(2);
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8 (1/0) */
/* 2 0,0   */

/* ADDX.L -(An),-(An) */
uae_u32 REGPARAM2 op_d188_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 13;
	CurrentInstrCycles = 30; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - 4;
	if (srca & 1) {
		m68k_incpci(4);
		srca += 2;
		exception3_read_access(opcode, srca, 2, 1);
		return 2 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) = srca;
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - 4;
	if (dsta & 1) {
		m68k_incpci(4);
		dsta += 2;
		exception3_read_access(opcode, dsta, 2, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = get_word_000(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	dst |= get_word_000(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) = dsta;
	uae_u32 newv = dst + src + (GET_XFLG() ? 1 : 0);
	int oldz = GET_ZFLG();
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(flgs ^ ((flgs ^ flgo) & (flgo ^ flgn)));
	COPY_CARRY();
	SET_ZFLG(GET_ZFLG() & (((uae_s32)(newv)) == 0));
	SET_NFLG(((uae_s32)(newv)) < 0);
	put_word_000(dsta + 2, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		int bflgs = ((uae_s16)(src)) < 0;
		int bflgo = ((uae_s16)(dst)) < 0;
		int bflgn = ((uae_s16)(newv)) < 0;
		SET_VFLG((bflgs ^ bflgn) & (bflgo ^ bflgn));
		SET_CFLG(bflgs ^ ((bflgs ^ bflgo) & (bflgo ^ bflgn)));
		COPY_CARRY();
		SET_ZFLG(GET_ZFLG() & (((uae_s16)(newv)) == 0));
		SET_NFLG(((uae_s16)(newv)) < 0);
		exception2_write(opcode, dsta + 2, 0x1, newv, 1);
		return 22 * CYCLE_UNIT / 2 + count_cycles;
	}
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 26 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, newv >> 16); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x1, newv >> 16, 1);
		return 30 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 30 * CYCLE_UNIT / 2 + count_cycles;
}
/* 30 (5/2) */
/* 2 0,0   */

/* ADD.L Dn,(An) */
uae_u32 REGPARAM2 op_d190_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 20; 
	uae_s32 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	if (dsta & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dsta, 2, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = get_word_000(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	dst |= get_word_000(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u32)(~dst)) < ((uae_u32)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		uae_s16 bnewv = (uae_s16)dst + (uae_s16)src;
		int bflgs = ((uae_s16)(src)) < 0;
		int bflgo = ((uae_s16)(dst)) < 0;
		int bflgn = bnewv < 0;
		ccr_68000_long_move_ae_LZN(bnewv);
		SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
		SET_XFLG(GET_CFLG());
		SET_VFLG((bflgs ^ bflgn) & (bflgo ^ bflgn));
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta + 2, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 2, 0x1, newv, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, newv >> 16); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x1, newv >> 16, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (3/2) */
/* 2 0,0   */

/* ADD.L Dn,(An)+ */
uae_u32 REGPARAM2 op_d198_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 20; 
	uae_s32 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	if (dsta & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dsta, 2, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = get_word_000(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	dst |= get_word_000(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) += 4;
	uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u32)(~dst)) < ((uae_u32)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		uae_s16 bnewv = (uae_s16)dst + (uae_s16)src;
		int bflgs = ((uae_s16)(src)) < 0;
		int bflgo = ((uae_s16)(dst)) < 0;
		int bflgn = bnewv < 0;
		ccr_68000_long_move_ae_LZN(bnewv);
		SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
		SET_XFLG(GET_CFLG());
		SET_VFLG((bflgs ^ bflgn) & (bflgo ^ bflgn));
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta + 2, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 2, 0x1, newv, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, newv >> 16); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x1, newv >> 16, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (3/2) */
/* 2 0,0   */

/* ADD.L Dn,-(An) */
uae_u32 REGPARAM2 op_d1a0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 22; 
	uae_s32 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - 4;
	if (dsta & 1) {
		m68k_incpci(2);
		m68k_areg(regs, dstreg) = dsta;
		exception3_read_access(opcode, dsta, 2, 1);
		return 2 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = get_word_000(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, dstreg) = dsta;
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	dst |= get_word_000(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, dstreg) = dsta;
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, dstreg) = dsta;
	uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u32)(~dst)) < ((uae_u32)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		uae_s16 bnewv = (uae_s16)dst + (uae_s16)src;
		int bflgs = ((uae_s16)(src)) < 0;
		int bflgo = ((uae_s16)(dst)) < 0;
		int bflgn = bnewv < 0;
		ccr_68000_long_move_ae_LZN(bnewv);
		SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
		SET_XFLG(GET_CFLG());
		SET_VFLG((bflgs ^ bflgn) & (bflgo ^ bflgn));
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta + 2, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 2, 0x1, newv, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, newv >> 16); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x1, newv >> 16, 1);
		return 22 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 22 * CYCLE_UNIT / 2 + count_cycles;
}
/* 22 (3/2) */
/* 2 0,0   */

/* ADD.L Dn,(d16,An) */
uae_u32 REGPARAM2 op_d1a8_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 24; 
	uae_s32 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dsta, 2, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = get_word_000(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	dst |= get_word_000(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u32)(~dst)) < ((uae_u32)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		uae_s16 bnewv = (uae_s16)dst + (uae_s16)src;
		int bflgs = ((uae_s16)(src)) < 0;
		int bflgo = ((uae_s16)(dst)) < 0;
		int bflgn = bnewv < 0;
		ccr_68000_long_move_ae_LZN(bnewv);
		SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
		SET_XFLG(GET_CFLG());
		SET_VFLG((bflgs ^ bflgn) & (bflgo ^ bflgn));
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta + 2, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 2, 0x1, newv, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, newv >> 16); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, newv >> 16, 1);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 24 * CYCLE_UNIT / 2 + count_cycles;
}
/* 24 (4/2) */
/* 4 0,0   */

/* ADD.L Dn,(d8,An,Xn) */
uae_u32 REGPARAM2 op_d1b0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 26; 
	uae_s32 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	BusCyclePenalty += 2;
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dsta, 2, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = get_word_000(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	dst |= get_word_000(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u32)(~dst)) < ((uae_u32)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		uae_s16 bnewv = (uae_s16)dst + (uae_s16)src;
		int bflgs = ((uae_s16)(src)) < 0;
		int bflgo = ((uae_s16)(dst)) < 0;
		int bflgn = bnewv < 0;
		ccr_68000_long_move_ae_LZN(bnewv);
		SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
		SET_XFLG(GET_CFLG());
		SET_VFLG((bflgs ^ bflgn) & (bflgo ^ bflgn));
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta + 2, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 2, 0x1, newv, 1);
		return 22 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, newv >> 16); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, newv >> 16, 1);
		return 26 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 26 * CYCLE_UNIT / 2 + count_cycles;
}
/* 26 (4/2) */
/* 4 4,0   */

/* ADD.L Dn,(xxx).W */
uae_u32 REGPARAM2 op_d1b8_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	OpcodeFamily = 11;
	CurrentInstrCycles = 24; 
	uae_s32 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, dsta, 2, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = get_word_000(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	dst |= get_word_000(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u32)(~dst)) < ((uae_u32)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		uae_s16 bnewv = (uae_s16)dst + (uae_s16)src;
		int bflgs = ((uae_s16)(src)) < 0;
		int bflgo = ((uae_s16)(dst)) < 0;
		int bflgn = bnewv < 0;
		ccr_68000_long_move_ae_LZN(bnewv);
		SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
		SET_XFLG(GET_CFLG());
		SET_VFLG((bflgs ^ bflgn) & (bflgo ^ bflgn));
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta + 2, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 2, 0x1, newv, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, newv >> 16); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, newv >> 16, 1);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 24 * CYCLE_UNIT / 2 + count_cycles;
}
/* 24 (4/2) */
/* 4 0,0   */

/* ADD.L Dn,(xxx).L */
uae_u32 REGPARAM2 op_d1b9_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	OpcodeFamily = 11;
	CurrentInstrCycles = 28; 
	uae_s32 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	dsta |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dsta & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, dsta, 2, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = get_word_000(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	dst |= get_word_000(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u32)(~dst)) < ((uae_u32)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		uae_s16 bnewv = (uae_s16)dst + (uae_s16)src;
		int bflgs = ((uae_s16)(src)) < 0;
		int bflgo = ((uae_s16)(dst)) < 0;
		int bflgn = bnewv < 0;
		ccr_68000_long_move_ae_LZN(bnewv);
		SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
		SET_XFLG(GET_CFLG());
		SET_VFLG((bflgs ^ bflgn) & (bflgo ^ bflgn));
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta + 2, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 2, 0x1, newv, 1);
		return 24 * CYCLE_UNIT / 2 + count_cycles;
	}
	put_word_000(dsta, newv >> 16); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 0, 0x1, newv >> 16, 1);
		return 28 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 28 * CYCLE_UNIT / 2 + count_cycles;
}
/* 28 (5/2) */
/* 6 0,0   */

/* ADDA.L Dn,An */
uae_u32 REGPARAM2 op_d1c0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 12;
	CurrentInstrCycles = 8;  
	uae_s32 src = m68k_dreg(regs, srcreg);
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = dst + src;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		areg_68000_long_replace_low(dstreg, newv);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	m68k_areg(regs, dstreg) = (newv);
	m68k_incpci(2);
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8 (1/0) */
/* 2 0,0   */

/* ADDA.L An,An */
uae_u32 REGPARAM2 op_d1c8_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 12;
	CurrentInstrCycles = 8;  
	uae_s32 src = m68k_areg(regs, srcreg);
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = dst + src;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		areg_68000_long_replace_low(dstreg, newv);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	m68k_areg(regs, dstreg) = (newv);
	m68k_incpci(2);
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8 (1/0) */
/* 2 0,0   */

/* ADDA.L (An),An */
uae_u32 REGPARAM2 op_d1d0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 12;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = dst + src;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		areg_68000_long_replace_low(dstreg, newv);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	m68k_areg(regs, dstreg) = (newv);
	m68k_incpci(2);
	return 14 * CYCLE_UNIT / 2 + count_cycles;
}
/* 14 (3/0) */
/* 2 0,0   */

/* ADDA.L (An)+,An */
uae_u32 REGPARAM2 op_d1d8_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 12;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) += 4;
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = dst + src;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		areg_68000_long_replace_low(dstreg, newv);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	m68k_areg(regs, dstreg) = (newv);
	m68k_incpci(2);
	return 14 * CYCLE_UNIT / 2 + count_cycles;
}
/* 14 (3/0) */
/* 2 0,0   */

/* ADDA.L -(An),An */
uae_u32 REGPARAM2 op_d1e0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 12;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - 4;
	if (srca & 1) {
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception3_read_access(opcode, srca, 2, 1);
		return 2 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) = srca;
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = dst + src;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		areg_68000_long_replace_low(dstreg, newv);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	m68k_areg(regs, dstreg) = (newv);
	m68k_incpci(2);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/0) */
/* 2 0,0   */

/* ADDA.L (d16,An),An */
uae_u32 REGPARAM2 op_d1e8_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 12;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = dst + src;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		areg_68000_long_replace_low(dstreg, newv);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	m68k_areg(regs, dstreg) = (newv);
	m68k_incpci(4);
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (4/0) */
/* 4 0,0   */

/* ADDA.L (d8,An,Xn),An */
uae_u32 REGPARAM2 op_d1f0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 12;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	BusCyclePenalty += 2;
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = dst + src;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		areg_68000_long_replace_low(dstreg, newv);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	m68k_areg(regs, dstreg) = (newv);
	m68k_incpci(4);
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (4/0) */
/* 4 4,0   */

/* ADDA.L (xxx).W,An */
uae_u32 REGPARAM2 op_d1f8_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 12;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, srca, 2, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = dst + src;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		areg_68000_long_replace_low(dstreg, newv);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	m68k_areg(regs, dstreg) = (newv);
	m68k_incpci(4);
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (4/0) */
/* 4 0,0   */

/* ADDA.L (xxx).L,An */
uae_u32 REGPARAM2 op_d1f9_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 12;
	CurrentInstrCycles = 22; 
	uaecptr srca;
	srca = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	srca |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, srca, 2, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = dst + src;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		areg_68000_long_replace_low(dstreg, newv);
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	m68k_areg(regs, dstreg) = (newv);
	m68k_incpci(6);
	return 22 * CYCLE_UNIT / 2 + count_cycles;
}
/* 22 (5/0) */
/* 6 0,0   */

/* ADDA.L (d16,PC),An */
uae_u32 REGPARAM2 op_d1fa_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 12;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	srca = m68k_getpci() + 2;
	srca += (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 2);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = dst + src;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		areg_68000_long_replace_low(dstreg, newv);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	m68k_areg(regs, dstreg) = (newv);
	m68k_incpci(4);
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (4/0) */
/* 4 0,0   */

/* ADDA.L (d8,PC,Xn),An */
uae_u32 REGPARAM2 op_d1fb_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 12;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	uaecptr tmppc = m68k_getpci() + 2;
	BusCyclePenalty += 2;
	srca = get_disp_ea_000(tmppc, get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 src = get_word_000(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 2);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = dst + src;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		areg_68000_long_replace_low(dstreg, newv);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	m68k_areg(regs, dstreg) = (newv);
	m68k_incpci(4);
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (4/0) */
/* 4 4,0   */

/* ADDA.L #<data>.L,An */
uae_u32 REGPARAM2 op_d1fc_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 12;
	CurrentInstrCycles = 16; 
	uae_s32 src;
	src = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	src |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = dst + src;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		areg_68000_long_replace_low(dstreg, newv);
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	m68k_areg(regs, dstreg) = (newv);
	m68k_incpci(6);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/0) */
/* 6 0,0   */

/* ASRQ.B #<data>,Dn */
uae_u32 REGPARAM2 op_e000_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 64;
	CurrentInstrCycles = 6;  
	uae_u32 cnt = srcreg;
	uae_s8 data = m68k_dreg(regs, dstreg);
	uae_u32 val = (uae_u8)data;
	CLEAR_CZNV();
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		SET_ZFLG(!(val & 0xff));
		SET_NFLG(val & 0x80);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	uae_u32 sign = (0x80 & val) >> 7;
	int ccnt = cnt & 63;
	cnt &= 63;
	if (cnt >= 8) {
		val = 0xff & (uae_u32)(0 - sign);
		SET_CFLG(sign);
		COPY_CARRY();
	} else {
		val >>= cnt - 1;
		SET_CFLG(val & 1);
		COPY_CARRY();
		val >>= 1;
		val |= (0xff << (8 - cnt)) & (uae_u32)(0 - sign);
		val &= 0xff;
	}
	SET_ZFLG(((uae_s8)(val)) == 0);
	SET_NFLG(((uae_s8)(val)) < 0);
	count_cycles += (2 * ccnt) * CYCLE_UNIT / 2;
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((val) & 0xff);
	m68k_incpci(2);
	return 6 * CYCLE_UNIT / 2 + count_cycles;
}
/* 6+ (1/0) */
/* 2 0,0   */

/* LSRQ.B #<data>,Dn */
uae_u32 REGPARAM2 op_e008_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 66;
	CurrentInstrCycles = 6;  
	uae_u32 cnt = srcreg;
	uae_s8 data = m68k_dreg(regs, dstreg);
	uae_u32 val = (uae_u8)data;
	CLEAR_CZNV();
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		SET_ZFLG(!(val & 0xff));
		SET_NFLG(val & 0x80);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int ccnt = cnt & 63;
	cnt &= 63;
	if (cnt >= 8) {
		SET_CFLG((cnt == 8) & (val >> 7));
		COPY_CARRY();
		val = 0;
	} else {
		val >>= cnt - 1;
		SET_CFLG(val & 1);
		COPY_CARRY();
		val >>= 1;
	}
	SET_ZFLG(((uae_s8)(val)) == 0);
	SET_NFLG(((uae_s8)(val)) < 0);
	count_cycles += (2 * ccnt) * CYCLE_UNIT / 2;
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((val) & 0xff);
	m68k_incpci(2);
	return 6 * CYCLE_UNIT / 2 + count_cycles;
}
/* 6+ (1/0) */
/* 2 0,0   */

/* ROXRQ.B #<data>,Dn */
uae_u32 REGPARAM2 op_e010_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 71;
	CurrentInstrCycles = 6;  
	uae_u32 cnt = srcreg;
	uae_s8 data = m68k_dreg(regs, dstreg);
	uae_u32 val = (uae_u8)data;
	CLEAR_CZNV();
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		SET_ZFLG(!(val & 0xff));
		SET_NFLG(val & 0x80);
		SET_CFLG(GET_XFLG());
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int ccnt = cnt & 63;
	cnt &= 63;
	{
		cnt--;
		{
			uae_u32 carry;
			uae_u32 hival = (val << 1) | GET_XFLG();
			hival <<= (7 - cnt);
			val >>= cnt;
			carry = val & 1;
			val >>= 1;
			val |= hival;
			SET_XFLG(carry);
			val &= 0xff;
		}
	}
	SET_CFLG(GET_XFLG());
	SET_ZFLG(((uae_s8)(val)) == 0);
	SET_NFLG(((uae_s8)(val)) < 0);
	count_cycles += (2 * ccnt) * CYCLE_UNIT / 2;
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((val) & 0xff);
	m68k_incpci(2);
	return 6 * CYCLE_UNIT / 2 + count_cycles;
}
/* 6+ (1/0) */
/* 2 0,0   */

/* RORQ.B #<data>,Dn */
uae_u32 REGPARAM2 op_e018_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 69;
	CurrentInstrCycles = 6;  
	uae_u32 cnt = srcreg;
	uae_s8 data = m68k_dreg(regs, dstreg);
	uae_u32 val = (uae_u8)data;
	CLEAR_CZNV();
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		SET_ZFLG(!(val & 0xff));
		SET_NFLG(val & 0x80);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int ccnt = cnt & 63;
	cnt &= 63;
	{
		uae_u32 hival;
		cnt &= 7;
		hival = val << (8 - cnt);
		val >>= cnt;
		val |= hival;
		val &= 0xff;
		SET_CFLG((val & 0x80) >> 7);
	}
	SET_ZFLG(((uae_s8)(val)) == 0);
	SET_NFLG(((uae_s8)(val)) < 0);
	count_cycles += (2 * ccnt) * CYCLE_UNIT / 2;
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((val) & 0xff);
	m68k_incpci(2);
	return 6 * CYCLE_UNIT / 2 + count_cycles;
}
/* 6+ (1/0) */
/* 2 0,0   */

/* ASR.B Dn,Dn */
uae_u32 REGPARAM2 op_e020_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 64;
	CurrentInstrCycles = 6;  
	uae_s8 cnt = m68k_dreg(regs, srcreg);
	uae_s8 data = m68k_dreg(regs, dstreg);
	uae_u32 val = (uae_u8)data;
	CLEAR_CZNV();
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		SET_ZFLG(!(val & 0xff));
		SET_NFLG(val & 0x80);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	uae_u32 sign = (0x80 & val) >> 7;
	int ccnt = cnt & 63;
	cnt &= 63;
	if (cnt >= 8) {
		val = 0xff & (uae_u32)(0 - sign);
		SET_CFLG(sign);
		COPY_CARRY();
	} else if (cnt > 0) {
		val >>= cnt - 1;
		SET_CFLG(val & 1);
		COPY_CARRY();
		val >>= 1;
		val |= (0xff << (8 - cnt)) & (uae_u32)(0 - sign);
		val &= 0xff;
	}
	SET_ZFLG(((uae_s8)(val)) == 0);
	SET_NFLG(((uae_s8)(val)) < 0);
	count_cycles += (2 * ccnt) * CYCLE_UNIT / 2;
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((val) & 0xff);
	m68k_incpci(2);
	return 6 * CYCLE_UNIT / 2 + count_cycles;
}
/* 6+ (1/0) */
/* 2 0,0   */

/* LSR.B Dn,Dn */
uae_u32 REGPARAM2 op_e028_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 66;
	CurrentInstrCycles = 6;  
	uae_s8 cnt = m68k_dreg(regs, srcreg);
	uae_s8 data = m68k_dreg(regs, dstreg);
	uae_u32 val = (uae_u8)data;
	CLEAR_CZNV();
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		SET_ZFLG(!(val & 0xff));
		SET_NFLG(val & 0x80);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int ccnt = cnt & 63;
	cnt &= 63;
	if (cnt >= 8) {
		SET_CFLG((cnt == 8) & (val >> 7));
		COPY_CARRY();
		val = 0;
	} else if (cnt > 0) {
		val >>= cnt - 1;
		SET_CFLG(val & 1);
		COPY_CARRY();
		val >>= 1;
	}
	SET_ZFLG(((uae_s8)(val)) == 0);
	SET_NFLG(((uae_s8)(val)) < 0);
	count_cycles += (2 * ccnt) * CYCLE_UNIT / 2;
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((val) & 0xff);
	m68k_incpci(2);
	return 6 * CYCLE_UNIT / 2 + count_cycles;
}
/* 6+ (1/0) */
/* 2 0,0   */

/* ROXR.B Dn,Dn */
uae_u32 REGPARAM2 op_e030_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 71;
	CurrentInstrCycles = 6;  
	uae_s8 cnt = m68k_dreg(regs, srcreg);
	uae_s8 data = m68k_dreg(regs, dstreg);
	uae_u32 val = (uae_u8)data;
	CLEAR_CZNV();
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		SET_ZFLG(!(val & 0xff));
		SET_NFLG(val & 0x80);
		SET_CFLG(GET_XFLG());
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int ccnt = cnt & 63;
	cnt &= 63;
	if (cnt >= 36) cnt -= 36;
	if (cnt >= 18) cnt -= 18;
	if (cnt >= 9) cnt -= 9;
	if (cnt > 0) {
		cnt--;
		{
			uae_u32 carry;
			uae_u32 hival = (val << 1) | GET_XFLG();
			hival <<= (7 - cnt);
			val >>= cnt;
			carry = val & 1;
			val >>= 1;
			val |= hival;
			SET_XFLG(carry);
			val &= 0xff;
		}
	}
	SET_CFLG(GET_XFLG());
	SET_ZFLG(((uae_s8)(val)) == 0);
	SET_NFLG(((uae_s8)(val)) < 0);
	count_cycles += (2 * ccnt) * CYCLE_UNIT / 2;
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((val) & 0xff);
	m68k_incpci(2);
	return 6 * CYCLE_UNIT / 2 + count_cycles;
}
/* 6+ (1/0) */
/* 2 0,0   */

/* ROR.B Dn,Dn */
uae_u32 REGPARAM2 op_e038_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 69;
	CurrentInstrCycles = 6;  
	uae_s8 cnt = m68k_dreg(regs, srcreg);
	uae_s8 data = m68k_dreg(regs, dstreg);
	uae_u32 val = (uae_u8)data;
	CLEAR_CZNV();
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		SET_ZFLG(!(val & 0xff));
		SET_NFLG(val & 0x80);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int ccnt = cnt & 63;
	cnt &= 63;
	if (cnt > 0) {
		uae_u32 hival;
		cnt &= 7;
		hival = val << (8 - cnt);
		val >>= cnt;
		val |= hival;
		val &= 0xff;
		SET_CFLG((val & 0x80) >> 7);
	}
	SET_ZFLG(((uae_s8)(val)) == 0);
	SET_NFLG(((uae_s8)(val)) < 0);
	count_cycles += (2 * ccnt) * CYCLE_UNIT / 2;
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((val) & 0xff);
	m68k_incpci(2);
	return 6 * CYCLE_UNIT / 2 + count_cycles;
}
/* 6+ (1/0) */
/* 2 0,0   */

/* ASRQ.W #<data>,Dn */
uae_u32 REGPARAM2 op_e040_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 64;
	CurrentInstrCycles = 6;  
	uae_u32 cnt = srcreg;
	uae_s16 data = m68k_dreg(regs, dstreg);
	uae_u32 val = (uae_u16)data;
	CLEAR_CZNV();
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		SET_ZFLG(!(val & 0xffff));
		SET_NFLG(val & 0x8000);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	uae_u32 sign = (0x8000 & val) >> 15;
	int ccnt = cnt & 63;
	cnt &= 63;
	if (cnt >= 16) {
		val = 0xffff & (uae_u32)(0 - sign);
		SET_CFLG(sign);
		COPY_CARRY();
	} else {
		val >>= cnt - 1;
		SET_CFLG(val & 1);
		COPY_CARRY();
		val >>= 1;
		val |= (0xffff << (16 - cnt)) & (uae_u32)(0 - sign);
		val &= 0xffff;
	}
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	count_cycles += (2 * ccnt) * CYCLE_UNIT / 2;
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((val) & 0xffff);
	m68k_incpci(2);
	return 6 * CYCLE_UNIT / 2 + count_cycles;
}
/* 6+ (1/0) */
/* 2 0,0   */

/* LSRQ.W #<data>,Dn */
uae_u32 REGPARAM2 op_e048_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 66;
	CurrentInstrCycles = 6;  
	uae_u32 cnt = srcreg;
	uae_s16 data = m68k_dreg(regs, dstreg);
	uae_u32 val = (uae_u16)data;
	CLEAR_CZNV();
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		SET_ZFLG(!(val & 0xffff));
		SET_NFLG(val & 0x8000);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int ccnt = cnt & 63;
	cnt &= 63;
	if (cnt >= 16) {
		SET_CFLG((cnt == 16) & (val >> 15));
		COPY_CARRY();
		val = 0;
	} else {
		val >>= cnt - 1;
		SET_CFLG(val & 1);
		COPY_CARRY();
		val >>= 1;
	}
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	count_cycles += (2 * ccnt) * CYCLE_UNIT / 2;
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((val) & 0xffff);
	m68k_incpci(2);
	return 6 * CYCLE_UNIT / 2 + count_cycles;
}
/* 6+ (1/0) */
/* 2 0,0   */

/* ROXRQ.W #<data>,Dn */
uae_u32 REGPARAM2 op_e050_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 71;
	CurrentInstrCycles = 6;  
	uae_u32 cnt = srcreg;
	uae_s16 data = m68k_dreg(regs, dstreg);
	uae_u32 val = (uae_u16)data;
	CLEAR_CZNV();
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		SET_ZFLG(!(val & 0xffff));
		SET_NFLG(val & 0x8000);
		SET_CFLG(GET_XFLG());
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int ccnt = cnt & 63;
	cnt &= 63;
	{
		cnt--;
		{
			uae_u32 carry;
			uae_u32 hival = (val << 1) | GET_XFLG();
			hival <<= (15 - cnt);
			val >>= cnt;
			carry = val & 1;
			val >>= 1;
			val |= hival;
			SET_XFLG(carry);
			val &= 0xffff;
		}
	}
	SET_CFLG(GET_XFLG());
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	count_cycles += (2 * ccnt) * CYCLE_UNIT / 2;
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((val) & 0xffff);
	m68k_incpci(2);
	return 6 * CYCLE_UNIT / 2 + count_cycles;
}
/* 6+ (1/0) */
/* 2 0,0   */

/* RORQ.W #<data>,Dn */
uae_u32 REGPARAM2 op_e058_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 69;
	CurrentInstrCycles = 6;  
	uae_u32 cnt = srcreg;
	uae_s16 data = m68k_dreg(regs, dstreg);
	uae_u32 val = (uae_u16)data;
	CLEAR_CZNV();
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		SET_ZFLG(!(val & 0xffff));
		SET_NFLG(val & 0x8000);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int ccnt = cnt & 63;
	cnt &= 63;
	{
		uae_u32 hival;
		cnt &= 15;
		hival = val << (16 - cnt);
		val >>= cnt;
		val |= hival;
		val &= 0xffff;
		SET_CFLG((val & 0x8000) >> 15);
	}
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	count_cycles += (2 * ccnt) * CYCLE_UNIT / 2;
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((val) & 0xffff);
	m68k_incpci(2);
	return 6 * CYCLE_UNIT / 2 + count_cycles;
}
/* 6+ (1/0) */
/* 2 0,0   */

/* ASR.W Dn,Dn */
uae_u32 REGPARAM2 op_e060_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 64;
	CurrentInstrCycles = 6;  
	uae_s16 cnt = m68k_dreg(regs, srcreg);
	uae_s16 data = m68k_dreg(regs, dstreg);
	uae_u32 val = (uae_u16)data;
	CLEAR_CZNV();
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		SET_ZFLG(!(val & 0xffff));
		SET_NFLG(val & 0x8000);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	uae_u32 sign = (0x8000 & val) >> 15;
	int ccnt = cnt & 63;
	cnt &= 63;
	if (cnt >= 16) {
		val = 0xffff & (uae_u32)(0 - sign);
		SET_CFLG(sign);
		COPY_CARRY();
	} else if (cnt > 0) {
		val >>= cnt - 1;
		SET_CFLG(val & 1);
		COPY_CARRY();
		val >>= 1;
		val |= (0xffff << (16 - cnt)) & (uae_u32)(0 - sign);
		val &= 0xffff;
	}
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	count_cycles += (2 * ccnt) * CYCLE_UNIT / 2;
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((val) & 0xffff);
	m68k_incpci(2);
	return 6 * CYCLE_UNIT / 2 + count_cycles;
}
/* 6+ (1/0) */
/* 2 0,0   */

/* LSR.W Dn,Dn */
uae_u32 REGPARAM2 op_e068_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 66;
	CurrentInstrCycles = 6;  
	uae_s16 cnt = m68k_dreg(regs, srcreg);
	uae_s16 data = m68k_dreg(regs, dstreg);
	uae_u32 val = (uae_u16)data;
	CLEAR_CZNV();
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		SET_ZFLG(!(val & 0xffff));
		SET_NFLG(val & 0x8000);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int ccnt = cnt & 63;
	cnt &= 63;
	if (cnt >= 16) {
		SET_CFLG((cnt == 16) & (val >> 15));
		COPY_CARRY();
		val = 0;
	} else if (cnt > 0) {
		val >>= cnt - 1;
		SET_CFLG(val & 1);
		COPY_CARRY();
		val >>= 1;
	}
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	count_cycles += (2 * ccnt) * CYCLE_UNIT / 2;
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((val) & 0xffff);
	m68k_incpci(2);
	return 6 * CYCLE_UNIT / 2 + count_cycles;
}
/* 6+ (1/0) */
/* 2 0,0   */

/* ROXR.W Dn,Dn */
uae_u32 REGPARAM2 op_e070_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 71;
	CurrentInstrCycles = 6;  
	uae_s16 cnt = m68k_dreg(regs, srcreg);
	uae_s16 data = m68k_dreg(regs, dstreg);
	uae_u32 val = (uae_u16)data;
	CLEAR_CZNV();
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		SET_ZFLG(!(val & 0xffff));
		SET_NFLG(val & 0x8000);
		SET_CFLG(GET_XFLG());
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int ccnt = cnt & 63;
	cnt &= 63;
	if (cnt >= 34) cnt -= 34;
	if (cnt >= 17) cnt -= 17;
	if (cnt > 0) {
		cnt--;
		{
			uae_u32 carry;
			uae_u32 hival = (val << 1) | GET_XFLG();
			hival <<= (15 - cnt);
			val >>= cnt;
			carry = val & 1;
			val >>= 1;
			val |= hival;
			SET_XFLG(carry);
			val &= 0xffff;
		}
	}
	SET_CFLG(GET_XFLG());
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	count_cycles += (2 * ccnt) * CYCLE_UNIT / 2;
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((val) & 0xffff);
	m68k_incpci(2);
	return 6 * CYCLE_UNIT / 2 + count_cycles;
}
/* 6+ (1/0) */
/* 2 0,0   */

/* ROR.W Dn,Dn */
uae_u32 REGPARAM2 op_e078_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 69;
	CurrentInstrCycles = 6;  
	uae_s16 cnt = m68k_dreg(regs, srcreg);
	uae_s16 data = m68k_dreg(regs, dstreg);
	uae_u32 val = (uae_u16)data;
	CLEAR_CZNV();
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		SET_ZFLG(!(val & 0xffff));
		SET_NFLG(val & 0x8000);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int ccnt = cnt & 63;
	cnt &= 63;
	if (cnt > 0) {
		uae_u32 hival;
		cnt &= 15;
		hival = val << (16 - cnt);
		val >>= cnt;
		val |= hival;
		val &= 0xffff;
		SET_CFLG((val & 0x8000) >> 15);
	}
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	count_cycles += (2 * ccnt) * CYCLE_UNIT / 2;
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((val) & 0xffff);
	m68k_incpci(2);
	return 6 * CYCLE_UNIT / 2 + count_cycles;
}
/* 6+ (1/0) */
/* 2 0,0   */

/* ASRQ.L #<data>,Dn */
uae_u32 REGPARAM2 op_e080_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 64;
	CurrentInstrCycles = 8;  
	uae_u32 cnt = srcreg;
	uae_s32 data = m68k_dreg(regs, dstreg);
	uae_u32 val = data;
	CLEAR_CZNV();
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		SET_NFLG(val & 0x8000);
		SET_ZFLG(!(val & 0xffff));
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	uae_u32 sign = (0x80000000 & val) >> 31;
	int ccnt = cnt & 63;
	cnt &= 63;
	if (cnt >= 32) {
		val = 0xffffffff & (uae_u32)(0 - sign);
		SET_CFLG(sign);
		COPY_CARRY();
	} else {
		val >>= cnt - 1;
		SET_CFLG(val & 1);
		COPY_CARRY();
		val >>= 1;
		val |= (0xffffffff << (32 - cnt)) & (uae_u32)(0 - sign);
		val &= 0xffffffff;
	}
	SET_ZFLG(((uae_s32)(val)) == 0);
	SET_NFLG(((uae_s32)(val)) < 0);
	count_cycles += (2 * ccnt) * CYCLE_UNIT / 2;
	m68k_dreg(regs, dstreg) = (val);
	m68k_incpci(2);
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8+ (1/0) */
/* 2 0,0   */

/* LSRQ.L #<data>,Dn */
uae_u32 REGPARAM2 op_e088_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 66;
	CurrentInstrCycles = 8;  
	uae_u32 cnt = srcreg;
	uae_s32 data = m68k_dreg(regs, dstreg);
	uae_u32 val = data;
	CLEAR_CZNV();
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		SET_NFLG(val & 0x8000);
		SET_ZFLG(!(val & 0xffff));
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int ccnt = cnt & 63;
	cnt &= 63;
	if (cnt >= 32) {
		SET_CFLG((cnt == 32) & (val >> 31));
		COPY_CARRY();
		val = 0;
	} else {
		val >>= cnt - 1;
		SET_CFLG(val & 1);
		COPY_CARRY();
		val >>= 1;
	}
	SET_ZFLG(((uae_s32)(val)) == 0);
	SET_NFLG(((uae_s32)(val)) < 0);
	count_cycles += (2 * ccnt) * CYCLE_UNIT / 2;
	m68k_dreg(regs, dstreg) = (val);
	m68k_incpci(2);
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8+ (1/0) */
/* 2 0,0   */

/* ROXRQ.L #<data>,Dn */
uae_u32 REGPARAM2 op_e090_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 71;
	CurrentInstrCycles = 8;  
	uae_u32 cnt = srcreg;
	uae_s32 data = m68k_dreg(regs, dstreg);
	uae_u32 val = data;
	CLEAR_CZNV();
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		SET_NFLG(val & 0x8000);
		SET_ZFLG(!(val & 0xffff));
		SET_CFLG(GET_XFLG());
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int ccnt = cnt & 63;
	cnt &= 63;
	{
		cnt--;
		{
			uae_u32 carry;
			uae_u32 hival = (val << 1) | GET_XFLG();
			hival <<= (31 - cnt);
			val >>= cnt;
			carry = val & 1;
			val >>= 1;
			val |= hival;
			SET_XFLG(carry);
			val &= 0xffffffff;
		}
	}
	SET_CFLG(GET_XFLG());
	SET_ZFLG(((uae_s32)(val)) == 0);
	SET_NFLG(((uae_s32)(val)) < 0);
	count_cycles += (2 * ccnt) * CYCLE_UNIT / 2;
	m68k_dreg(regs, dstreg) = (val);
	m68k_incpci(2);
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8+ (1/0) */
/* 2 0,0   */

/* RORQ.L #<data>,Dn */
uae_u32 REGPARAM2 op_e098_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 69;
	CurrentInstrCycles = 8;  
	uae_u32 cnt = srcreg;
	uae_s32 data = m68k_dreg(regs, dstreg);
	uae_u32 val = data;
	CLEAR_CZNV();
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		SET_NFLG(val & 0x8000);
		SET_ZFLG(!(val & 0xffff));
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int ccnt = cnt & 63;
	cnt &= 63;
	{
		uae_u32 hival;
		cnt &= 31;
		hival = val << (32 - cnt);
		val >>= cnt;
		val |= hival;
		val &= 0xffffffff;
		SET_CFLG((val & 0x80000000) >> 31);
	}
	SET_ZFLG(((uae_s32)(val)) == 0);
	SET_NFLG(((uae_s32)(val)) < 0);
	count_cycles += (2 * ccnt) * CYCLE_UNIT / 2;
	m68k_dreg(regs, dstreg) = (val);
	m68k_incpci(2);
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8+ (1/0) */
/* 2 0,0   */

/* ASR.L Dn,Dn */
uae_u32 REGPARAM2 op_e0a0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 64;
	CurrentInstrCycles = 8;  
	uae_s32 cnt = m68k_dreg(regs, srcreg);
	uae_s32 data = m68k_dreg(regs, dstreg);
	uae_u32 val = data;
	CLEAR_CZNV();
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		SET_NFLG(val & 0x8000);
		SET_ZFLG(!(val & 0xffff));
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	uae_u32 sign = (0x80000000 & val) >> 31;
	int ccnt = cnt & 63;
	cnt &= 63;
	if (cnt >= 32) {
		val = 0xffffffff & (uae_u32)(0 - sign);
		SET_CFLG(sign);
		COPY_CARRY();
	} else if (cnt > 0) {
		val >>= cnt - 1;
		SET_CFLG(val & 1);
		COPY_CARRY();
		val >>= 1;
		val |= (0xffffffff << (32 - cnt)) & (uae_u32)(0 - sign);
		val &= 0xffffffff;
	}
	SET_ZFLG(((uae_s32)(val)) == 0);
	SET_NFLG(((uae_s32)(val)) < 0);
	count_cycles += (2 * ccnt) * CYCLE_UNIT / 2;
	m68k_dreg(regs, dstreg) = (val);
	m68k_incpci(2);
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8+ (1/0) */
/* 2 0,0   */

/* LSR.L Dn,Dn */
uae_u32 REGPARAM2 op_e0a8_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 66;
	CurrentInstrCycles = 8;  
	uae_s32 cnt = m68k_dreg(regs, srcreg);
	uae_s32 data = m68k_dreg(regs, dstreg);
	uae_u32 val = data;
	CLEAR_CZNV();
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		SET_NFLG(val & 0x8000);
		SET_ZFLG(!(val & 0xffff));
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int ccnt = cnt & 63;
	cnt &= 63;
	if (cnt >= 32) {
		SET_CFLG((cnt == 32) & (val >> 31));
		COPY_CARRY();
		val = 0;
	} else if (cnt > 0) {
		val >>= cnt - 1;
		SET_CFLG(val & 1);
		COPY_CARRY();
		val >>= 1;
	}
	SET_ZFLG(((uae_s32)(val)) == 0);
	SET_NFLG(((uae_s32)(val)) < 0);
	count_cycles += (2 * ccnt) * CYCLE_UNIT / 2;
	m68k_dreg(regs, dstreg) = (val);
	m68k_incpci(2);
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8+ (1/0) */
/* 2 0,0   */

/* ROXR.L Dn,Dn */
uae_u32 REGPARAM2 op_e0b0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 71;
	CurrentInstrCycles = 8;  
	uae_s32 cnt = m68k_dreg(regs, srcreg);
	uae_s32 data = m68k_dreg(regs, dstreg);
	uae_u32 val = data;
	CLEAR_CZNV();
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		SET_NFLG(val & 0x8000);
		SET_ZFLG(!(val & 0xffff));
		SET_CFLG(GET_XFLG());
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int ccnt = cnt & 63;
	cnt &= 63;
	if (cnt >= 33) cnt -= 33;
	if (cnt > 0) {
		cnt--;
		{
			uae_u32 carry;
			uae_u32 hival = (val << 1) | GET_XFLG();
			hival <<= (31 - cnt);
			val >>= cnt;
			carry = val & 1;
			val >>= 1;
			val |= hival;
			SET_XFLG(carry);
			val &= 0xffffffff;
		}
	}
	SET_CFLG(GET_XFLG());
	SET_ZFLG(((uae_s32)(val)) == 0);
	SET_NFLG(((uae_s32)(val)) < 0);
	count_cycles += (2 * ccnt) * CYCLE_UNIT / 2;
	m68k_dreg(regs, dstreg) = (val);
	m68k_incpci(2);
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8+ (1/0) */
/* 2 0,0   */

/* ROR.L Dn,Dn */
uae_u32 REGPARAM2 op_e0b8_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 69;
	CurrentInstrCycles = 8;  
	uae_s32 cnt = m68k_dreg(regs, srcreg);
	uae_s32 data = m68k_dreg(regs, dstreg);
	uae_u32 val = data;
	CLEAR_CZNV();
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		SET_NFLG(val & 0x8000);
		SET_ZFLG(!(val & 0xffff));
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int ccnt = cnt & 63;
	cnt &= 63;
	if (cnt > 0) {
		uae_u32 hival;
		cnt &= 31;
		hival = val << (32 - cnt);
		val >>= cnt;
		val |= hival;
		val &= 0xffffffff;
		SET_CFLG((val & 0x80000000) >> 31);
	}
	SET_ZFLG(((uae_s32)(val)) == 0);
	SET_NFLG(((uae_s32)(val)) < 0);
	count_cycles += (2 * ccnt) * CYCLE_UNIT / 2;
	m68k_dreg(regs, dstreg) = (val);
	m68k_incpci(2);
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8+ (1/0) */
/* 2 0,0   */

/* ASRW.W (An) */
uae_u32 REGPARAM2 op_e0d0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 72;
	CurrentInstrCycles = 12; 
	uaecptr dataa;
	dataa = m68k_areg(regs, srcreg);
	if (dataa & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dataa, 1, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 data = get_word_000(dataa);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dataa + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 val = (uae_u16)data;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();
		SET_CFLG(val & 1);
		SET_ZFLG(!(val >> 1));
		SET_NFLG(val & 0x8000);
		SET_XFLG(GET_CFLG());
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	uae_u32 sign = 0x8000 & val;
	uae_u32 cflg = val & 1;
	val = (val >> 1) | sign;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	SET_CFLG(cflg);
	COPY_CARRY();
	put_word_000(dataa, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dataa + 0, 0x1, val, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (2/1) */
/* 2 0,0   */

/* ASRW.W (An)+ */
uae_u32 REGPARAM2 op_e0d8_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 72;
	CurrentInstrCycles = 12; 
	uaecptr dataa;
	dataa = m68k_areg(regs, srcreg);
	if (dataa & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dataa, 1, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 data = get_word_000(dataa);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) += 2 + 0;
		exception2_read(opcode, dataa + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) += 2;
	uae_u32 val = (uae_u16)data;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();
		SET_CFLG(val & 1);
		SET_ZFLG(!(val >> 1));
		SET_NFLG(val & 0x8000);
		SET_XFLG(GET_CFLG());
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	uae_u32 sign = 0x8000 & val;
	uae_u32 cflg = val & 1;
	val = (val >> 1) | sign;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	SET_CFLG(cflg);
	COPY_CARRY();
	put_word_000(dataa, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dataa + 0, 0x1, val, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (2/1) */
/* 2 0,0   */

/* ASRW.W -(An) */
uae_u32 REGPARAM2 op_e0e0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 72;
	CurrentInstrCycles = 14; 
	uaecptr dataa;
	dataa = m68k_areg(regs, srcreg) - 2;
	if (dataa & 1) {
		m68k_incpci(4);
		m68k_areg(regs, srcreg) = dataa;
		exception3_read_access(opcode, dataa, 1, 1);
		return 2 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 data = get_word_000(dataa);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, srcreg) = dataa;
		exception2_read(opcode, dataa + 0, 0x1, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) = dataa;
	uae_u32 val = (uae_u16)data;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();
		SET_CFLG(val & 1);
		SET_ZFLG(!(val >> 1));
		SET_NFLG(val & 0x8000);
		SET_XFLG(GET_CFLG());
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	uae_u32 sign = 0x8000 & val;
	uae_u32 cflg = val & 1;
	val = (val >> 1) | sign;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	SET_CFLG(cflg);
	COPY_CARRY();
	put_word_000(dataa, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dataa + 0, 0x1, val, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 14 * CYCLE_UNIT / 2 + count_cycles;
}
/* 14 (2/1) */
/* 2 0,0   */

/* ASRW.W (d16,An) */
uae_u32 REGPARAM2 op_e0e8_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 72;
	CurrentInstrCycles = 16; 
	uaecptr dataa;
	dataa = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dataa & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dataa, 1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 data = get_word_000(dataa);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dataa + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 val = (uae_u16)data;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();
		SET_CFLG(val & 1);
		SET_ZFLG(!(val >> 1));
		SET_NFLG(val & 0x8000);
		SET_XFLG(GET_CFLG());
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	uae_u32 sign = 0x8000 & val;
	uae_u32 cflg = val & 1;
	val = (val >> 1) | sign;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	SET_CFLG(cflg);
	COPY_CARRY();
	put_word_000(dataa, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dataa + 0, 0x1, val, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 4 0,0   */

/* ASRW.W (d8,An,Xn) */
uae_u32 REGPARAM2 op_e0f0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 72;
	CurrentInstrCycles = 18; 
	uaecptr dataa;
	BusCyclePenalty += 2;
	dataa = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dataa & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dataa, 1, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 data = get_word_000(dataa);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dataa + 0, 0x1, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 val = (uae_u16)data;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();
		SET_CFLG(val & 1);
		SET_ZFLG(!(val >> 1));
		SET_NFLG(val & 0x8000);
		SET_XFLG(GET_CFLG());
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	uae_u32 sign = 0x8000 & val;
	uae_u32 cflg = val & 1;
	val = (val >> 1) | sign;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	SET_CFLG(cflg);
	COPY_CARRY();
	put_word_000(dataa, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dataa + 0, 0x1, val, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (3/1) */
/* 4 4,0   */

/* ASRW.W (xxx).W */
uae_u32 REGPARAM2 op_e0f8_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 72;
	CurrentInstrCycles = 16; 
	uaecptr dataa;
	dataa = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dataa & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, dataa, 1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 data = get_word_000(dataa);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dataa + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 val = (uae_u16)data;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();
		SET_CFLG(val & 1);
		SET_ZFLG(!(val >> 1));
		SET_NFLG(val & 0x8000);
		SET_XFLG(GET_CFLG());
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	uae_u32 sign = 0x8000 & val;
	uae_u32 cflg = val & 1;
	val = (val >> 1) | sign;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	SET_CFLG(cflg);
	COPY_CARRY();
	put_word_000(dataa, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dataa + 0, 0x1, val, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 4 0,0   */

/* ASRW.W (xxx).L */
uae_u32 REGPARAM2 op_e0f9_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 72;
	CurrentInstrCycles = 20; 
	uaecptr dataa;
	dataa = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	dataa |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dataa & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, dataa, 1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 data = get_word_000(dataa);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dataa + 0, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 val = (uae_u16)data;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();
		SET_CFLG(val & 1);
		SET_ZFLG(!(val >> 1));
		SET_NFLG(val & 0x8000);
		SET_XFLG(GET_CFLG());
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	uae_u32 sign = 0x8000 & val;
	uae_u32 cflg = val & 1;
	val = (val >> 1) | sign;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	SET_CFLG(cflg);
	COPY_CARRY();
	put_word_000(dataa, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dataa + 0, 0x1, val, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (4/1) */
/* 6 0,0   */

/* ASLQ.B #<data>,Dn */
uae_u32 REGPARAM2 op_e100_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 65;
	CurrentInstrCycles = 6;  
	uae_u32 cnt = srcreg;
	uae_s8 data = m68k_dreg(regs, dstreg);
	uae_u32 val = (uae_u8)data;
	CLEAR_CZNV();
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		SET_ZFLG(!(val & 0xff));
		SET_NFLG(val & 0x80);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int ccnt = cnt & 63;
	cnt &= 63;
	if (cnt >= 8) {
		SET_VFLG(val != 0);
		SET_CFLG(cnt == 8 ? val & 1 : 0);
		COPY_CARRY();
		val = 0;
	} else {
		uae_u32 mask = (0xff << (7 - cnt)) & 0xff;
		SET_VFLG((val & mask) != mask && (val & mask) != 0);
		val <<= cnt - 1;
		SET_CFLG((val & 0x80) >> 7);
		COPY_CARRY();
		val <<= 1;
		val &= 0xff;
	}
	SET_ZFLG(((uae_s8)(val)) == 0);
	SET_NFLG(((uae_s8)(val)) < 0);
	count_cycles += (2 * ccnt) * CYCLE_UNIT / 2;
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((val) & 0xff);
	m68k_incpci(2);
	return 6 * CYCLE_UNIT / 2 + count_cycles;
}
/* 6+ (1/0) */
/* 2 0,0   */

/* LSLQ.B #<data>,Dn */
uae_u32 REGPARAM2 op_e108_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 67;
	CurrentInstrCycles = 6;  
	uae_u32 cnt = srcreg;
	uae_s8 data = m68k_dreg(regs, dstreg);
	uae_u32 val = (uae_u8)data;
	CLEAR_CZNV();
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		SET_ZFLG(!(val & 0xff));
		SET_NFLG(val & 0x80);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int ccnt = cnt & 63;
	cnt &= 63;
	if (cnt >= 8) {
		SET_CFLG(cnt == 8 ? val & 1 : 0);
		COPY_CARRY();
		val = 0;
	} else {
		val <<= (cnt - 1);
		SET_CFLG((val & 0x80) >> 7);
		COPY_CARRY();
		val <<= 1;
		val &= 0xff;
	}
	SET_ZFLG(((uae_s8)(val)) == 0);
	SET_NFLG(((uae_s8)(val)) < 0);
	count_cycles += (2 * ccnt) * CYCLE_UNIT / 2;
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((val) & 0xff);
	m68k_incpci(2);
	return 6 * CYCLE_UNIT / 2 + count_cycles;
}
/* 6+ (1/0) */
/* 2 0,0   */

/* ROXLQ.B #<data>,Dn */
uae_u32 REGPARAM2 op_e110_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 70;
	CurrentInstrCycles = 6;  
	uae_u32 cnt = srcreg;
	uae_s8 data = m68k_dreg(regs, dstreg);
	uae_u32 val = (uae_u8)data;
	CLEAR_CZNV();
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		SET_ZFLG(!(val & 0xff));
		SET_NFLG(val & 0x80);
		SET_CFLG(GET_XFLG());
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int ccnt = cnt & 63;
	cnt &= 63;
	{
		cnt--;
		{
			uae_u32 carry;
			uae_u32 loval = val >> (7 - cnt);
			carry = loval & 1;
			val = (((val << 1) | GET_XFLG()) << cnt) | (loval >> 1);
			SET_XFLG(carry);
			val &= 0xff;
		}
	}
	SET_CFLG(GET_XFLG());
	SET_ZFLG(((uae_s8)(val)) == 0);
	SET_NFLG(((uae_s8)(val)) < 0);
	count_cycles += (2 * ccnt) * CYCLE_UNIT / 2;
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((val) & 0xff);
	m68k_incpci(2);
	return 6 * CYCLE_UNIT / 2 + count_cycles;
}
/* 6+ (1/0) */
/* 2 0,0   */

/* ROLQ.B #<data>,Dn */
uae_u32 REGPARAM2 op_e118_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 68;
	CurrentInstrCycles = 6;  
	uae_u32 cnt = srcreg;
	uae_s8 data = m68k_dreg(regs, dstreg);
	uae_u32 val = (uae_u8)data;
	CLEAR_CZNV();
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		SET_ZFLG(!(val & 0xff));
		SET_NFLG(val & 0x80);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int ccnt = cnt & 63;
	cnt &= 63;
	{
		uae_u32 loval;
		cnt &= 7;
		loval = val >> (8 - cnt);
		val <<= cnt;
		val |= loval;
		val &= 0xff;
		SET_CFLG(val & 1);
	}
	SET_ZFLG(((uae_s8)(val)) == 0);
	SET_NFLG(((uae_s8)(val)) < 0);
	count_cycles += (2 * ccnt) * CYCLE_UNIT / 2;
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((val) & 0xff);
	m68k_incpci(2);
	return 6 * CYCLE_UNIT / 2 + count_cycles;
}
/* 6+ (1/0) */
/* 2 0,0   */

/* ASL.B Dn,Dn */
uae_u32 REGPARAM2 op_e120_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 65;
	CurrentInstrCycles = 6;  
	uae_s8 cnt = m68k_dreg(regs, srcreg);
	uae_s8 data = m68k_dreg(regs, dstreg);
	uae_u32 val = (uae_u8)data;
	CLEAR_CZNV();
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		SET_ZFLG(!(val & 0xff));
		SET_NFLG(val & 0x80);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int ccnt = cnt & 63;
	cnt &= 63;
	if (cnt >= 8) {
		SET_VFLG(val != 0);
		SET_CFLG(cnt == 8 ? val & 1 : 0);
		COPY_CARRY();
		val = 0;
	} else if (cnt > 0) {
		uae_u32 mask = (0xff << (7 - cnt)) & 0xff;
		SET_VFLG((val & mask) != mask && (val & mask) != 0);
		val <<= cnt - 1;
		SET_CFLG((val & 0x80) >> 7);
		COPY_CARRY();
		val <<= 1;
		val &= 0xff;
	}
	SET_ZFLG(((uae_s8)(val)) == 0);
	SET_NFLG(((uae_s8)(val)) < 0);
	count_cycles += (2 * ccnt) * CYCLE_UNIT / 2;
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((val) & 0xff);
	m68k_incpci(2);
	return 6 * CYCLE_UNIT / 2 + count_cycles;
}
/* 6+ (1/0) */
/* 2 0,0   */

/* LSL.B Dn,Dn */
uae_u32 REGPARAM2 op_e128_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 67;
	CurrentInstrCycles = 6;  
	uae_s8 cnt = m68k_dreg(regs, srcreg);
	uae_s8 data = m68k_dreg(regs, dstreg);
	uae_u32 val = (uae_u8)data;
	CLEAR_CZNV();
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		SET_ZFLG(!(val & 0xff));
		SET_NFLG(val & 0x80);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int ccnt = cnt & 63;
	cnt &= 63;
	if (cnt >= 8) {
		SET_CFLG(cnt == 8 ? val & 1 : 0);
		COPY_CARRY();
		val = 0;
	} else if (cnt > 0) {
		val <<= (cnt - 1);
		SET_CFLG((val & 0x80) >> 7);
		COPY_CARRY();
		val <<= 1;
		val &= 0xff;
	}
	SET_ZFLG(((uae_s8)(val)) == 0);
	SET_NFLG(((uae_s8)(val)) < 0);
	count_cycles += (2 * ccnt) * CYCLE_UNIT / 2;
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((val) & 0xff);
	m68k_incpci(2);
	return 6 * CYCLE_UNIT / 2 + count_cycles;
}
/* 6+ (1/0) */
/* 2 0,0   */

/* ROXL.B Dn,Dn */
uae_u32 REGPARAM2 op_e130_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 70;
	CurrentInstrCycles = 6;  
	uae_s8 cnt = m68k_dreg(regs, srcreg);
	uae_s8 data = m68k_dreg(regs, dstreg);
	uae_u32 val = (uae_u8)data;
	CLEAR_CZNV();
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		SET_ZFLG(!(val & 0xff));
		SET_NFLG(val & 0x80);
		SET_CFLG(GET_XFLG());
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int ccnt = cnt & 63;
	cnt &= 63;
	if (cnt >= 36) cnt -= 36;
	if (cnt >= 18) cnt -= 18;
	if (cnt >= 9) cnt -= 9;
	if (cnt > 0) {
		cnt--;
		{
			uae_u32 carry;
			uae_u32 loval = val >> (7 - cnt);
			carry = loval & 1;
			val = (((val << 1) | GET_XFLG()) << cnt) | (loval >> 1);
			SET_XFLG(carry);
			val &= 0xff;
		}
	}
	SET_CFLG(GET_XFLG());
	SET_ZFLG(((uae_s8)(val)) == 0);
	SET_NFLG(((uae_s8)(val)) < 0);
	count_cycles += (2 * ccnt) * CYCLE_UNIT / 2;
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((val) & 0xff);
	m68k_incpci(2);
	return 6 * CYCLE_UNIT / 2 + count_cycles;
}
/* 6+ (1/0) */
/* 2 0,0   */

/* ROL.B Dn,Dn */
uae_u32 REGPARAM2 op_e138_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 68;
	CurrentInstrCycles = 6;  
	uae_s8 cnt = m68k_dreg(regs, srcreg);
	uae_s8 data = m68k_dreg(regs, dstreg);
	uae_u32 val = (uae_u8)data;
	CLEAR_CZNV();
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		SET_ZFLG(!(val & 0xff));
		SET_NFLG(val & 0x80);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int ccnt = cnt & 63;
	cnt &= 63;
	if (cnt > 0) {
		uae_u32 loval;
		cnt &= 7;
		loval = val >> (8 - cnt);
		val <<= cnt;
		val |= loval;
		val &= 0xff;
		SET_CFLG(val & 1);
	}
	SET_ZFLG(((uae_s8)(val)) == 0);
	SET_NFLG(((uae_s8)(val)) < 0);
	count_cycles += (2 * ccnt) * CYCLE_UNIT / 2;
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((val) & 0xff);
	m68k_incpci(2);
	return 6 * CYCLE_UNIT / 2 + count_cycles;
}
/* 6+ (1/0) */
/* 2 0,0   */

/* ASLQ.W #<data>,Dn */
uae_u32 REGPARAM2 op_e140_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 65;
	CurrentInstrCycles = 6;  
	uae_u32 cnt = srcreg;
	uae_s16 data = m68k_dreg(regs, dstreg);
	uae_u32 val = (uae_u16)data;
	CLEAR_CZNV();
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		SET_ZFLG(!(val & 0xffff));
		SET_NFLG(val & 0x8000);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int ccnt = cnt & 63;
	cnt &= 63;
	if (cnt >= 16) {
		SET_VFLG(val != 0);
		SET_CFLG(cnt == 16 ? val & 1 : 0);
		COPY_CARRY();
		val = 0;
	} else {
		uae_u32 mask = (0xffff << (15 - cnt)) & 0xffff;
		SET_VFLG((val & mask) != mask && (val & mask) != 0);
		val <<= cnt - 1;
		SET_CFLG((val & 0x8000) >> 15);
		COPY_CARRY();
		val <<= 1;
		val &= 0xffff;
	}
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	count_cycles += (2 * ccnt) * CYCLE_UNIT / 2;
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((val) & 0xffff);
	m68k_incpci(2);
	return 6 * CYCLE_UNIT / 2 + count_cycles;
}
/* 6+ (1/0) */
/* 2 0,0   */

/* LSLQ.W #<data>,Dn */
uae_u32 REGPARAM2 op_e148_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 67;
	CurrentInstrCycles = 6;  
	uae_u32 cnt = srcreg;
	uae_s16 data = m68k_dreg(regs, dstreg);
	uae_u32 val = (uae_u16)data;
	CLEAR_CZNV();
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		SET_ZFLG(!(val & 0xffff));
		SET_NFLG(val & 0x8000);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int ccnt = cnt & 63;
	cnt &= 63;
	if (cnt >= 16) {
		SET_CFLG(cnt == 16 ? val & 1 : 0);
		COPY_CARRY();
		val = 0;
	} else {
		val <<= (cnt - 1);
		SET_CFLG((val & 0x8000) >> 15);
		COPY_CARRY();
		val <<= 1;
		val &= 0xffff;
	}
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	count_cycles += (2 * ccnt) * CYCLE_UNIT / 2;
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((val) & 0xffff);
	m68k_incpci(2);
	return 6 * CYCLE_UNIT / 2 + count_cycles;
}
/* 6+ (1/0) */
/* 2 0,0   */

/* ROXLQ.W #<data>,Dn */
uae_u32 REGPARAM2 op_e150_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 70;
	CurrentInstrCycles = 6;  
	uae_u32 cnt = srcreg;
	uae_s16 data = m68k_dreg(regs, dstreg);
	uae_u32 val = (uae_u16)data;
	CLEAR_CZNV();
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		SET_ZFLG(!(val & 0xffff));
		SET_NFLG(val & 0x8000);
		SET_CFLG(GET_XFLG());
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int ccnt = cnt & 63;
	cnt &= 63;
	{
		cnt--;
		{
			uae_u32 carry;
			uae_u32 loval = val >> (15 - cnt);
			carry = loval & 1;
			val = (((val << 1) | GET_XFLG()) << cnt) | (loval >> 1);
			SET_XFLG(carry);
			val &= 0xffff;
		}
	}
	SET_CFLG(GET_XFLG());
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	count_cycles += (2 * ccnt) * CYCLE_UNIT / 2;
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((val) & 0xffff);
	m68k_incpci(2);
	return 6 * CYCLE_UNIT / 2 + count_cycles;
}
/* 6+ (1/0) */
/* 2 0,0   */

/* ROLQ.W #<data>,Dn */
uae_u32 REGPARAM2 op_e158_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 68;
	CurrentInstrCycles = 6;  
	uae_u32 cnt = srcreg;
	uae_s16 data = m68k_dreg(regs, dstreg);
	uae_u32 val = (uae_u16)data;
	CLEAR_CZNV();
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		SET_ZFLG(!(val & 0xffff));
		SET_NFLG(val & 0x8000);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int ccnt = cnt & 63;
	cnt &= 63;
	{
		uae_u32 loval;
		cnt &= 15;
		loval = val >> (16 - cnt);
		val <<= cnt;
		val |= loval;
		val &= 0xffff;
		SET_CFLG(val & 1);
	}
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	count_cycles += (2 * ccnt) * CYCLE_UNIT / 2;
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((val) & 0xffff);
	m68k_incpci(2);
	return 6 * CYCLE_UNIT / 2 + count_cycles;
}
/* 6+ (1/0) */
/* 2 0,0   */

/* ASL.W Dn,Dn */
uae_u32 REGPARAM2 op_e160_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 65;
	CurrentInstrCycles = 6;  
	uae_s16 cnt = m68k_dreg(regs, srcreg);
	uae_s16 data = m68k_dreg(regs, dstreg);
	uae_u32 val = (uae_u16)data;
	CLEAR_CZNV();
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		SET_ZFLG(!(val & 0xffff));
		SET_NFLG(val & 0x8000);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int ccnt = cnt & 63;
	cnt &= 63;
	if (cnt >= 16) {
		SET_VFLG(val != 0);
		SET_CFLG(cnt == 16 ? val & 1 : 0);
		COPY_CARRY();
		val = 0;
	} else if (cnt > 0) {
		uae_u32 mask = (0xffff << (15 - cnt)) & 0xffff;
		SET_VFLG((val & mask) != mask && (val & mask) != 0);
		val <<= cnt - 1;
		SET_CFLG((val & 0x8000) >> 15);
		COPY_CARRY();
		val <<= 1;
		val &= 0xffff;
	}
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	count_cycles += (2 * ccnt) * CYCLE_UNIT / 2;
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((val) & 0xffff);
	m68k_incpci(2);
	return 6 * CYCLE_UNIT / 2 + count_cycles;
}
/* 6+ (1/0) */
/* 2 0,0   */

/* LSL.W Dn,Dn */
uae_u32 REGPARAM2 op_e168_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 67;
	CurrentInstrCycles = 6;  
	uae_s16 cnt = m68k_dreg(regs, srcreg);
	uae_s16 data = m68k_dreg(regs, dstreg);
	uae_u32 val = (uae_u16)data;
	CLEAR_CZNV();
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		SET_ZFLG(!(val & 0xffff));
		SET_NFLG(val & 0x8000);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int ccnt = cnt & 63;
	cnt &= 63;
	if (cnt >= 16) {
		SET_CFLG(cnt == 16 ? val & 1 : 0);
		COPY_CARRY();
		val = 0;
	} else if (cnt > 0) {
		val <<= (cnt - 1);
		SET_CFLG((val & 0x8000) >> 15);
		COPY_CARRY();
		val <<= 1;
		val &= 0xffff;
	}
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	count_cycles += (2 * ccnt) * CYCLE_UNIT / 2;
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((val) & 0xffff);
	m68k_incpci(2);
	return 6 * CYCLE_UNIT / 2 + count_cycles;
}
/* 6+ (1/0) */
/* 2 0,0   */

/* ROXL.W Dn,Dn */
uae_u32 REGPARAM2 op_e170_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 70;
	CurrentInstrCycles = 6;  
	uae_s16 cnt = m68k_dreg(regs, srcreg);
	uae_s16 data = m68k_dreg(regs, dstreg);
	uae_u32 val = (uae_u16)data;
	CLEAR_CZNV();
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		SET_ZFLG(!(val & 0xffff));
		SET_NFLG(val & 0x8000);
		SET_CFLG(GET_XFLG());
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int ccnt = cnt & 63;
	cnt &= 63;
	if (cnt >= 34) cnt -= 34;
	if (cnt >= 17) cnt -= 17;
	if (cnt > 0) {
		cnt--;
		{
			uae_u32 carry;
			uae_u32 loval = val >> (15 - cnt);
			carry = loval & 1;
			val = (((val << 1) | GET_XFLG()) << cnt) | (loval >> 1);
			SET_XFLG(carry);
			val &= 0xffff;
		}
	}
	SET_CFLG(GET_XFLG());
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	count_cycles += (2 * ccnt) * CYCLE_UNIT / 2;
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((val) & 0xffff);
	m68k_incpci(2);
	return 6 * CYCLE_UNIT / 2 + count_cycles;
}
/* 6+ (1/0) */
/* 2 0,0   */

/* ROL.W Dn,Dn */
uae_u32 REGPARAM2 op_e178_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 68;
	CurrentInstrCycles = 6;  
	uae_s16 cnt = m68k_dreg(regs, srcreg);
	uae_s16 data = m68k_dreg(regs, dstreg);
	uae_u32 val = (uae_u16)data;
	CLEAR_CZNV();
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		SET_ZFLG(!(val & 0xffff));
		SET_NFLG(val & 0x8000);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int ccnt = cnt & 63;
	cnt &= 63;
	if (cnt > 0) {
		uae_u32 loval;
		cnt &= 15;
		loval = val >> (16 - cnt);
		val <<= cnt;
		val |= loval;
		val &= 0xffff;
		SET_CFLG(val & 1);
	}
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	count_cycles += (2 * ccnt) * CYCLE_UNIT / 2;
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((val) & 0xffff);
	m68k_incpci(2);
	return 6 * CYCLE_UNIT / 2 + count_cycles;
}
/* 6+ (1/0) */
/* 2 0,0   */

/* ASLQ.L #<data>,Dn */
uae_u32 REGPARAM2 op_e180_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 65;
	CurrentInstrCycles = 8;  
	uae_u32 cnt = srcreg;
	uae_s32 data = m68k_dreg(regs, dstreg);
	uae_u32 val = data;
	CLEAR_CZNV();
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		SET_NFLG(val & 0x8000);
		SET_ZFLG(!(val & 0xffff));
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int ccnt = cnt & 63;
	cnt &= 63;
	if (cnt >= 32) {
		SET_VFLG(val != 0);
		SET_CFLG(cnt == 32 ? val & 1 : 0);
		COPY_CARRY();
		val = 0;
	} else {
		uae_u32 mask = (0xffffffff << (31 - cnt)) & 0xffffffff;
		SET_VFLG((val & mask) != mask && (val & mask) != 0);
		val <<= cnt - 1;
		SET_CFLG((val & 0x80000000) >> 31);
		COPY_CARRY();
		val <<= 1;
		val &= 0xffffffff;
	}
	SET_ZFLG(((uae_s32)(val)) == 0);
	SET_NFLG(((uae_s32)(val)) < 0);
	count_cycles += (2 * ccnt) * CYCLE_UNIT / 2;
	m68k_dreg(regs, dstreg) = (val);
	m68k_incpci(2);
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8+ (1/0) */
/* 2 0,0   */

/* LSLQ.L #<data>,Dn */
uae_u32 REGPARAM2 op_e188_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 67;
	CurrentInstrCycles = 8;  
	uae_u32 cnt = srcreg;
	uae_s32 data = m68k_dreg(regs, dstreg);
	uae_u32 val = data;
	CLEAR_CZNV();
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		SET_NFLG(val & 0x8000);
		SET_ZFLG(!(val & 0xffff));
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int ccnt = cnt & 63;
	cnt &= 63;
	if (cnt >= 32) {
		SET_CFLG(cnt == 32 ? val & 1 : 0);
		COPY_CARRY();
		val = 0;
	} else {
		val <<= (cnt - 1);
		SET_CFLG((val & 0x80000000) >> 31);
		COPY_CARRY();
		val <<= 1;
		val &= 0xffffffff;
	}
	SET_ZFLG(((uae_s32)(val)) == 0);
	SET_NFLG(((uae_s32)(val)) < 0);
	count_cycles += (2 * ccnt) * CYCLE_UNIT / 2;
	m68k_dreg(regs, dstreg) = (val);
	m68k_incpci(2);
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8+ (1/0) */
/* 2 0,0   */

/* ROXLQ.L #<data>,Dn */
uae_u32 REGPARAM2 op_e190_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 70;
	CurrentInstrCycles = 8;  
	uae_u32 cnt = srcreg;
	uae_s32 data = m68k_dreg(regs, dstreg);
	uae_u32 val = data;
	CLEAR_CZNV();
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		SET_NFLG(val & 0x8000);
		SET_ZFLG(!(val & 0xffff));
		SET_CFLG(GET_XFLG());
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int ccnt = cnt & 63;
	cnt &= 63;
	{
		cnt--;
		{
			uae_u32 carry;
			uae_u32 loval = val >> (31 - cnt);
			carry = loval & 1;
			val = (((val << 1) | GET_XFLG()) << cnt) | (loval >> 1);
			SET_XFLG(carry);
			val &= 0xffffffff;
		}
	}
	SET_CFLG(GET_XFLG());
	SET_ZFLG(((uae_s32)(val)) == 0);
	SET_NFLG(((uae_s32)(val)) < 0);
	count_cycles += (2 * ccnt) * CYCLE_UNIT / 2;
	m68k_dreg(regs, dstreg) = (val);
	m68k_incpci(2);
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8+ (1/0) */
/* 2 0,0   */

/* ROLQ.L #<data>,Dn */
uae_u32 REGPARAM2 op_e198_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 68;
	CurrentInstrCycles = 8;  
	uae_u32 cnt = srcreg;
	uae_s32 data = m68k_dreg(regs, dstreg);
	uae_u32 val = data;
	CLEAR_CZNV();
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		SET_NFLG(val & 0x8000);
		SET_ZFLG(!(val & 0xffff));
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int ccnt = cnt & 63;
	cnt &= 63;
	{
		uae_u32 loval;
		cnt &= 31;
		loval = val >> (32 - cnt);
		val <<= cnt;
		val |= loval;
		val &= 0xffffffff;
		SET_CFLG(val & 1);
	}
	SET_ZFLG(((uae_s32)(val)) == 0);
	SET_NFLG(((uae_s32)(val)) < 0);
	count_cycles += (2 * ccnt) * CYCLE_UNIT / 2;
	m68k_dreg(regs, dstreg) = (val);
	m68k_incpci(2);
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8+ (1/0) */
/* 2 0,0   */

/* ASL.L Dn,Dn */
uae_u32 REGPARAM2 op_e1a0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 65;
	CurrentInstrCycles = 8;  
	uae_s32 cnt = m68k_dreg(regs, srcreg);
	uae_s32 data = m68k_dreg(regs, dstreg);
	uae_u32 val = data;
	CLEAR_CZNV();
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		SET_NFLG(val & 0x8000);
		SET_ZFLG(!(val & 0xffff));
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int ccnt = cnt & 63;
	cnt &= 63;
	if (cnt >= 32) {
		SET_VFLG(val != 0);
		SET_CFLG(cnt == 32 ? val & 1 : 0);
		COPY_CARRY();
		val = 0;
	} else if (cnt > 0) {
		uae_u32 mask = (0xffffffff << (31 - cnt)) & 0xffffffff;
		SET_VFLG((val & mask) != mask && (val & mask) != 0);
		val <<= cnt - 1;
		SET_CFLG((val & 0x80000000) >> 31);
		COPY_CARRY();
		val <<= 1;
		val &= 0xffffffff;
	}
	SET_ZFLG(((uae_s32)(val)) == 0);
	SET_NFLG(((uae_s32)(val)) < 0);
	count_cycles += (2 * ccnt) * CYCLE_UNIT / 2;
	m68k_dreg(regs, dstreg) = (val);
	m68k_incpci(2);
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8+ (1/0) */
/* 2 0,0   */

/* LSL.L Dn,Dn */
uae_u32 REGPARAM2 op_e1a8_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 67;
	CurrentInstrCycles = 8;  
	uae_s32 cnt = m68k_dreg(regs, srcreg);
	uae_s32 data = m68k_dreg(regs, dstreg);
	uae_u32 val = data;
	CLEAR_CZNV();
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		SET_NFLG(val & 0x8000);
		SET_ZFLG(!(val & 0xffff));
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int ccnt = cnt & 63;
	cnt &= 63;
	if (cnt >= 32) {
		SET_CFLG(cnt == 32 ? val & 1 : 0);
		COPY_CARRY();
		val = 0;
	} else if (cnt > 0) {
		val <<= (cnt - 1);
		SET_CFLG((val & 0x80000000) >> 31);
		COPY_CARRY();
		val <<= 1;
		val &= 0xffffffff;
	}
	SET_ZFLG(((uae_s32)(val)) == 0);
	SET_NFLG(((uae_s32)(val)) < 0);
	count_cycles += (2 * ccnt) * CYCLE_UNIT / 2;
	m68k_dreg(regs, dstreg) = (val);
	m68k_incpci(2);
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8+ (1/0) */
/* 2 0,0   */

/* ROXL.L Dn,Dn */
uae_u32 REGPARAM2 op_e1b0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 70;
	CurrentInstrCycles = 8;  
	uae_s32 cnt = m68k_dreg(regs, srcreg);
	uae_s32 data = m68k_dreg(regs, dstreg);
	uae_u32 val = data;
	CLEAR_CZNV();
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		SET_NFLG(val & 0x8000);
		SET_ZFLG(!(val & 0xffff));
		SET_CFLG(GET_XFLG());
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int ccnt = cnt & 63;
	cnt &= 63;
	if (cnt >= 33) cnt -= 33;
	if (cnt > 0) {
		cnt--;
		{
			uae_u32 carry;
			uae_u32 loval = val >> (31 - cnt);
			carry = loval & 1;
			val = (((val << 1) | GET_XFLG()) << cnt) | (loval >> 1);
			SET_XFLG(carry);
			val &= 0xffffffff;
		}
	}
	SET_CFLG(GET_XFLG());
	SET_ZFLG(((uae_s32)(val)) == 0);
	SET_NFLG(((uae_s32)(val)) < 0);
	count_cycles += (2 * ccnt) * CYCLE_UNIT / 2;
	m68k_dreg(regs, dstreg) = (val);
	m68k_incpci(2);
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8+ (1/0) */
/* 2 0,0   */

/* ROL.L Dn,Dn */
uae_u32 REGPARAM2 op_e1b8_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 68;
	CurrentInstrCycles = 8;  
	uae_s32 cnt = m68k_dreg(regs, srcreg);
	uae_s32 data = m68k_dreg(regs, dstreg);
	uae_u32 val = data;
	CLEAR_CZNV();
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		SET_NFLG(val & 0x8000);
		SET_ZFLG(!(val & 0xffff));
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	int ccnt = cnt & 63;
	cnt &= 63;
	if (cnt > 0) {
		uae_u32 loval;
		cnt &= 31;
		loval = val >> (32 - cnt);
		val <<= cnt;
		val |= loval;
		val &= 0xffffffff;
		SET_CFLG(val & 1);
	}
	SET_ZFLG(((uae_s32)(val)) == 0);
	SET_NFLG(((uae_s32)(val)) < 0);
	count_cycles += (2 * ccnt) * CYCLE_UNIT / 2;
	m68k_dreg(regs, dstreg) = (val);
	m68k_incpci(2);
	return 8 * CYCLE_UNIT / 2 + count_cycles;
}
/* 8+ (1/0) */
/* 2 0,0   */

/* ASLW.W (An) */
uae_u32 REGPARAM2 op_e1d0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 73;
	CurrentInstrCycles = 12; 
	uaecptr dataa;
	dataa = m68k_areg(regs, srcreg);
	if (dataa & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dataa, 1, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 data = get_word_000(dataa);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dataa + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 val = (uae_u16)data;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();
		SET_CFLG(val & 0x8000);
		SET_ZFLG(!(val & 0x7fff));
		SET_NFLG(val & 0x4000);
		SET_XFLG(GET_CFLG());
		SET_VFLG((val & 0x8000) != ((val << 1) & 0x8000));
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	uae_u32 sign = 0x8000 & val;
	uae_u32 sign2;
	val <<= 1;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	sign2 = 0x8000 & val;
	SET_CFLG(sign != 0);
	COPY_CARRY();
	SET_VFLG(GET_VFLG() | (sign2 != sign));
	put_word_000(dataa, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dataa + 0, 0x1, val, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (2/1) */
/* 2 0,0   */

/* ASLW.W (An)+ */
uae_u32 REGPARAM2 op_e1d8_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 73;
	CurrentInstrCycles = 12; 
	uaecptr dataa;
	dataa = m68k_areg(regs, srcreg);
	if (dataa & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dataa, 1, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 data = get_word_000(dataa);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) += 2 + 0;
		exception2_read(opcode, dataa + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) += 2;
	uae_u32 val = (uae_u16)data;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();
		SET_CFLG(val & 0x8000);
		SET_ZFLG(!(val & 0x7fff));
		SET_NFLG(val & 0x4000);
		SET_XFLG(GET_CFLG());
		SET_VFLG((val & 0x8000) != ((val << 1) & 0x8000));
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	uae_u32 sign = 0x8000 & val;
	uae_u32 sign2;
	val <<= 1;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	sign2 = 0x8000 & val;
	SET_CFLG(sign != 0);
	COPY_CARRY();
	SET_VFLG(GET_VFLG() | (sign2 != sign));
	put_word_000(dataa, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dataa + 0, 0x1, val, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (2/1) */
/* 2 0,0   */

/* ASLW.W -(An) */
uae_u32 REGPARAM2 op_e1e0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 73;
	CurrentInstrCycles = 14; 
	uaecptr dataa;
	dataa = m68k_areg(regs, srcreg) - 2;
	if (dataa & 1) {
		m68k_incpci(4);
		m68k_areg(regs, srcreg) = dataa;
		exception3_read_access(opcode, dataa, 1, 1);
		return 2 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 data = get_word_000(dataa);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, srcreg) = dataa;
		exception2_read(opcode, dataa + 0, 0x1, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) = dataa;
	uae_u32 val = (uae_u16)data;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();
		SET_CFLG(val & 0x8000);
		SET_ZFLG(!(val & 0x7fff));
		SET_NFLG(val & 0x4000);
		SET_XFLG(GET_CFLG());
		SET_VFLG((val & 0x8000) != ((val << 1) & 0x8000));
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	uae_u32 sign = 0x8000 & val;
	uae_u32 sign2;
	val <<= 1;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	sign2 = 0x8000 & val;
	SET_CFLG(sign != 0);
	COPY_CARRY();
	SET_VFLG(GET_VFLG() | (sign2 != sign));
	put_word_000(dataa, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dataa + 0, 0x1, val, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 14 * CYCLE_UNIT / 2 + count_cycles;
}
/* 14 (2/1) */
/* 2 0,0   */

/* ASLW.W (d16,An) */
uae_u32 REGPARAM2 op_e1e8_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 73;
	CurrentInstrCycles = 16; 
	uaecptr dataa;
	dataa = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dataa & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dataa, 1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 data = get_word_000(dataa);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dataa + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 val = (uae_u16)data;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();
		SET_CFLG(val & 0x8000);
		SET_ZFLG(!(val & 0x7fff));
		SET_NFLG(val & 0x4000);
		SET_XFLG(GET_CFLG());
		SET_VFLG((val & 0x8000) != ((val << 1) & 0x8000));
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	uae_u32 sign = 0x8000 & val;
	uae_u32 sign2;
	val <<= 1;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	sign2 = 0x8000 & val;
	SET_CFLG(sign != 0);
	COPY_CARRY();
	SET_VFLG(GET_VFLG() | (sign2 != sign));
	put_word_000(dataa, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dataa + 0, 0x1, val, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 4 0,0   */

/* ASLW.W (d8,An,Xn) */
uae_u32 REGPARAM2 op_e1f0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 73;
	CurrentInstrCycles = 18; 
	uaecptr dataa;
	BusCyclePenalty += 2;
	dataa = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dataa & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dataa, 1, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 data = get_word_000(dataa);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dataa + 0, 0x1, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 val = (uae_u16)data;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();
		SET_CFLG(val & 0x8000);
		SET_ZFLG(!(val & 0x7fff));
		SET_NFLG(val & 0x4000);
		SET_XFLG(GET_CFLG());
		SET_VFLG((val & 0x8000) != ((val << 1) & 0x8000));
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	uae_u32 sign = 0x8000 & val;
	uae_u32 sign2;
	val <<= 1;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	sign2 = 0x8000 & val;
	SET_CFLG(sign != 0);
	COPY_CARRY();
	SET_VFLG(GET_VFLG() | (sign2 != sign));
	put_word_000(dataa, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dataa + 0, 0x1, val, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (3/1) */
/* 4 4,0   */

/* ASLW.W (xxx).W */
uae_u32 REGPARAM2 op_e1f8_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 73;
	CurrentInstrCycles = 16; 
	uaecptr dataa;
	dataa = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dataa & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, dataa, 1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 data = get_word_000(dataa);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dataa + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 val = (uae_u16)data;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();
		SET_CFLG(val & 0x8000);
		SET_ZFLG(!(val & 0x7fff));
		SET_NFLG(val & 0x4000);
		SET_XFLG(GET_CFLG());
		SET_VFLG((val & 0x8000) != ((val << 1) & 0x8000));
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	uae_u32 sign = 0x8000 & val;
	uae_u32 sign2;
	val <<= 1;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	sign2 = 0x8000 & val;
	SET_CFLG(sign != 0);
	COPY_CARRY();
	SET_VFLG(GET_VFLG() | (sign2 != sign));
	put_word_000(dataa, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dataa + 0, 0x1, val, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 4 0,0   */

/* ASLW.W (xxx).L */
uae_u32 REGPARAM2 op_e1f9_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 73;
	CurrentInstrCycles = 20; 
	uaecptr dataa;
	dataa = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	dataa |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dataa & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, dataa, 1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 data = get_word_000(dataa);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dataa + 0, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 val = (uae_u16)data;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();
		SET_CFLG(val & 0x8000);
		SET_ZFLG(!(val & 0x7fff));
		SET_NFLG(val & 0x4000);
		SET_XFLG(GET_CFLG());
		SET_VFLG((val & 0x8000) != ((val << 1) & 0x8000));
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	uae_u32 sign = 0x8000 & val;
	uae_u32 sign2;
	val <<= 1;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	sign2 = 0x8000 & val;
	SET_CFLG(sign != 0);
	COPY_CARRY();
	SET_VFLG(GET_VFLG() | (sign2 != sign));
	put_word_000(dataa, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dataa + 0, 0x1, val, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (4/1) */
/* 6 0,0   */

/* LSRW.W (An) */
uae_u32 REGPARAM2 op_e2d0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 74;
	CurrentInstrCycles = 12; 
	uaecptr dataa;
	dataa = m68k_areg(regs, srcreg);
	if (dataa & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dataa, 1, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 data = get_word_000(dataa);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dataa + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 val = (uae_u16)data;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();
		SET_CFLG(val & 1);
		SET_ZFLG(!(val & 0xfffe));
		SET_NFLG(0);
		SET_XFLG(GET_CFLG());
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	uae_u32 carry = val & 1;
	val >>= 1;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	SET_CFLG(carry);
	COPY_CARRY();
	put_word_000(dataa, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dataa + 0, 0x1, val, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (2/1) */
/* 2 0,0   */

/* LSRW.W (An)+ */
uae_u32 REGPARAM2 op_e2d8_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 74;
	CurrentInstrCycles = 12; 
	uaecptr dataa;
	dataa = m68k_areg(regs, srcreg);
	if (dataa & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dataa, 1, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 data = get_word_000(dataa);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) += 2 + 0;
		exception2_read(opcode, dataa + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) += 2;
	uae_u32 val = (uae_u16)data;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();
		SET_CFLG(val & 1);
		SET_ZFLG(!(val & 0xfffe));
		SET_NFLG(0);
		SET_XFLG(GET_CFLG());
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	uae_u32 carry = val & 1;
	val >>= 1;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	SET_CFLG(carry);
	COPY_CARRY();
	put_word_000(dataa, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dataa + 0, 0x1, val, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (2/1) */
/* 2 0,0   */

/* LSRW.W -(An) */
uae_u32 REGPARAM2 op_e2e0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 74;
	CurrentInstrCycles = 14; 
	uaecptr dataa;
	dataa = m68k_areg(regs, srcreg) - 2;
	if (dataa & 1) {
		m68k_incpci(4);
		m68k_areg(regs, srcreg) = dataa;
		exception3_read_access(opcode, dataa, 1, 1);
		return 2 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 data = get_word_000(dataa);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, srcreg) = dataa;
		exception2_read(opcode, dataa + 0, 0x1, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) = dataa;
	uae_u32 val = (uae_u16)data;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();
		SET_CFLG(val & 1);
		SET_ZFLG(!(val & 0xfffe));
		SET_NFLG(0);
		SET_XFLG(GET_CFLG());
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	uae_u32 carry = val & 1;
	val >>= 1;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	SET_CFLG(carry);
	COPY_CARRY();
	put_word_000(dataa, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dataa + 0, 0x1, val, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 14 * CYCLE_UNIT / 2 + count_cycles;
}
/* 14 (2/1) */
/* 2 0,0   */

/* LSRW.W (d16,An) */
uae_u32 REGPARAM2 op_e2e8_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 74;
	CurrentInstrCycles = 16; 
	uaecptr dataa;
	dataa = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dataa & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dataa, 1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 data = get_word_000(dataa);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dataa + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 val = (uae_u16)data;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();
		SET_CFLG(val & 1);
		SET_ZFLG(!(val & 0xfffe));
		SET_NFLG(0);
		SET_XFLG(GET_CFLG());
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	uae_u32 carry = val & 1;
	val >>= 1;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	SET_CFLG(carry);
	COPY_CARRY();
	put_word_000(dataa, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dataa + 0, 0x1, val, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 4 0,0   */

/* LSRW.W (d8,An,Xn) */
uae_u32 REGPARAM2 op_e2f0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 74;
	CurrentInstrCycles = 18; 
	uaecptr dataa;
	BusCyclePenalty += 2;
	dataa = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dataa & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dataa, 1, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 data = get_word_000(dataa);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dataa + 0, 0x1, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 val = (uae_u16)data;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();
		SET_CFLG(val & 1);
		SET_ZFLG(!(val & 0xfffe));
		SET_NFLG(0);
		SET_XFLG(GET_CFLG());
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	uae_u32 carry = val & 1;
	val >>= 1;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	SET_CFLG(carry);
	COPY_CARRY();
	put_word_000(dataa, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dataa + 0, 0x1, val, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (3/1) */
/* 4 4,0   */

/* LSRW.W (xxx).W */
uae_u32 REGPARAM2 op_e2f8_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 74;
	CurrentInstrCycles = 16; 
	uaecptr dataa;
	dataa = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dataa & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, dataa, 1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 data = get_word_000(dataa);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dataa + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 val = (uae_u16)data;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();
		SET_CFLG(val & 1);
		SET_ZFLG(!(val & 0xfffe));
		SET_NFLG(0);
		SET_XFLG(GET_CFLG());
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	uae_u32 carry = val & 1;
	val >>= 1;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	SET_CFLG(carry);
	COPY_CARRY();
	put_word_000(dataa, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dataa + 0, 0x1, val, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 4 0,0   */

/* LSRW.W (xxx).L */
uae_u32 REGPARAM2 op_e2f9_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 74;
	CurrentInstrCycles = 20; 
	uaecptr dataa;
	dataa = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	dataa |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dataa & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, dataa, 1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 data = get_word_000(dataa);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dataa + 0, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u32 val = (uae_u16)data;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();
		SET_CFLG(val & 1);
		SET_ZFLG(!(val & 0xfffe));
		SET_NFLG(0);
		SET_XFLG(GET_CFLG());
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	uae_u32 carry = val & 1;
	val >>= 1;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	SET_CFLG(carry);
	COPY_CARRY();
	put_word_000(dataa, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dataa + 0, 0x1, val, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (4/1) */
/* 6 0,0   */

/* LSLW.W (An) */
uae_u32 REGPARAM2 op_e3d0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 75;
	CurrentInstrCycles = 12; 
	uaecptr dataa;
	dataa = m68k_areg(regs, srcreg);
	if (dataa & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dataa, 1, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 data = get_word_000(dataa);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dataa + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u16 val = data;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();
		SET_CFLG(val & 0x8000);
		SET_ZFLG(!(val & 0x7fff));
		SET_NFLG(val & 0x4000);
		SET_XFLG(GET_CFLG());
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	uae_u32 carry = val & 0x8000;
	val <<= 1;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	SET_CFLG(carry >> 15);
	COPY_CARRY();
	put_word_000(dataa, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dataa + 0, 0x1, val, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (2/1) */
/* 2 0,0   */

/* LSLW.W (An)+ */
uae_u32 REGPARAM2 op_e3d8_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 75;
	CurrentInstrCycles = 12; 
	uaecptr dataa;
	dataa = m68k_areg(regs, srcreg);
	if (dataa & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dataa, 1, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 data = get_word_000(dataa);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) += 2 + 0;
		exception2_read(opcode, dataa + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) += 2;
	uae_u16 val = data;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();
		SET_CFLG(val & 0x8000);
		SET_ZFLG(!(val & 0x7fff));
		SET_NFLG(val & 0x4000);
		SET_XFLG(GET_CFLG());
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	uae_u32 carry = val & 0x8000;
	val <<= 1;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	SET_CFLG(carry >> 15);
	COPY_CARRY();
	put_word_000(dataa, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dataa + 0, 0x1, val, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (2/1) */
/* 2 0,0   */

/* LSLW.W -(An) */
uae_u32 REGPARAM2 op_e3e0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 75;
	CurrentInstrCycles = 14; 
	uaecptr dataa;
	dataa = m68k_areg(regs, srcreg) - 2;
	if (dataa & 1) {
		m68k_incpci(4);
		m68k_areg(regs, srcreg) = dataa;
		exception3_read_access(opcode, dataa, 1, 1);
		return 2 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 data = get_word_000(dataa);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, srcreg) = dataa;
		exception2_read(opcode, dataa + 0, 0x1, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) = dataa;
	uae_u16 val = data;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();
		SET_CFLG(val & 0x8000);
		SET_ZFLG(!(val & 0x7fff));
		SET_NFLG(val & 0x4000);
		SET_XFLG(GET_CFLG());
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	uae_u32 carry = val & 0x8000;
	val <<= 1;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	SET_CFLG(carry >> 15);
	COPY_CARRY();
	put_word_000(dataa, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dataa + 0, 0x1, val, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 14 * CYCLE_UNIT / 2 + count_cycles;
}
/* 14 (2/1) */
/* 2 0,0   */

/* LSLW.W (d16,An) */
uae_u32 REGPARAM2 op_e3e8_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 75;
	CurrentInstrCycles = 16; 
	uaecptr dataa;
	dataa = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dataa & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dataa, 1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 data = get_word_000(dataa);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dataa + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u16 val = data;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();
		SET_CFLG(val & 0x8000);
		SET_ZFLG(!(val & 0x7fff));
		SET_NFLG(val & 0x4000);
		SET_XFLG(GET_CFLG());
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	uae_u32 carry = val & 0x8000;
	val <<= 1;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	SET_CFLG(carry >> 15);
	COPY_CARRY();
	put_word_000(dataa, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dataa + 0, 0x1, val, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 4 0,0   */

/* LSLW.W (d8,An,Xn) */
uae_u32 REGPARAM2 op_e3f0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 75;
	CurrentInstrCycles = 18; 
	uaecptr dataa;
	BusCyclePenalty += 2;
	dataa = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dataa & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dataa, 1, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 data = get_word_000(dataa);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dataa + 0, 0x1, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u16 val = data;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();
		SET_CFLG(val & 0x8000);
		SET_ZFLG(!(val & 0x7fff));
		SET_NFLG(val & 0x4000);
		SET_XFLG(GET_CFLG());
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	uae_u32 carry = val & 0x8000;
	val <<= 1;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	SET_CFLG(carry >> 15);
	COPY_CARRY();
	put_word_000(dataa, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dataa + 0, 0x1, val, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (3/1) */
/* 4 4,0   */

/* LSLW.W (xxx).W */
uae_u32 REGPARAM2 op_e3f8_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 75;
	CurrentInstrCycles = 16; 
	uaecptr dataa;
	dataa = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dataa & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, dataa, 1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 data = get_word_000(dataa);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dataa + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u16 val = data;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();
		SET_CFLG(val & 0x8000);
		SET_ZFLG(!(val & 0x7fff));
		SET_NFLG(val & 0x4000);
		SET_XFLG(GET_CFLG());
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	uae_u32 carry = val & 0x8000;
	val <<= 1;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	SET_CFLG(carry >> 15);
	COPY_CARRY();
	put_word_000(dataa, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dataa + 0, 0x1, val, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 4 0,0   */

/* LSLW.W (xxx).L */
uae_u32 REGPARAM2 op_e3f9_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 75;
	CurrentInstrCycles = 20; 
	uaecptr dataa;
	dataa = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	dataa |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dataa & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, dataa, 1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 data = get_word_000(dataa);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dataa + 0, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u16 val = data;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();
		SET_CFLG(val & 0x8000);
		SET_ZFLG(!(val & 0x7fff));
		SET_NFLG(val & 0x4000);
		SET_XFLG(GET_CFLG());
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	uae_u32 carry = val & 0x8000;
	val <<= 1;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	SET_CFLG(carry >> 15);
	COPY_CARRY();
	put_word_000(dataa, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dataa + 0, 0x1, val, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (4/1) */
/* 6 0,0   */

/* ROXRW.W (An) */
uae_u32 REGPARAM2 op_e4d0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 79;
	CurrentInstrCycles = 12; 
	uaecptr dataa;
	dataa = m68k_areg(regs, srcreg);
	if (dataa & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dataa, 1, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 data = get_word_000(dataa);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dataa + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u16 val = data;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();SET_CFLG(val & 1);
		SET_ZFLG(!((val &0x7ffe) | GET_XFLG()))
		;SET_NFLG(GET_XFLG())
		;SET_XFLG(GET_CFLG());
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	uae_u32 carry = val & 1;
	val >>= 1;
	if (GET_XFLG()) val |= 0x8000;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	SET_CFLG(carry);
	COPY_CARRY();
	put_word_000(dataa, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dataa + 0, 0x1, val, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (2/1) */
/* 2 0,0   */

/* ROXRW.W (An)+ */
uae_u32 REGPARAM2 op_e4d8_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 79;
	CurrentInstrCycles = 12; 
	uaecptr dataa;
	dataa = m68k_areg(regs, srcreg);
	if (dataa & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dataa, 1, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 data = get_word_000(dataa);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) += 2 + 0;
		exception2_read(opcode, dataa + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) += 2;
	uae_u16 val = data;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();SET_CFLG(val & 1);
		SET_ZFLG(!((val &0x7ffe) | GET_XFLG()))
		;SET_NFLG(GET_XFLG())
		;SET_XFLG(GET_CFLG());
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	uae_u32 carry = val & 1;
	val >>= 1;
	if (GET_XFLG()) val |= 0x8000;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	SET_CFLG(carry);
	COPY_CARRY();
	put_word_000(dataa, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dataa + 0, 0x1, val, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (2/1) */
/* 2 0,0   */

/* ROXRW.W -(An) */
uae_u32 REGPARAM2 op_e4e0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 79;
	CurrentInstrCycles = 14; 
	uaecptr dataa;
	dataa = m68k_areg(regs, srcreg) - 2;
	if (dataa & 1) {
		m68k_incpci(4);
		m68k_areg(regs, srcreg) = dataa;
		exception3_read_access(opcode, dataa, 1, 1);
		return 2 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 data = get_word_000(dataa);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, srcreg) = dataa;
		exception2_read(opcode, dataa + 0, 0x1, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) = dataa;
	uae_u16 val = data;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();SET_CFLG(val & 1);
		SET_ZFLG(!((val &0x7ffe) | GET_XFLG()))
		;SET_NFLG(GET_XFLG())
		;SET_XFLG(GET_CFLG());
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	uae_u32 carry = val & 1;
	val >>= 1;
	if (GET_XFLG()) val |= 0x8000;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	SET_CFLG(carry);
	COPY_CARRY();
	put_word_000(dataa, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dataa + 0, 0x1, val, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 14 * CYCLE_UNIT / 2 + count_cycles;
}
/* 14 (2/1) */
/* 2 0,0   */

/* ROXRW.W (d16,An) */
uae_u32 REGPARAM2 op_e4e8_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 79;
	CurrentInstrCycles = 16; 
	uaecptr dataa;
	dataa = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dataa & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dataa, 1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 data = get_word_000(dataa);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dataa + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u16 val = data;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();SET_CFLG(val & 1);
		SET_ZFLG(!((val &0x7ffe) | GET_XFLG()))
		;SET_NFLG(GET_XFLG())
		;SET_XFLG(GET_CFLG());
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	uae_u32 carry = val & 1;
	val >>= 1;
	if (GET_XFLG()) val |= 0x8000;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	SET_CFLG(carry);
	COPY_CARRY();
	put_word_000(dataa, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dataa + 0, 0x1, val, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 4 0,0   */

/* ROXRW.W (d8,An,Xn) */
uae_u32 REGPARAM2 op_e4f0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 79;
	CurrentInstrCycles = 18; 
	uaecptr dataa;
	BusCyclePenalty += 2;
	dataa = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dataa & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dataa, 1, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 data = get_word_000(dataa);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dataa + 0, 0x1, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u16 val = data;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();SET_CFLG(val & 1);
		SET_ZFLG(!((val &0x7ffe) | GET_XFLG()))
		;SET_NFLG(GET_XFLG())
		;SET_XFLG(GET_CFLG());
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	uae_u32 carry = val & 1;
	val >>= 1;
	if (GET_XFLG()) val |= 0x8000;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	SET_CFLG(carry);
	COPY_CARRY();
	put_word_000(dataa, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dataa + 0, 0x1, val, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (3/1) */
/* 4 4,0   */

/* ROXRW.W (xxx).W */
uae_u32 REGPARAM2 op_e4f8_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 79;
	CurrentInstrCycles = 16; 
	uaecptr dataa;
	dataa = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dataa & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, dataa, 1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 data = get_word_000(dataa);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dataa + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u16 val = data;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();SET_CFLG(val & 1);
		SET_ZFLG(!((val &0x7ffe) | GET_XFLG()))
		;SET_NFLG(GET_XFLG())
		;SET_XFLG(GET_CFLG());
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	uae_u32 carry = val & 1;
	val >>= 1;
	if (GET_XFLG()) val |= 0x8000;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	SET_CFLG(carry);
	COPY_CARRY();
	put_word_000(dataa, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dataa + 0, 0x1, val, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 4 0,0   */

/* ROXRW.W (xxx).L */
uae_u32 REGPARAM2 op_e4f9_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 79;
	CurrentInstrCycles = 20; 
	uaecptr dataa;
	dataa = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	dataa |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dataa & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, dataa, 1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 data = get_word_000(dataa);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dataa + 0, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u16 val = data;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();SET_CFLG(val & 1);
		SET_ZFLG(!((val &0x7ffe) | GET_XFLG()))
		;SET_NFLG(GET_XFLG())
		;SET_XFLG(GET_CFLG());
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	uae_u32 carry = val & 1;
	val >>= 1;
	if (GET_XFLG()) val |= 0x8000;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	SET_CFLG(carry);
	COPY_CARRY();
	put_word_000(dataa, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dataa + 0, 0x1, val, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (4/1) */
/* 6 0,0   */

/* ROXLW.W (An) */
uae_u32 REGPARAM2 op_e5d0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 78;
	CurrentInstrCycles = 12; 
	uaecptr dataa;
	dataa = m68k_areg(regs, srcreg);
	if (dataa & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dataa, 1, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 data = get_word_000(dataa);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dataa + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u16 val = data;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();
		SET_CFLG(val & 0x8000);
		SET_ZFLG(!((val & 0x7fff) | GET_XFLG()));
		SET_NFLG(val & 0x4000);
		SET_XFLG(GET_CFLG());
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	uae_u32 carry = val & 0x8000;
	val <<= 1;
	if (GET_XFLG()) val |= 1;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	SET_CFLG(carry >> 15);
	COPY_CARRY();
	put_word_000(dataa, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dataa + 0, 0x1, val, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (2/1) */
/* 2 0,0   */

/* ROXLW.W (An)+ */
uae_u32 REGPARAM2 op_e5d8_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 78;
	CurrentInstrCycles = 12; 
	uaecptr dataa;
	dataa = m68k_areg(regs, srcreg);
	if (dataa & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dataa, 1, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 data = get_word_000(dataa);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) += 2 + 0;
		exception2_read(opcode, dataa + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) += 2;
	uae_u16 val = data;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();
		SET_CFLG(val & 0x8000);
		SET_ZFLG(!((val & 0x7fff) | GET_XFLG()));
		SET_NFLG(val & 0x4000);
		SET_XFLG(GET_CFLG());
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	uae_u32 carry = val & 0x8000;
	val <<= 1;
	if (GET_XFLG()) val |= 1;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	SET_CFLG(carry >> 15);
	COPY_CARRY();
	put_word_000(dataa, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dataa + 0, 0x1, val, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (2/1) */
/* 2 0,0   */

/* ROXLW.W -(An) */
uae_u32 REGPARAM2 op_e5e0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 78;
	CurrentInstrCycles = 14; 
	uaecptr dataa;
	dataa = m68k_areg(regs, srcreg) - 2;
	if (dataa & 1) {
		m68k_incpci(4);
		m68k_areg(regs, srcreg) = dataa;
		exception3_read_access(opcode, dataa, 1, 1);
		return 2 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 data = get_word_000(dataa);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, srcreg) = dataa;
		exception2_read(opcode, dataa + 0, 0x1, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) = dataa;
	uae_u16 val = data;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();
		SET_CFLG(val & 0x8000);
		SET_ZFLG(!((val & 0x7fff) | GET_XFLG()));
		SET_NFLG(val & 0x4000);
		SET_XFLG(GET_CFLG());
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	uae_u32 carry = val & 0x8000;
	val <<= 1;
	if (GET_XFLG()) val |= 1;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	SET_CFLG(carry >> 15);
	COPY_CARRY();
	put_word_000(dataa, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dataa + 0, 0x1, val, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 14 * CYCLE_UNIT / 2 + count_cycles;
}
/* 14 (2/1) */
/* 2 0,0   */

/* ROXLW.W (d16,An) */
uae_u32 REGPARAM2 op_e5e8_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 78;
	CurrentInstrCycles = 16; 
	uaecptr dataa;
	dataa = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dataa & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dataa, 1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 data = get_word_000(dataa);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dataa + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u16 val = data;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();
		SET_CFLG(val & 0x8000);
		SET_ZFLG(!((val & 0x7fff) | GET_XFLG()));
		SET_NFLG(val & 0x4000);
		SET_XFLG(GET_CFLG());
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	uae_u32 carry = val & 0x8000;
	val <<= 1;
	if (GET_XFLG()) val |= 1;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	SET_CFLG(carry >> 15);
	COPY_CARRY();
	put_word_000(dataa, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dataa + 0, 0x1, val, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 4 0,0   */

/* ROXLW.W (d8,An,Xn) */
uae_u32 REGPARAM2 op_e5f0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 78;
	CurrentInstrCycles = 18; 
	uaecptr dataa;
	BusCyclePenalty += 2;
	dataa = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dataa & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dataa, 1, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 data = get_word_000(dataa);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dataa + 0, 0x1, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u16 val = data;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();
		SET_CFLG(val & 0x8000);
		SET_ZFLG(!((val & 0x7fff) | GET_XFLG()));
		SET_NFLG(val & 0x4000);
		SET_XFLG(GET_CFLG());
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	uae_u32 carry = val & 0x8000;
	val <<= 1;
	if (GET_XFLG()) val |= 1;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	SET_CFLG(carry >> 15);
	COPY_CARRY();
	put_word_000(dataa, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dataa + 0, 0x1, val, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (3/1) */
/* 4 4,0   */

/* ROXLW.W (xxx).W */
uae_u32 REGPARAM2 op_e5f8_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 78;
	CurrentInstrCycles = 16; 
	uaecptr dataa;
	dataa = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dataa & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, dataa, 1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 data = get_word_000(dataa);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dataa + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u16 val = data;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();
		SET_CFLG(val & 0x8000);
		SET_ZFLG(!((val & 0x7fff) | GET_XFLG()));
		SET_NFLG(val & 0x4000);
		SET_XFLG(GET_CFLG());
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	uae_u32 carry = val & 0x8000;
	val <<= 1;
	if (GET_XFLG()) val |= 1;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	SET_CFLG(carry >> 15);
	COPY_CARRY();
	put_word_000(dataa, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dataa + 0, 0x1, val, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 4 0,0   */

/* ROXLW.W (xxx).L */
uae_u32 REGPARAM2 op_e5f9_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 78;
	CurrentInstrCycles = 20; 
	uaecptr dataa;
	dataa = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	dataa |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dataa & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, dataa, 1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 data = get_word_000(dataa);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dataa + 0, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u16 val = data;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();
		SET_CFLG(val & 0x8000);
		SET_ZFLG(!((val & 0x7fff) | GET_XFLG()));
		SET_NFLG(val & 0x4000);
		SET_XFLG(GET_CFLG());
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	uae_u32 carry = val & 0x8000;
	val <<= 1;
	if (GET_XFLG()) val |= 1;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	SET_CFLG(carry >> 15);
	COPY_CARRY();
	put_word_000(dataa, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dataa + 0, 0x1, val, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (4/1) */
/* 6 0,0   */

/* RORW.W (An) */
uae_u32 REGPARAM2 op_e6d0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 77;
	CurrentInstrCycles = 12; 
	uaecptr dataa;
	dataa = m68k_areg(regs, srcreg);
	if (dataa & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dataa, 1, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 data = get_word_000(dataa);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dataa + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u16 val = data;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();
		SET_CFLG(val & 1);
		SET_ZFLG(!val);
		SET_NFLG(val & 0x0001);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	uae_u32 carry = val & 1;
	val >>= 1;
	if (carry) val |= 0x8000;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	SET_CFLG(carry);
	put_word_000(dataa, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dataa + 0, 0x1, val, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (2/1) */
/* 2 0,0   */

/* RORW.W (An)+ */
uae_u32 REGPARAM2 op_e6d8_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 77;
	CurrentInstrCycles = 12; 
	uaecptr dataa;
	dataa = m68k_areg(regs, srcreg);
	if (dataa & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dataa, 1, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 data = get_word_000(dataa);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) += 2 + 0;
		exception2_read(opcode, dataa + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) += 2;
	uae_u16 val = data;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();
		SET_CFLG(val & 1);
		SET_ZFLG(!val);
		SET_NFLG(val & 0x0001);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	uae_u32 carry = val & 1;
	val >>= 1;
	if (carry) val |= 0x8000;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	SET_CFLG(carry);
	put_word_000(dataa, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dataa + 0, 0x1, val, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (2/1) */
/* 2 0,0   */

/* RORW.W -(An) */
uae_u32 REGPARAM2 op_e6e0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 77;
	CurrentInstrCycles = 14; 
	uaecptr dataa;
	dataa = m68k_areg(regs, srcreg) - 2;
	if (dataa & 1) {
		m68k_incpci(4);
		m68k_areg(regs, srcreg) = dataa;
		exception3_read_access(opcode, dataa, 1, 1);
		return 2 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 data = get_word_000(dataa);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, srcreg) = dataa;
		exception2_read(opcode, dataa + 0, 0x1, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) = dataa;
	uae_u16 val = data;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();
		SET_CFLG(val & 1);
		SET_ZFLG(!val);
		SET_NFLG(val & 0x0001);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	uae_u32 carry = val & 1;
	val >>= 1;
	if (carry) val |= 0x8000;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	SET_CFLG(carry);
	put_word_000(dataa, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dataa + 0, 0x1, val, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 14 * CYCLE_UNIT / 2 + count_cycles;
}
/* 14 (2/1) */
/* 2 0,0   */

/* RORW.W (d16,An) */
uae_u32 REGPARAM2 op_e6e8_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 77;
	CurrentInstrCycles = 16; 
	uaecptr dataa;
	dataa = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dataa & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dataa, 1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 data = get_word_000(dataa);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dataa + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u16 val = data;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();
		SET_CFLG(val & 1);
		SET_ZFLG(!val);
		SET_NFLG(val & 0x0001);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	uae_u32 carry = val & 1;
	val >>= 1;
	if (carry) val |= 0x8000;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	SET_CFLG(carry);
	put_word_000(dataa, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dataa + 0, 0x1, val, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 4 0,0   */

/* RORW.W (d8,An,Xn) */
uae_u32 REGPARAM2 op_e6f0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 77;
	CurrentInstrCycles = 18; 
	uaecptr dataa;
	BusCyclePenalty += 2;
	dataa = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dataa & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dataa, 1, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 data = get_word_000(dataa);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dataa + 0, 0x1, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u16 val = data;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();
		SET_CFLG(val & 1);
		SET_ZFLG(!val);
		SET_NFLG(val & 0x0001);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	uae_u32 carry = val & 1;
	val >>= 1;
	if (carry) val |= 0x8000;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	SET_CFLG(carry);
	put_word_000(dataa, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dataa + 0, 0x1, val, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (3/1) */
/* 4 4,0   */

/* RORW.W (xxx).W */
uae_u32 REGPARAM2 op_e6f8_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 77;
	CurrentInstrCycles = 16; 
	uaecptr dataa;
	dataa = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dataa & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, dataa, 1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 data = get_word_000(dataa);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dataa + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u16 val = data;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();
		SET_CFLG(val & 1);
		SET_ZFLG(!val);
		SET_NFLG(val & 0x0001);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	uae_u32 carry = val & 1;
	val >>= 1;
	if (carry) val |= 0x8000;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	SET_CFLG(carry);
	put_word_000(dataa, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dataa + 0, 0x1, val, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 4 0,0   */

/* RORW.W (xxx).L */
uae_u32 REGPARAM2 op_e6f9_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 77;
	CurrentInstrCycles = 20; 
	uaecptr dataa;
	dataa = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	dataa |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dataa & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, dataa, 1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 data = get_word_000(dataa);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dataa + 0, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u16 val = data;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();
		SET_CFLG(val & 1);
		SET_ZFLG(!val);
		SET_NFLG(val & 0x0001);
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	uae_u32 carry = val & 1;
	val >>= 1;
	if (carry) val |= 0x8000;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	SET_CFLG(carry);
	put_word_000(dataa, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dataa + 0, 0x1, val, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (4/1) */
/* 6 0,0   */

/* ROLW.W (An) */
uae_u32 REGPARAM2 op_e7d0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 76;
	CurrentInstrCycles = 12; 
	uaecptr dataa;
	dataa = m68k_areg(regs, srcreg);
	if (dataa & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dataa, 1, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 data = get_word_000(dataa);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dataa + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u16 val = data;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();SET_CFLG(val & 0x8000);
		SET_ZFLG(!val);
		SET_NFLG(val & 0x4000);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	uae_u32 carry = val & 0x8000;
	val <<= 1;
	if (carry)  val |= 1;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	SET_CFLG(carry >> 15);
	put_word_000(dataa, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dataa + 0, 0x1, val, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (2/1) */
/* 2 0,0   */

/* ROLW.W (An)+ */
uae_u32 REGPARAM2 op_e7d8_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 76;
	CurrentInstrCycles = 12; 
	uaecptr dataa;
	dataa = m68k_areg(regs, srcreg);
	if (dataa & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dataa, 1, 1);
		return 0 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 data = get_word_000(dataa);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) += 2 + 0;
		exception2_read(opcode, dataa + 0, 0x1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) += 2;
	uae_u16 val = data;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();SET_CFLG(val & 0x8000);
		SET_ZFLG(!val);
		SET_NFLG(val & 0x4000);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	uae_u32 carry = val & 0x8000;
	val <<= 1;
	if (carry)  val |= 1;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	SET_CFLG(carry >> 15);
	put_word_000(dataa, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dataa + 0, 0x1, val, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 12 * CYCLE_UNIT / 2 + count_cycles;
}
/* 12 (2/1) */
/* 2 0,0   */

/* ROLW.W -(An) */
uae_u32 REGPARAM2 op_e7e0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 76;
	CurrentInstrCycles = 14; 
	uaecptr dataa;
	dataa = m68k_areg(regs, srcreg) - 2;
	if (dataa & 1) {
		m68k_incpci(4);
		m68k_areg(regs, srcreg) = dataa;
		exception3_read_access(opcode, dataa, 1, 1);
		return 2 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 data = get_word_000(dataa);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, srcreg) = dataa;
		exception2_read(opcode, dataa + 0, 0x1, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_areg(regs, srcreg) = dataa;
	uae_u16 val = data;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();SET_CFLG(val & 0x8000);
		SET_ZFLG(!val);
		SET_NFLG(val & 0x4000);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	uae_u32 carry = val & 0x8000;
	val <<= 1;
	if (carry)  val |= 1;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	SET_CFLG(carry >> 15);
	put_word_000(dataa, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dataa + 0, 0x1, val, 1);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(2);
	return 14 * CYCLE_UNIT / 2 + count_cycles;
}
/* 14 (2/1) */
/* 2 0,0   */

/* ROLW.W (d16,An) */
uae_u32 REGPARAM2 op_e7e8_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 76;
	CurrentInstrCycles = 16; 
	uaecptr dataa;
	dataa = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dataa & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dataa, 1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 data = get_word_000(dataa);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dataa + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u16 val = data;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();SET_CFLG(val & 0x8000);
		SET_ZFLG(!val);
		SET_NFLG(val & 0x4000);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	uae_u32 carry = val & 0x8000;
	val <<= 1;
	if (carry)  val |= 1;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	SET_CFLG(carry >> 15);
	put_word_000(dataa, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dataa + 0, 0x1, val, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 4 0,0   */

/* ROLW.W (d8,An,Xn) */
uae_u32 REGPARAM2 op_e7f0_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 76;
	CurrentInstrCycles = 18; 
	uaecptr dataa;
	BusCyclePenalty += 2;
	dataa = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dataa & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dataa, 1, 1);
		return 6 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 data = get_word_000(dataa);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dataa + 0, 0x1, 1);
		return 10 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u16 val = data;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();SET_CFLG(val & 0x8000);
		SET_ZFLG(!val);
		SET_NFLG(val & 0x4000);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 14 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	uae_u32 carry = val & 0x8000;
	val <<= 1;
	if (carry)  val |= 1;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	SET_CFLG(carry >> 15);
	put_word_000(dataa, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dataa + 0, 0x1, val, 1);
		return 18 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 18 * CYCLE_UNIT / 2 + count_cycles;
}
/* 18 (3/1) */
/* 4 4,0   */

/* ROLW.W (xxx).W */
uae_u32 REGPARAM2 op_e7f8_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 76;
	CurrentInstrCycles = 16; 
	uaecptr dataa;
	dataa = (uae_s32)(uae_s16)get_word_000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dataa & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, dataa, 1, 1);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 data = get_word_000(dataa);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dataa + 0, 0x1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u16 val = data;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();SET_CFLG(val & 0x8000);
		SET_ZFLG(!val);
		SET_NFLG(val & 0x4000);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	uae_u32 carry = val & 0x8000;
	val <<= 1;
	if (carry)  val |= 1;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	SET_CFLG(carry >> 15);
	put_word_000(dataa, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dataa + 0, 0x1, val, 1);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(4);
	return 16 * CYCLE_UNIT / 2 + count_cycles;
}
/* 16 (3/1) */
/* 4 0,0   */

/* ROLW.W (xxx).L */
uae_u32 REGPARAM2 op_e7f9_12_ff(uae_u32 opcode)
{
	int count_cycles = 0;
	OpcodeFamily = 76;
	CurrentInstrCycles = 20; 
	uaecptr dataa;
	dataa = get_word_000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return 4 * CYCLE_UNIT / 2 + count_cycles;
	}
	dataa |= get_word_000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	if (dataa & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, dataa, 1, 1);
		return 8 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_s16 data = get_word_000(dataa);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dataa + 0, 0x1, 1);
		return 12 * CYCLE_UNIT / 2 + count_cycles;
	}
	uae_u16 val = data;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();SET_CFLG(val & 0x8000);
		SET_ZFLG(!val);
		SET_NFLG(val & 0x4000);
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return 16 * CYCLE_UNIT / 2 + count_cycles;
	}
	opcode = regs.ir;
	uae_u32 carry = val & 0x8000;
	val <<= 1;
	if (carry)  val |= 1;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	SET_CFLG(carry >> 15);
	put_word_000(dataa, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dataa + 0, 0x1, val, 1);
		return 20 * CYCLE_UNIT / 2 + count_cycles;
	}
	m68k_incpci(6);
	return 20 * CYCLE_UNIT / 2 + count_cycles;
}
/* 20 (4/1) */
/* 6 0,0   */

