#include "main.h"
#include "sysdeps.h"
#include "hatari-glue.h"
#include "maccess.h"
#include "memory.h"
#include "custom.h"
#include "newcpu.h"
#include "cpu_prefetch.h"
#include "cputbl.h"
#include "debugmem.h"
#define SET_ALWAYS_CFLG(x) SET_CFLG(x)
#define SET_ALWAYS_NFLG(x) SET_NFLG(x)
/* OR.B #<data>.B,Dn */
void REGPARAM2 op_0000_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 8;  
	uae_s8 src = (uae_u8)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uae_s8 dst = m68k_dreg(regs, dstreg);
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 8 (2/0) */
/* 4 0,0   */

/* OR.B #<data>.B,(An) */
void REGPARAM2 op_0010_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 16; 
	uae_s8 src = (uae_u8)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_byte(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* OR.B #<data>.B,(An)+ */
void REGPARAM2 op_0018_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 16; 
	uae_s8 src = (uae_u8)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_byte(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* OR.B #<data>.B,-(An) */
void REGPARAM2 op_0020_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 18; 
	uae_s8 src = (uae_u8)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
	do_cycles_ce000_internal(2);
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, dstreg) = dsta;
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	m68k_areg(regs, dstreg) = dsta;
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_byte(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 18 (3/1) */
/* 4 0,0   */

/* OR.B #<data>.B,(d16,An) */
void REGPARAM2 op_0028_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 20; 
	uae_s8 src = (uae_u8)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return;
	}
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_byte(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 20 (4/1) */
/* 6 0,0   */

/* OR.B #<data>.B,(d8,An,Xn) */
void REGPARAM2 op_0030_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 22; 
	uae_s8 src = (uae_u8)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr dsta;
	do_cycles_ce000_internal(2);
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_ce000_prefetch(6));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return;
	}
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_byte(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 22 (4/1) */
/* 6 4,0   */

/* OR.B #<data>.B,(xxx).W */
void REGPARAM2 op_0038_13_ff(uae_u32 opcode)
{
	OpcodeFamily = 1;
	CurrentInstrCycles = 20; 
	uae_s8 src = (uae_u8)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, 0);
		return;
	}
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_byte(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 20 (4/1) */
/* 6 0,0   */

/* OR.B #<data>.B,(xxx).L */
void REGPARAM2 op_0039_13_ff(uae_u32 opcode)
{
	OpcodeFamily = 1;
	CurrentInstrCycles = 24; 
	uae_s8 src = (uae_u8)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr dsta;
	dsta = get_word_ce000_prefetch(6) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return;
	}
	dsta |= get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 8, pcoffset);
		return;
	}
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(10);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 10, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_byte(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(10);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return;
	}
	m68k_incpci(8);
	return;
}
/* 24 (5/1) */
/* 8 0,0   */

/* ORSR.B #<data>.W */
void REGPARAM2 op_003c_13_ff(uae_u32 opcode)
{
	OpcodeFamily = 4;
	CurrentInstrCycles = 16; 
	MakeSR();
	uae_s16 src = regs.irc;
	src &= 0xFF;
	do_cycles_ce000_internal(8);
	regs.sr |= src;
	MakeFromSR();
	m68k_incpci(4);
	get_word_ce000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, 0);
		return;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 16 (2/0) */
/* 4 0,0   */

/* OR.W #<data>.W,Dn */
void REGPARAM2 op_0040_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 8;  
	uae_s16 src = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 8 (2/0) */
/* 4 0,0   */

/* OR.W #<data>.W,(An) */
void REGPARAM2 op_0050_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 16; 
	uae_s16 src = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	if (dsta & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, dsta, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 dst = x_get_word(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_word(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* OR.W #<data>.W,(An)+ */
void REGPARAM2 op_0058_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 16; 
	uae_s16 src = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	if (dsta & 1) {
		m68k_areg(regs, dstreg) += 2 + 0;
		m68k_incpci(4);
		exception3_read_access(opcode, dsta, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 dst = x_get_word(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, dstreg) += 2 + 0;
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	m68k_areg(regs, dstreg) += 2;
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_word(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* OR.W #<data>.W,-(An) */
void REGPARAM2 op_0060_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 18; 
	uae_s16 src = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - 2;
	do_cycles_ce000_internal(2);
	if (dsta & 1) {
		m68k_areg(regs, dstreg) = dsta;
		m68k_incpci(4);
		exception3_read_access(opcode, dsta, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 dst = x_get_word(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, dstreg) = dsta;
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	m68k_areg(regs, dstreg) = dsta;
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_word(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 18 (3/1) */
/* 4 0,0   */

/* OR.W #<data>.W,(d16,An) */
void REGPARAM2 op_0068_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 20; 
	uae_s16 src = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, dsta, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 dst = x_get_word(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_word(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 20 (4/1) */
/* 6 0,0   */

/* OR.W #<data>.W,(d8,An,Xn) */
void REGPARAM2 op_0070_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 22; 
	uae_s16 src = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr dsta;
	do_cycles_ce000_internal(2);
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_ce000_prefetch(6));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, dsta, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 dst = x_get_word(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_word(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 22 (4/1) */
/* 6 4,0   */

/* OR.W #<data>.W,(xxx).W */
void REGPARAM2 op_0078_13_ff(uae_u32 opcode)
{
	OpcodeFamily = 1;
	CurrentInstrCycles = 20; 
	uae_s16 src = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, 0);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, dsta, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 dst = x_get_word(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_word(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 20 (4/1) */
/* 6 0,0   */

/* OR.W #<data>.W,(xxx).L */
void REGPARAM2 op_0079_13_ff(uae_u32 opcode)
{
	OpcodeFamily = 1;
	CurrentInstrCycles = 24; 
	uae_s16 src = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr dsta;
	dsta = get_word_ce000_prefetch(6) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return;
	}
	dsta |= get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 8, pcoffset);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(8);
		exception3_read_access(opcode, dsta, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 dst = x_get_word(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(10);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 10, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_word(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(10);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return;
	}
	m68k_incpci(8);
	return;
}
/* 24 (5/1) */
/* 8 0,0   */

/* ORSR.W #<data>.W */
void REGPARAM2 op_007c_13_ff(uae_u32 opcode)
{
	OpcodeFamily = 4;
	CurrentInstrCycles = 16; 
	if (!regs.s) {
		Exception(8);
		return;
	}
	MakeSR();
	uae_s16 src = regs.irc;
	do_cycles_ce000_internal(8);
	regs.sr |= src;
	MakeFromSR();
	m68k_incpci(4);
	get_word_ce000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, 0);
		return;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 16 (2/0) */
/* 4 0,0   */

/* OR.L #<data>.L,Dn */
void REGPARAM2 op_0080_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 16; 
	uae_s32 src;
	src = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	src |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		m68k_dreg(regs, dstreg) = (src);
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	do_cycles_ce000_internal(4);
	m68k_dreg(regs, dstreg) = (src);
	m68k_incpci(6);
	return;
}
/* 16 (3/0) */
/* 6 0,0   */

/* OR.L #<data>.L,(An) */
void REGPARAM2 op_0090_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 28; 
	uae_s32 src;
	src = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	src |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	if (dsta & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, dsta, 2, 1);
		return;
	}
	uae_s32 dst = x_get_word(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	dst |= x_get_word(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return;
	}
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	x_put_word(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return;
	}
	x_put_word(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 28 (5/2) */
/* 6 0,0   */

/* OR.L #<data>.L,(An)+ */
void REGPARAM2 op_0098_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 28; 
	uae_s32 src;
	src = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	src |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	if (dsta & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, dsta, 2, 1);
		return;
	}
	uae_s32 dst = x_get_word(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	dst |= x_get_word(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return;
	}
	m68k_areg(regs, dstreg) += 4;
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	x_put_word(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return;
	}
	x_put_word(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 28 (5/2) */
/* 6 0,0   */

/* OR.L #<data>.L,-(An) */
void REGPARAM2 op_00a0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 30; 
	uae_s32 src;
	src = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	src |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - 4;
	do_cycles_ce000_internal(2);
	if (dsta & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, dsta, 2, 1);
		return;
	}
	uae_s32 dst = x_get_word(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	dst |= x_get_word(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		m68k_areg(regs, dstreg) = dsta;
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return;
	}
	m68k_areg(regs, dstreg) = dsta;
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	x_put_word(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return;
	}
	x_put_word(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 30 (5/2) */
/* 6 0,0   */

/* OR.L #<data>.L,(d16,An) */
void REGPARAM2 op_00a8_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 32; 
	uae_s32 src;
	src = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	src |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 8, -2);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, dsta, 2, 1);
		return;
	}
	uae_s32 dst = x_get_word(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	dst |= x_get_word(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return;
	}
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(10);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch_opcode(opcode, 10, pcoffset);
		return;
	}
	x_put_word(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(10);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return;
	}
	x_put_word(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(10);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return;
	}
	m68k_incpci(8);
	return;
}
/* 32 (6/2) */
/* 8 0,0   */

/* OR.L #<data>.L,(d8,An,Xn) */
void REGPARAM2 op_00b0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 34; 
	uae_s32 src;
	src = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	src |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	uaecptr dsta;
	do_cycles_ce000_internal(2);
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_ce000_prefetch(8));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 8, -2);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, dsta, 2, 1);
		return;
	}
	uae_s32 dst = x_get_word(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	dst |= x_get_word(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return;
	}
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(10);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch_opcode(opcode, 10, pcoffset);
		return;
	}
	x_put_word(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(10);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return;
	}
	x_put_word(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(10);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return;
	}
	m68k_incpci(8);
	return;
}
/* 34 (6/2) */
/* 8 4,0   */

/* OR.L #<data>.L,(xxx).W */
void REGPARAM2 op_00b8_13_ff(uae_u32 opcode)
{
	OpcodeFamily = 1;
	CurrentInstrCycles = 32; 
	uae_s32 src;
	src = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	src |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 8, 0);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(8);
		exception3_read_access(opcode, dsta, 2, 1);
		return;
	}
	uae_s32 dst = x_get_word(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	dst |= x_get_word(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return;
	}
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(10);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch_opcode(opcode, 10, pcoffset);
		return;
	}
	x_put_word(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(10);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return;
	}
	x_put_word(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(10);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return;
	}
	m68k_incpci(8);
	return;
}
/* 32 (6/2) */
/* 8 0,0   */

/* OR.L #<data>.L,(xxx).L */
void REGPARAM2 op_00b9_13_ff(uae_u32 opcode)
{
	OpcodeFamily = 1;
	CurrentInstrCycles = 36; 
	uae_s32 src;
	src = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	src |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	uaecptr dsta;
	dsta = get_word_ce000_prefetch(8) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 8, -2);
		return;
	}
	dsta |= get_word_ce000_prefetch(10);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 10, pcoffset);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(10);
		exception3_read_access(opcode, dsta, 2, 1);
		return;
	}
	uae_s32 dst = x_get_word(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(10);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	dst |= x_get_word(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(10);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return;
	}
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(12);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch_opcode(opcode, 12, pcoffset);
		return;
	}
	x_put_word(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(12);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return;
	}
	x_put_word(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(12);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return;
	}
	m68k_incpci(10);
	return;
}
/* 36 (7/2) */
/* 10 0,0   */

/* BTST.L Dn,Dn */
void REGPARAM2 op_0100_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 21;
	CurrentInstrCycles = 6;  
	ipl_fetch_next_pre();
	uae_s32 src = m68k_dreg(regs, srcreg);
	uae_s32 dst = m68k_dreg(regs, dstreg);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	src &= 31;
	do_cycles_ce000_internal(2);
	SET_ZFLG(1 ^ ((dst >> src) & 1));
	m68k_incpci(2);
	return;
}
/* 6 (1/0) */
/* 2 0,0   */

/* MVPMR.W (d16,An),Dn */
void REGPARAM2 op_0108_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 29;
	CurrentInstrCycles = 16; 
	uaecptr mempa = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	ipl_fetch_now();
	uae_u16 val  = (x_get_byte(mempa) & 0xff) << 8;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		opcode |= 0x10000;
		exception2_read(opcode, mempa + 0, 0x0, 1);
		return;
	}
	val |= (x_get_byte(mempa + 2) & 0xff);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, mempa + 2, 0x0, 1);
		return;
	}
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((val) & 0xffff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (4/0) */
/* 4 0,0   */

/* BTST.B Dn,(An) */
void REGPARAM2 op_0110_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 21;
	CurrentInstrCycles = 8;  
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	src &= 7;
	SET_ZFLG(1 ^ ((dst >> src) & 1));
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 8 (2/0) */
/* 2 0,0   */

/* BTST.B Dn,(An)+ */
void REGPARAM2 op_0118_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 21;
	CurrentInstrCycles = 8;  
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
	src &= 7;
	SET_ZFLG(1 ^ ((dst >> src) & 1));
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 8 (2/0) */
/* 2 0,0   */

/* BTST.B Dn,-(An) */
void REGPARAM2 op_0120_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 21;
	CurrentInstrCycles = 10; 
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
	do_cycles_ce000_internal(2);
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, dstreg) = dsta;
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	m68k_areg(regs, dstreg) = dsta;
	src &= 7;
	SET_ZFLG(1 ^ ((dst >> src) & 1));
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 10 (2/0) */
/* 2 0,0   */

/* BTST.B Dn,(d16,An) */
void REGPARAM2 op_0128_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 21;
	CurrentInstrCycles = 12; 
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	src &= 7;
	SET_ZFLG(1 ^ ((dst >> src) & 1));
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 12 (3/0) */
/* 4 0,0   */

/* BTST.B Dn,(d8,An,Xn) */
void REGPARAM2 op_0130_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 21;
	CurrentInstrCycles = 14; 
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	do_cycles_ce000_internal(2);
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	src &= 7;
	SET_ZFLG(1 ^ ((dst >> src) & 1));
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 14 (3/0) */
/* 4 4,0   */

/* BTST.B Dn,(xxx).W */
void REGPARAM2 op_0138_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	OpcodeFamily = 21;
	CurrentInstrCycles = 12; 
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	src &= 7;
	SET_ZFLG(1 ^ ((dst >> src) & 1));
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 12 (3/0) */
/* 4 0,0   */

/* BTST.B Dn,(xxx).L */
void REGPARAM2 op_0139_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	OpcodeFamily = 21;
	CurrentInstrCycles = 16; 
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	dsta |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	src &= 7;
	SET_ZFLG(1 ^ ((dst >> src) & 1));
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 16 (4/0) */
/* 6 0,0   */

/* BTST.B Dn,(d16,PC) */
void REGPARAM2 op_013a_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = 2;
	OpcodeFamily = 21;
	CurrentInstrCycles = 12; 
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_getpci() + 2;
	dsta += (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x0, 2);
		return;
	}
	src &= 7;
	SET_ZFLG(1 ^ ((dst >> src) & 1));
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 12 (3/0) */
/* 4 0,0   */

/* BTST.B Dn,(d8,PC,Xn) */
void REGPARAM2 op_013b_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = 3;
	OpcodeFamily = 21;
	CurrentInstrCycles = 14; 
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	uaecptr tmppc = m68k_getpci() + 2;
	do_cycles_ce000_internal(2);
	dsta = get_disp_ea_000(tmppc, get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x0, 2);
		return;
	}
	src &= 7;
	SET_ZFLG(1 ^ ((dst >> src) & 1));
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 14 (3/0) */
/* 4 4,0   */

/* BTST.B Dn,#<data>.B */
void REGPARAM2 op_013c_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	OpcodeFamily = 21;
	CurrentInstrCycles = 10; 
	uae_s8 src = m68k_dreg(regs, srcreg);
	uae_s8 dst = (uae_u8)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	src &= 7;
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	do_cycles_ce000_internal(2);
	SET_ZFLG(1 ^ ((dst >> src) & 1));
	m68k_incpci(4);
	return;
}
/* 10 (2/0) */
/* 4 0,0   */

/* BCHG.L Dn,Dn */
void REGPARAM2 op_0140_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 22;
	CurrentInstrCycles = 6;  
	uae_s32 src = m68k_dreg(regs, srcreg);
	uae_s32 dst = m68k_dreg(regs, dstreg);
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	src &= 31;
	do_cycles_ce000_internal(2);
	if (src > 15) do_cycles_ce000_internal(2);
	dst ^= (1 << src);
	SET_ZFLG(((uae_u32)dst & (1 << src)) >> src);
	m68k_dreg(regs, dstreg) = (dst);
	m68k_incpci(2);
	return;
}
/* 6 (1/0) */
/* 2 0,0   */

/* MVPMR.L (d16,An),Dn */
void REGPARAM2 op_0148_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 29;
	CurrentInstrCycles = 24; 
	uaecptr mempa = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	uae_u32 val  = (x_get_byte(mempa) & 0xff) << 24;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		opcode |= 0x10000;
		exception2_read(opcode, mempa + 0, 0x0, 1);
		return;
	}
	val |= (x_get_byte(mempa + 2) & 0xff) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, mempa + 2, 0x0, 1);
		return;
	}
	ipl_fetch_now();
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & 0x0000ffff) | val;
	val |= (x_get_byte(mempa + 4) & 0xff) << 8;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		opcode |= 0x10000;
		exception2_read(opcode, mempa + 4, 0x0, 1);
		return;
	}
	val |= (x_get_byte(mempa + 6) & 0xff);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, mempa + 6, 0x0, 1);
		return;
	}
	m68k_dreg(regs, dstreg) = (val);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 24 (6/0) */
/* 4 0,0   */

/* BCHG.B Dn,(An) */
void REGPARAM2 op_0150_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 22;
	CurrentInstrCycles = 12; 
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	regs.ir = regs.irc;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	src &= 7;
	dst ^= (1 << src);
	SET_ZFLG(((uae_u32)dst & (1 << src)) >> src);
	x_put_byte(dsta, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x0, dst, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 12 (2/1) */
/* 2 0,0   */

/* BCHG.B Dn,(An)+ */
void REGPARAM2 op_0158_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 22;
	CurrentInstrCycles = 12; 
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
	regs.ir = regs.irc;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	src &= 7;
	dst ^= (1 << src);
	SET_ZFLG(((uae_u32)dst & (1 << src)) >> src);
	x_put_byte(dsta, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x0, dst, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 12 (2/1) */
/* 2 0,0   */

/* BCHG.B Dn,-(An) */
void REGPARAM2 op_0160_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 22;
	CurrentInstrCycles = 14; 
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
	do_cycles_ce000_internal(2);
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, dstreg) = dsta;
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	m68k_areg(regs, dstreg) = dsta;
	regs.ir = regs.irc;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	src &= 7;
	dst ^= (1 << src);
	SET_ZFLG(((uae_u32)dst & (1 << src)) >> src);
	x_put_byte(dsta, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x0, dst, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 14 (2/1) */
/* 2 0,0   */

/* BCHG.B Dn,(d16,An) */
void REGPARAM2 op_0168_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 22;
	CurrentInstrCycles = 16; 
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	src &= 7;
	dst ^= (1 << src);
	SET_ZFLG(((uae_u32)dst & (1 << src)) >> src);
	x_put_byte(dsta, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x0, dst, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* BCHG.B Dn,(d8,An,Xn) */
void REGPARAM2 op_0170_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 22;
	CurrentInstrCycles = 18; 
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	do_cycles_ce000_internal(2);
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	src &= 7;
	dst ^= (1 << src);
	SET_ZFLG(((uae_u32)dst & (1 << src)) >> src);
	x_put_byte(dsta, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x0, dst, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 18 (3/1) */
/* 4 4,0   */

/* BCHG.B Dn,(xxx).W */
void REGPARAM2 op_0178_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	OpcodeFamily = 22;
	CurrentInstrCycles = 16; 
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	src &= 7;
	dst ^= (1 << src);
	SET_ZFLG(((uae_u32)dst & (1 << src)) >> src);
	x_put_byte(dsta, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x0, dst, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* BCHG.B Dn,(xxx).L */
void REGPARAM2 op_0179_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	OpcodeFamily = 22;
	CurrentInstrCycles = 20; 
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	dsta |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	regs.ir = regs.irc;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	opcode = regs.ir;
	src &= 7;
	dst ^= (1 << src);
	SET_ZFLG(((uae_u32)dst & (1 << src)) >> src);
	x_put_byte(dsta, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 0, 0x0, dst, 1);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 20 (4/1) */
/* 6 0,0   */

/* BCLR.L Dn,Dn */
void REGPARAM2 op_0180_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 23;
	CurrentInstrCycles = 8;  
	uae_s32 src = m68k_dreg(regs, srcreg);
	uae_s32 dst = m68k_dreg(regs, dstreg);
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	src &= 31;
	do_cycles_ce000_internal(2);
	if (src > 15) do_cycles_ce000_internal(2);
	do_cycles_ce000_internal(2);
	SET_ZFLG(1 ^ ((dst >> src) & 1));
	dst &= ~(1 << src);
	m68k_dreg(regs, dstreg) = (dst);
	m68k_incpci(2);
	return;
}
/* 8 (1/0) */
/* 2 0,0   */

/* MVPRM.W Dn,(d16,An) */
void REGPARAM2 op_0188_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 28;
	CurrentInstrCycles = 16; 
	uae_s16 src = m68k_dreg(regs, srcreg);
	uaecptr mempa = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	x_put_byte(mempa, src >> 8);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		opcode |= 0x10000;
		uae_u16 val = src;
		exception2_write(opcode, mempa + 0, 0x100, val, 1);
		return;
	}
	x_put_byte(mempa + 2, src); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		uae_u16 val = src;
		exception2_write(opcode, mempa + 2, 0x100, val, 1);
		return;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (2/2) */
/* 4 0,0   */

/* BCLR.B Dn,(An) */
void REGPARAM2 op_0190_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 23;
	CurrentInstrCycles = 14; 
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	regs.ir = regs.irc;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	src &= 7;
	do_cycles_ce000_internal(2);
	SET_ZFLG(1 ^ ((dst >> src) & 1));
	dst &= ~(1 << src);
	x_put_byte(dsta, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x0, dst, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 14 (2/1) */
/* 2 0,0   */

/* BCLR.B Dn,(An)+ */
void REGPARAM2 op_0198_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 23;
	CurrentInstrCycles = 14; 
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
	regs.ir = regs.irc;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	src &= 7;
	do_cycles_ce000_internal(2);
	SET_ZFLG(1 ^ ((dst >> src) & 1));
	dst &= ~(1 << src);
	x_put_byte(dsta, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x0, dst, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 14 (2/1) */
/* 2 0,0   */

/* BCLR.B Dn,-(An) */
void REGPARAM2 op_01a0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 23;
	CurrentInstrCycles = 16; 
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
	do_cycles_ce000_internal(2);
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, dstreg) = dsta;
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	m68k_areg(regs, dstreg) = dsta;
	regs.ir = regs.irc;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	src &= 7;
	do_cycles_ce000_internal(2);
	SET_ZFLG(1 ^ ((dst >> src) & 1));
	dst &= ~(1 << src);
	x_put_byte(dsta, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x0, dst, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 16 (2/1) */
/* 2 0,0   */

/* BCLR.B Dn,(d16,An) */
void REGPARAM2 op_01a8_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 23;
	CurrentInstrCycles = 18; 
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	src &= 7;
	do_cycles_ce000_internal(2);
	SET_ZFLG(1 ^ ((dst >> src) & 1));
	dst &= ~(1 << src);
	x_put_byte(dsta, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x0, dst, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 18 (3/1) */
/* 4 0,0   */

/* BCLR.B Dn,(d8,An,Xn) */
void REGPARAM2 op_01b0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 23;
	CurrentInstrCycles = 20; 
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	do_cycles_ce000_internal(2);
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	src &= 7;
	do_cycles_ce000_internal(2);
	SET_ZFLG(1 ^ ((dst >> src) & 1));
	dst &= ~(1 << src);
	x_put_byte(dsta, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x0, dst, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 20 (3/1) */
/* 4 4,0   */

/* BCLR.B Dn,(xxx).W */
void REGPARAM2 op_01b8_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	OpcodeFamily = 23;
	CurrentInstrCycles = 18; 
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	src &= 7;
	do_cycles_ce000_internal(2);
	SET_ZFLG(1 ^ ((dst >> src) & 1));
	dst &= ~(1 << src);
	x_put_byte(dsta, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x0, dst, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 18 (3/1) */
/* 4 0,0   */

/* BCLR.B Dn,(xxx).L */
void REGPARAM2 op_01b9_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	OpcodeFamily = 23;
	CurrentInstrCycles = 22; 
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	dsta |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	regs.ir = regs.irc;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	opcode = regs.ir;
	src &= 7;
	do_cycles_ce000_internal(2);
	SET_ZFLG(1 ^ ((dst >> src) & 1));
	dst &= ~(1 << src);
	x_put_byte(dsta, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 0, 0x0, dst, 1);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 22 (4/1) */
/* 6 0,0   */

/* BSET.L Dn,Dn */
void REGPARAM2 op_01c0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 24;
	CurrentInstrCycles = 6;  
	uae_s32 src = m68k_dreg(regs, srcreg);
	uae_s32 dst = m68k_dreg(regs, dstreg);
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	src &= 31;
	do_cycles_ce000_internal(2);
	if (src > 15) do_cycles_ce000_internal(2);
	SET_ZFLG(1 ^ ((dst >> src) & 1));
	dst |= (1 << src);
	m68k_dreg(regs, dstreg) = (dst);
	m68k_incpci(2);
	return;
}
/* 6 (1/0) */
/* 2 0,0   */

/* MVPRM.L Dn,(d16,An) */
void REGPARAM2 op_01c8_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 28;
	CurrentInstrCycles = 24; 
	uae_s32 src = m68k_dreg(regs, srcreg);
	uaecptr mempa = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	x_put_byte(mempa, src >> 24);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		opcode |= 0x10000;
		uae_u16 val = src >> 16;
		exception2_write(opcode, mempa + 0, 0x100, val, 1);
		return;
	}
	x_put_byte(mempa + 2, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		uae_u16 val = src >> 16;
		exception2_write(opcode, mempa + 2, 0x100, val, 1);
		return;
	}
	x_put_byte(mempa + 4, src >> 8);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		opcode |= 0x10000;
		uae_u16 val = src >> 0;
		exception2_write(opcode, mempa + 4, 0x100, val, 1);
		return;
	}
	x_put_byte(mempa + 6, src); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		uae_u16 val = src >> 0;
		exception2_write(opcode, mempa + 6, 0x100, val, 1);
		return;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 24 (2/4) */
/* 4 0,0   */

/* BSET.B Dn,(An) */
void REGPARAM2 op_01d0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 24;
	CurrentInstrCycles = 12; 
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	regs.ir = regs.irc;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	src &= 7;
	SET_ZFLG(1 ^ ((dst >> src) & 1));
	dst |= (1 << src);
	x_put_byte(dsta, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x0, dst, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 12 (2/1) */
/* 2 0,0   */

/* BSET.B Dn,(An)+ */
void REGPARAM2 op_01d8_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 24;
	CurrentInstrCycles = 12; 
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
	regs.ir = regs.irc;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	src &= 7;
	SET_ZFLG(1 ^ ((dst >> src) & 1));
	dst |= (1 << src);
	x_put_byte(dsta, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x0, dst, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 12 (2/1) */
/* 2 0,0   */

/* BSET.B Dn,-(An) */
void REGPARAM2 op_01e0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 24;
	CurrentInstrCycles = 14; 
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
	do_cycles_ce000_internal(2);
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, dstreg) = dsta;
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	m68k_areg(regs, dstreg) = dsta;
	regs.ir = regs.irc;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	src &= 7;
	SET_ZFLG(1 ^ ((dst >> src) & 1));
	dst |= (1 << src);
	x_put_byte(dsta, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x0, dst, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 14 (2/1) */
/* 2 0,0   */

/* BSET.B Dn,(d16,An) */
void REGPARAM2 op_01e8_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 24;
	CurrentInstrCycles = 16; 
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	src &= 7;
	SET_ZFLG(1 ^ ((dst >> src) & 1));
	dst |= (1 << src);
	x_put_byte(dsta, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x0, dst, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* BSET.B Dn,(d8,An,Xn) */
void REGPARAM2 op_01f0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 24;
	CurrentInstrCycles = 18; 
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	do_cycles_ce000_internal(2);
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	src &= 7;
	SET_ZFLG(1 ^ ((dst >> src) & 1));
	dst |= (1 << src);
	x_put_byte(dsta, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x0, dst, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 18 (3/1) */
/* 4 4,0   */

/* BSET.B Dn,(xxx).W */
void REGPARAM2 op_01f8_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	OpcodeFamily = 24;
	CurrentInstrCycles = 16; 
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	src &= 7;
	SET_ZFLG(1 ^ ((dst >> src) & 1));
	dst |= (1 << src);
	x_put_byte(dsta, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x0, dst, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* BSET.B Dn,(xxx).L */
void REGPARAM2 op_01f9_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	OpcodeFamily = 24;
	CurrentInstrCycles = 20; 
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	dsta |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	regs.ir = regs.irc;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	opcode = regs.ir;
	src &= 7;
	SET_ZFLG(1 ^ ((dst >> src) & 1));
	dst |= (1 << src);
	x_put_byte(dsta, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 0, 0x0, dst, 1);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 20 (4/1) */
/* 6 0,0   */

/* AND.B #<data>.B,Dn */
void REGPARAM2 op_0200_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 8;  
	uae_s8 src = (uae_u8)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uae_s8 dst = m68k_dreg(regs, dstreg);
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 8 (2/0) */
/* 4 0,0   */

/* AND.B #<data>.B,(An) */
void REGPARAM2 op_0210_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 16; 
	uae_s8 src = (uae_u8)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_byte(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* AND.B #<data>.B,(An)+ */
void REGPARAM2 op_0218_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 16; 
	uae_s8 src = (uae_u8)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_byte(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* AND.B #<data>.B,-(An) */
void REGPARAM2 op_0220_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 18; 
	uae_s8 src = (uae_u8)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
	do_cycles_ce000_internal(2);
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, dstreg) = dsta;
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	m68k_areg(regs, dstreg) = dsta;
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_byte(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 18 (3/1) */
/* 4 0,0   */

/* AND.B #<data>.B,(d16,An) */
void REGPARAM2 op_0228_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 20; 
	uae_s8 src = (uae_u8)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return;
	}
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_byte(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 20 (4/1) */
/* 6 0,0   */

/* AND.B #<data>.B,(d8,An,Xn) */
void REGPARAM2 op_0230_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 22; 
	uae_s8 src = (uae_u8)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr dsta;
	do_cycles_ce000_internal(2);
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_ce000_prefetch(6));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return;
	}
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_byte(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 22 (4/1) */
/* 6 4,0   */

/* AND.B #<data>.B,(xxx).W */
void REGPARAM2 op_0238_13_ff(uae_u32 opcode)
{
	OpcodeFamily = 2;
	CurrentInstrCycles = 20; 
	uae_s8 src = (uae_u8)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, 0);
		return;
	}
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_byte(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 20 (4/1) */
/* 6 0,0   */

/* AND.B #<data>.B,(xxx).L */
void REGPARAM2 op_0239_13_ff(uae_u32 opcode)
{
	OpcodeFamily = 2;
	CurrentInstrCycles = 24; 
	uae_s8 src = (uae_u8)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr dsta;
	dsta = get_word_ce000_prefetch(6) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return;
	}
	dsta |= get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 8, pcoffset);
		return;
	}
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(10);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 10, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_byte(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(10);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return;
	}
	m68k_incpci(8);
	return;
}
/* 24 (5/1) */
/* 8 0,0   */

/* ANDSR.B #<data>.W */
void REGPARAM2 op_023c_13_ff(uae_u32 opcode)
{
	OpcodeFamily = 5;
	CurrentInstrCycles = 16; 
	MakeSR();
	uae_s16 src = regs.irc;
	src &= 0xFF;
	src |= 0xff00;
	do_cycles_ce000_internal(8);
	regs.sr &= src;
	MakeFromSR();
	m68k_incpci(4);
	get_word_ce000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, 0);
		return;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 16 (2/0) */
/* 4 0,0   */

/* AND.W #<data>.W,Dn */
void REGPARAM2 op_0240_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 8;  
	uae_s16 src = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 8 (2/0) */
/* 4 0,0   */

/* AND.W #<data>.W,(An) */
void REGPARAM2 op_0250_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 16; 
	uae_s16 src = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	if (dsta & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, dsta, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 dst = x_get_word(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_word(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* AND.W #<data>.W,(An)+ */
void REGPARAM2 op_0258_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 16; 
	uae_s16 src = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	if (dsta & 1) {
		m68k_areg(regs, dstreg) += 2 + 0;
		m68k_incpci(4);
		exception3_read_access(opcode, dsta, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 dst = x_get_word(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, dstreg) += 2 + 0;
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	m68k_areg(regs, dstreg) += 2;
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_word(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* AND.W #<data>.W,-(An) */
void REGPARAM2 op_0260_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 18; 
	uae_s16 src = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - 2;
	do_cycles_ce000_internal(2);
	if (dsta & 1) {
		m68k_areg(regs, dstreg) = dsta;
		m68k_incpci(4);
		exception3_read_access(opcode, dsta, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 dst = x_get_word(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, dstreg) = dsta;
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	m68k_areg(regs, dstreg) = dsta;
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_word(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 18 (3/1) */
/* 4 0,0   */

/* AND.W #<data>.W,(d16,An) */
void REGPARAM2 op_0268_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 20; 
	uae_s16 src = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, dsta, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 dst = x_get_word(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_word(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 20 (4/1) */
/* 6 0,0   */

/* AND.W #<data>.W,(d8,An,Xn) */
void REGPARAM2 op_0270_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 22; 
	uae_s16 src = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr dsta;
	do_cycles_ce000_internal(2);
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_ce000_prefetch(6));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, dsta, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 dst = x_get_word(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_word(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 22 (4/1) */
/* 6 4,0   */

/* AND.W #<data>.W,(xxx).W */
void REGPARAM2 op_0278_13_ff(uae_u32 opcode)
{
	OpcodeFamily = 2;
	CurrentInstrCycles = 20; 
	uae_s16 src = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, 0);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, dsta, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 dst = x_get_word(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_word(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 20 (4/1) */
/* 6 0,0   */

/* AND.W #<data>.W,(xxx).L */
void REGPARAM2 op_0279_13_ff(uae_u32 opcode)
{
	OpcodeFamily = 2;
	CurrentInstrCycles = 24; 
	uae_s16 src = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr dsta;
	dsta = get_word_ce000_prefetch(6) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return;
	}
	dsta |= get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 8, pcoffset);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(8);
		exception3_read_access(opcode, dsta, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 dst = x_get_word(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(10);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 10, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_word(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(10);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return;
	}
	m68k_incpci(8);
	return;
}
/* 24 (5/1) */
/* 8 0,0   */

/* ANDSR.W #<data>.W */
void REGPARAM2 op_027c_13_ff(uae_u32 opcode)
{
	OpcodeFamily = 5;
	CurrentInstrCycles = 16; 
	if (!regs.s) {
		Exception(8);
		return;
	}
	MakeSR();
	uae_s16 src = regs.irc;
	do_cycles_ce000_internal(8);
	regs.sr &= src;
	MakeFromSR();
	m68k_incpci(4);
	get_word_ce000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, 0);
		return;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 16 (2/0) */
/* 4 0,0   */

/* AND.L #<data>.L,Dn */
void REGPARAM2 op_0280_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 16; 
	uae_s32 src;
	src = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	src |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		m68k_dreg(regs, dstreg) = (src);
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	do_cycles_ce000_internal(4);
	m68k_dreg(regs, dstreg) = (src);
	m68k_incpci(6);
	return;
}
/* 16 (3/0) */
/* 6 0,0   */

/* AND.L #<data>.L,(An) */
void REGPARAM2 op_0290_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 28; 
	uae_s32 src;
	src = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	src |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	if (dsta & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, dsta, 2, 1);
		return;
	}
	uae_s32 dst = x_get_word(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	dst |= x_get_word(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return;
	}
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	x_put_word(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return;
	}
	x_put_word(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 28 (5/2) */
/* 6 0,0   */

/* AND.L #<data>.L,(An)+ */
void REGPARAM2 op_0298_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 28; 
	uae_s32 src;
	src = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	src |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	if (dsta & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, dsta, 2, 1);
		return;
	}
	uae_s32 dst = x_get_word(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	dst |= x_get_word(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return;
	}
	m68k_areg(regs, dstreg) += 4;
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	x_put_word(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return;
	}
	x_put_word(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 28 (5/2) */
/* 6 0,0   */

/* AND.L #<data>.L,-(An) */
void REGPARAM2 op_02a0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 30; 
	uae_s32 src;
	src = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	src |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - 4;
	do_cycles_ce000_internal(2);
	if (dsta & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, dsta, 2, 1);
		return;
	}
	uae_s32 dst = x_get_word(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	dst |= x_get_word(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		m68k_areg(regs, dstreg) = dsta;
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return;
	}
	m68k_areg(regs, dstreg) = dsta;
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	x_put_word(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return;
	}
	x_put_word(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 30 (5/2) */
/* 6 0,0   */

/* AND.L #<data>.L,(d16,An) */
void REGPARAM2 op_02a8_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 32; 
	uae_s32 src;
	src = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	src |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 8, -2);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, dsta, 2, 1);
		return;
	}
	uae_s32 dst = x_get_word(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	dst |= x_get_word(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return;
	}
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(10);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch_opcode(opcode, 10, pcoffset);
		return;
	}
	x_put_word(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(10);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return;
	}
	x_put_word(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(10);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return;
	}
	m68k_incpci(8);
	return;
}
/* 32 (6/2) */
/* 8 0,0   */

/* AND.L #<data>.L,(d8,An,Xn) */
void REGPARAM2 op_02b0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 34; 
	uae_s32 src;
	src = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	src |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	uaecptr dsta;
	do_cycles_ce000_internal(2);
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_ce000_prefetch(8));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 8, -2);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, dsta, 2, 1);
		return;
	}
	uae_s32 dst = x_get_word(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	dst |= x_get_word(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return;
	}
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(10);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch_opcode(opcode, 10, pcoffset);
		return;
	}
	x_put_word(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(10);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return;
	}
	x_put_word(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(10);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return;
	}
	m68k_incpci(8);
	return;
}
/* 34 (6/2) */
/* 8 4,0   */

/* AND.L #<data>.L,(xxx).W */
void REGPARAM2 op_02b8_13_ff(uae_u32 opcode)
{
	OpcodeFamily = 2;
	CurrentInstrCycles = 32; 
	uae_s32 src;
	src = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	src |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 8, 0);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(8);
		exception3_read_access(opcode, dsta, 2, 1);
		return;
	}
	uae_s32 dst = x_get_word(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	dst |= x_get_word(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return;
	}
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(10);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch_opcode(opcode, 10, pcoffset);
		return;
	}
	x_put_word(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(10);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return;
	}
	x_put_word(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(10);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return;
	}
	m68k_incpci(8);
	return;
}
/* 32 (6/2) */
/* 8 0,0   */

/* AND.L #<data>.L,(xxx).L */
void REGPARAM2 op_02b9_13_ff(uae_u32 opcode)
{
	OpcodeFamily = 2;
	CurrentInstrCycles = 36; 
	uae_s32 src;
	src = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	src |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	uaecptr dsta;
	dsta = get_word_ce000_prefetch(8) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 8, -2);
		return;
	}
	dsta |= get_word_ce000_prefetch(10);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 10, pcoffset);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(10);
		exception3_read_access(opcode, dsta, 2, 1);
		return;
	}
	uae_s32 dst = x_get_word(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(10);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	dst |= x_get_word(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(10);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return;
	}
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(12);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch_opcode(opcode, 12, pcoffset);
		return;
	}
	x_put_word(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(12);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return;
	}
	x_put_word(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(12);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return;
	}
	m68k_incpci(10);
	return;
}
/* 36 (7/2) */
/* 10 0,0   */

/* SUB.B #<data>.B,Dn */
void REGPARAM2 op_0400_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 8;  
	uae_s8 src = (uae_u8)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uae_s8 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 8 (2/0) */
/* 4 0,0   */

/* SUB.B #<data>.B,(An) */
void REGPARAM2 op_0410_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 16; 
	uae_s8 src = (uae_u8)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_byte(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x0, newv, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* SUB.B #<data>.B,(An)+ */
void REGPARAM2 op_0418_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 16; 
	uae_s8 src = (uae_u8)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
	uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_byte(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x0, newv, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* SUB.B #<data>.B,-(An) */
void REGPARAM2 op_0420_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 18; 
	uae_s8 src = (uae_u8)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
	do_cycles_ce000_internal(2);
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, dstreg) = dsta;
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	m68k_areg(regs, dstreg) = dsta;
	uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_byte(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x0, newv, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 18 (3/1) */
/* 4 0,0   */

/* SUB.B #<data>.B,(d16,An) */
void REGPARAM2 op_0428_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 20; 
	uae_s8 src = (uae_u8)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return;
	}
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_byte(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 0, 0x0, newv, 1);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 20 (4/1) */
/* 6 0,0   */

/* SUB.B #<data>.B,(d8,An,Xn) */
void REGPARAM2 op_0430_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 22; 
	uae_s8 src = (uae_u8)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr dsta;
	do_cycles_ce000_internal(2);
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_ce000_prefetch(6));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return;
	}
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_byte(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 0, 0x0, newv, 1);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 22 (4/1) */
/* 6 4,0   */

/* SUB.B #<data>.B,(xxx).W */
void REGPARAM2 op_0438_13_ff(uae_u32 opcode)
{
	OpcodeFamily = 7;
	CurrentInstrCycles = 20; 
	uae_s8 src = (uae_u8)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, 0);
		return;
	}
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_byte(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 0, 0x0, newv, 1);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 20 (4/1) */
/* 6 0,0   */

/* SUB.B #<data>.B,(xxx).L */
void REGPARAM2 op_0439_13_ff(uae_u32 opcode)
{
	OpcodeFamily = 7;
	CurrentInstrCycles = 24; 
	uae_s8 src = (uae_u8)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr dsta;
	dsta = get_word_ce000_prefetch(6) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return;
	}
	dsta |= get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 8, pcoffset);
		return;
	}
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(10);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 10, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_byte(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(10);
		exception2_write(opcode, dsta + 0, 0x0, newv, 1);
		return;
	}
	m68k_incpci(8);
	return;
}
/* 24 (5/1) */
/* 8 0,0   */

/* SUB.W #<data>.W,Dn */
void REGPARAM2 op_0440_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 8;  
	uae_s16 src = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 8 (2/0) */
/* 4 0,0   */

/* SUB.W #<data>.W,(An) */
void REGPARAM2 op_0450_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 16; 
	uae_s16 src = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	if (dsta & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, dsta, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 dst = x_get_word(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_word(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, newv, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* SUB.W #<data>.W,(An)+ */
void REGPARAM2 op_0458_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 16; 
	uae_s16 src = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	if (dsta & 1) {
		m68k_areg(regs, dstreg) += 2 + 0;
		m68k_incpci(4);
		exception3_read_access(opcode, dsta, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 dst = x_get_word(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, dstreg) += 2 + 0;
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	m68k_areg(regs, dstreg) += 2;
	uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_word(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, newv, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* SUB.W #<data>.W,-(An) */
void REGPARAM2 op_0460_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 18; 
	uae_s16 src = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - 2;
	do_cycles_ce000_internal(2);
	if (dsta & 1) {
		m68k_areg(regs, dstreg) = dsta;
		m68k_incpci(4);
		exception3_read_access(opcode, dsta, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 dst = x_get_word(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, dstreg) = dsta;
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	m68k_areg(regs, dstreg) = dsta;
	uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_word(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, newv, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 18 (3/1) */
/* 4 0,0   */

/* SUB.W #<data>.W,(d16,An) */
void REGPARAM2 op_0468_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 20; 
	uae_s16 src = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, dsta, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 dst = x_get_word(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_word(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 0, 0x1, newv, 1);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 20 (4/1) */
/* 6 0,0   */

/* SUB.W #<data>.W,(d8,An,Xn) */
void REGPARAM2 op_0470_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 22; 
	uae_s16 src = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr dsta;
	do_cycles_ce000_internal(2);
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_ce000_prefetch(6));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, dsta, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 dst = x_get_word(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_word(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 0, 0x1, newv, 1);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 22 (4/1) */
/* 6 4,0   */

/* SUB.W #<data>.W,(xxx).W */
void REGPARAM2 op_0478_13_ff(uae_u32 opcode)
{
	OpcodeFamily = 7;
	CurrentInstrCycles = 20; 
	uae_s16 src = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, 0);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, dsta, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 dst = x_get_word(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_word(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 0, 0x1, newv, 1);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 20 (4/1) */
/* 6 0,0   */

/* SUB.W #<data>.W,(xxx).L */
void REGPARAM2 op_0479_13_ff(uae_u32 opcode)
{
	OpcodeFamily = 7;
	CurrentInstrCycles = 24; 
	uae_s16 src = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr dsta;
	dsta = get_word_ce000_prefetch(6) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return;
	}
	dsta |= get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 8, pcoffset);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(8);
		exception3_read_access(opcode, dsta, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 dst = x_get_word(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(10);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 10, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_word(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(10);
		exception2_write(opcode, dsta + 0, 0x1, newv, 1);
		return;
	}
	m68k_incpci(8);
	return;
}
/* 24 (5/1) */
/* 8 0,0   */

/* SUB.L #<data>.L,Dn */
void REGPARAM2 op_0480_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 14; 
	uae_s32 src;
	src = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	ipl_fetch_now();
	src |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		uae_s16 bnewv = (uae_s16)dst - (uae_s16)src;
		int bflgs = ((uae_s16)(src)) < 0;
		int bflgo = ((uae_s16)(dst)) < 0;
		int bflgn = bnewv < 0;
		ccr_68000_long_move_ae_LZN(bnewv);
		SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
		SET_XFLG(GET_CFLG());
		SET_VFLG((bflgs ^ bflgo) & (bflgn ^ bflgo));
		dreg_68000_long_replace_low(dstreg, bnewv);
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	opcode = regs.ir;
	do_cycles_ce000_internal(2);
	m68k_dreg(regs, dstreg) = (newv);
	m68k_incpci(6);
	return;
}
/* 14 (3/0) */
/* 6 0,0   */

/* SUB.L #<data>.L,(An) */
void REGPARAM2 op_0490_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 28; 
	uae_s32 src;
	src = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	src |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	if (dsta & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, dsta, 2, 1);
		return;
	}
	uae_s32 dst = x_get_word(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	dst |= x_get_word(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return;
	}
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		uae_s16 bnewv = (uae_s16)dst - (uae_s16)src;
		int bflgs = ((uae_s16)(src)) < 0;
		int bflgo = ((uae_s16)(dst)) < 0;
		int bflgn = bnewv < 0;
		ccr_68000_long_move_ae_LZN(bnewv);
		SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
		SET_XFLG(GET_CFLG());
		SET_VFLG((bflgs ^ bflgo) & (bflgn ^ bflgo));
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	x_put_word(dsta + 2, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 2, 0x1, newv, 1);
		return;
	}
	x_put_word(dsta, newv >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 0, 0x1, newv >> 16, 1);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 28 (5/2) */
/* 6 0,0   */

/* SUB.L #<data>.L,(An)+ */
void REGPARAM2 op_0498_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 28; 
	uae_s32 src;
	src = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	src |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	if (dsta & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, dsta, 2, 1);
		return;
	}
	uae_s32 dst = x_get_word(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	dst |= x_get_word(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return;
	}
	m68k_areg(regs, dstreg) += 4;
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		uae_s16 bnewv = (uae_s16)dst - (uae_s16)src;
		int bflgs = ((uae_s16)(src)) < 0;
		int bflgo = ((uae_s16)(dst)) < 0;
		int bflgn = bnewv < 0;
		ccr_68000_long_move_ae_LZN(bnewv);
		SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
		SET_XFLG(GET_CFLG());
		SET_VFLG((bflgs ^ bflgo) & (bflgn ^ bflgo));
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	x_put_word(dsta + 2, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 2, 0x1, newv, 1);
		return;
	}
	x_put_word(dsta, newv >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 0, 0x1, newv >> 16, 1);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 28 (5/2) */
/* 6 0,0   */

/* SUB.L #<data>.L,-(An) */
void REGPARAM2 op_04a0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 30; 
	uae_s32 src;
	src = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	src |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - 4;
	do_cycles_ce000_internal(2);
	if (dsta & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, dsta, 2, 1);
		return;
	}
	uae_s32 dst = x_get_word(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	dst |= x_get_word(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		m68k_areg(regs, dstreg) = dsta;
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return;
	}
	m68k_areg(regs, dstreg) = dsta;
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		uae_s16 bnewv = (uae_s16)dst - (uae_s16)src;
		int bflgs = ((uae_s16)(src)) < 0;
		int bflgo = ((uae_s16)(dst)) < 0;
		int bflgn = bnewv < 0;
		ccr_68000_long_move_ae_LZN(bnewv);
		SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
		SET_XFLG(GET_CFLG());
		SET_VFLG((bflgs ^ bflgo) & (bflgn ^ bflgo));
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	x_put_word(dsta + 2, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 2, 0x1, newv, 1);
		return;
	}
	x_put_word(dsta, newv >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 0, 0x1, newv >> 16, 1);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 30 (5/2) */
/* 6 0,0   */

/* SUB.L #<data>.L,(d16,An) */
void REGPARAM2 op_04a8_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 32; 
	uae_s32 src;
	src = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	src |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 8, -2);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, dsta, 2, 1);
		return;
	}
	uae_s32 dst = x_get_word(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	dst |= x_get_word(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return;
	}
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(10);
	if(hardware_bus_error) {
		int pcoffset = 0;
		uae_s16 bnewv = (uae_s16)dst - (uae_s16)src;
		int bflgs = ((uae_s16)(src)) < 0;
		int bflgo = ((uae_s16)(dst)) < 0;
		int bflgn = bnewv < 0;
		ccr_68000_long_move_ae_LZN(bnewv);
		SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
		SET_XFLG(GET_CFLG());
		SET_VFLG((bflgs ^ bflgo) & (bflgn ^ bflgo));
		exception2_fetch_opcode(opcode, 10, pcoffset);
		return;
	}
	x_put_word(dsta + 2, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(10);
		exception2_write(opcode, dsta + 2, 0x1, newv, 1);
		return;
	}
	x_put_word(dsta, newv >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(10);
		exception2_write(opcode, dsta + 0, 0x1, newv >> 16, 1);
		return;
	}
	m68k_incpci(8);
	return;
}
/* 32 (6/2) */
/* 8 0,0   */

/* SUB.L #<data>.L,(d8,An,Xn) */
void REGPARAM2 op_04b0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 34; 
	uae_s32 src;
	src = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	src |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	uaecptr dsta;
	do_cycles_ce000_internal(2);
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_ce000_prefetch(8));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 8, -2);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, dsta, 2, 1);
		return;
	}
	uae_s32 dst = x_get_word(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	dst |= x_get_word(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return;
	}
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(10);
	if(hardware_bus_error) {
		int pcoffset = 0;
		uae_s16 bnewv = (uae_s16)dst - (uae_s16)src;
		int bflgs = ((uae_s16)(src)) < 0;
		int bflgo = ((uae_s16)(dst)) < 0;
		int bflgn = bnewv < 0;
		ccr_68000_long_move_ae_LZN(bnewv);
		SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
		SET_XFLG(GET_CFLG());
		SET_VFLG((bflgs ^ bflgo) & (bflgn ^ bflgo));
		exception2_fetch_opcode(opcode, 10, pcoffset);
		return;
	}
	x_put_word(dsta + 2, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(10);
		exception2_write(opcode, dsta + 2, 0x1, newv, 1);
		return;
	}
	x_put_word(dsta, newv >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(10);
		exception2_write(opcode, dsta + 0, 0x1, newv >> 16, 1);
		return;
	}
	m68k_incpci(8);
	return;
}
/* 34 (6/2) */
/* 8 4,0   */

/* SUB.L #<data>.L,(xxx).W */
void REGPARAM2 op_04b8_13_ff(uae_u32 opcode)
{
	OpcodeFamily = 7;
	CurrentInstrCycles = 32; 
	uae_s32 src;
	src = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	src |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 8, 0);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(8);
		exception3_read_access(opcode, dsta, 2, 1);
		return;
	}
	uae_s32 dst = x_get_word(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	dst |= x_get_word(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return;
	}
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(10);
	if(hardware_bus_error) {
		int pcoffset = 0;
		uae_s16 bnewv = (uae_s16)dst - (uae_s16)src;
		int bflgs = ((uae_s16)(src)) < 0;
		int bflgo = ((uae_s16)(dst)) < 0;
		int bflgn = bnewv < 0;
		ccr_68000_long_move_ae_LZN(bnewv);
		SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
		SET_XFLG(GET_CFLG());
		SET_VFLG((bflgs ^ bflgo) & (bflgn ^ bflgo));
		exception2_fetch_opcode(opcode, 10, pcoffset);
		return;
	}
	x_put_word(dsta + 2, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(10);
		exception2_write(opcode, dsta + 2, 0x1, newv, 1);
		return;
	}
	x_put_word(dsta, newv >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(10);
		exception2_write(opcode, dsta + 0, 0x1, newv >> 16, 1);
		return;
	}
	m68k_incpci(8);
	return;
}
/* 32 (6/2) */
/* 8 0,0   */

/* SUB.L #<data>.L,(xxx).L */
void REGPARAM2 op_04b9_13_ff(uae_u32 opcode)
{
	OpcodeFamily = 7;
	CurrentInstrCycles = 36; 
	uae_s32 src;
	src = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	src |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	uaecptr dsta;
	dsta = get_word_ce000_prefetch(8) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 8, -2);
		return;
	}
	dsta |= get_word_ce000_prefetch(10);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 10, pcoffset);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(10);
		exception3_read_access(opcode, dsta, 2, 1);
		return;
	}
	uae_s32 dst = x_get_word(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(10);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	dst |= x_get_word(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(10);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return;
	}
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(12);
	if(hardware_bus_error) {
		int pcoffset = 0;
		uae_s16 bnewv = (uae_s16)dst - (uae_s16)src;
		int bflgs = ((uae_s16)(src)) < 0;
		int bflgo = ((uae_s16)(dst)) < 0;
		int bflgn = bnewv < 0;
		ccr_68000_long_move_ae_LZN(bnewv);
		SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
		SET_XFLG(GET_CFLG());
		SET_VFLG((bflgs ^ bflgo) & (bflgn ^ bflgo));
		exception2_fetch_opcode(opcode, 12, pcoffset);
		return;
	}
	x_put_word(dsta + 2, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(12);
		exception2_write(opcode, dsta + 2, 0x1, newv, 1);
		return;
	}
	x_put_word(dsta, newv >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(12);
		exception2_write(opcode, dsta + 0, 0x1, newv >> 16, 1);
		return;
	}
	m68k_incpci(10);
	return;
}
/* 36 (7/2) */
/* 10 0,0   */

/* ADD.B #<data>.B,Dn */
void REGPARAM2 op_0600_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 8;  
	uae_s8 src = (uae_u8)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uae_s8 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u8)(~dst)) < ((uae_u8)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 8 (2/0) */
/* 4 0,0   */

/* ADD.B #<data>.B,(An) */
void REGPARAM2 op_0610_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 16; 
	uae_s8 src = (uae_u8)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u8)(~dst)) < ((uae_u8)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_byte(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x0, newv, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* ADD.B #<data>.B,(An)+ */
void REGPARAM2 op_0618_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 16; 
	uae_s8 src = (uae_u8)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
	uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u8)(~dst)) < ((uae_u8)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_byte(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x0, newv, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* ADD.B #<data>.B,-(An) */
void REGPARAM2 op_0620_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 18; 
	uae_s8 src = (uae_u8)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
	do_cycles_ce000_internal(2);
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, dstreg) = dsta;
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	m68k_areg(regs, dstreg) = dsta;
	uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u8)(~dst)) < ((uae_u8)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_byte(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x0, newv, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 18 (3/1) */
/* 4 0,0   */

/* ADD.B #<data>.B,(d16,An) */
void REGPARAM2 op_0628_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 20; 
	uae_s8 src = (uae_u8)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return;
	}
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u8)(~dst)) < ((uae_u8)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_byte(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 0, 0x0, newv, 1);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 20 (4/1) */
/* 6 0,0   */

/* ADD.B #<data>.B,(d8,An,Xn) */
void REGPARAM2 op_0630_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 22; 
	uae_s8 src = (uae_u8)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr dsta;
	do_cycles_ce000_internal(2);
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_ce000_prefetch(6));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return;
	}
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u8)(~dst)) < ((uae_u8)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_byte(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 0, 0x0, newv, 1);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 22 (4/1) */
/* 6 4,0   */

/* ADD.B #<data>.B,(xxx).W */
void REGPARAM2 op_0638_13_ff(uae_u32 opcode)
{
	OpcodeFamily = 11;
	CurrentInstrCycles = 20; 
	uae_s8 src = (uae_u8)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, 0);
		return;
	}
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u8)(~dst)) < ((uae_u8)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_byte(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 0, 0x0, newv, 1);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 20 (4/1) */
/* 6 0,0   */

/* ADD.B #<data>.B,(xxx).L */
void REGPARAM2 op_0639_13_ff(uae_u32 opcode)
{
	OpcodeFamily = 11;
	CurrentInstrCycles = 24; 
	uae_s8 src = (uae_u8)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr dsta;
	dsta = get_word_ce000_prefetch(6) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return;
	}
	dsta |= get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 8, pcoffset);
		return;
	}
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u8)(~dst)) < ((uae_u8)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(10);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 10, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_byte(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(10);
		exception2_write(opcode, dsta + 0, 0x0, newv, 1);
		return;
	}
	m68k_incpci(8);
	return;
}
/* 24 (5/1) */
/* 8 0,0   */

/* ADD.W #<data>.W,Dn */
void REGPARAM2 op_0640_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 8;  
	uae_s16 src = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 8 (2/0) */
/* 4 0,0   */

/* ADD.W #<data>.W,(An) */
void REGPARAM2 op_0650_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 16; 
	uae_s16 src = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	if (dsta & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, dsta, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 dst = x_get_word(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_word(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, newv, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* ADD.W #<data>.W,(An)+ */
void REGPARAM2 op_0658_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 16; 
	uae_s16 src = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	if (dsta & 1) {
		m68k_areg(regs, dstreg) += 2 + 0;
		m68k_incpci(4);
		exception3_read_access(opcode, dsta, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 dst = x_get_word(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, dstreg) += 2 + 0;
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	m68k_areg(regs, dstreg) += 2;
	uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_word(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, newv, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* ADD.W #<data>.W,-(An) */
void REGPARAM2 op_0660_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 18; 
	uae_s16 src = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - 2;
	do_cycles_ce000_internal(2);
	if (dsta & 1) {
		m68k_areg(regs, dstreg) = dsta;
		m68k_incpci(4);
		exception3_read_access(opcode, dsta, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 dst = x_get_word(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, dstreg) = dsta;
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	m68k_areg(regs, dstreg) = dsta;
	uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_word(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, newv, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 18 (3/1) */
/* 4 0,0   */

/* ADD.W #<data>.W,(d16,An) */
void REGPARAM2 op_0668_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 20; 
	uae_s16 src = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, dsta, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 dst = x_get_word(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_word(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 0, 0x1, newv, 1);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 20 (4/1) */
/* 6 0,0   */

/* ADD.W #<data>.W,(d8,An,Xn) */
void REGPARAM2 op_0670_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 22; 
	uae_s16 src = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr dsta;
	do_cycles_ce000_internal(2);
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_ce000_prefetch(6));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, dsta, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 dst = x_get_word(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_word(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 0, 0x1, newv, 1);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 22 (4/1) */
/* 6 4,0   */

/* ADD.W #<data>.W,(xxx).W */
void REGPARAM2 op_0678_13_ff(uae_u32 opcode)
{
	OpcodeFamily = 11;
	CurrentInstrCycles = 20; 
	uae_s16 src = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, 0);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, dsta, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 dst = x_get_word(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_word(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 0, 0x1, newv, 1);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 20 (4/1) */
/* 6 0,0   */

/* ADD.W #<data>.W,(xxx).L */
void REGPARAM2 op_0679_13_ff(uae_u32 opcode)
{
	OpcodeFamily = 11;
	CurrentInstrCycles = 24; 
	uae_s16 src = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr dsta;
	dsta = get_word_ce000_prefetch(6) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return;
	}
	dsta |= get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 8, pcoffset);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(8);
		exception3_read_access(opcode, dsta, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 dst = x_get_word(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(10);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 10, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_word(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(10);
		exception2_write(opcode, dsta + 0, 0x1, newv, 1);
		return;
	}
	m68k_incpci(8);
	return;
}
/* 24 (5/1) */
/* 8 0,0   */

/* ADD.L #<data>.L,Dn */
void REGPARAM2 op_0680_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 14; 
	uae_s32 src;
	src = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	ipl_fetch_now();
	src |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u32)(~dst)) < ((uae_u32)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		uae_s16 bnewv = (uae_s16)dst + (uae_s16)src;
		int bflgs = ((uae_s16)(src)) < 0;
		int bflgo = ((uae_s16)(dst)) < 0;
		int bflgn = bnewv < 0;
		ccr_68000_long_move_ae_LZN(bnewv);
		SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
		SET_XFLG(GET_CFLG());
		SET_VFLG((bflgs ^ bflgn) & (bflgo ^ bflgn));
		dreg_68000_long_replace_low(dstreg, bnewv);
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	opcode = regs.ir;
	do_cycles_ce000_internal(2);
	m68k_dreg(regs, dstreg) = (newv);
	m68k_incpci(6);
	return;
}
/* 14 (3/0) */
/* 6 0,0   */

/* ADD.L #<data>.L,(An) */
void REGPARAM2 op_0690_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 28; 
	uae_s32 src;
	src = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	src |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	if (dsta & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, dsta, 2, 1);
		return;
	}
	uae_s32 dst = x_get_word(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	dst |= x_get_word(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return;
	}
	uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u32)(~dst)) < ((uae_u32)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		uae_s16 bnewv = (uae_s16)dst + (uae_s16)src;
		int bflgs = ((uae_s16)(src)) < 0;
		int bflgo = ((uae_s16)(dst)) < 0;
		int bflgn = bnewv < 0;
		ccr_68000_long_move_ae_LZN(bnewv);
		SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
		SET_XFLG(GET_CFLG());
		SET_VFLG((bflgs ^ bflgn) & (bflgo ^ bflgn));
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	x_put_word(dsta + 2, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 2, 0x1, newv, 1);
		return;
	}
	x_put_word(dsta, newv >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 0, 0x1, newv >> 16, 1);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 28 (5/2) */
/* 6 0,0   */

/* ADD.L #<data>.L,(An)+ */
void REGPARAM2 op_0698_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 28; 
	uae_s32 src;
	src = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	src |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	if (dsta & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, dsta, 2, 1);
		return;
	}
	uae_s32 dst = x_get_word(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	dst |= x_get_word(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return;
	}
	m68k_areg(regs, dstreg) += 4;
	uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u32)(~dst)) < ((uae_u32)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		uae_s16 bnewv = (uae_s16)dst + (uae_s16)src;
		int bflgs = ((uae_s16)(src)) < 0;
		int bflgo = ((uae_s16)(dst)) < 0;
		int bflgn = bnewv < 0;
		ccr_68000_long_move_ae_LZN(bnewv);
		SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
		SET_XFLG(GET_CFLG());
		SET_VFLG((bflgs ^ bflgn) & (bflgo ^ bflgn));
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	x_put_word(dsta + 2, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 2, 0x1, newv, 1);
		return;
	}
	x_put_word(dsta, newv >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 0, 0x1, newv >> 16, 1);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 28 (5/2) */
/* 6 0,0   */

/* ADD.L #<data>.L,-(An) */
void REGPARAM2 op_06a0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 30; 
	uae_s32 src;
	src = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	src |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - 4;
	do_cycles_ce000_internal(2);
	if (dsta & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, dsta, 2, 1);
		return;
	}
	uae_s32 dst = x_get_word(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	dst |= x_get_word(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		m68k_areg(regs, dstreg) = dsta;
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return;
	}
	m68k_areg(regs, dstreg) = dsta;
	uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u32)(~dst)) < ((uae_u32)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		uae_s16 bnewv = (uae_s16)dst + (uae_s16)src;
		int bflgs = ((uae_s16)(src)) < 0;
		int bflgo = ((uae_s16)(dst)) < 0;
		int bflgn = bnewv < 0;
		ccr_68000_long_move_ae_LZN(bnewv);
		SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
		SET_XFLG(GET_CFLG());
		SET_VFLG((bflgs ^ bflgn) & (bflgo ^ bflgn));
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	x_put_word(dsta + 2, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 2, 0x1, newv, 1);
		return;
	}
	x_put_word(dsta, newv >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 0, 0x1, newv >> 16, 1);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 30 (5/2) */
/* 6 0,0   */

/* ADD.L #<data>.L,(d16,An) */
void REGPARAM2 op_06a8_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 32; 
	uae_s32 src;
	src = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	src |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 8, -2);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, dsta, 2, 1);
		return;
	}
	uae_s32 dst = x_get_word(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	dst |= x_get_word(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return;
	}
	uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u32)(~dst)) < ((uae_u32)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(10);
	if(hardware_bus_error) {
		int pcoffset = 0;
		uae_s16 bnewv = (uae_s16)dst + (uae_s16)src;
		int bflgs = ((uae_s16)(src)) < 0;
		int bflgo = ((uae_s16)(dst)) < 0;
		int bflgn = bnewv < 0;
		ccr_68000_long_move_ae_LZN(bnewv);
		SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
		SET_XFLG(GET_CFLG());
		SET_VFLG((bflgs ^ bflgn) & (bflgo ^ bflgn));
		exception2_fetch_opcode(opcode, 10, pcoffset);
		return;
	}
	x_put_word(dsta + 2, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(10);
		exception2_write(opcode, dsta + 2, 0x1, newv, 1);
		return;
	}
	x_put_word(dsta, newv >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(10);
		exception2_write(opcode, dsta + 0, 0x1, newv >> 16, 1);
		return;
	}
	m68k_incpci(8);
	return;
}
/* 32 (6/2) */
/* 8 0,0   */

/* ADD.L #<data>.L,(d8,An,Xn) */
void REGPARAM2 op_06b0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 34; 
	uae_s32 src;
	src = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	src |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	uaecptr dsta;
	do_cycles_ce000_internal(2);
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_ce000_prefetch(8));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 8, -2);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, dsta, 2, 1);
		return;
	}
	uae_s32 dst = x_get_word(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	dst |= x_get_word(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return;
	}
	uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u32)(~dst)) < ((uae_u32)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(10);
	if(hardware_bus_error) {
		int pcoffset = 0;
		uae_s16 bnewv = (uae_s16)dst + (uae_s16)src;
		int bflgs = ((uae_s16)(src)) < 0;
		int bflgo = ((uae_s16)(dst)) < 0;
		int bflgn = bnewv < 0;
		ccr_68000_long_move_ae_LZN(bnewv);
		SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
		SET_XFLG(GET_CFLG());
		SET_VFLG((bflgs ^ bflgn) & (bflgo ^ bflgn));
		exception2_fetch_opcode(opcode, 10, pcoffset);
		return;
	}
	x_put_word(dsta + 2, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(10);
		exception2_write(opcode, dsta + 2, 0x1, newv, 1);
		return;
	}
	x_put_word(dsta, newv >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(10);
		exception2_write(opcode, dsta + 0, 0x1, newv >> 16, 1);
		return;
	}
	m68k_incpci(8);
	return;
}
/* 34 (6/2) */
/* 8 4,0   */

/* ADD.L #<data>.L,(xxx).W */
void REGPARAM2 op_06b8_13_ff(uae_u32 opcode)
{
	OpcodeFamily = 11;
	CurrentInstrCycles = 32; 
	uae_s32 src;
	src = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	src |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 8, 0);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(8);
		exception3_read_access(opcode, dsta, 2, 1);
		return;
	}
	uae_s32 dst = x_get_word(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	dst |= x_get_word(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return;
	}
	uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u32)(~dst)) < ((uae_u32)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(10);
	if(hardware_bus_error) {
		int pcoffset = 0;
		uae_s16 bnewv = (uae_s16)dst + (uae_s16)src;
		int bflgs = ((uae_s16)(src)) < 0;
		int bflgo = ((uae_s16)(dst)) < 0;
		int bflgn = bnewv < 0;
		ccr_68000_long_move_ae_LZN(bnewv);
		SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
		SET_XFLG(GET_CFLG());
		SET_VFLG((bflgs ^ bflgn) & (bflgo ^ bflgn));
		exception2_fetch_opcode(opcode, 10, pcoffset);
		return;
	}
	x_put_word(dsta + 2, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(10);
		exception2_write(opcode, dsta + 2, 0x1, newv, 1);
		return;
	}
	x_put_word(dsta, newv >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(10);
		exception2_write(opcode, dsta + 0, 0x1, newv >> 16, 1);
		return;
	}
	m68k_incpci(8);
	return;
}
/* 32 (6/2) */
/* 8 0,0   */

/* ADD.L #<data>.L,(xxx).L */
void REGPARAM2 op_06b9_13_ff(uae_u32 opcode)
{
	OpcodeFamily = 11;
	CurrentInstrCycles = 36; 
	uae_s32 src;
	src = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	src |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	uaecptr dsta;
	dsta = get_word_ce000_prefetch(8) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 8, -2);
		return;
	}
	dsta |= get_word_ce000_prefetch(10);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 10, pcoffset);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(10);
		exception3_read_access(opcode, dsta, 2, 1);
		return;
	}
	uae_s32 dst = x_get_word(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(10);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	dst |= x_get_word(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(10);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return;
	}
	uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u32)(~dst)) < ((uae_u32)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(12);
	if(hardware_bus_error) {
		int pcoffset = 0;
		uae_s16 bnewv = (uae_s16)dst + (uae_s16)src;
		int bflgs = ((uae_s16)(src)) < 0;
		int bflgo = ((uae_s16)(dst)) < 0;
		int bflgn = bnewv < 0;
		ccr_68000_long_move_ae_LZN(bnewv);
		SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
		SET_XFLG(GET_CFLG());
		SET_VFLG((bflgs ^ bflgn) & (bflgo ^ bflgn));
		exception2_fetch_opcode(opcode, 12, pcoffset);
		return;
	}
	x_put_word(dsta + 2, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(12);
		exception2_write(opcode, dsta + 2, 0x1, newv, 1);
		return;
	}
	x_put_word(dsta, newv >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(12);
		exception2_write(opcode, dsta + 0, 0x1, newv >> 16, 1);
		return;
	}
	m68k_incpci(10);
	return;
}
/* 36 (7/2) */
/* 10 0,0   */

/* BTST.L #<data>.W,Dn */
void REGPARAM2 op_0800_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 21;
	CurrentInstrCycles = 10; 
	ipl_fetch_now();
	uae_s16 src = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	src &= 31;
	do_cycles_ce000_internal(2);
	SET_ZFLG(1 ^ ((dst >> src) & 1));
	m68k_incpci(4);
	return;
}
/* 10 (2/0) */
/* 4 0,0   */

/* BTST.B #<data>.W,(An) */
void REGPARAM2 op_0810_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 21;
	CurrentInstrCycles = 12; 
	uae_s16 src = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	src &= 7;
	SET_ZFLG(1 ^ ((dst >> src) & 1));
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 12 (3/0) */
/* 4 0,0   */

/* BTST.B #<data>.W,(An)+ */
void REGPARAM2 op_0818_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 21;
	CurrentInstrCycles = 12; 
	uae_s16 src = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
	src &= 7;
	SET_ZFLG(1 ^ ((dst >> src) & 1));
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 12 (3/0) */
/* 4 0,0   */

/* BTST.B #<data>.W,-(An) */
void REGPARAM2 op_0820_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 21;
	CurrentInstrCycles = 14; 
	uae_s16 src = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
	do_cycles_ce000_internal(2);
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, dstreg) = dsta;
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	m68k_areg(regs, dstreg) = dsta;
	src &= 7;
	SET_ZFLG(1 ^ ((dst >> src) & 1));
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 14 (3/0) */
/* 4 0,0   */

/* BTST.B #<data>.W,(d16,An) */
void REGPARAM2 op_0828_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 21;
	CurrentInstrCycles = 16; 
	uae_s16 src = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return;
	}
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	src &= 7;
	SET_ZFLG(1 ^ ((dst >> src) & 1));
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 16 (4/0) */
/* 6 0,0   */

/* BTST.B #<data>.W,(d8,An,Xn) */
void REGPARAM2 op_0830_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 21;
	CurrentInstrCycles = 18; 
	uae_s16 src = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr dsta;
	do_cycles_ce000_internal(2);
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_ce000_prefetch(6));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return;
	}
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	src &= 7;
	SET_ZFLG(1 ^ ((dst >> src) & 1));
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 18 (4/0) */
/* 6 4,0   */

/* BTST.B #<data>.W,(xxx).W */
void REGPARAM2 op_0838_13_ff(uae_u32 opcode)
{
	OpcodeFamily = 21;
	CurrentInstrCycles = 16; 
	uae_s16 src = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, 0);
		return;
	}
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	src &= 7;
	SET_ZFLG(1 ^ ((dst >> src) & 1));
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 16 (4/0) */
/* 6 0,0   */

/* BTST.B #<data>.W,(xxx).L */
void REGPARAM2 op_0839_13_ff(uae_u32 opcode)
{
	OpcodeFamily = 21;
	CurrentInstrCycles = 20; 
	uae_s16 src = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr dsta;
	dsta = get_word_ce000_prefetch(6) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return;
	}
	dsta |= get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 8, pcoffset);
		return;
	}
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	src &= 7;
	SET_ZFLG(1 ^ ((dst >> src) & 1));
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(10);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 10, pcoffset);
		return;
	}
	m68k_incpci(8);
	return;
}
/* 20 (5/0) */
/* 8 0,0   */

/* BTST.B #<data>.W,(d16,PC) */
void REGPARAM2 op_083a_13_ff(uae_u32 opcode)
{
	uae_u32 dstreg = 2;
	OpcodeFamily = 21;
	CurrentInstrCycles = 16; 
	uae_s16 src = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr dsta;
	dsta = m68k_getpci() + 4;
	dsta += (uae_s32)(uae_s16)get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return;
	}
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x0, 2);
		return;
	}
	src &= 7;
	SET_ZFLG(1 ^ ((dst >> src) & 1));
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 16 (4/0) */
/* 6 0,0   */

/* BTST.B #<data>.W,(d8,PC,Xn) */
void REGPARAM2 op_083b_13_ff(uae_u32 opcode)
{
	uae_u32 dstreg = 3;
	OpcodeFamily = 21;
	CurrentInstrCycles = 18; 
	uae_s16 src = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr dsta;
	uaecptr tmppc = m68k_getpci() + 4;
	do_cycles_ce000_internal(2);
	dsta = get_disp_ea_000(tmppc, get_word_ce000_prefetch(6));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return;
	}
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x0, 2);
		return;
	}
	src &= 7;
	SET_ZFLG(1 ^ ((dst >> src) & 1));
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 18 (4/0) */
/* 6 4,0   */

/* BCHG.L #<data>.W,Dn */
void REGPARAM2 op_0840_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 22;
	CurrentInstrCycles = 10; 
	uae_s16 src = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	src &= 31;
	do_cycles_ce000_internal(2);
	if (src > 15) do_cycles_ce000_internal(2);
	dst ^= (1 << src);
	SET_ZFLG(((uae_u32)dst & (1 << src)) >> src);
	m68k_dreg(regs, dstreg) = (dst);
	m68k_incpci(4);
	return;
}
/* 10 (2/0) */
/* 4 0,0   */

/* BCHG.B #<data>.W,(An) */
void REGPARAM2 op_0850_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 22;
	CurrentInstrCycles = 16; 
	uae_s16 src = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	src &= 7;
	dst ^= (1 << src);
	SET_ZFLG(((uae_u32)dst & (1 << src)) >> src);
	x_put_byte(dsta, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x0, dst, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* BCHG.B #<data>.W,(An)+ */
void REGPARAM2 op_0858_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 22;
	CurrentInstrCycles = 16; 
	uae_s16 src = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	src &= 7;
	dst ^= (1 << src);
	SET_ZFLG(((uae_u32)dst & (1 << src)) >> src);
	x_put_byte(dsta, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x0, dst, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* BCHG.B #<data>.W,-(An) */
void REGPARAM2 op_0860_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 22;
	CurrentInstrCycles = 18; 
	uae_s16 src = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
	do_cycles_ce000_internal(2);
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, dstreg) = dsta;
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	m68k_areg(regs, dstreg) = dsta;
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	src &= 7;
	dst ^= (1 << src);
	SET_ZFLG(((uae_u32)dst & (1 << src)) >> src);
	x_put_byte(dsta, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x0, dst, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 18 (3/1) */
/* 4 0,0   */

/* BCHG.B #<data>.W,(d16,An) */
void REGPARAM2 op_0868_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 22;
	CurrentInstrCycles = 20; 
	uae_s16 src = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return;
	}
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	regs.ir = regs.irc;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	opcode = regs.ir;
	src &= 7;
	dst ^= (1 << src);
	SET_ZFLG(((uae_u32)dst & (1 << src)) >> src);
	x_put_byte(dsta, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 0, 0x0, dst, 1);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 20 (4/1) */
/* 6 0,0   */

/* BCHG.B #<data>.W,(d8,An,Xn) */
void REGPARAM2 op_0870_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 22;
	CurrentInstrCycles = 22; 
	uae_s16 src = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr dsta;
	do_cycles_ce000_internal(2);
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_ce000_prefetch(6));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return;
	}
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	regs.ir = regs.irc;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	opcode = regs.ir;
	src &= 7;
	dst ^= (1 << src);
	SET_ZFLG(((uae_u32)dst & (1 << src)) >> src);
	x_put_byte(dsta, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 0, 0x0, dst, 1);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 22 (4/1) */
/* 6 4,0   */

/* BCHG.B #<data>.W,(xxx).W */
void REGPARAM2 op_0878_13_ff(uae_u32 opcode)
{
	OpcodeFamily = 22;
	CurrentInstrCycles = 20; 
	uae_s16 src = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, 0);
		return;
	}
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	regs.ir = regs.irc;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	opcode = regs.ir;
	src &= 7;
	dst ^= (1 << src);
	SET_ZFLG(((uae_u32)dst & (1 << src)) >> src);
	x_put_byte(dsta, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 0, 0x0, dst, 1);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 20 (4/1) */
/* 6 0,0   */

/* BCHG.B #<data>.W,(xxx).L */
void REGPARAM2 op_0879_13_ff(uae_u32 opcode)
{
	OpcodeFamily = 22;
	CurrentInstrCycles = 24; 
	uae_s16 src = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr dsta;
	dsta = get_word_ce000_prefetch(6) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return;
	}
	dsta |= get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 8, pcoffset);
		return;
	}
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	regs.ir = regs.irc;
	get_word_ce000_prefetch(10);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 10, pcoffset);
		return;
	}
	opcode = regs.ir;
	src &= 7;
	dst ^= (1 << src);
	SET_ZFLG(((uae_u32)dst & (1 << src)) >> src);
	x_put_byte(dsta, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(10);
		exception2_write(opcode, dsta + 0, 0x0, dst, 1);
		return;
	}
	m68k_incpci(8);
	return;
}
/* 24 (5/1) */
/* 8 0,0   */

/* BCLR.L #<data>.W,Dn */
void REGPARAM2 op_0880_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 23;
	CurrentInstrCycles = 12; 
	uae_s16 src = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	src &= 31;
	do_cycles_ce000_internal(2);
	if (src > 15) do_cycles_ce000_internal(2);
	do_cycles_ce000_internal(2);
	SET_ZFLG(1 ^ ((dst >> src) & 1));
	dst &= ~(1 << src);
	m68k_dreg(regs, dstreg) = (dst);
	m68k_incpci(4);
	return;
}
/* 12 (2/0) */
/* 4 0,0   */

/* BCLR.B #<data>.W,(An) */
void REGPARAM2 op_0890_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 23;
	CurrentInstrCycles = 18; 
	uae_s16 src = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	src &= 7;
	do_cycles_ce000_internal(2);
	SET_ZFLG(1 ^ ((dst >> src) & 1));
	dst &= ~(1 << src);
	x_put_byte(dsta, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x0, dst, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 18 (3/1) */
/* 4 0,0   */

/* BCLR.B #<data>.W,(An)+ */
void REGPARAM2 op_0898_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 23;
	CurrentInstrCycles = 18; 
	uae_s16 src = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	src &= 7;
	do_cycles_ce000_internal(2);
	SET_ZFLG(1 ^ ((dst >> src) & 1));
	dst &= ~(1 << src);
	x_put_byte(dsta, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x0, dst, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 18 (3/1) */
/* 4 0,0   */

/* BCLR.B #<data>.W,-(An) */
void REGPARAM2 op_08a0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 23;
	CurrentInstrCycles = 20; 
	uae_s16 src = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
	do_cycles_ce000_internal(2);
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, dstreg) = dsta;
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	m68k_areg(regs, dstreg) = dsta;
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	src &= 7;
	do_cycles_ce000_internal(2);
	SET_ZFLG(1 ^ ((dst >> src) & 1));
	dst &= ~(1 << src);
	x_put_byte(dsta, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x0, dst, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 20 (3/1) */
/* 4 0,0   */

/* BCLR.B #<data>.W,(d16,An) */
void REGPARAM2 op_08a8_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 23;
	CurrentInstrCycles = 22; 
	uae_s16 src = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return;
	}
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	regs.ir = regs.irc;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	opcode = regs.ir;
	src &= 7;
	do_cycles_ce000_internal(2);
	SET_ZFLG(1 ^ ((dst >> src) & 1));
	dst &= ~(1 << src);
	x_put_byte(dsta, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 0, 0x0, dst, 1);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 22 (4/1) */
/* 6 0,0   */

/* BCLR.B #<data>.W,(d8,An,Xn) */
void REGPARAM2 op_08b0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 23;
	CurrentInstrCycles = 24; 
	uae_s16 src = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr dsta;
	do_cycles_ce000_internal(2);
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_ce000_prefetch(6));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return;
	}
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	regs.ir = regs.irc;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	opcode = regs.ir;
	src &= 7;
	do_cycles_ce000_internal(2);
	SET_ZFLG(1 ^ ((dst >> src) & 1));
	dst &= ~(1 << src);
	x_put_byte(dsta, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 0, 0x0, dst, 1);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 24 (4/1) */
/* 6 4,0   */

/* BCLR.B #<data>.W,(xxx).W */
void REGPARAM2 op_08b8_13_ff(uae_u32 opcode)
{
	OpcodeFamily = 23;
	CurrentInstrCycles = 22; 
	uae_s16 src = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, 0);
		return;
	}
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	regs.ir = regs.irc;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	opcode = regs.ir;
	src &= 7;
	do_cycles_ce000_internal(2);
	SET_ZFLG(1 ^ ((dst >> src) & 1));
	dst &= ~(1 << src);
	x_put_byte(dsta, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 0, 0x0, dst, 1);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 22 (4/1) */
/* 6 0,0   */

/* BCLR.B #<data>.W,(xxx).L */
void REGPARAM2 op_08b9_13_ff(uae_u32 opcode)
{
	OpcodeFamily = 23;
	CurrentInstrCycles = 26; 
	uae_s16 src = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr dsta;
	dsta = get_word_ce000_prefetch(6) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return;
	}
	dsta |= get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 8, pcoffset);
		return;
	}
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	regs.ir = regs.irc;
	get_word_ce000_prefetch(10);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 10, pcoffset);
		return;
	}
	opcode = regs.ir;
	src &= 7;
	do_cycles_ce000_internal(2);
	SET_ZFLG(1 ^ ((dst >> src) & 1));
	dst &= ~(1 << src);
	x_put_byte(dsta, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(10);
		exception2_write(opcode, dsta + 0, 0x0, dst, 1);
		return;
	}
	m68k_incpci(8);
	return;
}
/* 26 (5/1) */
/* 8 0,0   */

/* BSET.L #<data>.W,Dn */
void REGPARAM2 op_08c0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 24;
	CurrentInstrCycles = 10; 
	uae_s16 src = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	src &= 31;
	do_cycles_ce000_internal(2);
	if (src > 15) do_cycles_ce000_internal(2);
	SET_ZFLG(1 ^ ((dst >> src) & 1));
	dst |= (1 << src);
	m68k_dreg(regs, dstreg) = (dst);
	m68k_incpci(4);
	return;
}
/* 10 (2/0) */
/* 4 0,0   */

/* BSET.B #<data>.W,(An) */
void REGPARAM2 op_08d0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 24;
	CurrentInstrCycles = 16; 
	uae_s16 src = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	src &= 7;
	SET_ZFLG(1 ^ ((dst >> src) & 1));
	dst |= (1 << src);
	x_put_byte(dsta, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x0, dst, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* BSET.B #<data>.W,(An)+ */
void REGPARAM2 op_08d8_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 24;
	CurrentInstrCycles = 16; 
	uae_s16 src = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	src &= 7;
	SET_ZFLG(1 ^ ((dst >> src) & 1));
	dst |= (1 << src);
	x_put_byte(dsta, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x0, dst, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* BSET.B #<data>.W,-(An) */
void REGPARAM2 op_08e0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 24;
	CurrentInstrCycles = 18; 
	uae_s16 src = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
	do_cycles_ce000_internal(2);
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, dstreg) = dsta;
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	m68k_areg(regs, dstreg) = dsta;
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	src &= 7;
	SET_ZFLG(1 ^ ((dst >> src) & 1));
	dst |= (1 << src);
	x_put_byte(dsta, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x0, dst, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 18 (3/1) */
/* 4 0,0   */

/* BSET.B #<data>.W,(d16,An) */
void REGPARAM2 op_08e8_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 24;
	CurrentInstrCycles = 20; 
	uae_s16 src = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return;
	}
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	regs.ir = regs.irc;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	opcode = regs.ir;
	src &= 7;
	SET_ZFLG(1 ^ ((dst >> src) & 1));
	dst |= (1 << src);
	x_put_byte(dsta, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 0, 0x0, dst, 1);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 20 (4/1) */
/* 6 0,0   */

/* BSET.B #<data>.W,(d8,An,Xn) */
void REGPARAM2 op_08f0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 24;
	CurrentInstrCycles = 22; 
	uae_s16 src = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr dsta;
	do_cycles_ce000_internal(2);
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_ce000_prefetch(6));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return;
	}
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	regs.ir = regs.irc;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	opcode = regs.ir;
	src &= 7;
	SET_ZFLG(1 ^ ((dst >> src) & 1));
	dst |= (1 << src);
	x_put_byte(dsta, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 0, 0x0, dst, 1);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 22 (4/1) */
/* 6 4,0   */

/* BSET.B #<data>.W,(xxx).W */
void REGPARAM2 op_08f8_13_ff(uae_u32 opcode)
{
	OpcodeFamily = 24;
	CurrentInstrCycles = 20; 
	uae_s16 src = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, 0);
		return;
	}
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	regs.ir = regs.irc;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	opcode = regs.ir;
	src &= 7;
	SET_ZFLG(1 ^ ((dst >> src) & 1));
	dst |= (1 << src);
	x_put_byte(dsta, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 0, 0x0, dst, 1);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 20 (4/1) */
/* 6 0,0   */

/* BSET.B #<data>.W,(xxx).L */
void REGPARAM2 op_08f9_13_ff(uae_u32 opcode)
{
	OpcodeFamily = 24;
	CurrentInstrCycles = 24; 
	uae_s16 src = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr dsta;
	dsta = get_word_ce000_prefetch(6) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return;
	}
	dsta |= get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 8, pcoffset);
		return;
	}
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	regs.ir = regs.irc;
	get_word_ce000_prefetch(10);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 10, pcoffset);
		return;
	}
	opcode = regs.ir;
	src &= 7;
	SET_ZFLG(1 ^ ((dst >> src) & 1));
	dst |= (1 << src);
	x_put_byte(dsta, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(10);
		exception2_write(opcode, dsta + 0, 0x0, dst, 1);
		return;
	}
	m68k_incpci(8);
	return;
}
/* 24 (5/1) */
/* 8 0,0   */

/* EOR.B #<data>.B,Dn */
void REGPARAM2 op_0a00_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 3;
	CurrentInstrCycles = 8;  
	uae_s8 src = (uae_u8)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uae_s8 dst = m68k_dreg(regs, dstreg);
	src ^= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 8 (2/0) */
/* 4 0,0   */

/* EOR.B #<data>.B,(An) */
void REGPARAM2 op_0a10_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 3;
	CurrentInstrCycles = 16; 
	uae_s8 src = (uae_u8)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	src ^= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_byte(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* EOR.B #<data>.B,(An)+ */
void REGPARAM2 op_0a18_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 3;
	CurrentInstrCycles = 16; 
	uae_s8 src = (uae_u8)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
	src ^= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_byte(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* EOR.B #<data>.B,-(An) */
void REGPARAM2 op_0a20_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 3;
	CurrentInstrCycles = 18; 
	uae_s8 src = (uae_u8)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
	do_cycles_ce000_internal(2);
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, dstreg) = dsta;
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	m68k_areg(regs, dstreg) = dsta;
	src ^= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_byte(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 18 (3/1) */
/* 4 0,0   */

/* EOR.B #<data>.B,(d16,An) */
void REGPARAM2 op_0a28_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 3;
	CurrentInstrCycles = 20; 
	uae_s8 src = (uae_u8)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return;
	}
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	src ^= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_byte(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 20 (4/1) */
/* 6 0,0   */

/* EOR.B #<data>.B,(d8,An,Xn) */
void REGPARAM2 op_0a30_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 3;
	CurrentInstrCycles = 22; 
	uae_s8 src = (uae_u8)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr dsta;
	do_cycles_ce000_internal(2);
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_ce000_prefetch(6));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return;
	}
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	src ^= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_byte(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 22 (4/1) */
/* 6 4,0   */

/* EOR.B #<data>.B,(xxx).W */
void REGPARAM2 op_0a38_13_ff(uae_u32 opcode)
{
	OpcodeFamily = 3;
	CurrentInstrCycles = 20; 
	uae_s8 src = (uae_u8)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, 0);
		return;
	}
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	src ^= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_byte(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 20 (4/1) */
/* 6 0,0   */

/* EOR.B #<data>.B,(xxx).L */
void REGPARAM2 op_0a39_13_ff(uae_u32 opcode)
{
	OpcodeFamily = 3;
	CurrentInstrCycles = 24; 
	uae_s8 src = (uae_u8)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr dsta;
	dsta = get_word_ce000_prefetch(6) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return;
	}
	dsta |= get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 8, pcoffset);
		return;
	}
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	src ^= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(10);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 10, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_byte(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(10);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return;
	}
	m68k_incpci(8);
	return;
}
/* 24 (5/1) */
/* 8 0,0   */

/* EORSR.B #<data>.W */
void REGPARAM2 op_0a3c_13_ff(uae_u32 opcode)
{
	OpcodeFamily = 6;
	CurrentInstrCycles = 16; 
	MakeSR();
	uae_s16 src = regs.irc;
	src &= 0xFF;
	do_cycles_ce000_internal(8);
	regs.sr ^= src;
	MakeFromSR();
	m68k_incpci(4);
	get_word_ce000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, 0);
		return;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 16 (2/0) */
/* 4 0,0   */

/* EOR.W #<data>.W,Dn */
void REGPARAM2 op_0a40_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 3;
	CurrentInstrCycles = 8;  
	uae_s16 src = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	src ^= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 8 (2/0) */
/* 4 0,0   */

/* EOR.W #<data>.W,(An) */
void REGPARAM2 op_0a50_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 3;
	CurrentInstrCycles = 16; 
	uae_s16 src = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	if (dsta & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, dsta, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 dst = x_get_word(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	src ^= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_word(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* EOR.W #<data>.W,(An)+ */
void REGPARAM2 op_0a58_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 3;
	CurrentInstrCycles = 16; 
	uae_s16 src = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	if (dsta & 1) {
		m68k_areg(regs, dstreg) += 2 + 0;
		m68k_incpci(4);
		exception3_read_access(opcode, dsta, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 dst = x_get_word(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, dstreg) += 2 + 0;
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	m68k_areg(regs, dstreg) += 2;
	src ^= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_word(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* EOR.W #<data>.W,-(An) */
void REGPARAM2 op_0a60_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 3;
	CurrentInstrCycles = 18; 
	uae_s16 src = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - 2;
	do_cycles_ce000_internal(2);
	if (dsta & 1) {
		m68k_areg(regs, dstreg) = dsta;
		m68k_incpci(4);
		exception3_read_access(opcode, dsta, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 dst = x_get_word(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, dstreg) = dsta;
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	m68k_areg(regs, dstreg) = dsta;
	src ^= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_word(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 18 (3/1) */
/* 4 0,0   */

/* EOR.W #<data>.W,(d16,An) */
void REGPARAM2 op_0a68_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 3;
	CurrentInstrCycles = 20; 
	uae_s16 src = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, dsta, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 dst = x_get_word(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	src ^= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_word(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 20 (4/1) */
/* 6 0,0   */

/* EOR.W #<data>.W,(d8,An,Xn) */
void REGPARAM2 op_0a70_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 3;
	CurrentInstrCycles = 22; 
	uae_s16 src = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr dsta;
	do_cycles_ce000_internal(2);
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_ce000_prefetch(6));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, dsta, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 dst = x_get_word(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	src ^= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_word(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 22 (4/1) */
/* 6 4,0   */

/* EOR.W #<data>.W,(xxx).W */
void REGPARAM2 op_0a78_13_ff(uae_u32 opcode)
{
	OpcodeFamily = 3;
	CurrentInstrCycles = 20; 
	uae_s16 src = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, 0);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, dsta, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 dst = x_get_word(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	src ^= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_word(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 20 (4/1) */
/* 6 0,0   */

/* EOR.W #<data>.W,(xxx).L */
void REGPARAM2 op_0a79_13_ff(uae_u32 opcode)
{
	OpcodeFamily = 3;
	CurrentInstrCycles = 24; 
	uae_s16 src = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr dsta;
	dsta = get_word_ce000_prefetch(6) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return;
	}
	dsta |= get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 8, pcoffset);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(8);
		exception3_read_access(opcode, dsta, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 dst = x_get_word(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	src ^= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(10);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 10, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_word(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(10);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return;
	}
	m68k_incpci(8);
	return;
}
/* 24 (5/1) */
/* 8 0,0   */

/* EORSR.W #<data>.W */
void REGPARAM2 op_0a7c_13_ff(uae_u32 opcode)
{
	OpcodeFamily = 6;
	CurrentInstrCycles = 16; 
	if (!regs.s) {
		Exception(8);
		return;
	}
	MakeSR();
	uae_s16 src = regs.irc;
	do_cycles_ce000_internal(8);
	regs.sr ^= src;
	MakeFromSR();
	m68k_incpci(4);
	get_word_ce000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, 0);
		return;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 16 (2/0) */
/* 4 0,0   */

/* EOR.L #<data>.L,Dn */
void REGPARAM2 op_0a80_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 3;
	CurrentInstrCycles = 16; 
	uae_s32 src;
	src = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	src |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	src ^= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		m68k_dreg(regs, dstreg) = (src);
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	do_cycles_ce000_internal(4);
	m68k_dreg(regs, dstreg) = (src);
	m68k_incpci(6);
	return;
}
/* 16 (3/0) */
/* 6 0,0   */

/* EOR.L #<data>.L,(An) */
void REGPARAM2 op_0a90_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 3;
	CurrentInstrCycles = 28; 
	uae_s32 src;
	src = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	src |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	if (dsta & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, dsta, 2, 1);
		return;
	}
	uae_s32 dst = x_get_word(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	dst |= x_get_word(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return;
	}
	src ^= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	x_put_word(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return;
	}
	x_put_word(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 28 (5/2) */
/* 6 0,0   */

/* EOR.L #<data>.L,(An)+ */
void REGPARAM2 op_0a98_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 3;
	CurrentInstrCycles = 28; 
	uae_s32 src;
	src = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	src |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	if (dsta & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, dsta, 2, 1);
		return;
	}
	uae_s32 dst = x_get_word(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	dst |= x_get_word(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return;
	}
	m68k_areg(regs, dstreg) += 4;
	src ^= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	x_put_word(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return;
	}
	x_put_word(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 28 (5/2) */
/* 6 0,0   */

/* EOR.L #<data>.L,-(An) */
void REGPARAM2 op_0aa0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 3;
	CurrentInstrCycles = 30; 
	uae_s32 src;
	src = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	src |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - 4;
	do_cycles_ce000_internal(2);
	if (dsta & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, dsta, 2, 1);
		return;
	}
	uae_s32 dst = x_get_word(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	dst |= x_get_word(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		m68k_areg(regs, dstreg) = dsta;
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return;
	}
	m68k_areg(regs, dstreg) = dsta;
	src ^= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	x_put_word(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return;
	}
	x_put_word(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 30 (5/2) */
/* 6 0,0   */

/* EOR.L #<data>.L,(d16,An) */
void REGPARAM2 op_0aa8_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 3;
	CurrentInstrCycles = 32; 
	uae_s32 src;
	src = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	src |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 8, -2);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, dsta, 2, 1);
		return;
	}
	uae_s32 dst = x_get_word(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	dst |= x_get_word(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return;
	}
	src ^= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(10);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch_opcode(opcode, 10, pcoffset);
		return;
	}
	x_put_word(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(10);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return;
	}
	x_put_word(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(10);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return;
	}
	m68k_incpci(8);
	return;
}
/* 32 (6/2) */
/* 8 0,0   */

/* EOR.L #<data>.L,(d8,An,Xn) */
void REGPARAM2 op_0ab0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 3;
	CurrentInstrCycles = 34; 
	uae_s32 src;
	src = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	src |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	uaecptr dsta;
	do_cycles_ce000_internal(2);
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_ce000_prefetch(8));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 8, -2);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, dsta, 2, 1);
		return;
	}
	uae_s32 dst = x_get_word(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	dst |= x_get_word(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return;
	}
	src ^= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(10);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch_opcode(opcode, 10, pcoffset);
		return;
	}
	x_put_word(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(10);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return;
	}
	x_put_word(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(10);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return;
	}
	m68k_incpci(8);
	return;
}
/* 34 (6/2) */
/* 8 4,0   */

/* EOR.L #<data>.L,(xxx).W */
void REGPARAM2 op_0ab8_13_ff(uae_u32 opcode)
{
	OpcodeFamily = 3;
	CurrentInstrCycles = 32; 
	uae_s32 src;
	src = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	src |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 8, 0);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(8);
		exception3_read_access(opcode, dsta, 2, 1);
		return;
	}
	uae_s32 dst = x_get_word(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	dst |= x_get_word(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return;
	}
	src ^= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(10);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch_opcode(opcode, 10, pcoffset);
		return;
	}
	x_put_word(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(10);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return;
	}
	x_put_word(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(10);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return;
	}
	m68k_incpci(8);
	return;
}
/* 32 (6/2) */
/* 8 0,0   */

/* EOR.L #<data>.L,(xxx).L */
void REGPARAM2 op_0ab9_13_ff(uae_u32 opcode)
{
	OpcodeFamily = 3;
	CurrentInstrCycles = 36; 
	uae_s32 src;
	src = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	src |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	uaecptr dsta;
	dsta = get_word_ce000_prefetch(8) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 8, -2);
		return;
	}
	dsta |= get_word_ce000_prefetch(10);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 10, pcoffset);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(10);
		exception3_read_access(opcode, dsta, 2, 1);
		return;
	}
	uae_s32 dst = x_get_word(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(10);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	dst |= x_get_word(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(10);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return;
	}
	src ^= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(12);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch_opcode(opcode, 12, pcoffset);
		return;
	}
	x_put_word(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(12);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return;
	}
	x_put_word(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(12);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return;
	}
	m68k_incpci(10);
	return;
}
/* 36 (7/2) */
/* 10 0,0   */

/* CMP.B #<data>.B,Dn */
void REGPARAM2 op_0c00_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 25;
	CurrentInstrCycles = 8;  
	uae_s8 src = (uae_u8)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uae_s8 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 8 (2/0) */
/* 4 0,0   */

/* CMP.B #<data>.B,(An) */
void REGPARAM2 op_0c10_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 25;
	CurrentInstrCycles = 12; 
	uae_s8 src = (uae_u8)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 12 (3/0) */
/* 4 0,0   */

/* CMP.B #<data>.B,(An)+ */
void REGPARAM2 op_0c18_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 25;
	CurrentInstrCycles = 12; 
	uae_s8 src = (uae_u8)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
	uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 12 (3/0) */
/* 4 0,0   */

/* CMP.B #<data>.B,-(An) */
void REGPARAM2 op_0c20_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 25;
	CurrentInstrCycles = 14; 
	uae_s8 src = (uae_u8)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
	do_cycles_ce000_internal(2);
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, dstreg) = dsta;
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	m68k_areg(regs, dstreg) = dsta;
	uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 14 (3/0) */
/* 4 0,0   */

/* CMP.B #<data>.B,(d16,An) */
void REGPARAM2 op_0c28_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 25;
	CurrentInstrCycles = 16; 
	uae_s8 src = (uae_u8)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return;
	}
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 16 (4/0) */
/* 6 0,0   */

/* CMP.B #<data>.B,(d8,An,Xn) */
void REGPARAM2 op_0c30_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 25;
	CurrentInstrCycles = 18; 
	uae_s8 src = (uae_u8)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr dsta;
	do_cycles_ce000_internal(2);
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_ce000_prefetch(6));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return;
	}
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 18 (4/0) */
/* 6 4,0   */

/* CMP.B #<data>.B,(xxx).W */
void REGPARAM2 op_0c38_13_ff(uae_u32 opcode)
{
	OpcodeFamily = 25;
	CurrentInstrCycles = 16; 
	uae_s8 src = (uae_u8)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, 0);
		return;
	}
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 16 (4/0) */
/* 6 0,0   */

/* CMP.B #<data>.B,(xxx).L */
void REGPARAM2 op_0c39_13_ff(uae_u32 opcode)
{
	OpcodeFamily = 25;
	CurrentInstrCycles = 20; 
	uae_s8 src = (uae_u8)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr dsta;
	dsta = get_word_ce000_prefetch(6) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return;
	}
	dsta |= get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 8, pcoffset);
		return;
	}
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(10);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 10, pcoffset);
		return;
	}
	m68k_incpci(8);
	return;
}
/* 20 (5/0) */
/* 8 0,0   */

/* CMP.W #<data>.W,Dn */
void REGPARAM2 op_0c40_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 25;
	CurrentInstrCycles = 8;  
	uae_s16 src = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 8 (2/0) */
/* 4 0,0   */

/* CMP.W #<data>.W,(An) */
void REGPARAM2 op_0c50_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 25;
	CurrentInstrCycles = 12; 
	uae_s16 src = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	if (dsta & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, dsta, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 dst = x_get_word(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 12 (3/0) */
/* 4 0,0   */

/* CMP.W #<data>.W,(An)+ */
void REGPARAM2 op_0c58_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 25;
	CurrentInstrCycles = 12; 
	uae_s16 src = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	if (dsta & 1) {
		m68k_areg(regs, dstreg) += 2 + 0;
		m68k_incpci(4);
		exception3_read_access(opcode, dsta, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 dst = x_get_word(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, dstreg) += 2 + 0;
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	m68k_areg(regs, dstreg) += 2;
	uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 12 (3/0) */
/* 4 0,0   */

/* CMP.W #<data>.W,-(An) */
void REGPARAM2 op_0c60_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 25;
	CurrentInstrCycles = 14; 
	uae_s16 src = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - 2;
	do_cycles_ce000_internal(2);
	if (dsta & 1) {
		m68k_areg(regs, dstreg) = dsta;
		m68k_incpci(4);
		exception3_read_access(opcode, dsta, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 dst = x_get_word(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, dstreg) = dsta;
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	m68k_areg(regs, dstreg) = dsta;
	uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 14 (3/0) */
/* 4 0,0   */

/* CMP.W #<data>.W,(d16,An) */
void REGPARAM2 op_0c68_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 25;
	CurrentInstrCycles = 16; 
	uae_s16 src = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, dsta, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 dst = x_get_word(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 16 (4/0) */
/* 6 0,0   */

/* CMP.W #<data>.W,(d8,An,Xn) */
void REGPARAM2 op_0c70_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 25;
	CurrentInstrCycles = 18; 
	uae_s16 src = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr dsta;
	do_cycles_ce000_internal(2);
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_ce000_prefetch(6));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, dsta, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 dst = x_get_word(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 18 (4/0) */
/* 6 4,0   */

/* CMP.W #<data>.W,(xxx).W */
void REGPARAM2 op_0c78_13_ff(uae_u32 opcode)
{
	OpcodeFamily = 25;
	CurrentInstrCycles = 16; 
	uae_s16 src = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, 0);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, dsta, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 dst = x_get_word(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 16 (4/0) */
/* 6 0,0   */

/* CMP.W #<data>.W,(xxx).L */
void REGPARAM2 op_0c79_13_ff(uae_u32 opcode)
{
	OpcodeFamily = 25;
	CurrentInstrCycles = 20; 
	uae_s16 src = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr dsta;
	dsta = get_word_ce000_prefetch(6) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return;
	}
	dsta |= get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 8, pcoffset);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(8);
		exception3_read_access(opcode, dsta, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 dst = x_get_word(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(10);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 10, pcoffset);
		return;
	}
	m68k_incpci(8);
	return;
}
/* 20 (5/0) */
/* 8 0,0   */

/* CMP.L #<data>.L,Dn */
void REGPARAM2 op_0c80_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 25;
	CurrentInstrCycles = 14; 
	uae_s32 src;
	src = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	src |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	SET_NFLG(flgn != 0);
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	opcode = regs.ir;
	do_cycles_ce000_internal(2);
	m68k_incpci(6);
	return;
}
/* 14 (3/0) */
/* 6 0,0   */

/* CMP.L #<data>.L,(An) */
void REGPARAM2 op_0c90_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 25;
	CurrentInstrCycles = 20; 
	uae_s32 src;
	src = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	src |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	if (dsta & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, dsta, 2, 1);
		return;
	}
	uae_s32 dst = x_get_word(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	dst |= x_get_word(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return;
	}
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 20 (5/0) */
/* 6 0,0   */

/* CMP.L #<data>.L,(An)+ */
void REGPARAM2 op_0c98_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 25;
	CurrentInstrCycles = 20; 
	uae_s32 src;
	src = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	src |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	if (dsta & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, dsta, 2, 1);
		return;
	}
	uae_s32 dst = x_get_word(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	dst |= x_get_word(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return;
	}
	m68k_areg(regs, dstreg) += 4;
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 20 (5/0) */
/* 6 0,0   */

/* CMP.L #<data>.L,-(An) */
void REGPARAM2 op_0ca0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 25;
	CurrentInstrCycles = 22; 
	uae_s32 src;
	src = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	src |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - 4;
	do_cycles_ce000_internal(2);
	if (dsta & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, dsta, 2, 1);
		return;
	}
	uae_s32 dst = x_get_word(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	dst |= x_get_word(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		m68k_areg(regs, dstreg) = dsta;
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return;
	}
	m68k_areg(regs, dstreg) = dsta;
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 22 (5/0) */
/* 6 0,0   */

/* CMP.L #<data>.L,(d16,An) */
void REGPARAM2 op_0ca8_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 25;
	CurrentInstrCycles = 24; 
	uae_s32 src;
	src = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	src |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 8, -2);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, dsta, 2, 1);
		return;
	}
	uae_s32 dst = x_get_word(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	dst |= x_get_word(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return;
	}
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(10);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 10, pcoffset);
		return;
	}
	m68k_incpci(8);
	return;
}
/* 24 (6/0) */
/* 8 0,0   */

/* CMP.L #<data>.L,(d8,An,Xn) */
void REGPARAM2 op_0cb0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 25;
	CurrentInstrCycles = 26; 
	uae_s32 src;
	src = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	src |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	uaecptr dsta;
	do_cycles_ce000_internal(2);
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_ce000_prefetch(8));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 8, -2);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, dsta, 2, 1);
		return;
	}
	uae_s32 dst = x_get_word(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	dst |= x_get_word(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return;
	}
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(10);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 10, pcoffset);
		return;
	}
	m68k_incpci(8);
	return;
}
/* 26 (6/0) */
/* 8 4,0   */

/* CMP.L #<data>.L,(xxx).W */
void REGPARAM2 op_0cb8_13_ff(uae_u32 opcode)
{
	OpcodeFamily = 25;
	CurrentInstrCycles = 24; 
	uae_s32 src;
	src = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	src |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 8, 0);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(8);
		exception3_read_access(opcode, dsta, 2, 1);
		return;
	}
	uae_s32 dst = x_get_word(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	dst |= x_get_word(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return;
	}
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(10);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 10, pcoffset);
		return;
	}
	m68k_incpci(8);
	return;
}
/* 24 (6/0) */
/* 8 0,0   */

/* CMP.L #<data>.L,(xxx).L */
void REGPARAM2 op_0cb9_13_ff(uae_u32 opcode)
{
	OpcodeFamily = 25;
	CurrentInstrCycles = 28; 
	uae_s32 src;
	src = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	src |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	uaecptr dsta;
	dsta = get_word_ce000_prefetch(8) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 8, -2);
		return;
	}
	dsta |= get_word_ce000_prefetch(10);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 10, pcoffset);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(10);
		exception3_read_access(opcode, dsta, 2, 1);
		return;
	}
	uae_s32 dst = x_get_word(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(10);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	dst |= x_get_word(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(10);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return;
	}
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(12);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 12, pcoffset);
		return;
	}
	m68k_incpci(10);
	return;
}
/* 28 (7/0) */
/* 10 0,0   */

/* MOVES.B #<data>.W,(An) */
#ifndef CPUEMU_68000_ONLY
void REGPARAM2 op_0e10_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 103;
	CurrentInstrCycles = 18; 
	if (!regs.s) {
		Exception(8);
		return;
	}
	uae_s16 extra = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	do_cycles_ce000_internal(4);
	if (extra & 0x800) {
		uae_u32 src = regs.regs[(extra >> 12) & 15];
		uaecptr dsta;
		dsta = m68k_areg(regs, dstreg);
		do_cycles_ce000_internal(2);
		dfc_nommu_put_byte(dsta, src);
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(6);
			regs.irc = extra;
			exception2_write(opcode, dsta + 0, 0x0, src, 1);
			return;
		}
		m68k_incpci(4);
	} else {
		uaecptr srca;
		srca = m68k_areg(regs, dstreg);
		do_cycles_ce000_internal(2);
		ipl_fetch_now();
		uae_s8 src = sfc_nommu_get_byte(srca);
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(4);
			regs.irc = extra;
			regs.write_buffer = extra;
			exception2_read(opcode, srca + 0, 0x0, 1);
			return;
		}
		if (extra & 0x8000) {
			m68k_areg(regs, (extra >> 12) & 7) = (uae_s32)(uae_s8)src;
		} else {
			m68k_dreg(regs, (extra >> 12) & 7) = (m68k_dreg(regs, (extra >> 12) & 7) & ~0xff) | ((src) & 0xff);
		}
		m68k_incpci(4);
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 18 (3/0) */
/* 4 0,0   */

#endif
/* MOVES.B #<data>.W,(An)+ */
#ifndef CPUEMU_68000_ONLY
void REGPARAM2 op_0e18_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 103;
	CurrentInstrCycles = 20; 
	if (!regs.s) {
		Exception(8);
		return;
	}
	uae_s16 extra = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	do_cycles_ce000_internal(4);
	if (extra & 0x800) {
		uae_u32 src = regs.regs[(extra >> 12) & 15];
		uaecptr dsta;
		dsta = m68k_areg(regs, dstreg);
		do_cycles_ce000_internal(4);
		m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
		src = regs.regs[(extra >> 12) & 15];
		dfc_nommu_put_byte(dsta, src);
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(6);
			regs.irc = extra;
			exception2_write(opcode, dsta + 0, 0x0, src, 1);
			return;
		}
		m68k_incpci(4);
	} else {
		uaecptr srca;
		srca = m68k_areg(regs, dstreg);
		do_cycles_ce000_internal(4);
		ipl_fetch_now();
		uae_s8 src = sfc_nommu_get_byte(srca);
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(4);
			regs.irc = extra;
			regs.write_buffer = extra;
			exception2_read(opcode, srca + 0, 0x0, 1);
			return;
		}
		m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
		if (extra & 0x8000) {
			m68k_areg(regs, (extra >> 12) & 7) = (uae_s32)(uae_s8)src;
		} else {
			m68k_dreg(regs, (extra >> 12) & 7) = (m68k_dreg(regs, (extra >> 12) & 7) & ~0xff) | ((src) & 0xff);
		}
		m68k_incpci(4);
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 20 (3/0) */
/* 4 0,0   */

#endif
/* MOVES.B #<data>.W,-(An) */
#ifndef CPUEMU_68000_ONLY
void REGPARAM2 op_0e20_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 103;
	CurrentInstrCycles = 20; 
	if (!regs.s) {
		Exception(8);
		return;
	}
	uae_s16 extra = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	do_cycles_ce000_internal(4);
	if (extra & 0x800) {
		uae_u32 src = regs.regs[(extra >> 12) & 15];
		uaecptr dsta;
		dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
		do_cycles_ce000_internal(4);
		m68k_areg(regs, dstreg) = dsta;
		src = regs.regs[(extra >> 12) & 15];
		dfc_nommu_put_byte(dsta, src);
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(6);
			regs.irc = extra;
			exception2_write(opcode, dsta + 0, 0x0, src, 1);
			return;
		}
		m68k_incpci(4);
	} else {
		uaecptr srca;
		srca = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
		do_cycles_ce000_internal(4);
		ipl_fetch_now();
		uae_s8 src = sfc_nommu_get_byte(srca);
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(4);
			m68k_areg(regs, dstreg) = srca;
			regs.irc = extra;
			regs.write_buffer = extra;
			m68k_incpci(2);
			exception2_read(opcode, srca + 0, 0x0, 1);
			return;
		}
		m68k_areg(regs, dstreg) = srca;
		if (extra & 0x8000) {
			m68k_areg(regs, (extra >> 12) & 7) = (uae_s32)(uae_s8)src;
		} else {
			m68k_dreg(regs, (extra >> 12) & 7) = (m68k_dreg(regs, (extra >> 12) & 7) & ~0xff) | ((src) & 0xff);
		}
		m68k_incpci(4);
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 20 (3/0) */
/* 4 0,0   */

#endif
/* MOVES.B #<data>.W,(d16,An) */
#ifndef CPUEMU_68000_ONLY
void REGPARAM2 op_0e28_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 103;
	CurrentInstrCycles = 20; 
	if (!regs.s) {
		Exception(8);
		return;
	}
	uae_s16 extra = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	do_cycles_ce000_internal(4);
	if (extra & 0x800) {
		uae_u32 src = regs.regs[(extra >> 12) & 15];
		uaecptr dsta;
		dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(6);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch(opcode, 6, -2);
			return;
		}
		dfc_nommu_put_byte(dsta, src);
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(8);
			regs.irc = extra;
			exception2_write(opcode, dsta + 0, 0x0, src, 1);
			return;
		}
		m68k_incpci(6);
	} else {
		uaecptr srca;
		srca = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(6);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch(opcode, 6, -2);
			return;
		}
		ipl_fetch_now();
		uae_s8 src = sfc_nommu_get_byte(srca);
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(4);
			regs.irc = extra;
			regs.write_buffer = extra;
			m68k_incpci(4);
			exception2_read(opcode, srca + 0, 0x0, 1);
			return;
		}
		if (extra & 0x8000) {
			m68k_areg(regs, (extra >> 12) & 7) = (uae_s32)(uae_s8)src;
		} else {
			m68k_dreg(regs, (extra >> 12) & 7) = (m68k_dreg(regs, (extra >> 12) & 7) & ~0xff) | ((src) & 0xff);
		}
		m68k_incpci(6);
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 20 (4/0) */
/* 6 0,0   */

#endif
/* MOVES.B #<data>.W,(d8,An,Xn) */
#ifndef CPUEMU_68000_ONLY
void REGPARAM2 op_0e30_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 103;
	CurrentInstrCycles = 24; 
	if (!regs.s) {
		Exception(8);
		return;
	}
	uae_s16 extra = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	do_cycles_ce000_internal(4);
	if (extra & 0x800) {
		uae_u32 src = regs.regs[(extra >> 12) & 15];
		uaecptr dsta;
		dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_ce000_prefetch(6));
		do_cycles_ce000_internal(4);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch(opcode, 6, -2);
			return;
		}
		dfc_nommu_put_byte(dsta, src);
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(8);
			regs.irc = extra;
			exception2_write(opcode, dsta + 0, 0x0, src, 1);
			return;
		}
		m68k_incpci(6);
	} else {
		uaecptr srca;
		srca = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_ce000_prefetch(6));
		do_cycles_ce000_internal(4);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch(opcode, 6, -2);
			return;
		}
		ipl_fetch_now();
		uae_s8 src = sfc_nommu_get_byte(srca);
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(4);
			regs.irc = extra;
			regs.write_buffer = extra;
			m68k_incpci(4);
			exception2_read(opcode, srca + 0, 0x0, 1);
			return;
		}
		if (extra & 0x8000) {
			m68k_areg(regs, (extra >> 12) & 7) = (uae_s32)(uae_s8)src;
		} else {
			m68k_dreg(regs, (extra >> 12) & 7) = (m68k_dreg(regs, (extra >> 12) & 7) & ~0xff) | ((src) & 0xff);
		}
		m68k_incpci(6);
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 24 (4/0) */
/* 6 4,4   */

#endif
/* MOVES.B #<data>.W,(xxx).W */
#ifndef CPUEMU_68000_ONLY
void REGPARAM2 op_0e38_13_ff(uae_u32 opcode)
{
	OpcodeFamily = 103;
	CurrentInstrCycles = 20; 
	if (!regs.s) {
		Exception(8);
		return;
	}
	uae_s16 extra = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	do_cycles_ce000_internal(4);
	if (extra & 0x800) {
		uae_u32 src = regs.regs[(extra >> 12) & 15];
		uaecptr dsta;
		dsta = (uae_s32)(uae_s16)get_word_ce000_prefetch(6);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch(opcode, 6, 0);
			return;
		}
		dfc_nommu_put_byte(dsta, src);
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(8);
			regs.irc = extra;
			exception2_write(opcode, dsta + 0, 0x0, src, 1);
			return;
		}
		m68k_incpci(6);
	} else {
		uaecptr srca;
		srca = (uae_s32)(uae_s16)get_word_ce000_prefetch(6);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch(opcode, 6, 0);
			return;
		}
		ipl_fetch_now();
		uae_s8 src = sfc_nommu_get_byte(srca);
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(6);
			regs.irc = extra;
			regs.write_buffer = extra;
			m68k_incpci(4);
			exception2_read(opcode, srca + 0, 0x0, 1);
			return;
		}
		if (extra & 0x8000) {
			m68k_areg(regs, (extra >> 12) & 7) = (uae_s32)(uae_s8)src;
		} else {
			m68k_dreg(regs, (extra >> 12) & 7) = (m68k_dreg(regs, (extra >> 12) & 7) & ~0xff) | ((src) & 0xff);
		}
		m68k_incpci(6);
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 20 (4/0) */
/* 6 0,0   */

#endif
/* MOVES.B #<data>.W,(xxx).L */
#ifndef CPUEMU_68000_ONLY
void REGPARAM2 op_0e39_13_ff(uae_u32 opcode)
{
	OpcodeFamily = 103;
	CurrentInstrCycles = 24; 
	if (!regs.s) {
		Exception(8);
		return;
	}
	uae_s16 extra = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	do_cycles_ce000_internal(4);
	if (extra & 0x800) {
		uae_u32 src = regs.regs[(extra >> 12) & 15];
		uaecptr dsta;
		dsta = get_word_ce000_prefetch(6) << 16;
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch(opcode, 6, -2);
			return;
		}
		dsta |= get_word_ce000_prefetch(8);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch(opcode, 8, pcoffset);
			return;
		}
		dfc_nommu_put_byte(dsta, src);
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(10);
			regs.irc = extra;
			exception2_write(opcode, dsta + 0, 0x0, src, 1);
			return;
		}
		m68k_incpci(8);
	} else {
		uaecptr srca;
		srca = get_word_ce000_prefetch(6) << 16;
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch(opcode, 6, -2);
			return;
		}
		srca |= get_word_ce000_prefetch(8);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch(opcode, 8, pcoffset);
			return;
		}
		ipl_fetch_now();
		uae_s8 src = sfc_nommu_get_byte(srca);
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(8);
			regs.irc = extra;
			regs.write_buffer = extra;
			m68k_incpci(2);
			exception2_read(opcode, srca + 0, 0x0, 1);
			return;
		}
		if (extra & 0x8000) {
			m68k_areg(regs, (extra >> 12) & 7) = (uae_s32)(uae_s8)src;
		} else {
			m68k_dreg(regs, (extra >> 12) & 7) = (m68k_dreg(regs, (extra >> 12) & 7) & ~0xff) | ((src) & 0xff);
		}
		m68k_incpci(8);
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 24 (5/0) */
/* 8 0,0   */

#endif
/* MOVES.W #<data>.W,(An) */
#ifndef CPUEMU_68000_ONLY
void REGPARAM2 op_0e50_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 103;
	CurrentInstrCycles = 18; 
	if (!regs.s) {
		Exception(8);
		return;
	}
	uae_s16 extra = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	do_cycles_ce000_internal(4);
	if (extra & 0x800) {
		uae_u32 src = regs.regs[(extra >> 12) & 15];
		uaecptr dsta;
		dsta = m68k_areg(regs, dstreg);
		do_cycles_ce000_internal(2);
		if (dsta & 1) {
			regs.irc = extra;
			m68k_incpci(6);
			exception3_write_access(opcode, dsta, 1, src, 1);
			return;
		}
		dfc_nommu_put_word(dsta, src);
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(6);
			regs.irc = extra;
			exception2_write(opcode, dsta + 0, 0x1, src, 1);
			return;
		}
		m68k_incpci(4);
	} else {
		uaecptr srca;
		srca = m68k_areg(regs, dstreg);
		do_cycles_ce000_internal(2);
		if (srca & 1) {
			regs.irc = extra;
			regs.write_buffer = extra;
			m68k_incpci(6);
			exception3_read_access(opcode, srca, 1, 1);
			return;
		}
		ipl_fetch_now();
		uae_s16 src = sfc_nommu_get_word(srca);
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(4);
			regs.irc = extra;
			regs.write_buffer = extra;
			exception2_read(opcode, srca + 0, 0x1, 1);
			return;
		}
		if (extra & 0x8000) {
			m68k_areg(regs, (extra >> 12) & 7) = (uae_s32)(uae_s16)src;
		} else {
			m68k_dreg(regs, (extra >> 12) & 7) = (m68k_dreg(regs, (extra >> 12) & 7) & ~0xffff) | ((src) & 0xffff);
		}
		m68k_incpci(4);
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 18 (3/0) */
/* 4 0,0   */

#endif
/* MOVES.W #<data>.W,(An)+ */
#ifndef CPUEMU_68000_ONLY
void REGPARAM2 op_0e58_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 103;
	CurrentInstrCycles = 20; 
	if (!regs.s) {
		Exception(8);
		return;
	}
	uae_s16 extra = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	do_cycles_ce000_internal(4);
	if (extra & 0x800) {
		uae_u32 src = regs.regs[(extra >> 12) & 15];
		uaecptr dsta;
		dsta = m68k_areg(regs, dstreg);
		do_cycles_ce000_internal(4);
		if (dsta & 1) {
			m68k_areg(regs, dstreg) += 2 + 0;
			regs.irc = extra;
			if (dstreg + 8 == ((extra >> 12) & 15)) {
				src += 2;
			}
			m68k_incpci(6);
			exception3_write_access(opcode, dsta, 1, src, 1);
			return;
		}
		m68k_areg(regs, dstreg) += 2;
		src = regs.regs[(extra >> 12) & 15];
		dfc_nommu_put_word(dsta, src);
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(6);
			regs.irc = extra;
			exception2_write(opcode, dsta + 0, 0x1, src, 1);
			return;
		}
		m68k_incpci(4);
	} else {
		uaecptr srca;
		srca = m68k_areg(regs, dstreg);
		do_cycles_ce000_internal(4);
		if (srca & 1) {
			m68k_areg(regs, dstreg) += 2 + 0;
			regs.irc = extra;
			regs.write_buffer = extra;
			m68k_incpci(6);
			exception3_read_access(opcode, srca, 1, 1);
			return;
		}
		ipl_fetch_now();
		uae_s16 src = sfc_nommu_get_word(srca);
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(4);
			m68k_areg(regs, dstreg) += 2 + 0;
			regs.irc = extra;
			regs.write_buffer = extra;
			exception2_read(opcode, srca + 0, 0x1, 1);
			return;
		}
		m68k_areg(regs, dstreg) += 2;
		if (extra & 0x8000) {
			m68k_areg(regs, (extra >> 12) & 7) = (uae_s32)(uae_s16)src;
		} else {
			m68k_dreg(regs, (extra >> 12) & 7) = (m68k_dreg(regs, (extra >> 12) & 7) & ~0xffff) | ((src) & 0xffff);
		}
		m68k_incpci(4);
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 20 (3/0) */
/* 4 0,0   */

#endif
/* MOVES.W #<data>.W,-(An) */
#ifndef CPUEMU_68000_ONLY
void REGPARAM2 op_0e60_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 103;
	CurrentInstrCycles = 20; 
	if (!regs.s) {
		Exception(8);
		return;
	}
	uae_s16 extra = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	do_cycles_ce000_internal(4);
	if (extra & 0x800) {
		uae_u32 src = regs.regs[(extra >> 12) & 15];
		uaecptr dsta;
		dsta = m68k_areg(regs, dstreg) - 2;
		do_cycles_ce000_internal(4);
		if (dsta & 1) {
			regs.irc = extra;
			if (dstreg + 8 == ((extra >> 12) & 15)) {
				src += -2;
			}
			m68k_areg(regs, dstreg) = dsta;
			m68k_incpci(6);
			exception3_write_access(opcode, dsta, 1, src, 1);
			return;
		}
		m68k_areg(regs, dstreg) = dsta;
		src = regs.regs[(extra >> 12) & 15];
		dfc_nommu_put_word(dsta, src);
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(6);
			regs.irc = extra;
			exception2_write(opcode, dsta + 0, 0x1, src, 1);
			return;
		}
		m68k_incpci(4);
	} else {
		uaecptr srca;
		srca = m68k_areg(regs, dstreg) - 2;
		do_cycles_ce000_internal(4);
		if (srca & 1) {
			regs.irc = extra;
			regs.write_buffer = extra;
			m68k_areg(regs, dstreg) = srca;
			m68k_incpci(6);
			exception3_read_access(opcode, srca, 1, 1);
			return;
		}
		ipl_fetch_now();
		uae_s16 src = sfc_nommu_get_word(srca);
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(4);
			m68k_areg(regs, dstreg) = srca;
			regs.irc = extra;
			regs.write_buffer = extra;
			m68k_incpci(2);
			exception2_read(opcode, srca + 0, 0x1, 1);
			return;
		}
		m68k_areg(regs, dstreg) = srca;
		if (extra & 0x8000) {
			m68k_areg(regs, (extra >> 12) & 7) = (uae_s32)(uae_s16)src;
		} else {
			m68k_dreg(regs, (extra >> 12) & 7) = (m68k_dreg(regs, (extra >> 12) & 7) & ~0xffff) | ((src) & 0xffff);
		}
		m68k_incpci(4);
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 20 (3/0) */
/* 4 0,0   */

#endif
/* MOVES.W #<data>.W,(d16,An) */
#ifndef CPUEMU_68000_ONLY
void REGPARAM2 op_0e68_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 103;
	CurrentInstrCycles = 20; 
	if (!regs.s) {
		Exception(8);
		return;
	}
	uae_s16 extra = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	do_cycles_ce000_internal(4);
	if (extra & 0x800) {
		uae_u32 src = regs.regs[(extra >> 12) & 15];
		uaecptr dsta;
		dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(6);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch(opcode, 6, -2);
			return;
		}
		if (dsta & 1) {
			regs.irc = extra;
			m68k_incpci(8);
			exception3_write_access(opcode, dsta, 1, src, 1);
			return;
		}
		dfc_nommu_put_word(dsta, src);
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(8);
			regs.irc = extra;
			exception2_write(opcode, dsta + 0, 0x1, src, 1);
			return;
		}
		m68k_incpci(6);
	} else {
		uaecptr srca;
		srca = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(6);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch(opcode, 6, -2);
			return;
		}
		if (srca & 1) {
			regs.irc = extra;
			regs.write_buffer = extra;
			m68k_incpci(6);
			exception3_read_access(opcode, srca, 1, 1);
			return;
		}
		ipl_fetch_now();
		uae_s16 src = sfc_nommu_get_word(srca);
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(4);
			regs.irc = extra;
			regs.write_buffer = extra;
			m68k_incpci(4);
			exception2_read(opcode, srca + 0, 0x1, 1);
			return;
		}
		if (extra & 0x8000) {
			m68k_areg(regs, (extra >> 12) & 7) = (uae_s32)(uae_s16)src;
		} else {
			m68k_dreg(regs, (extra >> 12) & 7) = (m68k_dreg(regs, (extra >> 12) & 7) & ~0xffff) | ((src) & 0xffff);
		}
		m68k_incpci(6);
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 20 (4/0) */
/* 6 0,0   */

#endif
/* MOVES.W #<data>.W,(d8,An,Xn) */
#ifndef CPUEMU_68000_ONLY
void REGPARAM2 op_0e70_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 103;
	CurrentInstrCycles = 24; 
	if (!regs.s) {
		Exception(8);
		return;
	}
	uae_s16 extra = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	do_cycles_ce000_internal(4);
	if (extra & 0x800) {
		uae_u32 src = regs.regs[(extra >> 12) & 15];
		uaecptr dsta;
		dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_ce000_prefetch(6));
		do_cycles_ce000_internal(4);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch(opcode, 6, -2);
			return;
		}
		if (dsta & 1) {
			regs.irc = extra;
			m68k_incpci(8);
			exception3_write_access(opcode, dsta, 1, src, 1);
			return;
		}
		dfc_nommu_put_word(dsta, src);
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(8);
			regs.irc = extra;
			exception2_write(opcode, dsta + 0, 0x1, src, 1);
			return;
		}
		m68k_incpci(6);
	} else {
		uaecptr srca;
		srca = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_ce000_prefetch(6));
		do_cycles_ce000_internal(4);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch(opcode, 6, -2);
			return;
		}
		if (srca & 1) {
			regs.irc = extra;
			regs.write_buffer = extra;
			m68k_incpci(8);
			exception3_read_access(opcode, srca, 1, 1);
			return;
		}
		ipl_fetch_now();
		uae_s16 src = sfc_nommu_get_word(srca);
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(4);
			regs.irc = extra;
			regs.write_buffer = extra;
			m68k_incpci(4);
			exception2_read(opcode, srca + 0, 0x1, 1);
			return;
		}
		if (extra & 0x8000) {
			m68k_areg(regs, (extra >> 12) & 7) = (uae_s32)(uae_s16)src;
		} else {
			m68k_dreg(regs, (extra >> 12) & 7) = (m68k_dreg(regs, (extra >> 12) & 7) & ~0xffff) | ((src) & 0xffff);
		}
		m68k_incpci(6);
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 24 (4/0) */
/* 6 4,4   */

#endif
/* MOVES.W #<data>.W,(xxx).W */
#ifndef CPUEMU_68000_ONLY
void REGPARAM2 op_0e78_13_ff(uae_u32 opcode)
{
	OpcodeFamily = 103;
	CurrentInstrCycles = 20; 
	if (!regs.s) {
		Exception(8);
		return;
	}
	uae_s16 extra = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	do_cycles_ce000_internal(4);
	if (extra & 0x800) {
		uae_u32 src = regs.regs[(extra >> 12) & 15];
		uaecptr dsta;
		dsta = (uae_s32)(uae_s16)get_word_ce000_prefetch(6);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch(opcode, 6, 0);
			return;
		}
		if (dsta & 1) {
			regs.irc = extra;
			m68k_incpci(8);
			exception3_write_access(opcode, dsta, 1, src, 1);
			return;
		}
		dfc_nommu_put_word(dsta, src);
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(8);
			regs.irc = extra;
			exception2_write(opcode, dsta + 0, 0x1, src, 1);
			return;
		}
		m68k_incpci(6);
	} else {
		uaecptr srca;
		srca = (uae_s32)(uae_s16)get_word_ce000_prefetch(6);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch(opcode, 6, 0);
			return;
		}
		if (srca & 1) {
			regs.irc = extra;
			regs.write_buffer = extra;
			m68k_incpci(8);
			exception3_read_access(opcode, srca, 1, 1);
			return;
		}
		ipl_fetch_now();
		uae_s16 src = sfc_nommu_get_word(srca);
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(6);
			regs.irc = extra;
			regs.write_buffer = extra;
			m68k_incpci(4);
			exception2_read(opcode, srca + 0, 0x1, 1);
			return;
		}
		if (extra & 0x8000) {
			m68k_areg(regs, (extra >> 12) & 7) = (uae_s32)(uae_s16)src;
		} else {
			m68k_dreg(regs, (extra >> 12) & 7) = (m68k_dreg(regs, (extra >> 12) & 7) & ~0xffff) | ((src) & 0xffff);
		}
		m68k_incpci(6);
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 20 (4/0) */
/* 6 0,0   */

#endif
/* MOVES.W #<data>.W,(xxx).L */
#ifndef CPUEMU_68000_ONLY
void REGPARAM2 op_0e79_13_ff(uae_u32 opcode)
{
	OpcodeFamily = 103;
	CurrentInstrCycles = 24; 
	if (!regs.s) {
		Exception(8);
		return;
	}
	uae_s16 extra = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	do_cycles_ce000_internal(4);
	if (extra & 0x800) {
		uae_u32 src = regs.regs[(extra >> 12) & 15];
		uaecptr dsta;
		dsta = get_word_ce000_prefetch(6) << 16;
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch(opcode, 6, -2);
			return;
		}
		dsta |= get_word_ce000_prefetch(8);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch(opcode, 8, pcoffset);
			return;
		}
		if (dsta & 1) {
			regs.irc = extra;
			m68k_incpci(10);
			exception3_write_access(opcode, dsta, 1, src, 1);
			return;
		}
		dfc_nommu_put_word(dsta, src);
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(10);
			regs.irc = extra;
			exception2_write(opcode, dsta + 0, 0x1, src, 1);
			return;
		}
		m68k_incpci(8);
	} else {
		uaecptr srca;
		srca = get_word_ce000_prefetch(6) << 16;
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch(opcode, 6, -2);
			return;
		}
		srca |= get_word_ce000_prefetch(8);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch(opcode, 8, pcoffset);
			return;
		}
		if (srca & 1) {
			regs.irc = extra;
			regs.write_buffer = extra;
			m68k_incpci(10);
			exception3_read_access(opcode, srca, 1, 1);
			return;
		}
		ipl_fetch_now();
		uae_s16 src = sfc_nommu_get_word(srca);
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(8);
			regs.irc = extra;
			regs.write_buffer = extra;
			m68k_incpci(2);
			exception2_read(opcode, srca + 0, 0x1, 1);
			return;
		}
		if (extra & 0x8000) {
			m68k_areg(regs, (extra >> 12) & 7) = (uae_s32)(uae_s16)src;
		} else {
			m68k_dreg(regs, (extra >> 12) & 7) = (m68k_dreg(regs, (extra >> 12) & 7) & ~0xffff) | ((src) & 0xffff);
		}
		m68k_incpci(8);
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 24 (5/0) */
/* 8 0,0   */

#endif
/* MOVES.L #<data>.W,(An) */
#ifndef CPUEMU_68000_ONLY
void REGPARAM2 op_0e90_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 103;
	CurrentInstrCycles = 22; 
	if (!regs.s) {
		Exception(8);
		return;
	}
	uae_s16 extra = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	do_cycles_ce000_internal(4);
	if (extra & 0x800) {
		uae_u32 src = regs.regs[(extra >> 12) & 15];
		uaecptr dsta;
		dsta = m68k_areg(regs, dstreg);
		do_cycles_ce000_internal(2);
		if (dsta & 1) {
			regs.irc = extra;
			m68k_incpci(6);
			exception3_write_access(opcode, dsta, 2, src >> 16, 1);
			return;
		}
		src = regs.regs[(extra >> 12) & 15];
		dfc_nommu_put_word(dsta, src >> 16);
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(6);
			regs.irc = extra;
			exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
			return;
		}
		dfc_nommu_put_word(dsta + 2, src);
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(6);
			regs.irc = extra;
			exception2_write(opcode, dsta + 2, 0x1, src, 1);
			return;
		}
		m68k_incpci(4);
	} else {
		uaecptr srca;
		srca = m68k_areg(regs, dstreg);
		do_cycles_ce000_internal(2);
		if (srca & 1) {
			regs.irc = extra;
			regs.write_buffer = extra;
			m68k_incpci(6);
			exception3_read_access(opcode, srca, 2, 1);
			return;
		}
		uae_s32 src = sfc_nommu_get_word(srca) << 16;
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(4);
			regs.irc = extra;
			regs.write_buffer = extra;
			exception2_read(opcode, srca + 0, 0x1, 1);
			return;
		}
		ipl_fetch_now();
		src |= sfc_nommu_get_word(srca + 2);
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(4);
			regs.irc = extra;
			regs.write_buffer = extra;
			exception2_read(opcode, srca + 2, 0x1, 1);
			return;
		}
		if (extra & 0x8000) {
			m68k_areg(regs, (extra >> 12) & 7) = src;
		} else {
			m68k_dreg(regs, (extra >> 12) & 7) = (src);
		}
		m68k_incpci(4);
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 22 (4/0) */
/* 4 0,0   */

#endif
/* MOVES.L #<data>.W,(An)+ */
#ifndef CPUEMU_68000_ONLY
void REGPARAM2 op_0e98_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 103;
	CurrentInstrCycles = 24; 
	if (!regs.s) {
		Exception(8);
		return;
	}
	uae_s16 extra = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	do_cycles_ce000_internal(4);
	if (extra & 0x800) {
		uae_u32 src = regs.regs[(extra >> 12) & 15];
		uaecptr dsta;
		dsta = m68k_areg(regs, dstreg);
		do_cycles_ce000_internal(4);
		if (dsta & 1) {
			regs.irc = extra;
			if (dstreg + 8 == ((extra >> 12) & 15)) {
				src += 2;
			}
			m68k_areg(regs, dstreg) += 4;
			m68k_incpci(6);
			exception3_write_access(opcode, dsta, 2, src >> 16, 1);
			return;
		}
		m68k_areg(regs, dstreg) += 4;
		src = regs.regs[(extra >> 12) & 15];
		dfc_nommu_put_word(dsta, src >> 16);
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(6);
			regs.irc = extra;
			m68k_areg(regs, dstreg) += 4;
			exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
			return;
		}
		dfc_nommu_put_word(dsta + 2, src);
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(6);
			regs.irc = extra;
			m68k_areg(regs, dstreg) += 4;
			exception2_write(opcode, dsta + 2, 0x1, src, 1);
			return;
		}
		m68k_incpci(4);
	} else {
		uaecptr srca;
		srca = m68k_areg(regs, dstreg);
		do_cycles_ce000_internal(4);
		if (srca & 1) {
			regs.irc = extra;
			regs.write_buffer = extra;
			m68k_areg(regs, dstreg) += 4;
			m68k_incpci(6);
			exception3_read_access(opcode, srca, 2, 1);
			return;
		}
		uae_s32 src = sfc_nommu_get_word(srca) << 16;
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(4);
			regs.irc = extra;
			regs.write_buffer = extra;
			m68k_areg(regs, dstreg) += 4;
			exception2_read(opcode, srca + 0, 0x1, 1);
			return;
		}
		ipl_fetch_now();
		src |= sfc_nommu_get_word(srca + 2);
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(4);
			regs.irc = extra;
			regs.write_buffer = extra;
			m68k_areg(regs, dstreg) += 4;
			exception2_read(opcode, srca + 2, 0x1, 1);
			return;
		}
		m68k_areg(regs, dstreg) += 4;
		if (extra & 0x8000) {
			m68k_areg(regs, (extra >> 12) & 7) = src;
		} else {
			m68k_dreg(regs, (extra >> 12) & 7) = (src);
		}
		m68k_incpci(4);
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 24 (4/0) */
/* 4 0,0   */

#endif
/* MOVES.L #<data>.W,-(An) */
#ifndef CPUEMU_68000_ONLY
void REGPARAM2 op_0ea0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 103;
	CurrentInstrCycles = 24; 
	if (!regs.s) {
		Exception(8);
		return;
	}
	uae_s16 extra = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	do_cycles_ce000_internal(4);
	if (extra & 0x800) {
		uae_u32 src = regs.regs[(extra >> 12) & 15];
		uaecptr dsta;
		dsta = m68k_areg(regs, dstreg) - 4;
		do_cycles_ce000_internal(4);
		if (dsta & 1) {
			regs.irc = extra;
			if (dstreg + 8 == ((extra >> 12) & 15)) {
				src += -2;
			}
			m68k_incpci(6);
			m68k_areg(regs, dstreg) = dsta;
			exception3_write_access(opcode, dsta, 2, src >> 16, 1);
			return;
		}
		m68k_areg(regs, dstreg) = dsta;
		src = regs.regs[(extra >> 12) & 15];
		dfc_nommu_put_word(dsta, src >> 16);
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(6);
			regs.irc = extra;
			exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
			return;
		}
		dfc_nommu_put_word(dsta + 2, src);
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(6);
			regs.irc = extra;
			exception2_write(opcode, dsta + 2, 0x1, src, 1);
			return;
		}
		m68k_incpci(4);
	} else {
		uaecptr srca;
		srca = m68k_areg(regs, dstreg) - 4;
		do_cycles_ce000_internal(4);
		if (srca & 1) {
			regs.irc = extra;
			regs.write_buffer = extra;
			m68k_incpci(6);
			m68k_areg(regs, dstreg) = srca;
			exception3_read_access(opcode, srca, 2, 1);
			return;
		}
		uae_s32 src = sfc_nommu_get_word(srca) << 16;
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(4);
			regs.irc = extra;
			regs.write_buffer = extra;
			m68k_areg(regs, dstreg) = srca;
			m68k_incpci(2);
			exception2_read(opcode, srca + 0, 0x1, 1);
			return;
		}
		ipl_fetch_now();
		src |= sfc_nommu_get_word(srca + 2);
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(4);
			m68k_areg(regs, dstreg) = srca;
			regs.irc = extra;
			regs.write_buffer = extra;
			m68k_areg(regs, dstreg) = srca;
			m68k_incpci(2);
			exception2_read(opcode, srca + 2, 0x1, 1);
			return;
		}
		m68k_areg(regs, dstreg) = srca;
		if (extra & 0x8000) {
			m68k_areg(regs, (extra >> 12) & 7) = src;
		} else {
			m68k_dreg(regs, (extra >> 12) & 7) = (src);
		}
		m68k_incpci(4);
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 24 (4/0) */
/* 4 0,0   */

#endif
/* MOVES.L #<data>.W,(d16,An) */
#ifndef CPUEMU_68000_ONLY
void REGPARAM2 op_0ea8_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 103;
	CurrentInstrCycles = 24; 
	if (!regs.s) {
		Exception(8);
		return;
	}
	uae_s16 extra = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	do_cycles_ce000_internal(4);
	if (extra & 0x800) {
		uae_u32 src = regs.regs[(extra >> 12) & 15];
		uaecptr dsta;
		dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(6);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch(opcode, 6, -2);
			return;
		}
		if (dsta & 1) {
			regs.irc = extra;
			m68k_incpci(8);
			exception3_write_access(opcode, dsta, 2, src >> 16, 1);
			return;
		}
		src = regs.regs[(extra >> 12) & 15];
		dfc_nommu_put_word(dsta, src >> 16);
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(8);
			regs.irc = extra;
			exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
			return;
		}
		dfc_nommu_put_word(dsta + 2, src);
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(8);
			regs.irc = extra;
			exception2_write(opcode, dsta + 2, 0x1, src, 1);
			return;
		}
		m68k_incpci(6);
	} else {
		uaecptr srca;
		srca = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(6);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch(opcode, 6, -2);
			return;
		}
		if (srca & 1) {
			regs.irc = extra;
			regs.write_buffer = extra;
			m68k_incpci(6);
			exception3_read_access(opcode, srca, 2, 1);
			return;
		}
		uae_s32 src = sfc_nommu_get_word(srca) << 16;
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(4);
			regs.irc = extra;
			regs.write_buffer = extra;
			m68k_incpci(4);
			exception2_read(opcode, srca + 0, 0x1, 1);
			return;
		}
		ipl_fetch_now();
		src |= sfc_nommu_get_word(srca + 2);
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(4);
			regs.irc = extra;
			regs.write_buffer = extra;
			m68k_incpci(4);
			exception2_read(opcode, srca + 2, 0x1, 1);
			return;
		}
		if (extra & 0x8000) {
			m68k_areg(regs, (extra >> 12) & 7) = src;
		} else {
			m68k_dreg(regs, (extra >> 12) & 7) = (src);
		}
		m68k_incpci(6);
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 24 (5/0) */
/* 6 0,0   */

#endif
/* MOVES.L #<data>.W,(d8,An,Xn) */
#ifndef CPUEMU_68000_ONLY
void REGPARAM2 op_0eb0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 103;
	CurrentInstrCycles = 28; 
	if (!regs.s) {
		Exception(8);
		return;
	}
	uae_s16 extra = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	do_cycles_ce000_internal(4);
	if (extra & 0x800) {
		uae_u32 src = regs.regs[(extra >> 12) & 15];
		uaecptr dsta;
		dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_ce000_prefetch(6));
		do_cycles_ce000_internal(4);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch(opcode, 6, -2);
			return;
		}
		if (dsta & 1) {
			regs.irc = extra;
			m68k_incpci(8);
			exception3_write_access(opcode, dsta, 2, src >> 16, 1);
			return;
		}
		src = regs.regs[(extra >> 12) & 15];
		dfc_nommu_put_word(dsta, src >> 16);
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(8);
			regs.irc = extra;
			exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
			return;
		}
		dfc_nommu_put_word(dsta + 2, src);
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(8);
			regs.irc = extra;
			exception2_write(opcode, dsta + 2, 0x1, src, 1);
			return;
		}
		m68k_incpci(6);
	} else {
		uaecptr srca;
		srca = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_ce000_prefetch(6));
		do_cycles_ce000_internal(4);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch(opcode, 6, -2);
			return;
		}
		if (srca & 1) {
			regs.irc = extra;
			regs.write_buffer = extra;
			m68k_incpci(8);
			exception3_read_access(opcode, srca, 2, 1);
			return;
		}
		uae_s32 src = sfc_nommu_get_word(srca) << 16;
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(4);
			regs.irc = extra;
			regs.write_buffer = extra;
			m68k_incpci(4);
			exception2_read(opcode, srca + 0, 0x1, 1);
			return;
		}
		ipl_fetch_now();
		src |= sfc_nommu_get_word(srca + 2);
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(4);
			regs.irc = extra;
			regs.write_buffer = extra;
			m68k_incpci(4);
			exception2_read(opcode, srca + 2, 0x1, 1);
			return;
		}
		if (extra & 0x8000) {
			m68k_areg(regs, (extra >> 12) & 7) = src;
		} else {
			m68k_dreg(regs, (extra >> 12) & 7) = (src);
		}
		m68k_incpci(6);
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 28 (5/0) */
/* 6 4,4   */

#endif
/* MOVES.L #<data>.W,(xxx).W */
#ifndef CPUEMU_68000_ONLY
void REGPARAM2 op_0eb8_13_ff(uae_u32 opcode)
{
	OpcodeFamily = 103;
	CurrentInstrCycles = 24; 
	if (!regs.s) {
		Exception(8);
		return;
	}
	uae_s16 extra = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	do_cycles_ce000_internal(4);
	if (extra & 0x800) {
		uae_u32 src = regs.regs[(extra >> 12) & 15];
		uaecptr dsta;
		dsta = (uae_s32)(uae_s16)get_word_ce000_prefetch(6);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch(opcode, 6, 0);
			return;
		}
		if (dsta & 1) {
			regs.irc = extra;
			m68k_incpci(8);
			exception3_write_access(opcode, dsta, 2, src >> 16, 1);
			return;
		}
		src = regs.regs[(extra >> 12) & 15];
		dfc_nommu_put_word(dsta, src >> 16);
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(8);
			regs.irc = extra;
			exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
			return;
		}
		dfc_nommu_put_word(dsta + 2, src);
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(8);
			regs.irc = extra;
			exception2_write(opcode, dsta + 2, 0x1, src, 1);
			return;
		}
		m68k_incpci(6);
	} else {
		uaecptr srca;
		srca = (uae_s32)(uae_s16)get_word_ce000_prefetch(6);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch(opcode, 6, 0);
			return;
		}
		if (srca & 1) {
			regs.irc = extra;
			regs.write_buffer = extra;
			m68k_incpci(8);
			exception3_read_access(opcode, srca, 2, 1);
			return;
		}
		uae_s32 src = sfc_nommu_get_word(srca) << 16;
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(6);
			regs.irc = extra;
			regs.write_buffer = extra;
			m68k_incpci(4);
			exception2_read(opcode, srca + 0, 0x1, 1);
			return;
		}
		ipl_fetch_now();
		src |= sfc_nommu_get_word(srca + 2);
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(6);
			regs.irc = extra;
			regs.write_buffer = extra;
			m68k_incpci(4);
			exception2_read(opcode, srca + 2, 0x1, 1);
			return;
		}
		if (extra & 0x8000) {
			m68k_areg(regs, (extra >> 12) & 7) = src;
		} else {
			m68k_dreg(regs, (extra >> 12) & 7) = (src);
		}
		m68k_incpci(6);
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 24 (5/0) */
/* 6 0,0   */

#endif
/* MOVES.L #<data>.W,(xxx).L */
#ifndef CPUEMU_68000_ONLY
void REGPARAM2 op_0eb9_13_ff(uae_u32 opcode)
{
	OpcodeFamily = 103;
	CurrentInstrCycles = 28; 
	if (!regs.s) {
		Exception(8);
		return;
	}
	uae_s16 extra = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	do_cycles_ce000_internal(4);
	if (extra & 0x800) {
		uae_u32 src = regs.regs[(extra >> 12) & 15];
		uaecptr dsta;
		dsta = get_word_ce000_prefetch(6) << 16;
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch(opcode, 6, -2);
			return;
		}
		dsta |= get_word_ce000_prefetch(8);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch(opcode, 8, pcoffset);
			return;
		}
		if (dsta & 1) {
			regs.irc = extra;
			m68k_incpci(10);
			exception3_write_access(opcode, dsta, 2, src >> 16, 1);
			return;
		}
		src = regs.regs[(extra >> 12) & 15];
		dfc_nommu_put_word(dsta, src >> 16);
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(10);
			regs.irc = extra;
			exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
			return;
		}
		dfc_nommu_put_word(dsta + 2, src);
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(10);
			regs.irc = extra;
			exception2_write(opcode, dsta + 2, 0x1, src, 1);
			return;
		}
		m68k_incpci(8);
	} else {
		uaecptr srca;
		srca = get_word_ce000_prefetch(6) << 16;
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch(opcode, 6, -2);
			return;
		}
		srca |= get_word_ce000_prefetch(8);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch(opcode, 8, pcoffset);
			return;
		}
		if (srca & 1) {
			regs.irc = extra;
			regs.write_buffer = extra;
			m68k_incpci(10);
			exception3_read_access(opcode, srca, 2, 1);
			return;
		}
		uae_s32 src = sfc_nommu_get_word(srca) << 16;
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(8);
			regs.irc = extra;
			regs.write_buffer = extra;
			m68k_incpci(2);
			exception2_read(opcode, srca + 0, 0x1, 1);
			return;
		}
		ipl_fetch_now();
		src |= sfc_nommu_get_word(srca + 2);
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(8);
			regs.irc = extra;
			regs.write_buffer = extra;
			m68k_incpci(2);
			exception2_read(opcode, srca + 2, 0x1, 1);
			return;
		}
		if (extra & 0x8000) {
			m68k_areg(regs, (extra >> 12) & 7) = src;
		} else {
			m68k_dreg(regs, (extra >> 12) & 7) = (src);
		}
		m68k_incpci(8);
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 28 (6/0) */
/* 8 0,0   */

#endif
/* MOVE.B Dn,Dn */
void REGPARAM2 op_1000_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 4;  
	uae_s8 src = m68k_dreg(regs, srcreg);
	struct flag_struct oldflags;
	oldflags.cznv = regflags.cznv;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
	m68k_incpci(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 4 (1/0) */
/* 2 0,0   */

/* MOVE.B (An),Dn */
void REGPARAM2 op_1010_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 8;  
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
	m68k_incpci(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 8 (2/0) */
/* 2 0,0   */

/* MOVE.B (An)+,Dn */
void REGPARAM2 op_1018_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 8;  
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
	m68k_incpci(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 8 (2/0) */
/* 2 0,0   */

/* MOVE.B -(An),Dn */
void REGPARAM2 op_1020_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 10; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
	do_cycles_ce000_internal(2);
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	m68k_areg(regs, srcreg) = srca;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
	m68k_incpci(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 10 (2/0) */
/* 2 0,0   */

/* MOVE.B (d16,An),Dn */
void REGPARAM2 op_1028_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 12 (3/0) */
/* 4 0,0   */

/* MOVE.B (d8,An,Xn),Dn */
void REGPARAM2 op_1030_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	do_cycles_ce000_internal(2);
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 14 (3/0) */
/* 4 4,0   */

/* MOVE.B (xxx).W,Dn */
void REGPARAM2 op_1038_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 12 (3/0) */
/* 4 0,0   */

/* MOVE.B (xxx).L,Dn */
void REGPARAM2 op_1039_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	srca |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 16 (4/0) */
/* 6 0,0   */

/* MOVE.B (d16,PC),Dn */
void REGPARAM2 op_103a_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_getpci() + 2;
	srca += (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 2);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 12 (3/0) */
/* 4 0,0   */

/* MOVE.B (d8,PC,Xn),Dn */
void REGPARAM2 op_103b_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	uaecptr tmppc = m68k_getpci() + 2;
	do_cycles_ce000_internal(2);
	srca = get_disp_ea_000(tmppc, get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 2);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 14 (3/0) */
/* 4 4,0   */

/* MOVE.B #<data>.B,Dn */
void REGPARAM2 op_103c_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 8;  
	uae_s8 src = (uae_u8)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	struct flag_struct oldflags;
	oldflags.cznv = regflags.cznv;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 8 (2/0) */
/* 4 0,0   */

/* MOVE.B Dn,(An) */
void REGPARAM2 op_1080_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 8;  
	int loop_mode = regs.loop_mode;
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	struct flag_struct oldflags;
	oldflags.cznv = regflags.cznv;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	ipl_fetch_now();
	x_put_byte(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return;
	}
	m68k_incpci(2);
	if(!loop_mode) {
		regs.ir = regs.irc;
		opcode = regs.ir;
		get_word_ce000_prefetch(2);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 2, pcoffset);
			return;
		}
	} else {
		loop_mode = 0;
		loop_mode |= 2;
		loop_mode |= 4 << 16;
	}
	regs.loop_mode = loop_mode;
	return;
}
/* 8 (1/1) */
/* 2 0,0   */

/* MOVE.B (An),(An) */
void REGPARAM2 op_1090_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 12; 
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	ipl_fetch_now();
	x_put_byte(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return;
	}
	m68k_incpci(2);
	if(!loop_mode) {
		regs.ir = regs.irc;
		opcode = regs.ir;
		get_word_ce000_prefetch(2);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 2, pcoffset);
			return;
		}
	} else {
		loop_mode = 0;
		loop_mode |= 2;
		loop_mode |= 2 << 16;
	}
	regs.loop_mode = loop_mode;
	return;
}
/* 12 (2/1) */
/* 2 0,0   */

/* MOVE.B (An)+,(An) */
void REGPARAM2 op_1098_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 12; 
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	ipl_fetch_now();
	x_put_byte(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return;
	}
	m68k_incpci(2);
	if(!loop_mode) {
		regs.ir = regs.irc;
		opcode = regs.ir;
		get_word_ce000_prefetch(2);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 2, pcoffset);
			return;
		}
	} else {
		loop_mode = 0;
		loop_mode |= 2;
		loop_mode |= 2 << 16;
	}
	regs.loop_mode = loop_mode;
	return;
}
/* 12 (2/1) */
/* 2 0,0   */

/* MOVE.B -(An),(An) */
void REGPARAM2 op_10a0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 14; 
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
	do_cycles_ce000_internal(2);
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	m68k_areg(regs, srcreg) = srca;
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	ipl_fetch_now();
	x_put_byte(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return;
	}
	m68k_incpci(2);
	if(!loop_mode) {
		regs.ir = regs.irc;
		opcode = regs.ir;
		get_word_ce000_prefetch(2);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 2, pcoffset);
			return;
		}
	} else {
		loop_mode = 0;
		loop_mode |= 2;
		loop_mode |= 2 << 16;
	}
	regs.loop_mode = loop_mode;
	return;
}
/* 14 (2/1) */
/* 2 0,0   */

/* MOVE.B (d16,An),(An) */
void REGPARAM2 op_10a8_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	ipl_fetch_now();
	x_put_byte(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* MOVE.B (d8,An,Xn),(An) */
void REGPARAM2 op_10b0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	do_cycles_ce000_internal(2);
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	ipl_fetch_now();
	x_put_byte(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 18 (3/1) */
/* 4 4,0   */

/* MOVE.B (xxx).W,(An) */
void REGPARAM2 op_10b8_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	ipl_fetch_now();
	x_put_byte(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* MOVE.B (xxx).L,(An) */
void REGPARAM2 op_10b9_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	srca = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	srca |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	ipl_fetch_now();
	x_put_byte(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return;
	}
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 20 (4/1) */
/* 6 0,0   */

/* MOVE.B (d16,PC),(An) */
void REGPARAM2 op_10ba_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = m68k_getpci() + 2;
	srca += (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 2);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	ipl_fetch_now();
	x_put_byte(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* MOVE.B (d8,PC,Xn),(An) */
void REGPARAM2 op_10bb_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	uaecptr tmppc = m68k_getpci() + 2;
	do_cycles_ce000_internal(2);
	srca = get_disp_ea_000(tmppc, get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 2);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	ipl_fetch_now();
	x_put_byte(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 18 (3/1) */
/* 4 4,0   */

/* MOVE.B #<data>.B,(An) */
void REGPARAM2 op_10bc_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 12; 
	uae_s8 src = (uae_u8)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	struct flag_struct oldflags;
	oldflags.cznv = regflags.cznv;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	ipl_fetch_now();
	x_put_byte(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 12 (2/1) */
/* 4 0,0   */

/* MOVE.B Dn,(An)+ */
void REGPARAM2 op_10c0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 8;  
	int loop_mode = regs.loop_mode;
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
	struct flag_struct oldflags;
	oldflags.cznv = regflags.cznv;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	ipl_fetch_next_pre();
	x_put_byte(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, dstreg) -= areg_byteinc[dstreg];
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return;
	}
	m68k_incpci(2);
	if(!loop_mode) {
		regs.ir = regs.irc;
		opcode = regs.ir;
		get_word_ce000_prefetch(2);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 2, pcoffset);
			return;
		}
	} else {
		loop_mode = 0;
		loop_mode |= 2;
		loop_mode |= 4 << 16;
	}
	regs.loop_mode = loop_mode;
	return;
}
/* 8 (1/1) */
/* 2 0,0   */

/* MOVE.B (An),(An)+ */
void REGPARAM2 op_10d0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 12; 
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	x_put_byte(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, dstreg) -= areg_byteinc[dstreg];
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return;
	}
	m68k_incpci(2);
	if(!loop_mode) {
		regs.ir = regs.irc;
		opcode = regs.ir;
		get_word_ce000_prefetch(2);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 2, pcoffset);
			return;
		}
	} else {
		loop_mode = 0;
		loop_mode |= 2;
		loop_mode |= 2 << 16;
	}
	regs.loop_mode = loop_mode;
	return;
}
/* 12 (2/1) */
/* 2 0,0   */

/* MOVE.B (An)+,(An)+ */
void REGPARAM2 op_10d8_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 12; 
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	x_put_byte(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, dstreg) -= areg_byteinc[dstreg];
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return;
	}
	m68k_incpci(2);
	if(!loop_mode) {
		regs.ir = regs.irc;
		opcode = regs.ir;
		get_word_ce000_prefetch(2);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 2, pcoffset);
			return;
		}
	} else {
		loop_mode = 0;
		loop_mode |= 2;
		loop_mode |= 2 << 16;
	}
	regs.loop_mode = loop_mode;
	return;
}
/* 12 (2/1) */
/* 2 0,0   */

/* MOVE.B -(An),(An)+ */
void REGPARAM2 op_10e0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 14; 
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
	do_cycles_ce000_internal(2);
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	m68k_areg(regs, srcreg) = srca;
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	x_put_byte(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, dstreg) -= areg_byteinc[dstreg];
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return;
	}
	m68k_incpci(2);
	if(!loop_mode) {
		regs.ir = regs.irc;
		opcode = regs.ir;
		get_word_ce000_prefetch(2);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 2, pcoffset);
			return;
		}
	} else {
		loop_mode = 0;
		loop_mode |= 2;
		loop_mode |= 2 << 16;
	}
	regs.loop_mode = loop_mode;
	return;
}
/* 14 (2/1) */
/* 2 0,0   */

/* MOVE.B (d16,An),(An)+ */
void REGPARAM2 op_10e8_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	x_put_byte(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, dstreg) -= areg_byteinc[dstreg];
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* MOVE.B (d8,An,Xn),(An)+ */
void REGPARAM2 op_10f0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	do_cycles_ce000_internal(2);
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	x_put_byte(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, dstreg) -= areg_byteinc[dstreg];
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 18 (3/1) */
/* 4 4,0   */

/* MOVE.B (xxx).W,(An)+ */
void REGPARAM2 op_10f8_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	x_put_byte(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, dstreg) -= areg_byteinc[dstreg];
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* MOVE.B (xxx).L,(An)+ */
void REGPARAM2 op_10f9_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	srca = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	srca |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	x_put_byte(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		m68k_areg(regs, dstreg) -= areg_byteinc[dstreg];
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return;
	}
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 20 (4/1) */
/* 6 0,0   */

/* MOVE.B (d16,PC),(An)+ */
void REGPARAM2 op_10fa_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = m68k_getpci() + 2;
	srca += (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 2);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	x_put_byte(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, dstreg) -= areg_byteinc[dstreg];
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* MOVE.B (d8,PC,Xn),(An)+ */
void REGPARAM2 op_10fb_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	uaecptr tmppc = m68k_getpci() + 2;
	do_cycles_ce000_internal(2);
	srca = get_disp_ea_000(tmppc, get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 2);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	x_put_byte(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, dstreg) -= areg_byteinc[dstreg];
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 18 (3/1) */
/* 4 4,0   */

/* MOVE.B #<data>.B,(An)+ */
void REGPARAM2 op_10fc_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 12; 
	ipl_fetch_now();
	uae_s8 src = (uae_u8)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
	struct flag_struct oldflags;
	oldflags.cznv = regflags.cznv;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	x_put_byte(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, dstreg) -= areg_byteinc[dstreg];
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 12 (2/1) */
/* 4 0,0   */

/* MOVE.B Dn,-(An) */
void REGPARAM2 op_1100_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 8;  
	ipl_fetch_next_pre();
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
	m68k_areg(regs, dstreg) = dsta;
	regs.ir = regs.irc;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	struct flag_struct oldflags;
	oldflags.cznv = regflags.cznv;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	x_put_byte(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 8 (1/1) */
/* 2 0,0   */

/* MOVE.B (An),-(An) */
void REGPARAM2 op_1110_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 12; 
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
	m68k_areg(regs, dstreg) = dsta;
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_ce000_prefetch(4);
		if(hardware_bus_error) {
			int pcoffset = 0;
			m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
			ccr_68000_word_move_ae_normal((uae_s16)src);
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return;
		}
		opcode = regs.ir;
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	if(loop_mode & 0xfffe) {
		do_cycles_ce000_internal(loop_mode & 0xfffe);
		loop_mode = 1;
	}
	x_put_byte(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return;
	}
	m68k_incpci(2);
	regs.loop_mode = loop_mode;
	return;
}
/* 12 (2/1) */
/* 2 0,0   */

/* MOVE.B (An)+,-(An) */
void REGPARAM2 op_1118_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 12; 
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
	m68k_areg(regs, dstreg) = dsta;
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_ce000_prefetch(4);
		if(hardware_bus_error) {
			int pcoffset = 0;
			m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
			ccr_68000_word_move_ae_normal((uae_s16)src);
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return;
		}
		opcode = regs.ir;
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	if(loop_mode & 0xfffe) {
		do_cycles_ce000_internal(loop_mode & 0xfffe);
		loop_mode = 1;
	}
	x_put_byte(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return;
	}
	m68k_incpci(2);
	regs.loop_mode = loop_mode;
	return;
}
/* 12 (2/1) */
/* 2 0,0   */

/* MOVE.B -(An),-(An) */
void REGPARAM2 op_1120_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 14; 
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
	do_cycles_ce000_internal(2);
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	m68k_areg(regs, srcreg) = srca;
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
	m68k_areg(regs, dstreg) = dsta;
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_ce000_prefetch(4);
		if(hardware_bus_error) {
			int pcoffset = 0;
			m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
			ccr_68000_word_move_ae_normal((uae_s16)src);
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return;
		}
		opcode = regs.ir;
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	if(loop_mode & 0xfffe) {
		do_cycles_ce000_internal(loop_mode & 0xfffe);
		loop_mode = 1;
	}
	x_put_byte(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return;
	}
	m68k_incpci(2);
	regs.loop_mode = loop_mode;
	return;
}
/* 14 (2/1) */
/* 2 0,0   */

/* MOVE.B (d16,An),-(An) */
void REGPARAM2 op_1128_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
	m68k_areg(regs, dstreg) = dsta;
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	x_put_byte(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* MOVE.B (d8,An,Xn),-(An) */
void REGPARAM2 op_1130_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	do_cycles_ce000_internal(2);
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
	m68k_areg(regs, dstreg) = dsta;
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	x_put_byte(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 18 (3/1) */
/* 4 4,0   */

/* MOVE.B (xxx).W,-(An) */
void REGPARAM2 op_1138_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
	m68k_areg(regs, dstreg) = dsta;
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	x_put_byte(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* MOVE.B (xxx).L,-(An) */
void REGPARAM2 op_1139_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	srca = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	srca |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
	m68k_areg(regs, dstreg) = dsta;
	regs.ir = regs.irc;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	opcode = regs.ir;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	x_put_byte(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 20 (4/1) */
/* 6 0,0   */

/* MOVE.B (d16,PC),-(An) */
void REGPARAM2 op_113a_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = m68k_getpci() + 2;
	srca += (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 2);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
	m68k_areg(regs, dstreg) = dsta;
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	x_put_byte(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* MOVE.B (d8,PC,Xn),-(An) */
void REGPARAM2 op_113b_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	uaecptr tmppc = m68k_getpci() + 2;
	do_cycles_ce000_internal(2);
	srca = get_disp_ea_000(tmppc, get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 2);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
	m68k_areg(regs, dstreg) = dsta;
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	x_put_byte(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 18 (3/1) */
/* 4 4,0   */

/* MOVE.B #<data>.B,-(An) */
void REGPARAM2 op_113c_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 12; 
	ipl_fetch_now();
	uae_s8 src = (uae_u8)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
	m68k_areg(regs, dstreg) = dsta;
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	struct flag_struct oldflags;
	oldflags.cznv = regflags.cznv;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	x_put_byte(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 12 (2/1) */
/* 4 0,0   */

/* MOVE.B Dn,(d16,An) */
void REGPARAM2 op_1140_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 12; 
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	struct flag_struct oldflags;
	oldflags.cznv = regflags.cznv;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	ipl_fetch_now();
	x_put_byte(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 12 (2/1) */
/* 4 0,0   */

/* MOVE.B (An),(d16,An) */
void REGPARAM2 op_1150_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 4, 0);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	ipl_fetch_now();
	x_put_byte(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* MOVE.B (An)+,(d16,An) */
void REGPARAM2 op_1158_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 4, 0);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	ipl_fetch_now();
	x_put_byte(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* MOVE.B -(An),(d16,An) */
void REGPARAM2 op_1160_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
	do_cycles_ce000_internal(2);
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	m68k_areg(regs, srcreg) = srca;
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 4, 0);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	ipl_fetch_now();
	x_put_byte(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 18 (3/1) */
/* 4 0,0   */

/* MOVE.B (d16,An),(d16,An) */
void REGPARAM2 op_1168_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 6, 0);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	ipl_fetch_now();
	x_put_byte(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return;
	}
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 20 (4/1) */
/* 6 0,0   */

/* MOVE.B (d8,An,Xn),(d16,An) */
void REGPARAM2 op_1170_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 22; 
	uaecptr srca;
	do_cycles_ce000_internal(2);
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 6, 0);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	ipl_fetch_now();
	x_put_byte(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return;
	}
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 22 (4/1) */
/* 6 6,0   */

/* MOVE.B (xxx).W,(d16,An) */
void REGPARAM2 op_1178_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 6, 0);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	ipl_fetch_now();
	x_put_byte(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return;
	}
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 20 (4/1) */
/* 6 0,0   */

/* MOVE.B (xxx).L,(d16,An) */
void REGPARAM2 op_1179_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 24; 
	uaecptr srca;
	srca = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	srca |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 8, 0);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	ipl_fetch_now();
	x_put_byte(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return;
	}
	m68k_incpci(8);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 24 (5/1) */
/* 8 0,0   */

/* MOVE.B (d16,PC),(d16,An) */
void REGPARAM2 op_117a_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	srca = m68k_getpci() + 2;
	srca += (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 2);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 6, 0);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	ipl_fetch_now();
	x_put_byte(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return;
	}
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 20 (4/1) */
/* 6 0,0   */

/* MOVE.B (d8,PC,Xn),(d16,An) */
void REGPARAM2 op_117b_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 22; 
	uaecptr srca;
	uaecptr tmppc = m68k_getpci() + 2;
	do_cycles_ce000_internal(2);
	srca = get_disp_ea_000(tmppc, get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 2);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 6, 0);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	ipl_fetch_now();
	x_put_byte(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return;
	}
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 22 (4/1) */
/* 6 6,0   */

/* MOVE.B #<data>.B,(d16,An) */
void REGPARAM2 op_117c_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 16; 
	uae_s8 src = (uae_u8)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, 0);
		return;
	}
	struct flag_struct oldflags;
	oldflags.cznv = regflags.cznv;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	ipl_fetch_now();
	x_put_byte(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return;
	}
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 16 (3/1) */
/* 6 0,0   */

/* MOVE.B Dn,(d8,An,Xn) */
void REGPARAM2 op_1180_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 14; 
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	do_cycles_ce000_internal(2);
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	struct flag_struct oldflags;
	oldflags.cznv = regflags.cznv;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	ipl_fetch_now();
	x_put_byte(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 14 (2/1) */
/* 4 4,0   */

/* MOVE.B (An),(d8,An,Xn) */
void REGPARAM2 op_1190_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	uaecptr dsta;
	do_cycles_ce000_internal(2);
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 4, 0);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	ipl_fetch_now();
	x_put_byte(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 18 (3/1) */
/* 4 4,0   */

/* MOVE.B (An)+,(d8,An,Xn) */
void REGPARAM2 op_1198_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
	uaecptr dsta;
	do_cycles_ce000_internal(2);
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 4, 0);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	ipl_fetch_now();
	x_put_byte(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 18 (3/1) */
/* 4 4,0   */

/* MOVE.B -(An),(d8,An,Xn) */
void REGPARAM2 op_11a0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
	do_cycles_ce000_internal(2);
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	m68k_areg(regs, srcreg) = srca;
	uaecptr dsta;
	do_cycles_ce000_internal(2);
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 4, 0);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	ipl_fetch_now();
	x_put_byte(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 20 (3/1) */
/* 4 4,0   */

/* MOVE.B (d16,An),(d8,An,Xn) */
void REGPARAM2 op_11a8_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 22; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	uaecptr dsta;
	do_cycles_ce000_internal(2);
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_ce000_prefetch(6));
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 6, 0);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	ipl_fetch_now();
	x_put_byte(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return;
	}
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 22 (4/1) */
/* 6 4,0   */

/* MOVE.B (d8,An,Xn),(d8,An,Xn) */
void REGPARAM2 op_11b0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 24; 
	uaecptr srca;
	do_cycles_ce000_internal(2);
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	uaecptr dsta;
	do_cycles_ce000_internal(2);
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_ce000_prefetch(6));
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 6, 0);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	ipl_fetch_now();
	x_put_byte(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return;
	}
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 24 (4/1) */
/* 6 6,4   */

/* MOVE.B (xxx).W,(d8,An,Xn) */
void REGPARAM2 op_11b8_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 22; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	uaecptr dsta;
	do_cycles_ce000_internal(2);
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_ce000_prefetch(6));
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 6, 0);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	ipl_fetch_now();
	x_put_byte(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return;
	}
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 22 (4/1) */
/* 6 4,0   */

/* MOVE.B (xxx).L,(d8,An,Xn) */
void REGPARAM2 op_11b9_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 26; 
	uaecptr srca;
	srca = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	srca |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	uaecptr dsta;
	do_cycles_ce000_internal(2);
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_ce000_prefetch(8));
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 8, 0);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	ipl_fetch_now();
	x_put_byte(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return;
	}
	m68k_incpci(8);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 26 (5/1) */
/* 8 4,0   */

/* MOVE.B (d16,PC),(d8,An,Xn) */
void REGPARAM2 op_11ba_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 22; 
	uaecptr srca;
	srca = m68k_getpci() + 2;
	srca += (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 2);
		return;
	}
	uaecptr dsta;
	do_cycles_ce000_internal(2);
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_ce000_prefetch(6));
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 6, 0);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	ipl_fetch_now();
	x_put_byte(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return;
	}
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 22 (4/1) */
/* 6 4,0   */

/* MOVE.B (d8,PC,Xn),(d8,An,Xn) */
void REGPARAM2 op_11bb_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 24; 
	uaecptr srca;
	uaecptr tmppc = m68k_getpci() + 2;
	do_cycles_ce000_internal(2);
	srca = get_disp_ea_000(tmppc, get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 2);
		return;
	}
	uaecptr dsta;
	do_cycles_ce000_internal(2);
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_ce000_prefetch(6));
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 6, 0);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	ipl_fetch_now();
	x_put_byte(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return;
	}
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 24 (4/1) */
/* 6 6,4   */

/* MOVE.B #<data>.B,(d8,An,Xn) */
void REGPARAM2 op_11bc_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 18; 
	uae_s8 src = (uae_u8)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr dsta;
	do_cycles_ce000_internal(2);
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_ce000_prefetch(6));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, 0);
		return;
	}
	struct flag_struct oldflags;
	oldflags.cznv = regflags.cznv;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	ipl_fetch_now();
	x_put_byte(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return;
	}
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 18 (3/1) */
/* 6 4,0   */

/* MOVE.B Dn,(xxx).W */
void REGPARAM2 op_11c0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 30;
	CurrentInstrCycles = 12; 
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 4, 0);
		return;
	}
	struct flag_struct oldflags;
	oldflags.cznv = regflags.cznv;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	x_put_byte(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return;
	}
	ipl_fetch_next();
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 12 (2/1) */
/* 4 0,0   */

/* MOVE.B (An),(xxx).W */
void REGPARAM2 op_11d0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 30;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 4, 0);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	x_put_byte(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return;
	}
	ipl_fetch_next();
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* MOVE.B (An)+,(xxx).W */
void REGPARAM2 op_11d8_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 30;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 4, 0);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	x_put_byte(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return;
	}
	ipl_fetch_next();
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* MOVE.B -(An),(xxx).W */
void REGPARAM2 op_11e0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 30;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
	do_cycles_ce000_internal(2);
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	m68k_areg(regs, srcreg) = srca;
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 4, 0);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	x_put_byte(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return;
	}
	ipl_fetch_next();
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 18 (3/1) */
/* 4 0,0   */

/* MOVE.B (d16,An),(xxx).W */
void REGPARAM2 op_11e8_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 30;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 6, 0);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	x_put_byte(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return;
	}
	ipl_fetch_next();
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 20 (4/1) */
/* 6 0,0   */

/* MOVE.B (d8,An,Xn),(xxx).W */
void REGPARAM2 op_11f0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 30;
	CurrentInstrCycles = 22; 
	uaecptr srca;
	do_cycles_ce000_internal(2);
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 6, 0);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	x_put_byte(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return;
	}
	ipl_fetch_next();
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 22 (4/1) */
/* 6 6,0   */

/* MOVE.B (xxx).W,(xxx).W */
void REGPARAM2 op_11f8_13_ff(uae_u32 opcode)
{
	OpcodeFamily = 30;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 6, 0);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	x_put_byte(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return;
	}
	ipl_fetch_next();
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 20 (4/1) */
/* 6 0,0   */

/* MOVE.B (xxx).L,(xxx).W */
void REGPARAM2 op_11f9_13_ff(uae_u32 opcode)
{
	OpcodeFamily = 30;
	CurrentInstrCycles = 24; 
	uaecptr srca;
	srca = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	srca |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 8, 0);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	x_put_byte(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return;
	}
	ipl_fetch_next();
	m68k_incpci(8);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 24 (5/1) */
/* 8 0,0   */

/* MOVE.B (d16,PC),(xxx).W */
void REGPARAM2 op_11fa_13_ff(uae_u32 opcode)
{
	OpcodeFamily = 30;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	srca = m68k_getpci() + 2;
	srca += (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 2);
		return;
	}
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 6, 0);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	x_put_byte(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return;
	}
	ipl_fetch_next();
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 20 (4/1) */
/* 6 0,0   */

/* MOVE.B (d8,PC,Xn),(xxx).W */
void REGPARAM2 op_11fb_13_ff(uae_u32 opcode)
{
	OpcodeFamily = 30;
	CurrentInstrCycles = 22; 
	uaecptr srca;
	uaecptr tmppc = m68k_getpci() + 2;
	do_cycles_ce000_internal(2);
	srca = get_disp_ea_000(tmppc, get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 2);
		return;
	}
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 6, 0);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	x_put_byte(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return;
	}
	ipl_fetch_next();
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 22 (4/1) */
/* 6 6,0   */

/* MOVE.B #<data>.B,(xxx).W */
void REGPARAM2 op_11fc_13_ff(uae_u32 opcode)
{
	OpcodeFamily = 30;
	CurrentInstrCycles = 16; 
	uae_s8 src = (uae_u8)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 6, 0);
		return;
	}
	struct flag_struct oldflags;
	oldflags.cznv = regflags.cznv;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	x_put_byte(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return;
	}
	ipl_fetch_next();
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 16 (3/1) */
/* 6 0,0   */

/* MOVE.B Dn,(xxx).L */
void REGPARAM2 op_13c0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 30;
	CurrentInstrCycles = 16; 
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	dsta |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	struct flag_struct oldflags;
	oldflags.cznv = regflags.cznv;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	x_put_byte(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return;
	}
	ipl_fetch_next();
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 16 (3/1) */
/* 6 0,0   */

/* MOVE.B (An),(xxx).L */
void REGPARAM2 op_13d0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 30;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	uaecptr dsta;
	dsta = get_word_ce000_prefetch(4) << 16;
	dsta |= regs.irc;
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 4, 0);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	x_put_byte(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		regs.irc = dsta >> 16;
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return;
	}
	ipl_fetch_now();
	m68k_incpci(6);
	get_word_ce000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, 0);
		return;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 20 (4/1) */
/* 6 0,0   */

/* MOVE.B (An)+,(xxx).L */
void REGPARAM2 op_13d8_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 30;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
	uaecptr dsta;
	dsta = get_word_ce000_prefetch(4) << 16;
	dsta |= regs.irc;
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 4, 0);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	x_put_byte(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		regs.irc = dsta >> 16;
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return;
	}
	ipl_fetch_now();
	m68k_incpci(6);
	get_word_ce000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, 0);
		return;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 20 (4/1) */
/* 6 0,0   */

/* MOVE.B -(An),(xxx).L */
void REGPARAM2 op_13e0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 30;
	CurrentInstrCycles = 22; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
	do_cycles_ce000_internal(2);
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	m68k_areg(regs, srcreg) = srca;
	uaecptr dsta;
	dsta = get_word_ce000_prefetch(4) << 16;
	dsta |= regs.irc;
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 4, 0);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	x_put_byte(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		regs.irc = dsta >> 16;
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return;
	}
	ipl_fetch_now();
	m68k_incpci(6);
	get_word_ce000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, 0);
		return;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 22 (4/1) */
/* 6 0,0   */

/* MOVE.B (d16,An),(xxx).L */
void REGPARAM2 op_13e8_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 30;
	CurrentInstrCycles = 24; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	uaecptr dsta;
	dsta = get_word_ce000_prefetch(6) << 16;
	dsta |= regs.irc;
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 6, 0);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	x_put_byte(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		regs.irc = dsta >> 16;
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return;
	}
	ipl_fetch_now();
	m68k_incpci(8);
	get_word_ce000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, 0);
		return;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 24 (5/1) */
/* 8 0,0   */

/* MOVE.B (d8,An,Xn),(xxx).L */
void REGPARAM2 op_13f0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 30;
	CurrentInstrCycles = 26; 
	uaecptr srca;
	do_cycles_ce000_internal(2);
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	uaecptr dsta;
	dsta = get_word_ce000_prefetch(6) << 16;
	dsta |= regs.irc;
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 6, 0);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	x_put_byte(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		regs.irc = dsta >> 16;
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return;
	}
	ipl_fetch_now();
	m68k_incpci(8);
	get_word_ce000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, 0);
		return;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 26 (5/1) */
/* 8 8,0   */

/* MOVE.B (xxx).W,(xxx).L */
void REGPARAM2 op_13f8_13_ff(uae_u32 opcode)
{
	OpcodeFamily = 30;
	CurrentInstrCycles = 24; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	uaecptr dsta;
	dsta = get_word_ce000_prefetch(6) << 16;
	dsta |= regs.irc;
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 6, 0);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	x_put_byte(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		regs.irc = dsta >> 16;
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return;
	}
	ipl_fetch_now();
	m68k_incpci(8);
	get_word_ce000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, 0);
		return;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 24 (5/1) */
/* 8 0,0   */

/* MOVE.B (xxx).L,(xxx).L */
void REGPARAM2 op_13f9_13_ff(uae_u32 opcode)
{
	OpcodeFamily = 30;
	CurrentInstrCycles = 28; 
	uaecptr srca;
	srca = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	srca |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	uaecptr dsta;
	dsta = get_word_ce000_prefetch(8) << 16;
	dsta |= regs.irc;
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 8, 0);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	x_put_byte(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		regs.irc = dsta >> 16;
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return;
	}
	ipl_fetch_now();
	m68k_incpci(10);
	get_word_ce000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, 0);
		return;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 28 (6/1) */
/* 10 0,0   */

/* MOVE.B (d16,PC),(xxx).L */
void REGPARAM2 op_13fa_13_ff(uae_u32 opcode)
{
	OpcodeFamily = 30;
	CurrentInstrCycles = 24; 
	uaecptr srca;
	srca = m68k_getpci() + 2;
	srca += (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 2);
		return;
	}
	uaecptr dsta;
	dsta = get_word_ce000_prefetch(6) << 16;
	dsta |= regs.irc;
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 6, 0);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	x_put_byte(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		regs.irc = dsta >> 16;
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return;
	}
	ipl_fetch_now();
	m68k_incpci(8);
	get_word_ce000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, 0);
		return;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 24 (5/1) */
/* 8 0,0   */

/* MOVE.B (d8,PC,Xn),(xxx).L */
void REGPARAM2 op_13fb_13_ff(uae_u32 opcode)
{
	OpcodeFamily = 30;
	CurrentInstrCycles = 26; 
	uaecptr srca;
	uaecptr tmppc = m68k_getpci() + 2;
	do_cycles_ce000_internal(2);
	srca = get_disp_ea_000(tmppc, get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 2);
		return;
	}
	uaecptr dsta;
	dsta = get_word_ce000_prefetch(6) << 16;
	dsta |= regs.irc;
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 6, 0);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	x_put_byte(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		regs.irc = dsta >> 16;
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return;
	}
	ipl_fetch_now();
	m68k_incpci(8);
	get_word_ce000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, 0);
		return;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 26 (5/1) */
/* 8 8,0   */

/* MOVE.B #<data>.B,(xxx).L */
void REGPARAM2 op_13fc_13_ff(uae_u32 opcode)
{
	OpcodeFamily = 30;
	CurrentInstrCycles = 20; 
	uae_s8 src = (uae_u8)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr dsta;
	dsta = get_word_ce000_prefetch(6) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return;
	}
	dsta |= get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 8, pcoffset);
		return;
	}
	struct flag_struct oldflags;
	oldflags.cznv = regflags.cznv;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	x_put_byte(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return;
	}
	ipl_fetch_next();
	m68k_incpci(8);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 20 (4/1) */
/* 8 0,0   */

/* MOVE.L Dn,Dn */
void REGPARAM2 op_2000_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 4;  
	uae_s32 src = m68k_dreg(regs, srcreg);
	struct flag_struct oldflags;
	oldflags.cznv = regflags.cznv;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	m68k_dreg(regs, dstreg) = (src);
	m68k_incpci(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 4 (1/0) */
/* 2 0,0   */

/* MOVE.L An,Dn */
void REGPARAM2 op_2008_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 4;  
	uae_s32 src = m68k_areg(regs, srcreg);
	struct flag_struct oldflags;
	oldflags.cznv = regflags.cznv;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	m68k_dreg(regs, dstreg) = (src);
	m68k_incpci(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 4 (1/0) */
/* 2 0,0   */

/* MOVE.L (An),Dn */
void REGPARAM2 op_2010_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	m68k_dreg(regs, dstreg) = (src);
	m68k_incpci(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 12 (3/0) */
/* 2 0,0   */

/* MOVE.L (An)+,Dn */
void REGPARAM2 op_2018_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	m68k_areg(regs, srcreg) += 4;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	m68k_dreg(regs, dstreg) = (src);
	m68k_incpci(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 12 (3/0) */
/* 2 0,0   */

/* MOVE.L -(An),Dn */
void REGPARAM2 op_2020_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - 4;
	do_cycles_ce000_internal(2);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	m68k_areg(regs, srcreg) = srca;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	m68k_dreg(regs, dstreg) = (src);
	m68k_incpci(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 14 (3/0) */
/* 2 0,0   */

/* MOVE.L (d16,An),Dn */
void REGPARAM2 op_2028_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	m68k_dreg(regs, dstreg) = (src);
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 16 (4/0) */
/* 4 0,0   */

/* MOVE.L (d8,An,Xn),Dn */
void REGPARAM2 op_2030_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	do_cycles_ce000_internal(2);
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	m68k_dreg(regs, dstreg) = (src);
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 18 (4/0) */
/* 4 4,0   */

/* MOVE.L (xxx).W,Dn */
void REGPARAM2 op_2038_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	if (srca & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	m68k_dreg(regs, dstreg) = (src);
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 16 (4/0) */
/* 4 0,0   */

/* MOVE.L (xxx).L,Dn */
void REGPARAM2 op_2039_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	srca = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	srca |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	if (srca & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	m68k_dreg(regs, dstreg) = (src);
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 20 (5/0) */
/* 6 0,0   */

/* MOVE.L (d16,PC),Dn */
void REGPARAM2 op_203a_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = m68k_getpci() + 2;
	srca += (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 2);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return;
	}
	ipl_fetch_now();
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 2);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	m68k_dreg(regs, dstreg) = (src);
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 16 (4/0) */
/* 4 0,0   */

/* MOVE.L (d8,PC,Xn),Dn */
void REGPARAM2 op_203b_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	uaecptr tmppc = m68k_getpci() + 2;
	do_cycles_ce000_internal(2);
	srca = get_disp_ea_000(tmppc, get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 2);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return;
	}
	ipl_fetch_now();
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 2);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	m68k_dreg(regs, dstreg) = (src);
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 18 (4/0) */
/* 4 4,0   */

/* MOVE.L #<data>.L,Dn */
void REGPARAM2 op_203c_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 12; 
	uae_s32 src;
	src = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	src |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	struct flag_struct oldflags;
	oldflags.cznv = regflags.cznv;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	m68k_dreg(regs, dstreg) = (src);
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 12 (3/0) */
/* 6 0,0   */

/* MOVEA.L Dn,An */
void REGPARAM2 op_2040_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 31;
	CurrentInstrCycles = 4;  
	uae_s32 src = m68k_dreg(regs, srcreg);
	m68k_areg(regs, dstreg) = (src);
	m68k_incpci(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 4 (1/0) */
/* 2 0,0   */

/* MOVEA.L An,An */
void REGPARAM2 op_2048_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 31;
	CurrentInstrCycles = 4;  
	uae_s32 src = m68k_areg(regs, srcreg);
	m68k_areg(regs, dstreg) = (src);
	m68k_incpci(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 4 (1/0) */
/* 2 0,0   */

/* MOVEA.L (An),An */
void REGPARAM2 op_2050_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 31;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	m68k_areg(regs, dstreg) = (src);
	m68k_incpci(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 12 (3/0) */
/* 2 0,0   */

/* MOVEA.L (An)+,An */
void REGPARAM2 op_2058_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 31;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	m68k_areg(regs, srcreg) += 4;
	m68k_areg(regs, dstreg) = (src);
	m68k_incpci(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 12 (3/0) */
/* 2 0,0   */

/* MOVEA.L -(An),An */
void REGPARAM2 op_2060_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 31;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - 4;
	do_cycles_ce000_internal(2);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	m68k_areg(regs, srcreg) = srca;
	m68k_areg(regs, dstreg) = (src);
	m68k_incpci(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 14 (3/0) */
/* 2 0,0   */

/* MOVEA.L (d16,An),An */
void REGPARAM2 op_2068_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 31;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	m68k_areg(regs, dstreg) = (src);
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 16 (4/0) */
/* 4 0,0   */

/* MOVEA.L (d8,An,Xn),An */
void REGPARAM2 op_2070_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 31;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	do_cycles_ce000_internal(2);
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	m68k_areg(regs, dstreg) = (src);
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 18 (4/0) */
/* 4 4,0   */

/* MOVEA.L (xxx).W,An */
void REGPARAM2 op_2078_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 31;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	if (srca & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	m68k_areg(regs, dstreg) = (src);
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 16 (4/0) */
/* 4 0,0   */

/* MOVEA.L (xxx).L,An */
void REGPARAM2 op_2079_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 31;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	srca = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	srca |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	if (srca & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	m68k_areg(regs, dstreg) = (src);
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 20 (5/0) */
/* 6 0,0   */

/* MOVEA.L (d16,PC),An */
void REGPARAM2 op_207a_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 31;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = m68k_getpci() + 2;
	srca += (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 2);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return;
	}
	ipl_fetch_now();
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 2);
		return;
	}
	m68k_areg(regs, dstreg) = (src);
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 16 (4/0) */
/* 4 0,0   */

/* MOVEA.L (d8,PC,Xn),An */
void REGPARAM2 op_207b_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 31;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	uaecptr tmppc = m68k_getpci() + 2;
	do_cycles_ce000_internal(2);
	srca = get_disp_ea_000(tmppc, get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 2);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return;
	}
	ipl_fetch_now();
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 2);
		return;
	}
	m68k_areg(regs, dstreg) = (src);
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 18 (4/0) */
/* 4 4,0   */

/* MOVEA.L #<data>.L,An */
void REGPARAM2 op_207c_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 31;
	CurrentInstrCycles = 12; 
	uae_s32 src;
	src = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	src |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	m68k_areg(regs, dstreg) = (src);
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 12 (3/0) */
/* 6 0,0   */

/* MOVE.L Dn,(An) */
void REGPARAM2 op_2080_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 12; 
	int loop_mode = regs.loop_mode;
	uae_s32 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	struct flag_struct oldflags;
	oldflags.cznv = regflags.cznv;
	if (dsta & 1) {
		m68k_incpci(4);
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return;
	}
	ipl_fetch_now();
	x_put_word(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	x_put_word(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		ccr_68000_long_move_ae_LZN(src);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return;
	}
	m68k_incpci(2);
	if(!loop_mode) {
		regs.ir = regs.irc;
		opcode = regs.ir;
		get_word_ce000_prefetch(2);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 2, pcoffset);
			return;
		}
	} else {
		loop_mode = 0;
		loop_mode |= 2;
		loop_mode |= 4 << 16;
	}
	regs.loop_mode = loop_mode;
	return;
}
/* 12 (1/2) */
/* 2 0,0   */

/* MOVE.L An,(An) */
void REGPARAM2 op_2088_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 12; 
	int loop_mode = regs.loop_mode;
	uae_s32 src = m68k_areg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	struct flag_struct oldflags;
	oldflags.cznv = regflags.cznv;
	if (dsta & 1) {
		m68k_incpci(4);
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return;
	}
	ipl_fetch_now();
	x_put_word(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	x_put_word(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		ccr_68000_long_move_ae_LZN(src);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return;
	}
	m68k_incpci(2);
	if(!loop_mode) {
		regs.ir = regs.irc;
		opcode = regs.ir;
		get_word_ce000_prefetch(2);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 2, pcoffset);
			return;
		}
	} else {
		loop_mode = 0;
		loop_mode |= 2;
		loop_mode |= 4 << 16;
	}
	regs.loop_mode = loop_mode;
	return;
}
/* 12 (1/2) */
/* 2 0,0   */

/* MOVE.L (An),(An) */
void REGPARAM2 op_2090_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 20; 
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	if (dsta & 1) {
		m68k_incpci(4);
		ccr_68000_long_move_ae_LZN(src);
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return;
	}
	x_put_word(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		ccr_68000_long_move_ae_LZN(src);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	ipl_fetch_now();
	x_put_word(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return;
	}
	m68k_incpci(2);
	if(!loop_mode) {
		regs.ir = regs.irc;
		opcode = regs.ir;
		get_word_ce000_prefetch(2);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 2, pcoffset);
			return;
		}
	} else {
		loop_mode = 0;
		loop_mode |= 2;
		loop_mode |= 2 << 16;
	}
	regs.loop_mode = loop_mode;
	return;
}
/* 20 (3/2) */
/* 2 0,0   */

/* MOVE.L (An)+,(An) */
void REGPARAM2 op_2098_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 20; 
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	m68k_areg(regs, srcreg) += 4;
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	if (dsta & 1) {
		m68k_incpci(4);
		ccr_68000_long_move_ae_LZN(src);
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return;
	}
	x_put_word(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		ccr_68000_long_move_ae_LZN(src);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	ipl_fetch_now();
	x_put_word(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return;
	}
	m68k_incpci(2);
	if(!loop_mode) {
		regs.ir = regs.irc;
		opcode = regs.ir;
		get_word_ce000_prefetch(2);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 2, pcoffset);
			return;
		}
	} else {
		loop_mode = 0;
		loop_mode |= 2;
		loop_mode |= 2 << 16;
	}
	regs.loop_mode = loop_mode;
	return;
}
/* 20 (3/2) */
/* 2 0,0   */

/* MOVE.L -(An),(An) */
void REGPARAM2 op_20a0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 22; 
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - 4;
	do_cycles_ce000_internal(2);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	m68k_areg(regs, srcreg) = srca;
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	if (dsta & 1) {
		m68k_incpci(4);
		ccr_68000_long_move_ae_LZN(src);
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return;
	}
	x_put_word(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		ccr_68000_long_move_ae_LZN(src);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	ipl_fetch_now();
	x_put_word(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return;
	}
	m68k_incpci(2);
	if(!loop_mode) {
		regs.ir = regs.irc;
		opcode = regs.ir;
		get_word_ce000_prefetch(2);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 2, pcoffset);
			return;
		}
	} else {
		loop_mode = 0;
		loop_mode |= 2;
		loop_mode |= 2 << 16;
	}
	regs.loop_mode = loop_mode;
	return;
}
/* 22 (3/2) */
/* 2 0,0   */

/* MOVE.L (d16,An),(An) */
void REGPARAM2 op_20a8_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 24; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	if (dsta & 1) {
		m68k_incpci(6);
		ccr_68000_long_move_ae_LZN(src);
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return;
	}
	x_put_word(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		ccr_68000_long_move_ae_LZN(src);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	ipl_fetch_now();
	x_put_word(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 24 (4/2) */
/* 4 0,0   */

/* MOVE.L (d8,An,Xn),(An) */
void REGPARAM2 op_20b0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 26; 
	uaecptr srca;
	do_cycles_ce000_internal(2);
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	if (dsta & 1) {
		m68k_incpci(6);
		ccr_68000_long_move_ae_LZN(src);
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return;
	}
	x_put_word(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		ccr_68000_long_move_ae_LZN(src);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	ipl_fetch_now();
	x_put_word(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 26 (4/2) */
/* 4 4,0   */

/* MOVE.L (xxx).W,(An) */
void REGPARAM2 op_20b8_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 24; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	if (srca & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	if (dsta & 1) {
		m68k_incpci(6);
		ccr_68000_long_move_ae_LZN(src);
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return;
	}
	x_put_word(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		ccr_68000_long_move_ae_LZN(src);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	ipl_fetch_now();
	x_put_word(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 24 (4/2) */
/* 4 0,0   */

/* MOVE.L (xxx).L,(An) */
void REGPARAM2 op_20b9_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 28; 
	uaecptr srca;
	srca = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	srca |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	if (srca & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	if (dsta & 1) {
		m68k_incpci(8);
		ccr_68000_long_move_ae_LZN(src);
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return;
	}
	x_put_word(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		ccr_68000_long_move_ae_LZN(src);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	x_put_word(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return;
	}
	ipl_fetch_next();
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 28 (5/2) */
/* 6 0,0   */

/* MOVE.L (d16,PC),(An) */
void REGPARAM2 op_20ba_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 24; 
	uaecptr srca;
	srca = m68k_getpci() + 2;
	srca += (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 2);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return;
	}
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 2);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	if (dsta & 1) {
		m68k_incpci(6);
		ccr_68000_long_move_ae_LZN(src);
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return;
	}
	x_put_word(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		ccr_68000_long_move_ae_LZN(src);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	ipl_fetch_now();
	x_put_word(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 24 (4/2) */
/* 4 0,0   */

/* MOVE.L (d8,PC,Xn),(An) */
void REGPARAM2 op_20bb_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 26; 
	uaecptr srca;
	uaecptr tmppc = m68k_getpci() + 2;
	do_cycles_ce000_internal(2);
	srca = get_disp_ea_000(tmppc, get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 2);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return;
	}
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 2);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	if (dsta & 1) {
		m68k_incpci(6);
		ccr_68000_long_move_ae_LZN(src);
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return;
	}
	x_put_word(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		ccr_68000_long_move_ae_LZN(src);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	ipl_fetch_now();
	x_put_word(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 26 (4/2) */
/* 4 4,0   */

/* MOVE.L #<data>.L,(An) */
void REGPARAM2 op_20bc_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 20; 
	uae_s32 src;
	src = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	src |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	struct flag_struct oldflags;
	oldflags.cznv = regflags.cznv;
	ipl_fetch_now();
	if (dsta & 1) {
		m68k_incpci(8);
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return;
	}
	x_put_word(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	x_put_word(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		ccr_68000_long_move_ae_LZN(src);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return;
	}
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 20 (3/2) */
/* 6 0,0   */

/* MOVE.L Dn,(An)+ */
void REGPARAM2 op_20c0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 12; 
	int loop_mode = regs.loop_mode;
	uae_s32 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	m68k_areg(regs, dstreg) += 4;
	struct flag_struct oldflags;
	oldflags.cznv = regflags.cznv;
	if (dsta & 1) {
		m68k_incpci(4);
		m68k_areg(regs, dstreg) = dsta;
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return;
	}
	ipl_fetch_now();
	x_put_word(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, dstreg) -= 4;
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	x_put_word(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		ccr_68000_long_move_ae_LZN(src);
		m68k_areg(regs, dstreg) -= 4;
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return;
	}
	m68k_incpci(2);
	if(!loop_mode) {
		regs.ir = regs.irc;
		opcode = regs.ir;
		get_word_ce000_prefetch(2);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 2, pcoffset);
			return;
		}
	} else {
		loop_mode = 0;
		loop_mode |= 2;
		loop_mode |= 4 << 16;
	}
	regs.loop_mode = loop_mode;
	return;
}
/* 12 (1/2) */
/* 2 0,0   */

/* MOVE.L An,(An)+ */
void REGPARAM2 op_20c8_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 12; 
	int loop_mode = regs.loop_mode;
	uae_s32 src = m68k_areg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	m68k_areg(regs, dstreg) += 4;
	struct flag_struct oldflags;
	oldflags.cznv = regflags.cznv;
	if (dsta & 1) {
		m68k_incpci(4);
		m68k_areg(regs, dstreg) = dsta;
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return;
	}
	ipl_fetch_now();
	x_put_word(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, dstreg) -= 4;
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	x_put_word(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		ccr_68000_long_move_ae_LZN(src);
		m68k_areg(regs, dstreg) -= 4;
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return;
	}
	m68k_incpci(2);
	if(!loop_mode) {
		regs.ir = regs.irc;
		opcode = regs.ir;
		get_word_ce000_prefetch(2);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 2, pcoffset);
			return;
		}
	} else {
		loop_mode = 0;
		loop_mode |= 2;
		loop_mode |= 4 << 16;
	}
	regs.loop_mode = loop_mode;
	return;
}
/* 12 (1/2) */
/* 2 0,0   */

/* MOVE.L (An),(An)+ */
void REGPARAM2 op_20d0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 20; 
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	m68k_areg(regs, dstreg) += 4;
	ipl_fetch_now();
	if (dsta & 1) {
		m68k_incpci(4);
		ccr_68000_long_move_ae_LZN(src);
		m68k_areg(regs, dstreg) = dsta;
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return;
	}
	x_put_word(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		ccr_68000_long_move_ae_LZN(src);
		m68k_areg(regs, dstreg) -= 4;
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	x_put_word(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		ccr_68000_long_move_ae_normal(src);
		m68k_areg(regs, dstreg) -= 4;
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return;
	}
	m68k_incpci(2);
	if(!loop_mode) {
		regs.ir = regs.irc;
		opcode = regs.ir;
		get_word_ce000_prefetch(2);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 2, pcoffset);
			return;
		}
	} else {
		loop_mode = 0;
		loop_mode |= 2;
		loop_mode |= 2 << 16;
	}
	regs.loop_mode = loop_mode;
	return;
}
/* 20 (3/2) */
/* 2 0,0   */

/* MOVE.L (An)+,(An)+ */
void REGPARAM2 op_20d8_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 20; 
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	m68k_areg(regs, srcreg) += 4;
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	m68k_areg(regs, dstreg) += 4;
	ipl_fetch_now();
	if (dsta & 1) {
		m68k_incpci(4);
		ccr_68000_long_move_ae_LZN(src);
		m68k_areg(regs, dstreg) = dsta;
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return;
	}
	x_put_word(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		ccr_68000_long_move_ae_LZN(src);
		m68k_areg(regs, dstreg) -= 4;
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	x_put_word(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		ccr_68000_long_move_ae_normal(src);
		m68k_areg(regs, dstreg) -= 4;
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return;
	}
	m68k_incpci(2);
	if(!loop_mode) {
		regs.ir = regs.irc;
		opcode = regs.ir;
		get_word_ce000_prefetch(2);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 2, pcoffset);
			return;
		}
	} else {
		loop_mode = 0;
		loop_mode |= 2;
		loop_mode |= 2 << 16;
	}
	regs.loop_mode = loop_mode;
	return;
}
/* 20 (3/2) */
/* 2 0,0   */

/* MOVE.L -(An),(An)+ */
void REGPARAM2 op_20e0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 22; 
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - 4;
	do_cycles_ce000_internal(2);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	m68k_areg(regs, srcreg) = srca;
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	m68k_areg(regs, dstreg) += 4;
	ipl_fetch_now();
	if (dsta & 1) {
		m68k_incpci(4);
		ccr_68000_long_move_ae_LZN(src);
		m68k_areg(regs, dstreg) = dsta;
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return;
	}
	x_put_word(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		ccr_68000_long_move_ae_LZN(src);
		m68k_areg(regs, dstreg) -= 4;
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	x_put_word(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		ccr_68000_long_move_ae_normal(src);
		m68k_areg(regs, dstreg) -= 4;
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return;
	}
	m68k_incpci(2);
	if(!loop_mode) {
		regs.ir = regs.irc;
		opcode = regs.ir;
		get_word_ce000_prefetch(2);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 2, pcoffset);
			return;
		}
	} else {
		loop_mode = 0;
		loop_mode |= 2;
		loop_mode |= 2 << 16;
	}
	regs.loop_mode = loop_mode;
	return;
}
/* 22 (3/2) */
/* 2 0,0   */

/* MOVE.L (d16,An),(An)+ */
void REGPARAM2 op_20e8_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 24; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	m68k_areg(regs, dstreg) += 4;
	ipl_fetch_now();
	if (dsta & 1) {
		m68k_incpci(6);
		ccr_68000_long_move_ae_LZN(src);
		m68k_areg(regs, dstreg) = dsta;
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return;
	}
	x_put_word(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		ccr_68000_long_move_ae_LZN(src);
		m68k_areg(regs, dstreg) -= 4;
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	x_put_word(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		ccr_68000_long_move_ae_normal(src);
		m68k_areg(regs, dstreg) -= 4;
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 24 (4/2) */
/* 4 0,0   */

/* MOVE.L (d8,An,Xn),(An)+ */
void REGPARAM2 op_20f0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 26; 
	uaecptr srca;
	do_cycles_ce000_internal(2);
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	m68k_areg(regs, dstreg) += 4;
	ipl_fetch_now();
	if (dsta & 1) {
		m68k_incpci(6);
		ccr_68000_long_move_ae_LZN(src);
		m68k_areg(regs, dstreg) = dsta;
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return;
	}
	x_put_word(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		ccr_68000_long_move_ae_LZN(src);
		m68k_areg(regs, dstreg) -= 4;
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	x_put_word(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		ccr_68000_long_move_ae_normal(src);
		m68k_areg(regs, dstreg) -= 4;
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 26 (4/2) */
/* 4 4,0   */

/* MOVE.L (xxx).W,(An)+ */
void REGPARAM2 op_20f8_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 24; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	if (srca & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	m68k_areg(regs, dstreg) += 4;
	ipl_fetch_now();
	if (dsta & 1) {
		m68k_incpci(6);
		ccr_68000_long_move_ae_LZN(src);
		m68k_areg(regs, dstreg) = dsta;
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return;
	}
	x_put_word(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		ccr_68000_long_move_ae_LZN(src);
		m68k_areg(regs, dstreg) -= 4;
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	x_put_word(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		ccr_68000_long_move_ae_normal(src);
		m68k_areg(regs, dstreg) -= 4;
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 24 (4/2) */
/* 4 0,0   */

/* MOVE.L (xxx).L,(An)+ */
void REGPARAM2 op_20f9_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 28; 
	uaecptr srca;
	srca = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	srca |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	if (srca & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	m68k_areg(regs, dstreg) += 4;
	ipl_fetch_now();
	if (dsta & 1) {
		m68k_incpci(8);
		ccr_68000_long_move_ae_LZN(src);
		m68k_areg(regs, dstreg) = dsta;
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return;
	}
	x_put_word(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		ccr_68000_long_move_ae_LZN(src);
		m68k_areg(regs, dstreg) -= 4;
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	x_put_word(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		ccr_68000_long_move_ae_normal(src);
		m68k_areg(regs, dstreg) -= 4;
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return;
	}
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 28 (5/2) */
/* 6 0,0   */

/* MOVE.L (d16,PC),(An)+ */
void REGPARAM2 op_20fa_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 24; 
	uaecptr srca;
	srca = m68k_getpci() + 2;
	srca += (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 2);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return;
	}
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 2);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	m68k_areg(regs, dstreg) += 4;
	ipl_fetch_now();
	if (dsta & 1) {
		m68k_incpci(6);
		ccr_68000_long_move_ae_LZN(src);
		m68k_areg(regs, dstreg) = dsta;
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return;
	}
	x_put_word(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		ccr_68000_long_move_ae_LZN(src);
		m68k_areg(regs, dstreg) -= 4;
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	x_put_word(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		ccr_68000_long_move_ae_normal(src);
		m68k_areg(regs, dstreg) -= 4;
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 24 (4/2) */
/* 4 0,0   */

/* MOVE.L (d8,PC,Xn),(An)+ */
void REGPARAM2 op_20fb_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 26; 
	uaecptr srca;
	uaecptr tmppc = m68k_getpci() + 2;
	do_cycles_ce000_internal(2);
	srca = get_disp_ea_000(tmppc, get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 2);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return;
	}
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 2);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	m68k_areg(regs, dstreg) += 4;
	ipl_fetch_now();
	if (dsta & 1) {
		m68k_incpci(6);
		ccr_68000_long_move_ae_LZN(src);
		m68k_areg(regs, dstreg) = dsta;
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return;
	}
	x_put_word(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		ccr_68000_long_move_ae_LZN(src);
		m68k_areg(regs, dstreg) -= 4;
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	x_put_word(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		ccr_68000_long_move_ae_normal(src);
		m68k_areg(regs, dstreg) -= 4;
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 26 (4/2) */
/* 4 4,0   */

/* MOVE.L #<data>.L,(An)+ */
void REGPARAM2 op_20fc_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 20; 
	uae_s32 src;
	src = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	src |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	m68k_areg(regs, dstreg) += 4;
	struct flag_struct oldflags;
	oldflags.cznv = regflags.cznv;
	ipl_fetch_now();
	if (dsta & 1) {
		m68k_incpci(8);
		m68k_areg(regs, dstreg) = dsta;
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return;
	}
	x_put_word(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		m68k_areg(regs, dstreg) -= 4;
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	x_put_word(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		ccr_68000_long_move_ae_LZN(src);
		m68k_areg(regs, dstreg) -= 4;
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return;
	}
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 20 (3/2) */
/* 6 0,0   */

/* MOVE.L Dn,-(An) */
void REGPARAM2 op_2100_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 14; 
	ipl_fetch_next_pre();
	uae_s32 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - 4;
	m68k_areg(regs, dstreg) = dsta;
	regs.ir = regs.irc;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		m68k_areg(regs, dstreg) += 4;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	do_cycles_ce000_internal(2);
	struct flag_struct oldflags;
	oldflags.cznv = regflags.cznv;
	if (dsta & 1) {
		m68k_incpci(4);
		ccr_68000_long_move_ae_normal(src);
		m68k_areg(regs, dstreg) = dsta + 4;
		dsta += 2;
		exception3_write_access(opcode, dsta, 2, src, 1);
		return;
	}
	x_put_word(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		ccr_68000_long_move_ae_normal(src);
		m68k_areg(regs, dstreg) += 4;
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	x_put_word(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		ccr_68000_long_move_ae_normal(src);
		m68k_areg(regs, dstreg) += 4;
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 14 (1/2) */
/* 2 0,0   */

/* MOVE.L An,-(An) */
void REGPARAM2 op_2108_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 14; 
	ipl_fetch_next_pre();
	uae_s32 src = m68k_areg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - 4;
	m68k_areg(regs, dstreg) = dsta;
	regs.ir = regs.irc;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		m68k_areg(regs, dstreg) += 4;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	do_cycles_ce000_internal(2);
	struct flag_struct oldflags;
	oldflags.cznv = regflags.cznv;
	if (dsta & 1) {
		m68k_incpci(4);
		ccr_68000_long_move_ae_normal(src);
		m68k_areg(regs, dstreg) = dsta + 4;
		dsta += 2;
		exception3_write_access(opcode, dsta, 2, src, 1);
		return;
	}
	x_put_word(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		ccr_68000_long_move_ae_normal(src);
		m68k_areg(regs, dstreg) += 4;
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	x_put_word(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		ccr_68000_long_move_ae_normal(src);
		m68k_areg(regs, dstreg) += 4;
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 14 (1/2) */
/* 2 0,0   */

/* MOVE.L (An),-(An) */
void REGPARAM2 op_2110_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 20; 
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - 4;
	m68k_areg(regs, dstreg) = dsta;
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_ce000_prefetch(4);
		if(hardware_bus_error) {
			int pcoffset = 0;
			m68k_areg(regs, dstreg) += 4;
			ccr_68000_long_move_ae_LZN(src);
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return;
		}
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	if(loop_mode & 0xfffe) {
		do_cycles_ce000_internal(loop_mode & 0xfffe);
		loop_mode = 1;
	}
	if (dsta & 1) {
		m68k_incpci(4);
		ccr_68000_long_move_ae_normal(src);
		m68k_areg(regs, dstreg) = dsta + 4;
		dsta += 2;
		exception3_write_access(opcode, dsta, 2, src, 1);
		return;
	}
	x_put_word(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		ccr_68000_long_move_ae_normal(src);
		m68k_areg(regs, dstreg) += 4;
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	x_put_word(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		ccr_68000_long_move_ae_normal(src);
		m68k_areg(regs, dstreg) += 4;
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return;
	}
	m68k_incpci(2);
	regs.loop_mode = loop_mode;
	return;
}
/* 20 (3/2) */
/* 2 0,0   */

/* MOVE.L (An)+,-(An) */
void REGPARAM2 op_2118_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 20; 
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	m68k_areg(regs, srcreg) += 4;
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - 4;
	m68k_areg(regs, dstreg) = dsta;
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_ce000_prefetch(4);
		if(hardware_bus_error) {
			int pcoffset = 0;
			m68k_areg(regs, dstreg) += 4;
			ccr_68000_long_move_ae_LZN(src);
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return;
		}
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	if(loop_mode & 0xfffe) {
		do_cycles_ce000_internal(loop_mode & 0xfffe);
		loop_mode = 1;
	}
	if (dsta & 1) {
		m68k_incpci(4);
		ccr_68000_long_move_ae_normal(src);
		m68k_areg(regs, dstreg) = dsta + 4;
		dsta += 2;
		exception3_write_access(opcode, dsta, 2, src, 1);
		return;
	}
	x_put_word(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		ccr_68000_long_move_ae_normal(src);
		m68k_areg(regs, dstreg) += 4;
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	x_put_word(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		ccr_68000_long_move_ae_normal(src);
		m68k_areg(regs, dstreg) += 4;
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return;
	}
	m68k_incpci(2);
	regs.loop_mode = loop_mode;
	return;
}
/* 20 (3/2) */
/* 2 0,0   */

/* MOVE.L -(An),-(An) */
void REGPARAM2 op_2120_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 22; 
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - 4;
	do_cycles_ce000_internal(2);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	m68k_areg(regs, srcreg) = srca;
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - 4;
	m68k_areg(regs, dstreg) = dsta;
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_ce000_prefetch(4);
		if(hardware_bus_error) {
			int pcoffset = 0;
			m68k_areg(regs, dstreg) += 4;
			ccr_68000_long_move_ae_LZN(src);
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return;
		}
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	if(loop_mode & 0xfffe) {
		do_cycles_ce000_internal(loop_mode & 0xfffe);
		loop_mode = 1;
	}
	if (dsta & 1) {
		m68k_incpci(4);
		ccr_68000_long_move_ae_normal(src);
		m68k_areg(regs, dstreg) = dsta + 4;
		dsta += 2;
		exception3_write_access(opcode, dsta, 2, src, 1);
		return;
	}
	x_put_word(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		ccr_68000_long_move_ae_normal(src);
		m68k_areg(regs, dstreg) += 4;
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	x_put_word(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		ccr_68000_long_move_ae_normal(src);
		m68k_areg(regs, dstreg) += 4;
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return;
	}
	m68k_incpci(2);
	regs.loop_mode = loop_mode;
	return;
}
/* 22 (3/2) */
/* 2 0,0   */

/* MOVE.L (d16,An),-(An) */
void REGPARAM2 op_2128_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 24; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - 4;
	m68k_areg(regs, dstreg) = dsta;
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		m68k_areg(regs, dstreg) += 4;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(6);
		ccr_68000_long_move_ae_normal(src);
		m68k_areg(regs, dstreg) = dsta + 4;
		dsta += 2;
		exception3_write_access(opcode, dsta, 2, src, 1);
		return;
	}
	x_put_word(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		ccr_68000_long_move_ae_normal(src);
		m68k_areg(regs, dstreg) += 4;
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	x_put_word(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		ccr_68000_long_move_ae_normal(src);
		m68k_areg(regs, dstreg) += 4;
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 24 (4/2) */
/* 4 0,0   */

/* MOVE.L (d8,An,Xn),-(An) */
void REGPARAM2 op_2130_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 26; 
	uaecptr srca;
	do_cycles_ce000_internal(2);
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - 4;
	m68k_areg(regs, dstreg) = dsta;
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		m68k_areg(regs, dstreg) += 4;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(6);
		ccr_68000_long_move_ae_normal(src);
		m68k_areg(regs, dstreg) = dsta + 4;
		dsta += 2;
		exception3_write_access(opcode, dsta, 2, src, 1);
		return;
	}
	x_put_word(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		ccr_68000_long_move_ae_normal(src);
		m68k_areg(regs, dstreg) += 4;
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	x_put_word(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		ccr_68000_long_move_ae_normal(src);
		m68k_areg(regs, dstreg) += 4;
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 26 (4/2) */
/* 4 4,0   */

/* MOVE.L (xxx).W,-(An) */
void REGPARAM2 op_2138_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 24; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	if (srca & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - 4;
	m68k_areg(regs, dstreg) = dsta;
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		m68k_areg(regs, dstreg) += 4;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(6);
		ccr_68000_long_move_ae_normal(src);
		m68k_areg(regs, dstreg) = dsta + 4;
		dsta += 2;
		exception3_write_access(opcode, dsta, 2, src, 1);
		return;
	}
	x_put_word(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		ccr_68000_long_move_ae_normal(src);
		m68k_areg(regs, dstreg) += 4;
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	x_put_word(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		ccr_68000_long_move_ae_normal(src);
		m68k_areg(regs, dstreg) += 4;
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 24 (4/2) */
/* 4 0,0   */

/* MOVE.L (xxx).L,-(An) */
void REGPARAM2 op_2139_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 28; 
	uaecptr srca;
	srca = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	srca |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	if (srca & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - 4;
	m68k_areg(regs, dstreg) = dsta;
	regs.ir = regs.irc;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		m68k_areg(regs, dstreg) += 4;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(8);
		ccr_68000_long_move_ae_normal(src);
		m68k_areg(regs, dstreg) = dsta + 4;
		dsta += 2;
		exception3_write_access(opcode, dsta, 2, src, 1);
		return;
	}
	x_put_word(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		ccr_68000_long_move_ae_normal(src);
		m68k_areg(regs, dstreg) += 4;
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	x_put_word(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		ccr_68000_long_move_ae_normal(src);
		m68k_areg(regs, dstreg) += 4;
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 28 (5/2) */
/* 6 0,0   */

/* MOVE.L (d16,PC),-(An) */
void REGPARAM2 op_213a_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 24; 
	uaecptr srca;
	srca = m68k_getpci() + 2;
	srca += (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 2);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return;
	}
	ipl_fetch_now();
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 2);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - 4;
	m68k_areg(regs, dstreg) = dsta;
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		m68k_areg(regs, dstreg) += 4;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(6);
		ccr_68000_long_move_ae_normal(src);
		m68k_areg(regs, dstreg) = dsta + 4;
		dsta += 2;
		exception3_write_access(opcode, dsta, 2, src, 1);
		return;
	}
	x_put_word(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		ccr_68000_long_move_ae_normal(src);
		m68k_areg(regs, dstreg) += 4;
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	x_put_word(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		ccr_68000_long_move_ae_normal(src);
		m68k_areg(regs, dstreg) += 4;
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 24 (4/2) */
/* 4 0,0   */

/* MOVE.L (d8,PC,Xn),-(An) */
void REGPARAM2 op_213b_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 26; 
	uaecptr srca;
	uaecptr tmppc = m68k_getpci() + 2;
	do_cycles_ce000_internal(2);
	srca = get_disp_ea_000(tmppc, get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 2);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return;
	}
	ipl_fetch_now();
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 2);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - 4;
	m68k_areg(regs, dstreg) = dsta;
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		m68k_areg(regs, dstreg) += 4;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(6);
		ccr_68000_long_move_ae_normal(src);
		m68k_areg(regs, dstreg) = dsta + 4;
		dsta += 2;
		exception3_write_access(opcode, dsta, 2, src, 1);
		return;
	}
	x_put_word(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		ccr_68000_long_move_ae_normal(src);
		m68k_areg(regs, dstreg) += 4;
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	x_put_word(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		ccr_68000_long_move_ae_normal(src);
		m68k_areg(regs, dstreg) += 4;
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 26 (4/2) */
/* 4 4,0   */

/* MOVE.L #<data>.L,-(An) */
void REGPARAM2 op_213c_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 20; 
	uae_s32 src;
	src = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	ipl_fetch_now();
	src |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - 4;
	m68k_areg(regs, dstreg) = dsta;
	regs.ir = regs.irc;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		m68k_areg(regs, dstreg) += 4;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	struct flag_struct oldflags;
	oldflags.cznv = regflags.cznv;
	if (dsta & 1) {
		m68k_incpci(8);
		ccr_68000_long_move_ae_normal(src);
		m68k_areg(regs, dstreg) = dsta + 4;
		dsta += 2;
		exception3_write_access(opcode, dsta, 2, src, 1);
		return;
	}
	x_put_word(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		ccr_68000_long_move_ae_normal(src);
		m68k_areg(regs, dstreg) += 4;
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	x_put_word(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		ccr_68000_long_move_ae_normal(src);
		m68k_areg(regs, dstreg) += 4;
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 20 (3/2) */
/* 6 0,0   */

/* MOVE.L Dn,(d16,An) */
void REGPARAM2 op_2140_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 16; 
	uae_s32 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	struct flag_struct oldflags;
	oldflags.cznv = regflags.cznv;
	if (dsta & 1) {
		m68k_incpci(4);
		ccr_68000_long_move_ae_HNZ(src);
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return;
	}
	ipl_fetch_now();
	x_put_word(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		SET_NFLG(src < 0);
		if((src & 0xffff0000)) SET_ZFLG(0);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	x_put_word(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		ccr_68000_long_move_ae_LZN(src);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 16 (2/2) */
/* 4 0,0   */

/* MOVE.L An,(d16,An) */
void REGPARAM2 op_2148_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 16; 
	uae_s32 src = m68k_areg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	struct flag_struct oldflags;
	oldflags.cznv = regflags.cznv;
	if (dsta & 1) {
		m68k_incpci(4);
		ccr_68000_long_move_ae_HNZ(src);
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return;
	}
	ipl_fetch_now();
	x_put_word(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		SET_NFLG(src < 0);
		if((src & 0xffff0000)) SET_ZFLG(0);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	x_put_word(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		ccr_68000_long_move_ae_LZN(src);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 16 (2/2) */
/* 4 0,0   */

/* MOVE.L (An),(d16,An) */
void REGPARAM2 op_2150_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 24; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch(opcode, 4, 0);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(4);
		ccr_68000_long_move_ae_normal(src);
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return;
	}
	x_put_word(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	ipl_fetch_now();
	x_put_word(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 24 (4/2) */
/* 4 0,0   */

/* MOVE.L (An)+,(d16,An) */
void REGPARAM2 op_2158_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 24; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	m68k_areg(regs, srcreg) += 4;
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch(opcode, 4, 0);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(4);
		ccr_68000_long_move_ae_normal(src);
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return;
	}
	x_put_word(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	ipl_fetch_now();
	x_put_word(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 24 (4/2) */
/* 4 0,0   */

/* MOVE.L -(An),(d16,An) */
void REGPARAM2 op_2160_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 26; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - 4;
	do_cycles_ce000_internal(2);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	m68k_areg(regs, srcreg) = srca;
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch(opcode, 4, 0);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(4);
		ccr_68000_long_move_ae_normal(src);
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return;
	}
	x_put_word(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	ipl_fetch_now();
	x_put_word(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 26 (4/2) */
/* 4 0,0   */

/* MOVE.L (d16,An),(d16,An) */
void REGPARAM2 op_2168_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 28; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch(opcode, 6, 0);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(6);
		ccr_68000_long_move_ae_normal(src);
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return;
	}
	x_put_word(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	ipl_fetch_now();
	x_put_word(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return;
	}
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 28 (5/2) */
/* 6 0,0   */

/* MOVE.L (d8,An,Xn),(d16,An) */
void REGPARAM2 op_2170_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 30; 
	uaecptr srca;
	do_cycles_ce000_internal(2);
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch(opcode, 6, 0);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(6);
		ccr_68000_long_move_ae_normal(src);
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return;
	}
	x_put_word(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	ipl_fetch_now();
	x_put_word(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return;
	}
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 30 (5/2) */
/* 6 6,0   */

/* MOVE.L (xxx).W,(d16,An) */
void REGPARAM2 op_2178_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 28; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	if (srca & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch(opcode, 6, 0);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(6);
		ccr_68000_long_move_ae_normal(src);
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return;
	}
	x_put_word(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	ipl_fetch_now();
	x_put_word(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return;
	}
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 28 (5/2) */
/* 6 0,0   */

/* MOVE.L (xxx).L,(d16,An) */
void REGPARAM2 op_2179_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 32; 
	uaecptr srca;
	srca = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	srca |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	if (srca & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch(opcode, 8, 0);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(8);
		ccr_68000_long_move_ae_normal(src);
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return;
	}
	x_put_word(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	ipl_fetch_now();
	x_put_word(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return;
	}
	m68k_incpci(8);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 32 (6/2) */
/* 8 0,0   */

/* MOVE.L (d16,PC),(d16,An) */
void REGPARAM2 op_217a_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 28; 
	uaecptr srca;
	srca = m68k_getpci() + 2;
	srca += (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 2);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return;
	}
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 2);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch(opcode, 6, 0);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(6);
		ccr_68000_long_move_ae_normal(src);
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return;
	}
	x_put_word(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	ipl_fetch_now();
	x_put_word(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return;
	}
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 28 (5/2) */
/* 6 0,0   */

/* MOVE.L (d8,PC,Xn),(d16,An) */
void REGPARAM2 op_217b_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 30; 
	uaecptr srca;
	uaecptr tmppc = m68k_getpci() + 2;
	do_cycles_ce000_internal(2);
	srca = get_disp_ea_000(tmppc, get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 2);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return;
	}
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 2);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch(opcode, 6, 0);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(6);
		ccr_68000_long_move_ae_normal(src);
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return;
	}
	x_put_word(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	ipl_fetch_now();
	x_put_word(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return;
	}
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 30 (5/2) */
/* 6 6,0   */

/* MOVE.L #<data>.L,(d16,An) */
void REGPARAM2 op_217c_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 24; 
	uae_s32 src;
	src = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	src |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 8, 0);
		return;
	}
	struct flag_struct oldflags;
	oldflags.cznv = regflags.cznv;
	if (dsta & 1) {
		m68k_incpci(8);
		ccr_68000_long_move_ae_HNZ(src);
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return;
	}
	ipl_fetch_now();
	x_put_word(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		ccr_68000_long_move_ae_HNZ(src);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	x_put_word(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		ccr_68000_long_move_ae_LZN(src);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return;
	}
	m68k_incpci(8);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 24 (4/2) */
/* 8 0,0   */

/* MOVE.L Dn,(d8,An,Xn) */
void REGPARAM2 op_2180_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 18; 
	uae_s32 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	do_cycles_ce000_internal(2);
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	struct flag_struct oldflags;
	oldflags.cznv = regflags.cznv;
	if (dsta & 1) {
		m68k_incpci(4);
		ccr_68000_long_move_ae_HNZ(src);
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return;
	}
	ipl_fetch_now();
	x_put_word(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		SET_NFLG(src < 0);
		if((src & 0xffff0000)) SET_ZFLG(0);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	x_put_word(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		ccr_68000_long_move_ae_LZN(src);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 18 (2/2) */
/* 4 4,0   */

/* MOVE.L An,(d8,An,Xn) */
void REGPARAM2 op_2188_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 18; 
	uae_s32 src = m68k_areg(regs, srcreg);
	uaecptr dsta;
	do_cycles_ce000_internal(2);
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	struct flag_struct oldflags;
	oldflags.cznv = regflags.cznv;
	if (dsta & 1) {
		m68k_incpci(4);
		ccr_68000_long_move_ae_HNZ(src);
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return;
	}
	ipl_fetch_now();
	x_put_word(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		SET_NFLG(src < 0);
		if((src & 0xffff0000)) SET_ZFLG(0);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	x_put_word(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		ccr_68000_long_move_ae_LZN(src);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 18 (2/2) */
/* 4 4,0   */

/* MOVE.L (An),(d8,An,Xn) */
void REGPARAM2 op_2190_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 26; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	uaecptr dsta;
	do_cycles_ce000_internal(2);
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch(opcode, 4, 0);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(4);
		ccr_68000_long_move_ae_normal(src);
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return;
	}
	x_put_word(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	ipl_fetch_now();
	x_put_word(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 26 (4/2) */
/* 4 4,0   */

/* MOVE.L (An)+,(d8,An,Xn) */
void REGPARAM2 op_2198_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 26; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	m68k_areg(regs, srcreg) += 4;
	uaecptr dsta;
	do_cycles_ce000_internal(2);
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch(opcode, 4, 0);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(4);
		ccr_68000_long_move_ae_normal(src);
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return;
	}
	x_put_word(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	ipl_fetch_now();
	x_put_word(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 26 (4/2) */
/* 4 4,0   */

/* MOVE.L -(An),(d8,An,Xn) */
void REGPARAM2 op_21a0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 28; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - 4;
	do_cycles_ce000_internal(2);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	m68k_areg(regs, srcreg) = srca;
	uaecptr dsta;
	do_cycles_ce000_internal(2);
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch(opcode, 4, 0);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(4);
		ccr_68000_long_move_ae_normal(src);
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return;
	}
	x_put_word(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	ipl_fetch_now();
	x_put_word(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 28 (4/2) */
/* 4 4,0   */

/* MOVE.L (d16,An),(d8,An,Xn) */
void REGPARAM2 op_21a8_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 30; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	uaecptr dsta;
	do_cycles_ce000_internal(2);
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_ce000_prefetch(6));
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch(opcode, 6, 0);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(6);
		ccr_68000_long_move_ae_normal(src);
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return;
	}
	x_put_word(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	ipl_fetch_now();
	x_put_word(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return;
	}
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 30 (5/2) */
/* 6 4,0   */

/* MOVE.L (d8,An,Xn),(d8,An,Xn) */
void REGPARAM2 op_21b0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 32; 
	uaecptr srca;
	do_cycles_ce000_internal(2);
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	uaecptr dsta;
	do_cycles_ce000_internal(2);
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_ce000_prefetch(6));
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch(opcode, 6, 0);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(6);
		ccr_68000_long_move_ae_normal(src);
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return;
	}
	x_put_word(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	ipl_fetch_now();
	x_put_word(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return;
	}
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 32 (5/2) */
/* 6 6,4   */

/* MOVE.L (xxx).W,(d8,An,Xn) */
void REGPARAM2 op_21b8_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 30; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	if (srca & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	uaecptr dsta;
	do_cycles_ce000_internal(2);
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_ce000_prefetch(6));
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch(opcode, 6, 0);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(6);
		ccr_68000_long_move_ae_normal(src);
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return;
	}
	x_put_word(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	ipl_fetch_now();
	x_put_word(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return;
	}
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 30 (5/2) */
/* 6 4,0   */

/* MOVE.L (xxx).L,(d8,An,Xn) */
void REGPARAM2 op_21b9_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 34; 
	uaecptr srca;
	srca = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	srca |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	if (srca & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	uaecptr dsta;
	do_cycles_ce000_internal(2);
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_ce000_prefetch(8));
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch(opcode, 8, 0);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(8);
		ccr_68000_long_move_ae_normal(src);
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return;
	}
	x_put_word(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	ipl_fetch_now();
	x_put_word(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return;
	}
	m68k_incpci(8);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 34 (6/2) */
/* 8 4,0   */

/* MOVE.L (d16,PC),(d8,An,Xn) */
void REGPARAM2 op_21ba_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 30; 
	uaecptr srca;
	srca = m68k_getpci() + 2;
	srca += (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 2);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return;
	}
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 2);
		return;
	}
	uaecptr dsta;
	do_cycles_ce000_internal(2);
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_ce000_prefetch(6));
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch(opcode, 6, 0);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(6);
		ccr_68000_long_move_ae_normal(src);
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return;
	}
	x_put_word(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	ipl_fetch_now();
	x_put_word(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return;
	}
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 30 (5/2) */
/* 6 4,0   */

/* MOVE.L (d8,PC,Xn),(d8,An,Xn) */
void REGPARAM2 op_21bb_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 32; 
	uaecptr srca;
	uaecptr tmppc = m68k_getpci() + 2;
	do_cycles_ce000_internal(2);
	srca = get_disp_ea_000(tmppc, get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 2);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return;
	}
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 2);
		return;
	}
	uaecptr dsta;
	do_cycles_ce000_internal(2);
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_ce000_prefetch(6));
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch(opcode, 6, 0);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(6);
		ccr_68000_long_move_ae_normal(src);
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return;
	}
	x_put_word(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	ipl_fetch_now();
	x_put_word(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return;
	}
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 32 (5/2) */
/* 6 6,4   */

/* MOVE.L #<data>.L,(d8,An,Xn) */
void REGPARAM2 op_21bc_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 26; 
	uae_s32 src;
	src = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	src |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	uaecptr dsta;
	do_cycles_ce000_internal(2);
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_ce000_prefetch(8));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 8, 0);
		return;
	}
	struct flag_struct oldflags;
	oldflags.cznv = regflags.cznv;
	if (dsta & 1) {
		m68k_incpci(8);
		ccr_68000_long_move_ae_HNZ(src);
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return;
	}
	ipl_fetch_now();
	x_put_word(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		ccr_68000_long_move_ae_HNZ(src);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	x_put_word(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		ccr_68000_long_move_ae_LZN(src);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return;
	}
	m68k_incpci(8);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 26 (4/2) */
/* 8 4,0   */

/* MOVE.L Dn,(xxx).W */
void REGPARAM2 op_21c0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 30;
	CurrentInstrCycles = 16; 
	uae_s32 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch(opcode, 4, 0);
		return;
	}
	struct flag_struct oldflags;
	oldflags.cznv = regflags.cznv;
	if (dsta & 1) {
		m68k_incpci(4);
		ccr_68000_long_move_ae_normal(src);
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return;
	}
	x_put_word(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	ipl_fetch_now();
	x_put_word(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 16 (2/2) */
/* 4 0,0   */

/* MOVE.L An,(xxx).W */
void REGPARAM2 op_21c8_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 30;
	CurrentInstrCycles = 16; 
	uae_s32 src = m68k_areg(regs, srcreg);
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch(opcode, 4, 0);
		return;
	}
	struct flag_struct oldflags;
	oldflags.cznv = regflags.cznv;
	if (dsta & 1) {
		m68k_incpci(4);
		ccr_68000_long_move_ae_normal(src);
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return;
	}
	x_put_word(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	ipl_fetch_now();
	x_put_word(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 16 (2/2) */
/* 4 0,0   */

/* MOVE.L (An),(xxx).W */
void REGPARAM2 op_21d0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 30;
	CurrentInstrCycles = 24; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch(opcode, 4, 0);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(4);
		ccr_68000_long_move_ae_normal(src);
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return;
	}
	x_put_word(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		ccr_68000_long_move_ae_LZN(src);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	ipl_fetch_now();
	x_put_word(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 24 (4/2) */
/* 4 0,0   */

/* MOVE.L (An)+,(xxx).W */
void REGPARAM2 op_21d8_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 30;
	CurrentInstrCycles = 24; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	m68k_areg(regs, srcreg) += 4;
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch(opcode, 4, 0);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(4);
		ccr_68000_long_move_ae_normal(src);
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return;
	}
	x_put_word(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		ccr_68000_long_move_ae_LZN(src);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	ipl_fetch_now();
	x_put_word(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 24 (4/2) */
/* 4 0,0   */

/* MOVE.L -(An),(xxx).W */
void REGPARAM2 op_21e0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 30;
	CurrentInstrCycles = 26; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - 4;
	do_cycles_ce000_internal(2);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	m68k_areg(regs, srcreg) = srca;
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch(opcode, 4, 0);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(4);
		ccr_68000_long_move_ae_normal(src);
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return;
	}
	x_put_word(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		ccr_68000_long_move_ae_LZN(src);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	ipl_fetch_now();
	x_put_word(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 26 (4/2) */
/* 4 0,0   */

/* MOVE.L (d16,An),(xxx).W */
void REGPARAM2 op_21e8_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 30;
	CurrentInstrCycles = 28; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch(opcode, 6, 0);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(6);
		ccr_68000_long_move_ae_normal(src);
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return;
	}
	x_put_word(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		ccr_68000_long_move_ae_LZN(src);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	ipl_fetch_now();
	x_put_word(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return;
	}
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 28 (5/2) */
/* 6 0,0   */

/* MOVE.L (d8,An,Xn),(xxx).W */
void REGPARAM2 op_21f0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 30;
	CurrentInstrCycles = 30; 
	uaecptr srca;
	do_cycles_ce000_internal(2);
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch(opcode, 6, 0);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(6);
		ccr_68000_long_move_ae_normal(src);
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return;
	}
	x_put_word(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		ccr_68000_long_move_ae_LZN(src);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	ipl_fetch_now();
	x_put_word(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return;
	}
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 30 (5/2) */
/* 6 6,0   */

/* MOVE.L (xxx).W,(xxx).W */
void REGPARAM2 op_21f8_13_ff(uae_u32 opcode)
{
	OpcodeFamily = 30;
	CurrentInstrCycles = 28; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	if (srca & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch(opcode, 6, 0);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(6);
		ccr_68000_long_move_ae_normal(src);
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return;
	}
	x_put_word(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		ccr_68000_long_move_ae_LZN(src);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	ipl_fetch_now();
	x_put_word(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return;
	}
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 28 (5/2) */
/* 6 0,0   */

/* MOVE.L (xxx).L,(xxx).W */
void REGPARAM2 op_21f9_13_ff(uae_u32 opcode)
{
	OpcodeFamily = 30;
	CurrentInstrCycles = 32; 
	uaecptr srca;
	srca = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	srca |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	if (srca & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch(opcode, 8, 0);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(8);
		ccr_68000_long_move_ae_normal(src);
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return;
	}
	x_put_word(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		ccr_68000_long_move_ae_LZN(src);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	ipl_fetch_now();
	x_put_word(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return;
	}
	m68k_incpci(8);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 32 (6/2) */
/* 8 0,0   */

/* MOVE.L (d16,PC),(xxx).W */
void REGPARAM2 op_21fa_13_ff(uae_u32 opcode)
{
	OpcodeFamily = 30;
	CurrentInstrCycles = 28; 
	uaecptr srca;
	srca = m68k_getpci() + 2;
	srca += (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 2);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return;
	}
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 2);
		return;
	}
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch(opcode, 6, 0);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(6);
		ccr_68000_long_move_ae_normal(src);
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return;
	}
	x_put_word(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		ccr_68000_long_move_ae_LZN(src);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	ipl_fetch_now();
	x_put_word(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return;
	}
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 28 (5/2) */
/* 6 0,0   */

/* MOVE.L (d8,PC,Xn),(xxx).W */
void REGPARAM2 op_21fb_13_ff(uae_u32 opcode)
{
	OpcodeFamily = 30;
	CurrentInstrCycles = 30; 
	uaecptr srca;
	uaecptr tmppc = m68k_getpci() + 2;
	do_cycles_ce000_internal(2);
	srca = get_disp_ea_000(tmppc, get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 2);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return;
	}
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 2);
		return;
	}
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch(opcode, 6, 0);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(6);
		ccr_68000_long_move_ae_normal(src);
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return;
	}
	x_put_word(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		ccr_68000_long_move_ae_LZN(src);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	ipl_fetch_now();
	x_put_word(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return;
	}
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 30 (5/2) */
/* 6 6,0   */

/* MOVE.L #<data>.L,(xxx).W */
void REGPARAM2 op_21fc_13_ff(uae_u32 opcode)
{
	OpcodeFamily = 30;
	CurrentInstrCycles = 24; 
	uae_s32 src;
	src = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	src |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch(opcode, 8, 0);
		return;
	}
	struct flag_struct oldflags;
	oldflags.cznv = regflags.cznv;
	if (dsta & 1) {
		m68k_incpci(8);
		ccr_68000_long_move_ae_normal(src);
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return;
	}
	x_put_word(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	ipl_fetch_now();
	x_put_word(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return;
	}
	m68k_incpci(8);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 24 (4/2) */
/* 8 0,0   */

/* MOVE.L Dn,(xxx).L */
void REGPARAM2 op_23c0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 30;
	CurrentInstrCycles = 20; 
	uae_s32 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		// nothing;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	dsta |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	struct flag_struct oldflags;
	oldflags.cznv = regflags.cznv;
	if (dsta & 1) {
		m68k_incpci(6);
		ccr_68000_long_move_ae_normal(src);
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return;
	}
	x_put_word(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	x_put_word(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return;
	}
	ipl_fetch_next();
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 20 (3/2) */
/* 6 0,0   */

/* MOVE.L An,(xxx).L */
void REGPARAM2 op_23c8_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 30;
	CurrentInstrCycles = 20; 
	uae_s32 src = m68k_areg(regs, srcreg);
	uaecptr dsta;
	dsta = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		// nothing;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	dsta |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	struct flag_struct oldflags;
	oldflags.cznv = regflags.cznv;
	if (dsta & 1) {
		m68k_incpci(6);
		ccr_68000_long_move_ae_normal(src);
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return;
	}
	x_put_word(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	x_put_word(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return;
	}
	ipl_fetch_next();
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 20 (3/2) */
/* 6 0,0   */

/* MOVE.L (An),(xxx).L */
void REGPARAM2 op_23d0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 30;
	CurrentInstrCycles = 28; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	uaecptr dsta;
	dsta = get_word_ce000_prefetch(4) << 16;
	dsta |= regs.irc;
	if(hardware_bus_error) {
		int pcoffset = 0;
		// nothing;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(4);
		regs.irc = dsta >> 16;
		ccr_68000_long_move_ae_LZN(src);
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return;
	}
	x_put_word(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		ccr_68000_long_move_ae_LZN(src);
		regs.irc = dsta >> 16;
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	x_put_word(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		ccr_68000_long_move_ae_normal(src);
		regs.irc = dsta >> 16;
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return;
	}
	ipl_fetch_now();
	m68k_incpci(6);
	get_word_ce000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, 0);
		return;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 28 (5/2) */
/* 6 0,0   */

/* MOVE.L (An)+,(xxx).L */
void REGPARAM2 op_23d8_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 30;
	CurrentInstrCycles = 28; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	m68k_areg(regs, srcreg) += 4;
	uaecptr dsta;
	dsta = get_word_ce000_prefetch(4) << 16;
	dsta |= regs.irc;
	if(hardware_bus_error) {
		int pcoffset = 0;
		// nothing;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(4);
		regs.irc = dsta >> 16;
		ccr_68000_long_move_ae_LZN(src);
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return;
	}
	x_put_word(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		ccr_68000_long_move_ae_LZN(src);
		regs.irc = dsta >> 16;
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	x_put_word(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		ccr_68000_long_move_ae_normal(src);
		regs.irc = dsta >> 16;
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return;
	}
	ipl_fetch_now();
	m68k_incpci(6);
	get_word_ce000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, 0);
		return;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 28 (5/2) */
/* 6 0,0   */

/* MOVE.L -(An),(xxx).L */
void REGPARAM2 op_23e0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 30;
	CurrentInstrCycles = 30; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - 4;
	do_cycles_ce000_internal(2);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	m68k_areg(regs, srcreg) = srca;
	uaecptr dsta;
	dsta = get_word_ce000_prefetch(4) << 16;
	dsta |= regs.irc;
	if(hardware_bus_error) {
		int pcoffset = 0;
		// nothing;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(4);
		regs.irc = dsta >> 16;
		ccr_68000_long_move_ae_LZN(src);
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return;
	}
	x_put_word(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		ccr_68000_long_move_ae_LZN(src);
		regs.irc = dsta >> 16;
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	x_put_word(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		ccr_68000_long_move_ae_normal(src);
		regs.irc = dsta >> 16;
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return;
	}
	ipl_fetch_now();
	m68k_incpci(6);
	get_word_ce000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, 0);
		return;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 30 (5/2) */
/* 6 0,0   */

/* MOVE.L (d16,An),(xxx).L */
void REGPARAM2 op_23e8_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 30;
	CurrentInstrCycles = 32; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	uaecptr dsta;
	dsta = get_word_ce000_prefetch(6) << 16;
	dsta |= regs.irc;
	if(hardware_bus_error) {
		int pcoffset = 0;
		// nothing;
		exception2_fetch(opcode, 6, 0);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(6);
		regs.irc = dsta >> 16;
		ccr_68000_long_move_ae_LZN(src);
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return;
	}
	x_put_word(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		ccr_68000_long_move_ae_LZN(src);
		regs.irc = dsta >> 16;
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	x_put_word(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		ccr_68000_long_move_ae_normal(src);
		regs.irc = dsta >> 16;
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return;
	}
	ipl_fetch_now();
	m68k_incpci(8);
	get_word_ce000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, 0);
		return;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 32 (6/2) */
/* 8 0,0   */

/* MOVE.L (d8,An,Xn),(xxx).L */
void REGPARAM2 op_23f0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 30;
	CurrentInstrCycles = 34; 
	uaecptr srca;
	do_cycles_ce000_internal(2);
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	uaecptr dsta;
	dsta = get_word_ce000_prefetch(6) << 16;
	dsta |= regs.irc;
	if(hardware_bus_error) {
		int pcoffset = 0;
		// nothing;
		exception2_fetch(opcode, 6, 0);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(6);
		regs.irc = dsta >> 16;
		ccr_68000_long_move_ae_LZN(src);
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return;
	}
	x_put_word(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		ccr_68000_long_move_ae_LZN(src);
		regs.irc = dsta >> 16;
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	x_put_word(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		ccr_68000_long_move_ae_normal(src);
		regs.irc = dsta >> 16;
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return;
	}
	ipl_fetch_now();
	m68k_incpci(8);
	get_word_ce000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, 0);
		return;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 34 (6/2) */
/* 8 8,0   */

/* MOVE.L (xxx).W,(xxx).L */
void REGPARAM2 op_23f8_13_ff(uae_u32 opcode)
{
	OpcodeFamily = 30;
	CurrentInstrCycles = 32; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	if (srca & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	uaecptr dsta;
	dsta = get_word_ce000_prefetch(6) << 16;
	dsta |= regs.irc;
	if(hardware_bus_error) {
		int pcoffset = 0;
		// nothing;
		exception2_fetch(opcode, 6, 0);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(6);
		regs.irc = dsta >> 16;
		ccr_68000_long_move_ae_LZN(src);
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return;
	}
	x_put_word(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		ccr_68000_long_move_ae_LZN(src);
		regs.irc = dsta >> 16;
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	x_put_word(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		ccr_68000_long_move_ae_normal(src);
		regs.irc = dsta >> 16;
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return;
	}
	ipl_fetch_now();
	m68k_incpci(8);
	get_word_ce000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, 0);
		return;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 32 (6/2) */
/* 8 0,0   */

/* MOVE.L (xxx).L,(xxx).L */
void REGPARAM2 op_23f9_13_ff(uae_u32 opcode)
{
	OpcodeFamily = 30;
	CurrentInstrCycles = 36; 
	uaecptr srca;
	srca = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	srca |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	if (srca & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	uaecptr dsta;
	dsta = get_word_ce000_prefetch(8) << 16;
	dsta |= regs.irc;
	if(hardware_bus_error) {
		int pcoffset = 0;
		// nothing;
		exception2_fetch(opcode, 8, 0);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(8);
		regs.irc = dsta >> 16;
		ccr_68000_long_move_ae_LZN(src);
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return;
	}
	x_put_word(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		ccr_68000_long_move_ae_LZN(src);
		regs.irc = dsta >> 16;
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	x_put_word(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		ccr_68000_long_move_ae_normal(src);
		regs.irc = dsta >> 16;
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return;
	}
	ipl_fetch_now();
	m68k_incpci(10);
	get_word_ce000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, 0);
		return;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 36 (7/2) */
/* 10 0,0   */

/* MOVE.L (d16,PC),(xxx).L */
void REGPARAM2 op_23fa_13_ff(uae_u32 opcode)
{
	OpcodeFamily = 30;
	CurrentInstrCycles = 32; 
	uaecptr srca;
	srca = m68k_getpci() + 2;
	srca += (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 2);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return;
	}
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 2);
		return;
	}
	uaecptr dsta;
	dsta = get_word_ce000_prefetch(6) << 16;
	dsta |= regs.irc;
	if(hardware_bus_error) {
		int pcoffset = 0;
		// nothing;
		exception2_fetch(opcode, 6, 0);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(6);
		regs.irc = dsta >> 16;
		ccr_68000_long_move_ae_LZN(src);
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return;
	}
	x_put_word(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		ccr_68000_long_move_ae_LZN(src);
		regs.irc = dsta >> 16;
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	x_put_word(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		ccr_68000_long_move_ae_normal(src);
		regs.irc = dsta >> 16;
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return;
	}
	ipl_fetch_now();
	m68k_incpci(8);
	get_word_ce000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, 0);
		return;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 32 (6/2) */
/* 8 0,0   */

/* MOVE.L (d8,PC,Xn),(xxx).L */
void REGPARAM2 op_23fb_13_ff(uae_u32 opcode)
{
	OpcodeFamily = 30;
	CurrentInstrCycles = 34; 
	uaecptr srca;
	uaecptr tmppc = m68k_getpci() + 2;
	do_cycles_ce000_internal(2);
	srca = get_disp_ea_000(tmppc, get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 2);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return;
	}
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 2);
		return;
	}
	uaecptr dsta;
	dsta = get_word_ce000_prefetch(6) << 16;
	dsta |= regs.irc;
	if(hardware_bus_error) {
		int pcoffset = 0;
		// nothing;
		exception2_fetch(opcode, 6, 0);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(6);
		regs.irc = dsta >> 16;
		ccr_68000_long_move_ae_LZN(src);
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return;
	}
	x_put_word(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		ccr_68000_long_move_ae_LZN(src);
		regs.irc = dsta >> 16;
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	x_put_word(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		ccr_68000_long_move_ae_normal(src);
		regs.irc = dsta >> 16;
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return;
	}
	ipl_fetch_now();
	m68k_incpci(8);
	get_word_ce000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, 0);
		return;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 34 (6/2) */
/* 8 8,0   */

/* MOVE.L #<data>.L,(xxx).L */
void REGPARAM2 op_23fc_13_ff(uae_u32 opcode)
{
	OpcodeFamily = 30;
	CurrentInstrCycles = 28; 
	uae_s32 src;
	src = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	src |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	uaecptr dsta;
	dsta = get_word_ce000_prefetch(8) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 8, -2);
		return;
	}
	dsta |= get_word_ce000_prefetch(10);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch(opcode, 10, pcoffset);
		return;
	}
	struct flag_struct oldflags;
	oldflags.cznv = regflags.cznv;
	if (dsta & 1) {
		m68k_incpci(10);
		ccr_68000_long_move_ae_normal(src);
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return;
	}
	x_put_word(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(10);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	x_put_word(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(10);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return;
	}
	ipl_fetch_next();
	m68k_incpci(10);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 28 (5/2) */
/* 10 0,0   */

/* MOVE.W Dn,Dn */
void REGPARAM2 op_3000_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 4;  
	uae_s16 src = m68k_dreg(regs, srcreg);
	struct flag_struct oldflags;
	oldflags.cznv = regflags.cznv;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
	m68k_incpci(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 4 (1/0) */
/* 2 0,0   */

/* MOVE.W An,Dn */
void REGPARAM2 op_3008_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 4;  
	uae_s16 src = m68k_areg(regs, srcreg);
	struct flag_struct oldflags;
	oldflags.cznv = regflags.cznv;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
	m68k_incpci(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 4 (1/0) */
/* 2 0,0   */

/* MOVE.W (An),Dn */
void REGPARAM2 op_3010_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 8;  
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access2(opcode, srca, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
	m68k_incpci(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 8 (2/0) */
/* 2 0,0   */

/* MOVE.W (An)+,Dn */
void REGPARAM2 op_3018_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 8;  
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_areg(regs, srcreg) += 2 + 0;
		m68k_incpci(2);
		exception3_read_access2(opcode, srca, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) += 2 + 0;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	m68k_areg(regs, srcreg) += 2;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
	m68k_incpci(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 8 (2/0) */
/* 2 0,0   */

/* MOVE.W -(An),Dn */
void REGPARAM2 op_3020_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 10; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - 2;
	do_cycles_ce000_internal(2);
	if (srca & 1) {
		m68k_areg(regs, srcreg) = srca;
		m68k_incpci(2);
		exception3_read_access2(opcode, srca, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	m68k_areg(regs, srcreg) = srca;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
	m68k_incpci(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 10 (2/0) */
/* 2 0,0   */

/* MOVE.W (d16,An),Dn */
void REGPARAM2 op_3028_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 12 (3/0) */
/* 4 0,0   */

/* MOVE.W (d8,An,Xn),Dn */
void REGPARAM2 op_3030_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	do_cycles_ce000_internal(2);
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 14 (3/0) */
/* 4 4,0   */

/* MOVE.W (xxx).W,Dn */
void REGPARAM2 op_3038_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	if (srca & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 12 (3/0) */
/* 4 0,0   */

/* MOVE.W (xxx).L,Dn */
void REGPARAM2 op_3039_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	srca |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	if (srca & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 16 (4/0) */
/* 6 0,0   */

/* MOVE.W (d16,PC),Dn */
void REGPARAM2 op_303a_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_getpci() + 2;
	srca += (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 2);
		return;
	}
	ipl_fetch_now();
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 12 (3/0) */
/* 4 0,0   */

/* MOVE.W (d8,PC,Xn),Dn */
void REGPARAM2 op_303b_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	uaecptr tmppc = m68k_getpci() + 2;
	do_cycles_ce000_internal(2);
	srca = get_disp_ea_000(tmppc, get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 2);
		return;
	}
	ipl_fetch_now();
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 14 (3/0) */
/* 4 4,0   */

/* MOVE.W #<data>.W,Dn */
void REGPARAM2 op_303c_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 8;  
	uae_s16 src = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	struct flag_struct oldflags;
	oldflags.cznv = regflags.cznv;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 8 (2/0) */
/* 4 0,0   */

/* MOVEA.W Dn,An */
void REGPARAM2 op_3040_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 31;
	CurrentInstrCycles = 4;  
	uae_s16 src = m68k_dreg(regs, srcreg);
	src = (uae_s32)(uae_s16)src;
	m68k_areg(regs, dstreg) = (uae_s32)(uae_s16)(src);
	m68k_incpci(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 4 (1/0) */
/* 2 0,0   */

/* MOVEA.W An,An */
void REGPARAM2 op_3048_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 31;
	CurrentInstrCycles = 4;  
	uae_s16 src = m68k_areg(regs, srcreg);
	src = (uae_s32)(uae_s16)src;
	m68k_areg(regs, dstreg) = (uae_s32)(uae_s16)(src);
	m68k_incpci(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 4 (1/0) */
/* 2 0,0   */

/* MOVEA.W (An),An */
void REGPARAM2 op_3050_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 31;
	CurrentInstrCycles = 8;  
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access2(opcode, srca, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	src = (uae_s32)(uae_s16)src;
	m68k_areg(regs, dstreg) = (uae_s32)(uae_s16)(src);
	m68k_incpci(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 8 (2/0) */
/* 2 0,0   */

/* MOVEA.W (An)+,An */
void REGPARAM2 op_3058_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 31;
	CurrentInstrCycles = 8;  
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_areg(regs, srcreg) += 2 + 0;
		m68k_incpci(2);
		exception3_read_access2(opcode, srca, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) += 2 + 0;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	m68k_areg(regs, srcreg) += 2;
	src = (uae_s32)(uae_s16)src;
	m68k_areg(regs, dstreg) = (uae_s32)(uae_s16)(src);
	m68k_incpci(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 8 (2/0) */
/* 2 0,0   */

/* MOVEA.W -(An),An */
void REGPARAM2 op_3060_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 31;
	CurrentInstrCycles = 10; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - 2;
	do_cycles_ce000_internal(2);
	if (srca & 1) {
		m68k_areg(regs, srcreg) = srca;
		m68k_incpci(2);
		exception3_read_access2(opcode, srca, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	m68k_areg(regs, srcreg) = srca;
	src = (uae_s32)(uae_s16)src;
	m68k_areg(regs, dstreg) = (uae_s32)(uae_s16)(src);
	m68k_incpci(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 10 (2/0) */
/* 2 0,0   */

/* MOVEA.W (d16,An),An */
void REGPARAM2 op_3068_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 31;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	src = (uae_s32)(uae_s16)src;
	m68k_areg(regs, dstreg) = (uae_s32)(uae_s16)(src);
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 12 (3/0) */
/* 4 0,0   */

/* MOVEA.W (d8,An,Xn),An */
void REGPARAM2 op_3070_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 31;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	do_cycles_ce000_internal(2);
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	src = (uae_s32)(uae_s16)src;
	m68k_areg(regs, dstreg) = (uae_s32)(uae_s16)(src);
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 14 (3/0) */
/* 4 4,0   */

/* MOVEA.W (xxx).W,An */
void REGPARAM2 op_3078_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 31;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	if (srca & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	src = (uae_s32)(uae_s16)src;
	m68k_areg(regs, dstreg) = (uae_s32)(uae_s16)(src);
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 12 (3/0) */
/* 4 0,0   */

/* MOVEA.W (xxx).L,An */
void REGPARAM2 op_3079_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 31;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	srca |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	if (srca & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	src = (uae_s32)(uae_s16)src;
	m68k_areg(regs, dstreg) = (uae_s32)(uae_s16)(src);
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 16 (4/0) */
/* 6 0,0   */

/* MOVEA.W (d16,PC),An */
void REGPARAM2 op_307a_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 31;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_getpci() + 2;
	srca += (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 2);
		return;
	}
	ipl_fetch_now();
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return;
	}
	src = (uae_s32)(uae_s16)src;
	m68k_areg(regs, dstreg) = (uae_s32)(uae_s16)(src);
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 12 (3/0) */
/* 4 0,0   */

/* MOVEA.W (d8,PC,Xn),An */
void REGPARAM2 op_307b_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 31;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	uaecptr tmppc = m68k_getpci() + 2;
	do_cycles_ce000_internal(2);
	srca = get_disp_ea_000(tmppc, get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 2);
		return;
	}
	ipl_fetch_now();
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return;
	}
	src = (uae_s32)(uae_s16)src;
	m68k_areg(regs, dstreg) = (uae_s32)(uae_s16)(src);
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 14 (3/0) */
/* 4 4,0   */

/* MOVEA.W #<data>.W,An */
void REGPARAM2 op_307c_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 31;
	CurrentInstrCycles = 8;  
	uae_s16 src = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	src = (uae_s32)(uae_s16)src;
	m68k_areg(regs, dstreg) = (uae_s32)(uae_s16)(src);
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 8 (2/0) */
/* 4 0,0   */

/* MOVE.W Dn,(An) */
void REGPARAM2 op_3080_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 8;  
	int loop_mode = regs.loop_mode;
	uae_s16 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	struct flag_struct oldflags;
	oldflags.cznv = regflags.cznv;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(4);
		regflags.cznv = oldflags.cznv;
		exception3_write_access(opcode, dsta, 1, src, 1);
		return;
	}
	ipl_fetch_now();
	x_put_word(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return;
	}
	m68k_incpci(2);
	if(!loop_mode) {
		regs.ir = regs.irc;
		opcode = regs.ir;
		get_word_ce000_prefetch(2);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 2, pcoffset);
			return;
		}
	} else {
		loop_mode = 0;
		loop_mode |= 2;
		loop_mode |= 4 << 16;
	}
	regs.loop_mode = loop_mode;
	return;
}
/* 8 (1/1) */
/* 2 0,0   */

/* MOVE.W An,(An) */
void REGPARAM2 op_3088_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 8;  
	int loop_mode = regs.loop_mode;
	uae_s16 src = m68k_areg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	struct flag_struct oldflags;
	oldflags.cznv = regflags.cznv;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(4);
		regflags.cznv = oldflags.cznv;
		exception3_write_access(opcode, dsta, 1, src, 1);
		return;
	}
	ipl_fetch_now();
	x_put_word(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return;
	}
	m68k_incpci(2);
	if(!loop_mode) {
		regs.ir = regs.irc;
		opcode = regs.ir;
		get_word_ce000_prefetch(2);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 2, pcoffset);
			return;
		}
	} else {
		loop_mode = 0;
		loop_mode |= 2;
		loop_mode |= 4 << 16;
	}
	regs.loop_mode = loop_mode;
	return;
}
/* 8 (1/1) */
/* 2 0,0   */

/* MOVE.W (An),(An) */
void REGPARAM2 op_3090_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 12; 
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access2(opcode, srca, 1, 1);
		return;
	}
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(4);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		exception3_write_access(opcode, dsta, 1, src, 1);
		return;
	}
	ipl_fetch_now();
	x_put_word(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return;
	}
	m68k_incpci(2);
	if(!loop_mode) {
		regs.ir = regs.irc;
		opcode = regs.ir;
		get_word_ce000_prefetch(2);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 2, pcoffset);
			return;
		}
	} else {
		loop_mode = 0;
		loop_mode |= 2;
		loop_mode |= 2 << 16;
	}
	regs.loop_mode = loop_mode;
	return;
}
/* 12 (2/1) */
/* 2 0,0   */

/* MOVE.W (An)+,(An) */
void REGPARAM2 op_3098_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 12; 
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_areg(regs, srcreg) += 2 + 0;
		m68k_incpci(2);
		exception3_read_access2(opcode, srca, 1, 1);
		return;
	}
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) += 2 + 0;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	m68k_areg(regs, srcreg) += 2;
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(4);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		exception3_write_access(opcode, dsta, 1, src, 1);
		return;
	}
	ipl_fetch_now();
	x_put_word(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return;
	}
	m68k_incpci(2);
	if(!loop_mode) {
		regs.ir = regs.irc;
		opcode = regs.ir;
		get_word_ce000_prefetch(2);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 2, pcoffset);
			return;
		}
	} else {
		loop_mode = 0;
		loop_mode |= 2;
		loop_mode |= 2 << 16;
	}
	regs.loop_mode = loop_mode;
	return;
}
/* 12 (2/1) */
/* 2 0,0   */

/* MOVE.W -(An),(An) */
void REGPARAM2 op_30a0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 14; 
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - 2;
	do_cycles_ce000_internal(2);
	if (srca & 1) {
		m68k_areg(regs, srcreg) = srca;
		m68k_incpci(2);
		exception3_read_access2(opcode, srca, 1, 1);
		return;
	}
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	m68k_areg(regs, srcreg) = srca;
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(4);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		exception3_write_access(opcode, dsta, 1, src, 1);
		return;
	}
	ipl_fetch_now();
	x_put_word(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return;
	}
	m68k_incpci(2);
	if(!loop_mode) {
		regs.ir = regs.irc;
		opcode = regs.ir;
		get_word_ce000_prefetch(2);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 2, pcoffset);
			return;
		}
	} else {
		loop_mode = 0;
		loop_mode |= 2;
		loop_mode |= 2 << 16;
	}
	regs.loop_mode = loop_mode;
	return;
}
/* 14 (2/1) */
/* 2 0,0   */

/* MOVE.W (d16,An),(An) */
void REGPARAM2 op_30a8_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(6);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		exception3_write_access(opcode, dsta, 1, src, 1);
		return;
	}
	ipl_fetch_now();
	x_put_word(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* MOVE.W (d8,An,Xn),(An) */
void REGPARAM2 op_30b0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	do_cycles_ce000_internal(2);
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(6);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		exception3_write_access(opcode, dsta, 1, src, 1);
		return;
	}
	ipl_fetch_now();
	x_put_word(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 18 (3/1) */
/* 4 4,0   */

/* MOVE.W (xxx).W,(An) */
void REGPARAM2 op_30b8_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	if (srca & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(6);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		exception3_write_access(opcode, dsta, 1, src, 1);
		return;
	}
	ipl_fetch_now();
	x_put_word(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* MOVE.W (xxx).L,(An) */
void REGPARAM2 op_30b9_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	srca = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	srca |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	if (srca & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(8);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		exception3_write_access(opcode, dsta, 1, src, 1);
		return;
	}
	ipl_fetch_now();
	x_put_word(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return;
	}
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 20 (4/1) */
/* 6 0,0   */

/* MOVE.W (d16,PC),(An) */
void REGPARAM2 op_30ba_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = m68k_getpci() + 2;
	srca += (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 2);
		return;
	}
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(6);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		exception3_write_access(opcode, dsta, 1, src, 1);
		return;
	}
	ipl_fetch_now();
	x_put_word(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* MOVE.W (d8,PC,Xn),(An) */
void REGPARAM2 op_30bb_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	uaecptr tmppc = m68k_getpci() + 2;
	do_cycles_ce000_internal(2);
	srca = get_disp_ea_000(tmppc, get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 2);
		return;
	}
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(6);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		exception3_write_access(opcode, dsta, 1, src, 1);
		return;
	}
	ipl_fetch_now();
	x_put_word(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 18 (3/1) */
/* 4 4,0   */

/* MOVE.W #<data>.W,(An) */
void REGPARAM2 op_30bc_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 12; 
	uae_s16 src = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	struct flag_struct oldflags;
	oldflags.cznv = regflags.cznv;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(6);
		regflags.cznv = oldflags.cznv;
		exception3_write_access(opcode, dsta, 1, src, 1);
		return;
	}
	ipl_fetch_now();
	x_put_word(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 12 (2/1) */
/* 4 0,0   */

/* MOVE.W Dn,(An)+ */
void REGPARAM2 op_30c0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 8;  
	int loop_mode = regs.loop_mode;
	uae_s16 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	m68k_areg(regs, dstreg) += 2;
	struct flag_struct oldflags;
	oldflags.cznv = regflags.cznv;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	ipl_fetch_next_pre();
	if (dsta & 1) {
		m68k_incpci(4);
		regflags.cznv = oldflags.cznv;
		m68k_areg(regs, dstreg) = dsta;
		exception3_write_access(opcode, dsta, 1, src, 1);
		return;
	}
	x_put_word(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, dstreg) -= 2;
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return;
	}
	m68k_incpci(2);
	if(!loop_mode) {
		regs.ir = regs.irc;
		opcode = regs.ir;
		get_word_ce000_prefetch(2);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 2, pcoffset);
			return;
		}
	} else {
		loop_mode = 0;
		loop_mode |= 2;
		loop_mode |= 4 << 16;
	}
	regs.loop_mode = loop_mode;
	return;
}
/* 8 (1/1) */
/* 2 0,0   */

/* MOVE.W An,(An)+ */
void REGPARAM2 op_30c8_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 8;  
	int loop_mode = regs.loop_mode;
	uae_s16 src = m68k_areg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	m68k_areg(regs, dstreg) += 2;
	struct flag_struct oldflags;
	oldflags.cznv = regflags.cznv;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	ipl_fetch_next_pre();
	if (dsta & 1) {
		m68k_incpci(4);
		regflags.cznv = oldflags.cznv;
		m68k_areg(regs, dstreg) = dsta;
		exception3_write_access(opcode, dsta, 1, src, 1);
		return;
	}
	x_put_word(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, dstreg) -= 2;
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return;
	}
	m68k_incpci(2);
	if(!loop_mode) {
		regs.ir = regs.irc;
		opcode = regs.ir;
		get_word_ce000_prefetch(2);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 2, pcoffset);
			return;
		}
	} else {
		loop_mode = 0;
		loop_mode |= 2;
		loop_mode |= 4 << 16;
	}
	regs.loop_mode = loop_mode;
	return;
}
/* 8 (1/1) */
/* 2 0,0   */

/* MOVE.W (An),(An)+ */
void REGPARAM2 op_30d0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 12; 
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access2(opcode, srca, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	m68k_areg(regs, dstreg) += 2;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(4);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		m68k_areg(regs, dstreg) = dsta;
		exception3_write_access(opcode, dsta, 1, src, 1);
		return;
	}
	x_put_word(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, dstreg) -= 2;
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return;
	}
	m68k_incpci(2);
	if(!loop_mode) {
		regs.ir = regs.irc;
		opcode = regs.ir;
		get_word_ce000_prefetch(2);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 2, pcoffset);
			return;
		}
	} else {
		loop_mode = 0;
		loop_mode |= 2;
		loop_mode |= 2 << 16;
	}
	regs.loop_mode = loop_mode;
	return;
}
/* 12 (2/1) */
/* 2 0,0   */

/* MOVE.W (An)+,(An)+ */
void REGPARAM2 op_30d8_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 12; 
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_areg(regs, srcreg) += 2 + 0;
		m68k_incpci(2);
		exception3_read_access2(opcode, srca, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) += 2 + 0;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	m68k_areg(regs, srcreg) += 2;
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	m68k_areg(regs, dstreg) += 2;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(4);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		m68k_areg(regs, dstreg) = dsta;
		exception3_write_access(opcode, dsta, 1, src, 1);
		return;
	}
	x_put_word(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, dstreg) -= 2;
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return;
	}
	m68k_incpci(2);
	if(!loop_mode) {
		regs.ir = regs.irc;
		opcode = regs.ir;
		get_word_ce000_prefetch(2);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 2, pcoffset);
			return;
		}
	} else {
		loop_mode = 0;
		loop_mode |= 2;
		loop_mode |= 2 << 16;
	}
	regs.loop_mode = loop_mode;
	return;
}
/* 12 (2/1) */
/* 2 0,0   */

/* MOVE.W -(An),(An)+ */
void REGPARAM2 op_30e0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 14; 
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - 2;
	do_cycles_ce000_internal(2);
	if (srca & 1) {
		m68k_areg(regs, srcreg) = srca;
		m68k_incpci(2);
		exception3_read_access2(opcode, srca, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	m68k_areg(regs, srcreg) = srca;
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	m68k_areg(regs, dstreg) += 2;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(4);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		m68k_areg(regs, dstreg) = dsta;
		exception3_write_access(opcode, dsta, 1, src, 1);
		return;
	}
	x_put_word(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, dstreg) -= 2;
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return;
	}
	m68k_incpci(2);
	if(!loop_mode) {
		regs.ir = regs.irc;
		opcode = regs.ir;
		get_word_ce000_prefetch(2);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 2, pcoffset);
			return;
		}
	} else {
		loop_mode = 0;
		loop_mode |= 2;
		loop_mode |= 2 << 16;
	}
	regs.loop_mode = loop_mode;
	return;
}
/* 14 (2/1) */
/* 2 0,0   */

/* MOVE.W (d16,An),(An)+ */
void REGPARAM2 op_30e8_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	m68k_areg(regs, dstreg) += 2;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(6);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		m68k_areg(regs, dstreg) = dsta;
		exception3_write_access(opcode, dsta, 1, src, 1);
		return;
	}
	x_put_word(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, dstreg) -= 2;
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* MOVE.W (d8,An,Xn),(An)+ */
void REGPARAM2 op_30f0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	do_cycles_ce000_internal(2);
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	m68k_areg(regs, dstreg) += 2;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(6);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		m68k_areg(regs, dstreg) = dsta;
		exception3_write_access(opcode, dsta, 1, src, 1);
		return;
	}
	x_put_word(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, dstreg) -= 2;
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 18 (3/1) */
/* 4 4,0   */

/* MOVE.W (xxx).W,(An)+ */
void REGPARAM2 op_30f8_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	if (srca & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	m68k_areg(regs, dstreg) += 2;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(6);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		m68k_areg(regs, dstreg) = dsta;
		exception3_write_access(opcode, dsta, 1, src, 1);
		return;
	}
	x_put_word(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, dstreg) -= 2;
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* MOVE.W (xxx).L,(An)+ */
void REGPARAM2 op_30f9_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	srca = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	srca |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	if (srca & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	m68k_areg(regs, dstreg) += 2;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(8);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		m68k_areg(regs, dstreg) = dsta;
		exception3_write_access(opcode, dsta, 1, src, 1);
		return;
	}
	x_put_word(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		m68k_areg(regs, dstreg) -= 2;
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return;
	}
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 20 (4/1) */
/* 6 0,0   */

/* MOVE.W (d16,PC),(An)+ */
void REGPARAM2 op_30fa_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = m68k_getpci() + 2;
	srca += (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 2);
		return;
	}
	ipl_fetch_now();
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	m68k_areg(regs, dstreg) += 2;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(6);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		m68k_areg(regs, dstreg) = dsta;
		exception3_write_access(opcode, dsta, 1, src, 1);
		return;
	}
	x_put_word(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, dstreg) -= 2;
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* MOVE.W (d8,PC,Xn),(An)+ */
void REGPARAM2 op_30fb_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	uaecptr tmppc = m68k_getpci() + 2;
	do_cycles_ce000_internal(2);
	srca = get_disp_ea_000(tmppc, get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 2);
		return;
	}
	ipl_fetch_now();
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	m68k_areg(regs, dstreg) += 2;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(6);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		m68k_areg(regs, dstreg) = dsta;
		exception3_write_access(opcode, dsta, 1, src, 1);
		return;
	}
	x_put_word(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, dstreg) -= 2;
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 18 (3/1) */
/* 4 4,0   */

/* MOVE.W #<data>.W,(An)+ */
void REGPARAM2 op_30fc_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 12; 
	ipl_fetch_now();
	uae_s16 src = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	m68k_areg(regs, dstreg) += 2;
	struct flag_struct oldflags;
	oldflags.cznv = regflags.cznv;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(6);
		regflags.cznv = oldflags.cznv;
		m68k_areg(regs, dstreg) = dsta;
		exception3_write_access(opcode, dsta, 1, src, 1);
		return;
	}
	x_put_word(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, dstreg) -= 2;
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 12 (2/1) */
/* 4 0,0   */

/* MOVE.W Dn,-(An) */
void REGPARAM2 op_3100_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 8;  
	ipl_fetch_next_pre();
	uae_s16 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - 2;
	m68k_areg(regs, dstreg) = dsta;
	regs.ir = regs.irc;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		m68k_areg(regs, dstreg) += 2;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	struct flag_struct oldflags;
	oldflags.cznv = regflags.cznv;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_areg(regs, dstreg) = dsta;
		m68k_incpci(4);
		get_word_ce000_prefetch((m68k_getpci() & 1) ? -1 : 0);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		m68k_areg(regs, dstreg) = dsta;
		exception3_write_access(opcode, dsta, 1, src, 1);
		return;
	}
	x_put_word(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 8 (1/1) */
/* 2 0,0   */

/* MOVE.W An,-(An) */
void REGPARAM2 op_3108_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 8;  
	ipl_fetch_next_pre();
	uae_s16 src = m68k_areg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - 2;
	m68k_areg(regs, dstreg) = dsta;
	regs.ir = regs.irc;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		m68k_areg(regs, dstreg) += 2;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	struct flag_struct oldflags;
	oldflags.cznv = regflags.cznv;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_areg(regs, dstreg) = dsta;
		m68k_incpci(4);
		get_word_ce000_prefetch((m68k_getpci() & 1) ? -1 : 0);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		m68k_areg(regs, dstreg) = dsta;
		exception3_write_access(opcode, dsta, 1, src, 1);
		return;
	}
	x_put_word(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 8 (1/1) */
/* 2 0,0   */

/* MOVE.W (An),-(An) */
void REGPARAM2 op_3110_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 12; 
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access2(opcode, srca, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - 2;
	m68k_areg(regs, dstreg) = dsta;
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_ce000_prefetch(4);
		if(hardware_bus_error) {
			int pcoffset = 0;
			m68k_areg(regs, dstreg) += 2;
			ccr_68000_word_move_ae_normal((uae_s16)src);
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return;
		}
		opcode = regs.ir;
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if(loop_mode & 0xfffe) {
		do_cycles_ce000_internal(loop_mode & 0xfffe);
		loop_mode = 1;
	}
	if (dsta & 1) {
		m68k_areg(regs, dstreg) = dsta;
		m68k_incpci(4);
		get_word_ce000_prefetch((m68k_getpci() & 1) ? -1 : 0);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		m68k_areg(regs, dstreg) = dsta;
		exception3_write_access(opcode, dsta, 1, src, 1);
		return;
	}
	x_put_word(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return;
	}
	m68k_incpci(2);
	regs.loop_mode = loop_mode;
	return;
}
/* 12 (2/1) */
/* 2 0,0   */

/* MOVE.W (An)+,-(An) */
void REGPARAM2 op_3118_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 12; 
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_areg(regs, srcreg) += 2 + 0;
		m68k_incpci(2);
		exception3_read_access2(opcode, srca, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) += 2 + 0;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	m68k_areg(regs, srcreg) += 2;
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - 2;
	m68k_areg(regs, dstreg) = dsta;
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_ce000_prefetch(4);
		if(hardware_bus_error) {
			int pcoffset = 0;
			m68k_areg(regs, dstreg) += 2;
			ccr_68000_word_move_ae_normal((uae_s16)src);
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return;
		}
		opcode = regs.ir;
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if(loop_mode & 0xfffe) {
		do_cycles_ce000_internal(loop_mode & 0xfffe);
		loop_mode = 1;
	}
	if (dsta & 1) {
		m68k_areg(regs, dstreg) = dsta;
		m68k_incpci(4);
		get_word_ce000_prefetch((m68k_getpci() & 1) ? -1 : 0);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		m68k_areg(regs, dstreg) = dsta;
		exception3_write_access(opcode, dsta, 1, src, 1);
		return;
	}
	x_put_word(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return;
	}
	m68k_incpci(2);
	regs.loop_mode = loop_mode;
	return;
}
/* 12 (2/1) */
/* 2 0,0   */

/* MOVE.W -(An),-(An) */
void REGPARAM2 op_3120_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 14; 
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - 2;
	do_cycles_ce000_internal(2);
	if (srca & 1) {
		m68k_areg(regs, srcreg) = srca;
		m68k_incpci(2);
		exception3_read_access2(opcode, srca, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	m68k_areg(regs, srcreg) = srca;
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - 2;
	m68k_areg(regs, dstreg) = dsta;
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_ce000_prefetch(4);
		if(hardware_bus_error) {
			int pcoffset = 0;
			m68k_areg(regs, dstreg) += 2;
			ccr_68000_word_move_ae_normal((uae_s16)src);
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return;
		}
		opcode = regs.ir;
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if(loop_mode & 0xfffe) {
		do_cycles_ce000_internal(loop_mode & 0xfffe);
		loop_mode = 1;
	}
	if (dsta & 1) {
		m68k_areg(regs, dstreg) = dsta;
		m68k_incpci(4);
		get_word_ce000_prefetch((m68k_getpci() & 1) ? -1 : 0);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		m68k_areg(regs, dstreg) = dsta;
		exception3_write_access(opcode, dsta, 1, src, 1);
		return;
	}
	x_put_word(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return;
	}
	m68k_incpci(2);
	regs.loop_mode = loop_mode;
	return;
}
/* 14 (2/1) */
/* 2 0,0   */

/* MOVE.W (d16,An),-(An) */
void REGPARAM2 op_3128_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - 2;
	m68k_areg(regs, dstreg) = dsta;
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		m68k_areg(regs, dstreg) += 2;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_areg(regs, dstreg) = dsta;
		m68k_incpci(6);
		get_word_ce000_prefetch((m68k_getpci() & 1) ? -1 : 0);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		m68k_areg(regs, dstreg) = dsta;
		exception3_write_access(opcode, dsta, 1, src, 1);
		return;
	}
	x_put_word(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* MOVE.W (d8,An,Xn),-(An) */
void REGPARAM2 op_3130_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	do_cycles_ce000_internal(2);
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - 2;
	m68k_areg(regs, dstreg) = dsta;
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		m68k_areg(regs, dstreg) += 2;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_areg(regs, dstreg) = dsta;
		m68k_incpci(6);
		get_word_ce000_prefetch((m68k_getpci() & 1) ? -1 : 0);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		m68k_areg(regs, dstreg) = dsta;
		exception3_write_access(opcode, dsta, 1, src, 1);
		return;
	}
	x_put_word(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 18 (3/1) */
/* 4 4,0   */

/* MOVE.W (xxx).W,-(An) */
void REGPARAM2 op_3138_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	if (srca & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - 2;
	m68k_areg(regs, dstreg) = dsta;
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		m68k_areg(regs, dstreg) += 2;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_areg(regs, dstreg) = dsta;
		m68k_incpci(6);
		get_word_ce000_prefetch((m68k_getpci() & 1) ? -1 : 0);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		m68k_areg(regs, dstreg) = dsta;
		exception3_write_access(opcode, dsta, 1, src, 1);
		return;
	}
	x_put_word(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* MOVE.W (xxx).L,-(An) */
void REGPARAM2 op_3139_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	srca = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	srca |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	if (srca & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - 2;
	m68k_areg(regs, dstreg) = dsta;
	regs.ir = regs.irc;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		m68k_areg(regs, dstreg) += 2;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	opcode = regs.ir;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_areg(regs, dstreg) = dsta;
		m68k_incpci(8);
		get_word_ce000_prefetch((m68k_getpci() & 1) ? -1 : 0);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		m68k_areg(regs, dstreg) = dsta;
		exception3_write_access(opcode, dsta, 1, src, 1);
		return;
	}
	x_put_word(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 20 (4/1) */
/* 6 0,0   */

/* MOVE.W (d16,PC),-(An) */
void REGPARAM2 op_313a_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = m68k_getpci() + 2;
	srca += (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 2);
		return;
	}
	ipl_fetch_now();
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - 2;
	m68k_areg(regs, dstreg) = dsta;
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		m68k_areg(regs, dstreg) += 2;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_areg(regs, dstreg) = dsta;
		m68k_incpci(6);
		get_word_ce000_prefetch((m68k_getpci() & 1) ? -1 : 0);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		m68k_areg(regs, dstreg) = dsta;
		exception3_write_access(opcode, dsta, 1, src, 1);
		return;
	}
	x_put_word(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* MOVE.W (d8,PC,Xn),-(An) */
void REGPARAM2 op_313b_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	uaecptr tmppc = m68k_getpci() + 2;
	do_cycles_ce000_internal(2);
	srca = get_disp_ea_000(tmppc, get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 2);
		return;
	}
	ipl_fetch_now();
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - 2;
	m68k_areg(regs, dstreg) = dsta;
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		m68k_areg(regs, dstreg) += 2;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_areg(regs, dstreg) = dsta;
		m68k_incpci(6);
		get_word_ce000_prefetch((m68k_getpci() & 1) ? -1 : 0);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		m68k_areg(regs, dstreg) = dsta;
		exception3_write_access(opcode, dsta, 1, src, 1);
		return;
	}
	x_put_word(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 18 (3/1) */
/* 4 4,0   */

/* MOVE.W #<data>.W,-(An) */
void REGPARAM2 op_313c_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 12; 
	ipl_fetch_now();
	uae_s16 src = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - 2;
	m68k_areg(regs, dstreg) = dsta;
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		m68k_areg(regs, dstreg) += 2;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	struct flag_struct oldflags;
	oldflags.cznv = regflags.cznv;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_areg(regs, dstreg) = dsta;
		m68k_incpci(6);
		get_word_ce000_prefetch((m68k_getpci() & 1) ? -1 : 0);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		m68k_areg(regs, dstreg) = dsta;
		exception3_write_access(opcode, dsta, 1, src, 1);
		return;
	}
	x_put_word(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 12 (2/1) */
/* 4 0,0   */

/* MOVE.W Dn,(d16,An) */
void REGPARAM2 op_3140_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 12; 
	uae_s16 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	struct flag_struct oldflags;
	oldflags.cznv = regflags.cznv;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(4);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		exception3_write_access(opcode, dsta, 1, src, 1);
		return;
	}
	ipl_fetch_now();
	x_put_word(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 12 (2/1) */
/* 4 0,0   */

/* MOVE.W An,(d16,An) */
void REGPARAM2 op_3148_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 12; 
	uae_s16 src = m68k_areg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	struct flag_struct oldflags;
	oldflags.cznv = regflags.cznv;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(4);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		exception3_write_access(opcode, dsta, 1, src, 1);
		return;
	}
	ipl_fetch_now();
	x_put_word(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 12 (2/1) */
/* 4 0,0   */

/* MOVE.W (An),(d16,An) */
void REGPARAM2 op_3150_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access2(opcode, srca, 1, 1);
		return;
	}
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 4, 0);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(4);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		exception3_write_access(opcode, dsta, 1, src, 1);
		return;
	}
	ipl_fetch_now();
	x_put_word(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* MOVE.W (An)+,(d16,An) */
void REGPARAM2 op_3158_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_areg(regs, srcreg) += 2 + 0;
		m68k_incpci(2);
		exception3_read_access2(opcode, srca, 1, 1);
		return;
	}
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) += 2 + 0;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	m68k_areg(regs, srcreg) += 2;
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 4, 0);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(4);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		exception3_write_access(opcode, dsta, 1, src, 1);
		return;
	}
	ipl_fetch_now();
	x_put_word(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* MOVE.W -(An),(d16,An) */
void REGPARAM2 op_3160_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - 2;
	do_cycles_ce000_internal(2);
	if (srca & 1) {
		m68k_areg(regs, srcreg) = srca;
		m68k_incpci(2);
		exception3_read_access2(opcode, srca, 1, 1);
		return;
	}
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	m68k_areg(regs, srcreg) = srca;
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 4, 0);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(4);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		exception3_write_access(opcode, dsta, 1, src, 1);
		return;
	}
	ipl_fetch_now();
	x_put_word(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 18 (3/1) */
/* 4 0,0   */

/* MOVE.W (d16,An),(d16,An) */
void REGPARAM2 op_3168_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 6, 0);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(6);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		exception3_write_access(opcode, dsta, 1, src, 1);
		return;
	}
	ipl_fetch_now();
	x_put_word(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return;
	}
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 20 (4/1) */
/* 6 0,0   */

/* MOVE.W (d8,An,Xn),(d16,An) */
void REGPARAM2 op_3170_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 22; 
	uaecptr srca;
	do_cycles_ce000_internal(2);
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 6, 0);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(6);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		exception3_write_access(opcode, dsta, 1, src, 1);
		return;
	}
	ipl_fetch_now();
	x_put_word(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return;
	}
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 22 (4/1) */
/* 6 6,0   */

/* MOVE.W (xxx).W,(d16,An) */
void REGPARAM2 op_3178_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	if (srca & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 6, 0);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(6);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		exception3_write_access(opcode, dsta, 1, src, 1);
		return;
	}
	ipl_fetch_now();
	x_put_word(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return;
	}
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 20 (4/1) */
/* 6 0,0   */

/* MOVE.W (xxx).L,(d16,An) */
void REGPARAM2 op_3179_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 24; 
	uaecptr srca;
	srca = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	srca |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	if (srca & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 8, 0);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(8);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		exception3_write_access(opcode, dsta, 1, src, 1);
		return;
	}
	ipl_fetch_now();
	x_put_word(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return;
	}
	m68k_incpci(8);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 24 (5/1) */
/* 8 0,0   */

/* MOVE.W (d16,PC),(d16,An) */
void REGPARAM2 op_317a_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	srca = m68k_getpci() + 2;
	srca += (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 2);
		return;
	}
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 6, 0);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(6);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		exception3_write_access(opcode, dsta, 1, src, 1);
		return;
	}
	ipl_fetch_now();
	x_put_word(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return;
	}
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 20 (4/1) */
/* 6 0,0   */

/* MOVE.W (d8,PC,Xn),(d16,An) */
void REGPARAM2 op_317b_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 22; 
	uaecptr srca;
	uaecptr tmppc = m68k_getpci() + 2;
	do_cycles_ce000_internal(2);
	srca = get_disp_ea_000(tmppc, get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 2);
		return;
	}
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 6, 0);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(6);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		exception3_write_access(opcode, dsta, 1, src, 1);
		return;
	}
	ipl_fetch_now();
	x_put_word(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return;
	}
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 22 (4/1) */
/* 6 6,0   */

/* MOVE.W #<data>.W,(d16,An) */
void REGPARAM2 op_317c_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 16; 
	uae_s16 src = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, 0);
		return;
	}
	struct flag_struct oldflags;
	oldflags.cznv = regflags.cznv;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(6);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		exception3_write_access(opcode, dsta, 1, src, 1);
		return;
	}
	ipl_fetch_now();
	x_put_word(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return;
	}
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 16 (3/1) */
/* 6 0,0   */

/* MOVE.W Dn,(d8,An,Xn) */
void REGPARAM2 op_3180_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 14; 
	uae_s16 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	do_cycles_ce000_internal(2);
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	struct flag_struct oldflags;
	oldflags.cznv = regflags.cznv;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(4);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		exception3_write_access(opcode, dsta, 1, src, 1);
		return;
	}
	ipl_fetch_now();
	x_put_word(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 14 (2/1) */
/* 4 4,0   */

/* MOVE.W An,(d8,An,Xn) */
void REGPARAM2 op_3188_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 14; 
	uae_s16 src = m68k_areg(regs, srcreg);
	uaecptr dsta;
	do_cycles_ce000_internal(2);
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	struct flag_struct oldflags;
	oldflags.cznv = regflags.cznv;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(4);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		exception3_write_access(opcode, dsta, 1, src, 1);
		return;
	}
	ipl_fetch_now();
	x_put_word(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 14 (2/1) */
/* 4 4,0   */

/* MOVE.W (An),(d8,An,Xn) */
void REGPARAM2 op_3190_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access2(opcode, srca, 1, 1);
		return;
	}
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	uaecptr dsta;
	do_cycles_ce000_internal(2);
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 4, 0);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(4);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		exception3_write_access(opcode, dsta, 1, src, 1);
		return;
	}
	ipl_fetch_now();
	x_put_word(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 18 (3/1) */
/* 4 4,0   */

/* MOVE.W (An)+,(d8,An,Xn) */
void REGPARAM2 op_3198_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_areg(regs, srcreg) += 2 + 0;
		m68k_incpci(2);
		exception3_read_access2(opcode, srca, 1, 1);
		return;
	}
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) += 2 + 0;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	m68k_areg(regs, srcreg) += 2;
	uaecptr dsta;
	do_cycles_ce000_internal(2);
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 4, 0);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(4);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		exception3_write_access(opcode, dsta, 1, src, 1);
		return;
	}
	ipl_fetch_now();
	x_put_word(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 18 (3/1) */
/* 4 4,0   */

/* MOVE.W -(An),(d8,An,Xn) */
void REGPARAM2 op_31a0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - 2;
	do_cycles_ce000_internal(2);
	if (srca & 1) {
		m68k_areg(regs, srcreg) = srca;
		m68k_incpci(2);
		exception3_read_access2(opcode, srca, 1, 1);
		return;
	}
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	m68k_areg(regs, srcreg) = srca;
	uaecptr dsta;
	do_cycles_ce000_internal(2);
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 4, 0);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(4);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		exception3_write_access(opcode, dsta, 1, src, 1);
		return;
	}
	ipl_fetch_now();
	x_put_word(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 20 (3/1) */
/* 4 4,0   */

/* MOVE.W (d16,An),(d8,An,Xn) */
void REGPARAM2 op_31a8_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 22; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	uaecptr dsta;
	do_cycles_ce000_internal(2);
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_ce000_prefetch(6));
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 6, 0);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(6);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		exception3_write_access(opcode, dsta, 1, src, 1);
		return;
	}
	ipl_fetch_now();
	x_put_word(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return;
	}
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 22 (4/1) */
/* 6 4,0   */

/* MOVE.W (d8,An,Xn),(d8,An,Xn) */
void REGPARAM2 op_31b0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 24; 
	uaecptr srca;
	do_cycles_ce000_internal(2);
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	uaecptr dsta;
	do_cycles_ce000_internal(2);
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_ce000_prefetch(6));
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 6, 0);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(6);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		exception3_write_access(opcode, dsta, 1, src, 1);
		return;
	}
	ipl_fetch_now();
	x_put_word(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return;
	}
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 24 (4/1) */
/* 6 6,4   */

/* MOVE.W (xxx).W,(d8,An,Xn) */
void REGPARAM2 op_31b8_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 22; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	if (srca & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	uaecptr dsta;
	do_cycles_ce000_internal(2);
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_ce000_prefetch(6));
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 6, 0);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(6);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		exception3_write_access(opcode, dsta, 1, src, 1);
		return;
	}
	ipl_fetch_now();
	x_put_word(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return;
	}
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 22 (4/1) */
/* 6 4,0   */

/* MOVE.W (xxx).L,(d8,An,Xn) */
void REGPARAM2 op_31b9_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 26; 
	uaecptr srca;
	srca = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	srca |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	if (srca & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	uaecptr dsta;
	do_cycles_ce000_internal(2);
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_ce000_prefetch(8));
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 8, 0);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(8);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		exception3_write_access(opcode, dsta, 1, src, 1);
		return;
	}
	ipl_fetch_now();
	x_put_word(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return;
	}
	m68k_incpci(8);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 26 (5/1) */
/* 8 4,0   */

/* MOVE.W (d16,PC),(d8,An,Xn) */
void REGPARAM2 op_31ba_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 22; 
	uaecptr srca;
	srca = m68k_getpci() + 2;
	srca += (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 2);
		return;
	}
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return;
	}
	uaecptr dsta;
	do_cycles_ce000_internal(2);
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_ce000_prefetch(6));
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 6, 0);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(6);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		exception3_write_access(opcode, dsta, 1, src, 1);
		return;
	}
	ipl_fetch_now();
	x_put_word(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return;
	}
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 22 (4/1) */
/* 6 4,0   */

/* MOVE.W (d8,PC,Xn),(d8,An,Xn) */
void REGPARAM2 op_31bb_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 24; 
	uaecptr srca;
	uaecptr tmppc = m68k_getpci() + 2;
	do_cycles_ce000_internal(2);
	srca = get_disp_ea_000(tmppc, get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 2);
		return;
	}
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return;
	}
	uaecptr dsta;
	do_cycles_ce000_internal(2);
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_ce000_prefetch(6));
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 6, 0);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(6);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		exception3_write_access(opcode, dsta, 1, src, 1);
		return;
	}
	ipl_fetch_now();
	x_put_word(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return;
	}
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 24 (4/1) */
/* 6 6,4   */

/* MOVE.W #<data>.W,(d8,An,Xn) */
void REGPARAM2 op_31bc_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 18; 
	uae_s16 src = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr dsta;
	do_cycles_ce000_internal(2);
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_ce000_prefetch(6));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, 0);
		return;
	}
	struct flag_struct oldflags;
	oldflags.cznv = regflags.cznv;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(6);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		exception3_write_access(opcode, dsta, 1, src, 1);
		return;
	}
	ipl_fetch_now();
	x_put_word(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return;
	}
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 18 (3/1) */
/* 6 4,0   */

/* MOVE.W Dn,(xxx).W */
void REGPARAM2 op_31c0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 30;
	CurrentInstrCycles = 12; 
	uae_s16 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 4, 0);
		return;
	}
	struct flag_struct oldflags;
	oldflags.cznv = regflags.cznv;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(4);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		exception3_write_access(opcode, dsta, 1, src, 1);
		return;
	}
	x_put_word(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return;
	}
	ipl_fetch_next();
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 12 (2/1) */
/* 4 0,0   */

/* MOVE.W An,(xxx).W */
void REGPARAM2 op_31c8_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 30;
	CurrentInstrCycles = 12; 
	uae_s16 src = m68k_areg(regs, srcreg);
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 4, 0);
		return;
	}
	struct flag_struct oldflags;
	oldflags.cznv = regflags.cznv;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(4);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		exception3_write_access(opcode, dsta, 1, src, 1);
		return;
	}
	x_put_word(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return;
	}
	ipl_fetch_next();
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 12 (2/1) */
/* 4 0,0   */

/* MOVE.W (An),(xxx).W */
void REGPARAM2 op_31d0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 30;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access2(opcode, srca, 1, 1);
		return;
	}
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 4, 0);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(4);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		exception3_write_access(opcode, dsta, 1, src, 1);
		return;
	}
	x_put_word(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return;
	}
	ipl_fetch_next();
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* MOVE.W (An)+,(xxx).W */
void REGPARAM2 op_31d8_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 30;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_areg(regs, srcreg) += 2 + 0;
		m68k_incpci(2);
		exception3_read_access2(opcode, srca, 1, 1);
		return;
	}
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) += 2 + 0;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	m68k_areg(regs, srcreg) += 2;
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 4, 0);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(4);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		exception3_write_access(opcode, dsta, 1, src, 1);
		return;
	}
	x_put_word(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return;
	}
	ipl_fetch_next();
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* MOVE.W -(An),(xxx).W */
void REGPARAM2 op_31e0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 30;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - 2;
	do_cycles_ce000_internal(2);
	if (srca & 1) {
		m68k_areg(regs, srcreg) = srca;
		m68k_incpci(2);
		exception3_read_access2(opcode, srca, 1, 1);
		return;
	}
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	m68k_areg(regs, srcreg) = srca;
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 4, 0);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(4);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		exception3_write_access(opcode, dsta, 1, src, 1);
		return;
	}
	x_put_word(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return;
	}
	ipl_fetch_next();
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 18 (3/1) */
/* 4 0,0   */

/* MOVE.W (d16,An),(xxx).W */
void REGPARAM2 op_31e8_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 30;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 6, 0);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(6);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		exception3_write_access(opcode, dsta, 1, src, 1);
		return;
	}
	x_put_word(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return;
	}
	ipl_fetch_next();
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 20 (4/1) */
/* 6 0,0   */

/* MOVE.W (d8,An,Xn),(xxx).W */
void REGPARAM2 op_31f0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 30;
	CurrentInstrCycles = 22; 
	uaecptr srca;
	do_cycles_ce000_internal(2);
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 6, 0);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(6);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		exception3_write_access(opcode, dsta, 1, src, 1);
		return;
	}
	x_put_word(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return;
	}
	ipl_fetch_next();
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 22 (4/1) */
/* 6 6,0   */

/* MOVE.W (xxx).W,(xxx).W */
void REGPARAM2 op_31f8_13_ff(uae_u32 opcode)
{
	OpcodeFamily = 30;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	if (srca & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 6, 0);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(6);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		exception3_write_access(opcode, dsta, 1, src, 1);
		return;
	}
	x_put_word(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return;
	}
	ipl_fetch_next();
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 20 (4/1) */
/* 6 0,0   */

/* MOVE.W (xxx).L,(xxx).W */
void REGPARAM2 op_31f9_13_ff(uae_u32 opcode)
{
	OpcodeFamily = 30;
	CurrentInstrCycles = 24; 
	uaecptr srca;
	srca = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	srca |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	if (srca & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 8, 0);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(8);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		exception3_write_access(opcode, dsta, 1, src, 1);
		return;
	}
	x_put_word(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return;
	}
	ipl_fetch_next();
	m68k_incpci(8);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 24 (5/1) */
/* 8 0,0   */

/* MOVE.W (d16,PC),(xxx).W */
void REGPARAM2 op_31fa_13_ff(uae_u32 opcode)
{
	OpcodeFamily = 30;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	srca = m68k_getpci() + 2;
	srca += (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 2);
		return;
	}
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return;
	}
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 6, 0);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(6);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		exception3_write_access(opcode, dsta, 1, src, 1);
		return;
	}
	x_put_word(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return;
	}
	ipl_fetch_next();
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 20 (4/1) */
/* 6 0,0   */

/* MOVE.W (d8,PC,Xn),(xxx).W */
void REGPARAM2 op_31fb_13_ff(uae_u32 opcode)
{
	OpcodeFamily = 30;
	CurrentInstrCycles = 22; 
	uaecptr srca;
	uaecptr tmppc = m68k_getpci() + 2;
	do_cycles_ce000_internal(2);
	srca = get_disp_ea_000(tmppc, get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 2);
		return;
	}
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return;
	}
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 6, 0);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(6);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		exception3_write_access(opcode, dsta, 1, src, 1);
		return;
	}
	x_put_word(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return;
	}
	ipl_fetch_next();
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 22 (4/1) */
/* 6 6,0   */

/* MOVE.W #<data>.W,(xxx).W */
void REGPARAM2 op_31fc_13_ff(uae_u32 opcode)
{
	OpcodeFamily = 30;
	CurrentInstrCycles = 16; 
	uae_s16 src = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 6, 0);
		return;
	}
	struct flag_struct oldflags;
	oldflags.cznv = regflags.cznv;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(6);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		exception3_write_access(opcode, dsta, 1, src, 1);
		return;
	}
	x_put_word(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return;
	}
	ipl_fetch_next();
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 16 (3/1) */
/* 6 0,0   */

/* MOVE.W Dn,(xxx).L */
void REGPARAM2 op_33c0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 30;
	CurrentInstrCycles = 16; 
	uae_s16 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	dsta |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	struct flag_struct oldflags;
	oldflags.cznv = regflags.cznv;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(6);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		exception3_write_access(opcode, dsta, 1, src, 1);
		return;
	}
	x_put_word(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return;
	}
	ipl_fetch_next();
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 16 (3/1) */
/* 6 0,0   */

/* MOVE.W An,(xxx).L */
void REGPARAM2 op_33c8_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 30;
	CurrentInstrCycles = 16; 
	uae_s16 src = m68k_areg(regs, srcreg);
	uaecptr dsta;
	dsta = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	dsta |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	struct flag_struct oldflags;
	oldflags.cznv = regflags.cznv;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(6);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		exception3_write_access(opcode, dsta, 1, src, 1);
		return;
	}
	x_put_word(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return;
	}
	ipl_fetch_next();
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 16 (3/1) */
/* 6 0,0   */

/* MOVE.W (An),(xxx).L */
void REGPARAM2 op_33d0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 30;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access2(opcode, srca, 1, 1);
		return;
	}
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	uaecptr dsta;
	dsta = get_word_ce000_prefetch(4) << 16;
	dsta |= regs.irc;
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 4, 0);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(4);
		regs.irc = dsta >> 16;
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		exception3_write_access(opcode, dsta, 1, src, 1);
		return;
	}
	x_put_word(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		regs.irc = dsta >> 16;
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return;
	}
	ipl_fetch_now();
	m68k_incpci(6);
	get_word_ce000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, 0);
		return;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 20 (4/1) */
/* 6 0,0   */

/* MOVE.W (An)+,(xxx).L */
void REGPARAM2 op_33d8_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 30;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_areg(regs, srcreg) += 2 + 0;
		m68k_incpci(2);
		exception3_read_access2(opcode, srca, 1, 1);
		return;
	}
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) += 2 + 0;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	m68k_areg(regs, srcreg) += 2;
	uaecptr dsta;
	dsta = get_word_ce000_prefetch(4) << 16;
	dsta |= regs.irc;
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 4, 0);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(4);
		regs.irc = dsta >> 16;
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		exception3_write_access(opcode, dsta, 1, src, 1);
		return;
	}
	x_put_word(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		regs.irc = dsta >> 16;
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return;
	}
	ipl_fetch_now();
	m68k_incpci(6);
	get_word_ce000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, 0);
		return;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 20 (4/1) */
/* 6 0,0   */

/* MOVE.W -(An),(xxx).L */
void REGPARAM2 op_33e0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 30;
	CurrentInstrCycles = 22; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - 2;
	do_cycles_ce000_internal(2);
	if (srca & 1) {
		m68k_areg(regs, srcreg) = srca;
		m68k_incpci(2);
		exception3_read_access2(opcode, srca, 1, 1);
		return;
	}
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	m68k_areg(regs, srcreg) = srca;
	uaecptr dsta;
	dsta = get_word_ce000_prefetch(4) << 16;
	dsta |= regs.irc;
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 4, 0);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(4);
		regs.irc = dsta >> 16;
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		exception3_write_access(opcode, dsta, 1, src, 1);
		return;
	}
	x_put_word(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		regs.irc = dsta >> 16;
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return;
	}
	ipl_fetch_now();
	m68k_incpci(6);
	get_word_ce000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, 0);
		return;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 22 (4/1) */
/* 6 0,0   */

/* MOVE.W (d16,An),(xxx).L */
void REGPARAM2 op_33e8_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 30;
	CurrentInstrCycles = 24; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	uaecptr dsta;
	dsta = get_word_ce000_prefetch(6) << 16;
	dsta |= regs.irc;
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 6, 0);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(6);
		regs.irc = dsta >> 16;
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		exception3_write_access(opcode, dsta, 1, src, 1);
		return;
	}
	x_put_word(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		regs.irc = dsta >> 16;
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return;
	}
	ipl_fetch_now();
	m68k_incpci(8);
	get_word_ce000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, 0);
		return;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 24 (5/1) */
/* 8 0,0   */

/* MOVE.W (d8,An,Xn),(xxx).L */
void REGPARAM2 op_33f0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 30;
	CurrentInstrCycles = 26; 
	uaecptr srca;
	do_cycles_ce000_internal(2);
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	uaecptr dsta;
	dsta = get_word_ce000_prefetch(6) << 16;
	dsta |= regs.irc;
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 6, 0);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(6);
		regs.irc = dsta >> 16;
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		exception3_write_access(opcode, dsta, 1, src, 1);
		return;
	}
	x_put_word(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		regs.irc = dsta >> 16;
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return;
	}
	ipl_fetch_now();
	m68k_incpci(8);
	get_word_ce000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, 0);
		return;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 26 (5/1) */
/* 8 8,0   */

/* MOVE.W (xxx).W,(xxx).L */
void REGPARAM2 op_33f8_13_ff(uae_u32 opcode)
{
	OpcodeFamily = 30;
	CurrentInstrCycles = 24; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	if (srca & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	uaecptr dsta;
	dsta = get_word_ce000_prefetch(6) << 16;
	dsta |= regs.irc;
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 6, 0);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(6);
		regs.irc = dsta >> 16;
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		exception3_write_access(opcode, dsta, 1, src, 1);
		return;
	}
	x_put_word(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		regs.irc = dsta >> 16;
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return;
	}
	ipl_fetch_now();
	m68k_incpci(8);
	get_word_ce000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, 0);
		return;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 24 (5/1) */
/* 8 0,0   */

/* MOVE.W (xxx).L,(xxx).L */
void REGPARAM2 op_33f9_13_ff(uae_u32 opcode)
{
	OpcodeFamily = 30;
	CurrentInstrCycles = 28; 
	uaecptr srca;
	srca = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	srca |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	if (srca & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	uaecptr dsta;
	dsta = get_word_ce000_prefetch(8) << 16;
	dsta |= regs.irc;
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 8, 0);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(8);
		regs.irc = dsta >> 16;
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		exception3_write_access(opcode, dsta, 1, src, 1);
		return;
	}
	x_put_word(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		regs.irc = dsta >> 16;
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return;
	}
	ipl_fetch_now();
	m68k_incpci(10);
	get_word_ce000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, 0);
		return;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 28 (6/1) */
/* 10 0,0   */

/* MOVE.W (d16,PC),(xxx).L */
void REGPARAM2 op_33fa_13_ff(uae_u32 opcode)
{
	OpcodeFamily = 30;
	CurrentInstrCycles = 24; 
	uaecptr srca;
	srca = m68k_getpci() + 2;
	srca += (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 2);
		return;
	}
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return;
	}
	uaecptr dsta;
	dsta = get_word_ce000_prefetch(6) << 16;
	dsta |= regs.irc;
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 6, 0);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(6);
		regs.irc = dsta >> 16;
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		exception3_write_access(opcode, dsta, 1, src, 1);
		return;
	}
	x_put_word(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		regs.irc = dsta >> 16;
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return;
	}
	ipl_fetch_now();
	m68k_incpci(8);
	get_word_ce000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, 0);
		return;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 24 (5/1) */
/* 8 0,0   */

/* MOVE.W (d8,PC,Xn),(xxx).L */
void REGPARAM2 op_33fb_13_ff(uae_u32 opcode)
{
	OpcodeFamily = 30;
	CurrentInstrCycles = 26; 
	uaecptr srca;
	uaecptr tmppc = m68k_getpci() + 2;
	do_cycles_ce000_internal(2);
	srca = get_disp_ea_000(tmppc, get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 2);
		return;
	}
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return;
	}
	uaecptr dsta;
	dsta = get_word_ce000_prefetch(6) << 16;
	dsta |= regs.irc;
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 6, 0);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(6);
		regs.irc = dsta >> 16;
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		exception3_write_access(opcode, dsta, 1, src, 1);
		return;
	}
	x_put_word(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		regs.irc = dsta >> 16;
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return;
	}
	ipl_fetch_now();
	m68k_incpci(8);
	get_word_ce000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, 0);
		return;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 26 (5/1) */
/* 8 8,0   */

/* MOVE.W #<data>.W,(xxx).L */
void REGPARAM2 op_33fc_13_ff(uae_u32 opcode)
{
	OpcodeFamily = 30;
	CurrentInstrCycles = 20; 
	uae_s16 src = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr dsta;
	dsta = get_word_ce000_prefetch(6) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return;
	}
	dsta |= get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 8, pcoffset);
		return;
	}
	struct flag_struct oldflags;
	oldflags.cznv = regflags.cznv;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(8);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		exception3_write_access(opcode, dsta, 1, src, 1);
		return;
	}
	x_put_word(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return;
	}
	ipl_fetch_next();
	m68k_incpci(8);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 20 (4/1) */
/* 8 0,0   */

/* NEGX.B Dn */
void REGPARAM2 op_4000_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 16;
	CurrentInstrCycles = 4;  
	uae_s8 src = m68k_dreg(regs, srcreg);
	uae_u32 newv = 0 - src - (GET_XFLG() ? 1 : 0);
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(0)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_VFLG((flgs ^ flgo) & (flgo ^ flgn));
	SET_CFLG(flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
	COPY_CARRY();
	SET_ZFLG(GET_ZFLG() & (((uae_s8)(newv)) == 0));
	SET_NFLG(((uae_s8)(newv)) < 0);
	m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((newv) & 0xff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 4 (1/0) */
/* 2 0,0   */

/* NEGX.B (An) */
void REGPARAM2 op_4010_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 16;
	CurrentInstrCycles = 12; 
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	uae_u32 newv = 0 - src - (GET_XFLG() ? 1 : 0);
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(0)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_VFLG((flgs ^ flgo) & (flgo ^ flgn));
	SET_CFLG(flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
	COPY_CARRY();
	SET_ZFLG(GET_ZFLG() & (((uae_s8)(newv)) == 0));
	SET_NFLG(((uae_s8)(newv)) < 0);
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_ce000_prefetch(4);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return;
		}
		opcode = regs.ir;
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	if(loop_mode & 0xfffe) {
		do_cycles_ce000_internal(loop_mode & 0xfffe);
		loop_mode = 1;
	}
	x_put_byte(srca, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, srca + 0, 0x0, newv, 1);
		return;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return;
}
/* 12 (2/1) */
/* 2 0,0   */

/* NEGX.B (An)+ */
void REGPARAM2 op_4018_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 16;
	CurrentInstrCycles = 12; 
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
	uae_u32 newv = 0 - src - (GET_XFLG() ? 1 : 0);
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(0)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_VFLG((flgs ^ flgo) & (flgo ^ flgn));
	SET_CFLG(flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
	COPY_CARRY();
	SET_ZFLG(GET_ZFLG() & (((uae_s8)(newv)) == 0));
	SET_NFLG(((uae_s8)(newv)) < 0);
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_ce000_prefetch(4);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return;
		}
		opcode = regs.ir;
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	if(loop_mode & 0xfffe) {
		do_cycles_ce000_internal(loop_mode & 0xfffe);
		loop_mode = 1;
	}
	x_put_byte(srca, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, srca + 0, 0x0, newv, 1);
		return;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return;
}
/* 12 (2/1) */
/* 2 0,0   */

/* NEGX.B -(An) */
void REGPARAM2 op_4020_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 16;
	CurrentInstrCycles = 14; 
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
	do_cycles_ce000_internal(2);
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	m68k_areg(regs, srcreg) = srca;
	uae_u32 newv = 0 - src - (GET_XFLG() ? 1 : 0);
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(0)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_VFLG((flgs ^ flgo) & (flgo ^ flgn));
	SET_CFLG(flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
	COPY_CARRY();
	SET_ZFLG(GET_ZFLG() & (((uae_s8)(newv)) == 0));
	SET_NFLG(((uae_s8)(newv)) < 0);
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_ce000_prefetch(4);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return;
		}
		opcode = regs.ir;
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	if(loop_mode & 0xfffe) {
		do_cycles_ce000_internal(loop_mode & 0xfffe);
		loop_mode = 1;
	}
	x_put_byte(srca, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, srca + 0, 0x0, newv, 1);
		return;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return;
}
/* 14 (2/1) */
/* 2 0,0   */

/* NEGX.B (d16,An) */
void REGPARAM2 op_4028_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 16;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	uae_u32 newv = 0 - src - (GET_XFLG() ? 1 : 0);
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(0)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_VFLG((flgs ^ flgo) & (flgo ^ flgn));
	SET_CFLG(flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
	COPY_CARRY();
	SET_ZFLG(GET_ZFLG() & (((uae_s8)(newv)) == 0));
	SET_NFLG(((uae_s8)(newv)) < 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_byte(srca, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, srca + 0, 0x0, newv, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* NEGX.B (d8,An,Xn) */
void REGPARAM2 op_4030_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 16;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	do_cycles_ce000_internal(2);
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	uae_u32 newv = 0 - src - (GET_XFLG() ? 1 : 0);
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(0)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_VFLG((flgs ^ flgo) & (flgo ^ flgn));
	SET_CFLG(flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
	COPY_CARRY();
	SET_ZFLG(GET_ZFLG() & (((uae_s8)(newv)) == 0));
	SET_NFLG(((uae_s8)(newv)) < 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_byte(srca, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, srca + 0, 0x0, newv, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 18 (3/1) */
/* 4 4,0   */

/* NEGX.B (xxx).W */
void REGPARAM2 op_4038_13_ff(uae_u32 opcode)
{
	OpcodeFamily = 16;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	uae_u32 newv = 0 - src - (GET_XFLG() ? 1 : 0);
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(0)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_VFLG((flgs ^ flgo) & (flgo ^ flgn));
	SET_CFLG(flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
	COPY_CARRY();
	SET_ZFLG(GET_ZFLG() & (((uae_s8)(newv)) == 0));
	SET_NFLG(((uae_s8)(newv)) < 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_byte(srca, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, srca + 0, 0x0, newv, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* NEGX.B (xxx).L */
void REGPARAM2 op_4039_13_ff(uae_u32 opcode)
{
	OpcodeFamily = 16;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	srca = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	srca |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	uae_u32 newv = 0 - src - (GET_XFLG() ? 1 : 0);
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(0)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_VFLG((flgs ^ flgo) & (flgo ^ flgn));
	SET_CFLG(flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
	COPY_CARRY();
	SET_ZFLG(GET_ZFLG() & (((uae_s8)(newv)) == 0));
	SET_NFLG(((uae_s8)(newv)) < 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_byte(srca, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, srca + 0, 0x0, newv, 1);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 20 (4/1) */
/* 6 0,0   */

/* NEGX.W Dn */
void REGPARAM2 op_4040_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 16;
	CurrentInstrCycles = 4;  
	uae_s16 src = m68k_dreg(regs, srcreg);
	uae_u32 newv = 0 - src - (GET_XFLG() ? 1 : 0);
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(0)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_VFLG((flgs ^ flgo) & (flgo ^ flgn));
	SET_CFLG(flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
	COPY_CARRY();
	SET_ZFLG(GET_ZFLG() & (((uae_s16)(newv)) == 0));
	SET_NFLG(((uae_s16)(newv)) < 0);
	m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | ((newv) & 0xffff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 4 (1/0) */
/* 2 0,0   */

/* NEGX.W (An) */
void REGPARAM2 op_4050_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 16;
	CurrentInstrCycles = 12; 
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access2(opcode, srca, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	uae_u32 newv = 0 - src - (GET_XFLG() ? 1 : 0);
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(0)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_VFLG((flgs ^ flgo) & (flgo ^ flgn));
	SET_CFLG(flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
	COPY_CARRY();
	SET_ZFLG(GET_ZFLG() & (((uae_s16)(newv)) == 0));
	SET_NFLG(((uae_s16)(newv)) < 0);
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_ce000_prefetch(4);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return;
		}
		opcode = regs.ir;
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	if(loop_mode & 0xfffe) {
		do_cycles_ce000_internal(loop_mode & 0xfffe);
		loop_mode = 1;
	}
	x_put_word(srca, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, srca + 0, 0x1, newv, 1);
		return;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return;
}
/* 12 (2/1) */
/* 2 0,0   */

/* NEGX.W (An)+ */
void REGPARAM2 op_4058_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 16;
	CurrentInstrCycles = 12; 
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_areg(regs, srcreg) += 2 + 0;
		m68k_incpci(2);
		exception3_read_access2(opcode, srca, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) += 2 + 0;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	m68k_areg(regs, srcreg) += 2;
	uae_u32 newv = 0 - src - (GET_XFLG() ? 1 : 0);
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(0)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_VFLG((flgs ^ flgo) & (flgo ^ flgn));
	SET_CFLG(flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
	COPY_CARRY();
	SET_ZFLG(GET_ZFLG() & (((uae_s16)(newv)) == 0));
	SET_NFLG(((uae_s16)(newv)) < 0);
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_ce000_prefetch(4);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return;
		}
		opcode = regs.ir;
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	if(loop_mode & 0xfffe) {
		do_cycles_ce000_internal(loop_mode & 0xfffe);
		loop_mode = 1;
	}
	x_put_word(srca, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, srca + 0, 0x1, newv, 1);
		return;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return;
}
/* 12 (2/1) */
/* 2 0,0   */

/* NEGX.W -(An) */
void REGPARAM2 op_4060_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 16;
	CurrentInstrCycles = 14; 
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - 2;
	do_cycles_ce000_internal(2);
	if (srca & 1) {
		m68k_areg(regs, srcreg) = srca;
		m68k_incpci(2);
		exception3_read_access2(opcode, srca, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	m68k_areg(regs, srcreg) = srca;
	uae_u32 newv = 0 - src - (GET_XFLG() ? 1 : 0);
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(0)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_VFLG((flgs ^ flgo) & (flgo ^ flgn));
	SET_CFLG(flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
	COPY_CARRY();
	SET_ZFLG(GET_ZFLG() & (((uae_s16)(newv)) == 0));
	SET_NFLG(((uae_s16)(newv)) < 0);
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_ce000_prefetch(4);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return;
		}
		opcode = regs.ir;
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	if(loop_mode & 0xfffe) {
		do_cycles_ce000_internal(loop_mode & 0xfffe);
		loop_mode = 1;
	}
	x_put_word(srca, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, srca + 0, 0x1, newv, 1);
		return;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return;
}
/* 14 (2/1) */
/* 2 0,0   */

/* NEGX.W (d16,An) */
void REGPARAM2 op_4068_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 16;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	uae_u32 newv = 0 - src - (GET_XFLG() ? 1 : 0);
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(0)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_VFLG((flgs ^ flgo) & (flgo ^ flgn));
	SET_CFLG(flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
	COPY_CARRY();
	SET_ZFLG(GET_ZFLG() & (((uae_s16)(newv)) == 0));
	SET_NFLG(((uae_s16)(newv)) < 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_word(srca, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, srca + 0, 0x1, newv, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* NEGX.W (d8,An,Xn) */
void REGPARAM2 op_4070_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 16;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	do_cycles_ce000_internal(2);
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	uae_u32 newv = 0 - src - (GET_XFLG() ? 1 : 0);
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(0)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_VFLG((flgs ^ flgo) & (flgo ^ flgn));
	SET_CFLG(flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
	COPY_CARRY();
	SET_ZFLG(GET_ZFLG() & (((uae_s16)(newv)) == 0));
	SET_NFLG(((uae_s16)(newv)) < 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_word(srca, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, srca + 0, 0x1, newv, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 18 (3/1) */
/* 4 4,0   */

/* NEGX.W (xxx).W */
void REGPARAM2 op_4078_13_ff(uae_u32 opcode)
{
	OpcodeFamily = 16;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	if (srca & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	uae_u32 newv = 0 - src - (GET_XFLG() ? 1 : 0);
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(0)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_VFLG((flgs ^ flgo) & (flgo ^ flgn));
	SET_CFLG(flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
	COPY_CARRY();
	SET_ZFLG(GET_ZFLG() & (((uae_s16)(newv)) == 0));
	SET_NFLG(((uae_s16)(newv)) < 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_word(srca, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, srca + 0, 0x1, newv, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* NEGX.W (xxx).L */
void REGPARAM2 op_4079_13_ff(uae_u32 opcode)
{
	OpcodeFamily = 16;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	srca = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	srca |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	if (srca & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	uae_u32 newv = 0 - src - (GET_XFLG() ? 1 : 0);
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(0)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_VFLG((flgs ^ flgo) & (flgo ^ flgn));
	SET_CFLG(flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
	COPY_CARRY();
	SET_ZFLG(GET_ZFLG() & (((uae_s16)(newv)) == 0));
	SET_NFLG(((uae_s16)(newv)) < 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_word(srca, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, srca + 0, 0x1, newv, 1);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 20 (4/1) */
/* 6 0,0   */

/* NEGX.L Dn */
void REGPARAM2 op_4080_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 16;
	CurrentInstrCycles = 6;  
	uae_s32 src = m68k_dreg(regs, srcreg);
	uae_u32 newv = 0 - src - (GET_XFLG() ? 1 : 0);
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(0)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_VFLG((flgs ^ flgo) & (flgo ^ flgn));
	SET_CFLG(flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
	COPY_CARRY();
	SET_ZFLG(GET_ZFLG() & (((uae_s32)(newv)) == 0));
	SET_NFLG(((uae_s32)(newv)) < 0);
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		dreg_68000_long_replace_low(srcreg, newv);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	m68k_dreg(regs, srcreg) = (newv);
	do_cycles_ce000_internal(2);
	m68k_incpci(2);
	return;
}
/* 6 (1/0) */
/* 2 0,0   */

/* NEGX.L (An) */
void REGPARAM2 op_4090_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 16;
	CurrentInstrCycles = 20; 
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	uae_u32 newv = 0 - src - (GET_XFLG() ? 1 : 0);
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(0)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_VFLG((flgs ^ flgo) & (flgo ^ flgn));
	SET_CFLG(flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
	COPY_CARRY();
	SET_ZFLG(GET_ZFLG() & (((uae_s32)(newv)) == 0));
	SET_NFLG(((uae_s32)(newv)) < 0);
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_ce000_prefetch(4);
		if(hardware_bus_error) {
			int pcoffset = 0;
			int bflgs = ((uae_s16)(src)) < 0;
			int bflgo = ((uae_s16)(0)) < 0;
			int bflgn = ((uae_s16)(newv)) < 0;
			SET_VFLG((bflgs ^ bflgo) & (bflgo ^ bflgn));
			SET_CFLG(bflgs ^ ((bflgs ^ bflgn) & (bflgo ^ bflgn)));
			SET_ZFLG(GET_ZFLG() & (((uae_s16)(newv)) == 0));
			SET_NFLG(((uae_s16)(newv)) < 0);
			SET_XFLG(GET_CFLG());
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return;
		}
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	if(loop_mode & 0xfffe) {
		do_cycles_ce000_internal(loop_mode & 0xfffe);
		loop_mode = 1;
	}
	x_put_word(srca + 2, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, srca + 2, 0x1, newv, 1);
		return;
	}
	x_put_word(srca, newv >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, srca + 0, 0x1, newv >> 16, 1);
		return;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return;
}
/* 20 (3/2) */
/* 2 0,0   */

/* NEGX.L (An)+ */
void REGPARAM2 op_4098_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 16;
	CurrentInstrCycles = 20; 
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	m68k_areg(regs, srcreg) += 4;
	uae_u32 newv = 0 - src - (GET_XFLG() ? 1 : 0);
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(0)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_VFLG((flgs ^ flgo) & (flgo ^ flgn));
	SET_CFLG(flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
	COPY_CARRY();
	SET_ZFLG(GET_ZFLG() & (((uae_s32)(newv)) == 0));
	SET_NFLG(((uae_s32)(newv)) < 0);
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_ce000_prefetch(4);
		if(hardware_bus_error) {
			int pcoffset = 0;
			int bflgs = ((uae_s16)(src)) < 0;
			int bflgo = ((uae_s16)(0)) < 0;
			int bflgn = ((uae_s16)(newv)) < 0;
			SET_VFLG((bflgs ^ bflgo) & (bflgo ^ bflgn));
			SET_CFLG(bflgs ^ ((bflgs ^ bflgn) & (bflgo ^ bflgn)));
			SET_ZFLG(GET_ZFLG() & (((uae_s16)(newv)) == 0));
			SET_NFLG(((uae_s16)(newv)) < 0);
			SET_XFLG(GET_CFLG());
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return;
		}
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	if(loop_mode & 0xfffe) {
		do_cycles_ce000_internal(loop_mode & 0xfffe);
		loop_mode = 1;
	}
	x_put_word(srca + 2, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, srca + 2, 0x1, newv, 1);
		return;
	}
	x_put_word(srca, newv >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, srca + 0, 0x1, newv >> 16, 1);
		return;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return;
}
/* 20 (3/2) */
/* 2 0,0   */

/* NEGX.L -(An) */
void REGPARAM2 op_40a0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 16;
	CurrentInstrCycles = 22; 
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - 4;
	do_cycles_ce000_internal(2);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	m68k_areg(regs, srcreg) = srca;
	uae_u32 newv = 0 - src - (GET_XFLG() ? 1 : 0);
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(0)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_VFLG((flgs ^ flgo) & (flgo ^ flgn));
	SET_CFLG(flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
	COPY_CARRY();
	SET_ZFLG(GET_ZFLG() & (((uae_s32)(newv)) == 0));
	SET_NFLG(((uae_s32)(newv)) < 0);
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_ce000_prefetch(4);
		if(hardware_bus_error) {
			int pcoffset = 0;
			int bflgs = ((uae_s16)(src)) < 0;
			int bflgo = ((uae_s16)(0)) < 0;
			int bflgn = ((uae_s16)(newv)) < 0;
			SET_VFLG((bflgs ^ bflgo) & (bflgo ^ bflgn));
			SET_CFLG(bflgs ^ ((bflgs ^ bflgn) & (bflgo ^ bflgn)));
			SET_ZFLG(GET_ZFLG() & (((uae_s16)(newv)) == 0));
			SET_NFLG(((uae_s16)(newv)) < 0);
			SET_XFLG(GET_CFLG());
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return;
		}
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	if(loop_mode & 0xfffe) {
		do_cycles_ce000_internal(loop_mode & 0xfffe);
		loop_mode = 1;
	}
	x_put_word(srca + 2, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, srca + 2, 0x1, newv, 1);
		return;
	}
	x_put_word(srca, newv >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, srca + 0, 0x1, newv >> 16, 1);
		return;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return;
}
/* 22 (3/2) */
/* 2 0,0   */

/* NEGX.L (d16,An) */
void REGPARAM2 op_40a8_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 16;
	CurrentInstrCycles = 24; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	uae_u32 newv = 0 - src - (GET_XFLG() ? 1 : 0);
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(0)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_VFLG((flgs ^ flgo) & (flgo ^ flgn));
	SET_CFLG(flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
	COPY_CARRY();
	SET_ZFLG(GET_ZFLG() & (((uae_s32)(newv)) == 0));
	SET_NFLG(((uae_s32)(newv)) < 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		int bflgs = ((uae_s16)(src)) < 0;
		int bflgo = ((uae_s16)(0)) < 0;
		int bflgn = ((uae_s16)(newv)) < 0;
		SET_VFLG((bflgs ^ bflgo) & (bflgo ^ bflgn));
		SET_CFLG(bflgs ^ ((bflgs ^ bflgn) & (bflgo ^ bflgn)));
		SET_ZFLG(GET_ZFLG() & (((uae_s16)(newv)) == 0));
		SET_NFLG(((uae_s16)(newv)) < 0);
		SET_XFLG(GET_CFLG());
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	x_put_word(srca + 2, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, srca + 2, 0x1, newv, 1);
		return;
	}
	x_put_word(srca, newv >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, srca + 0, 0x1, newv >> 16, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 24 (4/2) */
/* 4 0,0   */

/* NEGX.L (d8,An,Xn) */
void REGPARAM2 op_40b0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 16;
	CurrentInstrCycles = 26; 
	uaecptr srca;
	do_cycles_ce000_internal(2);
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	uae_u32 newv = 0 - src - (GET_XFLG() ? 1 : 0);
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(0)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_VFLG((flgs ^ flgo) & (flgo ^ flgn));
	SET_CFLG(flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
	COPY_CARRY();
	SET_ZFLG(GET_ZFLG() & (((uae_s32)(newv)) == 0));
	SET_NFLG(((uae_s32)(newv)) < 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		int bflgs = ((uae_s16)(src)) < 0;
		int bflgo = ((uae_s16)(0)) < 0;
		int bflgn = ((uae_s16)(newv)) < 0;
		SET_VFLG((bflgs ^ bflgo) & (bflgo ^ bflgn));
		SET_CFLG(bflgs ^ ((bflgs ^ bflgn) & (bflgo ^ bflgn)));
		SET_ZFLG(GET_ZFLG() & (((uae_s16)(newv)) == 0));
		SET_NFLG(((uae_s16)(newv)) < 0);
		SET_XFLG(GET_CFLG());
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	x_put_word(srca + 2, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, srca + 2, 0x1, newv, 1);
		return;
	}
	x_put_word(srca, newv >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, srca + 0, 0x1, newv >> 16, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 26 (4/2) */
/* 4 4,0   */

/* NEGX.L (xxx).W */
void REGPARAM2 op_40b8_13_ff(uae_u32 opcode)
{
	OpcodeFamily = 16;
	CurrentInstrCycles = 24; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	if (srca & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	uae_u32 newv = 0 - src - (GET_XFLG() ? 1 : 0);
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(0)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_VFLG((flgs ^ flgo) & (flgo ^ flgn));
	SET_CFLG(flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
	COPY_CARRY();
	SET_ZFLG(GET_ZFLG() & (((uae_s32)(newv)) == 0));
	SET_NFLG(((uae_s32)(newv)) < 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		int bflgs = ((uae_s16)(src)) < 0;
		int bflgo = ((uae_s16)(0)) < 0;
		int bflgn = ((uae_s16)(newv)) < 0;
		SET_VFLG((bflgs ^ bflgo) & (bflgo ^ bflgn));
		SET_CFLG(bflgs ^ ((bflgs ^ bflgn) & (bflgo ^ bflgn)));
		SET_ZFLG(GET_ZFLG() & (((uae_s16)(newv)) == 0));
		SET_NFLG(((uae_s16)(newv)) < 0);
		SET_XFLG(GET_CFLG());
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	x_put_word(srca + 2, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, srca + 2, 0x1, newv, 1);
		return;
	}
	x_put_word(srca, newv >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, srca + 0, 0x1, newv >> 16, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 24 (4/2) */
/* 4 0,0   */

/* NEGX.L (xxx).L */
void REGPARAM2 op_40b9_13_ff(uae_u32 opcode)
{
	OpcodeFamily = 16;
	CurrentInstrCycles = 28; 
	uaecptr srca;
	srca = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	srca |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	if (srca & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	uae_u32 newv = 0 - src - (GET_XFLG() ? 1 : 0);
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(0)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_VFLG((flgs ^ flgo) & (flgo ^ flgn));
	SET_CFLG(flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
	COPY_CARRY();
	SET_ZFLG(GET_ZFLG() & (((uae_s32)(newv)) == 0));
	SET_NFLG(((uae_s32)(newv)) < 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		int bflgs = ((uae_s16)(src)) < 0;
		int bflgo = ((uae_s16)(0)) < 0;
		int bflgn = ((uae_s16)(newv)) < 0;
		SET_VFLG((bflgs ^ bflgo) & (bflgo ^ bflgn));
		SET_CFLG(bflgs ^ ((bflgs ^ bflgn) & (bflgo ^ bflgn)));
		SET_ZFLG(GET_ZFLG() & (((uae_s16)(newv)) == 0));
		SET_NFLG(((uae_s16)(newv)) < 0);
		SET_XFLG(GET_CFLG());
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	x_put_word(srca + 2, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, srca + 2, 0x1, newv, 1);
		return;
	}
	x_put_word(srca, newv >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, srca + 0, 0x1, newv >> 16, 1);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 28 (5/2) */
/* 6 0,0   */

/* MVSR2.W Dn */
void REGPARAM2 op_40c0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 32;
	CurrentInstrCycles = 4;  
	if (!regs.s) {
		Exception(8);
		return;
	}
	MakeSR();
	regs.ir = regs.irc;
	ipl_fetch_next();
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | ((regs.sr) & 0xffff);
	m68k_incpci(2);
	return;
}
/* 4 (1/0) */
/* 2 0,0   */

/* MVSR2.W (An) */
void REGPARAM2 op_40d0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 32;
	CurrentInstrCycles = 10; 
	if (!regs.s) {
		Exception(8);
		return;
	}
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	do_cycles_ce000_internal(2);
	ipl_fetch_now();
	MakeSR();
	regs.ir = regs.irc;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	if(srca & 1) {
		m68k_incpci(4);
		exception3_write(opcode, srca, 1, regs.sr & 0xffff, 1);
		return;
	}
	x_put_word(srca, regs.sr);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, srca + 0, 0x1, regs.sr, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 10 (1/1) */
/* 2 0,0   */

/* MVSR2.W (An)+ */
void REGPARAM2 op_40d8_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 32;
	CurrentInstrCycles = 12; 
	if (!regs.s) {
		Exception(8);
		return;
	}
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	do_cycles_ce000_internal(4);
	ipl_fetch_now();
	m68k_areg(regs, srcreg) += 2;
	MakeSR();
	regs.ir = regs.irc;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	if(srca & 1) {
		m68k_incpci(4);
		exception3_write(opcode, srca, 1, regs.sr & 0xffff, 1);
		return;
	}
	x_put_word(srca, regs.sr);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, srca + 0, 0x1, regs.sr, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 12 (1/1) */
/* 2 0,0   */

/* MVSR2.W -(An) */
void REGPARAM2 op_40e0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 32;
	CurrentInstrCycles = 12; 
	if (!regs.s) {
		Exception(8);
		return;
	}
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - 2;
	do_cycles_ce000_internal(4);
	ipl_fetch_now();
	m68k_areg(regs, srcreg) = srca;
	MakeSR();
	regs.ir = regs.irc;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	if(srca & 1) {
		m68k_incpci(4);
		exception3_write(opcode, srca, 1, regs.sr & 0xffff, 1);
		return;
	}
	x_put_word(srca, regs.sr);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, srca + 0, 0x1, regs.sr, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 12 (1/1) */
/* 2 0,0   */

/* MVSR2.W (d16,An) */
void REGPARAM2 op_40e8_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 32;
	CurrentInstrCycles = 12; 
	if (!regs.s) {
		Exception(8);
		return;
	}
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	ipl_fetch_now();
	MakeSR();
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	if(srca & 1) {
		m68k_incpci(6);
		exception3_write(opcode, srca, 1, regs.sr & 0xffff, 1);
		return;
	}
	x_put_word(srca, regs.sr);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, srca + 0, 0x1, regs.sr, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 12 (2/1) */
/* 4 0,0   */

/* MVSR2.W (d8,An,Xn) */
void REGPARAM2 op_40f0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 32;
	CurrentInstrCycles = 16; 
	if (!regs.s) {
		Exception(8);
		return;
	}
	uaecptr srca;
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_ce000_prefetch(4));
	do_cycles_ce000_internal(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	ipl_fetch_now();
	MakeSR();
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	if(srca & 1) {
		m68k_incpci(6);
		exception3_write(opcode, srca, 1, regs.sr & 0xffff, 1);
		return;
	}
	x_put_word(srca, regs.sr);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, srca + 0, 0x1, regs.sr, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (2/1) */
/* 4 4,0   */

/* MVSR2.W (xxx).W */
void REGPARAM2 op_40f8_13_ff(uae_u32 opcode)
{
	OpcodeFamily = 32;
	CurrentInstrCycles = 12; 
	if (!regs.s) {
		Exception(8);
		return;
	}
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	ipl_fetch_now();
	MakeSR();
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	if(srca & 1) {
		m68k_incpci(6);
		exception3_write(opcode, srca, 1, regs.sr & 0xffff, 1);
		return;
	}
	x_put_word(srca, regs.sr);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, srca + 0, 0x1, regs.sr, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 12 (2/1) */
/* 4 0,0   */

/* MVSR2.W (xxx).L */
void REGPARAM2 op_40f9_13_ff(uae_u32 opcode)
{
	OpcodeFamily = 32;
	CurrentInstrCycles = 16; 
	if (!regs.s) {
		Exception(8);
		return;
	}
	uaecptr srca;
	srca = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	srca |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	ipl_fetch_now();
	MakeSR();
	regs.ir = regs.irc;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	opcode = regs.ir;
	if(srca & 1) {
		m68k_incpci(8);
		exception3_write(opcode, srca, 1, regs.sr & 0xffff, 1);
		return;
	}
	x_put_word(srca, regs.sr);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, srca + 0, 0x1, regs.sr, 1);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 16 (3/1) */
/* 6 0,0   */

/* CHK.W Dn,Dn */
void REGPARAM2 op_4180_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 80;
	CurrentInstrCycles = 10; 
	uae_s16 src = m68k_dreg(regs, srcreg);
	uae_s16 dst = m68k_dreg(regs, dstreg);
	m68k_incpci(2);
	do_cycles_ce000_internal(4);
	if (dst > src) {
		setchkundefinedflags(src, dst, 1);
		Exception_cpu(6);
		return;
	}
	do_cycles_ce000_internal(2);
	if ((uae_s32)dst < 0) {
		setchkundefinedflags(src, dst, 1);
		Exception_cpu(6);
		return;
	}
	setchkundefinedflags(src, dst, 1);
	ipl_fetch_next();
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 10 (1/0) */
/* 2 0,0   */

/* CHK.W (An),Dn */
void REGPARAM2 op_4190_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 80;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access2(opcode, srca, 1, 1);
		return;
	}
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	m68k_incpci(2);
	do_cycles_ce000_internal(4);
	if (dst > src) {
		setchkundefinedflags(src, dst, 1);
		Exception_cpu(6);
		return;
	}
	do_cycles_ce000_internal(2);
	if ((uae_s32)dst < 0) {
		setchkundefinedflags(src, dst, 1);
		Exception_cpu(6);
		return;
	}
	setchkundefinedflags(src, dst, 1);
	ipl_fetch_next();
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 14 (2/0) */
/* 2 0,0   */

/* CHK.W (An)+,Dn */
void REGPARAM2 op_4198_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 80;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_areg(regs, srcreg) += 2 + 0;
		m68k_incpci(2);
		exception3_read_access2(opcode, srca, 1, 1);
		return;
	}
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) += 2 + 0;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	m68k_areg(regs, srcreg) += 2;
	uae_s16 dst = m68k_dreg(regs, dstreg);
	m68k_incpci(2);
	do_cycles_ce000_internal(4);
	if (dst > src) {
		setchkundefinedflags(src, dst, 1);
		Exception_cpu(6);
		return;
	}
	do_cycles_ce000_internal(2);
	if ((uae_s32)dst < 0) {
		setchkundefinedflags(src, dst, 1);
		Exception_cpu(6);
		return;
	}
	setchkundefinedflags(src, dst, 1);
	ipl_fetch_next();
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 14 (2/0) */
/* 2 0,0   */

/* CHK.W -(An),Dn */
void REGPARAM2 op_41a0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 80;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - 2;
	do_cycles_ce000_internal(2);
	if (srca & 1) {
		m68k_areg(regs, srcreg) = srca;
		m68k_incpci(2);
		exception3_read_access2(opcode, srca, 1, 1);
		return;
	}
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	m68k_areg(regs, srcreg) = srca;
	uae_s16 dst = m68k_dreg(regs, dstreg);
	m68k_incpci(2);
	do_cycles_ce000_internal(4);
	if (dst > src) {
		setchkundefinedflags(src, dst, 1);
		Exception_cpu(6);
		return;
	}
	do_cycles_ce000_internal(2);
	if ((uae_s32)dst < 0) {
		setchkundefinedflags(src, dst, 1);
		Exception_cpu(6);
		return;
	}
	setchkundefinedflags(src, dst, 1);
	ipl_fetch_next();
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 16 (2/0) */
/* 2 0,0   */

/* CHK.W (d16,An),Dn */
void REGPARAM2 op_41a8_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 80;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	m68k_incpci(4);
	do_cycles_ce000_internal(4);
	if (dst > src) {
		setchkundefinedflags(src, dst, 1);
		Exception_cpu(6);
		return;
	}
	do_cycles_ce000_internal(2);
	if ((uae_s32)dst < 0) {
		setchkundefinedflags(src, dst, 1);
		Exception_cpu(6);
		return;
	}
	setchkundefinedflags(src, dst, 1);
	ipl_fetch_next();
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 18 (3/0) */
/* 4 0,0   */

/* CHK.W (d8,An,Xn),Dn */
void REGPARAM2 op_41b0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 80;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	do_cycles_ce000_internal(2);
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	m68k_incpci(4);
	do_cycles_ce000_internal(4);
	if (dst > src) {
		setchkundefinedflags(src, dst, 1);
		Exception_cpu(6);
		return;
	}
	do_cycles_ce000_internal(2);
	if ((uae_s32)dst < 0) {
		setchkundefinedflags(src, dst, 1);
		Exception_cpu(6);
		return;
	}
	setchkundefinedflags(src, dst, 1);
	ipl_fetch_next();
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 20 (3/0) */
/* 4 4,0   */

/* CHK.W (xxx).W,Dn */
void REGPARAM2 op_41b8_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 80;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	if (srca & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	m68k_incpci(4);
	do_cycles_ce000_internal(4);
	if (dst > src) {
		setchkundefinedflags(src, dst, 1);
		Exception_cpu(6);
		return;
	}
	do_cycles_ce000_internal(2);
	if ((uae_s32)dst < 0) {
		setchkundefinedflags(src, dst, 1);
		Exception_cpu(6);
		return;
	}
	setchkundefinedflags(src, dst, 1);
	ipl_fetch_next();
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 18 (3/0) */
/* 4 0,0   */

/* CHK.W (xxx).L,Dn */
void REGPARAM2 op_41b9_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 80;
	CurrentInstrCycles = 22; 
	uaecptr srca;
	srca = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	srca |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	if (srca & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	m68k_incpci(6);
	do_cycles_ce000_internal(4);
	if (dst > src) {
		setchkundefinedflags(src, dst, 1);
		Exception_cpu(6);
		return;
	}
	do_cycles_ce000_internal(2);
	if ((uae_s32)dst < 0) {
		setchkundefinedflags(src, dst, 1);
		Exception_cpu(6);
		return;
	}
	setchkundefinedflags(src, dst, 1);
	ipl_fetch_next();
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 22 (4/0) */
/* 6 0,0   */

/* CHK.W (d16,PC),Dn */
void REGPARAM2 op_41ba_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 80;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	srca = m68k_getpci() + 2;
	srca += (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 2);
		return;
	}
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	m68k_incpci(4);
	do_cycles_ce000_internal(4);
	if (dst > src) {
		setchkundefinedflags(src, dst, 1);
		Exception_cpu(6);
		return;
	}
	do_cycles_ce000_internal(2);
	if ((uae_s32)dst < 0) {
		setchkundefinedflags(src, dst, 1);
		Exception_cpu(6);
		return;
	}
	setchkundefinedflags(src, dst, 1);
	ipl_fetch_next();
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 18 (3/0) */
/* 4 0,0   */

/* CHK.W (d8,PC,Xn),Dn */
void REGPARAM2 op_41bb_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 80;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	uaecptr tmppc = m68k_getpci() + 2;
	do_cycles_ce000_internal(2);
	srca = get_disp_ea_000(tmppc, get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 2);
		return;
	}
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	m68k_incpci(4);
	do_cycles_ce000_internal(4);
	if (dst > src) {
		setchkundefinedflags(src, dst, 1);
		Exception_cpu(6);
		return;
	}
	do_cycles_ce000_internal(2);
	if ((uae_s32)dst < 0) {
		setchkundefinedflags(src, dst, 1);
		Exception_cpu(6);
		return;
	}
	setchkundefinedflags(src, dst, 1);
	ipl_fetch_next();
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 20 (3/0) */
/* 4 4,0   */

/* CHK.W #<data>.W,Dn */
void REGPARAM2 op_41bc_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 80;
	CurrentInstrCycles = 14; 
	uae_s16 src = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	m68k_incpci(4);
	do_cycles_ce000_internal(4);
	if (dst > src) {
		setchkundefinedflags(src, dst, 1);
		Exception_cpu(6);
		return;
	}
	do_cycles_ce000_internal(2);
	if ((uae_s32)dst < 0) {
		setchkundefinedflags(src, dst, 1);
		Exception_cpu(6);
		return;
	}
	setchkundefinedflags(src, dst, 1);
	ipl_fetch_next();
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 14 (2/0) */
/* 4 0,0   */

/* LEA.L (An),An */
void REGPARAM2 op_41d0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 56;
	CurrentInstrCycles = 4;  
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	m68k_areg(regs, dstreg) = (srca);
	ipl_fetch_next();
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 4 (1/0) */
/* 2 0,0   */

/* LEA.L (d16,An),An */
void REGPARAM2 op_41e8_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 56;
	CurrentInstrCycles = 8;  
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	m68k_areg(regs, dstreg) = (srca);
	ipl_fetch_next();
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 8 (2/0) */
/* 4 0,0   */

/* LEA.L (d8,An,Xn),An */
void REGPARAM2 op_41f0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 56;
	CurrentInstrCycles = 12; 
	do_cycles_ce000_internal(2);
	uaecptr srca;
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	do_cycles_ce000_internal(2);
	m68k_areg(regs, dstreg) = (srca);
	ipl_fetch_next();
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 12 (2/0) */
/* 4 4,0   */

/* LEA.L (xxx).W,An */
void REGPARAM2 op_41f8_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 56;
	CurrentInstrCycles = 8;  
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	m68k_areg(regs, dstreg) = (srca);
	ipl_fetch_next();
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 8 (2/0) */
/* 4 0,0   */

/* LEA.L (xxx).L,An */
void REGPARAM2 op_41f9_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 56;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	srca |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	m68k_areg(regs, dstreg) = (srca);
	ipl_fetch_next();
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 12 (3/0) */
/* 6 0,0   */

/* LEA.L (d16,PC),An */
void REGPARAM2 op_41fa_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 56;
	CurrentInstrCycles = 8;  
	uaecptr srca;
	srca = m68k_getpci() + 2;
	srca += (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	m68k_areg(regs, dstreg) = (srca);
	ipl_fetch_next();
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 8 (2/0) */
/* 4 0,0   */

/* LEA.L (d8,PC,Xn),An */
void REGPARAM2 op_41fb_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 56;
	CurrentInstrCycles = 12; 
	do_cycles_ce000_internal(2);
	uaecptr srca;
	uaecptr tmppc = m68k_getpci() + 2;
	srca = get_disp_ea_000(tmppc, get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	do_cycles_ce000_internal(2);
	m68k_areg(regs, dstreg) = (srca);
	ipl_fetch_next();
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 12 (2/0) */
/* 4 4,0   */

/* CLR.B Dn */
void REGPARAM2 op_4200_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 18;
	CurrentInstrCycles = 4;  
	struct flag_struct oldflags;
	oldflags.cznv = regflags.cznv;
	regs.ir = regs.irc;
	ipl_fetch_next();
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();
		SET_ZFLG(1);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(0)) == 0);
	SET_NFLG(((uae_s8)(0)) < 0);
	m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((0) & 0xff);
	m68k_incpci(2);
	return;
}
/* 4 (1/0) */
/* 2 0,0   */

/* CLR.B (An) */
void REGPARAM2 op_4210_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 18;
	CurrentInstrCycles = 8;  
	int loop_mode = regs.loop_mode;
	struct flag_struct oldflags;
	oldflags.cznv = regflags.cznv;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	ipl_fetch_now();
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_ce000_prefetch(4);
		if(hardware_bus_error) {
			int pcoffset = 0;
			CLEAR_CZNV();
			SET_ZFLG(1);
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return;
		}
	} else {
		loop_mode = 0;
		loop_mode |= 2;
		loop_mode |= 4 << 16;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(0)) == 0);
	SET_NFLG(((uae_s8)(0)) < 0);
	if(loop_mode & 0xfffe) {
		do_cycles_ce000_internal(loop_mode & 0xfffe);
		loop_mode &= 0xffff0000;
		loop_mode |= 1;
	}
	x_put_byte(srca, 0);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		regflags.cznv = oldflags.cznv;
		exception2_write(opcode, srca + 0, 0x0, 0, 1);
		return;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return;
}
/* 8 (1/1) */
/* 2 0,0   */

/* CLR.B (An)+ */
void REGPARAM2 op_4218_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 18;
	CurrentInstrCycles = 8;  
	int loop_mode = regs.loop_mode;
	struct flag_struct oldflags;
	oldflags.cznv = regflags.cznv;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	ipl_fetch_now();
	m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_ce000_prefetch(4);
		if(hardware_bus_error) {
			int pcoffset = 0;
			CLEAR_CZNV();
			SET_ZFLG(1);
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return;
		}
	} else {
		loop_mode = 0;
		loop_mode |= 2;
		loop_mode |= 4 << 16;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(0)) == 0);
	SET_NFLG(((uae_s8)(0)) < 0);
	if(loop_mode & 0xfffe) {
		do_cycles_ce000_internal(loop_mode & 0xfffe);
		loop_mode &= 0xffff0000;
		loop_mode |= 1;
	}
	x_put_byte(srca, 0);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		regflags.cznv = oldflags.cznv;
		m68k_areg(regs, srcreg) -= areg_byteinc[srcreg];
		exception2_write(opcode, srca + 0, 0x0, 0, 1);
		return;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return;
}
/* 8 (1/1) */
/* 2 0,0   */

/* CLR.B -(An) */
void REGPARAM2 op_4220_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 18;
	CurrentInstrCycles = 10; 
	int loop_mode = regs.loop_mode;
	struct flag_struct oldflags;
	oldflags.cznv = regflags.cznv;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
	do_cycles_ce000_internal(2);
	ipl_fetch_now();
	m68k_areg(regs, srcreg) = srca;
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_ce000_prefetch(4);
		if(hardware_bus_error) {
			int pcoffset = 0;
			CLEAR_CZNV();
			SET_ZFLG(1);
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return;
		}
	} else {
		loop_mode = 0;
		loop_mode |= 2;
		loop_mode |= 4 << 16;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(0)) == 0);
	SET_NFLG(((uae_s8)(0)) < 0);
	if(loop_mode & 0xfffe) {
		do_cycles_ce000_internal(loop_mode & 0xfffe);
		loop_mode &= 0xffff0000;
		loop_mode |= 1;
	}
	x_put_byte(srca, 0);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		regflags.cznv = oldflags.cznv;
		m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
		exception2_write(opcode, srca + 0, 0x0, 0, 1);
		return;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return;
}
/* 10 (1/1) */
/* 2 0,0   */

/* CLR.B (d16,An) */
void REGPARAM2 op_4228_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 18;
	CurrentInstrCycles = 12; 
	struct flag_struct oldflags;
	oldflags.cznv = regflags.cznv;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	ipl_fetch_now();
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();
		SET_ZFLG(1);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(0)) == 0);
	SET_NFLG(((uae_s8)(0)) < 0);
	x_put_byte(srca, 0);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, srca + 0, 0x0, 0, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 12 (2/1) */
/* 4 0,0   */

/* CLR.B (d8,An,Xn) */
void REGPARAM2 op_4230_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 18;
	CurrentInstrCycles = 16; 
	struct flag_struct oldflags;
	oldflags.cznv = regflags.cznv;
	uaecptr srca;
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_ce000_prefetch(4));
	do_cycles_ce000_internal(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	ipl_fetch_now();
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();
		SET_ZFLG(1);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(0)) == 0);
	SET_NFLG(((uae_s8)(0)) < 0);
	x_put_byte(srca, 0);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, srca + 0, 0x0, 0, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (2/1) */
/* 4 4,0   */

/* CLR.B (xxx).W */
void REGPARAM2 op_4238_13_ff(uae_u32 opcode)
{
	OpcodeFamily = 18;
	CurrentInstrCycles = 12; 
	struct flag_struct oldflags;
	oldflags.cznv = regflags.cznv;
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	ipl_fetch_now();
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();
		SET_ZFLG(1);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(0)) == 0);
	SET_NFLG(((uae_s8)(0)) < 0);
	x_put_byte(srca, 0);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, srca + 0, 0x0, 0, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 12 (2/1) */
/* 4 0,0   */

/* CLR.B (xxx).L */
void REGPARAM2 op_4239_13_ff(uae_u32 opcode)
{
	OpcodeFamily = 18;
	CurrentInstrCycles = 16; 
	struct flag_struct oldflags;
	oldflags.cznv = regflags.cznv;
	uaecptr srca;
	srca = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	srca |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	ipl_fetch_now();
	regs.ir = regs.irc;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();
		SET_ZFLG(1);
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(0)) == 0);
	SET_NFLG(((uae_s8)(0)) < 0);
	x_put_byte(srca, 0);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, srca + 0, 0x0, 0, 1);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 16 (3/1) */
/* 6 0,0   */

/* CLR.W Dn */
void REGPARAM2 op_4240_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 18;
	CurrentInstrCycles = 4;  
	struct flag_struct oldflags;
	oldflags.cznv = regflags.cznv;
	regs.ir = regs.irc;
	ipl_fetch_next();
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();
		SET_ZFLG(1);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(0)) == 0);
	SET_NFLG(((uae_s16)(0)) < 0);
	m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | ((0) & 0xffff);
	m68k_incpci(2);
	return;
}
/* 4 (1/0) */
/* 2 0,0   */

/* CLR.W (An) */
void REGPARAM2 op_4250_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 18;
	CurrentInstrCycles = 8;  
	int loop_mode = regs.loop_mode;
	struct flag_struct oldflags;
	oldflags.cznv = regflags.cznv;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	ipl_fetch_now();
	if(srca & 1) {
		m68k_incpci(4);
		exception3_write(opcode, srca, 1, 0, 1);
		return;
	}
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_ce000_prefetch(4);
		if(hardware_bus_error) {
			int pcoffset = 0;
			CLEAR_CZNV();
			SET_ZFLG(1);
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return;
		}
	} else {
		loop_mode = 0;
		loop_mode |= 2;
		loop_mode |= 4 << 16;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(0)) == 0);
	SET_NFLG(((uae_s16)(0)) < 0);
	if(loop_mode & 0xfffe) {
		do_cycles_ce000_internal(loop_mode & 0xfffe);
		loop_mode &= 0xffff0000;
		loop_mode |= 1;
	}
	x_put_word(srca, 0);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		regflags.cznv = oldflags.cznv;
		exception2_write(opcode, srca + 0, 0x1, 0, 1);
		return;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return;
}
/* 8 (1/1) */
/* 2 0,0   */

/* CLR.W (An)+ */
void REGPARAM2 op_4258_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 18;
	CurrentInstrCycles = 8;  
	int loop_mode = regs.loop_mode;
	struct flag_struct oldflags;
	oldflags.cznv = regflags.cznv;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	ipl_fetch_now();
	m68k_areg(regs, srcreg) += 2;
	if(srca & 1) {
		m68k_areg(regs, srcreg) -= 2;
		m68k_incpci(4);
		exception3_write(opcode, srca, 1, 0, 1);
		return;
	}
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_ce000_prefetch(4);
		if(hardware_bus_error) {
			int pcoffset = 0;
			CLEAR_CZNV();
			SET_ZFLG(1);
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return;
		}
	} else {
		loop_mode = 0;
		loop_mode |= 2;
		loop_mode |= 4 << 16;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(0)) == 0);
	SET_NFLG(((uae_s16)(0)) < 0);
	if(loop_mode & 0xfffe) {
		do_cycles_ce000_internal(loop_mode & 0xfffe);
		loop_mode &= 0xffff0000;
		loop_mode |= 1;
	}
	x_put_word(srca, 0);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		regflags.cznv = oldflags.cznv;
		m68k_areg(regs, srcreg) -= 2;
		exception2_write(opcode, srca + 0, 0x1, 0, 1);
		return;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return;
}
/* 8 (1/1) */
/* 2 0,0   */

/* CLR.W -(An) */
void REGPARAM2 op_4260_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 18;
	CurrentInstrCycles = 10; 
	int loop_mode = regs.loop_mode;
	struct flag_struct oldflags;
	oldflags.cznv = regflags.cznv;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - 2;
	do_cycles_ce000_internal(2);
	ipl_fetch_now();
	m68k_areg(regs, srcreg) = srca;
	if(srca & 1) {
		m68k_areg(regs, srcreg) += 2;
		m68k_incpci(4);
		exception3_write(opcode, srca, 1, 0, 1);
		return;
	}
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_ce000_prefetch(4);
		if(hardware_bus_error) {
			int pcoffset = 0;
			CLEAR_CZNV();
			SET_ZFLG(1);
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return;
		}
	} else {
		loop_mode = 0;
		loop_mode |= 2;
		loop_mode |= 4 << 16;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(0)) == 0);
	SET_NFLG(((uae_s16)(0)) < 0);
	if(loop_mode & 0xfffe) {
		do_cycles_ce000_internal(loop_mode & 0xfffe);
		loop_mode &= 0xffff0000;
		loop_mode |= 1;
	}
	x_put_word(srca, 0);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		regflags.cznv = oldflags.cznv;
		m68k_areg(regs, srcreg) += 2;
		exception2_write(opcode, srca + 0, 0x1, 0, 1);
		return;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return;
}
/* 10 (1/1) */
/* 2 0,0   */

/* CLR.W (d16,An) */
void REGPARAM2 op_4268_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 18;
	CurrentInstrCycles = 12; 
	struct flag_struct oldflags;
	oldflags.cznv = regflags.cznv;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	ipl_fetch_now();
	if(srca & 1) {
		get_word_ce000_prefetch(6);
		CLEAR_CZNV();
		SET_ZFLG(((uae_s16)(0)) == 0);
		SET_NFLG(((uae_s16)(0)) < 0);
		m68k_incpci(6);
		exception3_write(opcode, srca, 1, 0, 1);
		return;
	}
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();
		SET_ZFLG(1);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(0)) == 0);
	SET_NFLG(((uae_s16)(0)) < 0);
	x_put_word(srca, 0);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, srca + 0, 0x1, 0, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 12 (2/1) */
/* 4 0,0   */

/* CLR.W (d8,An,Xn) */
void REGPARAM2 op_4270_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 18;
	CurrentInstrCycles = 16; 
	struct flag_struct oldflags;
	oldflags.cznv = regflags.cznv;
	uaecptr srca;
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_ce000_prefetch(4));
	do_cycles_ce000_internal(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	ipl_fetch_now();
	if(srca & 1) {
		get_word_ce000_prefetch(6);
		CLEAR_CZNV();
		SET_ZFLG(((uae_s16)(0)) == 0);
		SET_NFLG(((uae_s16)(0)) < 0);
		m68k_incpci(6);
		exception3_write(opcode, srca, 1, 0, 1);
		return;
	}
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();
		SET_ZFLG(1);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(0)) == 0);
	SET_NFLG(((uae_s16)(0)) < 0);
	x_put_word(srca, 0);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, srca + 0, 0x1, 0, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (2/1) */
/* 4 4,0   */

/* CLR.W (xxx).W */
void REGPARAM2 op_4278_13_ff(uae_u32 opcode)
{
	OpcodeFamily = 18;
	CurrentInstrCycles = 12; 
	struct flag_struct oldflags;
	oldflags.cznv = regflags.cznv;
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	ipl_fetch_now();
	if(srca & 1) {
		get_word_ce000_prefetch(6);
		CLEAR_CZNV();
		SET_ZFLG(((uae_s16)(0)) == 0);
		SET_NFLG(((uae_s16)(0)) < 0);
		m68k_incpci(6);
		exception3_write(opcode, srca, 1, 0, 1);
		return;
	}
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();
		SET_ZFLG(1);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(0)) == 0);
	SET_NFLG(((uae_s16)(0)) < 0);
	x_put_word(srca, 0);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, srca + 0, 0x1, 0, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 12 (2/1) */
/* 4 0,0   */

/* CLR.W (xxx).L */
void REGPARAM2 op_4279_13_ff(uae_u32 opcode)
{
	OpcodeFamily = 18;
	CurrentInstrCycles = 16; 
	struct flag_struct oldflags;
	oldflags.cznv = regflags.cznv;
	uaecptr srca;
	srca = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	srca |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	ipl_fetch_now();
	if(srca & 1) {
		get_word_ce000_prefetch(8);
		CLEAR_CZNV();
		SET_ZFLG(((uae_s16)(0)) == 0);
		SET_NFLG(((uae_s16)(0)) < 0);
		m68k_incpci(8);
		exception3_write(opcode, srca, 1, 0, 1);
		return;
	}
	regs.ir = regs.irc;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();
		SET_ZFLG(1);
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(0)) == 0);
	SET_NFLG(((uae_s16)(0)) < 0);
	x_put_word(srca, 0);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, srca + 0, 0x1, 0, 1);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 16 (3/1) */
/* 6 0,0   */

/* CLR.L Dn */
void REGPARAM2 op_4280_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 18;
	CurrentInstrCycles = 6;  
	struct flag_struct oldflags;
	oldflags.cznv = regflags.cznv;
	do_cycles_ce000_internal(2);
	regs.ir = regs.irc;
	ipl_fetch_next();
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();
		SET_ZFLG(1);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(0)) == 0);
	SET_NFLG(((uae_s32)(0)) < 0);
	m68k_dreg(regs, srcreg) = (0);
	m68k_incpci(2);
	return;
}
/* 6 (1/0) */
/* 2 0,0   */

/* CLR.L (An) */
void REGPARAM2 op_4290_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 18;
	CurrentInstrCycles = 12; 
	int loop_mode = regs.loop_mode;
	struct flag_struct oldflags;
	oldflags.cznv = regflags.cznv;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	ipl_fetch_now();
	if(srca & 1) {
		m68k_incpci(4);
		exception3_write(opcode, srca, 1, 0, 1);
		return;
	}
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_ce000_prefetch(4);
		if(hardware_bus_error) {
			int pcoffset = 0;
			CLEAR_CZNV();
			SET_ZFLG(1);
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return;
		}
	} else {
		loop_mode = 0;
		loop_mode |= 2;
		loop_mode |= 4 << 16;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(0)) == 0);
	SET_NFLG(((uae_s32)(0)) < 0);
	if(loop_mode & 0xfffe) {
		do_cycles_ce000_internal(loop_mode & 0xfffe);
		loop_mode &= 0xffff0000;
		loop_mode |= 1;
	}
	x_put_word(srca + 2, 0);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		regflags.cznv = oldflags.cznv;
		exception2_write(opcode, srca + 2, 0x1, 0, 1);
		return;
	}
	x_put_word(srca, 0 >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		regflags.cznv = oldflags.cznv;
		exception2_write(opcode, srca + 0, 0x1, 0 >> 16, 1);
		return;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return;
}
/* 12 (1/2) */
/* 2 0,0   */

/* CLR.L (An)+ */
void REGPARAM2 op_4298_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 18;
	CurrentInstrCycles = 12; 
	int loop_mode = regs.loop_mode;
	struct flag_struct oldflags;
	oldflags.cznv = regflags.cznv;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	ipl_fetch_now();
	m68k_areg(regs, srcreg) += 4;
	if(srca & 1) {
		m68k_areg(regs, srcreg) -= 4;
		m68k_incpci(4);
		exception3_write(opcode, srca, 1, 0, 1);
		return;
	}
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_ce000_prefetch(4);
		if(hardware_bus_error) {
			int pcoffset = 0;
			CLEAR_CZNV();
			SET_ZFLG(1);
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return;
		}
	} else {
		loop_mode = 0;
		loop_mode |= 2;
		loop_mode |= 4 << 16;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(0)) == 0);
	SET_NFLG(((uae_s32)(0)) < 0);
	if(loop_mode & 0xfffe) {
		do_cycles_ce000_internal(loop_mode & 0xfffe);
		loop_mode &= 0xffff0000;
		loop_mode |= 1;
	}
	x_put_word(srca + 2, 0);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		regflags.cznv = oldflags.cznv;
		m68k_areg(regs, srcreg) -= 4;
		exception2_write(opcode, srca + 2, 0x1, 0, 1);
		return;
	}
	x_put_word(srca, 0 >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		regflags.cznv = oldflags.cznv;
		m68k_areg(regs, srcreg) -= 4;
		exception2_write(opcode, srca + 0, 0x1, 0 >> 16, 1);
		return;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return;
}
/* 12 (1/2) */
/* 2 0,0   */

/* CLR.L -(An) */
void REGPARAM2 op_42a0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 18;
	CurrentInstrCycles = 14; 
	int loop_mode = regs.loop_mode;
	struct flag_struct oldflags;
	oldflags.cznv = regflags.cznv;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - 4;
	do_cycles_ce000_internal(2);
	ipl_fetch_now();
	m68k_areg(regs, srcreg) = srca;
	if(srca & 1) {
		m68k_areg(regs, srcreg) += 4;
		srca += 2;
		m68k_incpci(4);
		exception3_write(opcode, srca, 1, 0, 1);
		return;
	}
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_ce000_prefetch(4);
		if(hardware_bus_error) {
			int pcoffset = 0;
			CLEAR_CZNV();
			SET_ZFLG(1);
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return;
		}
	} else {
		loop_mode = 0;
		loop_mode |= 2;
		loop_mode |= 4 << 16;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(0)) == 0);
	SET_NFLG(((uae_s32)(0)) < 0);
	if(loop_mode & 0xfffe) {
		do_cycles_ce000_internal(loop_mode & 0xfffe);
		loop_mode &= 0xffff0000;
		loop_mode |= 1;
	}
	x_put_word(srca + 2, 0);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		regflags.cznv = oldflags.cznv;
		m68k_areg(regs, srcreg) += 4;
		exception2_write(opcode, srca + 2, 0x1, 0, 1);
		return;
	}
	x_put_word(srca, 0 >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		regflags.cznv = oldflags.cznv;
		m68k_areg(regs, srcreg) += 4;
		exception2_write(opcode, srca + 0, 0x1, 0 >> 16, 1);
		return;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return;
}
/* 14 (1/2) */
/* 2 0,0   */

/* CLR.L (d16,An) */
void REGPARAM2 op_42a8_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 18;
	CurrentInstrCycles = 16; 
	struct flag_struct oldflags;
	oldflags.cznv = regflags.cznv;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	ipl_fetch_now();
	if(srca & 1) {
		srca += 2;
		get_word_ce000_prefetch(6);
		CLEAR_CZNV();
		SET_ZFLG(((uae_s32)(0)) == 0);
		SET_NFLG(((uae_s32)(0)) < 0);
		m68k_incpci(6);
		exception3_write(opcode, srca, 1, 0, 1);
		return;
	}
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();
		SET_ZFLG(1);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(0)) == 0);
	SET_NFLG(((uae_s32)(0)) < 0);
	x_put_word(srca + 2, 0);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, srca + 2, 0x1, 0, 1);
		return;
	}
	x_put_word(srca, 0 >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, srca + 0, 0x1, 0 >> 16, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (2/2) */
/* 4 0,0   */

/* CLR.L (d8,An,Xn) */
void REGPARAM2 op_42b0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 18;
	CurrentInstrCycles = 20; 
	struct flag_struct oldflags;
	oldflags.cznv = regflags.cznv;
	uaecptr srca;
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_ce000_prefetch(4));
	do_cycles_ce000_internal(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	ipl_fetch_now();
	if(srca & 1) {
		srca += 2;
		get_word_ce000_prefetch(6);
		CLEAR_CZNV();
		SET_ZFLG(((uae_s32)(0)) == 0);
		SET_NFLG(((uae_s32)(0)) < 0);
		m68k_incpci(6);
		exception3_write(opcode, srca, 1, 0, 1);
		return;
	}
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();
		SET_ZFLG(1);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(0)) == 0);
	SET_NFLG(((uae_s32)(0)) < 0);
	x_put_word(srca + 2, 0);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, srca + 2, 0x1, 0, 1);
		return;
	}
	x_put_word(srca, 0 >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, srca + 0, 0x1, 0 >> 16, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 20 (2/2) */
/* 4 4,0   */

/* CLR.L (xxx).W */
void REGPARAM2 op_42b8_13_ff(uae_u32 opcode)
{
	OpcodeFamily = 18;
	CurrentInstrCycles = 16; 
	struct flag_struct oldflags;
	oldflags.cznv = regflags.cznv;
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	ipl_fetch_now();
	if(srca & 1) {
		srca += 2;
		get_word_ce000_prefetch(6);
		CLEAR_CZNV();
		SET_ZFLG(((uae_s32)(0)) == 0);
		SET_NFLG(((uae_s32)(0)) < 0);
		m68k_incpci(6);
		exception3_write(opcode, srca, 1, 0, 1);
		return;
	}
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();
		SET_ZFLG(1);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(0)) == 0);
	SET_NFLG(((uae_s32)(0)) < 0);
	x_put_word(srca + 2, 0);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, srca + 2, 0x1, 0, 1);
		return;
	}
	x_put_word(srca, 0 >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, srca + 0, 0x1, 0 >> 16, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (2/2) */
/* 4 0,0   */

/* CLR.L (xxx).L */
void REGPARAM2 op_42b9_13_ff(uae_u32 opcode)
{
	OpcodeFamily = 18;
	CurrentInstrCycles = 20; 
	struct flag_struct oldflags;
	oldflags.cznv = regflags.cznv;
	uaecptr srca;
	srca = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	srca |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	ipl_fetch_now();
	if(srca & 1) {
		srca += 2;
		get_word_ce000_prefetch(8);
		CLEAR_CZNV();
		SET_ZFLG(((uae_s32)(0)) == 0);
		SET_NFLG(((uae_s32)(0)) < 0);
		m68k_incpci(8);
		exception3_write(opcode, srca, 1, 0, 1);
		return;
	}
	regs.ir = regs.irc;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();
		SET_ZFLG(1);
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(0)) == 0);
	SET_NFLG(((uae_s32)(0)) < 0);
	x_put_word(srca + 2, 0);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, srca + 2, 0x1, 0, 1);
		return;
	}
	x_put_word(srca, 0 >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, srca + 0, 0x1, 0 >> 16, 1);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 20 (3/2) */
/* 6 0,0   */

/* MVSR2.B Dn */
#ifndef CPUEMU_68000_ONLY
void REGPARAM2 op_42c0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 32;
	CurrentInstrCycles = 4;  
	MakeSR();
	regs.ir = regs.irc;
	ipl_fetch_next();
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | ((regs.sr & 0xff) & 0xffff);
	m68k_incpci(2);
	return;
}
/* 4 (1/0) */
/* 2 0,0   */

#endif
/* MVSR2.B (An) */
#ifndef CPUEMU_68000_ONLY
void REGPARAM2 op_42d0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 32;
	CurrentInstrCycles = 10; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	do_cycles_ce000_internal(2);
	ipl_fetch_now();
	MakeSR();
	regs.ir = regs.irc;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	if(srca & 1) {
		m68k_incpci(4);
		exception3_write(opcode, srca, 1, regs.sr & 0xff, 1);
		return;
	}
	x_put_word(srca, regs.sr & 0xff);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, srca + 0, 0x1, regs.sr & 0xff, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 10 (1/1) */
/* 2 0,0   */

#endif
/* MVSR2.B (An)+ */
#ifndef CPUEMU_68000_ONLY
void REGPARAM2 op_42d8_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 32;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	do_cycles_ce000_internal(4);
	ipl_fetch_now();
	m68k_areg(regs, srcreg) += 2;
	MakeSR();
	regs.ir = regs.irc;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	if(srca & 1) {
		m68k_incpci(4);
		exception3_write(opcode, srca, 1, regs.sr & 0xff, 1);
		return;
	}
	x_put_word(srca, regs.sr & 0xff);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, srca + 0, 0x1, regs.sr & 0xff, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 12 (1/1) */
/* 2 0,0   */

#endif
/* MVSR2.B -(An) */
#ifndef CPUEMU_68000_ONLY
void REGPARAM2 op_42e0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 32;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - 2;
	do_cycles_ce000_internal(4);
	ipl_fetch_now();
	m68k_areg(regs, srcreg) = srca;
	MakeSR();
	regs.ir = regs.irc;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	if(srca & 1) {
		m68k_incpci(4);
		exception3_write(opcode, srca, 1, regs.sr & 0xff, 1);
		return;
	}
	x_put_word(srca, regs.sr & 0xff);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, srca + 0, 0x1, regs.sr & 0xff, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 12 (1/1) */
/* 2 0,0   */

#endif
/* MVSR2.B (d16,An) */
#ifndef CPUEMU_68000_ONLY
void REGPARAM2 op_42e8_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 32;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	ipl_fetch_now();
	MakeSR();
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	if(srca & 1) {
		m68k_incpci(6);
		exception3_write(opcode, srca, 1, regs.sr & 0xff, 1);
		return;
	}
	x_put_word(srca, regs.sr & 0xff);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, srca + 0, 0x1, regs.sr & 0xff, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 12 (2/1) */
/* 4 0,0   */

#endif
/* MVSR2.B (d8,An,Xn) */
#ifndef CPUEMU_68000_ONLY
void REGPARAM2 op_42f0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 32;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_ce000_prefetch(4));
	do_cycles_ce000_internal(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	ipl_fetch_now();
	MakeSR();
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	if(srca & 1) {
		m68k_incpci(6);
		exception3_write(opcode, srca, 1, regs.sr & 0xff, 1);
		return;
	}
	x_put_word(srca, regs.sr & 0xff);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, srca + 0, 0x1, regs.sr & 0xff, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (2/1) */
/* 4 4,0   */

#endif
/* MVSR2.B (xxx).W */
#ifndef CPUEMU_68000_ONLY
void REGPARAM2 op_42f8_13_ff(uae_u32 opcode)
{
	OpcodeFamily = 32;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	ipl_fetch_now();
	MakeSR();
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	if(srca & 1) {
		m68k_incpci(6);
		exception3_write(opcode, srca, 1, regs.sr & 0xff, 1);
		return;
	}
	x_put_word(srca, regs.sr & 0xff);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, srca + 0, 0x1, regs.sr & 0xff, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 12 (2/1) */
/* 4 0,0   */

#endif
/* MVSR2.B (xxx).L */
#ifndef CPUEMU_68000_ONLY
void REGPARAM2 op_42f9_13_ff(uae_u32 opcode)
{
	OpcodeFamily = 32;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	srca |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	ipl_fetch_now();
	MakeSR();
	regs.ir = regs.irc;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	opcode = regs.ir;
	if(srca & 1) {
		m68k_incpci(8);
		exception3_write(opcode, srca, 1, regs.sr & 0xff, 1);
		return;
	}
	x_put_word(srca, regs.sr & 0xff);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, srca + 0, 0x1, regs.sr & 0xff, 1);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 16 (3/1) */
/* 6 0,0   */

#endif
/* NEG.B Dn */
void REGPARAM2 op_4400_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 15;
	CurrentInstrCycles = 4;  
	uae_s8 src = m68k_dreg(regs, srcreg);
	uae_u32 dst = ((uae_u8)(0)) - ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(0)) < 0;
	int flgn = ((uae_s8)(dst)) < 0;
	SET_ZFLG(((uae_s8)(dst)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u8)(src)) > ((uae_u8)(0)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((dst) & 0xff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 4 (1/0) */
/* 2 0,0   */

/* NEG.B (An) */
void REGPARAM2 op_4410_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 15;
	CurrentInstrCycles = 12; 
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	uae_u32 dst = ((uae_u8)(0)) - ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(0)) < 0;
	int flgn = ((uae_s8)(dst)) < 0;
	SET_ZFLG(((uae_s8)(dst)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u8)(src)) > ((uae_u8)(0)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_ce000_prefetch(4);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return;
		}
		opcode = regs.ir;
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	if(loop_mode & 0xfffe) {
		do_cycles_ce000_internal(loop_mode & 0xfffe);
		loop_mode = 1;
	}
	x_put_byte(srca, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, srca + 0, 0x0, dst, 1);
		return;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return;
}
/* 12 (2/1) */
/* 2 0,0   */

/* NEG.B (An)+ */
void REGPARAM2 op_4418_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 15;
	CurrentInstrCycles = 12; 
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
	uae_u32 dst = ((uae_u8)(0)) - ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(0)) < 0;
	int flgn = ((uae_s8)(dst)) < 0;
	SET_ZFLG(((uae_s8)(dst)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u8)(src)) > ((uae_u8)(0)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_ce000_prefetch(4);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return;
		}
		opcode = regs.ir;
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	if(loop_mode & 0xfffe) {
		do_cycles_ce000_internal(loop_mode & 0xfffe);
		loop_mode = 1;
	}
	x_put_byte(srca, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, srca + 0, 0x0, dst, 1);
		return;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return;
}
/* 12 (2/1) */
/* 2 0,0   */

/* NEG.B -(An) */
void REGPARAM2 op_4420_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 15;
	CurrentInstrCycles = 14; 
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
	do_cycles_ce000_internal(2);
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	m68k_areg(regs, srcreg) = srca;
	uae_u32 dst = ((uae_u8)(0)) - ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(0)) < 0;
	int flgn = ((uae_s8)(dst)) < 0;
	SET_ZFLG(((uae_s8)(dst)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u8)(src)) > ((uae_u8)(0)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_ce000_prefetch(4);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return;
		}
		opcode = regs.ir;
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	if(loop_mode & 0xfffe) {
		do_cycles_ce000_internal(loop_mode & 0xfffe);
		loop_mode = 1;
	}
	x_put_byte(srca, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, srca + 0, 0x0, dst, 1);
		return;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return;
}
/* 14 (2/1) */
/* 2 0,0   */

/* NEG.B (d16,An) */
void REGPARAM2 op_4428_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 15;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	uae_u32 dst = ((uae_u8)(0)) - ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(0)) < 0;
	int flgn = ((uae_s8)(dst)) < 0;
	SET_ZFLG(((uae_s8)(dst)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u8)(src)) > ((uae_u8)(0)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_byte(srca, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, srca + 0, 0x0, dst, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* NEG.B (d8,An,Xn) */
void REGPARAM2 op_4430_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 15;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	do_cycles_ce000_internal(2);
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	uae_u32 dst = ((uae_u8)(0)) - ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(0)) < 0;
	int flgn = ((uae_s8)(dst)) < 0;
	SET_ZFLG(((uae_s8)(dst)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u8)(src)) > ((uae_u8)(0)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_byte(srca, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, srca + 0, 0x0, dst, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 18 (3/1) */
/* 4 4,0   */

/* NEG.B (xxx).W */
void REGPARAM2 op_4438_13_ff(uae_u32 opcode)
{
	OpcodeFamily = 15;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	uae_u32 dst = ((uae_u8)(0)) - ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(0)) < 0;
	int flgn = ((uae_s8)(dst)) < 0;
	SET_ZFLG(((uae_s8)(dst)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u8)(src)) > ((uae_u8)(0)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_byte(srca, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, srca + 0, 0x0, dst, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* NEG.B (xxx).L */
void REGPARAM2 op_4439_13_ff(uae_u32 opcode)
{
	OpcodeFamily = 15;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	srca = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	srca |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	uae_u32 dst = ((uae_u8)(0)) - ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(0)) < 0;
	int flgn = ((uae_s8)(dst)) < 0;
	SET_ZFLG(((uae_s8)(dst)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u8)(src)) > ((uae_u8)(0)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_byte(srca, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, srca + 0, 0x0, dst, 1);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 20 (4/1) */
/* 6 0,0   */

/* NEG.W Dn */
void REGPARAM2 op_4440_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 15;
	CurrentInstrCycles = 4;  
	uae_s16 src = m68k_dreg(regs, srcreg);
	uae_u32 dst = ((uae_u16)(0)) - ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(0)) < 0;
	int flgn = ((uae_s16)(dst)) < 0;
	SET_ZFLG(((uae_s16)(dst)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u16)(src)) > ((uae_u16)(0)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | ((dst) & 0xffff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 4 (1/0) */
/* 2 0,0   */

/* NEG.W (An) */
void REGPARAM2 op_4450_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 15;
	CurrentInstrCycles = 12; 
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access2(opcode, srca, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	uae_u32 dst = ((uae_u16)(0)) - ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(0)) < 0;
	int flgn = ((uae_s16)(dst)) < 0;
	SET_ZFLG(((uae_s16)(dst)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u16)(src)) > ((uae_u16)(0)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_ce000_prefetch(4);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return;
		}
		opcode = regs.ir;
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	if(loop_mode & 0xfffe) {
		do_cycles_ce000_internal(loop_mode & 0xfffe);
		loop_mode = 1;
	}
	x_put_word(srca, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, srca + 0, 0x1, dst, 1);
		return;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return;
}
/* 12 (2/1) */
/* 2 0,0   */

/* NEG.W (An)+ */
void REGPARAM2 op_4458_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 15;
	CurrentInstrCycles = 12; 
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_areg(regs, srcreg) += 2 + 0;
		m68k_incpci(2);
		exception3_read_access2(opcode, srca, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) += 2 + 0;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	m68k_areg(regs, srcreg) += 2;
	uae_u32 dst = ((uae_u16)(0)) - ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(0)) < 0;
	int flgn = ((uae_s16)(dst)) < 0;
	SET_ZFLG(((uae_s16)(dst)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u16)(src)) > ((uae_u16)(0)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_ce000_prefetch(4);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return;
		}
		opcode = regs.ir;
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	if(loop_mode & 0xfffe) {
		do_cycles_ce000_internal(loop_mode & 0xfffe);
		loop_mode = 1;
	}
	x_put_word(srca, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, srca + 0, 0x1, dst, 1);
		return;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return;
}
/* 12 (2/1) */
/* 2 0,0   */

/* NEG.W -(An) */
void REGPARAM2 op_4460_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 15;
	CurrentInstrCycles = 14; 
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - 2;
	do_cycles_ce000_internal(2);
	if (srca & 1) {
		m68k_areg(regs, srcreg) = srca;
		m68k_incpci(2);
		exception3_read_access2(opcode, srca, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	m68k_areg(regs, srcreg) = srca;
	uae_u32 dst = ((uae_u16)(0)) - ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(0)) < 0;
	int flgn = ((uae_s16)(dst)) < 0;
	SET_ZFLG(((uae_s16)(dst)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u16)(src)) > ((uae_u16)(0)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_ce000_prefetch(4);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return;
		}
		opcode = regs.ir;
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	if(loop_mode & 0xfffe) {
		do_cycles_ce000_internal(loop_mode & 0xfffe);
		loop_mode = 1;
	}
	x_put_word(srca, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, srca + 0, 0x1, dst, 1);
		return;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return;
}
/* 14 (2/1) */
/* 2 0,0   */

/* NEG.W (d16,An) */
void REGPARAM2 op_4468_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 15;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	uae_u32 dst = ((uae_u16)(0)) - ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(0)) < 0;
	int flgn = ((uae_s16)(dst)) < 0;
	SET_ZFLG(((uae_s16)(dst)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u16)(src)) > ((uae_u16)(0)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_word(srca, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, srca + 0, 0x1, dst, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* NEG.W (d8,An,Xn) */
void REGPARAM2 op_4470_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 15;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	do_cycles_ce000_internal(2);
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	uae_u32 dst = ((uae_u16)(0)) - ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(0)) < 0;
	int flgn = ((uae_s16)(dst)) < 0;
	SET_ZFLG(((uae_s16)(dst)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u16)(src)) > ((uae_u16)(0)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_word(srca, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, srca + 0, 0x1, dst, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 18 (3/1) */
/* 4 4,0   */

/* NEG.W (xxx).W */
void REGPARAM2 op_4478_13_ff(uae_u32 opcode)
{
	OpcodeFamily = 15;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	if (srca & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	uae_u32 dst = ((uae_u16)(0)) - ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(0)) < 0;
	int flgn = ((uae_s16)(dst)) < 0;
	SET_ZFLG(((uae_s16)(dst)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u16)(src)) > ((uae_u16)(0)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_word(srca, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, srca + 0, 0x1, dst, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* NEG.W (xxx).L */
void REGPARAM2 op_4479_13_ff(uae_u32 opcode)
{
	OpcodeFamily = 15;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	srca = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	srca |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	if (srca & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	uae_u32 dst = ((uae_u16)(0)) - ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(0)) < 0;
	int flgn = ((uae_s16)(dst)) < 0;
	SET_ZFLG(((uae_s16)(dst)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u16)(src)) > ((uae_u16)(0)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_word(srca, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, srca + 0, 0x1, dst, 1);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 20 (4/1) */
/* 6 0,0   */

/* NEG.L Dn */
void REGPARAM2 op_4480_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 15;
	CurrentInstrCycles = 6;  
	uae_s32 src = m68k_dreg(regs, srcreg);
	uae_u32 dst = ((uae_u32)(0)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(0)) < 0;
	int flgn = ((uae_s32)(dst)) < 0;
	SET_ZFLG(((uae_s32)(dst)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(0)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		dreg_68000_long_replace_low(srcreg, dst);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	m68k_dreg(regs, srcreg) = (dst);
	do_cycles_ce000_internal(2);
	m68k_incpci(2);
	return;
}
/* 6 (1/0) */
/* 2 0,0   */

/* NEG.L (An) */
void REGPARAM2 op_4490_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 15;
	CurrentInstrCycles = 20; 
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	uae_u32 dst = ((uae_u32)(0)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(0)) < 0;
	int flgn = ((uae_s32)(dst)) < 0;
	SET_ZFLG(((uae_s32)(dst)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(0)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_ce000_prefetch(4);
		if(hardware_bus_error) {
			int pcoffset = 0;
			int bflgs = ((uae_s16)(src)) < 0;
			int bflgo = ((uae_s16)(0)) < 0;
			int bflgn = ((uae_s16)(dst)) < 0;
			SET_ZFLG(((uae_s16)(dst)) == 0);
			SET_VFLG((bflgs ^ bflgo) & (bflgn ^ bflgo));
			SET_CFLG(((uae_u16)(src)) > ((uae_u16)(0)));
			SET_NFLG(bflgn != 0);
			SET_XFLG(GET_CFLG());
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return;
		}
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	if(loop_mode & 0xfffe) {
		do_cycles_ce000_internal(loop_mode & 0xfffe);
		loop_mode = 1;
	}
	x_put_word(srca + 2, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, srca + 2, 0x1, dst, 1);
		return;
	}
	x_put_word(srca, dst >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, srca + 0, 0x1, dst >> 16, 1);
		return;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return;
}
/* 20 (3/2) */
/* 2 0,0   */

/* NEG.L (An)+ */
void REGPARAM2 op_4498_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 15;
	CurrentInstrCycles = 20; 
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	m68k_areg(regs, srcreg) += 4;
	uae_u32 dst = ((uae_u32)(0)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(0)) < 0;
	int flgn = ((uae_s32)(dst)) < 0;
	SET_ZFLG(((uae_s32)(dst)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(0)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_ce000_prefetch(4);
		if(hardware_bus_error) {
			int pcoffset = 0;
			int bflgs = ((uae_s16)(src)) < 0;
			int bflgo = ((uae_s16)(0)) < 0;
			int bflgn = ((uae_s16)(dst)) < 0;
			SET_ZFLG(((uae_s16)(dst)) == 0);
			SET_VFLG((bflgs ^ bflgo) & (bflgn ^ bflgo));
			SET_CFLG(((uae_u16)(src)) > ((uae_u16)(0)));
			SET_NFLG(bflgn != 0);
			SET_XFLG(GET_CFLG());
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return;
		}
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	if(loop_mode & 0xfffe) {
		do_cycles_ce000_internal(loop_mode & 0xfffe);
		loop_mode = 1;
	}
	x_put_word(srca + 2, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, srca + 2, 0x1, dst, 1);
		return;
	}
	x_put_word(srca, dst >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, srca + 0, 0x1, dst >> 16, 1);
		return;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return;
}
/* 20 (3/2) */
/* 2 0,0   */

/* NEG.L -(An) */
void REGPARAM2 op_44a0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 15;
	CurrentInstrCycles = 22; 
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - 4;
	do_cycles_ce000_internal(2);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	m68k_areg(regs, srcreg) = srca;
	uae_u32 dst = ((uae_u32)(0)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(0)) < 0;
	int flgn = ((uae_s32)(dst)) < 0;
	SET_ZFLG(((uae_s32)(dst)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(0)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_ce000_prefetch(4);
		if(hardware_bus_error) {
			int pcoffset = 0;
			int bflgs = ((uae_s16)(src)) < 0;
			int bflgo = ((uae_s16)(0)) < 0;
			int bflgn = ((uae_s16)(dst)) < 0;
			SET_ZFLG(((uae_s16)(dst)) == 0);
			SET_VFLG((bflgs ^ bflgo) & (bflgn ^ bflgo));
			SET_CFLG(((uae_u16)(src)) > ((uae_u16)(0)));
			SET_NFLG(bflgn != 0);
			SET_XFLG(GET_CFLG());
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return;
		}
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	if(loop_mode & 0xfffe) {
		do_cycles_ce000_internal(loop_mode & 0xfffe);
		loop_mode = 1;
	}
	x_put_word(srca + 2, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, srca + 2, 0x1, dst, 1);
		return;
	}
	x_put_word(srca, dst >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, srca + 0, 0x1, dst >> 16, 1);
		return;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return;
}
/* 22 (3/2) */
/* 2 0,0   */

/* NEG.L (d16,An) */
void REGPARAM2 op_44a8_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 15;
	CurrentInstrCycles = 24; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	uae_u32 dst = ((uae_u32)(0)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(0)) < 0;
	int flgn = ((uae_s32)(dst)) < 0;
	SET_ZFLG(((uae_s32)(dst)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(0)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		int bflgs = ((uae_s16)(src)) < 0;
		int bflgo = ((uae_s16)(0)) < 0;
		int bflgn = ((uae_s16)(dst)) < 0;
		SET_ZFLG(((uae_s16)(dst)) == 0);
		SET_VFLG((bflgs ^ bflgo) & (bflgn ^ bflgo));
		SET_CFLG(((uae_u16)(src)) > ((uae_u16)(0)));
		SET_NFLG(bflgn != 0);
		SET_XFLG(GET_CFLG());
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	x_put_word(srca + 2, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, srca + 2, 0x1, dst, 1);
		return;
	}
	x_put_word(srca, dst >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, srca + 0, 0x1, dst >> 16, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 24 (4/2) */
/* 4 0,0   */

/* NEG.L (d8,An,Xn) */
void REGPARAM2 op_44b0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 15;
	CurrentInstrCycles = 26; 
	uaecptr srca;
	do_cycles_ce000_internal(2);
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	uae_u32 dst = ((uae_u32)(0)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(0)) < 0;
	int flgn = ((uae_s32)(dst)) < 0;
	SET_ZFLG(((uae_s32)(dst)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(0)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		int bflgs = ((uae_s16)(src)) < 0;
		int bflgo = ((uae_s16)(0)) < 0;
		int bflgn = ((uae_s16)(dst)) < 0;
		SET_ZFLG(((uae_s16)(dst)) == 0);
		SET_VFLG((bflgs ^ bflgo) & (bflgn ^ bflgo));
		SET_CFLG(((uae_u16)(src)) > ((uae_u16)(0)));
		SET_NFLG(bflgn != 0);
		SET_XFLG(GET_CFLG());
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	x_put_word(srca + 2, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, srca + 2, 0x1, dst, 1);
		return;
	}
	x_put_word(srca, dst >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, srca + 0, 0x1, dst >> 16, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 26 (4/2) */
/* 4 4,0   */

/* NEG.L (xxx).W */
void REGPARAM2 op_44b8_13_ff(uae_u32 opcode)
{
	OpcodeFamily = 15;
	CurrentInstrCycles = 24; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	if (srca & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	uae_u32 dst = ((uae_u32)(0)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(0)) < 0;
	int flgn = ((uae_s32)(dst)) < 0;
	SET_ZFLG(((uae_s32)(dst)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(0)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		int bflgs = ((uae_s16)(src)) < 0;
		int bflgo = ((uae_s16)(0)) < 0;
		int bflgn = ((uae_s16)(dst)) < 0;
		SET_ZFLG(((uae_s16)(dst)) == 0);
		SET_VFLG((bflgs ^ bflgo) & (bflgn ^ bflgo));
		SET_CFLG(((uae_u16)(src)) > ((uae_u16)(0)));
		SET_NFLG(bflgn != 0);
		SET_XFLG(GET_CFLG());
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	x_put_word(srca + 2, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, srca + 2, 0x1, dst, 1);
		return;
	}
	x_put_word(srca, dst >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, srca + 0, 0x1, dst >> 16, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 24 (4/2) */
/* 4 0,0   */

/* NEG.L (xxx).L */
void REGPARAM2 op_44b9_13_ff(uae_u32 opcode)
{
	OpcodeFamily = 15;
	CurrentInstrCycles = 28; 
	uaecptr srca;
	srca = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	srca |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	if (srca & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	uae_u32 dst = ((uae_u32)(0)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(0)) < 0;
	int flgn = ((uae_s32)(dst)) < 0;
	SET_ZFLG(((uae_s32)(dst)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(0)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		int bflgs = ((uae_s16)(src)) < 0;
		int bflgo = ((uae_s16)(0)) < 0;
		int bflgn = ((uae_s16)(dst)) < 0;
		SET_ZFLG(((uae_s16)(dst)) == 0);
		SET_VFLG((bflgs ^ bflgo) & (bflgn ^ bflgo));
		SET_CFLG(((uae_u16)(src)) > ((uae_u16)(0)));
		SET_NFLG(bflgn != 0);
		SET_XFLG(GET_CFLG());
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	x_put_word(srca + 2, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, srca + 2, 0x1, dst, 1);
		return;
	}
	x_put_word(srca, dst >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, srca + 0, 0x1, dst >> 16, 1);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 28 (5/2) */
/* 6 0,0   */

/* MV2SR.B Dn */
void REGPARAM2 op_44c0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 33;
	CurrentInstrCycles = 12; 
	uae_s16 src = m68k_dreg(regs, srcreg);
	do_cycles_ce000_internal(4);
	MakeSR();
	regs.sr &= 0xFF00;
	regs.sr |= src & 0xFF;
	MakeFromSR();
	m68k_incpci(2);
	get_word_ce000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, 0);
		return;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 12 (2/0) */
/* 2 0,0   */

/* MV2SR.B (An) */
void REGPARAM2 op_44d0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 33;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access2(opcode, srca, 1, 1);
		return;
	}
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	do_cycles_ce000_internal(4);
	MakeSR();
	regs.sr &= 0xFF00;
	regs.sr |= src & 0xFF;
	MakeFromSR();
	m68k_incpci(2);
	get_word_ce000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, 0);
		return;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 16 (3/0) */
/* 2 0,0   */

/* MV2SR.B (An)+ */
void REGPARAM2 op_44d8_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 33;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_areg(regs, srcreg) += 2 + 0;
		m68k_incpci(2);
		exception3_read_access2(opcode, srca, 1, 1);
		return;
	}
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) += 2 + 0;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	m68k_areg(regs, srcreg) += 2;
	do_cycles_ce000_internal(4);
	MakeSR();
	regs.sr &= 0xFF00;
	regs.sr |= src & 0xFF;
	MakeFromSR();
	m68k_incpci(2);
	get_word_ce000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, 0);
		return;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 16 (3/0) */
/* 2 0,0   */

/* MV2SR.B -(An) */
void REGPARAM2 op_44e0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 33;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - 2;
	do_cycles_ce000_internal(2);
	if (srca & 1) {
		m68k_areg(regs, srcreg) = srca;
		m68k_incpci(2);
		exception3_read_access2(opcode, srca, 1, 1);
		return;
	}
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	m68k_areg(regs, srcreg) = srca;
	do_cycles_ce000_internal(4);
	MakeSR();
	regs.sr &= 0xFF00;
	regs.sr |= src & 0xFF;
	MakeFromSR();
	m68k_incpci(2);
	get_word_ce000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, 0);
		return;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 18 (3/0) */
/* 2 0,0   */

/* MV2SR.B (d16,An) */
void REGPARAM2 op_44e8_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 33;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	do_cycles_ce000_internal(4);
	MakeSR();
	regs.sr &= 0xFF00;
	regs.sr |= src & 0xFF;
	MakeFromSR();
	m68k_incpci(4);
	get_word_ce000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, 0);
		return;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 20 (4/0) */
/* 4 0,0   */

/* MV2SR.B (d8,An,Xn) */
void REGPARAM2 op_44f0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 33;
	CurrentInstrCycles = 22; 
	uaecptr srca;
	do_cycles_ce000_internal(2);
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	do_cycles_ce000_internal(4);
	MakeSR();
	regs.sr &= 0xFF00;
	regs.sr |= src & 0xFF;
	MakeFromSR();
	m68k_incpci(4);
	get_word_ce000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, 0);
		return;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 22 (4/0) */
/* 4 4,0   */

/* MV2SR.B (xxx).W */
void REGPARAM2 op_44f8_13_ff(uae_u32 opcode)
{
	OpcodeFamily = 33;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	if (srca & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	do_cycles_ce000_internal(4);
	MakeSR();
	regs.sr &= 0xFF00;
	regs.sr |= src & 0xFF;
	MakeFromSR();
	m68k_incpci(4);
	get_word_ce000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, 0);
		return;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 20 (4/0) */
/* 4 0,0   */

/* MV2SR.B (xxx).L */
void REGPARAM2 op_44f9_13_ff(uae_u32 opcode)
{
	OpcodeFamily = 33;
	CurrentInstrCycles = 24; 
	uaecptr srca;
	srca = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	srca |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	if (srca & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	do_cycles_ce000_internal(4);
	MakeSR();
	regs.sr &= 0xFF00;
	regs.sr |= src & 0xFF;
	MakeFromSR();
	m68k_incpci(6);
	get_word_ce000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, 0);
		return;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 24 (5/0) */
/* 6 0,0   */

/* MV2SR.B (d16,PC) */
void REGPARAM2 op_44fa_13_ff(uae_u32 opcode)
{
	OpcodeFamily = 33;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	srca = m68k_getpci() + 2;
	srca += (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 2);
		return;
	}
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return;
	}
	do_cycles_ce000_internal(4);
	MakeSR();
	regs.sr &= 0xFF00;
	regs.sr |= src & 0xFF;
	MakeFromSR();
	m68k_incpci(4);
	get_word_ce000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, 0);
		return;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 20 (4/0) */
/* 4 0,0   */

/* MV2SR.B (d8,PC,Xn) */
void REGPARAM2 op_44fb_13_ff(uae_u32 opcode)
{
	OpcodeFamily = 33;
	CurrentInstrCycles = 22; 
	uaecptr srca;
	uaecptr tmppc = m68k_getpci() + 2;
	do_cycles_ce000_internal(2);
	srca = get_disp_ea_000(tmppc, get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 2);
		return;
	}
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return;
	}
	do_cycles_ce000_internal(4);
	MakeSR();
	regs.sr &= 0xFF00;
	regs.sr |= src & 0xFF;
	MakeFromSR();
	m68k_incpci(4);
	get_word_ce000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, 0);
		return;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 22 (4/0) */
/* 4 4,0   */

/* MV2SR.B #<data>.B */
void REGPARAM2 op_44fc_13_ff(uae_u32 opcode)
{
	OpcodeFamily = 33;
	CurrentInstrCycles = 16; 
	uae_s16 src = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	do_cycles_ce000_internal(4);
	MakeSR();
	regs.sr &= 0xFF00;
	regs.sr |= src & 0xFF;
	MakeFromSR();
	m68k_incpci(4);
	get_word_ce000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, 0);
		return;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 16 (3/0) */
/* 4 0,0   */

/* NOT.B Dn */
void REGPARAM2 op_4600_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 19;
	CurrentInstrCycles = 4;  
	uae_s8 src = m68k_dreg(regs, srcreg);
	uae_u32 dst = ~src;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(dst)) == 0);
	SET_NFLG(((uae_s8)(dst)) < 0);
	m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((dst) & 0xff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 4 (1/0) */
/* 2 0,0   */

/* NOT.B (An) */
void REGPARAM2 op_4610_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 19;
	CurrentInstrCycles = 12; 
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	uae_u32 dst = ~src;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(dst)) == 0);
	SET_NFLG(((uae_s8)(dst)) < 0);
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_ce000_prefetch(4);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return;
		}
		opcode = regs.ir;
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	if(loop_mode & 0xfffe) {
		do_cycles_ce000_internal(loop_mode & 0xfffe);
		loop_mode = 1;
	}
	x_put_byte(srca, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, srca + 0, 0x0, dst, 1);
		return;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return;
}
/* 12 (2/1) */
/* 2 0,0   */

/* NOT.B (An)+ */
void REGPARAM2 op_4618_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 19;
	CurrentInstrCycles = 12; 
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
	uae_u32 dst = ~src;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(dst)) == 0);
	SET_NFLG(((uae_s8)(dst)) < 0);
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_ce000_prefetch(4);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return;
		}
		opcode = regs.ir;
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	if(loop_mode & 0xfffe) {
		do_cycles_ce000_internal(loop_mode & 0xfffe);
		loop_mode = 1;
	}
	x_put_byte(srca, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, srca + 0, 0x0, dst, 1);
		return;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return;
}
/* 12 (2/1) */
/* 2 0,0   */

/* NOT.B -(An) */
void REGPARAM2 op_4620_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 19;
	CurrentInstrCycles = 14; 
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
	do_cycles_ce000_internal(2);
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	m68k_areg(regs, srcreg) = srca;
	uae_u32 dst = ~src;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(dst)) == 0);
	SET_NFLG(((uae_s8)(dst)) < 0);
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_ce000_prefetch(4);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return;
		}
		opcode = regs.ir;
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	if(loop_mode & 0xfffe) {
		do_cycles_ce000_internal(loop_mode & 0xfffe);
		loop_mode = 1;
	}
	x_put_byte(srca, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, srca + 0, 0x0, dst, 1);
		return;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return;
}
/* 14 (2/1) */
/* 2 0,0   */

/* NOT.B (d16,An) */
void REGPARAM2 op_4628_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 19;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	uae_u32 dst = ~src;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(dst)) == 0);
	SET_NFLG(((uae_s8)(dst)) < 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_byte(srca, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, srca + 0, 0x0, dst, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* NOT.B (d8,An,Xn) */
void REGPARAM2 op_4630_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 19;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	do_cycles_ce000_internal(2);
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	uae_u32 dst = ~src;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(dst)) == 0);
	SET_NFLG(((uae_s8)(dst)) < 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_byte(srca, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, srca + 0, 0x0, dst, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 18 (3/1) */
/* 4 4,0   */

/* NOT.B (xxx).W */
void REGPARAM2 op_4638_13_ff(uae_u32 opcode)
{
	OpcodeFamily = 19;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	uae_u32 dst = ~src;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(dst)) == 0);
	SET_NFLG(((uae_s8)(dst)) < 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_byte(srca, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, srca + 0, 0x0, dst, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* NOT.B (xxx).L */
void REGPARAM2 op_4639_13_ff(uae_u32 opcode)
{
	OpcodeFamily = 19;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	srca = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	srca |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	uae_u32 dst = ~src;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(dst)) == 0);
	SET_NFLG(((uae_s8)(dst)) < 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_byte(srca, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, srca + 0, 0x0, dst, 1);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 20 (4/1) */
/* 6 0,0   */

/* NOT.W Dn */
void REGPARAM2 op_4640_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 19;
	CurrentInstrCycles = 4;  
	uae_s16 src = m68k_dreg(regs, srcreg);
	uae_u32 dst = ~src;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(dst)) == 0);
	SET_NFLG(((uae_s16)(dst)) < 0);
	m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | ((dst) & 0xffff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 4 (1/0) */
/* 2 0,0   */

/* NOT.W (An) */
void REGPARAM2 op_4650_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 19;
	CurrentInstrCycles = 12; 
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access2(opcode, srca, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	uae_u32 dst = ~src;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(dst)) == 0);
	SET_NFLG(((uae_s16)(dst)) < 0);
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_ce000_prefetch(4);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return;
		}
		opcode = regs.ir;
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	if(loop_mode & 0xfffe) {
		do_cycles_ce000_internal(loop_mode & 0xfffe);
		loop_mode = 1;
	}
	x_put_word(srca, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, srca + 0, 0x1, dst, 1);
		return;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return;
}
/* 12 (2/1) */
/* 2 0,0   */

/* NOT.W (An)+ */
void REGPARAM2 op_4658_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 19;
	CurrentInstrCycles = 12; 
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_areg(regs, srcreg) += 2 + 0;
		m68k_incpci(2);
		exception3_read_access2(opcode, srca, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) += 2 + 0;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	m68k_areg(regs, srcreg) += 2;
	uae_u32 dst = ~src;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(dst)) == 0);
	SET_NFLG(((uae_s16)(dst)) < 0);
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_ce000_prefetch(4);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return;
		}
		opcode = regs.ir;
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	if(loop_mode & 0xfffe) {
		do_cycles_ce000_internal(loop_mode & 0xfffe);
		loop_mode = 1;
	}
	x_put_word(srca, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, srca + 0, 0x1, dst, 1);
		return;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return;
}
/* 12 (2/1) */
/* 2 0,0   */

/* NOT.W -(An) */
void REGPARAM2 op_4660_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 19;
	CurrentInstrCycles = 14; 
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - 2;
	do_cycles_ce000_internal(2);
	if (srca & 1) {
		m68k_areg(regs, srcreg) = srca;
		m68k_incpci(2);
		exception3_read_access2(opcode, srca, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	m68k_areg(regs, srcreg) = srca;
	uae_u32 dst = ~src;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(dst)) == 0);
	SET_NFLG(((uae_s16)(dst)) < 0);
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_ce000_prefetch(4);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return;
		}
		opcode = regs.ir;
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	if(loop_mode & 0xfffe) {
		do_cycles_ce000_internal(loop_mode & 0xfffe);
		loop_mode = 1;
	}
	x_put_word(srca, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, srca + 0, 0x1, dst, 1);
		return;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return;
}
/* 14 (2/1) */
/* 2 0,0   */

/* NOT.W (d16,An) */
void REGPARAM2 op_4668_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 19;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	uae_u32 dst = ~src;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(dst)) == 0);
	SET_NFLG(((uae_s16)(dst)) < 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_word(srca, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, srca + 0, 0x1, dst, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* NOT.W (d8,An,Xn) */
void REGPARAM2 op_4670_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 19;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	do_cycles_ce000_internal(2);
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	uae_u32 dst = ~src;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(dst)) == 0);
	SET_NFLG(((uae_s16)(dst)) < 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_word(srca, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, srca + 0, 0x1, dst, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 18 (3/1) */
/* 4 4,0   */

/* NOT.W (xxx).W */
void REGPARAM2 op_4678_13_ff(uae_u32 opcode)
{
	OpcodeFamily = 19;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	if (srca & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	uae_u32 dst = ~src;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(dst)) == 0);
	SET_NFLG(((uae_s16)(dst)) < 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_word(srca, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, srca + 0, 0x1, dst, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* NOT.W (xxx).L */
void REGPARAM2 op_4679_13_ff(uae_u32 opcode)
{
	OpcodeFamily = 19;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	srca = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	srca |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	if (srca & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	uae_u32 dst = ~src;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(dst)) == 0);
	SET_NFLG(((uae_s16)(dst)) < 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_word(srca, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, srca + 0, 0x1, dst, 1);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 20 (4/1) */
/* 6 0,0   */

/* NOT.L Dn */
void REGPARAM2 op_4680_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 19;
	CurrentInstrCycles = 6;  
	uae_s32 src = m68k_dreg(regs, srcreg);
	uae_u32 dst = ~src;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(dst)) == 0);
	SET_NFLG(((uae_s32)(dst)) < 0);
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		dreg_68000_long_replace_low(srcreg, dst);
		SET_VFLG(0);SET_ZFLG(!dst);
		SET_NFLG(dst & 0x80000000);
		SET_CFLG(0);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	m68k_dreg(regs, srcreg) = (dst);
	do_cycles_ce000_internal(2);
	m68k_incpci(2);
	return;
}
/* 6 (1/0) */
/* 2 0,0   */

/* NOT.L (An) */
void REGPARAM2 op_4690_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 19;
	CurrentInstrCycles = 20; 
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	uae_u32 dst = ~src;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(dst)) == 0);
	SET_NFLG(((uae_s32)(dst)) < 0);
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_ce000_prefetch(4);
		if(hardware_bus_error) {
			int pcoffset = 0;
			SET_VFLG(0);
			SET_ZFLG(!(dst & 0xffff));
			SET_NFLG(dst & 0x8000);
			SET_CFLG(0);
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return;
		}
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	if(loop_mode & 0xfffe) {
		do_cycles_ce000_internal(loop_mode & 0xfffe);
		loop_mode = 1;
	}
	x_put_word(srca + 2, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, srca + 2, 0x1, dst, 1);
		return;
	}
	x_put_word(srca, dst >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, srca + 0, 0x1, dst >> 16, 1);
		return;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return;
}
/* 20 (3/2) */
/* 2 0,0   */

/* NOT.L (An)+ */
void REGPARAM2 op_4698_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 19;
	CurrentInstrCycles = 20; 
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	m68k_areg(regs, srcreg) += 4;
	uae_u32 dst = ~src;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(dst)) == 0);
	SET_NFLG(((uae_s32)(dst)) < 0);
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_ce000_prefetch(4);
		if(hardware_bus_error) {
			int pcoffset = 0;
			SET_VFLG(0);
			SET_ZFLG(!(dst & 0xffff));
			SET_NFLG(dst & 0x8000);
			SET_CFLG(0);
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return;
		}
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	if(loop_mode & 0xfffe) {
		do_cycles_ce000_internal(loop_mode & 0xfffe);
		loop_mode = 1;
	}
	x_put_word(srca + 2, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, srca + 2, 0x1, dst, 1);
		return;
	}
	x_put_word(srca, dst >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, srca + 0, 0x1, dst >> 16, 1);
		return;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return;
}
/* 20 (3/2) */
/* 2 0,0   */

/* NOT.L -(An) */
void REGPARAM2 op_46a0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 19;
	CurrentInstrCycles = 22; 
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - 4;
	do_cycles_ce000_internal(2);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	m68k_areg(regs, srcreg) = srca;
	uae_u32 dst = ~src;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(dst)) == 0);
	SET_NFLG(((uae_s32)(dst)) < 0);
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_ce000_prefetch(4);
		if(hardware_bus_error) {
			int pcoffset = 0;
			SET_VFLG(0);
			SET_ZFLG(!(dst & 0xffff));
			SET_NFLG(dst & 0x8000);
			SET_CFLG(0);
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return;
		}
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	if(loop_mode & 0xfffe) {
		do_cycles_ce000_internal(loop_mode & 0xfffe);
		loop_mode = 1;
	}
	x_put_word(srca + 2, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, srca + 2, 0x1, dst, 1);
		return;
	}
	x_put_word(srca, dst >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, srca + 0, 0x1, dst >> 16, 1);
		return;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return;
}
/* 22 (3/2) */
/* 2 0,0   */

/* NOT.L (d16,An) */
void REGPARAM2 op_46a8_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 19;
	CurrentInstrCycles = 24; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	uae_u32 dst = ~src;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(dst)) == 0);
	SET_NFLG(((uae_s32)(dst)) < 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		SET_VFLG(0);
		SET_ZFLG(!(dst & 0xffff));
		SET_NFLG(dst & 0x8000);
		SET_CFLG(0);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	x_put_word(srca + 2, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, srca + 2, 0x1, dst, 1);
		return;
	}
	x_put_word(srca, dst >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, srca + 0, 0x1, dst >> 16, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 24 (4/2) */
/* 4 0,0   */

/* NOT.L (d8,An,Xn) */
void REGPARAM2 op_46b0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 19;
	CurrentInstrCycles = 26; 
	uaecptr srca;
	do_cycles_ce000_internal(2);
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	uae_u32 dst = ~src;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(dst)) == 0);
	SET_NFLG(((uae_s32)(dst)) < 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		SET_VFLG(0);
		SET_ZFLG(!(dst & 0xffff));
		SET_NFLG(dst & 0x8000);
		SET_CFLG(0);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	x_put_word(srca + 2, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, srca + 2, 0x1, dst, 1);
		return;
	}
	x_put_word(srca, dst >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, srca + 0, 0x1, dst >> 16, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 26 (4/2) */
/* 4 4,0   */

/* NOT.L (xxx).W */
void REGPARAM2 op_46b8_13_ff(uae_u32 opcode)
{
	OpcodeFamily = 19;
	CurrentInstrCycles = 24; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	if (srca & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	uae_u32 dst = ~src;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(dst)) == 0);
	SET_NFLG(((uae_s32)(dst)) < 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		SET_VFLG(0);
		SET_ZFLG(!(dst & 0xffff));
		SET_NFLG(dst & 0x8000);
		SET_CFLG(0);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	x_put_word(srca + 2, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, srca + 2, 0x1, dst, 1);
		return;
	}
	x_put_word(srca, dst >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, srca + 0, 0x1, dst >> 16, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 24 (4/2) */
/* 4 0,0   */

/* NOT.L (xxx).L */
void REGPARAM2 op_46b9_13_ff(uae_u32 opcode)
{
	OpcodeFamily = 19;
	CurrentInstrCycles = 28; 
	uaecptr srca;
	srca = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	srca |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	if (srca & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	uae_u32 dst = ~src;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(dst)) == 0);
	SET_NFLG(((uae_s32)(dst)) < 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		SET_VFLG(0);
		SET_ZFLG(!(dst & 0xffff));
		SET_NFLG(dst & 0x8000);
		SET_CFLG(0);
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	x_put_word(srca + 2, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, srca + 2, 0x1, dst, 1);
		return;
	}
	x_put_word(srca, dst >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, srca + 0, 0x1, dst >> 16, 1);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 28 (5/2) */
/* 6 0,0   */

/* MV2SR.W Dn */
void REGPARAM2 op_46c0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 33;
	CurrentInstrCycles = 12; 
	if (!regs.s) {
		Exception(8);
		return;
	}
	uae_s16 src = m68k_dreg(regs, srcreg);
	do_cycles_ce000_internal(4);
	regs.sr = src;
	MakeFromSR();
	m68k_incpci(2);
	get_word_ce000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, 0);
		return;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 12 (2/0) */
/* 2 0,0   */

/* MV2SR.W (An) */
void REGPARAM2 op_46d0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 33;
	CurrentInstrCycles = 16; 
	if (!regs.s) {
		Exception(8);
		return;
	}
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access2(opcode, srca, 1, 1);
		return;
	}
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	do_cycles_ce000_internal(4);
	regs.sr = src;
	MakeFromSR();
	m68k_incpci(2);
	get_word_ce000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, 0);
		return;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 16 (3/0) */
/* 2 0,0   */

/* MV2SR.W (An)+ */
void REGPARAM2 op_46d8_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 33;
	CurrentInstrCycles = 16; 
	if (!regs.s) {
		Exception(8);
		return;
	}
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_areg(regs, srcreg) += 2 + 0;
		m68k_incpci(2);
		exception3_read_access2(opcode, srca, 1, 1);
		return;
	}
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) += 2 + 0;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	m68k_areg(regs, srcreg) += 2;
	do_cycles_ce000_internal(4);
	regs.sr = src;
	MakeFromSR();
	m68k_incpci(2);
	get_word_ce000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, 0);
		return;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 16 (3/0) */
/* 2 0,0   */

/* MV2SR.W -(An) */
void REGPARAM2 op_46e0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 33;
	CurrentInstrCycles = 18; 
	if (!regs.s) {
		Exception(8);
		return;
	}
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - 2;
	do_cycles_ce000_internal(2);
	if (srca & 1) {
		m68k_areg(regs, srcreg) = srca;
		m68k_incpci(2);
		exception3_read_access2(opcode, srca, 1, 1);
		return;
	}
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	m68k_areg(regs, srcreg) = srca;
	do_cycles_ce000_internal(4);
	regs.sr = src;
	MakeFromSR();
	m68k_incpci(2);
	get_word_ce000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, 0);
		return;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 18 (3/0) */
/* 2 0,0   */

/* MV2SR.W (d16,An) */
void REGPARAM2 op_46e8_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 33;
	CurrentInstrCycles = 20; 
	if (!regs.s) {
		Exception(8);
		return;
	}
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	do_cycles_ce000_internal(4);
	regs.sr = src;
	MakeFromSR();
	m68k_incpci(4);
	get_word_ce000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, 0);
		return;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 20 (4/0) */
/* 4 0,0   */

/* MV2SR.W (d8,An,Xn) */
void REGPARAM2 op_46f0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 33;
	CurrentInstrCycles = 22; 
	if (!regs.s) {
		Exception(8);
		return;
	}
	uaecptr srca;
	do_cycles_ce000_internal(2);
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	do_cycles_ce000_internal(4);
	regs.sr = src;
	MakeFromSR();
	m68k_incpci(4);
	get_word_ce000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, 0);
		return;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 22 (4/0) */
/* 4 4,0   */

/* MV2SR.W (xxx).W */
void REGPARAM2 op_46f8_13_ff(uae_u32 opcode)
{
	OpcodeFamily = 33;
	CurrentInstrCycles = 20; 
	if (!regs.s) {
		Exception(8);
		return;
	}
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	if (srca & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	do_cycles_ce000_internal(4);
	regs.sr = src;
	MakeFromSR();
	m68k_incpci(4);
	get_word_ce000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, 0);
		return;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 20 (4/0) */
/* 4 0,0   */

/* MV2SR.W (xxx).L */
void REGPARAM2 op_46f9_13_ff(uae_u32 opcode)
{
	OpcodeFamily = 33;
	CurrentInstrCycles = 24; 
	if (!regs.s) {
		Exception(8);
		return;
	}
	uaecptr srca;
	srca = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	srca |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	if (srca & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	do_cycles_ce000_internal(4);
	regs.sr = src;
	MakeFromSR();
	m68k_incpci(6);
	get_word_ce000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, 0);
		return;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 24 (5/0) */
/* 6 0,0   */

/* MV2SR.W (d16,PC) */
void REGPARAM2 op_46fa_13_ff(uae_u32 opcode)
{
	OpcodeFamily = 33;
	CurrentInstrCycles = 20; 
	if (!regs.s) {
		Exception(8);
		return;
	}
	uaecptr srca;
	srca = m68k_getpci() + 2;
	srca += (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 2);
		return;
	}
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return;
	}
	do_cycles_ce000_internal(4);
	regs.sr = src;
	MakeFromSR();
	m68k_incpci(4);
	get_word_ce000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, 0);
		return;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 20 (4/0) */
/* 4 0,0   */

/* MV2SR.W (d8,PC,Xn) */
void REGPARAM2 op_46fb_13_ff(uae_u32 opcode)
{
	OpcodeFamily = 33;
	CurrentInstrCycles = 22; 
	if (!regs.s) {
		Exception(8);
		return;
	}
	uaecptr srca;
	uaecptr tmppc = m68k_getpci() + 2;
	do_cycles_ce000_internal(2);
	srca = get_disp_ea_000(tmppc, get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 2);
		return;
	}
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return;
	}
	do_cycles_ce000_internal(4);
	regs.sr = src;
	MakeFromSR();
	m68k_incpci(4);
	get_word_ce000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, 0);
		return;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 22 (4/0) */
/* 4 4,0   */

/* MV2SR.W #<data>.W */
void REGPARAM2 op_46fc_13_ff(uae_u32 opcode)
{
	OpcodeFamily = 33;
	CurrentInstrCycles = 16; 
	if (!regs.s) {
		Exception(8);
		return;
	}
	uae_s16 src = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	do_cycles_ce000_internal(4);
	regs.sr = src;
	MakeFromSR();
	m68k_incpci(4);
	get_word_ce000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, 0);
		return;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 16 (3/0) */
/* 4 0,0   */

/* NBCD.B Dn */
void REGPARAM2 op_4800_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 17;
	CurrentInstrCycles = 6;  
	uae_s8 src = m68k_dreg(regs, srcreg);
	uae_u16 newv_lo = - (src & 0xF) - (GET_XFLG() ? 1 : 0);
	uae_u16 newv_hi = - (src & 0xF0);
	uae_u16 newv;
	int cflg, tmp_newv;
	tmp_newv = newv_hi + newv_lo;
	if (newv_lo > 9) newv_lo -= 6;
	newv = newv_hi + newv_lo;
	cflg = (newv & 0x1F0) > 0x90;
	if (cflg) newv -= 0x60;
	SET_CFLG(cflg);
	COPY_CARRY();
	SET_ZFLG(GET_ZFLG() & (((uae_s8)(newv)) == 0));
	SET_NFLG(((uae_s8)(newv)) < 0);
	SET_VFLG((tmp_newv & 0x80) != 0 && (newv & 0x80) == 0);
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	do_cycles_ce000_internal(2);
	m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((newv) & 0xff);
	m68k_incpci(2);
	return;
}
/* 6 (1/0) */
/* 2 0,0   */

/* NBCD.B (An) */
void REGPARAM2 op_4810_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 17;
	CurrentInstrCycles = 12; 
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	uae_u16 newv_lo = - (src & 0xF) - (GET_XFLG() ? 1 : 0);
	uae_u16 newv_hi = - (src & 0xF0);
	uae_u16 newv;
	int cflg, tmp_newv;
	tmp_newv = newv_hi + newv_lo;
	if (newv_lo > 9) newv_lo -= 6;
	newv = newv_hi + newv_lo;
	cflg = (newv & 0x1F0) > 0x90;
	if (cflg) newv -= 0x60;
	SET_CFLG(cflg);
	COPY_CARRY();
	SET_ZFLG(GET_ZFLG() & (((uae_s8)(newv)) == 0));
	SET_NFLG(((uae_s8)(newv)) < 0);
	SET_VFLG((tmp_newv & 0x80) != 0 && (newv & 0x80) == 0);
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_ce000_prefetch(4);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return;
		}
		opcode = regs.ir;
	} else {
		loop_mode = 0;
		loop_mode |= 6;
		loop_mode |= 6 << 16;
	}
	if(loop_mode & 0xfffe) {
		do_cycles_ce000_internal(loop_mode & 0xfffe);
		loop_mode = 1;
	}
	x_put_byte(srca, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, srca + 0, 0x0, newv, 1);
		return;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return;
}
/* 12 (2/1) */
/* 2 0,0   */

/* NBCD.B (An)+ */
void REGPARAM2 op_4818_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 17;
	CurrentInstrCycles = 12; 
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
	uae_u16 newv_lo = - (src & 0xF) - (GET_XFLG() ? 1 : 0);
	uae_u16 newv_hi = - (src & 0xF0);
	uae_u16 newv;
	int cflg, tmp_newv;
	tmp_newv = newv_hi + newv_lo;
	if (newv_lo > 9) newv_lo -= 6;
	newv = newv_hi + newv_lo;
	cflg = (newv & 0x1F0) > 0x90;
	if (cflg) newv -= 0x60;
	SET_CFLG(cflg);
	COPY_CARRY();
	SET_ZFLG(GET_ZFLG() & (((uae_s8)(newv)) == 0));
	SET_NFLG(((uae_s8)(newv)) < 0);
	SET_VFLG((tmp_newv & 0x80) != 0 && (newv & 0x80) == 0);
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_ce000_prefetch(4);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return;
		}
		opcode = regs.ir;
	} else {
		loop_mode = 0;
		loop_mode |= 6;
		loop_mode |= 6 << 16;
	}
	if(loop_mode & 0xfffe) {
		do_cycles_ce000_internal(loop_mode & 0xfffe);
		loop_mode = 1;
	}
	x_put_byte(srca, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, srca + 0, 0x0, newv, 1);
		return;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return;
}
/* 12 (2/1) */
/* 2 0,0   */

/* NBCD.B -(An) */
void REGPARAM2 op_4820_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 17;
	CurrentInstrCycles = 14; 
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
	do_cycles_ce000_internal(2);
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	m68k_areg(regs, srcreg) = srca;
	uae_u16 newv_lo = - (src & 0xF) - (GET_XFLG() ? 1 : 0);
	uae_u16 newv_hi = - (src & 0xF0);
	uae_u16 newv;
	int cflg, tmp_newv;
	tmp_newv = newv_hi + newv_lo;
	if (newv_lo > 9) newv_lo -= 6;
	newv = newv_hi + newv_lo;
	cflg = (newv & 0x1F0) > 0x90;
	if (cflg) newv -= 0x60;
	SET_CFLG(cflg);
	COPY_CARRY();
	SET_ZFLG(GET_ZFLG() & (((uae_s8)(newv)) == 0));
	SET_NFLG(((uae_s8)(newv)) < 0);
	SET_VFLG((tmp_newv & 0x80) != 0 && (newv & 0x80) == 0);
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_ce000_prefetch(4);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return;
		}
		opcode = regs.ir;
	} else {
		loop_mode = 0;
		loop_mode |= 6;
		loop_mode |= 6 << 16;
	}
	if(loop_mode & 0xfffe) {
		do_cycles_ce000_internal(loop_mode & 0xfffe);
		loop_mode = 1;
	}
	x_put_byte(srca, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, srca + 0, 0x0, newv, 1);
		return;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return;
}
/* 14 (2/1) */
/* 2 0,0   */

/* NBCD.B (d16,An) */
void REGPARAM2 op_4828_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 17;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	uae_u16 newv_lo = - (src & 0xF) - (GET_XFLG() ? 1 : 0);
	uae_u16 newv_hi = - (src & 0xF0);
	uae_u16 newv;
	int cflg, tmp_newv;
	tmp_newv = newv_hi + newv_lo;
	if (newv_lo > 9) newv_lo -= 6;
	newv = newv_hi + newv_lo;
	cflg = (newv & 0x1F0) > 0x90;
	if (cflg) newv -= 0x60;
	SET_CFLG(cflg);
	COPY_CARRY();
	SET_ZFLG(GET_ZFLG() & (((uae_s8)(newv)) == 0));
	SET_NFLG(((uae_s8)(newv)) < 0);
	SET_VFLG((tmp_newv & 0x80) != 0 && (newv & 0x80) == 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_byte(srca, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, srca + 0, 0x0, newv, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* NBCD.B (d8,An,Xn) */
void REGPARAM2 op_4830_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 17;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	do_cycles_ce000_internal(2);
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	uae_u16 newv_lo = - (src & 0xF) - (GET_XFLG() ? 1 : 0);
	uae_u16 newv_hi = - (src & 0xF0);
	uae_u16 newv;
	int cflg, tmp_newv;
	tmp_newv = newv_hi + newv_lo;
	if (newv_lo > 9) newv_lo -= 6;
	newv = newv_hi + newv_lo;
	cflg = (newv & 0x1F0) > 0x90;
	if (cflg) newv -= 0x60;
	SET_CFLG(cflg);
	COPY_CARRY();
	SET_ZFLG(GET_ZFLG() & (((uae_s8)(newv)) == 0));
	SET_NFLG(((uae_s8)(newv)) < 0);
	SET_VFLG((tmp_newv & 0x80) != 0 && (newv & 0x80) == 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_byte(srca, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, srca + 0, 0x0, newv, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 18 (3/1) */
/* 4 4,0   */

/* NBCD.B (xxx).W */
void REGPARAM2 op_4838_13_ff(uae_u32 opcode)
{
	OpcodeFamily = 17;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	uae_u16 newv_lo = - (src & 0xF) - (GET_XFLG() ? 1 : 0);
	uae_u16 newv_hi = - (src & 0xF0);
	uae_u16 newv;
	int cflg, tmp_newv;
	tmp_newv = newv_hi + newv_lo;
	if (newv_lo > 9) newv_lo -= 6;
	newv = newv_hi + newv_lo;
	cflg = (newv & 0x1F0) > 0x90;
	if (cflg) newv -= 0x60;
	SET_CFLG(cflg);
	COPY_CARRY();
	SET_ZFLG(GET_ZFLG() & (((uae_s8)(newv)) == 0));
	SET_NFLG(((uae_s8)(newv)) < 0);
	SET_VFLG((tmp_newv & 0x80) != 0 && (newv & 0x80) == 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_byte(srca, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, srca + 0, 0x0, newv, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* NBCD.B (xxx).L */
void REGPARAM2 op_4839_13_ff(uae_u32 opcode)
{
	OpcodeFamily = 17;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	srca = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	srca |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	uae_u16 newv_lo = - (src & 0xF) - (GET_XFLG() ? 1 : 0);
	uae_u16 newv_hi = - (src & 0xF0);
	uae_u16 newv;
	int cflg, tmp_newv;
	tmp_newv = newv_hi + newv_lo;
	if (newv_lo > 9) newv_lo -= 6;
	newv = newv_hi + newv_lo;
	cflg = (newv & 0x1F0) > 0x90;
	if (cflg) newv -= 0x60;
	SET_CFLG(cflg);
	COPY_CARRY();
	SET_ZFLG(GET_ZFLG() & (((uae_s8)(newv)) == 0));
	SET_NFLG(((uae_s8)(newv)) < 0);
	SET_VFLG((tmp_newv & 0x80) != 0 && (newv & 0x80) == 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_byte(srca, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, srca + 0, 0x0, newv, 1);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 20 (4/1) */
/* 6 0,0   */

/* SWAP.W Dn */
void REGPARAM2 op_4840_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 34;
	CurrentInstrCycles = 4;  
	uae_s32 src = m68k_dreg(regs, srcreg);
	uae_u32 dst = ((src >> 16)&0xFFFF) | ((src&0xFFFF)<<16);
	m68k_dreg(regs, srcreg) = (dst);
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(dst)) == 0);
	SET_NFLG(((uae_s32)(dst)) < 0);
	regs.ir = regs.irc;
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 4 (1/0) */
/* 2 0,0   */

/* BKPTQ.L #<data> */
#ifndef CPUEMU_68000_ONLY
void REGPARAM2 op_4848_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 99;
	CurrentInstrCycles = 4;  
	do_cycles_ce000_internal(4);
	op_illg_noret(opcode);
	return;
}
/* 4 (0/0) */
/* 2 0,0   */

#endif
/* PEA.L (An) */
void REGPARAM2 op_4850_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 57;
	CurrentInstrCycles = 12; 
	uae_u16 old_opcode = opcode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, 7) - 4;
	m68k_areg(regs, 7) = dsta;
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		m68k_areg(regs, 7) += 4;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	if (dsta & 1) {
		regs.ir = old_opcode;
		m68k_incpci(2);
		exception3_write_access(old_opcode, dsta, sz_word, srca >> 16, 1);
		return;
	}
	x_put_word(dsta, srca >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x1, srca >> 16, 1);
		return;
	}
	x_put_word(dsta + 2, srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 2, 0x1, srca, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 12 (1/2) */
/* 2 0,0   */

/* PEA.L (d16,An) */
void REGPARAM2 op_4868_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 57;
	CurrentInstrCycles = 16; 
	uae_u16 old_opcode = opcode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, 7) - 4;
	m68k_areg(regs, 7) = dsta;
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		m68k_areg(regs, 7) += 4;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	if (dsta & 1) {
		regs.ir = old_opcode;
		m68k_incpci(2);
		exception3_write_access(old_opcode, dsta, sz_word, srca >> 16, 1);
		return;
	}
	x_put_word(dsta, srca >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, srca >> 16, 1);
		return;
	}
	x_put_word(dsta + 2, srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 2, 0x1, srca, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (2/2) */
/* 4 0,0   */

/* PEA.L (d8,An,Xn) */
void REGPARAM2 op_4870_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 57;
	CurrentInstrCycles = 20; 
	do_cycles_ce000_internal(2);
	ipl_fetch_now();
	uae_u16 old_opcode = opcode;
	uaecptr srca;
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, 7) - 4;
	m68k_areg(regs, 7) = dsta;
	do_cycles_ce000_internal(2);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		m68k_areg(regs, 7) += 4;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	if (dsta & 1) {
		regs.ir = old_opcode;
		m68k_incpci(2);
		exception3_write_access(old_opcode, dsta, sz_word, srca >> 16, 1);
		return;
	}
	x_put_word(dsta, srca >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, srca >> 16, 1);
		return;
	}
	x_put_word(dsta + 2, srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 2, 0x1, srca, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 20 (2/2) */
/* 4 4,0   */

/* PEA.L (xxx).W */
void REGPARAM2 op_4878_13_ff(uae_u32 opcode)
{
	OpcodeFamily = 57;
	CurrentInstrCycles = 16; 
	uae_u16 old_opcode = opcode;
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, 7) - 4;
	m68k_areg(regs, 7) = dsta;
	if (dsta & 1) {
		regs.ir = old_opcode;
		m68k_incpci(2);
		exception3_write_access(old_opcode, dsta, sz_word, srca >> 16, 1);
		return;
	}
	x_put_word(dsta, srca >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, srca >> 16, 1);
		return;
	}
	x_put_word(dsta + 2, srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 2, 0x1, srca, 1);
		return;
	}
	ipl_fetch_next();
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (2/2) */
/* 4 0,0   */

/* PEA.L (xxx).L */
void REGPARAM2 op_4879_13_ff(uae_u32 opcode)
{
	OpcodeFamily = 57;
	CurrentInstrCycles = 20; 
	uae_u16 old_opcode = opcode;
	uaecptr srca;
	srca = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	srca |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, 7) - 4;
	m68k_areg(regs, 7) = dsta;
	if (dsta & 1) {
		regs.ir = old_opcode;
		m68k_incpci(2);
		exception3_write_access(old_opcode, dsta, sz_word, srca >> 16, 1);
		return;
	}
	x_put_word(dsta, srca >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 0, 0x1, srca >> 16, 1);
		return;
	}
	x_put_word(dsta + 2, srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 2, 0x1, srca, 1);
		return;
	}
	ipl_fetch_next();
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 20 (3/2) */
/* 6 0,0   */

/* PEA.L (d16,PC) */
void REGPARAM2 op_487a_13_ff(uae_u32 opcode)
{
	OpcodeFamily = 57;
	CurrentInstrCycles = 16; 
	uae_u16 old_opcode = opcode;
	uaecptr srca;
	srca = m68k_getpci() + 2;
	srca += (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, 7) - 4;
	m68k_areg(regs, 7) = dsta;
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		m68k_areg(regs, 7) += 4;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	if (dsta & 1) {
		regs.ir = old_opcode;
		m68k_incpci(2);
		exception3_write_access(old_opcode, dsta, sz_word, srca >> 16, 1);
		return;
	}
	x_put_word(dsta, srca >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, srca >> 16, 1);
		return;
	}
	x_put_word(dsta + 2, srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 2, 0x1, srca, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (2/2) */
/* 4 0,0   */

/* PEA.L (d8,PC,Xn) */
void REGPARAM2 op_487b_13_ff(uae_u32 opcode)
{
	OpcodeFamily = 57;
	CurrentInstrCycles = 20; 
	do_cycles_ce000_internal(2);
	ipl_fetch_now();
	uae_u16 old_opcode = opcode;
	uaecptr srca;
	uaecptr tmppc = m68k_getpci() + 2;
	srca = get_disp_ea_000(tmppc, get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, 7) - 4;
	m68k_areg(regs, 7) = dsta;
	do_cycles_ce000_internal(2);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		m68k_areg(regs, 7) += 4;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	if (dsta & 1) {
		regs.ir = old_opcode;
		m68k_incpci(2);
		exception3_write_access(old_opcode, dsta, sz_word, srca >> 16, 1);
		return;
	}
	x_put_word(dsta, srca >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, srca >> 16, 1);
		return;
	}
	x_put_word(dsta + 2, srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 2, 0x1, srca, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 20 (2/2) */
/* 4 4,0   */

/* EXT.W Dn */
void REGPARAM2 op_4880_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 36;
	CurrentInstrCycles = 4;  
	uae_s32 src = m68k_dreg(regs, srcreg);
	uae_u16 dst = (uae_s16)(uae_s8)src;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(dst)) == 0);
	SET_NFLG(((uae_s16)(dst)) < 0);
	m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | ((dst) & 0xffff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 4 (1/0) */
/* 2 0,0   */

/* MVMLE.W #<data>.W,(An) */
void REGPARAM2 op_4890_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 38;
	CurrentInstrCycles = 8;  
	uae_u16 mask = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 2);
		return;
	}
	uaecptr srca;
	srca = m68k_areg(regs, dstreg);
	uae_u16 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
	if ((amask || dmask) && (srca & 1)) {
		uaecptr srcav = srca;
		if(dmask) {
			srcav = m68k_dreg(regs, movem_index1[dmask]) >> 0;
		} else if (amask) {
			srcav = m68k_areg(regs, movem_index1[amask]) >> 0;
		}
		regs.read_buffer = mask;
		m68k_incpci(6);
		exception3_write_access(opcode, srca, 1, srcav, 1);
		return;
	}
	while (dmask) {
		x_put_word(srca, m68k_dreg(regs, movem_index1[dmask]));
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(6);
			exception2_write(opcode, srca + 0, 0x1, m68k_dreg(regs, movem_index1[dmask]), 1);
			return;
		}
		srca += 2;
		dmask = movem_next[dmask];
	}
	while (amask) {
		x_put_word(srca, m68k_areg(regs, movem_index1[amask]));
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(6);
			exception2_write(opcode, srca + 0, 0x1, m68k_areg(regs, movem_index1[amask]), 1);
			return;
		}
		srca += 2;
		amask = movem_next[amask];
	}
	ipl_fetch_next();
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 8+ (2/0) */
/* 4 0,0   */

/* MVMLE.W #<data>.W,-(An) */
void REGPARAM2 op_48a0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 38;
	CurrentInstrCycles = 8;  
	uae_u16 mask = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 2);
		return;
	}
	uaecptr srca;
	srca = m68k_areg(regs, dstreg) - 0;
	uae_u16 amask = mask & 0xff, dmask = (mask >> 8) & 0xff;
	if ((amask || dmask) && (srca & 1)) {
		srca -= 2;
		uaecptr srcav = srca;
		if(amask) {
			srcav = m68k_areg(regs, movem_index2[amask]);
		} else if (dmask) {
			srcav = m68k_dreg(regs, movem_index2[dmask]);
		}
		regs.read_buffer = mask;
		m68k_incpci(6);
		exception3_write_access(opcode, srca, 1, srcav, 1);
		return;
	}
	while (amask) {
		srca -= 2;
		x_put_word(srca, m68k_areg(regs, movem_index2[amask]));
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(6);
			exception2_write(opcode, srca + 0, 0x1, m68k_areg(regs, movem_index2[amask]), 1);
			return;
		}
		amask = movem_next[amask];
	}
	while (dmask) {
		srca -= 2;
		x_put_word(srca, m68k_dreg(regs, movem_index2[dmask]));
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(6);
			exception2_write(opcode, srca + 0, 0x1, m68k_dreg(regs, movem_index2[dmask]), 1);
			return;
		}
		dmask = movem_next[dmask];
	}
	m68k_areg(regs, dstreg) = srca;
	ipl_fetch_next();
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 8+ (2/0) */
/* 4 0,0   */

/* MVMLE.W #<data>.W,(d16,An) */
void REGPARAM2 op_48a8_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 38;
	CurrentInstrCycles = 12; 
	uae_u16 mask = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr srca;
	srca = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, 2);
		return;
	}
	uae_u16 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
	if ((amask || dmask) && (srca & 1)) {
		uaecptr srcav = srca;
		if(dmask) {
			srcav = m68k_dreg(regs, movem_index1[dmask]) >> 0;
		} else if (amask) {
			srcav = m68k_areg(regs, movem_index1[amask]) >> 0;
		}
		m68k_incpci(8);
		exception3_write_access(opcode, srca, 1, srcav, 1);
		return;
	}
	while (dmask) {
		x_put_word(srca, m68k_dreg(regs, movem_index1[dmask]));
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(8);
			exception2_write(opcode, srca + 0, 0x1, m68k_dreg(regs, movem_index1[dmask]), 1);
			return;
		}
		srca += 2;
		dmask = movem_next[dmask];
	}
	while (amask) {
		x_put_word(srca, m68k_areg(regs, movem_index1[amask]));
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(8);
			exception2_write(opcode, srca + 0, 0x1, m68k_areg(regs, movem_index1[amask]), 1);
			return;
		}
		srca += 2;
		amask = movem_next[amask];
	}
	ipl_fetch_next();
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 12+ (3/0) */
/* 6 0,0   */

/* MVMLE.W #<data>.W,(d8,An,Xn) */
void REGPARAM2 op_48b0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 38;
	CurrentInstrCycles = 14; 
	uae_u16 mask = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	do_cycles_ce000_internal(2);
	uaecptr srca;
	srca = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_ce000_prefetch(6));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, 2);
		return;
	}
	uae_u16 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
	if ((amask || dmask) && (srca & 1)) {
		uaecptr srcav = srca;
		if(dmask) {
			srcav = m68k_dreg(regs, movem_index1[dmask]) >> 0;
		} else if (amask) {
			srcav = m68k_areg(regs, movem_index1[amask]) >> 0;
		}
		m68k_incpci(8);
		exception3_write_access(opcode, srca, 1, srcav, 1);
		return;
	}
	while (dmask) {
		x_put_word(srca, m68k_dreg(regs, movem_index1[dmask]));
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(8);
			exception2_write(opcode, srca + 0, 0x1, m68k_dreg(regs, movem_index1[dmask]), 1);
			return;
		}
		srca += 2;
		dmask = movem_next[dmask];
	}
	while (amask) {
		x_put_word(srca, m68k_areg(regs, movem_index1[amask]));
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(8);
			exception2_write(opcode, srca + 0, 0x1, m68k_areg(regs, movem_index1[amask]), 1);
			return;
		}
		srca += 2;
		amask = movem_next[amask];
	}
	ipl_fetch_next();
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 14+ (3/0) */
/* 6 4,0   */

/* MVMLE.W #<data>.W,(xxx).W */
void REGPARAM2 op_48b8_13_ff(uae_u32 opcode)
{
	OpcodeFamily = 38;
	CurrentInstrCycles = 12; 
	uae_u16 mask = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, 2);
		return;
	}
	uae_u16 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
	if ((amask || dmask) && (srca & 1)) {
		uaecptr srcav = srca;
		if(dmask) {
			srcav = m68k_dreg(regs, movem_index1[dmask]) >> 0;
		} else if (amask) {
			srcav = m68k_areg(regs, movem_index1[amask]) >> 0;
		}
		m68k_incpci(8);
		exception3_write_access(opcode, srca, 1, srcav, 1);
		return;
	}
	while (dmask) {
		x_put_word(srca, m68k_dreg(regs, movem_index1[dmask]));
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(8);
			exception2_write(opcode, srca + 0, 0x1, m68k_dreg(regs, movem_index1[dmask]), 1);
			return;
		}
		srca += 2;
		dmask = movem_next[dmask];
	}
	while (amask) {
		x_put_word(srca, m68k_areg(regs, movem_index1[amask]));
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(8);
			exception2_write(opcode, srca + 0, 0x1, m68k_areg(regs, movem_index1[amask]), 1);
			return;
		}
		srca += 2;
		amask = movem_next[amask];
	}
	ipl_fetch_next();
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 12+ (3/0) */
/* 6 0,0   */

/* MVMLE.W #<data>.W,(xxx).L */
void REGPARAM2 op_48b9_13_ff(uae_u32 opcode)
{
	OpcodeFamily = 38;
	CurrentInstrCycles = 16; 
	uae_u16 mask = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr srca;
	srca = get_word_ce000_prefetch(6) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return;
	}
	srca |= get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		pcoffset += 2;
		exception2_fetch(opcode, 8, pcoffset);
		return;
	}
	uae_u16 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
	if ((amask || dmask) && (srca & 1)) {
		uaecptr srcav = srca;
		if(dmask) {
			srcav = m68k_dreg(regs, movem_index1[dmask]) >> 0;
		} else if (amask) {
			srcav = m68k_areg(regs, movem_index1[amask]) >> 0;
		}
		m68k_incpci(10);
		exception3_write_access(opcode, srca, 1, srcav, 1);
		return;
	}
	while (dmask) {
		x_put_word(srca, m68k_dreg(regs, movem_index1[dmask]));
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(10);
			exception2_write(opcode, srca + 0, 0x1, m68k_dreg(regs, movem_index1[dmask]), 1);
			return;
		}
		srca += 2;
		dmask = movem_next[dmask];
	}
	while (amask) {
		x_put_word(srca, m68k_areg(regs, movem_index1[amask]));
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(10);
			exception2_write(opcode, srca + 0, 0x1, m68k_areg(regs, movem_index1[amask]), 1);
			return;
		}
		srca += 2;
		amask = movem_next[amask];
	}
	ipl_fetch_next();
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(10);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 10, pcoffset);
		return;
	}
	m68k_incpci(8);
	return;
}
/* 16+ (4/0) */
/* 8 0,0   */

/* EXT.L Dn */
void REGPARAM2 op_48c0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 36;
	CurrentInstrCycles = 4;  
	uae_s32 src = m68k_dreg(regs, srcreg);
	uae_u32 dst = (uae_s32)(uae_s16)src;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(dst)) == 0);
	SET_NFLG(((uae_s32)(dst)) < 0);
	m68k_dreg(regs, srcreg) = (dst);
	regs.ir = regs.irc;
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 4 (1/0) */
/* 2 0,0   */

/* MVMLE.L #<data>.W,(An) */
void REGPARAM2 op_48d0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 38;
	CurrentInstrCycles = 8;  
	uae_u16 mask = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 2);
		return;
	}
	uaecptr srca;
	srca = m68k_areg(regs, dstreg);
	uae_u16 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
	if ((amask || dmask) && (srca & 1)) {
		uaecptr srcav = srca;
		if(dmask) {
			srcav = m68k_dreg(regs, movem_index1[dmask]) >> 16;
		} else if (amask) {
			srcav = m68k_areg(regs, movem_index1[amask]) >> 16;
		}
		regs.read_buffer = mask;
		m68k_incpci(6);
		exception3_write_access(opcode, srca, 2, srcav, 1);
		return;
	}
	while (dmask) {
		x_put_word(srca, m68k_dreg(regs, movem_index1[dmask]) >> 16);
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(6);
			exception2_write(opcode, srca + 0, 0x1, m68k_dreg(regs, movem_index1[dmask]) >> 16, 1);
			return;
		}
		x_put_word(srca + 2, m68k_dreg(regs, movem_index1[dmask]));
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(6);
			exception2_write(opcode, srca + 2, 0x1, m68k_dreg(regs, movem_index1[dmask]), 1);
			return;
		}
		srca += 4;
		dmask = movem_next[dmask];
	}
	while (amask) {
		x_put_word(srca, m68k_areg(regs, movem_index1[amask]) >> 16);
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(6);
			exception2_write(opcode, srca + 0, 0x1, m68k_areg(regs, movem_index1[amask]) >> 16, 1);
			return;
		}
		x_put_word(srca + 2, m68k_areg(regs, movem_index1[amask]));
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(6);
			exception2_write(opcode, srca + 2, 0x1, m68k_areg(regs, movem_index1[amask]), 1);
			return;
		}
		srca += 4;
		amask = movem_next[amask];
	}
	ipl_fetch_next();
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 8+ (2/0) */
/* 4 0,0   */

/* MVMLE.L #<data>.W,-(An) */
void REGPARAM2 op_48e0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 38;
	CurrentInstrCycles = 8;  
	uae_u16 mask = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 2);
		return;
	}
	uaecptr srca;
	srca = m68k_areg(regs, dstreg) - 0;
	uae_u16 amask = mask & 0xff, dmask = (mask >> 8) & 0xff;
	if ((amask || dmask) && (srca & 1)) {
		srca -= 2;
		uaecptr srcav = srca;
		if(amask) {
			srcav = m68k_areg(regs, movem_index2[amask]);
		} else if (dmask) {
			srcav = m68k_dreg(regs, movem_index2[dmask]);
		}
		regs.read_buffer = mask;
		m68k_incpci(6);
		exception3_write_access(opcode, srca, 2, srcav, 1);
		return;
	}
	while (amask) {
		x_put_word(srca - 2, m68k_areg(regs, movem_index2[amask]));
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(6);
			exception2_write(opcode, srca + -2, 0x1, m68k_areg(regs, movem_index2[amask]), 1);
			return;
		}
		x_put_word(srca - 4, m68k_areg(regs, movem_index2[amask]) >> 16);
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(6);
			exception2_write(opcode, srca + -4, 0x1, m68k_areg(regs, movem_index2[amask]) >> 16, 1);
			return;
		}
		srca -= 4;
		amask = movem_next[amask];
	}
	while (dmask) {
		x_put_word(srca - 2, m68k_dreg(regs, movem_index2[dmask]));
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(6);
			exception2_write(opcode, srca + -2, 0x1, m68k_dreg(regs, movem_index2[dmask]), 1);
			return;
		}
		x_put_word(srca - 4, m68k_dreg(regs, movem_index2[dmask]) >> 16);
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(6);
			exception2_write(opcode, srca + -4, 0x1, m68k_dreg(regs, movem_index2[dmask]) >> 16, 1);
			return;
		}
		srca -= 4;
		dmask = movem_next[dmask];
	}
	m68k_areg(regs, dstreg) = srca;
	ipl_fetch_next();
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 8+ (2/0) */
/* 4 0,0   */

/* MVMLE.L #<data>.W,(d16,An) */
void REGPARAM2 op_48e8_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 38;
	CurrentInstrCycles = 12; 
	uae_u16 mask = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr srca;
	srca = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, 2);
		return;
	}
	uae_u16 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
	if ((amask || dmask) && (srca & 1)) {
		uaecptr srcav = srca;
		if(dmask) {
			srcav = m68k_dreg(regs, movem_index1[dmask]) >> 16;
		} else if (amask) {
			srcav = m68k_areg(regs, movem_index1[amask]) >> 16;
		}
		m68k_incpci(8);
		exception3_write_access(opcode, srca, 2, srcav, 1);
		return;
	}
	while (dmask) {
		x_put_word(srca, m68k_dreg(regs, movem_index1[dmask]) >> 16);
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(8);
			exception2_write(opcode, srca + 0, 0x1, m68k_dreg(regs, movem_index1[dmask]) >> 16, 1);
			return;
		}
		x_put_word(srca + 2, m68k_dreg(regs, movem_index1[dmask]));
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(8);
			exception2_write(opcode, srca + 2, 0x1, m68k_dreg(regs, movem_index1[dmask]), 1);
			return;
		}
		srca += 4;
		dmask = movem_next[dmask];
	}
	while (amask) {
		x_put_word(srca, m68k_areg(regs, movem_index1[amask]) >> 16);
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(8);
			exception2_write(opcode, srca + 0, 0x1, m68k_areg(regs, movem_index1[amask]) >> 16, 1);
			return;
		}
		x_put_word(srca + 2, m68k_areg(regs, movem_index1[amask]));
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(8);
			exception2_write(opcode, srca + 2, 0x1, m68k_areg(regs, movem_index1[amask]), 1);
			return;
		}
		srca += 4;
		amask = movem_next[amask];
	}
	ipl_fetch_next();
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 12+ (3/0) */
/* 6 0,0   */

/* MVMLE.L #<data>.W,(d8,An,Xn) */
void REGPARAM2 op_48f0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 38;
	CurrentInstrCycles = 14; 
	uae_u16 mask = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	do_cycles_ce000_internal(2);
	uaecptr srca;
	srca = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_ce000_prefetch(6));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, 2);
		return;
	}
	uae_u16 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
	if ((amask || dmask) && (srca & 1)) {
		uaecptr srcav = srca;
		if(dmask) {
			srcav = m68k_dreg(regs, movem_index1[dmask]) >> 16;
		} else if (amask) {
			srcav = m68k_areg(regs, movem_index1[amask]) >> 16;
		}
		m68k_incpci(8);
		exception3_write_access(opcode, srca, 2, srcav, 1);
		return;
	}
	while (dmask) {
		x_put_word(srca, m68k_dreg(regs, movem_index1[dmask]) >> 16);
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(8);
			exception2_write(opcode, srca + 0, 0x1, m68k_dreg(regs, movem_index1[dmask]) >> 16, 1);
			return;
		}
		x_put_word(srca + 2, m68k_dreg(regs, movem_index1[dmask]));
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(8);
			exception2_write(opcode, srca + 2, 0x1, m68k_dreg(regs, movem_index1[dmask]), 1);
			return;
		}
		srca += 4;
		dmask = movem_next[dmask];
	}
	while (amask) {
		x_put_word(srca, m68k_areg(regs, movem_index1[amask]) >> 16);
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(8);
			exception2_write(opcode, srca + 0, 0x1, m68k_areg(regs, movem_index1[amask]) >> 16, 1);
			return;
		}
		x_put_word(srca + 2, m68k_areg(regs, movem_index1[amask]));
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(8);
			exception2_write(opcode, srca + 2, 0x1, m68k_areg(regs, movem_index1[amask]), 1);
			return;
		}
		srca += 4;
		amask = movem_next[amask];
	}
	ipl_fetch_next();
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 14+ (3/0) */
/* 6 4,0   */

/* MVMLE.L #<data>.W,(xxx).W */
void REGPARAM2 op_48f8_13_ff(uae_u32 opcode)
{
	OpcodeFamily = 38;
	CurrentInstrCycles = 12; 
	uae_u16 mask = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, 2);
		return;
	}
	uae_u16 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
	if ((amask || dmask) && (srca & 1)) {
		uaecptr srcav = srca;
		if(dmask) {
			srcav = m68k_dreg(regs, movem_index1[dmask]) >> 16;
		} else if (amask) {
			srcav = m68k_areg(regs, movem_index1[amask]) >> 16;
		}
		m68k_incpci(8);
		exception3_write_access(opcode, srca, 2, srcav, 1);
		return;
	}
	while (dmask) {
		x_put_word(srca, m68k_dreg(regs, movem_index1[dmask]) >> 16);
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(8);
			exception2_write(opcode, srca + 0, 0x1, m68k_dreg(regs, movem_index1[dmask]) >> 16, 1);
			return;
		}
		x_put_word(srca + 2, m68k_dreg(regs, movem_index1[dmask]));
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(8);
			exception2_write(opcode, srca + 2, 0x1, m68k_dreg(regs, movem_index1[dmask]), 1);
			return;
		}
		srca += 4;
		dmask = movem_next[dmask];
	}
	while (amask) {
		x_put_word(srca, m68k_areg(regs, movem_index1[amask]) >> 16);
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(8);
			exception2_write(opcode, srca + 0, 0x1, m68k_areg(regs, movem_index1[amask]) >> 16, 1);
			return;
		}
		x_put_word(srca + 2, m68k_areg(regs, movem_index1[amask]));
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(8);
			exception2_write(opcode, srca + 2, 0x1, m68k_areg(regs, movem_index1[amask]), 1);
			return;
		}
		srca += 4;
		amask = movem_next[amask];
	}
	ipl_fetch_next();
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 12+ (3/0) */
/* 6 0,0   */

/* MVMLE.L #<data>.W,(xxx).L */
void REGPARAM2 op_48f9_13_ff(uae_u32 opcode)
{
	OpcodeFamily = 38;
	CurrentInstrCycles = 16; 
	uae_u16 mask = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr srca;
	srca = get_word_ce000_prefetch(6) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return;
	}
	srca |= get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		pcoffset += 2;
		exception2_fetch(opcode, 8, pcoffset);
		return;
	}
	uae_u16 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
	if ((amask || dmask) && (srca & 1)) {
		uaecptr srcav = srca;
		if(dmask) {
			srcav = m68k_dreg(regs, movem_index1[dmask]) >> 16;
		} else if (amask) {
			srcav = m68k_areg(regs, movem_index1[amask]) >> 16;
		}
		m68k_incpci(10);
		exception3_write_access(opcode, srca, 2, srcav, 1);
		return;
	}
	while (dmask) {
		x_put_word(srca, m68k_dreg(regs, movem_index1[dmask]) >> 16);
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(10);
			exception2_write(opcode, srca + 0, 0x1, m68k_dreg(regs, movem_index1[dmask]) >> 16, 1);
			return;
		}
		x_put_word(srca + 2, m68k_dreg(regs, movem_index1[dmask]));
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(10);
			exception2_write(opcode, srca + 2, 0x1, m68k_dreg(regs, movem_index1[dmask]), 1);
			return;
		}
		srca += 4;
		dmask = movem_next[dmask];
	}
	while (amask) {
		x_put_word(srca, m68k_areg(regs, movem_index1[amask]) >> 16);
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(10);
			exception2_write(opcode, srca + 0, 0x1, m68k_areg(regs, movem_index1[amask]) >> 16, 1);
			return;
		}
		x_put_word(srca + 2, m68k_areg(regs, movem_index1[amask]));
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(10);
			exception2_write(opcode, srca + 2, 0x1, m68k_areg(regs, movem_index1[amask]), 1);
			return;
		}
		srca += 4;
		amask = movem_next[amask];
	}
	ipl_fetch_next();
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(10);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 10, pcoffset);
		return;
	}
	m68k_incpci(8);
	return;
}
/* 16+ (4/0) */
/* 8 0,0   */

/* TST.B Dn */
void REGPARAM2 op_4a00_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 20;
	CurrentInstrCycles = 4;  
	uae_s8 src = m68k_dreg(regs, srcreg);
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	regs.ir = regs.irc;
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 4 (1/0) */
/* 2 0,0   */

/* TST.B (An) */
void REGPARAM2 op_4a10_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 20;
	CurrentInstrCycles = 8;  
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	if(!loop_mode) {
		regs.ir = regs.irc;
		opcode = regs.ir;
		get_word_ce000_prefetch(4);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return;
		}
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return;
}
/* 8 (2/0) */
/* 2 0,0   */

/* TST.B (An)+ */
void REGPARAM2 op_4a18_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 20;
	CurrentInstrCycles = 8;  
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	if(!loop_mode) {
		regs.ir = regs.irc;
		opcode = regs.ir;
		get_word_ce000_prefetch(4);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return;
		}
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return;
}
/* 8 (2/0) */
/* 2 0,0   */

/* TST.B -(An) */
void REGPARAM2 op_4a20_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 20;
	CurrentInstrCycles = 10; 
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
	do_cycles_ce000_internal(2);
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	m68k_areg(regs, srcreg) = srca;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	if(!loop_mode) {
		regs.ir = regs.irc;
		opcode = regs.ir;
		get_word_ce000_prefetch(4);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return;
		}
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return;
}
/* 10 (2/0) */
/* 2 0,0   */

/* TST.B (d16,An) */
void REGPARAM2 op_4a28_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 20;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 12 (3/0) */
/* 4 0,0   */

/* TST.B (d8,An,Xn) */
void REGPARAM2 op_4a30_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 20;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	do_cycles_ce000_internal(2);
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 14 (3/0) */
/* 4 4,0   */

/* TST.B (xxx).W */
void REGPARAM2 op_4a38_13_ff(uae_u32 opcode)
{
	OpcodeFamily = 20;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 12 (3/0) */
/* 4 0,0   */

/* TST.B (xxx).L */
void REGPARAM2 op_4a39_13_ff(uae_u32 opcode)
{
	OpcodeFamily = 20;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	srca |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 16 (4/0) */
/* 6 0,0   */

/* TST.W Dn */
void REGPARAM2 op_4a40_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 20;
	CurrentInstrCycles = 4;  
	uae_s16 src = m68k_dreg(regs, srcreg);
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	regs.ir = regs.irc;
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 4 (1/0) */
/* 2 0,0   */

/* TST.W (An) */
void REGPARAM2 op_4a50_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 20;
	CurrentInstrCycles = 8;  
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access2(opcode, srca, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if(!loop_mode) {
		regs.ir = regs.irc;
		opcode = regs.ir;
		get_word_ce000_prefetch(4);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return;
		}
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return;
}
/* 8 (2/0) */
/* 2 0,0   */

/* TST.W (An)+ */
void REGPARAM2 op_4a58_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 20;
	CurrentInstrCycles = 8;  
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_areg(regs, srcreg) += 2 + 0;
		m68k_incpci(2);
		exception3_read_access2(opcode, srca, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) += 2 + 0;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	m68k_areg(regs, srcreg) += 2;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if(!loop_mode) {
		regs.ir = regs.irc;
		opcode = regs.ir;
		get_word_ce000_prefetch(4);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return;
		}
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return;
}
/* 8 (2/0) */
/* 2 0,0   */

/* TST.W -(An) */
void REGPARAM2 op_4a60_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 20;
	CurrentInstrCycles = 10; 
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - 2;
	do_cycles_ce000_internal(2);
	if (srca & 1) {
		m68k_areg(regs, srcreg) = srca;
		m68k_incpci(2);
		exception3_read_access2(opcode, srca, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	m68k_areg(regs, srcreg) = srca;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if(!loop_mode) {
		regs.ir = regs.irc;
		opcode = regs.ir;
		get_word_ce000_prefetch(4);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return;
		}
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return;
}
/* 10 (2/0) */
/* 2 0,0   */

/* TST.W (d16,An) */
void REGPARAM2 op_4a68_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 20;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 12 (3/0) */
/* 4 0,0   */

/* TST.W (d8,An,Xn) */
void REGPARAM2 op_4a70_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 20;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	do_cycles_ce000_internal(2);
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 14 (3/0) */
/* 4 4,0   */

/* TST.W (xxx).W */
void REGPARAM2 op_4a78_13_ff(uae_u32 opcode)
{
	OpcodeFamily = 20;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	if (srca & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 12 (3/0) */
/* 4 0,0   */

/* TST.W (xxx).L */
void REGPARAM2 op_4a79_13_ff(uae_u32 opcode)
{
	OpcodeFamily = 20;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	srca |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	if (srca & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 16 (4/0) */
/* 6 0,0   */

/* TST.L Dn */
void REGPARAM2 op_4a80_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 20;
	CurrentInstrCycles = 4;  
	uae_s32 src = m68k_dreg(regs, srcreg);
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	regs.ir = regs.irc;
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 4 (1/0) */
/* 2 0,0   */

/* TST.L (An) */
void REGPARAM2 op_4a90_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 20;
	CurrentInstrCycles = 12; 
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	if(!loop_mode) {
		regs.ir = regs.irc;
		opcode = regs.ir;
		get_word_ce000_prefetch(4);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return;
		}
	} else {
		loop_mode = 0;
		loop_mode |= 6;
		loop_mode |= 4 << 16;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return;
}
/* 12 (3/0) */
/* 2 0,0   */

/* TST.L (An)+ */
void REGPARAM2 op_4a98_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 20;
	CurrentInstrCycles = 12; 
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	m68k_areg(regs, srcreg) += 4;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	if(!loop_mode) {
		regs.ir = regs.irc;
		opcode = regs.ir;
		get_word_ce000_prefetch(4);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return;
		}
	} else {
		loop_mode = 0;
		loop_mode |= 6;
		loop_mode |= 4 << 16;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return;
}
/* 12 (3/0) */
/* 2 0,0   */

/* TST.L -(An) */
void REGPARAM2 op_4aa0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 20;
	CurrentInstrCycles = 14; 
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - 4;
	do_cycles_ce000_internal(2);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	m68k_areg(regs, srcreg) = srca;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	if(!loop_mode) {
		regs.ir = regs.irc;
		opcode = regs.ir;
		get_word_ce000_prefetch(4);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return;
		}
	} else {
		loop_mode = 0;
		loop_mode |= 6;
		loop_mode |= 4 << 16;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return;
}
/* 14 (3/0) */
/* 2 0,0   */

/* TST.L (d16,An) */
void REGPARAM2 op_4aa8_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 20;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (4/0) */
/* 4 0,0   */

/* TST.L (d8,An,Xn) */
void REGPARAM2 op_4ab0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 20;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	do_cycles_ce000_internal(2);
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 18 (4/0) */
/* 4 4,0   */

/* TST.L (xxx).W */
void REGPARAM2 op_4ab8_13_ff(uae_u32 opcode)
{
	OpcodeFamily = 20;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	if (srca & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (4/0) */
/* 4 0,0   */

/* TST.L (xxx).L */
void REGPARAM2 op_4ab9_13_ff(uae_u32 opcode)
{
	OpcodeFamily = 20;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	srca = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	srca |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	if (srca & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 20 (5/0) */
/* 6 0,0   */

/* TAS.B Dn */
void REGPARAM2 op_4ac0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 98;
	CurrentInstrCycles = 4;  
	uae_s8 src = m68k_dreg(regs, srcreg);
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	src |= 0x80;
	m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((src) & 0xff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 4 (1/0) */
/* 2 0,0   */

/* TAS.B (An) */
void REGPARAM2 op_4ad0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 98;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	do_cycles_ce000_internal(2);
	uae_u8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		regs.read_buffer = regs.irc & 0xff00;
		regs.read_buffer |= 0x80;
		opcode |= 0x80000;
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	do_cycles_ce000_internal(2);
	src |= 0x80;
	if (!is_cycle_ce(srca)) {
		ipl_fetch_now();
		x_put_byte(srca, src);
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(4);
			opcode |= 0x80000;
			exception2_write(opcode, srca + 0, 0x0, src, 1);
			return;
		}
	} else {
		do_cycles_ce000_internal(4);
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 12 (1/1) */
/* 2 0,0   */

/* TAS.B (An)+ */
void REGPARAM2 op_4ad8_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 98;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	do_cycles_ce000_internal(4);
	m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
	uae_u8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		regs.read_buffer = regs.irc & 0xff00;
		regs.read_buffer |= 0x80;
		opcode |= 0x80000;
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	do_cycles_ce000_internal(2);
	src |= 0x80;
	if (!is_cycle_ce(srca)) {
		ipl_fetch_now();
		x_put_byte(srca, src);
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(4);
			opcode |= 0x80000;
			exception2_write(opcode, srca + 0, 0x0, src, 1);
			return;
		}
	} else {
		do_cycles_ce000_internal(4);
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 14 (1/1) */
/* 2 0,0   */

/* TAS.B -(An) */
void REGPARAM2 op_4ae0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 98;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
	do_cycles_ce000_internal(4);
	m68k_areg(regs, srcreg) = srca;
	uae_u8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		regs.read_buffer = regs.irc & 0xff00;
		regs.read_buffer |= 0x80;
		opcode |= 0x80000;
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	do_cycles_ce000_internal(2);
	src |= 0x80;
	if (!is_cycle_ce(srca)) {
		ipl_fetch_now();
		x_put_byte(srca, src);
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(4);
			opcode |= 0x80000;
			exception2_write(opcode, srca + 0, 0x0, src, 1);
			return;
		}
	} else {
		do_cycles_ce000_internal(4);
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 14 (1/1) */
/* 2 0,0   */

/* TAS.B (d16,An) */
void REGPARAM2 op_4ae8_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 98;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	uae_u8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		regs.read_buffer = regs.irc & 0xff00;
		regs.read_buffer |= 0x80;
		m68k_incpci(2);
		opcode |= 0x80000;
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	do_cycles_ce000_internal(2);
	src |= 0x80;
	if (!is_cycle_ce(srca)) {
		ipl_fetch_now();
		x_put_byte(srca, src);
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(6);
			opcode |= 0x80000;
			exception2_write(opcode, srca + 0, 0x0, src, 1);
			return;
		}
	} else {
		do_cycles_ce000_internal(4);
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 14 (2/1) */
/* 4 0,0   */

/* TAS.B (d8,An,Xn) */
void REGPARAM2 op_4af0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 98;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_ce000_prefetch(4));
	do_cycles_ce000_internal(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	uae_u8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		regs.read_buffer = regs.irc & 0xff00;
		regs.read_buffer |= 0x80;
		m68k_incpci(2);
		opcode |= 0x80000;
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	do_cycles_ce000_internal(2);
	src |= 0x80;
	if (!is_cycle_ce(srca)) {
		ipl_fetch_now();
		x_put_byte(srca, src);
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(6);
			opcode |= 0x80000;
			exception2_write(opcode, srca + 0, 0x0, src, 1);
			return;
		}
	} else {
		do_cycles_ce000_internal(4);
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 18 (2/1) */
/* 4 4,0   */

/* TAS.B (xxx).W */
void REGPARAM2 op_4af8_13_ff(uae_u32 opcode)
{
	OpcodeFamily = 98;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uae_u8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		regs.read_buffer = regs.irc & 0xff00;
		regs.read_buffer |= 0x80;
		m68k_incpci(2);
		opcode |= 0x80000;
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	do_cycles_ce000_internal(2);
	src |= 0x80;
	if (!is_cycle_ce(srca)) {
		ipl_fetch_now();
		x_put_byte(srca, src);
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(6);
			opcode |= 0x80000;
			exception2_write(opcode, srca + 0, 0x0, src, 1);
			return;
		}
	} else {
		do_cycles_ce000_internal(4);
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 14 (2/1) */
/* 4 0,0   */

/* TAS.B (xxx).L */
void REGPARAM2 op_4af9_13_ff(uae_u32 opcode)
{
	OpcodeFamily = 98;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	srca = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	srca |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	uae_u8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		regs.read_buffer = regs.irc & 0xff00;
		regs.read_buffer |= 0x80;
		m68k_incpci(2);
		opcode |= 0x80000;
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	do_cycles_ce000_internal(2);
	src |= 0x80;
	if (!is_cycle_ce(srca)) {
		ipl_fetch_now();
		x_put_byte(srca, src);
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(8);
			opcode |= 0x80000;
			exception2_write(opcode, srca + 0, 0x0, src, 1);
			return;
		}
	} else {
		do_cycles_ce000_internal(4);
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 18 (3/1) */
/* 6 0,0   */

/* MVMEL.W #<data>.W,(An) */
void REGPARAM2 op_4c90_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 37;
	CurrentInstrCycles = 12; 
	uae_u16 mask = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
	uaecptr srca;
	srca = m68k_areg(regs, dstreg);
	if (srca & 1) {
		uaecptr srcav = srca;
		m68k_incpci(6);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	while (dmask) {
		uae_u32 v = (uae_s32)(uae_s16)x_get_word(srca);
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(6);
			exception2_read(opcode, srca + 0, 0x1, 1);
			return;
		}
		m68k_dreg(regs, movem_index1[dmask]) = v;
		srca += 2;
		dmask = movem_next[dmask];
	}
	while (amask) {
		uae_u32 v = (uae_s32)(uae_s16)x_get_word(srca);
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(6);
			exception2_read(opcode, srca + 0, 0x1, 1);
			return;
		}
		m68k_areg(regs, movem_index1[amask]) = v;
		srca += 2;
		amask = movem_next[amask];
	}
	x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	ipl_fetch_next();
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 12+ (3/0) */
/* 4 0,0   */

/* MVMEL.W #<data>.W,(An)+ */
void REGPARAM2 op_4c98_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 37;
	CurrentInstrCycles = 12; 
	ipl_fetch_now();
	uae_u16 mask = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
	uaecptr srca;
	srca = m68k_areg(regs, dstreg);
	if (srca & 1) {
		uaecptr srcav = srca;
		m68k_incpci(6);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	while (dmask) {
		uae_u32 v = (uae_s32)(uae_s16)x_get_word(srca);
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(6);
			exception2_read(opcode, srca + 0, 0x1, 1);
			return;
		}
		m68k_dreg(regs, movem_index1[dmask]) = v;
		srca += 2;
		dmask = movem_next[dmask];
	}
	while (amask) {
		uae_u32 v = (uae_s32)(uae_s16)x_get_word(srca);
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(6);
			exception2_read(opcode, srca + 0, 0x1, 1);
			return;
		}
		m68k_areg(regs, movem_index1[amask]) = v;
		srca += 2;
		amask = movem_next[amask];
	}
	x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	m68k_areg(regs, dstreg) = srca;
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 12+ (3/0) */
/* 4 0,0   */

/* MVMEL.W #<data>.W,(d16,An) */
void REGPARAM2 op_4ca8_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 37;
	CurrentInstrCycles = 16; 
	uae_u16 mask = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
	uaecptr srca;
	srca = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return;
	}
	if (srca & 1) {
		uaecptr srcav = srca;
		m68k_incpci(8);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	while (dmask) {
		uae_u32 v = (uae_s32)(uae_s16)x_get_word(srca);
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(8);
			exception2_read(opcode, srca + 0, 0x1, 1);
			return;
		}
		m68k_dreg(regs, movem_index1[dmask]) = v;
		srca += 2;
		dmask = movem_next[dmask];
	}
	while (amask) {
		uae_u32 v = (uae_s32)(uae_s16)x_get_word(srca);
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(8);
			exception2_read(opcode, srca + 0, 0x1, 1);
			return;
		}
		m68k_areg(regs, movem_index1[amask]) = v;
		srca += 2;
		amask = movem_next[amask];
	}
	x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	ipl_fetch_next();
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 16+ (4/0) */
/* 6 0,0   */

/* MVMEL.W #<data>.W,(d8,An,Xn) */
void REGPARAM2 op_4cb0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 37;
	CurrentInstrCycles = 18; 
	uae_u16 mask = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
	do_cycles_ce000_internal(2);
	uaecptr srca;
	srca = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_ce000_prefetch(6));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return;
	}
	if (srca & 1) {
		uaecptr srcav = srca;
		m68k_incpci(8);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	while (dmask) {
		uae_u32 v = (uae_s32)(uae_s16)x_get_word(srca);
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(8);
			exception2_read(opcode, srca + 0, 0x1, 1);
			return;
		}
		m68k_dreg(regs, movem_index1[dmask]) = v;
		srca += 2;
		dmask = movem_next[dmask];
	}
	while (amask) {
		uae_u32 v = (uae_s32)(uae_s16)x_get_word(srca);
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(8);
			exception2_read(opcode, srca + 0, 0x1, 1);
			return;
		}
		m68k_areg(regs, movem_index1[amask]) = v;
		srca += 2;
		amask = movem_next[amask];
	}
	x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	ipl_fetch_next();
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 18+ (4/0) */
/* 6 4,0   */

/* MVMEL.W #<data>.W,(xxx).W */
void REGPARAM2 op_4cb8_13_ff(uae_u32 opcode)
{
	OpcodeFamily = 37;
	CurrentInstrCycles = 16; 
	uae_u16 mask = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return;
	}
	if (srca & 1) {
		uaecptr srcav = srca;
		m68k_incpci(8);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	while (dmask) {
		uae_u32 v = (uae_s32)(uae_s16)x_get_word(srca);
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(8);
			exception2_read(opcode, srca + 0, 0x1, 1);
			return;
		}
		m68k_dreg(regs, movem_index1[dmask]) = v;
		srca += 2;
		dmask = movem_next[dmask];
	}
	while (amask) {
		uae_u32 v = (uae_s32)(uae_s16)x_get_word(srca);
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(8);
			exception2_read(opcode, srca + 0, 0x1, 1);
			return;
		}
		m68k_areg(regs, movem_index1[amask]) = v;
		srca += 2;
		amask = movem_next[amask];
	}
	x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	ipl_fetch_next();
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 16+ (4/0) */
/* 6 0,0   */

/* MVMEL.W #<data>.W,(xxx).L */
void REGPARAM2 op_4cb9_13_ff(uae_u32 opcode)
{
	OpcodeFamily = 37;
	CurrentInstrCycles = 20; 
	uae_u16 mask = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
	uaecptr srca;
	srca = get_word_ce000_prefetch(6) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return;
	}
	srca |= get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 8, pcoffset);
		return;
	}
	if (srca & 1) {
		uaecptr srcav = srca;
		m68k_incpci(10);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	while (dmask) {
		uae_u32 v = (uae_s32)(uae_s16)x_get_word(srca);
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(10);
			exception2_read(opcode, srca + 0, 0x1, 1);
			return;
		}
		m68k_dreg(regs, movem_index1[dmask]) = v;
		srca += 2;
		dmask = movem_next[dmask];
	}
	while (amask) {
		uae_u32 v = (uae_s32)(uae_s16)x_get_word(srca);
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(10);
			exception2_read(opcode, srca + 0, 0x1, 1);
			return;
		}
		m68k_areg(regs, movem_index1[amask]) = v;
		srca += 2;
		amask = movem_next[amask];
	}
	x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(10);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	ipl_fetch_next();
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(10);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 10, pcoffset);
		return;
	}
	m68k_incpci(8);
	return;
}
/* 20+ (5/0) */
/* 8 0,0   */

/* MVMEL.W #<data>.W,(d16,PC) */
void REGPARAM2 op_4cba_13_ff(uae_u32 opcode)
{
	uae_u32 dstreg = 2;
	OpcodeFamily = 37;
	CurrentInstrCycles = 16; 
	uae_u16 mask = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
	uaecptr srca;
	srca = m68k_getpci() + 4;
	srca += (uae_s32)(uae_s16)get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return;
	}
	if (srca & 1) {
		uaecptr srcav = srca;
		m68k_incpci(8);
		exception3_read_access(opcode, srca, 1, 2);
		return;
	}
	while (dmask) {
		uae_u32 v = (uae_s32)(uae_s16)x_get_word(srca);
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(8);
			exception2_read(opcode, srca + 0, 0x1, 2);
			return;
		}
		m68k_dreg(regs, movem_index1[dmask]) = v;
		srca += 2;
		dmask = movem_next[dmask];
	}
	while (amask) {
		uae_u32 v = (uae_s32)(uae_s16)x_get_word(srca);
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(8);
			exception2_read(opcode, srca + 0, 0x1, 2);
			return;
		}
		m68k_areg(regs, movem_index1[amask]) = v;
		srca += 2;
		amask = movem_next[amask];
	}
	x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return;
	}
	ipl_fetch_next();
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 16+ (4/0) */
/* 6 0,0   */

/* MVMEL.W #<data>.W,(d8,PC,Xn) */
void REGPARAM2 op_4cbb_13_ff(uae_u32 opcode)
{
	uae_u32 dstreg = 3;
	OpcodeFamily = 37;
	CurrentInstrCycles = 18; 
	uae_u16 mask = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
	do_cycles_ce000_internal(2);
	uaecptr srca;
	uaecptr tmppc = m68k_getpci() + 4;
	srca = get_disp_ea_000(tmppc, get_word_ce000_prefetch(6));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return;
	}
	if (srca & 1) {
		uaecptr srcav = srca;
		m68k_incpci(8);
		exception3_read_access(opcode, srca, 1, 2);
		return;
	}
	while (dmask) {
		uae_u32 v = (uae_s32)(uae_s16)x_get_word(srca);
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(8);
			exception2_read(opcode, srca + 0, 0x1, 2);
			return;
		}
		m68k_dreg(regs, movem_index1[dmask]) = v;
		srca += 2;
		dmask = movem_next[dmask];
	}
	while (amask) {
		uae_u32 v = (uae_s32)(uae_s16)x_get_word(srca);
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(8);
			exception2_read(opcode, srca + 0, 0x1, 2);
			return;
		}
		m68k_areg(regs, movem_index1[amask]) = v;
		srca += 2;
		amask = movem_next[amask];
	}
	x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return;
	}
	ipl_fetch_next();
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 18+ (4/0) */
/* 6 4,0   */

/* MVMEL.L #<data>.W,(An) */
void REGPARAM2 op_4cd0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 37;
	CurrentInstrCycles = 12; 
	uae_u16 mask = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
	uaecptr srca;
	srca = m68k_areg(regs, dstreg);
	if (srca & 1) {
		uaecptr srcav = srca;
		m68k_incpci(6);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	while (dmask) {
		uae_u32 v = (x_get_word(srca) << 16) | (m68k_dreg(regs, movem_index1[dmask]) & 0xffff);
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(6);
			exception2_read(opcode, srca + 0, 0x1, 1);
			return;
		}
		v &= 0xffff0000;
		v |= x_get_word(srca + 2); 
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(6);
			exception2_read(opcode, srca + 2, 0x1, 1);
			return;
		}
		m68k_dreg(regs, movem_index1[dmask]) = v;
		srca += 4;
		dmask = movem_next[dmask];
	}
	while (amask) {
		uae_u32 v = (x_get_word(srca) << 16) | (m68k_areg(regs, movem_index1[amask]) & 0xffff);
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(6);
			exception2_read(opcode, srca + 0, 0x1, 1);
			return;
		}
		v &= 0xffff0000;
		v |= x_get_word(srca + 2);
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(6);
			exception2_read(opcode, srca + 2, 0x1, 1);
			return;
		}
		m68k_areg(regs, movem_index1[amask]) = v;
		srca += 4;
		amask = movem_next[amask];
	}
	x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	ipl_fetch_next();
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 12+ (3/0) */
/* 4 0,0   */

/* MVMEL.L #<data>.W,(An)+ */
void REGPARAM2 op_4cd8_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 37;
	CurrentInstrCycles = 12; 
	ipl_fetch_now();
	uae_u16 mask = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
	uaecptr srca;
	srca = m68k_areg(regs, dstreg);
	if (srca & 1) {
		uaecptr srcav = srca;
		m68k_incpci(6);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	while (dmask) {
		uae_u32 v = (x_get_word(srca) << 16) | (m68k_dreg(regs, movem_index1[dmask]) & 0xffff);
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(6);
			exception2_read(opcode, srca + 0, 0x1, 1);
			return;
		}
		v &= 0xffff0000;
		v |= x_get_word(srca + 2); 
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(6);
			exception2_read(opcode, srca + 2, 0x1, 1);
			return;
		}
		m68k_dreg(regs, movem_index1[dmask]) = v;
		srca += 4;
		dmask = movem_next[dmask];
	}
	while (amask) {
		uae_u32 v = (x_get_word(srca) << 16) | (m68k_areg(regs, movem_index1[amask]) & 0xffff);
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(6);
			exception2_read(opcode, srca + 0, 0x1, 1);
			return;
		}
		v &= 0xffff0000;
		v |= x_get_word(srca + 2);
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(6);
			exception2_read(opcode, srca + 2, 0x1, 1);
			return;
		}
		m68k_areg(regs, movem_index1[amask]) = v;
		srca += 4;
		amask = movem_next[amask];
	}
	x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	m68k_areg(regs, dstreg) = srca;
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 12+ (3/0) */
/* 4 0,0   */

/* MVMEL.L #<data>.W,(d16,An) */
void REGPARAM2 op_4ce8_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 37;
	CurrentInstrCycles = 16; 
	uae_u16 mask = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
	uaecptr srca;
	srca = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return;
	}
	if (srca & 1) {
		uaecptr srcav = srca;
		m68k_incpci(8);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	while (dmask) {
		uae_u32 v = (x_get_word(srca) << 16) | (m68k_dreg(regs, movem_index1[dmask]) & 0xffff);
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(8);
			exception2_read(opcode, srca + 0, 0x1, 1);
			return;
		}
		v &= 0xffff0000;
		v |= x_get_word(srca + 2); 
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(8);
			exception2_read(opcode, srca + 2, 0x1, 1);
			return;
		}
		m68k_dreg(regs, movem_index1[dmask]) = v;
		srca += 4;
		dmask = movem_next[dmask];
	}
	while (amask) {
		uae_u32 v = (x_get_word(srca) << 16) | (m68k_areg(regs, movem_index1[amask]) & 0xffff);
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(8);
			exception2_read(opcode, srca + 0, 0x1, 1);
			return;
		}
		v &= 0xffff0000;
		v |= x_get_word(srca + 2);
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(8);
			exception2_read(opcode, srca + 2, 0x1, 1);
			return;
		}
		m68k_areg(regs, movem_index1[amask]) = v;
		srca += 4;
		amask = movem_next[amask];
	}
	x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	ipl_fetch_next();
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 16+ (4/0) */
/* 6 0,0   */

/* MVMEL.L #<data>.W,(d8,An,Xn) */
void REGPARAM2 op_4cf0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 37;
	CurrentInstrCycles = 18; 
	uae_u16 mask = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
	do_cycles_ce000_internal(2);
	uaecptr srca;
	srca = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_ce000_prefetch(6));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return;
	}
	if (srca & 1) {
		uaecptr srcav = srca;
		m68k_incpci(8);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	while (dmask) {
		uae_u32 v = (x_get_word(srca) << 16) | (m68k_dreg(regs, movem_index1[dmask]) & 0xffff);
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(8);
			exception2_read(opcode, srca + 0, 0x1, 1);
			return;
		}
		v &= 0xffff0000;
		v |= x_get_word(srca + 2); 
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(8);
			exception2_read(opcode, srca + 2, 0x1, 1);
			return;
		}
		m68k_dreg(regs, movem_index1[dmask]) = v;
		srca += 4;
		dmask = movem_next[dmask];
	}
	while (amask) {
		uae_u32 v = (x_get_word(srca) << 16) | (m68k_areg(regs, movem_index1[amask]) & 0xffff);
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(8);
			exception2_read(opcode, srca + 0, 0x1, 1);
			return;
		}
		v &= 0xffff0000;
		v |= x_get_word(srca + 2);
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(8);
			exception2_read(opcode, srca + 2, 0x1, 1);
			return;
		}
		m68k_areg(regs, movem_index1[amask]) = v;
		srca += 4;
		amask = movem_next[amask];
	}
	x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	ipl_fetch_next();
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 18+ (4/0) */
/* 6 4,0   */

/* MVMEL.L #<data>.W,(xxx).W */
void REGPARAM2 op_4cf8_13_ff(uae_u32 opcode)
{
	OpcodeFamily = 37;
	CurrentInstrCycles = 16; 
	uae_u16 mask = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return;
	}
	if (srca & 1) {
		uaecptr srcav = srca;
		m68k_incpci(8);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	while (dmask) {
		uae_u32 v = (x_get_word(srca) << 16) | (m68k_dreg(regs, movem_index1[dmask]) & 0xffff);
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(8);
			exception2_read(opcode, srca + 0, 0x1, 1);
			return;
		}
		v &= 0xffff0000;
		v |= x_get_word(srca + 2); 
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(8);
			exception2_read(opcode, srca + 2, 0x1, 1);
			return;
		}
		m68k_dreg(regs, movem_index1[dmask]) = v;
		srca += 4;
		dmask = movem_next[dmask];
	}
	while (amask) {
		uae_u32 v = (x_get_word(srca) << 16) | (m68k_areg(regs, movem_index1[amask]) & 0xffff);
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(8);
			exception2_read(opcode, srca + 0, 0x1, 1);
			return;
		}
		v &= 0xffff0000;
		v |= x_get_word(srca + 2);
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(8);
			exception2_read(opcode, srca + 2, 0x1, 1);
			return;
		}
		m68k_areg(regs, movem_index1[amask]) = v;
		srca += 4;
		amask = movem_next[amask];
	}
	x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	ipl_fetch_next();
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 16+ (4/0) */
/* 6 0,0   */

/* MVMEL.L #<data>.W,(xxx).L */
void REGPARAM2 op_4cf9_13_ff(uae_u32 opcode)
{
	OpcodeFamily = 37;
	CurrentInstrCycles = 20; 
	uae_u16 mask = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
	uaecptr srca;
	srca = get_word_ce000_prefetch(6) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return;
	}
	srca |= get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 8, pcoffset);
		return;
	}
	if (srca & 1) {
		uaecptr srcav = srca;
		m68k_incpci(10);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	while (dmask) {
		uae_u32 v = (x_get_word(srca) << 16) | (m68k_dreg(regs, movem_index1[dmask]) & 0xffff);
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(10);
			exception2_read(opcode, srca + 0, 0x1, 1);
			return;
		}
		v &= 0xffff0000;
		v |= x_get_word(srca + 2); 
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(10);
			exception2_read(opcode, srca + 2, 0x1, 1);
			return;
		}
		m68k_dreg(regs, movem_index1[dmask]) = v;
		srca += 4;
		dmask = movem_next[dmask];
	}
	while (amask) {
		uae_u32 v = (x_get_word(srca) << 16) | (m68k_areg(regs, movem_index1[amask]) & 0xffff);
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(10);
			exception2_read(opcode, srca + 0, 0x1, 1);
			return;
		}
		v &= 0xffff0000;
		v |= x_get_word(srca + 2);
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(10);
			exception2_read(opcode, srca + 2, 0x1, 1);
			return;
		}
		m68k_areg(regs, movem_index1[amask]) = v;
		srca += 4;
		amask = movem_next[amask];
	}
	x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(10);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	ipl_fetch_next();
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(10);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 10, pcoffset);
		return;
	}
	m68k_incpci(8);
	return;
}
/* 20+ (5/0) */
/* 8 0,0   */

/* MVMEL.L #<data>.W,(d16,PC) */
void REGPARAM2 op_4cfa_13_ff(uae_u32 opcode)
{
	uae_u32 dstreg = 2;
	OpcodeFamily = 37;
	CurrentInstrCycles = 16; 
	uae_u16 mask = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
	uaecptr srca;
	srca = m68k_getpci() + 4;
	srca += (uae_s32)(uae_s16)get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return;
	}
	if (srca & 1) {
		uaecptr srcav = srca;
		m68k_incpci(8);
		exception3_read_access(opcode, srca, 2, 2);
		return;
	}
	while (dmask) {
		uae_u32 v = (x_get_word(srca) << 16) | (m68k_dreg(regs, movem_index1[dmask]) & 0xffff);
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(8);
			exception2_read(opcode, srca + 0, 0x1, 2);
			return;
		}
		v &= 0xffff0000;
		v |= x_get_word(srca + 2); 
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(8);
			exception2_read(opcode, srca + 2, 0x1, 2);
			return;
		}
		m68k_dreg(regs, movem_index1[dmask]) = v;
		srca += 4;
		dmask = movem_next[dmask];
	}
	while (amask) {
		uae_u32 v = (x_get_word(srca) << 16) | (m68k_areg(regs, movem_index1[amask]) & 0xffff);
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(8);
			exception2_read(opcode, srca + 0, 0x1, 2);
			return;
		}
		v &= 0xffff0000;
		v |= x_get_word(srca + 2);
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(8);
			exception2_read(opcode, srca + 2, 0x1, 2);
			return;
		}
		m68k_areg(regs, movem_index1[amask]) = v;
		srca += 4;
		amask = movem_next[amask];
	}
	x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return;
	}
	ipl_fetch_next();
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 16+ (4/0) */
/* 6 0,0   */

/* MVMEL.L #<data>.W,(d8,PC,Xn) */
void REGPARAM2 op_4cfb_13_ff(uae_u32 opcode)
{
	uae_u32 dstreg = 3;
	OpcodeFamily = 37;
	CurrentInstrCycles = 18; 
	uae_u16 mask = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
	do_cycles_ce000_internal(2);
	uaecptr srca;
	uaecptr tmppc = m68k_getpci() + 4;
	srca = get_disp_ea_000(tmppc, get_word_ce000_prefetch(6));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return;
	}
	if (srca & 1) {
		uaecptr srcav = srca;
		m68k_incpci(8);
		exception3_read_access(opcode, srca, 2, 2);
		return;
	}
	while (dmask) {
		uae_u32 v = (x_get_word(srca) << 16) | (m68k_dreg(regs, movem_index1[dmask]) & 0xffff);
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(8);
			exception2_read(opcode, srca + 0, 0x1, 2);
			return;
		}
		v &= 0xffff0000;
		v |= x_get_word(srca + 2); 
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(8);
			exception2_read(opcode, srca + 2, 0x1, 2);
			return;
		}
		m68k_dreg(regs, movem_index1[dmask]) = v;
		srca += 4;
		dmask = movem_next[dmask];
	}
	while (amask) {
		uae_u32 v = (x_get_word(srca) << 16) | (m68k_areg(regs, movem_index1[amask]) & 0xffff);
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(8);
			exception2_read(opcode, srca + 0, 0x1, 2);
			return;
		}
		v &= 0xffff0000;
		v |= x_get_word(srca + 2);
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(8);
			exception2_read(opcode, srca + 2, 0x1, 2);
			return;
		}
		m68k_areg(regs, movem_index1[amask]) = v;
		srca += 4;
		amask = movem_next[amask];
	}
	x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return;
	}
	ipl_fetch_next();
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 18+ (4/0) */
/* 6 4,0   */

/* TRAPQ.L #<data> */
void REGPARAM2 op_4e40_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 15);
	OpcodeFamily = 39;
	CurrentInstrCycles = 4;  
	uae_u32 src = srcreg;
	m68k_incpci(2);
	Exception_cpu(src + 32);
	return;
	return;
}
/* 4 (0/0) */
/* 2 0,0   */

/* LINK.W An,#<data>.W */
void REGPARAM2 op_4e50_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 47;
	CurrentInstrCycles = 16; 
	ipl_fetch_now();
	uae_s32 src = m68k_areg(regs, srcreg);
	uaecptr olda;
	olda = m68k_areg(regs, 7) - 4;
	m68k_areg(regs, 7) = olda;
	uae_s16 offs = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		m68k_areg(regs, 7) += 4;
		exception2_fetch(opcode, 4, 2);
		return;
	}
	if (olda & 1) {
		m68k_areg(regs, 7) += 4;
		m68k_areg(regs, srcreg) = olda;
		m68k_incpci(6);
		exception3_write_access(opcode, olda, sz_word, src >> 16, 1);
		return;
	}
	x_put_word(olda, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		m68k_areg(regs, 7) += 4;
		m68k_areg(regs, srcreg) = olda;
		exception2_write(opcode, olda + 0, 0x1, src >> 16, 1);
		return;
	}
	x_put_word(olda + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		m68k_areg(regs, 7) += 4;
		m68k_areg(regs, srcreg) = olda;
		exception2_write(opcode, olda + 2, 0x1, src, 1);
		return;
	}
	m68k_areg(regs, srcreg) = (m68k_areg(regs, 7));
	m68k_areg(regs, 7) += offs;
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (2/2) */
/* 4 0,0   */

/* UNLK.L An */
void REGPARAM2 op_4e58_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 48;
	CurrentInstrCycles = 12; 
	ipl_fetch_now();
	uae_s32 src = m68k_areg(regs, srcreg);
	uae_u32 olda = src;
	if (olda & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, olda, 2, 1);
		return;
	}
	uae_s32 old = x_get_word(olda) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, olda + 0, 0x1, 1);
		return;
	}
	old |= x_get_word(olda + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, olda + 2, 0x1, 1);
		return;
	}
	m68k_areg(regs, 7) = src + 4;
	m68k_areg(regs, srcreg) = (old);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 12 (3/0) */
/* 2 0,0   */

/* MVR2USP.L An */
void REGPARAM2 op_4e60_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 40;
	CurrentInstrCycles = 6;  
	if (!regs.s) {
		Exception(8);
		return;
	}
	uae_s32 src = m68k_areg(regs, srcreg);
	regs.usp = src;
	do_cycles_ce000_internal(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 6 (1/0) */
/* 2 0,0   */

/* MVUSP2R.L An */
void REGPARAM2 op_4e68_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 41;
	CurrentInstrCycles = 6;  
	if (!regs.s) {
		Exception(8);
		return;
	}
	m68k_areg(regs, srcreg) = (regs.usp);
	do_cycles_ce000_internal(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 6 (1/0) */
/* 2 0,0   */

/* RESET.L  */
void REGPARAM2 op_4e70_13_ff(uae_u32 opcode)
{
	OpcodeFamily = 42;
	CurrentInstrCycles = 132;
	if (!regs.s) {
		Exception(8);
		return;
	}
	bool r = cpureset();
	do_cycles_ce000_internal(128);
	if (r) {
		return;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 132 (1/0) */
/* 2 0,0   */

/* NOP.L  */
void REGPARAM2 op_4e71_13_ff(uae_u32 opcode)
{
	OpcodeFamily = 43;
	CurrentInstrCycles = 4;  
	regs.ir = regs.irc;
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 4 (1/0) */
/* 2 0,0   */

/* STOP.L #<data>.W */
void REGPARAM2 op_4e72_13_ff(uae_u32 opcode)
{
	OpcodeFamily = 44;
	CurrentInstrCycles = 4;  
	if (!regs.s) {
		Exception(8);
		return;
	}
	if (!regs.stopped) {
		uae_u16 src = regs.irc;
		regs.irc = src;
	}
	uae_u16 sr = regs.irc;
	ipl_fetch_next();
	checkint();
	regs.sr = sr;
	MakeFromSR_STOP();
	do_cycles_stop(4);
	m68k_setstopped(1);
	return;
}
/* 4 (0/0) */

/* RTE.L  */
void REGPARAM2 op_4e73_13_ff(uae_u32 opcode)
{
	OpcodeFamily = 45;
	CurrentInstrCycles = 24; 
	if (!regs.s) {
		Exception(8);
		return;
	}
	if (m68k_areg(regs, 7) & 1) {
		exception3_read_access(opcode, m68k_areg(regs, 7), 1, 1);
		return;
	}
	uaecptr oldpc = m68k_getpci();
	uae_u16 newsr;
	uae_u32 newpc;
	uaecptr a = m68k_areg(regs, 7);
	uae_u16 sr = x_get_word(a);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		exception2_read(opcode, a + 0, 0x1, 1);
		return;
	}
	uae_u16 format = x_get_word(a + 2 + 4);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		exception2_read(opcode, a + 6, 0x1, 1);
		return;
	}
	uae_u32 pc = x_get_word(a + 2) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		exception2_read(opcode, a + 2, 0x1, 1);
		return;
	}
	int frame = format >> 12;
	int offset = 8;
	if (frame == 0x0) {
		m68k_areg(regs, 7) += offset;
	} else if (frame == 0x8) {
		m68k_areg(regs, 7) += offset + 50;
	} else {
		SET_NFLG(((uae_s16)format) < 0); 
		SET_ZFLG(format == 0);
		SET_VFLG(0);
		Exception_cpu(14);
		return;
	}
	pc |= x_get_word(a + 2 + 2); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		exception2_read(opcode, a + 4, 0x1, 1);
		return;
	}
	regs.sr = sr;
	MakeFromSR();
	if (pc & 1) {
		m68k_incpci(2);
		exception3_read_prefetch_only(opcode, pc);
		return;
	}
	newsr = sr; newpc = pc;
	m68k_setpci_j(newpc);
	#ifdef DEBUGGER
	branch_stack_pop_rte(oldpc);
	#endif
	int pcadjust = oldpc - m68k_getpci() + 2;
	get_word_ce000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		pcoffset += pcadjust;
		exception2_fetch_opcode(opcode, 0, pcoffset);
		return;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 24 (6/0) */
/* 2 0,0 B */

/* RTD.L #<data>.W */
#ifndef CPUEMU_68000_ONLY
void REGPARAM2 op_4e74_13_ff(uae_u32 opcode)
{
	OpcodeFamily = 46;
	CurrentInstrCycles = 16; 
	uaecptr oldpc = m68k_getpci();
	uaecptr pca;
	pca = m68k_areg(regs, 7);
	if (pca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, pca, 2, 1);
		return;
	}
	uae_s32 pc = x_get_word(pca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, pca + 0, 0x1, 1);
		return;
	}
	pc |= x_get_word(pca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, pca + 2, 0x1, 1);
		return;
	}
	m68k_areg(regs, 7) += 4;
	uae_s16 offs = regs.irc;
	m68k_areg(regs, 7) += offs;
	if (pc & 1) {
		m68k_incpci(2);
		exception3_read_prefetch_only(opcode, pc);
		return;
	}
	m68k_setpci_j(pc);
	get_word_ce000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		m68k_setpci_j(oldpc + 2);
		exception2_fetch_opcode(opcode, 0, pcoffset);
		return;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		m68k_setpci_j(oldpc + 2);
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 16 (4/0) */
/* 4 0,0 B */

#endif
/* RTS.L  */
void REGPARAM2 op_4e75_13_ff(uae_u32 opcode)
{
	OpcodeFamily = 49;
	CurrentInstrCycles = 16; 
	uaecptr oldpc = m68k_getpci();
	if (m68k_areg(regs, 7) & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, m68k_areg(regs, 7), 1, 1);
		return;
	}
	uaecptr newpc, dsta = m68k_areg(regs, 7);
	newpc = x_get_word(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	newpc |= x_get_word(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return;
	}
	m68k_areg(regs, 7) += 4;
	m68k_setpci_j(newpc);
	#ifdef DEBUGGER
	if (debugmem_trace) {
		branch_stack_pop_rts(oldpc);
	}
	#endif
	if (m68k_getpci() & 1) {
		uaecptr faultpc = m68k_getpci();
		m68k_setpci_j(oldpc);
		m68k_incpci(2);
		exception3_read_prefetch_only(opcode, faultpc);
		return;
	}
	int pcadjust = oldpc - m68k_getpci() + 2;
	get_word_ce000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		pcoffset += pcadjust;
		exception2_fetch_opcode(opcode, 0, pcoffset);
		return;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 16 (4/0) */
/* 2 0,0 B */

/* TRAPV.L  */
void REGPARAM2 op_4e76_13_ff(uae_u32 opcode)
{
	OpcodeFamily = 50;
	CurrentInstrCycles = 4;  
	m68k_incpci(2);
	if (GET_VFLG()) {
		do_cycles_ce000_internal(2);
		Exception_cpu(7);
		return;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 4 (1/0) */
/* 2 0,0   */

/* RTR.L  */
void REGPARAM2 op_4e77_13_ff(uae_u32 opcode)
{
	OpcodeFamily = 51;
	CurrentInstrCycles = 20; 
	if (m68k_areg(regs, 7) & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, m68k_areg(regs, 7), 1, 1);
		return;
	}
	uaecptr oldpc = m68k_getpci();
	MakeSR();
	uaecptr sra;
	sra = m68k_areg(regs, 7);
	if (sra & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, sra, 1, 1);
		return;
	}
	uae_s16 sr = x_get_word(sra);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, sra + 0, 0x1, 1);
		return;
	}
	m68k_areg(regs, 7) += 2;
	uaecptr pca;
	pca = m68k_areg(regs, 7);
	if (pca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, pca, 2, 1);
		return;
	}
	uae_s32 pc = x_get_word(pca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, pca + 0, 0x1, 1);
		return;
	}
	pc |= x_get_word(pca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, pca + 2, 0x1, 1);
		return;
	}
	m68k_areg(regs, 7) += 4;
	regs.sr &= 0xFF00; sr &= 0xFF;
	regs.sr |= sr;
	MakeFromSR();
	m68k_setpci_j(pc);
	if (m68k_getpci() & 1) {
		uaecptr faultpc = m68k_getpci();
		m68k_setpci_j(oldpc + 2);
		exception3_read_prefetch_only(opcode, faultpc);
		return;
	}
	int pcadjust = oldpc - m68k_getpci() + 2;
	get_word_ce000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		pcoffset += pcadjust;
		exception2_fetch_opcode(opcode, 0, pcoffset);
		return;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 20 (5/0) */
/* 2 0,0 B */

/* MOVEC2.L #<data>.W */
#ifndef CPUEMU_68000_ONLY
void REGPARAM2 op_4e7a_13_ff(uae_u32 opcode)
{
	OpcodeFamily = 82;
	CurrentInstrCycles = 12; 
	if(!regs.s) {
		Exception(8);
		return;
	}
	uae_s16 src = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	ipl_fetch_now();
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	int regno = (src >> 12) & 15;
	uae_u32 *regp = regs.regs + regno;
	if (!m68k_movec2(src & 0xFFF, regp)) {
		return;
	}
	do_cycles_ce000_internal(4);
	m68k_incpci(4);
	return;
}
/* 12 (2/0) */
/* 4 0,0   */

#endif
/* MOVE2C.L #<data>.W */
#ifndef CPUEMU_68000_ONLY
void REGPARAM2 op_4e7b_13_ff(uae_u32 opcode)
{
	OpcodeFamily = 83;
	CurrentInstrCycles = 10; 
	if(!regs.s) {
		Exception(8);
		return;
	}
	uae_s16 src = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	ipl_fetch_now();
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	int regno = (src >> 12) & 15;
	uae_u32 *regp = regs.regs + regno;
	if (!m68k_move2c(src & 0xFFF, regp)) {
		return;
	}
	do_cycles_ce000_internal(2);
	m68k_incpci(4);
	return;
}
/* 10 (2/0) */
/* 4 0,0   */

#endif
/* JSR.L (An) */
void REGPARAM2 op_4e90_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 52;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	ipl_fetch_now();
	uaecptr oldpc = m68k_getpci();
	uaecptr nextpc = oldpc + 2;
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_prefetch_only(opcode, srca);
		return;
	}
	m68k_setpci_j(srca);
	get_word_ce000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		pcoffset = (oldpc - srca) + 2;
		exception2_fetch_opcode(opcode, 0, pcoffset);
		return;
	}
	m68k_areg(regs, 7) -= 4;
	if (m68k_areg(regs, 7) & 1) {
		m68k_setpci_j(oldpc);
		m68k_incpci(2);
		exception3_write_access(opcode, m68k_areg(regs, 7), 1, oldpc >> 16, 1);
		return;
	}
	uaecptr dsta = m68k_areg(regs, 7);
	x_put_word(dsta, nextpc >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_write(opcode, dsta + 0, 0x1, nextpc >> 16, 1);
		return;
	}
	x_put_word(dsta + 2, nextpc);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_write(opcode, dsta + 2, 0x1, nextpc, 1);
		return;
	}
	#ifdef DEBUGGER
	if (debugmem_trace) {
		branch_stack_push(oldpc, nextpc);
	}
	#endif
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, 0);
		return;
	}
	return;
}
/* 16 (2/2) */
/* 2 0,0 B */

/* JSR.L (d16,An) */
void REGPARAM2 op_4ea8_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 52;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)regs.irc;
	ipl_fetch_now();
	uaecptr oldpc = m68k_getpci();
	uaecptr nextpc = oldpc + 4;
	if (srca & 1) {
		do_cycles_ce000_internal(2);
		m68k_incpci(2);
		exception3_read_prefetch_only(opcode, srca);
		return;
	}
	do_cycles_ce000_internal(2);
	m68k_setpci_j(srca);
	get_word_ce000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		pcoffset = (oldpc - srca) + 4;
		exception2_fetch_opcode(opcode, 0, pcoffset);
		return;
	}
	m68k_areg(regs, 7) -= 4;
	if (m68k_areg(regs, 7) & 1) {
		m68k_setpci_j(oldpc);
		m68k_incpci(4);
		exception3_write_access(opcode, m68k_areg(regs, 7), 1, oldpc >> 16, 1);
		return;
	}
	uaecptr dsta = m68k_areg(regs, 7);
	x_put_word(dsta, nextpc >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_write(opcode, dsta + 0, 0x1, nextpc >> 16, 1);
		return;
	}
	x_put_word(dsta + 2, nextpc);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_write(opcode, dsta + 2, 0x1, nextpc, 1);
		return;
	}
	#ifdef DEBUGGER
	if (debugmem_trace) {
		branch_stack_push(oldpc, nextpc);
	}
	#endif
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, 0);
		return;
	}
	return;
}
/* 18 (2/2) */
/* 4 0,0 B */

/* JSR.L (d8,An,Xn) */
void REGPARAM2 op_4eb0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 52;
	CurrentInstrCycles = 22; 
	uaecptr srca;
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), regs.irc);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, 0);
		return;
	}
	ipl_fetch_now();
	uaecptr oldpc = m68k_getpci();
	uaecptr nextpc = oldpc + 2;
	if (srca & 1) {
		do_cycles_ce000_internal(6);
		m68k_incpci(2);
		exception3_read_prefetch_only(opcode, srca);
		return;
	}
	do_cycles_ce000_internal(6);
	nextpc += 2;
	m68k_setpci_j(srca);
	get_word_ce000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		pcoffset = (oldpc - srca) + 4;
		exception2_fetch_opcode(opcode, 0, pcoffset);
		return;
	}
	m68k_areg(regs, 7) -= 4;
	if (m68k_areg(regs, 7) & 1) {
		m68k_setpci_j(oldpc);
		m68k_incpci(4);
		exception3_write_access(opcode, m68k_areg(regs, 7), 1, oldpc >> 16, 1);
		return;
	}
	uaecptr dsta = m68k_areg(regs, 7);
	x_put_word(dsta, nextpc >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_write(opcode, dsta + 0, 0x1, nextpc >> 16, 1);
		return;
	}
	x_put_word(dsta + 2, nextpc);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_write(opcode, dsta + 2, 0x1, nextpc, 1);
		return;
	}
	#ifdef DEBUGGER
	if (debugmem_trace) {
		branch_stack_push(oldpc, nextpc);
	}
	#endif
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, 0);
		return;
	}
	return;
}
/* 22 (2/2) */
/* 2 2,0 B */

/* JSR.L (xxx).W */
void REGPARAM2 op_4eb8_13_ff(uae_u32 opcode)
{
	OpcodeFamily = 52;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)regs.irc;
	ipl_fetch_now();
	uaecptr oldpc = m68k_getpci();
	uaecptr nextpc = oldpc + 4;
	if (srca & 1) {
		do_cycles_ce000_internal(2);
		m68k_incpci(4);
		exception3_read_prefetch_only(opcode, srca);
		return;
	}
	do_cycles_ce000_internal(2);
	m68k_setpci_j(srca);
	get_word_ce000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		pcoffset = (oldpc - srca) + 4;
		exception2_fetch_opcode(opcode, 0, pcoffset);
		return;
	}
	m68k_areg(regs, 7) -= 4;
	if (m68k_areg(regs, 7) & 1) {
		m68k_setpci_j(oldpc);
		m68k_incpci(4);
		exception3_write_access(opcode, m68k_areg(regs, 7), 1, oldpc >> 16, 1);
		return;
	}
	uaecptr dsta = m68k_areg(regs, 7);
	x_put_word(dsta, nextpc >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x1, nextpc >> 16, 1);
		return;
	}
	x_put_word(dsta + 2, nextpc);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 2, 0x1, nextpc, 1);
		return;
	}
	#ifdef DEBUGGER
	if (debugmem_trace) {
		branch_stack_push(oldpc, nextpc);
	}
	#endif
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, 0);
		return;
	}
	return;
}
/* 18 (2/2) */
/* 4 0,0 B */

/* JSR.L (xxx).L */
void REGPARAM2 op_4eb9_13_ff(uae_u32 opcode)
{
	OpcodeFamily = 52;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	srca = get_word_ce000_prefetch(4) << 16;
	srca |= regs.irc;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	ipl_fetch_now();
	uaecptr oldpc = m68k_getpci();
	uaecptr nextpc = oldpc + 6;
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_prefetch_only(opcode, srca);
		return;
	}
	m68k_setpci_j(srca);
	get_word_ce000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		pcoffset = (oldpc - srca) + 6;
		exception2_fetch_opcode(opcode, 0, pcoffset);
		return;
	}
	m68k_areg(regs, 7) -= 4;
	if (m68k_areg(regs, 7) & 1) {
		m68k_setpci_j(oldpc);
		m68k_incpci(6);
		exception3_write_access(opcode, m68k_areg(regs, 7), 1, oldpc >> 16, 1);
		return;
	}
	uaecptr dsta = m68k_areg(regs, 7);
	x_put_word(dsta, nextpc >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, nextpc >> 16, 1);
		return;
	}
	x_put_word(dsta + 2, nextpc);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 2, 0x1, nextpc, 1);
		return;
	}
	#ifdef DEBUGGER
	if (debugmem_trace) {
		branch_stack_push(oldpc, nextpc);
	}
	#endif
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, 0);
		return;
	}
	return;
}
/* 20 (3/2) */
/* 6 0,0 B */

/* JSR.L (d16,PC) */
void REGPARAM2 op_4eba_13_ff(uae_u32 opcode)
{
	OpcodeFamily = 52;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	srca = m68k_getpci() + 2;
	srca += (uae_s32)(uae_s16)regs.irc;
	ipl_fetch_now();
	uaecptr oldpc = m68k_getpci();
	uaecptr nextpc = oldpc + 4;
	if (srca & 1) {
		do_cycles_ce000_internal(2);
		m68k_incpci(2);
		exception3_read_prefetch_only(opcode, srca);
		return;
	}
	do_cycles_ce000_internal(2);
	m68k_setpci_j(srca);
	get_word_ce000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		pcoffset = (oldpc - srca) + 4;
		exception2_fetch_opcode(opcode, 0, pcoffset);
		return;
	}
	m68k_areg(regs, 7) -= 4;
	if (m68k_areg(regs, 7) & 1) {
		m68k_setpci_j(oldpc);
		m68k_incpci(4);
		exception3_write_access(opcode, m68k_areg(regs, 7), 1, oldpc >> 16, 1);
		return;
	}
	uaecptr dsta = m68k_areg(regs, 7);
	x_put_word(dsta, nextpc >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_write(opcode, dsta + 0, 0x1, nextpc >> 16, 1);
		return;
	}
	x_put_word(dsta + 2, nextpc);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_write(opcode, dsta + 2, 0x1, nextpc, 1);
		return;
	}
	#ifdef DEBUGGER
	if (debugmem_trace) {
		branch_stack_push(oldpc, nextpc);
	}
	#endif
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, 0);
		return;
	}
	return;
}
/* 18 (2/2) */
/* 4 0,0 B */

/* JSR.L (d8,PC,Xn) */
void REGPARAM2 op_4ebb_13_ff(uae_u32 opcode)
{
	OpcodeFamily = 52;
	CurrentInstrCycles = 22; 
	uaecptr srca;
	uaecptr tmppc = m68k_getpci() + 2;
	srca = get_disp_ea_000(tmppc, regs.irc);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, 0);
		return;
	}
	ipl_fetch_now();
	uaecptr oldpc = m68k_getpci();
	uaecptr nextpc = oldpc + 2;
	if (srca & 1) {
		do_cycles_ce000_internal(6);
		m68k_incpci(2);
		exception3_read_prefetch_only(opcode, srca);
		return;
	}
	do_cycles_ce000_internal(6);
	nextpc += 2;
	m68k_setpci_j(srca);
	get_word_ce000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		pcoffset = (oldpc - srca) + 4;
		exception2_fetch_opcode(opcode, 0, pcoffset);
		return;
	}
	m68k_areg(regs, 7) -= 4;
	if (m68k_areg(regs, 7) & 1) {
		m68k_setpci_j(oldpc);
		m68k_incpci(4);
		exception3_write_access(opcode, m68k_areg(regs, 7), 1, oldpc >> 16, 1);
		return;
	}
	uaecptr dsta = m68k_areg(regs, 7);
	x_put_word(dsta, nextpc >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_write(opcode, dsta + 0, 0x1, nextpc >> 16, 1);
		return;
	}
	x_put_word(dsta + 2, nextpc);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_write(opcode, dsta + 2, 0x1, nextpc, 1);
		return;
	}
	#ifdef DEBUGGER
	if (debugmem_trace) {
		branch_stack_push(oldpc, nextpc);
	}
	#endif
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, 0);
		return;
	}
	return;
}
/* 22 (2/2) */
/* 2 2,0 B */

/* JMP.L (An) */
void REGPARAM2 op_4ed0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 53;
	CurrentInstrCycles = 8;  
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	ipl_fetch_now();
	uaecptr oldpc = m68k_getpci();
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_prefetch_only(opcode, srca);
		return;
	}
	m68k_setpci_j(srca);
	get_word_ce000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		pcoffset = (oldpc - srca) + 2;
		exception2_fetch_opcode(opcode, 0, pcoffset);
		return;
	}
	regs.ir = regs.irc;
	get_word_ce000_prefetch(2);
	opcode = regs.ir;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, 0);
		return;
	}
	return;
}
/* 8 (2/0) */
/* 2 0,0 B */

/* JMP.L (d16,An) */
void REGPARAM2 op_4ee8_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 53;
	CurrentInstrCycles = 10; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)regs.irc;
	ipl_fetch_now();
	uaecptr oldpc = m68k_getpci();
	if (srca & 1) {
		do_cycles_ce000_internal(2);
		m68k_incpci(2);
		exception3_read_prefetch_only(opcode, srca);
		return;
	}
	do_cycles_ce000_internal(2);
	m68k_setpci_j(srca);
	get_word_ce000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		pcoffset = (oldpc - srca) + 2;
		exception2_fetch_opcode(opcode, 0, pcoffset);
		return;
	}
	regs.ir = regs.irc;
	get_word_ce000_prefetch(2);
	opcode = regs.ir;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, 0);
		return;
	}
	return;
}
/* 10 (2/0) */
/* 4 0,0 B */

/* JMP.L (d8,An,Xn) */
void REGPARAM2 op_4ef0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 53;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), regs.irc);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, 0);
		return;
	}
	ipl_fetch_now();
	uaecptr oldpc = m68k_getpci();
	if (srca & 1) {
		do_cycles_ce000_internal(6);
		m68k_incpci(2);
		exception3_read_prefetch_only(opcode, srca);
		return;
	}
	do_cycles_ce000_internal(6);
	m68k_setpci_j(srca);
	get_word_ce000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		pcoffset = (oldpc - srca) + 2;
		exception2_fetch_opcode(opcode, 0, pcoffset);
		return;
	}
	regs.ir = regs.irc;
	get_word_ce000_prefetch(2);
	opcode = regs.ir;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, 0);
		return;
	}
	return;
}
/* 14 (2/0) */
/* 2 2,0 B */

/* JMP.L (xxx).W */
void REGPARAM2 op_4ef8_13_ff(uae_u32 opcode)
{
	OpcodeFamily = 53;
	CurrentInstrCycles = 10; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)regs.irc;
	ipl_fetch_now();
	uaecptr oldpc = m68k_getpci();
	if (srca & 1) {
		do_cycles_ce000_internal(2);
		m68k_incpci(2);
		exception3_read_prefetch_only(opcode, srca);
		return;
	}
	do_cycles_ce000_internal(2);
	m68k_setpci_j(srca);
	get_word_ce000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		pcoffset = (oldpc - srca) + 2;
		exception2_fetch_opcode(opcode, 0, pcoffset);
		return;
	}
	regs.ir = regs.irc;
	get_word_ce000_prefetch(2);
	opcode = regs.ir;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, 0);
		return;
	}
	return;
}
/* 10 (2/0) */
/* 4 0,0 B */

/* JMP.L (xxx).L */
void REGPARAM2 op_4ef9_13_ff(uae_u32 opcode)
{
	OpcodeFamily = 53;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = get_word_ce000_prefetch(4) << 16;
	srca |= regs.irc;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	ipl_fetch_now();
	uaecptr oldpc = m68k_getpci();
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_prefetch_only(opcode, srca);
		return;
	}
	m68k_setpci_j(srca);
	get_word_ce000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		pcoffset = (oldpc - srca) + 2;
		exception2_fetch_opcode(opcode, 0, pcoffset);
		return;
	}
	regs.ir = regs.irc;
	get_word_ce000_prefetch(2);
	opcode = regs.ir;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, 0);
		return;
	}
	return;
}
/* 12 (3/0) */
/* 6 0,0 B */

/* JMP.L (d16,PC) */
void REGPARAM2 op_4efa_13_ff(uae_u32 opcode)
{
	OpcodeFamily = 53;
	CurrentInstrCycles = 10; 
	uaecptr srca;
	srca = m68k_getpci() + 2;
	srca += (uae_s32)(uae_s16)regs.irc;
	ipl_fetch_now();
	uaecptr oldpc = m68k_getpci();
	if (srca & 1) {
		do_cycles_ce000_internal(2);
		m68k_incpci(2);
		exception3_read_prefetch_only(opcode, srca);
		return;
	}
	do_cycles_ce000_internal(2);
	m68k_setpci_j(srca);
	get_word_ce000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		pcoffset = (oldpc - srca) + 2;
		exception2_fetch_opcode(opcode, 0, pcoffset);
		return;
	}
	regs.ir = regs.irc;
	get_word_ce000_prefetch(2);
	opcode = regs.ir;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, 0);
		return;
	}
	return;
}
/* 10 (2/0) */
/* 4 0,0 B */

/* JMP.L (d8,PC,Xn) */
void REGPARAM2 op_4efb_13_ff(uae_u32 opcode)
{
	OpcodeFamily = 53;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	uaecptr tmppc = m68k_getpci() + 2;
	srca = get_disp_ea_000(tmppc, regs.irc);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, 0);
		return;
	}
	ipl_fetch_now();
	uaecptr oldpc = m68k_getpci();
	if (srca & 1) {
		do_cycles_ce000_internal(6);
		m68k_incpci(2);
		exception3_read_prefetch_only(opcode, srca);
		return;
	}
	do_cycles_ce000_internal(6);
	m68k_setpci_j(srca);
	get_word_ce000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		pcoffset = (oldpc - srca) + 2;
		exception2_fetch_opcode(opcode, 0, pcoffset);
		return;
	}
	regs.ir = regs.irc;
	get_word_ce000_prefetch(2);
	opcode = regs.ir;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, 0);
		return;
	}
	return;
}
/* 14 (2/0) */
/* 2 2,0 B */

/* ADDQ.B #<data>,Dn */
void REGPARAM2 op_5000_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 4;  
	uae_u32 src = srcreg;
	uae_s8 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u8)(~dst)) < ((uae_u8)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 4 (1/0) */
/* 2 0,0   */

/* ADDQ.B #<data>,(An) */
void REGPARAM2 op_5010_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 12; 
	uae_u32 src = srcreg;
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u8)(~dst)) < ((uae_u8)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_byte(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x0, newv, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 12 (2/1) */
/* 2 0,0   */

/* ADDQ.B #<data>,(An)+ */
void REGPARAM2 op_5018_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 12; 
	uae_u32 src = srcreg;
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
	uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u8)(~dst)) < ((uae_u8)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_byte(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x0, newv, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 12 (2/1) */
/* 2 0,0   */

/* ADDQ.B #<data>,-(An) */
void REGPARAM2 op_5020_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 14; 
	uae_u32 src = srcreg;
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
	do_cycles_ce000_internal(2);
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, dstreg) = dsta;
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	m68k_areg(regs, dstreg) = dsta;
	uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u8)(~dst)) < ((uae_u8)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_byte(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x0, newv, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 14 (2/1) */
/* 2 0,0   */

/* ADDQ.B #<data>,(d16,An) */
void REGPARAM2 op_5028_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 16; 
	uae_u32 src = srcreg;
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u8)(~dst)) < ((uae_u8)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_byte(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x0, newv, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* ADDQ.B #<data>,(d8,An,Xn) */
void REGPARAM2 op_5030_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 18; 
	uae_u32 src = srcreg;
	uaecptr dsta;
	do_cycles_ce000_internal(2);
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u8)(~dst)) < ((uae_u8)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_byte(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x0, newv, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 18 (3/1) */
/* 4 4,0   */

/* ADDQ.B #<data>,(xxx).W */
void REGPARAM2 op_5038_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	OpcodeFamily = 11;
	CurrentInstrCycles = 16; 
	uae_u32 src = srcreg;
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u8)(~dst)) < ((uae_u8)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_byte(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x0, newv, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* ADDQ.B #<data>,(xxx).L */
void REGPARAM2 op_5039_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	OpcodeFamily = 11;
	CurrentInstrCycles = 20; 
	uae_u32 src = srcreg;
	uaecptr dsta;
	dsta = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	dsta |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u8)(~dst)) < ((uae_u8)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_byte(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 0, 0x0, newv, 1);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 20 (4/1) */
/* 6 0,0   */

/* ADDQ.W #<data>,Dn */
void REGPARAM2 op_5040_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 4;  
	uae_u32 src = srcreg;
	uae_s16 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 4 (1/0) */
/* 2 0,0   */

/* ADDAQ.W #<data>,An */
void REGPARAM2 op_5048_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 12;
	CurrentInstrCycles = 8;  
	uae_u32 src = srcreg;
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = dst + src;
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		areg_68000_long_replace_low(dstreg, newv);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	do_cycles_ce000_internal(4);
	m68k_areg(regs, dstreg) = (newv);
	m68k_incpci(2);
	return;
}
/* 8 (1/0) */
/* 2 0,0   */

/* ADDQ.W #<data>,(An) */
void REGPARAM2 op_5050_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 12; 
	uae_u32 src = srcreg;
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	if (dsta & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dsta, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 dst = x_get_word(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_word(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x1, newv, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 12 (2/1) */
/* 2 0,0   */

/* ADDQ.W #<data>,(An)+ */
void REGPARAM2 op_5058_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 12; 
	uae_u32 src = srcreg;
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	if (dsta & 1) {
		m68k_areg(regs, dstreg) += 2 + 0;
		m68k_incpci(2);
		exception3_read_access(opcode, dsta, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 dst = x_get_word(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, dstreg) += 2 + 0;
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	m68k_areg(regs, dstreg) += 2;
	uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_word(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x1, newv, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 12 (2/1) */
/* 2 0,0   */

/* ADDQ.W #<data>,-(An) */
void REGPARAM2 op_5060_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 14; 
	uae_u32 src = srcreg;
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - 2;
	do_cycles_ce000_internal(2);
	if (dsta & 1) {
		m68k_areg(regs, dstreg) = dsta;
		m68k_incpci(2);
		exception3_read_access(opcode, dsta, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 dst = x_get_word(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, dstreg) = dsta;
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	m68k_areg(regs, dstreg) = dsta;
	uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_word(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x1, newv, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 14 (2/1) */
/* 2 0,0   */

/* ADDQ.W #<data>,(d16,An) */
void REGPARAM2 op_5068_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 16; 
	uae_u32 src = srcreg;
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dsta, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 dst = x_get_word(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_word(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, newv, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* ADDQ.W #<data>,(d8,An,Xn) */
void REGPARAM2 op_5070_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 18; 
	uae_u32 src = srcreg;
	uaecptr dsta;
	do_cycles_ce000_internal(2);
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dsta, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 dst = x_get_word(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_word(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, newv, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 18 (3/1) */
/* 4 4,0   */

/* ADDQ.W #<data>,(xxx).W */
void REGPARAM2 op_5078_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	OpcodeFamily = 11;
	CurrentInstrCycles = 16; 
	uae_u32 src = srcreg;
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, dsta, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 dst = x_get_word(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_word(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, newv, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* ADDQ.W #<data>,(xxx).L */
void REGPARAM2 op_5079_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	OpcodeFamily = 11;
	CurrentInstrCycles = 20; 
	uae_u32 src = srcreg;
	uaecptr dsta;
	dsta = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	dsta |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, dsta, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 dst = x_get_word(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_word(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 0, 0x1, newv, 1);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 20 (4/1) */
/* 6 0,0   */

/* ADDQ.L #<data>,Dn */
void REGPARAM2 op_5080_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 8;  
	uae_u32 src = srcreg;
	uae_s32 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u32)(~dst)) < ((uae_u32)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		uae_s16 bnewv = (uae_s16)dst + (uae_s16)src;
		int bflgs = ((uae_s16)(src)) < 0;
		int bflgo = ((uae_s16)(dst)) < 0;
		int bflgn = bnewv < 0;
		ccr_68000_long_move_ae_LZN(bnewv);
		SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
		SET_XFLG(GET_CFLG());
		SET_VFLG((bflgs ^ bflgn) & (bflgo ^ bflgn));
		dreg_68000_long_replace_low(dstreg, bnewv);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	do_cycles_ce000_internal(4);
	m68k_dreg(regs, dstreg) = (newv);
	m68k_incpci(2);
	return;
}
/* 8 (1/0) */
/* 2 0,0   */

/* ADDAQ.L #<data>,An */
void REGPARAM2 op_5088_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 12;
	CurrentInstrCycles = 8;  
	uae_u32 src = srcreg;
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = dst + src;
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		areg_68000_long_replace_low(dstreg, newv);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	do_cycles_ce000_internal(4);
	m68k_areg(regs, dstreg) = (newv);
	m68k_incpci(2);
	return;
}
/* 8 (1/0) */
/* 2 0,0   */

/* ADDQ.L #<data>,(An) */
void REGPARAM2 op_5090_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 20; 
	uae_u32 src = srcreg;
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	if (dsta & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dsta, 2, 1);
		return;
	}
	uae_s32 dst = x_get_word(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	dst |= x_get_word(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return;
	}
	uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u32)(~dst)) < ((uae_u32)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		uae_s16 bnewv = (uae_s16)dst + (uae_s16)src;
		int bflgs = ((uae_s16)(src)) < 0;
		int bflgo = ((uae_s16)(dst)) < 0;
		int bflgn = bnewv < 0;
		ccr_68000_long_move_ae_LZN(bnewv);
		SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
		SET_XFLG(GET_CFLG());
		SET_VFLG((bflgs ^ bflgn) & (bflgo ^ bflgn));
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	x_put_word(dsta + 2, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 2, 0x1, newv, 1);
		return;
	}
	x_put_word(dsta, newv >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x1, newv >> 16, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 20 (3/2) */
/* 2 0,0   */

/* ADDQ.L #<data>,(An)+ */
void REGPARAM2 op_5098_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 20; 
	uae_u32 src = srcreg;
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	if (dsta & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dsta, 2, 1);
		return;
	}
	uae_s32 dst = x_get_word(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	dst |= x_get_word(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return;
	}
	m68k_areg(regs, dstreg) += 4;
	uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u32)(~dst)) < ((uae_u32)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		uae_s16 bnewv = (uae_s16)dst + (uae_s16)src;
		int bflgs = ((uae_s16)(src)) < 0;
		int bflgo = ((uae_s16)(dst)) < 0;
		int bflgn = bnewv < 0;
		ccr_68000_long_move_ae_LZN(bnewv);
		SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
		SET_XFLG(GET_CFLG());
		SET_VFLG((bflgs ^ bflgn) & (bflgo ^ bflgn));
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	x_put_word(dsta + 2, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 2, 0x1, newv, 1);
		return;
	}
	x_put_word(dsta, newv >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x1, newv >> 16, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 20 (3/2) */
/* 2 0,0   */

/* ADDQ.L #<data>,-(An) */
void REGPARAM2 op_50a0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 22; 
	uae_u32 src = srcreg;
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - 4;
	do_cycles_ce000_internal(2);
	if (dsta & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dsta, 2, 1);
		return;
	}
	uae_s32 dst = x_get_word(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	dst |= x_get_word(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, dstreg) = dsta;
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return;
	}
	m68k_areg(regs, dstreg) = dsta;
	uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u32)(~dst)) < ((uae_u32)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		uae_s16 bnewv = (uae_s16)dst + (uae_s16)src;
		int bflgs = ((uae_s16)(src)) < 0;
		int bflgo = ((uae_s16)(dst)) < 0;
		int bflgn = bnewv < 0;
		ccr_68000_long_move_ae_LZN(bnewv);
		SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
		SET_XFLG(GET_CFLG());
		SET_VFLG((bflgs ^ bflgn) & (bflgo ^ bflgn));
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	x_put_word(dsta + 2, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 2, 0x1, newv, 1);
		return;
	}
	x_put_word(dsta, newv >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x1, newv >> 16, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 22 (3/2) */
/* 2 0,0   */

/* ADDQ.L #<data>,(d16,An) */
void REGPARAM2 op_50a8_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 24; 
	uae_u32 src = srcreg;
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dsta, 2, 1);
		return;
	}
	uae_s32 dst = x_get_word(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	dst |= x_get_word(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return;
	}
	uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u32)(~dst)) < ((uae_u32)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		uae_s16 bnewv = (uae_s16)dst + (uae_s16)src;
		int bflgs = ((uae_s16)(src)) < 0;
		int bflgo = ((uae_s16)(dst)) < 0;
		int bflgn = bnewv < 0;
		ccr_68000_long_move_ae_LZN(bnewv);
		SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
		SET_XFLG(GET_CFLG());
		SET_VFLG((bflgs ^ bflgn) & (bflgo ^ bflgn));
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	x_put_word(dsta + 2, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 2, 0x1, newv, 1);
		return;
	}
	x_put_word(dsta, newv >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, newv >> 16, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 24 (4/2) */
/* 4 0,0   */

/* ADDQ.L #<data>,(d8,An,Xn) */
void REGPARAM2 op_50b0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 26; 
	uae_u32 src = srcreg;
	uaecptr dsta;
	do_cycles_ce000_internal(2);
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dsta, 2, 1);
		return;
	}
	uae_s32 dst = x_get_word(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	dst |= x_get_word(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return;
	}
	uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u32)(~dst)) < ((uae_u32)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		uae_s16 bnewv = (uae_s16)dst + (uae_s16)src;
		int bflgs = ((uae_s16)(src)) < 0;
		int bflgo = ((uae_s16)(dst)) < 0;
		int bflgn = bnewv < 0;
		ccr_68000_long_move_ae_LZN(bnewv);
		SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
		SET_XFLG(GET_CFLG());
		SET_VFLG((bflgs ^ bflgn) & (bflgo ^ bflgn));
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	x_put_word(dsta + 2, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 2, 0x1, newv, 1);
		return;
	}
	x_put_word(dsta, newv >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, newv >> 16, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 26 (4/2) */
/* 4 4,0   */

/* ADDQ.L #<data>,(xxx).W */
void REGPARAM2 op_50b8_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	OpcodeFamily = 11;
	CurrentInstrCycles = 24; 
	uae_u32 src = srcreg;
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, dsta, 2, 1);
		return;
	}
	uae_s32 dst = x_get_word(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	dst |= x_get_word(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return;
	}
	uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u32)(~dst)) < ((uae_u32)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		uae_s16 bnewv = (uae_s16)dst + (uae_s16)src;
		int bflgs = ((uae_s16)(src)) < 0;
		int bflgo = ((uae_s16)(dst)) < 0;
		int bflgn = bnewv < 0;
		ccr_68000_long_move_ae_LZN(bnewv);
		SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
		SET_XFLG(GET_CFLG());
		SET_VFLG((bflgs ^ bflgn) & (bflgo ^ bflgn));
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	x_put_word(dsta + 2, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 2, 0x1, newv, 1);
		return;
	}
	x_put_word(dsta, newv >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, newv >> 16, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 24 (4/2) */
/* 4 0,0   */

/* ADDQ.L #<data>,(xxx).L */
void REGPARAM2 op_50b9_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	OpcodeFamily = 11;
	CurrentInstrCycles = 28; 
	uae_u32 src = srcreg;
	uaecptr dsta;
	dsta = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	dsta |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, dsta, 2, 1);
		return;
	}
	uae_s32 dst = x_get_word(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	dst |= x_get_word(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return;
	}
	uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u32)(~dst)) < ((uae_u32)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		uae_s16 bnewv = (uae_s16)dst + (uae_s16)src;
		int bflgs = ((uae_s16)(src)) < 0;
		int bflgo = ((uae_s16)(dst)) < 0;
		int bflgn = bnewv < 0;
		ccr_68000_long_move_ae_LZN(bnewv);
		SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
		SET_XFLG(GET_CFLG());
		SET_VFLG((bflgs ^ bflgn) & (bflgo ^ bflgn));
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	x_put_word(dsta + 2, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 2, 0x1, newv, 1);
		return;
	}
	x_put_word(dsta, newv >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 0, 0x1, newv >> 16, 1);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 28 (5/2) */
/* 6 0,0   */

/* Scc.B Dn (T) */
void REGPARAM2 op_50c0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 4;  
	int val = cctrue(0) ? 0xff : 0x00;
	int cycles = val ? 2 : 0;
	if (!val) {
		m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff);
	}
	regs.ir = regs.irc;
	if (!val)
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if(!val && regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff);
	if (cycles > 0) do_cycles_ce000_internal(cycles);
	m68k_incpci(2);
	return;
}
/* 4+ (1/0) */
/* 2 0,0   */

/* DBcc.W Dn,#<data>.W (T) */
void REGPARAM2 op_50c8_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 58;
	CurrentInstrCycles = 10; 
	int pcadjust = -2;
	uae_s16 src = m68k_dreg(regs, srcreg);
	uae_s16 offs = regs.irc;
	int was_loop_mode = regs.loop_mode;
	regs.loop_mode = 0;
	uaecptr oldpc = m68k_getpci();
	do_cycles_ce000_internal(2);
	if (!cctrue(0)) {
		m68k_incpci((uae_s32)offs + 2);
		if (offs & 1) {
			get_word_ce000_prefetch(-1);
			exception3_read_prefetch(opcode, m68k_getpci());
			return;
		}
		if(offs == -4 && !regs.t1 && loop_mode_table[regs.ird]) {
			if(!was_loop_mode) {
				uae_u16 irc = regs.irc;
				get_word_ce000_prefetch(0);
				if(hardware_bus_error) {
					int pcoffset = 0;
					exception2_fetch_opcode(opcode, 0, 0);
					return;
				}
				get_word_ce000_prefetch(2);
				if(hardware_bus_error) {
					int pcoffset = 0;
					exception2_fetch_opcode(opcode, 2, 0);
					return;
				}
				regs.irc = irc;
			} else {
				do_cycles_ce000_internal(2);
			}
			regs.loop_mode = 1;
			src = m68k_dreg(regs, srcreg);
			m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
			if (src) {
				loop_mode_table[regs.ird](regs.ird);
				 // quick exit if condition false and count expired
				if (!cctrue(0) && (m68k_dreg(regs, srcreg) & 0xffff) == 0) {
					m68k_dreg(regs, srcreg) |= 0xffff;
					 // loop exit: add possible extra cycle(s)
					if(regs.loop_mode >> 16) {
						do_cycles_ce000_internal(regs.loop_mode >> 16);
					}
					regs.loop_mode = 0;
					m68k_setpci_j(oldpc + 4);
					get_word_ce000_prefetch(0);
					if(hardware_bus_error) {
						int pcoffset = 0;
						m68k_setpci_j(oldpc + 2);
						exception2_fetch_opcode(opcode, 0, pcoffset);
						return;
					}
					regs.ir = regs.irc;
					opcode = regs.ir;
					ipl_fetch_next();
					get_word_ce000_prefetch(2);
					if(hardware_bus_error) {
						int pcoffset = 0;
						m68k_setpci_j(oldpc + 2);
						exception2_fetch_opcode(opcode, 2, pcoffset);
						return;
					}
					return;
				}
				 // loop continue: add possible extra cycle(s)
				if(regs.loop_mode & 0xfffe) {
					do_cycles_ce000_internal(regs.loop_mode & 0xfffe);
				}
				m68k_setpci_j(oldpc);
				ipl_fetch_now();
				return;
			}
			regs.loop_mode = 0;
			m68k_setpci_j(oldpc + 4);
			get_word_ce000_prefetch(0);
			if(hardware_bus_error) {
				int pcoffset = 0;
				m68k_setpci_j(oldpc + 2);
				exception2_fetch_opcode(opcode, 0, pcoffset);
				return;
			}
			regs.ir = regs.irc;
			opcode = regs.ir;
			ipl_fetch_next();
			get_word_ce000_prefetch(2);
			if(hardware_bus_error) {
				int pcoffset = 0;
				m68k_setpci_j(oldpc + 2);
				exception2_fetch_opcode(opcode, 2, pcoffset);
				return;
			}
			return;
		}
		get_word_ce000_prefetch(0);
		if(hardware_bus_error) {
			int pcoffset = 0;
			pcoffset = oldpc - m68k_getpci() + 4;
			exception2_fetch_opcode(opcode, 0, pcoffset);
			return;
		}
		if (src) {
			m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
			regs.ir = regs.irc;
			opcode = regs.ir;
			ipl_fetch_next();
			get_word_ce000_prefetch(2);
			if(hardware_bus_error) {
				int pcoffset = 0;
				exception2_fetch_opcode(opcode, 2, 0);
				return;
			}
			return;
		}
		do_cycles_ce000_internal(2);
		pcadjust = 0;
	}
	m68k_setpci_j(oldpc + 4);
	get_word_ce000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		pcoffset += pcadjust;
		exception2_fetch_opcode(opcode, 0, pcoffset);
		return;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	if (!cctrue(0)) {
		m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
	}
	ipl_fetch_next();
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 10 (2/0) */
/* 4 0,0 B */

/* Scc.B (An) (T) */
void REGPARAM2 op_50d0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 10; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	do_cycles_ce000_internal(2);
	ipl_fetch_now();
	regs.ir = regs.irc;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	int val = cctrue(0) ? 0xff : 0x00;
	x_put_byte(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 10 (1/1) */
/* 2 0,0   */

/* Scc.B (An)+ (T) */
void REGPARAM2 op_50d8_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	do_cycles_ce000_internal(4);
	ipl_fetch_now();
	m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
	regs.ir = regs.irc;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	int val = cctrue(0) ? 0xff : 0x00;
	x_put_byte(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 12 (1/1) */
/* 2 0,0   */

/* Scc.B -(An) (T) */
void REGPARAM2 op_50e0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
	do_cycles_ce000_internal(4);
	ipl_fetch_now();
	m68k_areg(regs, srcreg) = srca;
	regs.ir = regs.irc;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	int val = cctrue(0) ? 0xff : 0x00;
	x_put_byte(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 12 (1/1) */
/* 2 0,0   */

/* Scc.B (d16,An) (T) */
void REGPARAM2 op_50e8_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	ipl_fetch_now();
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	int val = cctrue(0) ? 0xff : 0x00;
	x_put_byte(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 12 (2/1) */
/* 4 0,0   */

/* Scc.B (d8,An,Xn) (T) */
void REGPARAM2 op_50f0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_ce000_prefetch(4));
	do_cycles_ce000_internal(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	ipl_fetch_now();
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	int val = cctrue(0) ? 0xff : 0x00;
	x_put_byte(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (2/1) */
/* 4 4,0   */

/* Scc.B (xxx).W (T) */
void REGPARAM2 op_50f8_13_ff(uae_u32 opcode)
{
	OpcodeFamily = 59;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	ipl_fetch_now();
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	int val = cctrue(0) ? 0xff : 0x00;
	x_put_byte(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 12 (2/1) */
/* 4 0,0   */

/* Scc.B (xxx).L (T) */
void REGPARAM2 op_50f9_13_ff(uae_u32 opcode)
{
	OpcodeFamily = 59;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	srca |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	ipl_fetch_now();
	regs.ir = regs.irc;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	opcode = regs.ir;
	int val = cctrue(0) ? 0xff : 0x00;
	x_put_byte(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 16 (3/1) */
/* 6 0,0   */

/* SUBQ.B #<data>,Dn */
void REGPARAM2 op_5100_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 4;  
	uae_u32 src = srcreg;
	uae_s8 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 4 (1/0) */
/* 2 0,0   */

/* SUBQ.B #<data>,(An) */
void REGPARAM2 op_5110_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 12; 
	uae_u32 src = srcreg;
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_byte(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x0, newv, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 12 (2/1) */
/* 2 0,0   */

/* SUBQ.B #<data>,(An)+ */
void REGPARAM2 op_5118_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 12; 
	uae_u32 src = srcreg;
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
	uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_byte(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x0, newv, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 12 (2/1) */
/* 2 0,0   */

/* SUBQ.B #<data>,-(An) */
void REGPARAM2 op_5120_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 14; 
	uae_u32 src = srcreg;
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
	do_cycles_ce000_internal(2);
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, dstreg) = dsta;
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	m68k_areg(regs, dstreg) = dsta;
	uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_byte(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x0, newv, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 14 (2/1) */
/* 2 0,0   */

/* SUBQ.B #<data>,(d16,An) */
void REGPARAM2 op_5128_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 16; 
	uae_u32 src = srcreg;
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_byte(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x0, newv, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* SUBQ.B #<data>,(d8,An,Xn) */
void REGPARAM2 op_5130_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 18; 
	uae_u32 src = srcreg;
	uaecptr dsta;
	do_cycles_ce000_internal(2);
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_byte(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x0, newv, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 18 (3/1) */
/* 4 4,0   */

/* SUBQ.B #<data>,(xxx).W */
void REGPARAM2 op_5138_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	OpcodeFamily = 7;
	CurrentInstrCycles = 16; 
	uae_u32 src = srcreg;
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_byte(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x0, newv, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* SUBQ.B #<data>,(xxx).L */
void REGPARAM2 op_5139_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	OpcodeFamily = 7;
	CurrentInstrCycles = 20; 
	uae_u32 src = srcreg;
	uaecptr dsta;
	dsta = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	dsta |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_byte(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 0, 0x0, newv, 1);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 20 (4/1) */
/* 6 0,0   */

/* SUBQ.W #<data>,Dn */
void REGPARAM2 op_5140_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 4;  
	uae_u32 src = srcreg;
	uae_s16 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 4 (1/0) */
/* 2 0,0   */

/* SUBAQ.W #<data>,An */
void REGPARAM2 op_5148_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 8;
	CurrentInstrCycles = 8;  
	uae_u32 src = srcreg;
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = dst - src;
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		areg_68000_long_replace_low(dstreg, newv);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	do_cycles_ce000_internal(4);
	m68k_areg(regs, dstreg) = (newv);
	m68k_incpci(2);
	return;
}
/* 8 (1/0) */
/* 2 0,0   */

/* SUBQ.W #<data>,(An) */
void REGPARAM2 op_5150_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 12; 
	uae_u32 src = srcreg;
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	if (dsta & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dsta, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 dst = x_get_word(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_word(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x1, newv, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 12 (2/1) */
/* 2 0,0   */

/* SUBQ.W #<data>,(An)+ */
void REGPARAM2 op_5158_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 12; 
	uae_u32 src = srcreg;
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	if (dsta & 1) {
		m68k_areg(regs, dstreg) += 2 + 0;
		m68k_incpci(2);
		exception3_read_access(opcode, dsta, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 dst = x_get_word(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, dstreg) += 2 + 0;
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	m68k_areg(regs, dstreg) += 2;
	uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_word(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x1, newv, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 12 (2/1) */
/* 2 0,0   */

/* SUBQ.W #<data>,-(An) */
void REGPARAM2 op_5160_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 14; 
	uae_u32 src = srcreg;
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - 2;
	do_cycles_ce000_internal(2);
	if (dsta & 1) {
		m68k_areg(regs, dstreg) = dsta;
		m68k_incpci(2);
		exception3_read_access(opcode, dsta, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 dst = x_get_word(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, dstreg) = dsta;
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	m68k_areg(regs, dstreg) = dsta;
	uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_word(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x1, newv, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 14 (2/1) */
/* 2 0,0   */

/* SUBQ.W #<data>,(d16,An) */
void REGPARAM2 op_5168_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 16; 
	uae_u32 src = srcreg;
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dsta, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 dst = x_get_word(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_word(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, newv, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* SUBQ.W #<data>,(d8,An,Xn) */
void REGPARAM2 op_5170_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 18; 
	uae_u32 src = srcreg;
	uaecptr dsta;
	do_cycles_ce000_internal(2);
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dsta, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 dst = x_get_word(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_word(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, newv, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 18 (3/1) */
/* 4 4,0   */

/* SUBQ.W #<data>,(xxx).W */
void REGPARAM2 op_5178_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	OpcodeFamily = 7;
	CurrentInstrCycles = 16; 
	uae_u32 src = srcreg;
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, dsta, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 dst = x_get_word(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_word(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, newv, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* SUBQ.W #<data>,(xxx).L */
void REGPARAM2 op_5179_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	OpcodeFamily = 7;
	CurrentInstrCycles = 20; 
	uae_u32 src = srcreg;
	uaecptr dsta;
	dsta = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	dsta |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, dsta, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 dst = x_get_word(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_word(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 0, 0x1, newv, 1);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 20 (4/1) */
/* 6 0,0   */

/* SUBQ.L #<data>,Dn */
void REGPARAM2 op_5180_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 8;  
	uae_u32 src = srcreg;
	uae_s32 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		uae_s16 bnewv = (uae_s16)dst - (uae_s16)src;
		int bflgs = ((uae_s16)(src)) < 0;
		int bflgo = ((uae_s16)(dst)) < 0;
		int bflgn = bnewv < 0;
		ccr_68000_long_move_ae_LZN(bnewv);
		SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
		SET_XFLG(GET_CFLG());
		SET_VFLG((bflgs ^ bflgo) & (bflgn ^ bflgo));
		dreg_68000_long_replace_low(dstreg, bnewv);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	do_cycles_ce000_internal(4);
	m68k_dreg(regs, dstreg) = (newv);
	m68k_incpci(2);
	return;
}
/* 8 (1/0) */
/* 2 0,0   */

/* SUBAQ.L #<data>,An */
void REGPARAM2 op_5188_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 8;
	CurrentInstrCycles = 8;  
	uae_u32 src = srcreg;
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = dst - src;
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		areg_68000_long_replace_low(dstreg, newv);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	do_cycles_ce000_internal(4);
	m68k_areg(regs, dstreg) = (newv);
	m68k_incpci(2);
	return;
}
/* 8 (1/0) */
/* 2 0,0   */

/* SUBQ.L #<data>,(An) */
void REGPARAM2 op_5190_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 20; 
	uae_u32 src = srcreg;
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	if (dsta & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dsta, 2, 1);
		return;
	}
	uae_s32 dst = x_get_word(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	dst |= x_get_word(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return;
	}
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		uae_s16 bnewv = (uae_s16)dst - (uae_s16)src;
		int bflgs = ((uae_s16)(src)) < 0;
		int bflgo = ((uae_s16)(dst)) < 0;
		int bflgn = bnewv < 0;
		ccr_68000_long_move_ae_LZN(bnewv);
		SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
		SET_XFLG(GET_CFLG());
		SET_VFLG((bflgs ^ bflgo) & (bflgn ^ bflgo));
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	x_put_word(dsta + 2, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 2, 0x1, newv, 1);
		return;
	}
	x_put_word(dsta, newv >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x1, newv >> 16, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 20 (3/2) */
/* 2 0,0   */

/* SUBQ.L #<data>,(An)+ */
void REGPARAM2 op_5198_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 20; 
	uae_u32 src = srcreg;
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	if (dsta & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dsta, 2, 1);
		return;
	}
	uae_s32 dst = x_get_word(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	dst |= x_get_word(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return;
	}
	m68k_areg(regs, dstreg) += 4;
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		uae_s16 bnewv = (uae_s16)dst - (uae_s16)src;
		int bflgs = ((uae_s16)(src)) < 0;
		int bflgo = ((uae_s16)(dst)) < 0;
		int bflgn = bnewv < 0;
		ccr_68000_long_move_ae_LZN(bnewv);
		SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
		SET_XFLG(GET_CFLG());
		SET_VFLG((bflgs ^ bflgo) & (bflgn ^ bflgo));
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	x_put_word(dsta + 2, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 2, 0x1, newv, 1);
		return;
	}
	x_put_word(dsta, newv >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x1, newv >> 16, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 20 (3/2) */
/* 2 0,0   */

/* SUBQ.L #<data>,-(An) */
void REGPARAM2 op_51a0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 22; 
	uae_u32 src = srcreg;
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - 4;
	do_cycles_ce000_internal(2);
	if (dsta & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dsta, 2, 1);
		return;
	}
	uae_s32 dst = x_get_word(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	dst |= x_get_word(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, dstreg) = dsta;
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return;
	}
	m68k_areg(regs, dstreg) = dsta;
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		uae_s16 bnewv = (uae_s16)dst - (uae_s16)src;
		int bflgs = ((uae_s16)(src)) < 0;
		int bflgo = ((uae_s16)(dst)) < 0;
		int bflgn = bnewv < 0;
		ccr_68000_long_move_ae_LZN(bnewv);
		SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
		SET_XFLG(GET_CFLG());
		SET_VFLG((bflgs ^ bflgo) & (bflgn ^ bflgo));
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	x_put_word(dsta + 2, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 2, 0x1, newv, 1);
		return;
	}
	x_put_word(dsta, newv >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x1, newv >> 16, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 22 (3/2) */
/* 2 0,0   */

/* SUBQ.L #<data>,(d16,An) */
void REGPARAM2 op_51a8_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 24; 
	uae_u32 src = srcreg;
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dsta, 2, 1);
		return;
	}
	uae_s32 dst = x_get_word(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	dst |= x_get_word(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return;
	}
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		uae_s16 bnewv = (uae_s16)dst - (uae_s16)src;
		int bflgs = ((uae_s16)(src)) < 0;
		int bflgo = ((uae_s16)(dst)) < 0;
		int bflgn = bnewv < 0;
		ccr_68000_long_move_ae_LZN(bnewv);
		SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
		SET_XFLG(GET_CFLG());
		SET_VFLG((bflgs ^ bflgo) & (bflgn ^ bflgo));
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	x_put_word(dsta + 2, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 2, 0x1, newv, 1);
		return;
	}
	x_put_word(dsta, newv >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, newv >> 16, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 24 (4/2) */
/* 4 0,0   */

/* SUBQ.L #<data>,(d8,An,Xn) */
void REGPARAM2 op_51b0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 26; 
	uae_u32 src = srcreg;
	uaecptr dsta;
	do_cycles_ce000_internal(2);
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dsta, 2, 1);
		return;
	}
	uae_s32 dst = x_get_word(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	dst |= x_get_word(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return;
	}
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		uae_s16 bnewv = (uae_s16)dst - (uae_s16)src;
		int bflgs = ((uae_s16)(src)) < 0;
		int bflgo = ((uae_s16)(dst)) < 0;
		int bflgn = bnewv < 0;
		ccr_68000_long_move_ae_LZN(bnewv);
		SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
		SET_XFLG(GET_CFLG());
		SET_VFLG((bflgs ^ bflgo) & (bflgn ^ bflgo));
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	x_put_word(dsta + 2, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 2, 0x1, newv, 1);
		return;
	}
	x_put_word(dsta, newv >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, newv >> 16, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 26 (4/2) */
/* 4 4,0   */

/* SUBQ.L #<data>,(xxx).W */
void REGPARAM2 op_51b8_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	OpcodeFamily = 7;
	CurrentInstrCycles = 24; 
	uae_u32 src = srcreg;
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, dsta, 2, 1);
		return;
	}
	uae_s32 dst = x_get_word(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	dst |= x_get_word(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return;
	}
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		uae_s16 bnewv = (uae_s16)dst - (uae_s16)src;
		int bflgs = ((uae_s16)(src)) < 0;
		int bflgo = ((uae_s16)(dst)) < 0;
		int bflgn = bnewv < 0;
		ccr_68000_long_move_ae_LZN(bnewv);
		SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
		SET_XFLG(GET_CFLG());
		SET_VFLG((bflgs ^ bflgo) & (bflgn ^ bflgo));
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	x_put_word(dsta + 2, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 2, 0x1, newv, 1);
		return;
	}
	x_put_word(dsta, newv >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, newv >> 16, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 24 (4/2) */
/* 4 0,0   */

/* SUBQ.L #<data>,(xxx).L */
void REGPARAM2 op_51b9_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	OpcodeFamily = 7;
	CurrentInstrCycles = 28; 
	uae_u32 src = srcreg;
	uaecptr dsta;
	dsta = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	dsta |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, dsta, 2, 1);
		return;
	}
	uae_s32 dst = x_get_word(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	dst |= x_get_word(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return;
	}
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		uae_s16 bnewv = (uae_s16)dst - (uae_s16)src;
		int bflgs = ((uae_s16)(src)) < 0;
		int bflgo = ((uae_s16)(dst)) < 0;
		int bflgn = bnewv < 0;
		ccr_68000_long_move_ae_LZN(bnewv);
		SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
		SET_XFLG(GET_CFLG());
		SET_VFLG((bflgs ^ bflgo) & (bflgn ^ bflgo));
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	x_put_word(dsta + 2, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 2, 0x1, newv, 1);
		return;
	}
	x_put_word(dsta, newv >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 0, 0x1, newv >> 16, 1);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 28 (5/2) */
/* 6 0,0   */

/* Scc.B Dn (F) */
void REGPARAM2 op_51c0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 4;  
	int val = cctrue(1) ? 0xff : 0x00;
	int cycles = val ? 2 : 0;
	if (!val) {
		m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff);
	}
	regs.ir = regs.irc;
	if (!val)
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if(!val && regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff);
	if (cycles > 0) do_cycles_ce000_internal(cycles);
	m68k_incpci(2);
	return;
}
/* 4+ (1/0) */
/* 2 0,0   */

/* DBcc.W Dn,#<data>.W (F) */
void REGPARAM2 op_51c8_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 58;
	CurrentInstrCycles = 10; 
	int pcadjust = -2;
	uae_s16 src = m68k_dreg(regs, srcreg);
	uae_s16 offs = regs.irc;
	int was_loop_mode = regs.loop_mode;
	regs.loop_mode = 0;
	uaecptr oldpc = m68k_getpci();
	do_cycles_ce000_internal(2);
	if (!cctrue(1)) {
		m68k_incpci((uae_s32)offs + 2);
		if (offs & 1) {
			get_word_ce000_prefetch(-1);
			exception3_read_prefetch(opcode, m68k_getpci());
			return;
		}
		if(offs == -4 && !regs.t1 && loop_mode_table[regs.ird]) {
			if(!was_loop_mode) {
				uae_u16 irc = regs.irc;
				get_word_ce000_prefetch(0);
				if(hardware_bus_error) {
					int pcoffset = 0;
					exception2_fetch_opcode(opcode, 0, 0);
					return;
				}
				get_word_ce000_prefetch(2);
				if(hardware_bus_error) {
					int pcoffset = 0;
					exception2_fetch_opcode(opcode, 2, 0);
					return;
				}
				regs.irc = irc;
			} else {
				do_cycles_ce000_internal(2);
			}
			regs.loop_mode = 1;
			src = m68k_dreg(regs, srcreg);
			m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
			if (src) {
				loop_mode_table[regs.ird](regs.ird);
				 // quick exit if condition false and count expired
				if (!cctrue(1) && (m68k_dreg(regs, srcreg) & 0xffff) == 0) {
					m68k_dreg(regs, srcreg) |= 0xffff;
					 // loop exit: add possible extra cycle(s)
					if(regs.loop_mode >> 16) {
						do_cycles_ce000_internal(regs.loop_mode >> 16);
					}
					regs.loop_mode = 0;
					m68k_setpci_j(oldpc + 4);
					get_word_ce000_prefetch(0);
					if(hardware_bus_error) {
						int pcoffset = 0;
						m68k_setpci_j(oldpc + 2);
						exception2_fetch_opcode(opcode, 0, pcoffset);
						return;
					}
					regs.ir = regs.irc;
					opcode = regs.ir;
					ipl_fetch_next();
					get_word_ce000_prefetch(2);
					if(hardware_bus_error) {
						int pcoffset = 0;
						m68k_setpci_j(oldpc + 2);
						exception2_fetch_opcode(opcode, 2, pcoffset);
						return;
					}
					return;
				}
				 // loop continue: add possible extra cycle(s)
				if(regs.loop_mode & 0xfffe) {
					do_cycles_ce000_internal(regs.loop_mode & 0xfffe);
				}
				m68k_setpci_j(oldpc);
				ipl_fetch_now();
				return;
			}
			regs.loop_mode = 0;
			m68k_setpci_j(oldpc + 4);
			get_word_ce000_prefetch(0);
			if(hardware_bus_error) {
				int pcoffset = 0;
				m68k_setpci_j(oldpc + 2);
				exception2_fetch_opcode(opcode, 0, pcoffset);
				return;
			}
			regs.ir = regs.irc;
			opcode = regs.ir;
			ipl_fetch_next();
			get_word_ce000_prefetch(2);
			if(hardware_bus_error) {
				int pcoffset = 0;
				m68k_setpci_j(oldpc + 2);
				exception2_fetch_opcode(opcode, 2, pcoffset);
				return;
			}
			return;
		}
		get_word_ce000_prefetch(0);
		if(hardware_bus_error) {
			int pcoffset = 0;
			pcoffset = oldpc - m68k_getpci() + 4;
			exception2_fetch_opcode(opcode, 0, pcoffset);
			return;
		}
		if (src) {
			m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
			regs.ir = regs.irc;
			opcode = regs.ir;
			ipl_fetch_next();
			get_word_ce000_prefetch(2);
			if(hardware_bus_error) {
				int pcoffset = 0;
				exception2_fetch_opcode(opcode, 2, 0);
				return;
			}
			return;
		}
		do_cycles_ce000_internal(2);
		pcadjust = 0;
	}
	m68k_setpci_j(oldpc + 4);
	get_word_ce000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		pcoffset += pcadjust;
		exception2_fetch_opcode(opcode, 0, pcoffset);
		return;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	if (!cctrue(1)) {
		m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
	}
	ipl_fetch_next();
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 10 (2/0) */
/* 4 0,0 B */

/* Scc.B (An) (F) */
void REGPARAM2 op_51d0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 10; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	do_cycles_ce000_internal(2);
	ipl_fetch_now();
	regs.ir = regs.irc;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	int val = cctrue(1) ? 0xff : 0x00;
	x_put_byte(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 10 (1/1) */
/* 2 0,0   */

/* Scc.B (An)+ (F) */
void REGPARAM2 op_51d8_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	do_cycles_ce000_internal(4);
	ipl_fetch_now();
	m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
	regs.ir = regs.irc;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	int val = cctrue(1) ? 0xff : 0x00;
	x_put_byte(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 12 (1/1) */
/* 2 0,0   */

/* Scc.B -(An) (F) */
void REGPARAM2 op_51e0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
	do_cycles_ce000_internal(4);
	ipl_fetch_now();
	m68k_areg(regs, srcreg) = srca;
	regs.ir = regs.irc;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	int val = cctrue(1) ? 0xff : 0x00;
	x_put_byte(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 12 (1/1) */
/* 2 0,0   */

/* Scc.B (d16,An) (F) */
void REGPARAM2 op_51e8_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	ipl_fetch_now();
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	int val = cctrue(1) ? 0xff : 0x00;
	x_put_byte(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 12 (2/1) */
/* 4 0,0   */

/* Scc.B (d8,An,Xn) (F) */
void REGPARAM2 op_51f0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_ce000_prefetch(4));
	do_cycles_ce000_internal(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	ipl_fetch_now();
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	int val = cctrue(1) ? 0xff : 0x00;
	x_put_byte(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (2/1) */
/* 4 4,0   */

/* Scc.B (xxx).W (F) */
void REGPARAM2 op_51f8_13_ff(uae_u32 opcode)
{
	OpcodeFamily = 59;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	ipl_fetch_now();
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	int val = cctrue(1) ? 0xff : 0x00;
	x_put_byte(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 12 (2/1) */
/* 4 0,0   */

/* Scc.B (xxx).L (F) */
void REGPARAM2 op_51f9_13_ff(uae_u32 opcode)
{
	OpcodeFamily = 59;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	srca |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	ipl_fetch_now();
	regs.ir = regs.irc;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	opcode = regs.ir;
	int val = cctrue(1) ? 0xff : 0x00;
	x_put_byte(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 16 (3/1) */
/* 6 0,0   */

/* Scc.B Dn (HI) */
void REGPARAM2 op_52c0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 4;  
	int val = cctrue(2) ? 0xff : 0x00;
	int cycles = val ? 2 : 0;
	if (!val) {
		m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff);
	}
	regs.ir = regs.irc;
	if (!val)
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if(!val && regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff);
	if (cycles > 0) do_cycles_ce000_internal(cycles);
	m68k_incpci(2);
	return;
}
/* 4+ (1/0) */
/* 2 0,0   */

/* DBcc.W Dn,#<data>.W (HI) */
void REGPARAM2 op_52c8_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 58;
	CurrentInstrCycles = 10; 
	int pcadjust = -2;
	uae_s16 src = m68k_dreg(regs, srcreg);
	uae_s16 offs = regs.irc;
	int was_loop_mode = regs.loop_mode;
	regs.loop_mode = 0;
	uaecptr oldpc = m68k_getpci();
	do_cycles_ce000_internal(2);
	if (!cctrue(2)) {
		m68k_incpci((uae_s32)offs + 2);
		if (offs & 1) {
			get_word_ce000_prefetch(-1);
			exception3_read_prefetch(opcode, m68k_getpci());
			return;
		}
		if(offs == -4 && !regs.t1 && loop_mode_table[regs.ird]) {
			if(!was_loop_mode) {
				uae_u16 irc = regs.irc;
				get_word_ce000_prefetch(0);
				if(hardware_bus_error) {
					int pcoffset = 0;
					exception2_fetch_opcode(opcode, 0, 0);
					return;
				}
				get_word_ce000_prefetch(2);
				if(hardware_bus_error) {
					int pcoffset = 0;
					exception2_fetch_opcode(opcode, 2, 0);
					return;
				}
				regs.irc = irc;
			} else {
				do_cycles_ce000_internal(2);
			}
			regs.loop_mode = 1;
			src = m68k_dreg(regs, srcreg);
			m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
			if (src) {
				loop_mode_table[regs.ird](regs.ird);
				 // quick exit if condition false and count expired
				if (!cctrue(2) && (m68k_dreg(regs, srcreg) & 0xffff) == 0) {
					m68k_dreg(regs, srcreg) |= 0xffff;
					 // loop exit: add possible extra cycle(s)
					if(regs.loop_mode >> 16) {
						do_cycles_ce000_internal(regs.loop_mode >> 16);
					}
					regs.loop_mode = 0;
					m68k_setpci_j(oldpc + 4);
					get_word_ce000_prefetch(0);
					if(hardware_bus_error) {
						int pcoffset = 0;
						m68k_setpci_j(oldpc + 2);
						exception2_fetch_opcode(opcode, 0, pcoffset);
						return;
					}
					regs.ir = regs.irc;
					opcode = regs.ir;
					ipl_fetch_next();
					get_word_ce000_prefetch(2);
					if(hardware_bus_error) {
						int pcoffset = 0;
						m68k_setpci_j(oldpc + 2);
						exception2_fetch_opcode(opcode, 2, pcoffset);
						return;
					}
					return;
				}
				 // loop continue: add possible extra cycle(s)
				if(regs.loop_mode & 0xfffe) {
					do_cycles_ce000_internal(regs.loop_mode & 0xfffe);
				}
				m68k_setpci_j(oldpc);
				ipl_fetch_now();
				return;
			}
			regs.loop_mode = 0;
			m68k_setpci_j(oldpc + 4);
			get_word_ce000_prefetch(0);
			if(hardware_bus_error) {
				int pcoffset = 0;
				m68k_setpci_j(oldpc + 2);
				exception2_fetch_opcode(opcode, 0, pcoffset);
				return;
			}
			regs.ir = regs.irc;
			opcode = regs.ir;
			ipl_fetch_next();
			get_word_ce000_prefetch(2);
			if(hardware_bus_error) {
				int pcoffset = 0;
				m68k_setpci_j(oldpc + 2);
				exception2_fetch_opcode(opcode, 2, pcoffset);
				return;
			}
			return;
		}
		get_word_ce000_prefetch(0);
		if(hardware_bus_error) {
			int pcoffset = 0;
			pcoffset = oldpc - m68k_getpci() + 4;
			exception2_fetch_opcode(opcode, 0, pcoffset);
			return;
		}
		if (src) {
			m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
			regs.ir = regs.irc;
			opcode = regs.ir;
			ipl_fetch_next();
			get_word_ce000_prefetch(2);
			if(hardware_bus_error) {
				int pcoffset = 0;
				exception2_fetch_opcode(opcode, 2, 0);
				return;
			}
			return;
		}
		do_cycles_ce000_internal(2);
		pcadjust = 0;
	}
	m68k_setpci_j(oldpc + 4);
	get_word_ce000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		pcoffset += pcadjust;
		exception2_fetch_opcode(opcode, 0, pcoffset);
		return;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	if (!cctrue(2)) {
		m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
	}
	ipl_fetch_next();
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 10 (2/0) */
/* 4 0,0 B */

/* Scc.B (An) (HI) */
void REGPARAM2 op_52d0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 10; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	do_cycles_ce000_internal(2);
	ipl_fetch_now();
	regs.ir = regs.irc;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	int val = cctrue(2) ? 0xff : 0x00;
	x_put_byte(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 10 (1/1) */
/* 2 0,0   */

/* Scc.B (An)+ (HI) */
void REGPARAM2 op_52d8_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	do_cycles_ce000_internal(4);
	ipl_fetch_now();
	m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
	regs.ir = regs.irc;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	int val = cctrue(2) ? 0xff : 0x00;
	x_put_byte(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 12 (1/1) */
/* 2 0,0   */

/* Scc.B -(An) (HI) */
void REGPARAM2 op_52e0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
	do_cycles_ce000_internal(4);
	ipl_fetch_now();
	m68k_areg(regs, srcreg) = srca;
	regs.ir = regs.irc;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	int val = cctrue(2) ? 0xff : 0x00;
	x_put_byte(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 12 (1/1) */
/* 2 0,0   */

/* Scc.B (d16,An) (HI) */
void REGPARAM2 op_52e8_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	ipl_fetch_now();
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	int val = cctrue(2) ? 0xff : 0x00;
	x_put_byte(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 12 (2/1) */
/* 4 0,0   */

/* Scc.B (d8,An,Xn) (HI) */
void REGPARAM2 op_52f0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_ce000_prefetch(4));
	do_cycles_ce000_internal(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	ipl_fetch_now();
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	int val = cctrue(2) ? 0xff : 0x00;
	x_put_byte(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (2/1) */
/* 4 4,0   */

/* Scc.B (xxx).W (HI) */
void REGPARAM2 op_52f8_13_ff(uae_u32 opcode)
{
	OpcodeFamily = 59;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	ipl_fetch_now();
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	int val = cctrue(2) ? 0xff : 0x00;
	x_put_byte(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 12 (2/1) */
/* 4 0,0   */

/* Scc.B (xxx).L (HI) */
void REGPARAM2 op_52f9_13_ff(uae_u32 opcode)
{
	OpcodeFamily = 59;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	srca |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	ipl_fetch_now();
	regs.ir = regs.irc;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	opcode = regs.ir;
	int val = cctrue(2) ? 0xff : 0x00;
	x_put_byte(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 16 (3/1) */
/* 6 0,0   */

/* Scc.B Dn (LS) */
void REGPARAM2 op_53c0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 4;  
	int val = cctrue(3) ? 0xff : 0x00;
	int cycles = val ? 2 : 0;
	if (!val) {
		m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff);
	}
	regs.ir = regs.irc;
	if (!val)
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if(!val && regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff);
	if (cycles > 0) do_cycles_ce000_internal(cycles);
	m68k_incpci(2);
	return;
}
/* 4+ (1/0) */
/* 2 0,0   */

/* DBcc.W Dn,#<data>.W (LS) */
void REGPARAM2 op_53c8_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 58;
	CurrentInstrCycles = 10; 
	int pcadjust = -2;
	uae_s16 src = m68k_dreg(regs, srcreg);
	uae_s16 offs = regs.irc;
	int was_loop_mode = regs.loop_mode;
	regs.loop_mode = 0;
	uaecptr oldpc = m68k_getpci();
	do_cycles_ce000_internal(2);
	if (!cctrue(3)) {
		m68k_incpci((uae_s32)offs + 2);
		if (offs & 1) {
			get_word_ce000_prefetch(-1);
			exception3_read_prefetch(opcode, m68k_getpci());
			return;
		}
		if(offs == -4 && !regs.t1 && loop_mode_table[regs.ird]) {
			if(!was_loop_mode) {
				uae_u16 irc = regs.irc;
				get_word_ce000_prefetch(0);
				if(hardware_bus_error) {
					int pcoffset = 0;
					exception2_fetch_opcode(opcode, 0, 0);
					return;
				}
				get_word_ce000_prefetch(2);
				if(hardware_bus_error) {
					int pcoffset = 0;
					exception2_fetch_opcode(opcode, 2, 0);
					return;
				}
				regs.irc = irc;
			} else {
				do_cycles_ce000_internal(2);
			}
			regs.loop_mode = 1;
			src = m68k_dreg(regs, srcreg);
			m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
			if (src) {
				loop_mode_table[regs.ird](regs.ird);
				 // quick exit if condition false and count expired
				if (!cctrue(3) && (m68k_dreg(regs, srcreg) & 0xffff) == 0) {
					m68k_dreg(regs, srcreg) |= 0xffff;
					 // loop exit: add possible extra cycle(s)
					if(regs.loop_mode >> 16) {
						do_cycles_ce000_internal(regs.loop_mode >> 16);
					}
					regs.loop_mode = 0;
					m68k_setpci_j(oldpc + 4);
					get_word_ce000_prefetch(0);
					if(hardware_bus_error) {
						int pcoffset = 0;
						m68k_setpci_j(oldpc + 2);
						exception2_fetch_opcode(opcode, 0, pcoffset);
						return;
					}
					regs.ir = regs.irc;
					opcode = regs.ir;
					ipl_fetch_next();
					get_word_ce000_prefetch(2);
					if(hardware_bus_error) {
						int pcoffset = 0;
						m68k_setpci_j(oldpc + 2);
						exception2_fetch_opcode(opcode, 2, pcoffset);
						return;
					}
					return;
				}
				 // loop continue: add possible extra cycle(s)
				if(regs.loop_mode & 0xfffe) {
					do_cycles_ce000_internal(regs.loop_mode & 0xfffe);
				}
				m68k_setpci_j(oldpc);
				ipl_fetch_now();
				return;
			}
			regs.loop_mode = 0;
			m68k_setpci_j(oldpc + 4);
			get_word_ce000_prefetch(0);
			if(hardware_bus_error) {
				int pcoffset = 0;
				m68k_setpci_j(oldpc + 2);
				exception2_fetch_opcode(opcode, 0, pcoffset);
				return;
			}
			regs.ir = regs.irc;
			opcode = regs.ir;
			ipl_fetch_next();
			get_word_ce000_prefetch(2);
			if(hardware_bus_error) {
				int pcoffset = 0;
				m68k_setpci_j(oldpc + 2);
				exception2_fetch_opcode(opcode, 2, pcoffset);
				return;
			}
			return;
		}
		get_word_ce000_prefetch(0);
		if(hardware_bus_error) {
			int pcoffset = 0;
			pcoffset = oldpc - m68k_getpci() + 4;
			exception2_fetch_opcode(opcode, 0, pcoffset);
			return;
		}
		if (src) {
			m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
			regs.ir = regs.irc;
			opcode = regs.ir;
			ipl_fetch_next();
			get_word_ce000_prefetch(2);
			if(hardware_bus_error) {
				int pcoffset = 0;
				exception2_fetch_opcode(opcode, 2, 0);
				return;
			}
			return;
		}
		do_cycles_ce000_internal(2);
		pcadjust = 0;
	}
	m68k_setpci_j(oldpc + 4);
	get_word_ce000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		pcoffset += pcadjust;
		exception2_fetch_opcode(opcode, 0, pcoffset);
		return;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	if (!cctrue(3)) {
		m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
	}
	ipl_fetch_next();
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 10 (2/0) */
/* 4 0,0 B */

/* Scc.B (An) (LS) */
void REGPARAM2 op_53d0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 10; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	do_cycles_ce000_internal(2);
	ipl_fetch_now();
	regs.ir = regs.irc;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	int val = cctrue(3) ? 0xff : 0x00;
	x_put_byte(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 10 (1/1) */
/* 2 0,0   */

/* Scc.B (An)+ (LS) */
void REGPARAM2 op_53d8_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	do_cycles_ce000_internal(4);
	ipl_fetch_now();
	m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
	regs.ir = regs.irc;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	int val = cctrue(3) ? 0xff : 0x00;
	x_put_byte(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 12 (1/1) */
/* 2 0,0   */

/* Scc.B -(An) (LS) */
void REGPARAM2 op_53e0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
	do_cycles_ce000_internal(4);
	ipl_fetch_now();
	m68k_areg(regs, srcreg) = srca;
	regs.ir = regs.irc;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	int val = cctrue(3) ? 0xff : 0x00;
	x_put_byte(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 12 (1/1) */
/* 2 0,0   */

/* Scc.B (d16,An) (LS) */
void REGPARAM2 op_53e8_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	ipl_fetch_now();
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	int val = cctrue(3) ? 0xff : 0x00;
	x_put_byte(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 12 (2/1) */
/* 4 0,0   */

/* Scc.B (d8,An,Xn) (LS) */
void REGPARAM2 op_53f0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_ce000_prefetch(4));
	do_cycles_ce000_internal(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	ipl_fetch_now();
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	int val = cctrue(3) ? 0xff : 0x00;
	x_put_byte(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (2/1) */
/* 4 4,0   */

/* Scc.B (xxx).W (LS) */
void REGPARAM2 op_53f8_13_ff(uae_u32 opcode)
{
	OpcodeFamily = 59;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	ipl_fetch_now();
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	int val = cctrue(3) ? 0xff : 0x00;
	x_put_byte(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 12 (2/1) */
/* 4 0,0   */

/* Scc.B (xxx).L (LS) */
void REGPARAM2 op_53f9_13_ff(uae_u32 opcode)
{
	OpcodeFamily = 59;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	srca |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	ipl_fetch_now();
	regs.ir = regs.irc;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	opcode = regs.ir;
	int val = cctrue(3) ? 0xff : 0x00;
	x_put_byte(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 16 (3/1) */
/* 6 0,0   */

/* Scc.B Dn (CC) */
void REGPARAM2 op_54c0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 4;  
	int val = cctrue(4) ? 0xff : 0x00;
	int cycles = val ? 2 : 0;
	if (!val) {
		m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff);
	}
	regs.ir = regs.irc;
	if (!val)
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if(!val && regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff);
	if (cycles > 0) do_cycles_ce000_internal(cycles);
	m68k_incpci(2);
	return;
}
/* 4+ (1/0) */
/* 2 0,0   */

/* DBcc.W Dn,#<data>.W (CC) */
void REGPARAM2 op_54c8_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 58;
	CurrentInstrCycles = 10; 
	int pcadjust = -2;
	uae_s16 src = m68k_dreg(regs, srcreg);
	uae_s16 offs = regs.irc;
	int was_loop_mode = regs.loop_mode;
	regs.loop_mode = 0;
	uaecptr oldpc = m68k_getpci();
	do_cycles_ce000_internal(2);
	if (!cctrue(4)) {
		m68k_incpci((uae_s32)offs + 2);
		if (offs & 1) {
			get_word_ce000_prefetch(-1);
			exception3_read_prefetch(opcode, m68k_getpci());
			return;
		}
		if(offs == -4 && !regs.t1 && loop_mode_table[regs.ird]) {
			if(!was_loop_mode) {
				uae_u16 irc = regs.irc;
				get_word_ce000_prefetch(0);
				if(hardware_bus_error) {
					int pcoffset = 0;
					exception2_fetch_opcode(opcode, 0, 0);
					return;
				}
				get_word_ce000_prefetch(2);
				if(hardware_bus_error) {
					int pcoffset = 0;
					exception2_fetch_opcode(opcode, 2, 0);
					return;
				}
				regs.irc = irc;
			} else {
				do_cycles_ce000_internal(2);
			}
			regs.loop_mode = 1;
			src = m68k_dreg(regs, srcreg);
			m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
			if (src) {
				loop_mode_table[regs.ird](regs.ird);
				 // quick exit if condition false and count expired
				if (!cctrue(4) && (m68k_dreg(regs, srcreg) & 0xffff) == 0) {
					m68k_dreg(regs, srcreg) |= 0xffff;
					 // loop exit: add possible extra cycle(s)
					if(regs.loop_mode >> 16) {
						do_cycles_ce000_internal(regs.loop_mode >> 16);
					}
					regs.loop_mode = 0;
					m68k_setpci_j(oldpc + 4);
					get_word_ce000_prefetch(0);
					if(hardware_bus_error) {
						int pcoffset = 0;
						m68k_setpci_j(oldpc + 2);
						exception2_fetch_opcode(opcode, 0, pcoffset);
						return;
					}
					regs.ir = regs.irc;
					opcode = regs.ir;
					ipl_fetch_next();
					get_word_ce000_prefetch(2);
					if(hardware_bus_error) {
						int pcoffset = 0;
						m68k_setpci_j(oldpc + 2);
						exception2_fetch_opcode(opcode, 2, pcoffset);
						return;
					}
					return;
				}
				 // loop continue: add possible extra cycle(s)
				if(regs.loop_mode & 0xfffe) {
					do_cycles_ce000_internal(regs.loop_mode & 0xfffe);
				}
				m68k_setpci_j(oldpc);
				ipl_fetch_now();
				return;
			}
			regs.loop_mode = 0;
			m68k_setpci_j(oldpc + 4);
			get_word_ce000_prefetch(0);
			if(hardware_bus_error) {
				int pcoffset = 0;
				m68k_setpci_j(oldpc + 2);
				exception2_fetch_opcode(opcode, 0, pcoffset);
				return;
			}
			regs.ir = regs.irc;
			opcode = regs.ir;
			ipl_fetch_next();
			get_word_ce000_prefetch(2);
			if(hardware_bus_error) {
				int pcoffset = 0;
				m68k_setpci_j(oldpc + 2);
				exception2_fetch_opcode(opcode, 2, pcoffset);
				return;
			}
			return;
		}
		get_word_ce000_prefetch(0);
		if(hardware_bus_error) {
			int pcoffset = 0;
			pcoffset = oldpc - m68k_getpci() + 4;
			exception2_fetch_opcode(opcode, 0, pcoffset);
			return;
		}
		if (src) {
			m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
			regs.ir = regs.irc;
			opcode = regs.ir;
			ipl_fetch_next();
			get_word_ce000_prefetch(2);
			if(hardware_bus_error) {
				int pcoffset = 0;
				exception2_fetch_opcode(opcode, 2, 0);
				return;
			}
			return;
		}
		do_cycles_ce000_internal(2);
		pcadjust = 0;
	}
	m68k_setpci_j(oldpc + 4);
	get_word_ce000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		pcoffset += pcadjust;
		exception2_fetch_opcode(opcode, 0, pcoffset);
		return;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	if (!cctrue(4)) {
		m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
	}
	ipl_fetch_next();
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 10 (2/0) */
/* 4 0,0 B */

/* Scc.B (An) (CC) */
void REGPARAM2 op_54d0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 10; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	do_cycles_ce000_internal(2);
	ipl_fetch_now();
	regs.ir = regs.irc;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	int val = cctrue(4) ? 0xff : 0x00;
	x_put_byte(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 10 (1/1) */
/* 2 0,0   */

/* Scc.B (An)+ (CC) */
void REGPARAM2 op_54d8_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	do_cycles_ce000_internal(4);
	ipl_fetch_now();
	m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
	regs.ir = regs.irc;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	int val = cctrue(4) ? 0xff : 0x00;
	x_put_byte(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 12 (1/1) */
/* 2 0,0   */

/* Scc.B -(An) (CC) */
void REGPARAM2 op_54e0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
	do_cycles_ce000_internal(4);
	ipl_fetch_now();
	m68k_areg(regs, srcreg) = srca;
	regs.ir = regs.irc;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	int val = cctrue(4) ? 0xff : 0x00;
	x_put_byte(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 12 (1/1) */
/* 2 0,0   */

/* Scc.B (d16,An) (CC) */
void REGPARAM2 op_54e8_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	ipl_fetch_now();
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	int val = cctrue(4) ? 0xff : 0x00;
	x_put_byte(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 12 (2/1) */
/* 4 0,0   */

/* Scc.B (d8,An,Xn) (CC) */
void REGPARAM2 op_54f0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_ce000_prefetch(4));
	do_cycles_ce000_internal(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	ipl_fetch_now();
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	int val = cctrue(4) ? 0xff : 0x00;
	x_put_byte(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (2/1) */
/* 4 4,0   */

/* Scc.B (xxx).W (CC) */
void REGPARAM2 op_54f8_13_ff(uae_u32 opcode)
{
	OpcodeFamily = 59;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	ipl_fetch_now();
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	int val = cctrue(4) ? 0xff : 0x00;
	x_put_byte(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 12 (2/1) */
/* 4 0,0   */

/* Scc.B (xxx).L (CC) */
void REGPARAM2 op_54f9_13_ff(uae_u32 opcode)
{
	OpcodeFamily = 59;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	srca |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	ipl_fetch_now();
	regs.ir = regs.irc;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	opcode = regs.ir;
	int val = cctrue(4) ? 0xff : 0x00;
	x_put_byte(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 16 (3/1) */
/* 6 0,0   */

/* Scc.B Dn (CS) */
void REGPARAM2 op_55c0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 4;  
	int val = cctrue(5) ? 0xff : 0x00;
	int cycles = val ? 2 : 0;
	if (!val) {
		m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff);
	}
	regs.ir = regs.irc;
	if (!val)
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if(!val && regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff);
	if (cycles > 0) do_cycles_ce000_internal(cycles);
	m68k_incpci(2);
	return;
}
/* 4+ (1/0) */
/* 2 0,0   */

/* DBcc.W Dn,#<data>.W (CS) */
void REGPARAM2 op_55c8_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 58;
	CurrentInstrCycles = 10; 
	int pcadjust = -2;
	uae_s16 src = m68k_dreg(regs, srcreg);
	uae_s16 offs = regs.irc;
	int was_loop_mode = regs.loop_mode;
	regs.loop_mode = 0;
	uaecptr oldpc = m68k_getpci();
	do_cycles_ce000_internal(2);
	if (!cctrue(5)) {
		m68k_incpci((uae_s32)offs + 2);
		if (offs & 1) {
			get_word_ce000_prefetch(-1);
			exception3_read_prefetch(opcode, m68k_getpci());
			return;
		}
		if(offs == -4 && !regs.t1 && loop_mode_table[regs.ird]) {
			if(!was_loop_mode) {
				uae_u16 irc = regs.irc;
				get_word_ce000_prefetch(0);
				if(hardware_bus_error) {
					int pcoffset = 0;
					exception2_fetch_opcode(opcode, 0, 0);
					return;
				}
				get_word_ce000_prefetch(2);
				if(hardware_bus_error) {
					int pcoffset = 0;
					exception2_fetch_opcode(opcode, 2, 0);
					return;
				}
				regs.irc = irc;
			} else {
				do_cycles_ce000_internal(2);
			}
			regs.loop_mode = 1;
			src = m68k_dreg(regs, srcreg);
			m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
			if (src) {
				loop_mode_table[regs.ird](regs.ird);
				 // quick exit if condition false and count expired
				if (!cctrue(5) && (m68k_dreg(regs, srcreg) & 0xffff) == 0) {
					m68k_dreg(regs, srcreg) |= 0xffff;
					 // loop exit: add possible extra cycle(s)
					if(regs.loop_mode >> 16) {
						do_cycles_ce000_internal(regs.loop_mode >> 16);
					}
					regs.loop_mode = 0;
					m68k_setpci_j(oldpc + 4);
					get_word_ce000_prefetch(0);
					if(hardware_bus_error) {
						int pcoffset = 0;
						m68k_setpci_j(oldpc + 2);
						exception2_fetch_opcode(opcode, 0, pcoffset);
						return;
					}
					regs.ir = regs.irc;
					opcode = regs.ir;
					ipl_fetch_next();
					get_word_ce000_prefetch(2);
					if(hardware_bus_error) {
						int pcoffset = 0;
						m68k_setpci_j(oldpc + 2);
						exception2_fetch_opcode(opcode, 2, pcoffset);
						return;
					}
					return;
				}
				 // loop continue: add possible extra cycle(s)
				if(regs.loop_mode & 0xfffe) {
					do_cycles_ce000_internal(regs.loop_mode & 0xfffe);
				}
				m68k_setpci_j(oldpc);
				ipl_fetch_now();
				return;
			}
			regs.loop_mode = 0;
			m68k_setpci_j(oldpc + 4);
			get_word_ce000_prefetch(0);
			if(hardware_bus_error) {
				int pcoffset = 0;
				m68k_setpci_j(oldpc + 2);
				exception2_fetch_opcode(opcode, 0, pcoffset);
				return;
			}
			regs.ir = regs.irc;
			opcode = regs.ir;
			ipl_fetch_next();
			get_word_ce000_prefetch(2);
			if(hardware_bus_error) {
				int pcoffset = 0;
				m68k_setpci_j(oldpc + 2);
				exception2_fetch_opcode(opcode, 2, pcoffset);
				return;
			}
			return;
		}
		get_word_ce000_prefetch(0);
		if(hardware_bus_error) {
			int pcoffset = 0;
			pcoffset = oldpc - m68k_getpci() + 4;
			exception2_fetch_opcode(opcode, 0, pcoffset);
			return;
		}
		if (src) {
			m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
			regs.ir = regs.irc;
			opcode = regs.ir;
			ipl_fetch_next();
			get_word_ce000_prefetch(2);
			if(hardware_bus_error) {
				int pcoffset = 0;
				exception2_fetch_opcode(opcode, 2, 0);
				return;
			}
			return;
		}
		do_cycles_ce000_internal(2);
		pcadjust = 0;
	}
	m68k_setpci_j(oldpc + 4);
	get_word_ce000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		pcoffset += pcadjust;
		exception2_fetch_opcode(opcode, 0, pcoffset);
		return;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	if (!cctrue(5)) {
		m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
	}
	ipl_fetch_next();
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 10 (2/0) */
/* 4 0,0 B */

/* Scc.B (An) (CS) */
void REGPARAM2 op_55d0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 10; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	do_cycles_ce000_internal(2);
	ipl_fetch_now();
	regs.ir = regs.irc;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	int val = cctrue(5) ? 0xff : 0x00;
	x_put_byte(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 10 (1/1) */
/* 2 0,0   */

/* Scc.B (An)+ (CS) */
void REGPARAM2 op_55d8_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	do_cycles_ce000_internal(4);
	ipl_fetch_now();
	m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
	regs.ir = regs.irc;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	int val = cctrue(5) ? 0xff : 0x00;
	x_put_byte(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 12 (1/1) */
/* 2 0,0   */

/* Scc.B -(An) (CS) */
void REGPARAM2 op_55e0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
	do_cycles_ce000_internal(4);
	ipl_fetch_now();
	m68k_areg(regs, srcreg) = srca;
	regs.ir = regs.irc;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	int val = cctrue(5) ? 0xff : 0x00;
	x_put_byte(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 12 (1/1) */
/* 2 0,0   */

/* Scc.B (d16,An) (CS) */
void REGPARAM2 op_55e8_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	ipl_fetch_now();
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	int val = cctrue(5) ? 0xff : 0x00;
	x_put_byte(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 12 (2/1) */
/* 4 0,0   */

/* Scc.B (d8,An,Xn) (CS) */
void REGPARAM2 op_55f0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_ce000_prefetch(4));
	do_cycles_ce000_internal(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	ipl_fetch_now();
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	int val = cctrue(5) ? 0xff : 0x00;
	x_put_byte(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (2/1) */
/* 4 4,0   */

/* Scc.B (xxx).W (CS) */
void REGPARAM2 op_55f8_13_ff(uae_u32 opcode)
{
	OpcodeFamily = 59;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	ipl_fetch_now();
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	int val = cctrue(5) ? 0xff : 0x00;
	x_put_byte(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 12 (2/1) */
/* 4 0,0   */

/* Scc.B (xxx).L (CS) */
void REGPARAM2 op_55f9_13_ff(uae_u32 opcode)
{
	OpcodeFamily = 59;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	srca |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	ipl_fetch_now();
	regs.ir = regs.irc;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	opcode = regs.ir;
	int val = cctrue(5) ? 0xff : 0x00;
	x_put_byte(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 16 (3/1) */
/* 6 0,0   */

/* Scc.B Dn (NE) */
void REGPARAM2 op_56c0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 4;  
	int val = cctrue(6) ? 0xff : 0x00;
	int cycles = val ? 2 : 0;
	if (!val) {
		m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff);
	}
	regs.ir = regs.irc;
	if (!val)
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if(!val && regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff);
	if (cycles > 0) do_cycles_ce000_internal(cycles);
	m68k_incpci(2);
	return;
}
/* 4+ (1/0) */
/* 2 0,0   */

/* DBcc.W Dn,#<data>.W (NE) */
void REGPARAM2 op_56c8_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 58;
	CurrentInstrCycles = 10; 
	int pcadjust = -2;
	uae_s16 src = m68k_dreg(regs, srcreg);
	uae_s16 offs = regs.irc;
	int was_loop_mode = regs.loop_mode;
	regs.loop_mode = 0;
	uaecptr oldpc = m68k_getpci();
	do_cycles_ce000_internal(2);
	if (!cctrue(6)) {
		m68k_incpci((uae_s32)offs + 2);
		if (offs & 1) {
			get_word_ce000_prefetch(-1);
			exception3_read_prefetch(opcode, m68k_getpci());
			return;
		}
		if(offs == -4 && !regs.t1 && loop_mode_table[regs.ird]) {
			if(!was_loop_mode) {
				uae_u16 irc = regs.irc;
				get_word_ce000_prefetch(0);
				if(hardware_bus_error) {
					int pcoffset = 0;
					exception2_fetch_opcode(opcode, 0, 0);
					return;
				}
				get_word_ce000_prefetch(2);
				if(hardware_bus_error) {
					int pcoffset = 0;
					exception2_fetch_opcode(opcode, 2, 0);
					return;
				}
				regs.irc = irc;
			} else {
				do_cycles_ce000_internal(2);
			}
			regs.loop_mode = 1;
			src = m68k_dreg(regs, srcreg);
			m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
			if (src) {
				loop_mode_table[regs.ird](regs.ird);
				 // quick exit if condition false and count expired
				if (!cctrue(6) && (m68k_dreg(regs, srcreg) & 0xffff) == 0) {
					m68k_dreg(regs, srcreg) |= 0xffff;
					 // loop exit: add possible extra cycle(s)
					if(regs.loop_mode >> 16) {
						do_cycles_ce000_internal(regs.loop_mode >> 16);
					}
					regs.loop_mode = 0;
					m68k_setpci_j(oldpc + 4);
					get_word_ce000_prefetch(0);
					if(hardware_bus_error) {
						int pcoffset = 0;
						m68k_setpci_j(oldpc + 2);
						exception2_fetch_opcode(opcode, 0, pcoffset);
						return;
					}
					regs.ir = regs.irc;
					opcode = regs.ir;
					ipl_fetch_next();
					get_word_ce000_prefetch(2);
					if(hardware_bus_error) {
						int pcoffset = 0;
						m68k_setpci_j(oldpc + 2);
						exception2_fetch_opcode(opcode, 2, pcoffset);
						return;
					}
					return;
				}
				 // loop continue: add possible extra cycle(s)
				if(regs.loop_mode & 0xfffe) {
					do_cycles_ce000_internal(regs.loop_mode & 0xfffe);
				}
				m68k_setpci_j(oldpc);
				ipl_fetch_now();
				return;
			}
			regs.loop_mode = 0;
			m68k_setpci_j(oldpc + 4);
			get_word_ce000_prefetch(0);
			if(hardware_bus_error) {
				int pcoffset = 0;
				m68k_setpci_j(oldpc + 2);
				exception2_fetch_opcode(opcode, 0, pcoffset);
				return;
			}
			regs.ir = regs.irc;
			opcode = regs.ir;
			ipl_fetch_next();
			get_word_ce000_prefetch(2);
			if(hardware_bus_error) {
				int pcoffset = 0;
				m68k_setpci_j(oldpc + 2);
				exception2_fetch_opcode(opcode, 2, pcoffset);
				return;
			}
			return;
		}
		get_word_ce000_prefetch(0);
		if(hardware_bus_error) {
			int pcoffset = 0;
			pcoffset = oldpc - m68k_getpci() + 4;
			exception2_fetch_opcode(opcode, 0, pcoffset);
			return;
		}
		if (src) {
			m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
			regs.ir = regs.irc;
			opcode = regs.ir;
			ipl_fetch_next();
			get_word_ce000_prefetch(2);
			if(hardware_bus_error) {
				int pcoffset = 0;
				exception2_fetch_opcode(opcode, 2, 0);
				return;
			}
			return;
		}
		do_cycles_ce000_internal(2);
		pcadjust = 0;
	}
	m68k_setpci_j(oldpc + 4);
	get_word_ce000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		pcoffset += pcadjust;
		exception2_fetch_opcode(opcode, 0, pcoffset);
		return;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	if (!cctrue(6)) {
		m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
	}
	ipl_fetch_next();
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 10 (2/0) */
/* 4 0,0 B */

/* Scc.B (An) (NE) */
void REGPARAM2 op_56d0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 10; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	do_cycles_ce000_internal(2);
	ipl_fetch_now();
	regs.ir = regs.irc;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	int val = cctrue(6) ? 0xff : 0x00;
	x_put_byte(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 10 (1/1) */
/* 2 0,0   */

/* Scc.B (An)+ (NE) */
void REGPARAM2 op_56d8_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	do_cycles_ce000_internal(4);
	ipl_fetch_now();
	m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
	regs.ir = regs.irc;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	int val = cctrue(6) ? 0xff : 0x00;
	x_put_byte(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 12 (1/1) */
/* 2 0,0   */

/* Scc.B -(An) (NE) */
void REGPARAM2 op_56e0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
	do_cycles_ce000_internal(4);
	ipl_fetch_now();
	m68k_areg(regs, srcreg) = srca;
	regs.ir = regs.irc;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	int val = cctrue(6) ? 0xff : 0x00;
	x_put_byte(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 12 (1/1) */
/* 2 0,0   */

/* Scc.B (d16,An) (NE) */
void REGPARAM2 op_56e8_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	ipl_fetch_now();
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	int val = cctrue(6) ? 0xff : 0x00;
	x_put_byte(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 12 (2/1) */
/* 4 0,0   */

/* Scc.B (d8,An,Xn) (NE) */
void REGPARAM2 op_56f0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_ce000_prefetch(4));
	do_cycles_ce000_internal(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	ipl_fetch_now();
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	int val = cctrue(6) ? 0xff : 0x00;
	x_put_byte(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (2/1) */
/* 4 4,0   */

/* Scc.B (xxx).W (NE) */
void REGPARAM2 op_56f8_13_ff(uae_u32 opcode)
{
	OpcodeFamily = 59;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	ipl_fetch_now();
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	int val = cctrue(6) ? 0xff : 0x00;
	x_put_byte(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 12 (2/1) */
/* 4 0,0   */

/* Scc.B (xxx).L (NE) */
void REGPARAM2 op_56f9_13_ff(uae_u32 opcode)
{
	OpcodeFamily = 59;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	srca |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	ipl_fetch_now();
	regs.ir = regs.irc;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	opcode = regs.ir;
	int val = cctrue(6) ? 0xff : 0x00;
	x_put_byte(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 16 (3/1) */
/* 6 0,0   */

/* Scc.B Dn (EQ) */
void REGPARAM2 op_57c0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 4;  
	int val = cctrue(7) ? 0xff : 0x00;
	int cycles = val ? 2 : 0;
	if (!val) {
		m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff);
	}
	regs.ir = regs.irc;
	if (!val)
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if(!val && regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff);
	if (cycles > 0) do_cycles_ce000_internal(cycles);
	m68k_incpci(2);
	return;
}
/* 4+ (1/0) */
/* 2 0,0   */

/* DBcc.W Dn,#<data>.W (EQ) */
void REGPARAM2 op_57c8_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 58;
	CurrentInstrCycles = 10; 
	int pcadjust = -2;
	uae_s16 src = m68k_dreg(regs, srcreg);
	uae_s16 offs = regs.irc;
	int was_loop_mode = regs.loop_mode;
	regs.loop_mode = 0;
	uaecptr oldpc = m68k_getpci();
	do_cycles_ce000_internal(2);
	if (!cctrue(7)) {
		m68k_incpci((uae_s32)offs + 2);
		if (offs & 1) {
			get_word_ce000_prefetch(-1);
			exception3_read_prefetch(opcode, m68k_getpci());
			return;
		}
		if(offs == -4 && !regs.t1 && loop_mode_table[regs.ird]) {
			if(!was_loop_mode) {
				uae_u16 irc = regs.irc;
				get_word_ce000_prefetch(0);
				if(hardware_bus_error) {
					int pcoffset = 0;
					exception2_fetch_opcode(opcode, 0, 0);
					return;
				}
				get_word_ce000_prefetch(2);
				if(hardware_bus_error) {
					int pcoffset = 0;
					exception2_fetch_opcode(opcode, 2, 0);
					return;
				}
				regs.irc = irc;
			} else {
				do_cycles_ce000_internal(2);
			}
			regs.loop_mode = 1;
			src = m68k_dreg(regs, srcreg);
			m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
			if (src) {
				loop_mode_table[regs.ird](regs.ird);
				 // quick exit if condition false and count expired
				if (!cctrue(7) && (m68k_dreg(regs, srcreg) & 0xffff) == 0) {
					m68k_dreg(regs, srcreg) |= 0xffff;
					 // loop exit: add possible extra cycle(s)
					if(regs.loop_mode >> 16) {
						do_cycles_ce000_internal(regs.loop_mode >> 16);
					}
					regs.loop_mode = 0;
					m68k_setpci_j(oldpc + 4);
					get_word_ce000_prefetch(0);
					if(hardware_bus_error) {
						int pcoffset = 0;
						m68k_setpci_j(oldpc + 2);
						exception2_fetch_opcode(opcode, 0, pcoffset);
						return;
					}
					regs.ir = regs.irc;
					opcode = regs.ir;
					ipl_fetch_next();
					get_word_ce000_prefetch(2);
					if(hardware_bus_error) {
						int pcoffset = 0;
						m68k_setpci_j(oldpc + 2);
						exception2_fetch_opcode(opcode, 2, pcoffset);
						return;
					}
					return;
				}
				 // loop continue: add possible extra cycle(s)
				if(regs.loop_mode & 0xfffe) {
					do_cycles_ce000_internal(regs.loop_mode & 0xfffe);
				}
				m68k_setpci_j(oldpc);
				ipl_fetch_now();
				return;
			}
			regs.loop_mode = 0;
			m68k_setpci_j(oldpc + 4);
			get_word_ce000_prefetch(0);
			if(hardware_bus_error) {
				int pcoffset = 0;
				m68k_setpci_j(oldpc + 2);
				exception2_fetch_opcode(opcode, 0, pcoffset);
				return;
			}
			regs.ir = regs.irc;
			opcode = regs.ir;
			ipl_fetch_next();
			get_word_ce000_prefetch(2);
			if(hardware_bus_error) {
				int pcoffset = 0;
				m68k_setpci_j(oldpc + 2);
				exception2_fetch_opcode(opcode, 2, pcoffset);
				return;
			}
			return;
		}
		get_word_ce000_prefetch(0);
		if(hardware_bus_error) {
			int pcoffset = 0;
			pcoffset = oldpc - m68k_getpci() + 4;
			exception2_fetch_opcode(opcode, 0, pcoffset);
			return;
		}
		if (src) {
			m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
			regs.ir = regs.irc;
			opcode = regs.ir;
			ipl_fetch_next();
			get_word_ce000_prefetch(2);
			if(hardware_bus_error) {
				int pcoffset = 0;
				exception2_fetch_opcode(opcode, 2, 0);
				return;
			}
			return;
		}
		do_cycles_ce000_internal(2);
		pcadjust = 0;
	}
	m68k_setpci_j(oldpc + 4);
	get_word_ce000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		pcoffset += pcadjust;
		exception2_fetch_opcode(opcode, 0, pcoffset);
		return;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	if (!cctrue(7)) {
		m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
	}
	ipl_fetch_next();
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 10 (2/0) */
/* 4 0,0 B */

/* Scc.B (An) (EQ) */
void REGPARAM2 op_57d0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 10; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	do_cycles_ce000_internal(2);
	ipl_fetch_now();
	regs.ir = regs.irc;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	int val = cctrue(7) ? 0xff : 0x00;
	x_put_byte(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 10 (1/1) */
/* 2 0,0   */

/* Scc.B (An)+ (EQ) */
void REGPARAM2 op_57d8_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	do_cycles_ce000_internal(4);
	ipl_fetch_now();
	m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
	regs.ir = regs.irc;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	int val = cctrue(7) ? 0xff : 0x00;
	x_put_byte(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 12 (1/1) */
/* 2 0,0   */

/* Scc.B -(An) (EQ) */
void REGPARAM2 op_57e0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
	do_cycles_ce000_internal(4);
	ipl_fetch_now();
	m68k_areg(regs, srcreg) = srca;
	regs.ir = regs.irc;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	int val = cctrue(7) ? 0xff : 0x00;
	x_put_byte(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 12 (1/1) */
/* 2 0,0   */

/* Scc.B (d16,An) (EQ) */
void REGPARAM2 op_57e8_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	ipl_fetch_now();
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	int val = cctrue(7) ? 0xff : 0x00;
	x_put_byte(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 12 (2/1) */
/* 4 0,0   */

/* Scc.B (d8,An,Xn) (EQ) */
void REGPARAM2 op_57f0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_ce000_prefetch(4));
	do_cycles_ce000_internal(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	ipl_fetch_now();
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	int val = cctrue(7) ? 0xff : 0x00;
	x_put_byte(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (2/1) */
/* 4 4,0   */

/* Scc.B (xxx).W (EQ) */
void REGPARAM2 op_57f8_13_ff(uae_u32 opcode)
{
	OpcodeFamily = 59;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	ipl_fetch_now();
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	int val = cctrue(7) ? 0xff : 0x00;
	x_put_byte(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 12 (2/1) */
/* 4 0,0   */

/* Scc.B (xxx).L (EQ) */
void REGPARAM2 op_57f9_13_ff(uae_u32 opcode)
{
	OpcodeFamily = 59;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	srca |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	ipl_fetch_now();
	regs.ir = regs.irc;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	opcode = regs.ir;
	int val = cctrue(7) ? 0xff : 0x00;
	x_put_byte(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 16 (3/1) */
/* 6 0,0   */

/* Scc.B Dn (VC) */
void REGPARAM2 op_58c0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 4;  
	int val = cctrue(8) ? 0xff : 0x00;
	int cycles = val ? 2 : 0;
	if (!val) {
		m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff);
	}
	regs.ir = regs.irc;
	if (!val)
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if(!val && regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff);
	if (cycles > 0) do_cycles_ce000_internal(cycles);
	m68k_incpci(2);
	return;
}
/* 4+ (1/0) */
/* 2 0,0   */

/* DBcc.W Dn,#<data>.W (VC) */
void REGPARAM2 op_58c8_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 58;
	CurrentInstrCycles = 10; 
	int pcadjust = -2;
	uae_s16 src = m68k_dreg(regs, srcreg);
	uae_s16 offs = regs.irc;
	int was_loop_mode = regs.loop_mode;
	regs.loop_mode = 0;
	uaecptr oldpc = m68k_getpci();
	do_cycles_ce000_internal(2);
	if (!cctrue(8)) {
		m68k_incpci((uae_s32)offs + 2);
		if (offs & 1) {
			get_word_ce000_prefetch(-1);
			exception3_read_prefetch(opcode, m68k_getpci());
			return;
		}
		if(offs == -4 && !regs.t1 && loop_mode_table[regs.ird]) {
			if(!was_loop_mode) {
				uae_u16 irc = regs.irc;
				get_word_ce000_prefetch(0);
				if(hardware_bus_error) {
					int pcoffset = 0;
					exception2_fetch_opcode(opcode, 0, 0);
					return;
				}
				get_word_ce000_prefetch(2);
				if(hardware_bus_error) {
					int pcoffset = 0;
					exception2_fetch_opcode(opcode, 2, 0);
					return;
				}
				regs.irc = irc;
			} else {
				do_cycles_ce000_internal(2);
			}
			regs.loop_mode = 1;
			src = m68k_dreg(regs, srcreg);
			m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
			if (src) {
				loop_mode_table[regs.ird](regs.ird);
				 // quick exit if condition false and count expired
				if (!cctrue(8) && (m68k_dreg(regs, srcreg) & 0xffff) == 0) {
					m68k_dreg(regs, srcreg) |= 0xffff;
					 // loop exit: add possible extra cycle(s)
					if(regs.loop_mode >> 16) {
						do_cycles_ce000_internal(regs.loop_mode >> 16);
					}
					regs.loop_mode = 0;
					m68k_setpci_j(oldpc + 4);
					get_word_ce000_prefetch(0);
					if(hardware_bus_error) {
						int pcoffset = 0;
						m68k_setpci_j(oldpc + 2);
						exception2_fetch_opcode(opcode, 0, pcoffset);
						return;
					}
					regs.ir = regs.irc;
					opcode = regs.ir;
					ipl_fetch_next();
					get_word_ce000_prefetch(2);
					if(hardware_bus_error) {
						int pcoffset = 0;
						m68k_setpci_j(oldpc + 2);
						exception2_fetch_opcode(opcode, 2, pcoffset);
						return;
					}
					return;
				}
				 // loop continue: add possible extra cycle(s)
				if(regs.loop_mode & 0xfffe) {
					do_cycles_ce000_internal(regs.loop_mode & 0xfffe);
				}
				m68k_setpci_j(oldpc);
				ipl_fetch_now();
				return;
			}
			regs.loop_mode = 0;
			m68k_setpci_j(oldpc + 4);
			get_word_ce000_prefetch(0);
			if(hardware_bus_error) {
				int pcoffset = 0;
				m68k_setpci_j(oldpc + 2);
				exception2_fetch_opcode(opcode, 0, pcoffset);
				return;
			}
			regs.ir = regs.irc;
			opcode = regs.ir;
			ipl_fetch_next();
			get_word_ce000_prefetch(2);
			if(hardware_bus_error) {
				int pcoffset = 0;
				m68k_setpci_j(oldpc + 2);
				exception2_fetch_opcode(opcode, 2, pcoffset);
				return;
			}
			return;
		}
		get_word_ce000_prefetch(0);
		if(hardware_bus_error) {
			int pcoffset = 0;
			pcoffset = oldpc - m68k_getpci() + 4;
			exception2_fetch_opcode(opcode, 0, pcoffset);
			return;
		}
		if (src) {
			m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
			regs.ir = regs.irc;
			opcode = regs.ir;
			ipl_fetch_next();
			get_word_ce000_prefetch(2);
			if(hardware_bus_error) {
				int pcoffset = 0;
				exception2_fetch_opcode(opcode, 2, 0);
				return;
			}
			return;
		}
		do_cycles_ce000_internal(2);
		pcadjust = 0;
	}
	m68k_setpci_j(oldpc + 4);
	get_word_ce000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		pcoffset += pcadjust;
		exception2_fetch_opcode(opcode, 0, pcoffset);
		return;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	if (!cctrue(8)) {
		m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
	}
	ipl_fetch_next();
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 10 (2/0) */
/* 4 0,0 B */

/* Scc.B (An) (VC) */
void REGPARAM2 op_58d0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 10; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	do_cycles_ce000_internal(2);
	ipl_fetch_now();
	regs.ir = regs.irc;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	int val = cctrue(8) ? 0xff : 0x00;
	x_put_byte(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 10 (1/1) */
/* 2 0,0   */

/* Scc.B (An)+ (VC) */
void REGPARAM2 op_58d8_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	do_cycles_ce000_internal(4);
	ipl_fetch_now();
	m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
	regs.ir = regs.irc;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	int val = cctrue(8) ? 0xff : 0x00;
	x_put_byte(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 12 (1/1) */
/* 2 0,0   */

/* Scc.B -(An) (VC) */
void REGPARAM2 op_58e0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
	do_cycles_ce000_internal(4);
	ipl_fetch_now();
	m68k_areg(regs, srcreg) = srca;
	regs.ir = regs.irc;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	int val = cctrue(8) ? 0xff : 0x00;
	x_put_byte(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 12 (1/1) */
/* 2 0,0   */

/* Scc.B (d16,An) (VC) */
void REGPARAM2 op_58e8_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	ipl_fetch_now();
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	int val = cctrue(8) ? 0xff : 0x00;
	x_put_byte(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 12 (2/1) */
/* 4 0,0   */

/* Scc.B (d8,An,Xn) (VC) */
void REGPARAM2 op_58f0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_ce000_prefetch(4));
	do_cycles_ce000_internal(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	ipl_fetch_now();
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	int val = cctrue(8) ? 0xff : 0x00;
	x_put_byte(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (2/1) */
/* 4 4,0   */

/* Scc.B (xxx).W (VC) */
void REGPARAM2 op_58f8_13_ff(uae_u32 opcode)
{
	OpcodeFamily = 59;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	ipl_fetch_now();
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	int val = cctrue(8) ? 0xff : 0x00;
	x_put_byte(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 12 (2/1) */
/* 4 0,0   */

/* Scc.B (xxx).L (VC) */
void REGPARAM2 op_58f9_13_ff(uae_u32 opcode)
{
	OpcodeFamily = 59;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	srca |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	ipl_fetch_now();
	regs.ir = regs.irc;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	opcode = regs.ir;
	int val = cctrue(8) ? 0xff : 0x00;
	x_put_byte(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 16 (3/1) */
/* 6 0,0   */

/* Scc.B Dn (VS) */
void REGPARAM2 op_59c0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 4;  
	int val = cctrue(9) ? 0xff : 0x00;
	int cycles = val ? 2 : 0;
	if (!val) {
		m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff);
	}
	regs.ir = regs.irc;
	if (!val)
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if(!val && regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff);
	if (cycles > 0) do_cycles_ce000_internal(cycles);
	m68k_incpci(2);
	return;
}
/* 4+ (1/0) */
/* 2 0,0   */

/* DBcc.W Dn,#<data>.W (VS) */
void REGPARAM2 op_59c8_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 58;
	CurrentInstrCycles = 10; 
	int pcadjust = -2;
	uae_s16 src = m68k_dreg(regs, srcreg);
	uae_s16 offs = regs.irc;
	int was_loop_mode = regs.loop_mode;
	regs.loop_mode = 0;
	uaecptr oldpc = m68k_getpci();
	do_cycles_ce000_internal(2);
	if (!cctrue(9)) {
		m68k_incpci((uae_s32)offs + 2);
		if (offs & 1) {
			get_word_ce000_prefetch(-1);
			exception3_read_prefetch(opcode, m68k_getpci());
			return;
		}
		if(offs == -4 && !regs.t1 && loop_mode_table[regs.ird]) {
			if(!was_loop_mode) {
				uae_u16 irc = regs.irc;
				get_word_ce000_prefetch(0);
				if(hardware_bus_error) {
					int pcoffset = 0;
					exception2_fetch_opcode(opcode, 0, 0);
					return;
				}
				get_word_ce000_prefetch(2);
				if(hardware_bus_error) {
					int pcoffset = 0;
					exception2_fetch_opcode(opcode, 2, 0);
					return;
				}
				regs.irc = irc;
			} else {
				do_cycles_ce000_internal(2);
			}
			regs.loop_mode = 1;
			src = m68k_dreg(regs, srcreg);
			m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
			if (src) {
				loop_mode_table[regs.ird](regs.ird);
				 // quick exit if condition false and count expired
				if (!cctrue(9) && (m68k_dreg(regs, srcreg) & 0xffff) == 0) {
					m68k_dreg(regs, srcreg) |= 0xffff;
					 // loop exit: add possible extra cycle(s)
					if(regs.loop_mode >> 16) {
						do_cycles_ce000_internal(regs.loop_mode >> 16);
					}
					regs.loop_mode = 0;
					m68k_setpci_j(oldpc + 4);
					get_word_ce000_prefetch(0);
					if(hardware_bus_error) {
						int pcoffset = 0;
						m68k_setpci_j(oldpc + 2);
						exception2_fetch_opcode(opcode, 0, pcoffset);
						return;
					}
					regs.ir = regs.irc;
					opcode = regs.ir;
					ipl_fetch_next();
					get_word_ce000_prefetch(2);
					if(hardware_bus_error) {
						int pcoffset = 0;
						m68k_setpci_j(oldpc + 2);
						exception2_fetch_opcode(opcode, 2, pcoffset);
						return;
					}
					return;
				}
				 // loop continue: add possible extra cycle(s)
				if(regs.loop_mode & 0xfffe) {
					do_cycles_ce000_internal(regs.loop_mode & 0xfffe);
				}
				m68k_setpci_j(oldpc);
				ipl_fetch_now();
				return;
			}
			regs.loop_mode = 0;
			m68k_setpci_j(oldpc + 4);
			get_word_ce000_prefetch(0);
			if(hardware_bus_error) {
				int pcoffset = 0;
				m68k_setpci_j(oldpc + 2);
				exception2_fetch_opcode(opcode, 0, pcoffset);
				return;
			}
			regs.ir = regs.irc;
			opcode = regs.ir;
			ipl_fetch_next();
			get_word_ce000_prefetch(2);
			if(hardware_bus_error) {
				int pcoffset = 0;
				m68k_setpci_j(oldpc + 2);
				exception2_fetch_opcode(opcode, 2, pcoffset);
				return;
			}
			return;
		}
		get_word_ce000_prefetch(0);
		if(hardware_bus_error) {
			int pcoffset = 0;
			pcoffset = oldpc - m68k_getpci() + 4;
			exception2_fetch_opcode(opcode, 0, pcoffset);
			return;
		}
		if (src) {
			m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
			regs.ir = regs.irc;
			opcode = regs.ir;
			ipl_fetch_next();
			get_word_ce000_prefetch(2);
			if(hardware_bus_error) {
				int pcoffset = 0;
				exception2_fetch_opcode(opcode, 2, 0);
				return;
			}
			return;
		}
		do_cycles_ce000_internal(2);
		pcadjust = 0;
	}
	m68k_setpci_j(oldpc + 4);
	get_word_ce000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		pcoffset += pcadjust;
		exception2_fetch_opcode(opcode, 0, pcoffset);
		return;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	if (!cctrue(9)) {
		m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
	}
	ipl_fetch_next();
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 10 (2/0) */
/* 4 0,0 B */

/* Scc.B (An) (VS) */
void REGPARAM2 op_59d0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 10; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	do_cycles_ce000_internal(2);
	ipl_fetch_now();
	regs.ir = regs.irc;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	int val = cctrue(9) ? 0xff : 0x00;
	x_put_byte(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 10 (1/1) */
/* 2 0,0   */

/* Scc.B (An)+ (VS) */
void REGPARAM2 op_59d8_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	do_cycles_ce000_internal(4);
	ipl_fetch_now();
	m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
	regs.ir = regs.irc;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	int val = cctrue(9) ? 0xff : 0x00;
	x_put_byte(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 12 (1/1) */
/* 2 0,0   */

/* Scc.B -(An) (VS) */
void REGPARAM2 op_59e0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
	do_cycles_ce000_internal(4);
	ipl_fetch_now();
	m68k_areg(regs, srcreg) = srca;
	regs.ir = regs.irc;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	int val = cctrue(9) ? 0xff : 0x00;
	x_put_byte(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 12 (1/1) */
/* 2 0,0   */

/* Scc.B (d16,An) (VS) */
void REGPARAM2 op_59e8_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	ipl_fetch_now();
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	int val = cctrue(9) ? 0xff : 0x00;
	x_put_byte(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 12 (2/1) */
/* 4 0,0   */

/* Scc.B (d8,An,Xn) (VS) */
void REGPARAM2 op_59f0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_ce000_prefetch(4));
	do_cycles_ce000_internal(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	ipl_fetch_now();
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	int val = cctrue(9) ? 0xff : 0x00;
	x_put_byte(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (2/1) */
/* 4 4,0   */

/* Scc.B (xxx).W (VS) */
void REGPARAM2 op_59f8_13_ff(uae_u32 opcode)
{
	OpcodeFamily = 59;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	ipl_fetch_now();
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	int val = cctrue(9) ? 0xff : 0x00;
	x_put_byte(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 12 (2/1) */
/* 4 0,0   */

/* Scc.B (xxx).L (VS) */
void REGPARAM2 op_59f9_13_ff(uae_u32 opcode)
{
	OpcodeFamily = 59;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	srca |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	ipl_fetch_now();
	regs.ir = regs.irc;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	opcode = regs.ir;
	int val = cctrue(9) ? 0xff : 0x00;
	x_put_byte(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 16 (3/1) */
/* 6 0,0   */

/* Scc.B Dn (PL) */
void REGPARAM2 op_5ac0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 4;  
	int val = cctrue(10) ? 0xff : 0x00;
	int cycles = val ? 2 : 0;
	if (!val) {
		m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff);
	}
	regs.ir = regs.irc;
	if (!val)
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if(!val && regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff);
	if (cycles > 0) do_cycles_ce000_internal(cycles);
	m68k_incpci(2);
	return;
}
/* 4+ (1/0) */
/* 2 0,0   */

/* DBcc.W Dn,#<data>.W (PL) */
void REGPARAM2 op_5ac8_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 58;
	CurrentInstrCycles = 10; 
	int pcadjust = -2;
	uae_s16 src = m68k_dreg(regs, srcreg);
	uae_s16 offs = regs.irc;
	int was_loop_mode = regs.loop_mode;
	regs.loop_mode = 0;
	uaecptr oldpc = m68k_getpci();
	do_cycles_ce000_internal(2);
	if (!cctrue(10)) {
		m68k_incpci((uae_s32)offs + 2);
		if (offs & 1) {
			get_word_ce000_prefetch(-1);
			exception3_read_prefetch(opcode, m68k_getpci());
			return;
		}
		if(offs == -4 && !regs.t1 && loop_mode_table[regs.ird]) {
			if(!was_loop_mode) {
				uae_u16 irc = regs.irc;
				get_word_ce000_prefetch(0);
				if(hardware_bus_error) {
					int pcoffset = 0;
					exception2_fetch_opcode(opcode, 0, 0);
					return;
				}
				get_word_ce000_prefetch(2);
				if(hardware_bus_error) {
					int pcoffset = 0;
					exception2_fetch_opcode(opcode, 2, 0);
					return;
				}
				regs.irc = irc;
			} else {
				do_cycles_ce000_internal(2);
			}
			regs.loop_mode = 1;
			src = m68k_dreg(regs, srcreg);
			m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
			if (src) {
				loop_mode_table[regs.ird](regs.ird);
				 // quick exit if condition false and count expired
				if (!cctrue(10) && (m68k_dreg(regs, srcreg) & 0xffff) == 0) {
					m68k_dreg(regs, srcreg) |= 0xffff;
					 // loop exit: add possible extra cycle(s)
					if(regs.loop_mode >> 16) {
						do_cycles_ce000_internal(regs.loop_mode >> 16);
					}
					regs.loop_mode = 0;
					m68k_setpci_j(oldpc + 4);
					get_word_ce000_prefetch(0);
					if(hardware_bus_error) {
						int pcoffset = 0;
						m68k_setpci_j(oldpc + 2);
						exception2_fetch_opcode(opcode, 0, pcoffset);
						return;
					}
					regs.ir = regs.irc;
					opcode = regs.ir;
					ipl_fetch_next();
					get_word_ce000_prefetch(2);
					if(hardware_bus_error) {
						int pcoffset = 0;
						m68k_setpci_j(oldpc + 2);
						exception2_fetch_opcode(opcode, 2, pcoffset);
						return;
					}
					return;
				}
				 // loop continue: add possible extra cycle(s)
				if(regs.loop_mode & 0xfffe) {
					do_cycles_ce000_internal(regs.loop_mode & 0xfffe);
				}
				m68k_setpci_j(oldpc);
				ipl_fetch_now();
				return;
			}
			regs.loop_mode = 0;
			m68k_setpci_j(oldpc + 4);
			get_word_ce000_prefetch(0);
			if(hardware_bus_error) {
				int pcoffset = 0;
				m68k_setpci_j(oldpc + 2);
				exception2_fetch_opcode(opcode, 0, pcoffset);
				return;
			}
			regs.ir = regs.irc;
			opcode = regs.ir;
			ipl_fetch_next();
			get_word_ce000_prefetch(2);
			if(hardware_bus_error) {
				int pcoffset = 0;
				m68k_setpci_j(oldpc + 2);
				exception2_fetch_opcode(opcode, 2, pcoffset);
				return;
			}
			return;
		}
		get_word_ce000_prefetch(0);
		if(hardware_bus_error) {
			int pcoffset = 0;
			pcoffset = oldpc - m68k_getpci() + 4;
			exception2_fetch_opcode(opcode, 0, pcoffset);
			return;
		}
		if (src) {
			m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
			regs.ir = regs.irc;
			opcode = regs.ir;
			ipl_fetch_next();
			get_word_ce000_prefetch(2);
			if(hardware_bus_error) {
				int pcoffset = 0;
				exception2_fetch_opcode(opcode, 2, 0);
				return;
			}
			return;
		}
		do_cycles_ce000_internal(2);
		pcadjust = 0;
	}
	m68k_setpci_j(oldpc + 4);
	get_word_ce000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		pcoffset += pcadjust;
		exception2_fetch_opcode(opcode, 0, pcoffset);
		return;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	if (!cctrue(10)) {
		m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
	}
	ipl_fetch_next();
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 10 (2/0) */
/* 4 0,0 B */

/* Scc.B (An) (PL) */
void REGPARAM2 op_5ad0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 10; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	do_cycles_ce000_internal(2);
	ipl_fetch_now();
	regs.ir = regs.irc;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	int val = cctrue(10) ? 0xff : 0x00;
	x_put_byte(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 10 (1/1) */
/* 2 0,0   */

/* Scc.B (An)+ (PL) */
void REGPARAM2 op_5ad8_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	do_cycles_ce000_internal(4);
	ipl_fetch_now();
	m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
	regs.ir = regs.irc;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	int val = cctrue(10) ? 0xff : 0x00;
	x_put_byte(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 12 (1/1) */
/* 2 0,0   */

/* Scc.B -(An) (PL) */
void REGPARAM2 op_5ae0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
	do_cycles_ce000_internal(4);
	ipl_fetch_now();
	m68k_areg(regs, srcreg) = srca;
	regs.ir = regs.irc;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	int val = cctrue(10) ? 0xff : 0x00;
	x_put_byte(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 12 (1/1) */
/* 2 0,0   */

/* Scc.B (d16,An) (PL) */
void REGPARAM2 op_5ae8_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	ipl_fetch_now();
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	int val = cctrue(10) ? 0xff : 0x00;
	x_put_byte(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 12 (2/1) */
/* 4 0,0   */

/* Scc.B (d8,An,Xn) (PL) */
void REGPARAM2 op_5af0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_ce000_prefetch(4));
	do_cycles_ce000_internal(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	ipl_fetch_now();
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	int val = cctrue(10) ? 0xff : 0x00;
	x_put_byte(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (2/1) */
/* 4 4,0   */

/* Scc.B (xxx).W (PL) */
void REGPARAM2 op_5af8_13_ff(uae_u32 opcode)
{
	OpcodeFamily = 59;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	ipl_fetch_now();
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	int val = cctrue(10) ? 0xff : 0x00;
	x_put_byte(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 12 (2/1) */
/* 4 0,0   */

/* Scc.B (xxx).L (PL) */
void REGPARAM2 op_5af9_13_ff(uae_u32 opcode)
{
	OpcodeFamily = 59;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	srca |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	ipl_fetch_now();
	regs.ir = regs.irc;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	opcode = regs.ir;
	int val = cctrue(10) ? 0xff : 0x00;
	x_put_byte(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 16 (3/1) */
/* 6 0,0   */

/* Scc.B Dn (MI) */
void REGPARAM2 op_5bc0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 4;  
	int val = cctrue(11) ? 0xff : 0x00;
	int cycles = val ? 2 : 0;
	if (!val) {
		m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff);
	}
	regs.ir = regs.irc;
	if (!val)
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if(!val && regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff);
	if (cycles > 0) do_cycles_ce000_internal(cycles);
	m68k_incpci(2);
	return;
}
/* 4+ (1/0) */
/* 2 0,0   */

/* DBcc.W Dn,#<data>.W (MI) */
void REGPARAM2 op_5bc8_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 58;
	CurrentInstrCycles = 10; 
	int pcadjust = -2;
	uae_s16 src = m68k_dreg(regs, srcreg);
	uae_s16 offs = regs.irc;
	int was_loop_mode = regs.loop_mode;
	regs.loop_mode = 0;
	uaecptr oldpc = m68k_getpci();
	do_cycles_ce000_internal(2);
	if (!cctrue(11)) {
		m68k_incpci((uae_s32)offs + 2);
		if (offs & 1) {
			get_word_ce000_prefetch(-1);
			exception3_read_prefetch(opcode, m68k_getpci());
			return;
		}
		if(offs == -4 && !regs.t1 && loop_mode_table[regs.ird]) {
			if(!was_loop_mode) {
				uae_u16 irc = regs.irc;
				get_word_ce000_prefetch(0);
				if(hardware_bus_error) {
					int pcoffset = 0;
					exception2_fetch_opcode(opcode, 0, 0);
					return;
				}
				get_word_ce000_prefetch(2);
				if(hardware_bus_error) {
					int pcoffset = 0;
					exception2_fetch_opcode(opcode, 2, 0);
					return;
				}
				regs.irc = irc;
			} else {
				do_cycles_ce000_internal(2);
			}
			regs.loop_mode = 1;
			src = m68k_dreg(regs, srcreg);
			m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
			if (src) {
				loop_mode_table[regs.ird](regs.ird);
				 // quick exit if condition false and count expired
				if (!cctrue(11) && (m68k_dreg(regs, srcreg) & 0xffff) == 0) {
					m68k_dreg(regs, srcreg) |= 0xffff;
					 // loop exit: add possible extra cycle(s)
					if(regs.loop_mode >> 16) {
						do_cycles_ce000_internal(regs.loop_mode >> 16);
					}
					regs.loop_mode = 0;
					m68k_setpci_j(oldpc + 4);
					get_word_ce000_prefetch(0);
					if(hardware_bus_error) {
						int pcoffset = 0;
						m68k_setpci_j(oldpc + 2);
						exception2_fetch_opcode(opcode, 0, pcoffset);
						return;
					}
					regs.ir = regs.irc;
					opcode = regs.ir;
					ipl_fetch_next();
					get_word_ce000_prefetch(2);
					if(hardware_bus_error) {
						int pcoffset = 0;
						m68k_setpci_j(oldpc + 2);
						exception2_fetch_opcode(opcode, 2, pcoffset);
						return;
					}
					return;
				}
				 // loop continue: add possible extra cycle(s)
				if(regs.loop_mode & 0xfffe) {
					do_cycles_ce000_internal(regs.loop_mode & 0xfffe);
				}
				m68k_setpci_j(oldpc);
				ipl_fetch_now();
				return;
			}
			regs.loop_mode = 0;
			m68k_setpci_j(oldpc + 4);
			get_word_ce000_prefetch(0);
			if(hardware_bus_error) {
				int pcoffset = 0;
				m68k_setpci_j(oldpc + 2);
				exception2_fetch_opcode(opcode, 0, pcoffset);
				return;
			}
			regs.ir = regs.irc;
			opcode = regs.ir;
			ipl_fetch_next();
			get_word_ce000_prefetch(2);
			if(hardware_bus_error) {
				int pcoffset = 0;
				m68k_setpci_j(oldpc + 2);
				exception2_fetch_opcode(opcode, 2, pcoffset);
				return;
			}
			return;
		}
		get_word_ce000_prefetch(0);
		if(hardware_bus_error) {
			int pcoffset = 0;
			pcoffset = oldpc - m68k_getpci() + 4;
			exception2_fetch_opcode(opcode, 0, pcoffset);
			return;
		}
		if (src) {
			m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
			regs.ir = regs.irc;
			opcode = regs.ir;
			ipl_fetch_next();
			get_word_ce000_prefetch(2);
			if(hardware_bus_error) {
				int pcoffset = 0;
				exception2_fetch_opcode(opcode, 2, 0);
				return;
			}
			return;
		}
		do_cycles_ce000_internal(2);
		pcadjust = 0;
	}
	m68k_setpci_j(oldpc + 4);
	get_word_ce000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		pcoffset += pcadjust;
		exception2_fetch_opcode(opcode, 0, pcoffset);
		return;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	if (!cctrue(11)) {
		m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
	}
	ipl_fetch_next();
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 10 (2/0) */
/* 4 0,0 B */

/* Scc.B (An) (MI) */
void REGPARAM2 op_5bd0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 10; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	do_cycles_ce000_internal(2);
	ipl_fetch_now();
	regs.ir = regs.irc;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	int val = cctrue(11) ? 0xff : 0x00;
	x_put_byte(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 10 (1/1) */
/* 2 0,0   */

/* Scc.B (An)+ (MI) */
void REGPARAM2 op_5bd8_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	do_cycles_ce000_internal(4);
	ipl_fetch_now();
	m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
	regs.ir = regs.irc;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	int val = cctrue(11) ? 0xff : 0x00;
	x_put_byte(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 12 (1/1) */
/* 2 0,0   */

/* Scc.B -(An) (MI) */
void REGPARAM2 op_5be0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
	do_cycles_ce000_internal(4);
	ipl_fetch_now();
	m68k_areg(regs, srcreg) = srca;
	regs.ir = regs.irc;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	int val = cctrue(11) ? 0xff : 0x00;
	x_put_byte(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 12 (1/1) */
/* 2 0,0   */

/* Scc.B (d16,An) (MI) */
void REGPARAM2 op_5be8_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	ipl_fetch_now();
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	int val = cctrue(11) ? 0xff : 0x00;
	x_put_byte(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 12 (2/1) */
/* 4 0,0   */

/* Scc.B (d8,An,Xn) (MI) */
void REGPARAM2 op_5bf0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_ce000_prefetch(4));
	do_cycles_ce000_internal(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	ipl_fetch_now();
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	int val = cctrue(11) ? 0xff : 0x00;
	x_put_byte(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (2/1) */
/* 4 4,0   */

/* Scc.B (xxx).W (MI) */
void REGPARAM2 op_5bf8_13_ff(uae_u32 opcode)
{
	OpcodeFamily = 59;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	ipl_fetch_now();
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	int val = cctrue(11) ? 0xff : 0x00;
	x_put_byte(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 12 (2/1) */
/* 4 0,0   */

/* Scc.B (xxx).L (MI) */
void REGPARAM2 op_5bf9_13_ff(uae_u32 opcode)
{
	OpcodeFamily = 59;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	srca |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	ipl_fetch_now();
	regs.ir = regs.irc;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	opcode = regs.ir;
	int val = cctrue(11) ? 0xff : 0x00;
	x_put_byte(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 16 (3/1) */
/* 6 0,0   */

/* Scc.B Dn (GE) */
void REGPARAM2 op_5cc0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 4;  
	int val = cctrue(12) ? 0xff : 0x00;
	int cycles = val ? 2 : 0;
	if (!val) {
		m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff);
	}
	regs.ir = regs.irc;
	if (!val)
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if(!val && regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff);
	if (cycles > 0) do_cycles_ce000_internal(cycles);
	m68k_incpci(2);
	return;
}
/* 4+ (1/0) */
/* 2 0,0   */

/* DBcc.W Dn,#<data>.W (GE) */
void REGPARAM2 op_5cc8_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 58;
	CurrentInstrCycles = 10; 
	int pcadjust = -2;
	uae_s16 src = m68k_dreg(regs, srcreg);
	uae_s16 offs = regs.irc;
	int was_loop_mode = regs.loop_mode;
	regs.loop_mode = 0;
	uaecptr oldpc = m68k_getpci();
	do_cycles_ce000_internal(2);
	if (!cctrue(12)) {
		m68k_incpci((uae_s32)offs + 2);
		if (offs & 1) {
			get_word_ce000_prefetch(-1);
			exception3_read_prefetch(opcode, m68k_getpci());
			return;
		}
		if(offs == -4 && !regs.t1 && loop_mode_table[regs.ird]) {
			if(!was_loop_mode) {
				uae_u16 irc = regs.irc;
				get_word_ce000_prefetch(0);
				if(hardware_bus_error) {
					int pcoffset = 0;
					exception2_fetch_opcode(opcode, 0, 0);
					return;
				}
				get_word_ce000_prefetch(2);
				if(hardware_bus_error) {
					int pcoffset = 0;
					exception2_fetch_opcode(opcode, 2, 0);
					return;
				}
				regs.irc = irc;
			} else {
				do_cycles_ce000_internal(2);
			}
			regs.loop_mode = 1;
			src = m68k_dreg(regs, srcreg);
			m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
			if (src) {
				loop_mode_table[regs.ird](regs.ird);
				 // quick exit if condition false and count expired
				if (!cctrue(12) && (m68k_dreg(regs, srcreg) & 0xffff) == 0) {
					m68k_dreg(regs, srcreg) |= 0xffff;
					 // loop exit: add possible extra cycle(s)
					if(regs.loop_mode >> 16) {
						do_cycles_ce000_internal(regs.loop_mode >> 16);
					}
					regs.loop_mode = 0;
					m68k_setpci_j(oldpc + 4);
					get_word_ce000_prefetch(0);
					if(hardware_bus_error) {
						int pcoffset = 0;
						m68k_setpci_j(oldpc + 2);
						exception2_fetch_opcode(opcode, 0, pcoffset);
						return;
					}
					regs.ir = regs.irc;
					opcode = regs.ir;
					ipl_fetch_next();
					get_word_ce000_prefetch(2);
					if(hardware_bus_error) {
						int pcoffset = 0;
						m68k_setpci_j(oldpc + 2);
						exception2_fetch_opcode(opcode, 2, pcoffset);
						return;
					}
					return;
				}
				 // loop continue: add possible extra cycle(s)
				if(regs.loop_mode & 0xfffe) {
					do_cycles_ce000_internal(regs.loop_mode & 0xfffe);
				}
				m68k_setpci_j(oldpc);
				ipl_fetch_now();
				return;
			}
			regs.loop_mode = 0;
			m68k_setpci_j(oldpc + 4);
			get_word_ce000_prefetch(0);
			if(hardware_bus_error) {
				int pcoffset = 0;
				m68k_setpci_j(oldpc + 2);
				exception2_fetch_opcode(opcode, 0, pcoffset);
				return;
			}
			regs.ir = regs.irc;
			opcode = regs.ir;
			ipl_fetch_next();
			get_word_ce000_prefetch(2);
			if(hardware_bus_error) {
				int pcoffset = 0;
				m68k_setpci_j(oldpc + 2);
				exception2_fetch_opcode(opcode, 2, pcoffset);
				return;
			}
			return;
		}
		get_word_ce000_prefetch(0);
		if(hardware_bus_error) {
			int pcoffset = 0;
			pcoffset = oldpc - m68k_getpci() + 4;
			exception2_fetch_opcode(opcode, 0, pcoffset);
			return;
		}
		if (src) {
			m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
			regs.ir = regs.irc;
			opcode = regs.ir;
			ipl_fetch_next();
			get_word_ce000_prefetch(2);
			if(hardware_bus_error) {
				int pcoffset = 0;
				exception2_fetch_opcode(opcode, 2, 0);
				return;
			}
			return;
		}
		do_cycles_ce000_internal(2);
		pcadjust = 0;
	}
	m68k_setpci_j(oldpc + 4);
	get_word_ce000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		pcoffset += pcadjust;
		exception2_fetch_opcode(opcode, 0, pcoffset);
		return;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	if (!cctrue(12)) {
		m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
	}
	ipl_fetch_next();
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 10 (2/0) */
/* 4 0,0 B */

/* Scc.B (An) (GE) */
void REGPARAM2 op_5cd0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 10; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	do_cycles_ce000_internal(2);
	ipl_fetch_now();
	regs.ir = regs.irc;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	int val = cctrue(12) ? 0xff : 0x00;
	x_put_byte(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 10 (1/1) */
/* 2 0,0   */

/* Scc.B (An)+ (GE) */
void REGPARAM2 op_5cd8_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	do_cycles_ce000_internal(4);
	ipl_fetch_now();
	m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
	regs.ir = regs.irc;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	int val = cctrue(12) ? 0xff : 0x00;
	x_put_byte(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 12 (1/1) */
/* 2 0,0   */

/* Scc.B -(An) (GE) */
void REGPARAM2 op_5ce0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
	do_cycles_ce000_internal(4);
	ipl_fetch_now();
	m68k_areg(regs, srcreg) = srca;
	regs.ir = regs.irc;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	int val = cctrue(12) ? 0xff : 0x00;
	x_put_byte(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 12 (1/1) */
/* 2 0,0   */

/* Scc.B (d16,An) (GE) */
void REGPARAM2 op_5ce8_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	ipl_fetch_now();
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	int val = cctrue(12) ? 0xff : 0x00;
	x_put_byte(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 12 (2/1) */
/* 4 0,0   */

/* Scc.B (d8,An,Xn) (GE) */
void REGPARAM2 op_5cf0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_ce000_prefetch(4));
	do_cycles_ce000_internal(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	ipl_fetch_now();
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	int val = cctrue(12) ? 0xff : 0x00;
	x_put_byte(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (2/1) */
/* 4 4,0   */

/* Scc.B (xxx).W (GE) */
void REGPARAM2 op_5cf8_13_ff(uae_u32 opcode)
{
	OpcodeFamily = 59;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	ipl_fetch_now();
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	int val = cctrue(12) ? 0xff : 0x00;
	x_put_byte(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 12 (2/1) */
/* 4 0,0   */

/* Scc.B (xxx).L (GE) */
void REGPARAM2 op_5cf9_13_ff(uae_u32 opcode)
{
	OpcodeFamily = 59;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	srca |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	ipl_fetch_now();
	regs.ir = regs.irc;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	opcode = regs.ir;
	int val = cctrue(12) ? 0xff : 0x00;
	x_put_byte(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 16 (3/1) */
/* 6 0,0   */

/* Scc.B Dn (LT) */
void REGPARAM2 op_5dc0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 4;  
	int val = cctrue(13) ? 0xff : 0x00;
	int cycles = val ? 2 : 0;
	if (!val) {
		m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff);
	}
	regs.ir = regs.irc;
	if (!val)
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if(!val && regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff);
	if (cycles > 0) do_cycles_ce000_internal(cycles);
	m68k_incpci(2);
	return;
}
/* 4+ (1/0) */
/* 2 0,0   */

/* DBcc.W Dn,#<data>.W (LT) */
void REGPARAM2 op_5dc8_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 58;
	CurrentInstrCycles = 10; 
	int pcadjust = -2;
	uae_s16 src = m68k_dreg(regs, srcreg);
	uae_s16 offs = regs.irc;
	int was_loop_mode = regs.loop_mode;
	regs.loop_mode = 0;
	uaecptr oldpc = m68k_getpci();
	do_cycles_ce000_internal(2);
	if (!cctrue(13)) {
		m68k_incpci((uae_s32)offs + 2);
		if (offs & 1) {
			get_word_ce000_prefetch(-1);
			exception3_read_prefetch(opcode, m68k_getpci());
			return;
		}
		if(offs == -4 && !regs.t1 && loop_mode_table[regs.ird]) {
			if(!was_loop_mode) {
				uae_u16 irc = regs.irc;
				get_word_ce000_prefetch(0);
				if(hardware_bus_error) {
					int pcoffset = 0;
					exception2_fetch_opcode(opcode, 0, 0);
					return;
				}
				get_word_ce000_prefetch(2);
				if(hardware_bus_error) {
					int pcoffset = 0;
					exception2_fetch_opcode(opcode, 2, 0);
					return;
				}
				regs.irc = irc;
			} else {
				do_cycles_ce000_internal(2);
			}
			regs.loop_mode = 1;
			src = m68k_dreg(regs, srcreg);
			m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
			if (src) {
				loop_mode_table[regs.ird](regs.ird);
				 // quick exit if condition false and count expired
				if (!cctrue(13) && (m68k_dreg(regs, srcreg) & 0xffff) == 0) {
					m68k_dreg(regs, srcreg) |= 0xffff;
					 // loop exit: add possible extra cycle(s)
					if(regs.loop_mode >> 16) {
						do_cycles_ce000_internal(regs.loop_mode >> 16);
					}
					regs.loop_mode = 0;
					m68k_setpci_j(oldpc + 4);
					get_word_ce000_prefetch(0);
					if(hardware_bus_error) {
						int pcoffset = 0;
						m68k_setpci_j(oldpc + 2);
						exception2_fetch_opcode(opcode, 0, pcoffset);
						return;
					}
					regs.ir = regs.irc;
					opcode = regs.ir;
					ipl_fetch_next();
					get_word_ce000_prefetch(2);
					if(hardware_bus_error) {
						int pcoffset = 0;
						m68k_setpci_j(oldpc + 2);
						exception2_fetch_opcode(opcode, 2, pcoffset);
						return;
					}
					return;
				}
				 // loop continue: add possible extra cycle(s)
				if(regs.loop_mode & 0xfffe) {
					do_cycles_ce000_internal(regs.loop_mode & 0xfffe);
				}
				m68k_setpci_j(oldpc);
				ipl_fetch_now();
				return;
			}
			regs.loop_mode = 0;
			m68k_setpci_j(oldpc + 4);
			get_word_ce000_prefetch(0);
			if(hardware_bus_error) {
				int pcoffset = 0;
				m68k_setpci_j(oldpc + 2);
				exception2_fetch_opcode(opcode, 0, pcoffset);
				return;
			}
			regs.ir = regs.irc;
			opcode = regs.ir;
			ipl_fetch_next();
			get_word_ce000_prefetch(2);
			if(hardware_bus_error) {
				int pcoffset = 0;
				m68k_setpci_j(oldpc + 2);
				exception2_fetch_opcode(opcode, 2, pcoffset);
				return;
			}
			return;
		}
		get_word_ce000_prefetch(0);
		if(hardware_bus_error) {
			int pcoffset = 0;
			pcoffset = oldpc - m68k_getpci() + 4;
			exception2_fetch_opcode(opcode, 0, pcoffset);
			return;
		}
		if (src) {
			m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
			regs.ir = regs.irc;
			opcode = regs.ir;
			ipl_fetch_next();
			get_word_ce000_prefetch(2);
			if(hardware_bus_error) {
				int pcoffset = 0;
				exception2_fetch_opcode(opcode, 2, 0);
				return;
			}
			return;
		}
		do_cycles_ce000_internal(2);
		pcadjust = 0;
	}
	m68k_setpci_j(oldpc + 4);
	get_word_ce000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		pcoffset += pcadjust;
		exception2_fetch_opcode(opcode, 0, pcoffset);
		return;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	if (!cctrue(13)) {
		m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
	}
	ipl_fetch_next();
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 10 (2/0) */
/* 4 0,0 B */

/* Scc.B (An) (LT) */
void REGPARAM2 op_5dd0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 10; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	do_cycles_ce000_internal(2);
	ipl_fetch_now();
	regs.ir = regs.irc;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	int val = cctrue(13) ? 0xff : 0x00;
	x_put_byte(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 10 (1/1) */
/* 2 0,0   */

/* Scc.B (An)+ (LT) */
void REGPARAM2 op_5dd8_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	do_cycles_ce000_internal(4);
	ipl_fetch_now();
	m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
	regs.ir = regs.irc;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	int val = cctrue(13) ? 0xff : 0x00;
	x_put_byte(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 12 (1/1) */
/* 2 0,0   */

/* Scc.B -(An) (LT) */
void REGPARAM2 op_5de0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
	do_cycles_ce000_internal(4);
	ipl_fetch_now();
	m68k_areg(regs, srcreg) = srca;
	regs.ir = regs.irc;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	int val = cctrue(13) ? 0xff : 0x00;
	x_put_byte(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 12 (1/1) */
/* 2 0,0   */

/* Scc.B (d16,An) (LT) */
void REGPARAM2 op_5de8_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	ipl_fetch_now();
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	int val = cctrue(13) ? 0xff : 0x00;
	x_put_byte(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 12 (2/1) */
/* 4 0,0   */

/* Scc.B (d8,An,Xn) (LT) */
void REGPARAM2 op_5df0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_ce000_prefetch(4));
	do_cycles_ce000_internal(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	ipl_fetch_now();
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	int val = cctrue(13) ? 0xff : 0x00;
	x_put_byte(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (2/1) */
/* 4 4,0   */

/* Scc.B (xxx).W (LT) */
void REGPARAM2 op_5df8_13_ff(uae_u32 opcode)
{
	OpcodeFamily = 59;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	ipl_fetch_now();
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	int val = cctrue(13) ? 0xff : 0x00;
	x_put_byte(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 12 (2/1) */
/* 4 0,0   */

/* Scc.B (xxx).L (LT) */
void REGPARAM2 op_5df9_13_ff(uae_u32 opcode)
{
	OpcodeFamily = 59;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	srca |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	ipl_fetch_now();
	regs.ir = regs.irc;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	opcode = regs.ir;
	int val = cctrue(13) ? 0xff : 0x00;
	x_put_byte(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 16 (3/1) */
/* 6 0,0   */

/* Scc.B Dn (GT) */
void REGPARAM2 op_5ec0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 4;  
	int val = cctrue(14) ? 0xff : 0x00;
	int cycles = val ? 2 : 0;
	if (!val) {
		m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff);
	}
	regs.ir = regs.irc;
	if (!val)
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if(!val && regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff);
	if (cycles > 0) do_cycles_ce000_internal(cycles);
	m68k_incpci(2);
	return;
}
/* 4+ (1/0) */
/* 2 0,0   */

/* DBcc.W Dn,#<data>.W (GT) */
void REGPARAM2 op_5ec8_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 58;
	CurrentInstrCycles = 10; 
	int pcadjust = -2;
	uae_s16 src = m68k_dreg(regs, srcreg);
	uae_s16 offs = regs.irc;
	int was_loop_mode = regs.loop_mode;
	regs.loop_mode = 0;
	uaecptr oldpc = m68k_getpci();
	do_cycles_ce000_internal(2);
	if (!cctrue(14)) {
		m68k_incpci((uae_s32)offs + 2);
		if (offs & 1) {
			get_word_ce000_prefetch(-1);
			exception3_read_prefetch(opcode, m68k_getpci());
			return;
		}
		if(offs == -4 && !regs.t1 && loop_mode_table[regs.ird]) {
			if(!was_loop_mode) {
				uae_u16 irc = regs.irc;
				get_word_ce000_prefetch(0);
				if(hardware_bus_error) {
					int pcoffset = 0;
					exception2_fetch_opcode(opcode, 0, 0);
					return;
				}
				get_word_ce000_prefetch(2);
				if(hardware_bus_error) {
					int pcoffset = 0;
					exception2_fetch_opcode(opcode, 2, 0);
					return;
				}
				regs.irc = irc;
			} else {
				do_cycles_ce000_internal(2);
			}
			regs.loop_mode = 1;
			src = m68k_dreg(regs, srcreg);
			m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
			if (src) {
				loop_mode_table[regs.ird](regs.ird);
				 // quick exit if condition false and count expired
				if (!cctrue(14) && (m68k_dreg(regs, srcreg) & 0xffff) == 0) {
					m68k_dreg(regs, srcreg) |= 0xffff;
					 // loop exit: add possible extra cycle(s)
					if(regs.loop_mode >> 16) {
						do_cycles_ce000_internal(regs.loop_mode >> 16);
					}
					regs.loop_mode = 0;
					m68k_setpci_j(oldpc + 4);
					get_word_ce000_prefetch(0);
					if(hardware_bus_error) {
						int pcoffset = 0;
						m68k_setpci_j(oldpc + 2);
						exception2_fetch_opcode(opcode, 0, pcoffset);
						return;
					}
					regs.ir = regs.irc;
					opcode = regs.ir;
					ipl_fetch_next();
					get_word_ce000_prefetch(2);
					if(hardware_bus_error) {
						int pcoffset = 0;
						m68k_setpci_j(oldpc + 2);
						exception2_fetch_opcode(opcode, 2, pcoffset);
						return;
					}
					return;
				}
				 // loop continue: add possible extra cycle(s)
				if(regs.loop_mode & 0xfffe) {
					do_cycles_ce000_internal(regs.loop_mode & 0xfffe);
				}
				m68k_setpci_j(oldpc);
				ipl_fetch_now();
				return;
			}
			regs.loop_mode = 0;
			m68k_setpci_j(oldpc + 4);
			get_word_ce000_prefetch(0);
			if(hardware_bus_error) {
				int pcoffset = 0;
				m68k_setpci_j(oldpc + 2);
				exception2_fetch_opcode(opcode, 0, pcoffset);
				return;
			}
			regs.ir = regs.irc;
			opcode = regs.ir;
			ipl_fetch_next();
			get_word_ce000_prefetch(2);
			if(hardware_bus_error) {
				int pcoffset = 0;
				m68k_setpci_j(oldpc + 2);
				exception2_fetch_opcode(opcode, 2, pcoffset);
				return;
			}
			return;
		}
		get_word_ce000_prefetch(0);
		if(hardware_bus_error) {
			int pcoffset = 0;
			pcoffset = oldpc - m68k_getpci() + 4;
			exception2_fetch_opcode(opcode, 0, pcoffset);
			return;
		}
		if (src) {
			m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
			regs.ir = regs.irc;
			opcode = regs.ir;
			ipl_fetch_next();
			get_word_ce000_prefetch(2);
			if(hardware_bus_error) {
				int pcoffset = 0;
				exception2_fetch_opcode(opcode, 2, 0);
				return;
			}
			return;
		}
		do_cycles_ce000_internal(2);
		pcadjust = 0;
	}
	m68k_setpci_j(oldpc + 4);
	get_word_ce000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		pcoffset += pcadjust;
		exception2_fetch_opcode(opcode, 0, pcoffset);
		return;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	if (!cctrue(14)) {
		m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
	}
	ipl_fetch_next();
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 10 (2/0) */
/* 4 0,0 B */

/* Scc.B (An) (GT) */
void REGPARAM2 op_5ed0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 10; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	do_cycles_ce000_internal(2);
	ipl_fetch_now();
	regs.ir = regs.irc;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	int val = cctrue(14) ? 0xff : 0x00;
	x_put_byte(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 10 (1/1) */
/* 2 0,0   */

/* Scc.B (An)+ (GT) */
void REGPARAM2 op_5ed8_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	do_cycles_ce000_internal(4);
	ipl_fetch_now();
	m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
	regs.ir = regs.irc;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	int val = cctrue(14) ? 0xff : 0x00;
	x_put_byte(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 12 (1/1) */
/* 2 0,0   */

/* Scc.B -(An) (GT) */
void REGPARAM2 op_5ee0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
	do_cycles_ce000_internal(4);
	ipl_fetch_now();
	m68k_areg(regs, srcreg) = srca;
	regs.ir = regs.irc;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	int val = cctrue(14) ? 0xff : 0x00;
	x_put_byte(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 12 (1/1) */
/* 2 0,0   */

/* Scc.B (d16,An) (GT) */
void REGPARAM2 op_5ee8_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	ipl_fetch_now();
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	int val = cctrue(14) ? 0xff : 0x00;
	x_put_byte(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 12 (2/1) */
/* 4 0,0   */

/* Scc.B (d8,An,Xn) (GT) */
void REGPARAM2 op_5ef0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_ce000_prefetch(4));
	do_cycles_ce000_internal(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	ipl_fetch_now();
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	int val = cctrue(14) ? 0xff : 0x00;
	x_put_byte(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (2/1) */
/* 4 4,0   */

/* Scc.B (xxx).W (GT) */
void REGPARAM2 op_5ef8_13_ff(uae_u32 opcode)
{
	OpcodeFamily = 59;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	ipl_fetch_now();
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	int val = cctrue(14) ? 0xff : 0x00;
	x_put_byte(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 12 (2/1) */
/* 4 0,0   */

/* Scc.B (xxx).L (GT) */
void REGPARAM2 op_5ef9_13_ff(uae_u32 opcode)
{
	OpcodeFamily = 59;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	srca |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	ipl_fetch_now();
	regs.ir = regs.irc;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	opcode = regs.ir;
	int val = cctrue(14) ? 0xff : 0x00;
	x_put_byte(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 16 (3/1) */
/* 6 0,0   */

/* Scc.B Dn (LE) */
void REGPARAM2 op_5fc0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 4;  
	int val = cctrue(15) ? 0xff : 0x00;
	int cycles = val ? 2 : 0;
	if (!val) {
		m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff);
	}
	regs.ir = regs.irc;
	if (!val)
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if(!val && regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff);
	if (cycles > 0) do_cycles_ce000_internal(cycles);
	m68k_incpci(2);
	return;
}
/* 4+ (1/0) */
/* 2 0,0   */

/* DBcc.W Dn,#<data>.W (LE) */
void REGPARAM2 op_5fc8_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 58;
	CurrentInstrCycles = 10; 
	int pcadjust = -2;
	uae_s16 src = m68k_dreg(regs, srcreg);
	uae_s16 offs = regs.irc;
	int was_loop_mode = regs.loop_mode;
	regs.loop_mode = 0;
	uaecptr oldpc = m68k_getpci();
	do_cycles_ce000_internal(2);
	if (!cctrue(15)) {
		m68k_incpci((uae_s32)offs + 2);
		if (offs & 1) {
			get_word_ce000_prefetch(-1);
			exception3_read_prefetch(opcode, m68k_getpci());
			return;
		}
		if(offs == -4 && !regs.t1 && loop_mode_table[regs.ird]) {
			if(!was_loop_mode) {
				uae_u16 irc = regs.irc;
				get_word_ce000_prefetch(0);
				if(hardware_bus_error) {
					int pcoffset = 0;
					exception2_fetch_opcode(opcode, 0, 0);
					return;
				}
				get_word_ce000_prefetch(2);
				if(hardware_bus_error) {
					int pcoffset = 0;
					exception2_fetch_opcode(opcode, 2, 0);
					return;
				}
				regs.irc = irc;
			} else {
				do_cycles_ce000_internal(2);
			}
			regs.loop_mode = 1;
			src = m68k_dreg(regs, srcreg);
			m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
			if (src) {
				loop_mode_table[regs.ird](regs.ird);
				 // quick exit if condition false and count expired
				if (!cctrue(15) && (m68k_dreg(regs, srcreg) & 0xffff) == 0) {
					m68k_dreg(regs, srcreg) |= 0xffff;
					 // loop exit: add possible extra cycle(s)
					if(regs.loop_mode >> 16) {
						do_cycles_ce000_internal(regs.loop_mode >> 16);
					}
					regs.loop_mode = 0;
					m68k_setpci_j(oldpc + 4);
					get_word_ce000_prefetch(0);
					if(hardware_bus_error) {
						int pcoffset = 0;
						m68k_setpci_j(oldpc + 2);
						exception2_fetch_opcode(opcode, 0, pcoffset);
						return;
					}
					regs.ir = regs.irc;
					opcode = regs.ir;
					ipl_fetch_next();
					get_word_ce000_prefetch(2);
					if(hardware_bus_error) {
						int pcoffset = 0;
						m68k_setpci_j(oldpc + 2);
						exception2_fetch_opcode(opcode, 2, pcoffset);
						return;
					}
					return;
				}
				 // loop continue: add possible extra cycle(s)
				if(regs.loop_mode & 0xfffe) {
					do_cycles_ce000_internal(regs.loop_mode & 0xfffe);
				}
				m68k_setpci_j(oldpc);
				ipl_fetch_now();
				return;
			}
			regs.loop_mode = 0;
			m68k_setpci_j(oldpc + 4);
			get_word_ce000_prefetch(0);
			if(hardware_bus_error) {
				int pcoffset = 0;
				m68k_setpci_j(oldpc + 2);
				exception2_fetch_opcode(opcode, 0, pcoffset);
				return;
			}
			regs.ir = regs.irc;
			opcode = regs.ir;
			ipl_fetch_next();
			get_word_ce000_prefetch(2);
			if(hardware_bus_error) {
				int pcoffset = 0;
				m68k_setpci_j(oldpc + 2);
				exception2_fetch_opcode(opcode, 2, pcoffset);
				return;
			}
			return;
		}
		get_word_ce000_prefetch(0);
		if(hardware_bus_error) {
			int pcoffset = 0;
			pcoffset = oldpc - m68k_getpci() + 4;
			exception2_fetch_opcode(opcode, 0, pcoffset);
			return;
		}
		if (src) {
			m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
			regs.ir = regs.irc;
			opcode = regs.ir;
			ipl_fetch_next();
			get_word_ce000_prefetch(2);
			if(hardware_bus_error) {
				int pcoffset = 0;
				exception2_fetch_opcode(opcode, 2, 0);
				return;
			}
			return;
		}
		do_cycles_ce000_internal(2);
		pcadjust = 0;
	}
	m68k_setpci_j(oldpc + 4);
	get_word_ce000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		pcoffset += pcadjust;
		exception2_fetch_opcode(opcode, 0, pcoffset);
		return;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	if (!cctrue(15)) {
		m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
	}
	ipl_fetch_next();
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 10 (2/0) */
/* 4 0,0 B */

/* Scc.B (An) (LE) */
void REGPARAM2 op_5fd0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 10; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	do_cycles_ce000_internal(2);
	ipl_fetch_now();
	regs.ir = regs.irc;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	int val = cctrue(15) ? 0xff : 0x00;
	x_put_byte(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 10 (1/1) */
/* 2 0,0   */

/* Scc.B (An)+ (LE) */
void REGPARAM2 op_5fd8_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	do_cycles_ce000_internal(4);
	ipl_fetch_now();
	m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
	regs.ir = regs.irc;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	int val = cctrue(15) ? 0xff : 0x00;
	x_put_byte(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 12 (1/1) */
/* 2 0,0   */

/* Scc.B -(An) (LE) */
void REGPARAM2 op_5fe0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
	do_cycles_ce000_internal(4);
	ipl_fetch_now();
	m68k_areg(regs, srcreg) = srca;
	regs.ir = regs.irc;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	int val = cctrue(15) ? 0xff : 0x00;
	x_put_byte(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 12 (1/1) */
/* 2 0,0   */

/* Scc.B (d16,An) (LE) */
void REGPARAM2 op_5fe8_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	ipl_fetch_now();
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	int val = cctrue(15) ? 0xff : 0x00;
	x_put_byte(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 12 (2/1) */
/* 4 0,0   */

/* Scc.B (d8,An,Xn) (LE) */
void REGPARAM2 op_5ff0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_ce000_prefetch(4));
	do_cycles_ce000_internal(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	ipl_fetch_now();
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	int val = cctrue(15) ? 0xff : 0x00;
	x_put_byte(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (2/1) */
/* 4 4,0   */

/* Scc.B (xxx).W (LE) */
void REGPARAM2 op_5ff8_13_ff(uae_u32 opcode)
{
	OpcodeFamily = 59;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	ipl_fetch_now();
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	int val = cctrue(15) ? 0xff : 0x00;
	x_put_byte(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 12 (2/1) */
/* 4 0,0   */

/* Scc.B (xxx).L (LE) */
void REGPARAM2 op_5ff9_13_ff(uae_u32 opcode)
{
	OpcodeFamily = 59;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	srca |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	ipl_fetch_now();
	regs.ir = regs.irc;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	opcode = regs.ir;
	int val = cctrue(15) ? 0xff : 0x00;
	x_put_byte(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 16 (3/1) */
/* 6 0,0   */

/* Bcc.W #<data>.W (T) */
void REGPARAM2 op_6000_13_ff(uae_u32 opcode)
{
	OpcodeFamily = 55;
	CurrentInstrCycles = 12; 
	uaecptr oldpc = m68k_getpci();
	uae_s16 src = regs.irc;
	do_cycles_ce000_internal(2);
	if (cctrue(0)) {
		if (src & 1) {
			uaecptr oldpc = m68k_getpci();
			uae_u16 rb = regs.irc;
			m68k_incpci(((uae_s32)src + 2) & ~1);
			get_word_ce000_prefetch(0);
			m68k_setpci_j(oldpc);
			uaecptr newpc = m68k_getpci() + (uae_s32)src + 2;
			m68k_incpci(2);
			regs.read_buffer = rb;
			exception3_read_prefetch(opcode, newpc);
			return;
		}
		m68k_incpci((uae_s32)src + 2);
		int pcadjust = oldpc - m68k_getpci() + 2;
		get_word_ce000_prefetch(0);
		if(hardware_bus_error) {
			int pcoffset = 0;
			pcoffset += pcadjust;
			exception2_fetch_opcode(opcode, 0, pcoffset);
			return;
		}
		regs.ir = regs.irc;
		opcode = regs.ir;
		ipl_fetch_next();
		get_word_ce000_prefetch(2);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 2, pcoffset);
			return;
		}
		return;
	}
	m68k_incpci(4);
	do_cycles_ce000_internal(2);
	get_word_ce000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, pcoffset);
		return;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 12 (2/0) */
/* 4 0,0 B */

/* BccQ.B #<data> (T) */
void REGPARAM2 op_6001_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (uae_s32)(uae_s8)(real_opcode & 255);
	OpcodeFamily = 55;
	CurrentInstrCycles = 6;  
	uaecptr oldpc = m68k_getpci();
	uae_u32 src = srcreg;
	do_cycles_ce000_internal(2);
	if (cctrue(0)) {
		if (src & 1) {
			uaecptr oldpc = m68k_getpci();
			uae_u16 rb = regs.irc;
			m68k_incpci(((uae_s32)src + 2) & ~1);
			get_word_ce000_prefetch(0);
			m68k_setpci_j(oldpc);
			uaecptr newpc = m68k_getpci() + (uae_s32)src + 2;
			m68k_incpci(2);
			regs.read_buffer = rb;
			exception3_read_prefetch(opcode, newpc);
			return;
		}
		m68k_incpci((uae_s32)src + 2);
		int pcadjust = oldpc - m68k_getpci() + 2;
		get_word_ce000_prefetch(0);
		if(hardware_bus_error) {
			int pcoffset = 0;
			pcoffset += pcadjust;
			exception2_fetch_opcode(opcode, 0, pcoffset);
			return;
		}
		regs.ir = regs.irc;
		opcode = regs.ir;
		ipl_fetch_next();
		get_word_ce000_prefetch(2);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 2, pcoffset);
			return;
		}
		return;
	}
	m68k_incpci(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 6 (1/0) */
/* 2 0,0 B */

/* Bcc.L #<data>.L (T) */
void REGPARAM2 op_60ff_13_ff(uae_u32 opcode)
{
	OpcodeFamily = 55;
	CurrentInstrCycles = 8;  
	uaecptr oldpc = m68k_getpci();
	do_cycles_ce000_internal(2);
	if (cctrue(0)) {
		exception3_read_prefetch(opcode, m68k_getpci() + 1);
		return;
	}
	m68k_incpci(2);
	do_cycles_ce000_internal(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 8 (1/0) */
/* 2 0,0   */

/* BSR.W #<data>.W */
void REGPARAM2 op_6100_13_ff(uae_u32 opcode)
{
	OpcodeFamily = 54;
	CurrentInstrCycles = 18; 
	uae_s32 s;
	uae_s16 src = regs.irc;
	s = (uae_s32)src + 2;
	do_cycles_ce000_internal(2);
	uaecptr oldpc = m68k_getpci();
	uaecptr nextpc = oldpc + 4;
	if (m68k_areg(regs, 7) & 1) {
		m68k_incpci(2);
		exception3_write_access(opcode, oldpc + s, sz_word, oldpc, 1);
		return;
	}
	if (s & 1) {
		m68k_incpci(2);
		exception3_read_prefetch_only(opcode, oldpc + s);
		return;
	}
	m68k_areg(regs, 7) -= 4;
	uaecptr dsta = m68k_areg(regs, 7);
	x_put_word(dsta, nextpc >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		exception2_write(opcode, dsta + 0, 0x1, nextpc >> 16, 1);
		return;
	}
	x_put_word(dsta + 2, nextpc);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		exception2_write(opcode, dsta + 2, 0x1, nextpc, 1);
		return;
	}
	m68k_incpci(s);
	#ifdef DEBUGGER
	if (debugmem_trace) {
		branch_stack_push(oldpc, nextpc);
	}
	#endif
	get_word_ce000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, pcoffset);
		return;
	}
	regs.ir = regs.irc;
	ipl_fetch_next();
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 18 (2/2) */
/* 4 0,0 B */

/* BSRQ.B #<data> */
void REGPARAM2 op_6101_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (uae_s32)(uae_s8)(real_opcode & 255);
	OpcodeFamily = 54;
	CurrentInstrCycles = 18; 
	uae_s32 s;
	uae_u32 src = srcreg;
	s = (uae_s32)src + 2;
	do_cycles_ce000_internal(2);
	uaecptr oldpc = m68k_getpci();
	uaecptr nextpc = oldpc + 2;
	if (m68k_areg(regs, 7) & 1) {
		m68k_incpci(2);
		exception3_write_access(opcode, oldpc + s, sz_word, oldpc, 1);
		return;
	}
	if (s & 1) {
		m68k_incpci(2);
		exception3_read_prefetch_only(opcode, oldpc + s);
		return;
	}
	m68k_areg(regs, 7) -= 4;
	uaecptr dsta = m68k_areg(regs, 7);
	x_put_word(dsta, nextpc >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		exception2_write(opcode, dsta + 0, 0x1, nextpc >> 16, 1);
		return;
	}
	x_put_word(dsta + 2, nextpc);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		exception2_write(opcode, dsta + 2, 0x1, nextpc, 1);
		return;
	}
	m68k_incpci(s);
	#ifdef DEBUGGER
	if (debugmem_trace) {
		branch_stack_push(oldpc, nextpc);
	}
	#endif
	get_word_ce000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, pcoffset);
		return;
	}
	regs.ir = regs.irc;
	ipl_fetch_next();
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 18 (2/2) */
/* 2 0,0 B */

/* BSR.L #<data>.L */
void REGPARAM2 op_61ff_13_ff(uae_u32 opcode)
{
	OpcodeFamily = 54;
	CurrentInstrCycles = 18; 
	uae_s32 s;
	uae_u32 src = 0xffffffff;
	s = (uae_s32)src + 2;
	do_cycles_ce000_internal(2);
	uaecptr oldpc = m68k_getpci();
	uaecptr nextpc = oldpc + 2;
	if (m68k_areg(regs, 7) & 1) {
		m68k_incpci(2);
		exception3_write_access(opcode, oldpc + s, sz_word, oldpc, 1);
		return;
	}
	if (s & 1) {
		m68k_incpci(2);
		exception3_read_prefetch_only(opcode, oldpc + s);
		return;
	}
	m68k_areg(regs, 7) -= 4;
	uaecptr dsta = m68k_areg(regs, 7);
	x_put_word(dsta, nextpc >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		exception2_write(opcode, dsta + 0, 0x1, nextpc >> 16, 1);
		return;
	}
	x_put_word(dsta + 2, nextpc);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		exception2_write(opcode, dsta + 2, 0x1, nextpc, 1);
		return;
	}
	m68k_incpci(s);
	#ifdef DEBUGGER
	if (debugmem_trace) {
		branch_stack_push(oldpc, nextpc);
	}
	#endif
	get_word_ce000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, pcoffset);
		return;
	}
	regs.ir = regs.irc;
	ipl_fetch_next();
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 18 (2/2) */
/* 2 0,0 B */

/* Bcc.W #<data>.W (HI) */
void REGPARAM2 op_6200_13_ff(uae_u32 opcode)
{
	OpcodeFamily = 55;
	CurrentInstrCycles = 12; 
	uaecptr oldpc = m68k_getpci();
	uae_s16 src = regs.irc;
	do_cycles_ce000_internal(2);
	if (cctrue(2)) {
		if (src & 1) {
			uaecptr oldpc = m68k_getpci();
			uae_u16 rb = regs.irc;
			m68k_incpci(((uae_s32)src + 2) & ~1);
			get_word_ce000_prefetch(0);
			m68k_setpci_j(oldpc);
			uaecptr newpc = m68k_getpci() + (uae_s32)src + 2;
			m68k_incpci(2);
			regs.read_buffer = rb;
			exception3_read_prefetch(opcode, newpc);
			return;
		}
		m68k_incpci((uae_s32)src + 2);
		int pcadjust = oldpc - m68k_getpci() + 2;
		get_word_ce000_prefetch(0);
		if(hardware_bus_error) {
			int pcoffset = 0;
			pcoffset += pcadjust;
			exception2_fetch_opcode(opcode, 0, pcoffset);
			return;
		}
		regs.ir = regs.irc;
		opcode = regs.ir;
		ipl_fetch_next();
		get_word_ce000_prefetch(2);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 2, pcoffset);
			return;
		}
		return;
	}
	m68k_incpci(4);
	do_cycles_ce000_internal(2);
	get_word_ce000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, pcoffset);
		return;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 12 (2/0) */
/* 4 0,0 B */

/* BccQ.B #<data> (HI) */
void REGPARAM2 op_6201_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (uae_s32)(uae_s8)(real_opcode & 255);
	OpcodeFamily = 55;
	CurrentInstrCycles = 6;  
	uaecptr oldpc = m68k_getpci();
	uae_u32 src = srcreg;
	do_cycles_ce000_internal(2);
	if (cctrue(2)) {
		if (src & 1) {
			uaecptr oldpc = m68k_getpci();
			uae_u16 rb = regs.irc;
			m68k_incpci(((uae_s32)src + 2) & ~1);
			get_word_ce000_prefetch(0);
			m68k_setpci_j(oldpc);
			uaecptr newpc = m68k_getpci() + (uae_s32)src + 2;
			m68k_incpci(2);
			regs.read_buffer = rb;
			exception3_read_prefetch(opcode, newpc);
			return;
		}
		m68k_incpci((uae_s32)src + 2);
		int pcadjust = oldpc - m68k_getpci() + 2;
		get_word_ce000_prefetch(0);
		if(hardware_bus_error) {
			int pcoffset = 0;
			pcoffset += pcadjust;
			exception2_fetch_opcode(opcode, 0, pcoffset);
			return;
		}
		regs.ir = regs.irc;
		opcode = regs.ir;
		ipl_fetch_next();
		get_word_ce000_prefetch(2);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 2, pcoffset);
			return;
		}
		return;
	}
	m68k_incpci(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 6 (1/0) */
/* 2 0,0 B */

/* Bcc.L #<data>.L (HI) */
void REGPARAM2 op_62ff_13_ff(uae_u32 opcode)
{
	OpcodeFamily = 55;
	CurrentInstrCycles = 8;  
	uaecptr oldpc = m68k_getpci();
	do_cycles_ce000_internal(2);
	if (cctrue(2)) {
		exception3_read_prefetch(opcode, m68k_getpci() + 1);
		return;
	}
	m68k_incpci(2);
	do_cycles_ce000_internal(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 8 (1/0) */
/* 2 0,0   */

/* Bcc.W #<data>.W (LS) */
void REGPARAM2 op_6300_13_ff(uae_u32 opcode)
{
	OpcodeFamily = 55;
	CurrentInstrCycles = 12; 
	uaecptr oldpc = m68k_getpci();
	uae_s16 src = regs.irc;
	do_cycles_ce000_internal(2);
	if (cctrue(3)) {
		if (src & 1) {
			uaecptr oldpc = m68k_getpci();
			uae_u16 rb = regs.irc;
			m68k_incpci(((uae_s32)src + 2) & ~1);
			get_word_ce000_prefetch(0);
			m68k_setpci_j(oldpc);
			uaecptr newpc = m68k_getpci() + (uae_s32)src + 2;
			m68k_incpci(2);
			regs.read_buffer = rb;
			exception3_read_prefetch(opcode, newpc);
			return;
		}
		m68k_incpci((uae_s32)src + 2);
		int pcadjust = oldpc - m68k_getpci() + 2;
		get_word_ce000_prefetch(0);
		if(hardware_bus_error) {
			int pcoffset = 0;
			pcoffset += pcadjust;
			exception2_fetch_opcode(opcode, 0, pcoffset);
			return;
		}
		regs.ir = regs.irc;
		opcode = regs.ir;
		ipl_fetch_next();
		get_word_ce000_prefetch(2);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 2, pcoffset);
			return;
		}
		return;
	}
	m68k_incpci(4);
	do_cycles_ce000_internal(2);
	get_word_ce000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, pcoffset);
		return;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 12 (2/0) */
/* 4 0,0 B */

/* BccQ.B #<data> (LS) */
void REGPARAM2 op_6301_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (uae_s32)(uae_s8)(real_opcode & 255);
	OpcodeFamily = 55;
	CurrentInstrCycles = 6;  
	uaecptr oldpc = m68k_getpci();
	uae_u32 src = srcreg;
	do_cycles_ce000_internal(2);
	if (cctrue(3)) {
		if (src & 1) {
			uaecptr oldpc = m68k_getpci();
			uae_u16 rb = regs.irc;
			m68k_incpci(((uae_s32)src + 2) & ~1);
			get_word_ce000_prefetch(0);
			m68k_setpci_j(oldpc);
			uaecptr newpc = m68k_getpci() + (uae_s32)src + 2;
			m68k_incpci(2);
			regs.read_buffer = rb;
			exception3_read_prefetch(opcode, newpc);
			return;
		}
		m68k_incpci((uae_s32)src + 2);
		int pcadjust = oldpc - m68k_getpci() + 2;
		get_word_ce000_prefetch(0);
		if(hardware_bus_error) {
			int pcoffset = 0;
			pcoffset += pcadjust;
			exception2_fetch_opcode(opcode, 0, pcoffset);
			return;
		}
		regs.ir = regs.irc;
		opcode = regs.ir;
		ipl_fetch_next();
		get_word_ce000_prefetch(2);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 2, pcoffset);
			return;
		}
		return;
	}
	m68k_incpci(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 6 (1/0) */
/* 2 0,0 B */

/* Bcc.L #<data>.L (LS) */
void REGPARAM2 op_63ff_13_ff(uae_u32 opcode)
{
	OpcodeFamily = 55;
	CurrentInstrCycles = 8;  
	uaecptr oldpc = m68k_getpci();
	do_cycles_ce000_internal(2);
	if (cctrue(3)) {
		exception3_read_prefetch(opcode, m68k_getpci() + 1);
		return;
	}
	m68k_incpci(2);
	do_cycles_ce000_internal(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 8 (1/0) */
/* 2 0,0   */

/* Bcc.W #<data>.W (CC) */
void REGPARAM2 op_6400_13_ff(uae_u32 opcode)
{
	OpcodeFamily = 55;
	CurrentInstrCycles = 12; 
	uaecptr oldpc = m68k_getpci();
	uae_s16 src = regs.irc;
	do_cycles_ce000_internal(2);
	if (cctrue(4)) {
		if (src & 1) {
			uaecptr oldpc = m68k_getpci();
			uae_u16 rb = regs.irc;
			m68k_incpci(((uae_s32)src + 2) & ~1);
			get_word_ce000_prefetch(0);
			m68k_setpci_j(oldpc);
			uaecptr newpc = m68k_getpci() + (uae_s32)src + 2;
			m68k_incpci(2);
			regs.read_buffer = rb;
			exception3_read_prefetch(opcode, newpc);
			return;
		}
		m68k_incpci((uae_s32)src + 2);
		int pcadjust = oldpc - m68k_getpci() + 2;
		get_word_ce000_prefetch(0);
		if(hardware_bus_error) {
			int pcoffset = 0;
			pcoffset += pcadjust;
			exception2_fetch_opcode(opcode, 0, pcoffset);
			return;
		}
		regs.ir = regs.irc;
		opcode = regs.ir;
		ipl_fetch_next();
		get_word_ce000_prefetch(2);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 2, pcoffset);
			return;
		}
		return;
	}
	m68k_incpci(4);
	do_cycles_ce000_internal(2);
	get_word_ce000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, pcoffset);
		return;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 12 (2/0) */
/* 4 0,0 B */

/* BccQ.B #<data> (CC) */
void REGPARAM2 op_6401_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (uae_s32)(uae_s8)(real_opcode & 255);
	OpcodeFamily = 55;
	CurrentInstrCycles = 6;  
	uaecptr oldpc = m68k_getpci();
	uae_u32 src = srcreg;
	do_cycles_ce000_internal(2);
	if (cctrue(4)) {
		if (src & 1) {
			uaecptr oldpc = m68k_getpci();
			uae_u16 rb = regs.irc;
			m68k_incpci(((uae_s32)src + 2) & ~1);
			get_word_ce000_prefetch(0);
			m68k_setpci_j(oldpc);
			uaecptr newpc = m68k_getpci() + (uae_s32)src + 2;
			m68k_incpci(2);
			regs.read_buffer = rb;
			exception3_read_prefetch(opcode, newpc);
			return;
		}
		m68k_incpci((uae_s32)src + 2);
		int pcadjust = oldpc - m68k_getpci() + 2;
		get_word_ce000_prefetch(0);
		if(hardware_bus_error) {
			int pcoffset = 0;
			pcoffset += pcadjust;
			exception2_fetch_opcode(opcode, 0, pcoffset);
			return;
		}
		regs.ir = regs.irc;
		opcode = regs.ir;
		ipl_fetch_next();
		get_word_ce000_prefetch(2);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 2, pcoffset);
			return;
		}
		return;
	}
	m68k_incpci(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 6 (1/0) */
/* 2 0,0 B */

/* Bcc.L #<data>.L (CC) */
void REGPARAM2 op_64ff_13_ff(uae_u32 opcode)
{
	OpcodeFamily = 55;
	CurrentInstrCycles = 8;  
	uaecptr oldpc = m68k_getpci();
	do_cycles_ce000_internal(2);
	if (cctrue(4)) {
		exception3_read_prefetch(opcode, m68k_getpci() + 1);
		return;
	}
	m68k_incpci(2);
	do_cycles_ce000_internal(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 8 (1/0) */
/* 2 0,0   */

/* Bcc.W #<data>.W (CS) */
void REGPARAM2 op_6500_13_ff(uae_u32 opcode)
{
	OpcodeFamily = 55;
	CurrentInstrCycles = 12; 
	uaecptr oldpc = m68k_getpci();
	uae_s16 src = regs.irc;
	do_cycles_ce000_internal(2);
	if (cctrue(5)) {
		if (src & 1) {
			uaecptr oldpc = m68k_getpci();
			uae_u16 rb = regs.irc;
			m68k_incpci(((uae_s32)src + 2) & ~1);
			get_word_ce000_prefetch(0);
			m68k_setpci_j(oldpc);
			uaecptr newpc = m68k_getpci() + (uae_s32)src + 2;
			m68k_incpci(2);
			regs.read_buffer = rb;
			exception3_read_prefetch(opcode, newpc);
			return;
		}
		m68k_incpci((uae_s32)src + 2);
		int pcadjust = oldpc - m68k_getpci() + 2;
		get_word_ce000_prefetch(0);
		if(hardware_bus_error) {
			int pcoffset = 0;
			pcoffset += pcadjust;
			exception2_fetch_opcode(opcode, 0, pcoffset);
			return;
		}
		regs.ir = regs.irc;
		opcode = regs.ir;
		ipl_fetch_next();
		get_word_ce000_prefetch(2);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 2, pcoffset);
			return;
		}
		return;
	}
	m68k_incpci(4);
	do_cycles_ce000_internal(2);
	get_word_ce000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, pcoffset);
		return;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 12 (2/0) */
/* 4 0,0 B */

/* BccQ.B #<data> (CS) */
void REGPARAM2 op_6501_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (uae_s32)(uae_s8)(real_opcode & 255);
	OpcodeFamily = 55;
	CurrentInstrCycles = 6;  
	uaecptr oldpc = m68k_getpci();
	uae_u32 src = srcreg;
	do_cycles_ce000_internal(2);
	if (cctrue(5)) {
		if (src & 1) {
			uaecptr oldpc = m68k_getpci();
			uae_u16 rb = regs.irc;
			m68k_incpci(((uae_s32)src + 2) & ~1);
			get_word_ce000_prefetch(0);
			m68k_setpci_j(oldpc);
			uaecptr newpc = m68k_getpci() + (uae_s32)src + 2;
			m68k_incpci(2);
			regs.read_buffer = rb;
			exception3_read_prefetch(opcode, newpc);
			return;
		}
		m68k_incpci((uae_s32)src + 2);
		int pcadjust = oldpc - m68k_getpci() + 2;
		get_word_ce000_prefetch(0);
		if(hardware_bus_error) {
			int pcoffset = 0;
			pcoffset += pcadjust;
			exception2_fetch_opcode(opcode, 0, pcoffset);
			return;
		}
		regs.ir = regs.irc;
		opcode = regs.ir;
		ipl_fetch_next();
		get_word_ce000_prefetch(2);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 2, pcoffset);
			return;
		}
		return;
	}
	m68k_incpci(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 6 (1/0) */
/* 2 0,0 B */

/* Bcc.L #<data>.L (CS) */
void REGPARAM2 op_65ff_13_ff(uae_u32 opcode)
{
	OpcodeFamily = 55;
	CurrentInstrCycles = 8;  
	uaecptr oldpc = m68k_getpci();
	do_cycles_ce000_internal(2);
	if (cctrue(5)) {
		exception3_read_prefetch(opcode, m68k_getpci() + 1);
		return;
	}
	m68k_incpci(2);
	do_cycles_ce000_internal(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 8 (1/0) */
/* 2 0,0   */

/* Bcc.W #<data>.W (NE) */
void REGPARAM2 op_6600_13_ff(uae_u32 opcode)
{
	OpcodeFamily = 55;
	CurrentInstrCycles = 12; 
	uaecptr oldpc = m68k_getpci();
	uae_s16 src = regs.irc;
	do_cycles_ce000_internal(2);
	if (cctrue(6)) {
		if (src & 1) {
			uaecptr oldpc = m68k_getpci();
			uae_u16 rb = regs.irc;
			m68k_incpci(((uae_s32)src + 2) & ~1);
			get_word_ce000_prefetch(0);
			m68k_setpci_j(oldpc);
			uaecptr newpc = m68k_getpci() + (uae_s32)src + 2;
			m68k_incpci(2);
			regs.read_buffer = rb;
			exception3_read_prefetch(opcode, newpc);
			return;
		}
		m68k_incpci((uae_s32)src + 2);
		int pcadjust = oldpc - m68k_getpci() + 2;
		get_word_ce000_prefetch(0);
		if(hardware_bus_error) {
			int pcoffset = 0;
			pcoffset += pcadjust;
			exception2_fetch_opcode(opcode, 0, pcoffset);
			return;
		}
		regs.ir = regs.irc;
		opcode = regs.ir;
		ipl_fetch_next();
		get_word_ce000_prefetch(2);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 2, pcoffset);
			return;
		}
		return;
	}
	m68k_incpci(4);
	do_cycles_ce000_internal(2);
	get_word_ce000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, pcoffset);
		return;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 12 (2/0) */
/* 4 0,0 B */

/* BccQ.B #<data> (NE) */
void REGPARAM2 op_6601_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (uae_s32)(uae_s8)(real_opcode & 255);
	OpcodeFamily = 55;
	CurrentInstrCycles = 6;  
	uaecptr oldpc = m68k_getpci();
	uae_u32 src = srcreg;
	do_cycles_ce000_internal(2);
	if (cctrue(6)) {
		if (src & 1) {
			uaecptr oldpc = m68k_getpci();
			uae_u16 rb = regs.irc;
			m68k_incpci(((uae_s32)src + 2) & ~1);
			get_word_ce000_prefetch(0);
			m68k_setpci_j(oldpc);
			uaecptr newpc = m68k_getpci() + (uae_s32)src + 2;
			m68k_incpci(2);
			regs.read_buffer = rb;
			exception3_read_prefetch(opcode, newpc);
			return;
		}
		m68k_incpci((uae_s32)src + 2);
		int pcadjust = oldpc - m68k_getpci() + 2;
		get_word_ce000_prefetch(0);
		if(hardware_bus_error) {
			int pcoffset = 0;
			pcoffset += pcadjust;
			exception2_fetch_opcode(opcode, 0, pcoffset);
			return;
		}
		regs.ir = regs.irc;
		opcode = regs.ir;
		ipl_fetch_next();
		get_word_ce000_prefetch(2);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 2, pcoffset);
			return;
		}
		return;
	}
	m68k_incpci(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 6 (1/0) */
/* 2 0,0 B */

/* Bcc.L #<data>.L (NE) */
void REGPARAM2 op_66ff_13_ff(uae_u32 opcode)
{
	OpcodeFamily = 55;
	CurrentInstrCycles = 8;  
	uaecptr oldpc = m68k_getpci();
	do_cycles_ce000_internal(2);
	if (cctrue(6)) {
		exception3_read_prefetch(opcode, m68k_getpci() + 1);
		return;
	}
	m68k_incpci(2);
	do_cycles_ce000_internal(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 8 (1/0) */
/* 2 0,0   */

/* Bcc.W #<data>.W (EQ) */
void REGPARAM2 op_6700_13_ff(uae_u32 opcode)
{
	OpcodeFamily = 55;
	CurrentInstrCycles = 12; 
	uaecptr oldpc = m68k_getpci();
	uae_s16 src = regs.irc;
	do_cycles_ce000_internal(2);
	if (cctrue(7)) {
		if (src & 1) {
			uaecptr oldpc = m68k_getpci();
			uae_u16 rb = regs.irc;
			m68k_incpci(((uae_s32)src + 2) & ~1);
			get_word_ce000_prefetch(0);
			m68k_setpci_j(oldpc);
			uaecptr newpc = m68k_getpci() + (uae_s32)src + 2;
			m68k_incpci(2);
			regs.read_buffer = rb;
			exception3_read_prefetch(opcode, newpc);
			return;
		}
		m68k_incpci((uae_s32)src + 2);
		int pcadjust = oldpc - m68k_getpci() + 2;
		get_word_ce000_prefetch(0);
		if(hardware_bus_error) {
			int pcoffset = 0;
			pcoffset += pcadjust;
			exception2_fetch_opcode(opcode, 0, pcoffset);
			return;
		}
		regs.ir = regs.irc;
		opcode = regs.ir;
		ipl_fetch_next();
		get_word_ce000_prefetch(2);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 2, pcoffset);
			return;
		}
		return;
	}
	m68k_incpci(4);
	do_cycles_ce000_internal(2);
	get_word_ce000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, pcoffset);
		return;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 12 (2/0) */
/* 4 0,0 B */

/* BccQ.B #<data> (EQ) */
void REGPARAM2 op_6701_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (uae_s32)(uae_s8)(real_opcode & 255);
	OpcodeFamily = 55;
	CurrentInstrCycles = 6;  
	uaecptr oldpc = m68k_getpci();
	uae_u32 src = srcreg;
	do_cycles_ce000_internal(2);
	if (cctrue(7)) {
		if (src & 1) {
			uaecptr oldpc = m68k_getpci();
			uae_u16 rb = regs.irc;
			m68k_incpci(((uae_s32)src + 2) & ~1);
			get_word_ce000_prefetch(0);
			m68k_setpci_j(oldpc);
			uaecptr newpc = m68k_getpci() + (uae_s32)src + 2;
			m68k_incpci(2);
			regs.read_buffer = rb;
			exception3_read_prefetch(opcode, newpc);
			return;
		}
		m68k_incpci((uae_s32)src + 2);
		int pcadjust = oldpc - m68k_getpci() + 2;
		get_word_ce000_prefetch(0);
		if(hardware_bus_error) {
			int pcoffset = 0;
			pcoffset += pcadjust;
			exception2_fetch_opcode(opcode, 0, pcoffset);
			return;
		}
		regs.ir = regs.irc;
		opcode = regs.ir;
		ipl_fetch_next();
		get_word_ce000_prefetch(2);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 2, pcoffset);
			return;
		}
		return;
	}
	m68k_incpci(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 6 (1/0) */
/* 2 0,0 B */

/* Bcc.L #<data>.L (EQ) */
void REGPARAM2 op_67ff_13_ff(uae_u32 opcode)
{
	OpcodeFamily = 55;
	CurrentInstrCycles = 8;  
	uaecptr oldpc = m68k_getpci();
	do_cycles_ce000_internal(2);
	if (cctrue(7)) {
		exception3_read_prefetch(opcode, m68k_getpci() + 1);
		return;
	}
	m68k_incpci(2);
	do_cycles_ce000_internal(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 8 (1/0) */
/* 2 0,0   */

/* Bcc.W #<data>.W (VC) */
void REGPARAM2 op_6800_13_ff(uae_u32 opcode)
{
	OpcodeFamily = 55;
	CurrentInstrCycles = 12; 
	uaecptr oldpc = m68k_getpci();
	uae_s16 src = regs.irc;
	do_cycles_ce000_internal(2);
	if (cctrue(8)) {
		if (src & 1) {
			uaecptr oldpc = m68k_getpci();
			uae_u16 rb = regs.irc;
			m68k_incpci(((uae_s32)src + 2) & ~1);
			get_word_ce000_prefetch(0);
			m68k_setpci_j(oldpc);
			uaecptr newpc = m68k_getpci() + (uae_s32)src + 2;
			m68k_incpci(2);
			regs.read_buffer = rb;
			exception3_read_prefetch(opcode, newpc);
			return;
		}
		m68k_incpci((uae_s32)src + 2);
		int pcadjust = oldpc - m68k_getpci() + 2;
		get_word_ce000_prefetch(0);
		if(hardware_bus_error) {
			int pcoffset = 0;
			pcoffset += pcadjust;
			exception2_fetch_opcode(opcode, 0, pcoffset);
			return;
		}
		regs.ir = regs.irc;
		opcode = regs.ir;
		ipl_fetch_next();
		get_word_ce000_prefetch(2);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 2, pcoffset);
			return;
		}
		return;
	}
	m68k_incpci(4);
	do_cycles_ce000_internal(2);
	get_word_ce000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, pcoffset);
		return;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 12 (2/0) */
/* 4 0,0 B */

/* BccQ.B #<data> (VC) */
void REGPARAM2 op_6801_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (uae_s32)(uae_s8)(real_opcode & 255);
	OpcodeFamily = 55;
	CurrentInstrCycles = 6;  
	uaecptr oldpc = m68k_getpci();
	uae_u32 src = srcreg;
	do_cycles_ce000_internal(2);
	if (cctrue(8)) {
		if (src & 1) {
			uaecptr oldpc = m68k_getpci();
			uae_u16 rb = regs.irc;
			m68k_incpci(((uae_s32)src + 2) & ~1);
			get_word_ce000_prefetch(0);
			m68k_setpci_j(oldpc);
			uaecptr newpc = m68k_getpci() + (uae_s32)src + 2;
			m68k_incpci(2);
			regs.read_buffer = rb;
			exception3_read_prefetch(opcode, newpc);
			return;
		}
		m68k_incpci((uae_s32)src + 2);
		int pcadjust = oldpc - m68k_getpci() + 2;
		get_word_ce000_prefetch(0);
		if(hardware_bus_error) {
			int pcoffset = 0;
			pcoffset += pcadjust;
			exception2_fetch_opcode(opcode, 0, pcoffset);
			return;
		}
		regs.ir = regs.irc;
		opcode = regs.ir;
		ipl_fetch_next();
		get_word_ce000_prefetch(2);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 2, pcoffset);
			return;
		}
		return;
	}
	m68k_incpci(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 6 (1/0) */
/* 2 0,0 B */

/* Bcc.L #<data>.L (VC) */
void REGPARAM2 op_68ff_13_ff(uae_u32 opcode)
{
	OpcodeFamily = 55;
	CurrentInstrCycles = 8;  
	uaecptr oldpc = m68k_getpci();
	do_cycles_ce000_internal(2);
	if (cctrue(8)) {
		exception3_read_prefetch(opcode, m68k_getpci() + 1);
		return;
	}
	m68k_incpci(2);
	do_cycles_ce000_internal(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 8 (1/0) */
/* 2 0,0   */

/* Bcc.W #<data>.W (VS) */
void REGPARAM2 op_6900_13_ff(uae_u32 opcode)
{
	OpcodeFamily = 55;
	CurrentInstrCycles = 12; 
	uaecptr oldpc = m68k_getpci();
	uae_s16 src = regs.irc;
	do_cycles_ce000_internal(2);
	if (cctrue(9)) {
		if (src & 1) {
			uaecptr oldpc = m68k_getpci();
			uae_u16 rb = regs.irc;
			m68k_incpci(((uae_s32)src + 2) & ~1);
			get_word_ce000_prefetch(0);
			m68k_setpci_j(oldpc);
			uaecptr newpc = m68k_getpci() + (uae_s32)src + 2;
			m68k_incpci(2);
			regs.read_buffer = rb;
			exception3_read_prefetch(opcode, newpc);
			return;
		}
		m68k_incpci((uae_s32)src + 2);
		int pcadjust = oldpc - m68k_getpci() + 2;
		get_word_ce000_prefetch(0);
		if(hardware_bus_error) {
			int pcoffset = 0;
			pcoffset += pcadjust;
			exception2_fetch_opcode(opcode, 0, pcoffset);
			return;
		}
		regs.ir = regs.irc;
		opcode = regs.ir;
		ipl_fetch_next();
		get_word_ce000_prefetch(2);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 2, pcoffset);
			return;
		}
		return;
	}
	m68k_incpci(4);
	do_cycles_ce000_internal(2);
	get_word_ce000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, pcoffset);
		return;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 12 (2/0) */
/* 4 0,0 B */

/* BccQ.B #<data> (VS) */
void REGPARAM2 op_6901_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (uae_s32)(uae_s8)(real_opcode & 255);
	OpcodeFamily = 55;
	CurrentInstrCycles = 6;  
	uaecptr oldpc = m68k_getpci();
	uae_u32 src = srcreg;
	do_cycles_ce000_internal(2);
	if (cctrue(9)) {
		if (src & 1) {
			uaecptr oldpc = m68k_getpci();
			uae_u16 rb = regs.irc;
			m68k_incpci(((uae_s32)src + 2) & ~1);
			get_word_ce000_prefetch(0);
			m68k_setpci_j(oldpc);
			uaecptr newpc = m68k_getpci() + (uae_s32)src + 2;
			m68k_incpci(2);
			regs.read_buffer = rb;
			exception3_read_prefetch(opcode, newpc);
			return;
		}
		m68k_incpci((uae_s32)src + 2);
		int pcadjust = oldpc - m68k_getpci() + 2;
		get_word_ce000_prefetch(0);
		if(hardware_bus_error) {
			int pcoffset = 0;
			pcoffset += pcadjust;
			exception2_fetch_opcode(opcode, 0, pcoffset);
			return;
		}
		regs.ir = regs.irc;
		opcode = regs.ir;
		ipl_fetch_next();
		get_word_ce000_prefetch(2);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 2, pcoffset);
			return;
		}
		return;
	}
	m68k_incpci(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 6 (1/0) */
/* 2 0,0 B */

/* Bcc.L #<data>.L (VS) */
void REGPARAM2 op_69ff_13_ff(uae_u32 opcode)
{
	OpcodeFamily = 55;
	CurrentInstrCycles = 8;  
	uaecptr oldpc = m68k_getpci();
	do_cycles_ce000_internal(2);
	if (cctrue(9)) {
		exception3_read_prefetch(opcode, m68k_getpci() + 1);
		return;
	}
	m68k_incpci(2);
	do_cycles_ce000_internal(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 8 (1/0) */
/* 2 0,0   */

/* Bcc.W #<data>.W (PL) */
void REGPARAM2 op_6a00_13_ff(uae_u32 opcode)
{
	OpcodeFamily = 55;
	CurrentInstrCycles = 12; 
	uaecptr oldpc = m68k_getpci();
	uae_s16 src = regs.irc;
	do_cycles_ce000_internal(2);
	if (cctrue(10)) {
		if (src & 1) {
			uaecptr oldpc = m68k_getpci();
			uae_u16 rb = regs.irc;
			m68k_incpci(((uae_s32)src + 2) & ~1);
			get_word_ce000_prefetch(0);
			m68k_setpci_j(oldpc);
			uaecptr newpc = m68k_getpci() + (uae_s32)src + 2;
			m68k_incpci(2);
			regs.read_buffer = rb;
			exception3_read_prefetch(opcode, newpc);
			return;
		}
		m68k_incpci((uae_s32)src + 2);
		int pcadjust = oldpc - m68k_getpci() + 2;
		get_word_ce000_prefetch(0);
		if(hardware_bus_error) {
			int pcoffset = 0;
			pcoffset += pcadjust;
			exception2_fetch_opcode(opcode, 0, pcoffset);
			return;
		}
		regs.ir = regs.irc;
		opcode = regs.ir;
		ipl_fetch_next();
		get_word_ce000_prefetch(2);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 2, pcoffset);
			return;
		}
		return;
	}
	m68k_incpci(4);
	do_cycles_ce000_internal(2);
	get_word_ce000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, pcoffset);
		return;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 12 (2/0) */
/* 4 0,0 B */

/* BccQ.B #<data> (PL) */
void REGPARAM2 op_6a01_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (uae_s32)(uae_s8)(real_opcode & 255);
	OpcodeFamily = 55;
	CurrentInstrCycles = 6;  
	uaecptr oldpc = m68k_getpci();
	uae_u32 src = srcreg;
	do_cycles_ce000_internal(2);
	if (cctrue(10)) {
		if (src & 1) {
			uaecptr oldpc = m68k_getpci();
			uae_u16 rb = regs.irc;
			m68k_incpci(((uae_s32)src + 2) & ~1);
			get_word_ce000_prefetch(0);
			m68k_setpci_j(oldpc);
			uaecptr newpc = m68k_getpci() + (uae_s32)src + 2;
			m68k_incpci(2);
			regs.read_buffer = rb;
			exception3_read_prefetch(opcode, newpc);
			return;
		}
		m68k_incpci((uae_s32)src + 2);
		int pcadjust = oldpc - m68k_getpci() + 2;
		get_word_ce000_prefetch(0);
		if(hardware_bus_error) {
			int pcoffset = 0;
			pcoffset += pcadjust;
			exception2_fetch_opcode(opcode, 0, pcoffset);
			return;
		}
		regs.ir = regs.irc;
		opcode = regs.ir;
		ipl_fetch_next();
		get_word_ce000_prefetch(2);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 2, pcoffset);
			return;
		}
		return;
	}
	m68k_incpci(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 6 (1/0) */
/* 2 0,0 B */

/* Bcc.L #<data>.L (PL) */
void REGPARAM2 op_6aff_13_ff(uae_u32 opcode)
{
	OpcodeFamily = 55;
	CurrentInstrCycles = 8;  
	uaecptr oldpc = m68k_getpci();
	do_cycles_ce000_internal(2);
	if (cctrue(10)) {
		exception3_read_prefetch(opcode, m68k_getpci() + 1);
		return;
	}
	m68k_incpci(2);
	do_cycles_ce000_internal(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 8 (1/0) */
/* 2 0,0   */

/* Bcc.W #<data>.W (MI) */
void REGPARAM2 op_6b00_13_ff(uae_u32 opcode)
{
	OpcodeFamily = 55;
	CurrentInstrCycles = 12; 
	uaecptr oldpc = m68k_getpci();
	uae_s16 src = regs.irc;
	do_cycles_ce000_internal(2);
	if (cctrue(11)) {
		if (src & 1) {
			uaecptr oldpc = m68k_getpci();
			uae_u16 rb = regs.irc;
			m68k_incpci(((uae_s32)src + 2) & ~1);
			get_word_ce000_prefetch(0);
			m68k_setpci_j(oldpc);
			uaecptr newpc = m68k_getpci() + (uae_s32)src + 2;
			m68k_incpci(2);
			regs.read_buffer = rb;
			exception3_read_prefetch(opcode, newpc);
			return;
		}
		m68k_incpci((uae_s32)src + 2);
		int pcadjust = oldpc - m68k_getpci() + 2;
		get_word_ce000_prefetch(0);
		if(hardware_bus_error) {
			int pcoffset = 0;
			pcoffset += pcadjust;
			exception2_fetch_opcode(opcode, 0, pcoffset);
			return;
		}
		regs.ir = regs.irc;
		opcode = regs.ir;
		ipl_fetch_next();
		get_word_ce000_prefetch(2);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 2, pcoffset);
			return;
		}
		return;
	}
	m68k_incpci(4);
	do_cycles_ce000_internal(2);
	get_word_ce000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, pcoffset);
		return;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 12 (2/0) */
/* 4 0,0 B */

/* BccQ.B #<data> (MI) */
void REGPARAM2 op_6b01_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (uae_s32)(uae_s8)(real_opcode & 255);
	OpcodeFamily = 55;
	CurrentInstrCycles = 6;  
	uaecptr oldpc = m68k_getpci();
	uae_u32 src = srcreg;
	do_cycles_ce000_internal(2);
	if (cctrue(11)) {
		if (src & 1) {
			uaecptr oldpc = m68k_getpci();
			uae_u16 rb = regs.irc;
			m68k_incpci(((uae_s32)src + 2) & ~1);
			get_word_ce000_prefetch(0);
			m68k_setpci_j(oldpc);
			uaecptr newpc = m68k_getpci() + (uae_s32)src + 2;
			m68k_incpci(2);
			regs.read_buffer = rb;
			exception3_read_prefetch(opcode, newpc);
			return;
		}
		m68k_incpci((uae_s32)src + 2);
		int pcadjust = oldpc - m68k_getpci() + 2;
		get_word_ce000_prefetch(0);
		if(hardware_bus_error) {
			int pcoffset = 0;
			pcoffset += pcadjust;
			exception2_fetch_opcode(opcode, 0, pcoffset);
			return;
		}
		regs.ir = regs.irc;
		opcode = regs.ir;
		ipl_fetch_next();
		get_word_ce000_prefetch(2);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 2, pcoffset);
			return;
		}
		return;
	}
	m68k_incpci(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 6 (1/0) */
/* 2 0,0 B */

/* Bcc.L #<data>.L (MI) */
void REGPARAM2 op_6bff_13_ff(uae_u32 opcode)
{
	OpcodeFamily = 55;
	CurrentInstrCycles = 8;  
	uaecptr oldpc = m68k_getpci();
	do_cycles_ce000_internal(2);
	if (cctrue(11)) {
		exception3_read_prefetch(opcode, m68k_getpci() + 1);
		return;
	}
	m68k_incpci(2);
	do_cycles_ce000_internal(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 8 (1/0) */
/* 2 0,0   */

/* Bcc.W #<data>.W (GE) */
void REGPARAM2 op_6c00_13_ff(uae_u32 opcode)
{
	OpcodeFamily = 55;
	CurrentInstrCycles = 12; 
	uaecptr oldpc = m68k_getpci();
	uae_s16 src = regs.irc;
	do_cycles_ce000_internal(2);
	if (cctrue(12)) {
		if (src & 1) {
			uaecptr oldpc = m68k_getpci();
			uae_u16 rb = regs.irc;
			m68k_incpci(((uae_s32)src + 2) & ~1);
			get_word_ce000_prefetch(0);
			m68k_setpci_j(oldpc);
			uaecptr newpc = m68k_getpci() + (uae_s32)src + 2;
			m68k_incpci(2);
			regs.read_buffer = rb;
			exception3_read_prefetch(opcode, newpc);
			return;
		}
		m68k_incpci((uae_s32)src + 2);
		int pcadjust = oldpc - m68k_getpci() + 2;
		get_word_ce000_prefetch(0);
		if(hardware_bus_error) {
			int pcoffset = 0;
			pcoffset += pcadjust;
			exception2_fetch_opcode(opcode, 0, pcoffset);
			return;
		}
		regs.ir = regs.irc;
		opcode = regs.ir;
		ipl_fetch_next();
		get_word_ce000_prefetch(2);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 2, pcoffset);
			return;
		}
		return;
	}
	m68k_incpci(4);
	do_cycles_ce000_internal(2);
	get_word_ce000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, pcoffset);
		return;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 12 (2/0) */
/* 4 0,0 B */

/* BccQ.B #<data> (GE) */
void REGPARAM2 op_6c01_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (uae_s32)(uae_s8)(real_opcode & 255);
	OpcodeFamily = 55;
	CurrentInstrCycles = 6;  
	uaecptr oldpc = m68k_getpci();
	uae_u32 src = srcreg;
	do_cycles_ce000_internal(2);
	if (cctrue(12)) {
		if (src & 1) {
			uaecptr oldpc = m68k_getpci();
			uae_u16 rb = regs.irc;
			m68k_incpci(((uae_s32)src + 2) & ~1);
			get_word_ce000_prefetch(0);
			m68k_setpci_j(oldpc);
			uaecptr newpc = m68k_getpci() + (uae_s32)src + 2;
			m68k_incpci(2);
			regs.read_buffer = rb;
			exception3_read_prefetch(opcode, newpc);
			return;
		}
		m68k_incpci((uae_s32)src + 2);
		int pcadjust = oldpc - m68k_getpci() + 2;
		get_word_ce000_prefetch(0);
		if(hardware_bus_error) {
			int pcoffset = 0;
			pcoffset += pcadjust;
			exception2_fetch_opcode(opcode, 0, pcoffset);
			return;
		}
		regs.ir = regs.irc;
		opcode = regs.ir;
		ipl_fetch_next();
		get_word_ce000_prefetch(2);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 2, pcoffset);
			return;
		}
		return;
	}
	m68k_incpci(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 6 (1/0) */
/* 2 0,0 B */

/* Bcc.L #<data>.L (GE) */
void REGPARAM2 op_6cff_13_ff(uae_u32 opcode)
{
	OpcodeFamily = 55;
	CurrentInstrCycles = 8;  
	uaecptr oldpc = m68k_getpci();
	do_cycles_ce000_internal(2);
	if (cctrue(12)) {
		exception3_read_prefetch(opcode, m68k_getpci() + 1);
		return;
	}
	m68k_incpci(2);
	do_cycles_ce000_internal(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 8 (1/0) */
/* 2 0,0   */

/* Bcc.W #<data>.W (LT) */
void REGPARAM2 op_6d00_13_ff(uae_u32 opcode)
{
	OpcodeFamily = 55;
	CurrentInstrCycles = 12; 
	uaecptr oldpc = m68k_getpci();
	uae_s16 src = regs.irc;
	do_cycles_ce000_internal(2);
	if (cctrue(13)) {
		if (src & 1) {
			uaecptr oldpc = m68k_getpci();
			uae_u16 rb = regs.irc;
			m68k_incpci(((uae_s32)src + 2) & ~1);
			get_word_ce000_prefetch(0);
			m68k_setpci_j(oldpc);
			uaecptr newpc = m68k_getpci() + (uae_s32)src + 2;
			m68k_incpci(2);
			regs.read_buffer = rb;
			exception3_read_prefetch(opcode, newpc);
			return;
		}
		m68k_incpci((uae_s32)src + 2);
		int pcadjust = oldpc - m68k_getpci() + 2;
		get_word_ce000_prefetch(0);
		if(hardware_bus_error) {
			int pcoffset = 0;
			pcoffset += pcadjust;
			exception2_fetch_opcode(opcode, 0, pcoffset);
			return;
		}
		regs.ir = regs.irc;
		opcode = regs.ir;
		ipl_fetch_next();
		get_word_ce000_prefetch(2);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 2, pcoffset);
			return;
		}
		return;
	}
	m68k_incpci(4);
	do_cycles_ce000_internal(2);
	get_word_ce000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, pcoffset);
		return;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 12 (2/0) */
/* 4 0,0 B */

/* BccQ.B #<data> (LT) */
void REGPARAM2 op_6d01_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (uae_s32)(uae_s8)(real_opcode & 255);
	OpcodeFamily = 55;
	CurrentInstrCycles = 6;  
	uaecptr oldpc = m68k_getpci();
	uae_u32 src = srcreg;
	do_cycles_ce000_internal(2);
	if (cctrue(13)) {
		if (src & 1) {
			uaecptr oldpc = m68k_getpci();
			uae_u16 rb = regs.irc;
			m68k_incpci(((uae_s32)src + 2) & ~1);
			get_word_ce000_prefetch(0);
			m68k_setpci_j(oldpc);
			uaecptr newpc = m68k_getpci() + (uae_s32)src + 2;
			m68k_incpci(2);
			regs.read_buffer = rb;
			exception3_read_prefetch(opcode, newpc);
			return;
		}
		m68k_incpci((uae_s32)src + 2);
		int pcadjust = oldpc - m68k_getpci() + 2;
		get_word_ce000_prefetch(0);
		if(hardware_bus_error) {
			int pcoffset = 0;
			pcoffset += pcadjust;
			exception2_fetch_opcode(opcode, 0, pcoffset);
			return;
		}
		regs.ir = regs.irc;
		opcode = regs.ir;
		ipl_fetch_next();
		get_word_ce000_prefetch(2);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 2, pcoffset);
			return;
		}
		return;
	}
	m68k_incpci(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 6 (1/0) */
/* 2 0,0 B */

/* Bcc.L #<data>.L (LT) */
void REGPARAM2 op_6dff_13_ff(uae_u32 opcode)
{
	OpcodeFamily = 55;
	CurrentInstrCycles = 8;  
	uaecptr oldpc = m68k_getpci();
	do_cycles_ce000_internal(2);
	if (cctrue(13)) {
		exception3_read_prefetch(opcode, m68k_getpci() + 1);
		return;
	}
	m68k_incpci(2);
	do_cycles_ce000_internal(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 8 (1/0) */
/* 2 0,0   */

/* Bcc.W #<data>.W (GT) */
void REGPARAM2 op_6e00_13_ff(uae_u32 opcode)
{
	OpcodeFamily = 55;
	CurrentInstrCycles = 12; 
	uaecptr oldpc = m68k_getpci();
	uae_s16 src = regs.irc;
	do_cycles_ce000_internal(2);
	if (cctrue(14)) {
		if (src & 1) {
			uaecptr oldpc = m68k_getpci();
			uae_u16 rb = regs.irc;
			m68k_incpci(((uae_s32)src + 2) & ~1);
			get_word_ce000_prefetch(0);
			m68k_setpci_j(oldpc);
			uaecptr newpc = m68k_getpci() + (uae_s32)src + 2;
			m68k_incpci(2);
			regs.read_buffer = rb;
			exception3_read_prefetch(opcode, newpc);
			return;
		}
		m68k_incpci((uae_s32)src + 2);
		int pcadjust = oldpc - m68k_getpci() + 2;
		get_word_ce000_prefetch(0);
		if(hardware_bus_error) {
			int pcoffset = 0;
			pcoffset += pcadjust;
			exception2_fetch_opcode(opcode, 0, pcoffset);
			return;
		}
		regs.ir = regs.irc;
		opcode = regs.ir;
		ipl_fetch_next();
		get_word_ce000_prefetch(2);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 2, pcoffset);
			return;
		}
		return;
	}
	m68k_incpci(4);
	do_cycles_ce000_internal(2);
	get_word_ce000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, pcoffset);
		return;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 12 (2/0) */
/* 4 0,0 B */

/* BccQ.B #<data> (GT) */
void REGPARAM2 op_6e01_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (uae_s32)(uae_s8)(real_opcode & 255);
	OpcodeFamily = 55;
	CurrentInstrCycles = 6;  
	uaecptr oldpc = m68k_getpci();
	uae_u32 src = srcreg;
	do_cycles_ce000_internal(2);
	if (cctrue(14)) {
		if (src & 1) {
			uaecptr oldpc = m68k_getpci();
			uae_u16 rb = regs.irc;
			m68k_incpci(((uae_s32)src + 2) & ~1);
			get_word_ce000_prefetch(0);
			m68k_setpci_j(oldpc);
			uaecptr newpc = m68k_getpci() + (uae_s32)src + 2;
			m68k_incpci(2);
			regs.read_buffer = rb;
			exception3_read_prefetch(opcode, newpc);
			return;
		}
		m68k_incpci((uae_s32)src + 2);
		int pcadjust = oldpc - m68k_getpci() + 2;
		get_word_ce000_prefetch(0);
		if(hardware_bus_error) {
			int pcoffset = 0;
			pcoffset += pcadjust;
			exception2_fetch_opcode(opcode, 0, pcoffset);
			return;
		}
		regs.ir = regs.irc;
		opcode = regs.ir;
		ipl_fetch_next();
		get_word_ce000_prefetch(2);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 2, pcoffset);
			return;
		}
		return;
	}
	m68k_incpci(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 6 (1/0) */
/* 2 0,0 B */

/* Bcc.L #<data>.L (GT) */
void REGPARAM2 op_6eff_13_ff(uae_u32 opcode)
{
	OpcodeFamily = 55;
	CurrentInstrCycles = 8;  
	uaecptr oldpc = m68k_getpci();
	do_cycles_ce000_internal(2);
	if (cctrue(14)) {
		exception3_read_prefetch(opcode, m68k_getpci() + 1);
		return;
	}
	m68k_incpci(2);
	do_cycles_ce000_internal(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 8 (1/0) */
/* 2 0,0   */

/* Bcc.W #<data>.W (LE) */
void REGPARAM2 op_6f00_13_ff(uae_u32 opcode)
{
	OpcodeFamily = 55;
	CurrentInstrCycles = 12; 
	uaecptr oldpc = m68k_getpci();
	uae_s16 src = regs.irc;
	do_cycles_ce000_internal(2);
	if (cctrue(15)) {
		if (src & 1) {
			uaecptr oldpc = m68k_getpci();
			uae_u16 rb = regs.irc;
			m68k_incpci(((uae_s32)src + 2) & ~1);
			get_word_ce000_prefetch(0);
			m68k_setpci_j(oldpc);
			uaecptr newpc = m68k_getpci() + (uae_s32)src + 2;
			m68k_incpci(2);
			regs.read_buffer = rb;
			exception3_read_prefetch(opcode, newpc);
			return;
		}
		m68k_incpci((uae_s32)src + 2);
		int pcadjust = oldpc - m68k_getpci() + 2;
		get_word_ce000_prefetch(0);
		if(hardware_bus_error) {
			int pcoffset = 0;
			pcoffset += pcadjust;
			exception2_fetch_opcode(opcode, 0, pcoffset);
			return;
		}
		regs.ir = regs.irc;
		opcode = regs.ir;
		ipl_fetch_next();
		get_word_ce000_prefetch(2);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 2, pcoffset);
			return;
		}
		return;
	}
	m68k_incpci(4);
	do_cycles_ce000_internal(2);
	get_word_ce000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, pcoffset);
		return;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 12 (2/0) */
/* 4 0,0 B */

/* BccQ.B #<data> (LE) */
void REGPARAM2 op_6f01_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (uae_s32)(uae_s8)(real_opcode & 255);
	OpcodeFamily = 55;
	CurrentInstrCycles = 6;  
	uaecptr oldpc = m68k_getpci();
	uae_u32 src = srcreg;
	do_cycles_ce000_internal(2);
	if (cctrue(15)) {
		if (src & 1) {
			uaecptr oldpc = m68k_getpci();
			uae_u16 rb = regs.irc;
			m68k_incpci(((uae_s32)src + 2) & ~1);
			get_word_ce000_prefetch(0);
			m68k_setpci_j(oldpc);
			uaecptr newpc = m68k_getpci() + (uae_s32)src + 2;
			m68k_incpci(2);
			regs.read_buffer = rb;
			exception3_read_prefetch(opcode, newpc);
			return;
		}
		m68k_incpci((uae_s32)src + 2);
		int pcadjust = oldpc - m68k_getpci() + 2;
		get_word_ce000_prefetch(0);
		if(hardware_bus_error) {
			int pcoffset = 0;
			pcoffset += pcadjust;
			exception2_fetch_opcode(opcode, 0, pcoffset);
			return;
		}
		regs.ir = regs.irc;
		opcode = regs.ir;
		ipl_fetch_next();
		get_word_ce000_prefetch(2);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 2, pcoffset);
			return;
		}
		return;
	}
	m68k_incpci(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 6 (1/0) */
/* 2 0,0 B */

/* Bcc.L #<data>.L (LE) */
void REGPARAM2 op_6fff_13_ff(uae_u32 opcode)
{
	OpcodeFamily = 55;
	CurrentInstrCycles = 8;  
	uaecptr oldpc = m68k_getpci();
	do_cycles_ce000_internal(2);
	if (cctrue(15)) {
		exception3_read_prefetch(opcode, m68k_getpci() + 1);
		return;
	}
	m68k_incpci(2);
	do_cycles_ce000_internal(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 8 (1/0) */
/* 2 0,0   */

/* MOVEQ.L #<data>,Dn */
void REGPARAM2 op_7000_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (uae_s32)(uae_s8)(real_opcode & 255);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 4;  
	uae_u32 src = srcreg;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	m68k_dreg(regs, dstreg) = (src);
	m68k_incpci(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 4 (1/0) */
/* 2 0,0   */

/* OR.B Dn,Dn */
void REGPARAM2 op_8000_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 4;  
	uae_s8 src = m68k_dreg(regs, srcreg);
	uae_s8 dst = m68k_dreg(regs, dstreg);
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 4 (1/0) */
/* 2 0,0   */

/* OR.B (An),Dn */
void REGPARAM2 op_8010_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 8;  
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	uae_s8 dst = m68k_dreg(regs, dstreg);
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
	if(!loop_mode) {
		regs.ir = regs.irc;
		opcode = regs.ir;
		get_word_ce000_prefetch(4);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return;
		}
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	if (loop_mode) {
		do_cycles_ce000_internal(4);
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return;
}
/* 8 (2/0) */
/* 2 0,0   */

/* OR.B (An)+,Dn */
void REGPARAM2 op_8018_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 8;  
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
	uae_s8 dst = m68k_dreg(regs, dstreg);
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
	if(!loop_mode) {
		regs.ir = regs.irc;
		opcode = regs.ir;
		get_word_ce000_prefetch(4);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return;
		}
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	if (loop_mode) {
		do_cycles_ce000_internal(4);
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return;
}
/* 8 (2/0) */
/* 2 0,0   */

/* OR.B -(An),Dn */
void REGPARAM2 op_8020_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 10; 
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
	do_cycles_ce000_internal(2);
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	m68k_areg(regs, srcreg) = srca;
	uae_s8 dst = m68k_dreg(regs, dstreg);
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
	if(!loop_mode) {
		regs.ir = regs.irc;
		opcode = regs.ir;
		get_word_ce000_prefetch(4);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return;
		}
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	if (loop_mode) {
		do_cycles_ce000_internal(4);
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return;
}
/* 10 (2/0) */
/* 2 0,0   */

/* OR.B (d16,An),Dn */
void REGPARAM2 op_8028_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	uae_s8 dst = m68k_dreg(regs, dstreg);
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 12 (3/0) */
/* 4 0,0   */

/* OR.B (d8,An,Xn),Dn */
void REGPARAM2 op_8030_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	do_cycles_ce000_internal(2);
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	uae_s8 dst = m68k_dreg(regs, dstreg);
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 14 (3/0) */
/* 4 4,0   */

/* OR.B (xxx).W,Dn */
void REGPARAM2 op_8038_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	uae_s8 dst = m68k_dreg(regs, dstreg);
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 12 (3/0) */
/* 4 0,0   */

/* OR.B (xxx).L,Dn */
void REGPARAM2 op_8039_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	srca |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	uae_s8 dst = m68k_dreg(regs, dstreg);
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 16 (4/0) */
/* 6 0,0   */

/* OR.B (d16,PC),Dn */
void REGPARAM2 op_803a_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_getpci() + 2;
	srca += (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 2);
		return;
	}
	uae_s8 dst = m68k_dreg(regs, dstreg);
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 12 (3/0) */
/* 4 0,0   */

/* OR.B (d8,PC,Xn),Dn */
void REGPARAM2 op_803b_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	uaecptr tmppc = m68k_getpci() + 2;
	do_cycles_ce000_internal(2);
	srca = get_disp_ea_000(tmppc, get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 2);
		return;
	}
	uae_s8 dst = m68k_dreg(regs, dstreg);
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 14 (3/0) */
/* 4 4,0   */

/* OR.B #<data>.B,Dn */
void REGPARAM2 op_803c_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 8;  
	uae_s8 src = (uae_u8)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uae_s8 dst = m68k_dreg(regs, dstreg);
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 8 (2/0) */
/* 4 0,0   */

/* OR.W Dn,Dn */
void REGPARAM2 op_8040_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 4;  
	uae_s16 src = m68k_dreg(regs, srcreg);
	uae_s16 dst = m68k_dreg(regs, dstreg);
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 4 (1/0) */
/* 2 0,0   */

/* OR.W (An),Dn */
void REGPARAM2 op_8050_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 8;  
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access2(opcode, srca, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
	if(!loop_mode) {
		regs.ir = regs.irc;
		opcode = regs.ir;
		get_word_ce000_prefetch(4);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return;
		}
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	if (loop_mode) {
		do_cycles_ce000_internal(4);
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return;
}
/* 8 (2/0) */
/* 2 0,0   */

/* OR.W (An)+,Dn */
void REGPARAM2 op_8058_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 8;  
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_areg(regs, srcreg) += 2 + 0;
		m68k_incpci(2);
		exception3_read_access2(opcode, srca, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) += 2 + 0;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	m68k_areg(regs, srcreg) += 2;
	uae_s16 dst = m68k_dreg(regs, dstreg);
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
	if(!loop_mode) {
		regs.ir = regs.irc;
		opcode = regs.ir;
		get_word_ce000_prefetch(4);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return;
		}
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	if (loop_mode) {
		do_cycles_ce000_internal(4);
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return;
}
/* 8 (2/0) */
/* 2 0,0   */

/* OR.W -(An),Dn */
void REGPARAM2 op_8060_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 10; 
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - 2;
	do_cycles_ce000_internal(2);
	if (srca & 1) {
		m68k_areg(regs, srcreg) = srca;
		m68k_incpci(2);
		exception3_read_access2(opcode, srca, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	m68k_areg(regs, srcreg) = srca;
	uae_s16 dst = m68k_dreg(regs, dstreg);
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
	if(!loop_mode) {
		regs.ir = regs.irc;
		opcode = regs.ir;
		get_word_ce000_prefetch(4);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return;
		}
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	if (loop_mode) {
		do_cycles_ce000_internal(4);
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return;
}
/* 10 (2/0) */
/* 2 0,0   */

/* OR.W (d16,An),Dn */
void REGPARAM2 op_8068_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 12 (3/0) */
/* 4 0,0   */

/* OR.W (d8,An,Xn),Dn */
void REGPARAM2 op_8070_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	do_cycles_ce000_internal(2);
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 14 (3/0) */
/* 4 4,0   */

/* OR.W (xxx).W,Dn */
void REGPARAM2 op_8078_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	if (srca & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 12 (3/0) */
/* 4 0,0   */

/* OR.W (xxx).L,Dn */
void REGPARAM2 op_8079_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	srca |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	if (srca & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 16 (4/0) */
/* 6 0,0   */

/* OR.W (d16,PC),Dn */
void REGPARAM2 op_807a_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_getpci() + 2;
	srca += (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 2);
		return;
	}
	ipl_fetch_now();
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 12 (3/0) */
/* 4 0,0   */

/* OR.W (d8,PC,Xn),Dn */
void REGPARAM2 op_807b_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	uaecptr tmppc = m68k_getpci() + 2;
	do_cycles_ce000_internal(2);
	srca = get_disp_ea_000(tmppc, get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 2);
		return;
	}
	ipl_fetch_now();
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 14 (3/0) */
/* 4 4,0   */

/* OR.W #<data>.W,Dn */
void REGPARAM2 op_807c_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 8;  
	uae_s16 src = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 8 (2/0) */
/* 4 0,0   */

/* OR.L Dn,Dn */
void REGPARAM2 op_8080_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 6;  
	uae_s32 src = m68k_dreg(regs, srcreg);
	uae_s32 dst = m68k_dreg(regs, dstreg);
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		m68k_dreg(regs, dstreg) = (src);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	do_cycles_ce000_internal(2);
	m68k_dreg(regs, dstreg) = (src);
	m68k_incpci(2);
	return;
}
/* 6 (1/0) */
/* 2 0,0   */

/* OR.L (An),Dn */
void REGPARAM2 op_8090_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 14; 
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_ce000_prefetch(4);
		if(hardware_bus_error) {
			int pcoffset = 0;
			m68k_dreg(regs, dstreg) = (src);
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return;
		}
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	do_cycles_ce000_internal(2);
	if(loop_mode & 0xfffe) {
		do_cycles_ce000_internal(loop_mode & 0xfffe);
		loop_mode = 1;
	}
	m68k_dreg(regs, dstreg) = (src);
	if (loop_mode) {
		do_cycles_ce000_internal(4);
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return;
}
/* 14 (3/0) */
/* 2 0,0   */

/* OR.L (An)+,Dn */
void REGPARAM2 op_8098_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 14; 
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	m68k_areg(regs, srcreg) += 4;
	uae_s32 dst = m68k_dreg(regs, dstreg);
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_ce000_prefetch(4);
		if(hardware_bus_error) {
			int pcoffset = 0;
			m68k_dreg(regs, dstreg) = (src);
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return;
		}
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	do_cycles_ce000_internal(2);
	if(loop_mode & 0xfffe) {
		do_cycles_ce000_internal(loop_mode & 0xfffe);
		loop_mode = 1;
	}
	m68k_dreg(regs, dstreg) = (src);
	if (loop_mode) {
		do_cycles_ce000_internal(4);
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return;
}
/* 14 (3/0) */
/* 2 0,0   */

/* OR.L -(An),Dn */
void REGPARAM2 op_80a0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 16; 
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - 4;
	do_cycles_ce000_internal(2);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	m68k_areg(regs, srcreg) = srca;
	uae_s32 dst = m68k_dreg(regs, dstreg);
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_ce000_prefetch(4);
		if(hardware_bus_error) {
			int pcoffset = 0;
			m68k_dreg(regs, dstreg) = (src);
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return;
		}
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	do_cycles_ce000_internal(2);
	if(loop_mode & 0xfffe) {
		do_cycles_ce000_internal(loop_mode & 0xfffe);
		loop_mode = 1;
	}
	m68k_dreg(regs, dstreg) = (src);
	if (loop_mode) {
		do_cycles_ce000_internal(4);
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return;
}
/* 16 (3/0) */
/* 2 0,0   */

/* OR.L (d16,An),Dn */
void REGPARAM2 op_80a8_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		m68k_dreg(regs, dstreg) = (src);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	do_cycles_ce000_internal(2);
	m68k_dreg(regs, dstreg) = (src);
	m68k_incpci(4);
	return;
}
/* 18 (4/0) */
/* 4 0,0   */

/* OR.L (d8,An,Xn),Dn */
void REGPARAM2 op_80b0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	do_cycles_ce000_internal(2);
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		m68k_dreg(regs, dstreg) = (src);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	do_cycles_ce000_internal(2);
	m68k_dreg(regs, dstreg) = (src);
	m68k_incpci(4);
	return;
}
/* 20 (4/0) */
/* 4 4,0   */

/* OR.L (xxx).W,Dn */
void REGPARAM2 op_80b8_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	if (srca & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		m68k_dreg(regs, dstreg) = (src);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	do_cycles_ce000_internal(2);
	m68k_dreg(regs, dstreg) = (src);
	m68k_incpci(4);
	return;
}
/* 18 (4/0) */
/* 4 0,0   */

/* OR.L (xxx).L,Dn */
void REGPARAM2 op_80b9_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 22; 
	uaecptr srca;
	srca = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	srca |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	if (srca & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		m68k_dreg(regs, dstreg) = (src);
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	do_cycles_ce000_internal(2);
	m68k_dreg(regs, dstreg) = (src);
	m68k_incpci(6);
	return;
}
/* 22 (5/0) */
/* 6 0,0   */

/* OR.L (d16,PC),Dn */
void REGPARAM2 op_80ba_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	srca = m68k_getpci() + 2;
	srca += (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 2);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return;
	}
	ipl_fetch_now();
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 2);
		return;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		m68k_dreg(regs, dstreg) = (src);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	do_cycles_ce000_internal(2);
	m68k_dreg(regs, dstreg) = (src);
	m68k_incpci(4);
	return;
}
/* 18 (4/0) */
/* 4 0,0   */

/* OR.L (d8,PC,Xn),Dn */
void REGPARAM2 op_80bb_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	uaecptr tmppc = m68k_getpci() + 2;
	do_cycles_ce000_internal(2);
	srca = get_disp_ea_000(tmppc, get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 2);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return;
	}
	ipl_fetch_now();
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 2);
		return;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		m68k_dreg(regs, dstreg) = (src);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	do_cycles_ce000_internal(2);
	m68k_dreg(regs, dstreg) = (src);
	m68k_incpci(4);
	return;
}
/* 20 (4/0) */
/* 4 4,0   */

/* OR.L #<data>.L,Dn */
void REGPARAM2 op_80bc_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 16; 
	uae_s32 src;
	src = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	src |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		m68k_dreg(regs, dstreg) = (src);
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	do_cycles_ce000_internal(4);
	m68k_dreg(regs, dstreg) = (src);
	m68k_incpci(6);
	return;
}
/* 16 (3/0) */
/* 6 0,0   */

/* DIVU.W Dn,Dn */
void REGPARAM2 op_80c0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 60;
	CurrentInstrCycles = 4;  
	uae_s16 src = m68k_dreg(regs, srcreg);
	uae_s32 dst = m68k_dreg(regs, dstreg);
	if (src == 0) {
		divbyzero_special(0, dst);
		m68k_incpci(2);
		do_cycles_ce000_internal(4);
		Exception_cpu(5);
		return;
	}
	uae_u32 newv = (uae_u32)dst / (uae_u32)(uae_u16)src;
	uae_u32 rem = (uae_u32)dst % (uae_u32)(uae_u16)src;
	int cycles = getDivu68kCycles((uae_u32)dst, (uae_u16)src);
	do_cycles_ce000_internal(cycles);
	if (newv > 0xffff) {
		setdivuflags((uae_u32)dst, (uae_u16)src);
	} else {
		CLEAR_CZNV();
		SET_ZFLG(((uae_s16)(newv)) == 0);
		SET_NFLG(((uae_s16)(newv)) < 0);
		newv = (newv & 0xffff) | ((uae_u32)rem << 16);
		m68k_dreg(regs, dstreg) = (newv);
	}
	ipl_fetch_next();
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 4+ (1/0) */
/* 2 0,0   */

/* DIVU.W (An),Dn */
void REGPARAM2 op_80d0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 60;
	CurrentInstrCycles = 8;  
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access2(opcode, srca, 1, 1);
		return;
	}
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	if (src == 0) {
		divbyzero_special(0, dst);
		m68k_incpci(2);
		do_cycles_ce000_internal(4);
		Exception_cpu(5);
		return;
	}
	uae_u32 newv = (uae_u32)dst / (uae_u32)(uae_u16)src;
	uae_u32 rem = (uae_u32)dst % (uae_u32)(uae_u16)src;
	int cycles = getDivu68kCycles((uae_u32)dst, (uae_u16)src);
	do_cycles_ce000_internal(cycles);
	if (newv > 0xffff) {
		setdivuflags((uae_u32)dst, (uae_u16)src);
	} else {
		CLEAR_CZNV();
		SET_ZFLG(((uae_s16)(newv)) == 0);
		SET_NFLG(((uae_s16)(newv)) < 0);
		newv = (newv & 0xffff) | ((uae_u32)rem << 16);
		m68k_dreg(regs, dstreg) = (newv);
	}
	ipl_fetch_next();
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 8+ (2/0) */
/* 2 0,0   */

/* DIVU.W (An)+,Dn */
void REGPARAM2 op_80d8_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 60;
	CurrentInstrCycles = 8;  
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_areg(regs, srcreg) += 2 + 0;
		m68k_incpci(2);
		exception3_read_access2(opcode, srca, 1, 1);
		return;
	}
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) += 2 + 0;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	m68k_areg(regs, srcreg) += 2;
	uae_s32 dst = m68k_dreg(regs, dstreg);
	if (src == 0) {
		divbyzero_special(0, dst);
		m68k_incpci(2);
		do_cycles_ce000_internal(4);
		Exception_cpu(5);
		return;
	}
	uae_u32 newv = (uae_u32)dst / (uae_u32)(uae_u16)src;
	uae_u32 rem = (uae_u32)dst % (uae_u32)(uae_u16)src;
	int cycles = getDivu68kCycles((uae_u32)dst, (uae_u16)src);
	do_cycles_ce000_internal(cycles);
	if (newv > 0xffff) {
		setdivuflags((uae_u32)dst, (uae_u16)src);
	} else {
		CLEAR_CZNV();
		SET_ZFLG(((uae_s16)(newv)) == 0);
		SET_NFLG(((uae_s16)(newv)) < 0);
		newv = (newv & 0xffff) | ((uae_u32)rem << 16);
		m68k_dreg(regs, dstreg) = (newv);
	}
	ipl_fetch_next();
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 8+ (2/0) */
/* 2 0,0   */

/* DIVU.W -(An),Dn */
void REGPARAM2 op_80e0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 60;
	CurrentInstrCycles = 10; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - 2;
	do_cycles_ce000_internal(2);
	if (srca & 1) {
		m68k_areg(regs, srcreg) = srca;
		m68k_incpci(2);
		exception3_read_access2(opcode, srca, 1, 1);
		return;
	}
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	m68k_areg(regs, srcreg) = srca;
	uae_s32 dst = m68k_dreg(regs, dstreg);
	if (src == 0) {
		divbyzero_special(0, dst);
		m68k_incpci(2);
		do_cycles_ce000_internal(4);
		Exception_cpu(5);
		return;
	}
	uae_u32 newv = (uae_u32)dst / (uae_u32)(uae_u16)src;
	uae_u32 rem = (uae_u32)dst % (uae_u32)(uae_u16)src;
	int cycles = getDivu68kCycles((uae_u32)dst, (uae_u16)src);
	do_cycles_ce000_internal(cycles);
	if (newv > 0xffff) {
		setdivuflags((uae_u32)dst, (uae_u16)src);
	} else {
		CLEAR_CZNV();
		SET_ZFLG(((uae_s16)(newv)) == 0);
		SET_NFLG(((uae_s16)(newv)) < 0);
		newv = (newv & 0xffff) | ((uae_u32)rem << 16);
		m68k_dreg(regs, dstreg) = (newv);
	}
	ipl_fetch_next();
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 10+ (2/0) */
/* 2 0,0   */

/* DIVU.W (d16,An),Dn */
void REGPARAM2 op_80e8_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 60;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	if (src == 0) {
		divbyzero_special(0, dst);
		m68k_incpci(4);
		do_cycles_ce000_internal(4);
		Exception_cpu(5);
		return;
	}
	uae_u32 newv = (uae_u32)dst / (uae_u32)(uae_u16)src;
	uae_u32 rem = (uae_u32)dst % (uae_u32)(uae_u16)src;
	int cycles = getDivu68kCycles((uae_u32)dst, (uae_u16)src);
	do_cycles_ce000_internal(cycles);
	if (newv > 0xffff) {
		setdivuflags((uae_u32)dst, (uae_u16)src);
	} else {
		CLEAR_CZNV();
		SET_ZFLG(((uae_s16)(newv)) == 0);
		SET_NFLG(((uae_s16)(newv)) < 0);
		newv = (newv & 0xffff) | ((uae_u32)rem << 16);
		m68k_dreg(regs, dstreg) = (newv);
	}
	ipl_fetch_next();
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 12+ (3/0) */
/* 4 0,0   */

/* DIVU.W (d8,An,Xn),Dn */
void REGPARAM2 op_80f0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 60;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	do_cycles_ce000_internal(2);
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	if (src == 0) {
		divbyzero_special(0, dst);
		m68k_incpci(4);
		do_cycles_ce000_internal(4);
		Exception_cpu(5);
		return;
	}
	uae_u32 newv = (uae_u32)dst / (uae_u32)(uae_u16)src;
	uae_u32 rem = (uae_u32)dst % (uae_u32)(uae_u16)src;
	int cycles = getDivu68kCycles((uae_u32)dst, (uae_u16)src);
	do_cycles_ce000_internal(cycles);
	if (newv > 0xffff) {
		setdivuflags((uae_u32)dst, (uae_u16)src);
	} else {
		CLEAR_CZNV();
		SET_ZFLG(((uae_s16)(newv)) == 0);
		SET_NFLG(((uae_s16)(newv)) < 0);
		newv = (newv & 0xffff) | ((uae_u32)rem << 16);
		m68k_dreg(regs, dstreg) = (newv);
	}
	ipl_fetch_next();
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 14+ (3/0) */
/* 4 4,0   */

/* DIVU.W (xxx).W,Dn */
void REGPARAM2 op_80f8_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 60;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	if (srca & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	if (src == 0) {
		divbyzero_special(0, dst);
		m68k_incpci(4);
		do_cycles_ce000_internal(4);
		Exception_cpu(5);
		return;
	}
	uae_u32 newv = (uae_u32)dst / (uae_u32)(uae_u16)src;
	uae_u32 rem = (uae_u32)dst % (uae_u32)(uae_u16)src;
	int cycles = getDivu68kCycles((uae_u32)dst, (uae_u16)src);
	do_cycles_ce000_internal(cycles);
	if (newv > 0xffff) {
		setdivuflags((uae_u32)dst, (uae_u16)src);
	} else {
		CLEAR_CZNV();
		SET_ZFLG(((uae_s16)(newv)) == 0);
		SET_NFLG(((uae_s16)(newv)) < 0);
		newv = (newv & 0xffff) | ((uae_u32)rem << 16);
		m68k_dreg(regs, dstreg) = (newv);
	}
	ipl_fetch_next();
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 12+ (3/0) */
/* 4 0,0   */

/* DIVU.W (xxx).L,Dn */
void REGPARAM2 op_80f9_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 60;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	srca |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	if (srca & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	if (src == 0) {
		divbyzero_special(0, dst);
		m68k_incpci(6);
		do_cycles_ce000_internal(4);
		Exception_cpu(5);
		return;
	}
	uae_u32 newv = (uae_u32)dst / (uae_u32)(uae_u16)src;
	uae_u32 rem = (uae_u32)dst % (uae_u32)(uae_u16)src;
	int cycles = getDivu68kCycles((uae_u32)dst, (uae_u16)src);
	do_cycles_ce000_internal(cycles);
	if (newv > 0xffff) {
		setdivuflags((uae_u32)dst, (uae_u16)src);
	} else {
		CLEAR_CZNV();
		SET_ZFLG(((uae_s16)(newv)) == 0);
		SET_NFLG(((uae_s16)(newv)) < 0);
		newv = (newv & 0xffff) | ((uae_u32)rem << 16);
		m68k_dreg(regs, dstreg) = (newv);
	}
	ipl_fetch_next();
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 16+ (4/0) */
/* 6 0,0   */

/* DIVU.W (d16,PC),Dn */
void REGPARAM2 op_80fa_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 60;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_getpci() + 2;
	srca += (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 2);
		return;
	}
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	if (src == 0) {
		divbyzero_special(0, dst);
		m68k_incpci(4);
		do_cycles_ce000_internal(4);
		Exception_cpu(5);
		return;
	}
	uae_u32 newv = (uae_u32)dst / (uae_u32)(uae_u16)src;
	uae_u32 rem = (uae_u32)dst % (uae_u32)(uae_u16)src;
	int cycles = getDivu68kCycles((uae_u32)dst, (uae_u16)src);
	do_cycles_ce000_internal(cycles);
	if (newv > 0xffff) {
		setdivuflags((uae_u32)dst, (uae_u16)src);
	} else {
		CLEAR_CZNV();
		SET_ZFLG(((uae_s16)(newv)) == 0);
		SET_NFLG(((uae_s16)(newv)) < 0);
		newv = (newv & 0xffff) | ((uae_u32)rem << 16);
		m68k_dreg(regs, dstreg) = (newv);
	}
	ipl_fetch_next();
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 12+ (3/0) */
/* 4 0,0   */

/* DIVU.W (d8,PC,Xn),Dn */
void REGPARAM2 op_80fb_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 60;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	uaecptr tmppc = m68k_getpci() + 2;
	do_cycles_ce000_internal(2);
	srca = get_disp_ea_000(tmppc, get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 2);
		return;
	}
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	if (src == 0) {
		divbyzero_special(0, dst);
		m68k_incpci(4);
		do_cycles_ce000_internal(4);
		Exception_cpu(5);
		return;
	}
	uae_u32 newv = (uae_u32)dst / (uae_u32)(uae_u16)src;
	uae_u32 rem = (uae_u32)dst % (uae_u32)(uae_u16)src;
	int cycles = getDivu68kCycles((uae_u32)dst, (uae_u16)src);
	do_cycles_ce000_internal(cycles);
	if (newv > 0xffff) {
		setdivuflags((uae_u32)dst, (uae_u16)src);
	} else {
		CLEAR_CZNV();
		SET_ZFLG(((uae_s16)(newv)) == 0);
		SET_NFLG(((uae_s16)(newv)) < 0);
		newv = (newv & 0xffff) | ((uae_u32)rem << 16);
		m68k_dreg(regs, dstreg) = (newv);
	}
	ipl_fetch_next();
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 14+ (3/0) */
/* 4 4,0   */

/* DIVU.W #<data>.W,Dn */
void REGPARAM2 op_80fc_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 60;
	CurrentInstrCycles = 8;  
	uae_s16 src = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	if (src == 0) {
		divbyzero_special(0, dst);
		m68k_incpci(4);
		do_cycles_ce000_internal(4);
		Exception_cpu(5);
		return;
	}
	uae_u32 newv = (uae_u32)dst / (uae_u32)(uae_u16)src;
	uae_u32 rem = (uae_u32)dst % (uae_u32)(uae_u16)src;
	int cycles = getDivu68kCycles((uae_u32)dst, (uae_u16)src);
	do_cycles_ce000_internal(cycles);
	if (newv > 0xffff) {
		setdivuflags((uae_u32)dst, (uae_u16)src);
	} else {
		CLEAR_CZNV();
		SET_ZFLG(((uae_s16)(newv)) == 0);
		SET_NFLG(((uae_s16)(newv)) < 0);
		newv = (newv & 0xffff) | ((uae_u32)rem << 16);
		m68k_dreg(regs, dstreg) = (newv);
	}
	ipl_fetch_next();
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 8+ (2/0) */
/* 4 0,0   */

/* SBCD.B Dn,Dn */
void REGPARAM2 op_8100_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 10;
	CurrentInstrCycles = 6;  
	uae_s8 src = m68k_dreg(regs, srcreg);
	uae_s8 dst = m68k_dreg(regs, dstreg);
	uae_u16 newv_lo = (dst & 0xF) - (src & 0xF) - (GET_XFLG() ? 1 : 0);
	uae_u16 newv_hi = (dst & 0xF0) - (src & 0xF0);
	uae_u16 newv, tmp_newv;
	int bcd = 0;
	newv = tmp_newv = newv_hi + newv_lo;
if (newv_lo & 0xF0) { newv -= 6; bcd = 6; };
if ((((dst & 0xFF) - (src & 0xFF) - (GET_XFLG() ? 1 : 0)) & 0x100) > 0xFF) { newv -= 0x60; }
	SET_CFLG((((dst & 0xFF) - (src & 0xFF) - bcd - (GET_XFLG() ? 1 : 0)) & 0x300) > 0xFF);
	COPY_CARRY();
	SET_ZFLG(GET_ZFLG() & (((uae_s8)(newv)) == 0));
	SET_NFLG(((uae_s8)(newv)) < 0);
	SET_VFLG((tmp_newv & 0x80) != 0 && (newv & 0x80) == 0);
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	do_cycles_ce000_internal(2);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
	m68k_incpci(2);
	return;
}
/* 6 (1/0) */
/* 2 0,0   */

/* SBCD.B -(An),-(An) */
void REGPARAM2 op_8108_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 10;
	CurrentInstrCycles = 18; 
	int loop_mode = regs.loop_mode;
	do_cycles_ce000_internal(2);
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	m68k_areg(regs, srcreg) = srca;
	ipl_fetch_next_pre();
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, dstreg) = dsta;
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	m68k_areg(regs, dstreg) = dsta;
	uae_u16 newv_lo = (dst & 0xF) - (src & 0xF) - (GET_XFLG() ? 1 : 0);
	uae_u16 newv_hi = (dst & 0xF0) - (src & 0xF0);
	uae_u16 newv, tmp_newv;
	int bcd = 0;
	newv = tmp_newv = newv_hi + newv_lo;
if (newv_lo & 0xF0) { newv -= 6; bcd = 6; };
if ((((dst & 0xFF) - (src & 0xFF) - (GET_XFLG() ? 1 : 0)) & 0x100) > 0xFF) { newv -= 0x60; }
	SET_CFLG((((dst & 0xFF) - (src & 0xFF) - bcd - (GET_XFLG() ? 1 : 0)) & 0x300) > 0xFF);
	COPY_CARRY();
	SET_ZFLG(GET_ZFLG() & (((uae_s8)(newv)) == 0));
	SET_NFLG(((uae_s8)(newv)) < 0);
	SET_VFLG((tmp_newv & 0x80) != 0 && (newv & 0x80) == 0);
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_ce000_prefetch(4);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return;
		}
		opcode = regs.ir;
	} else {
		loop_mode = 0;
		loop_mode |= 6;
		loop_mode |= 6 << 16;
	}
	if(loop_mode & 0xfffe) {
		do_cycles_ce000_internal(loop_mode & 0xfffe);
		loop_mode = 1;
	}
	x_put_byte(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x0, newv, 1);
		return;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return;
}
/* 18 (3/1) */
/* 2 0,0   */

/* OR.B Dn,(An) */
void REGPARAM2 op_8110_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 12; 
	int loop_mode = regs.loop_mode;
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_ce000_prefetch(4);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return;
		}
		opcode = regs.ir;
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	if(loop_mode & 0xfffe) {
		do_cycles_ce000_internal(loop_mode & 0xfffe);
		loop_mode = 1;
	}
	x_put_byte(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return;
}
/* 12 (2/1) */
/* 2 0,0   */

/* OR.B Dn,(An)+ */
void REGPARAM2 op_8118_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 12; 
	int loop_mode = regs.loop_mode;
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_ce000_prefetch(4);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return;
		}
		opcode = regs.ir;
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	if(loop_mode & 0xfffe) {
		do_cycles_ce000_internal(loop_mode & 0xfffe);
		loop_mode = 1;
	}
	x_put_byte(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return;
}
/* 12 (2/1) */
/* 2 0,0   */

/* OR.B Dn,-(An) */
void REGPARAM2 op_8120_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 14; 
	int loop_mode = regs.loop_mode;
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
	do_cycles_ce000_internal(2);
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, dstreg) = dsta;
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	m68k_areg(regs, dstreg) = dsta;
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_ce000_prefetch(4);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return;
		}
		opcode = regs.ir;
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	if(loop_mode & 0xfffe) {
		do_cycles_ce000_internal(loop_mode & 0xfffe);
		loop_mode = 1;
	}
	x_put_byte(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return;
}
/* 14 (2/1) */
/* 2 0,0   */

/* OR.B Dn,(d16,An) */
void REGPARAM2 op_8128_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 16; 
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_byte(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* OR.B Dn,(d8,An,Xn) */
void REGPARAM2 op_8130_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 18; 
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	do_cycles_ce000_internal(2);
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_byte(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 18 (3/1) */
/* 4 4,0   */

/* OR.B Dn,(xxx).W */
void REGPARAM2 op_8138_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	OpcodeFamily = 1;
	CurrentInstrCycles = 16; 
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_byte(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* OR.B Dn,(xxx).L */
void REGPARAM2 op_8139_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	OpcodeFamily = 1;
	CurrentInstrCycles = 20; 
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	dsta |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_byte(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 20 (4/1) */
/* 6 0,0   */

/* OR.W Dn,(An) */
void REGPARAM2 op_8150_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 12; 
	int loop_mode = regs.loop_mode;
	uae_s16 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	if (dsta & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dsta, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 dst = x_get_word(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_ce000_prefetch(4);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return;
		}
		opcode = regs.ir;
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	if(loop_mode & 0xfffe) {
		do_cycles_ce000_internal(loop_mode & 0xfffe);
		loop_mode = 1;
	}
	x_put_word(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return;
}
/* 12 (2/1) */
/* 2 0,0   */

/* OR.W Dn,(An)+ */
void REGPARAM2 op_8158_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 12; 
	int loop_mode = regs.loop_mode;
	uae_s16 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	if (dsta & 1) {
		m68k_areg(regs, dstreg) += 2 + 0;
		m68k_incpci(2);
		exception3_read_access(opcode, dsta, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 dst = x_get_word(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, dstreg) += 2 + 0;
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	m68k_areg(regs, dstreg) += 2;
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_ce000_prefetch(4);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return;
		}
		opcode = regs.ir;
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	if(loop_mode & 0xfffe) {
		do_cycles_ce000_internal(loop_mode & 0xfffe);
		loop_mode = 1;
	}
	x_put_word(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return;
}
/* 12 (2/1) */
/* 2 0,0   */

/* OR.W Dn,-(An) */
void REGPARAM2 op_8160_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 14; 
	int loop_mode = regs.loop_mode;
	uae_s16 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - 2;
	do_cycles_ce000_internal(2);
	if (dsta & 1) {
		m68k_areg(regs, dstreg) = dsta;
		m68k_incpci(2);
		exception3_read_access(opcode, dsta, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 dst = x_get_word(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, dstreg) = dsta;
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	m68k_areg(regs, dstreg) = dsta;
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_ce000_prefetch(4);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return;
		}
		opcode = regs.ir;
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	if(loop_mode & 0xfffe) {
		do_cycles_ce000_internal(loop_mode & 0xfffe);
		loop_mode = 1;
	}
	x_put_word(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return;
}
/* 14 (2/1) */
/* 2 0,0   */

/* OR.W Dn,(d16,An) */
void REGPARAM2 op_8168_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 16; 
	uae_s16 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dsta, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 dst = x_get_word(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_word(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* OR.W Dn,(d8,An,Xn) */
void REGPARAM2 op_8170_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 18; 
	uae_s16 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	do_cycles_ce000_internal(2);
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dsta, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 dst = x_get_word(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_word(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 18 (3/1) */
/* 4 4,0   */

/* OR.W Dn,(xxx).W */
void REGPARAM2 op_8178_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	OpcodeFamily = 1;
	CurrentInstrCycles = 16; 
	uae_s16 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, dsta, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 dst = x_get_word(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_word(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* OR.W Dn,(xxx).L */
void REGPARAM2 op_8179_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	OpcodeFamily = 1;
	CurrentInstrCycles = 20; 
	uae_s16 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	dsta |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, dsta, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 dst = x_get_word(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_word(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 20 (4/1) */
/* 6 0,0   */

/* OR.L Dn,(An) */
void REGPARAM2 op_8190_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 20; 
	int loop_mode = regs.loop_mode;
	uae_s32 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	if (dsta & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dsta, 2, 1);
		return;
	}
	uae_s32 dst = x_get_word(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	dst |= x_get_word(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return;
	}
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_ce000_prefetch(4);
		if(hardware_bus_error) {
			int pcoffset = 0;
			ccr_68000_long_move_ae_LZN(src);
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return;
		}
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	if(loop_mode & 0xfffe) {
		do_cycles_ce000_internal(loop_mode & 0xfffe);
		loop_mode = 1;
	}
	x_put_word(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return;
	}
	x_put_word(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return;
}
/* 20 (3/2) */
/* 2 0,0   */

/* OR.L Dn,(An)+ */
void REGPARAM2 op_8198_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 20; 
	int loop_mode = regs.loop_mode;
	uae_s32 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	if (dsta & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dsta, 2, 1);
		return;
	}
	uae_s32 dst = x_get_word(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	dst |= x_get_word(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return;
	}
	m68k_areg(regs, dstreg) += 4;
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_ce000_prefetch(4);
		if(hardware_bus_error) {
			int pcoffset = 0;
			ccr_68000_long_move_ae_LZN(src);
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return;
		}
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	if(loop_mode & 0xfffe) {
		do_cycles_ce000_internal(loop_mode & 0xfffe);
		loop_mode = 1;
	}
	x_put_word(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return;
	}
	x_put_word(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return;
}
/* 20 (3/2) */
/* 2 0,0   */

/* OR.L Dn,-(An) */
void REGPARAM2 op_81a0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 22; 
	int loop_mode = regs.loop_mode;
	uae_s32 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - 4;
	do_cycles_ce000_internal(2);
	if (dsta & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dsta, 2, 1);
		return;
	}
	uae_s32 dst = x_get_word(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	dst |= x_get_word(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, dstreg) = dsta;
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return;
	}
	m68k_areg(regs, dstreg) = dsta;
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_ce000_prefetch(4);
		if(hardware_bus_error) {
			int pcoffset = 0;
			ccr_68000_long_move_ae_LZN(src);
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return;
		}
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	if(loop_mode & 0xfffe) {
		do_cycles_ce000_internal(loop_mode & 0xfffe);
		loop_mode = 1;
	}
	x_put_word(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return;
	}
	x_put_word(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return;
}
/* 22 (3/2) */
/* 2 0,0   */

/* OR.L Dn,(d16,An) */
void REGPARAM2 op_81a8_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 24; 
	uae_s32 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dsta, 2, 1);
		return;
	}
	uae_s32 dst = x_get_word(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	dst |= x_get_word(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return;
	}
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	x_put_word(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return;
	}
	x_put_word(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 24 (4/2) */
/* 4 0,0   */

/* OR.L Dn,(d8,An,Xn) */
void REGPARAM2 op_81b0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 26; 
	uae_s32 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	do_cycles_ce000_internal(2);
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dsta, 2, 1);
		return;
	}
	uae_s32 dst = x_get_word(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	dst |= x_get_word(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return;
	}
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	x_put_word(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return;
	}
	x_put_word(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 26 (4/2) */
/* 4 4,0   */

/* OR.L Dn,(xxx).W */
void REGPARAM2 op_81b8_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	OpcodeFamily = 1;
	CurrentInstrCycles = 24; 
	uae_s32 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, dsta, 2, 1);
		return;
	}
	uae_s32 dst = x_get_word(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	dst |= x_get_word(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return;
	}
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	x_put_word(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return;
	}
	x_put_word(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 24 (4/2) */
/* 4 0,0   */

/* OR.L Dn,(xxx).L */
void REGPARAM2 op_81b9_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	OpcodeFamily = 1;
	CurrentInstrCycles = 28; 
	uae_s32 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	dsta |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, dsta, 2, 1);
		return;
	}
	uae_s32 dst = x_get_word(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	dst |= x_get_word(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return;
	}
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	x_put_word(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return;
	}
	x_put_word(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 28 (5/2) */
/* 6 0,0   */

/* DIVS.W Dn,Dn */
void REGPARAM2 op_81c0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 61;
	CurrentInstrCycles = 4;  
	uae_s16 src = m68k_dreg(regs, srcreg);
	uae_s32 dst = m68k_dreg(regs, dstreg);
	if (src == 0) {
		divbyzero_special(1, dst);
		m68k_incpci(2);
		do_cycles_ce000_internal(4);
		Exception_cpu(5);
		return;
	}
	int extra = 0;
	int cycles = getDivs68kCycles((uae_s32)dst, (uae_s16)src, &extra);
	if (extra) {
		cycles -= 2;
		do_cycles_ce000_internal(cycles);
		ipl_fetch_next();
		cycles = 2;
		do_cycles_ce000_internal(cycles);
	} else {
		do_cycles_ce000_internal(cycles);
		ipl_fetch_next();
	}
	if (dst == 0x80000000 && src == -1) {
		setdivsflags((uae_s32)dst, (uae_s16)src);
	} else {
		uae_s32 newv = (uae_s32)dst / (uae_s32)(uae_s16)src;
		uae_u16 rem = (uae_s32)dst % (uae_s32)(uae_s16)src;
		if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) {
			setdivsflags((uae_s32)dst, (uae_s16)src);
		} else {
			if (((uae_s16)rem < 0) != ((uae_s32)dst < 0)) rem = -rem;
			CLEAR_CZNV();
			SET_ZFLG(((uae_s16)(newv)) == 0);
			SET_NFLG(((uae_s16)(newv)) < 0);
			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
			m68k_dreg(regs, dstreg) = (newv);
		}
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 4+ (1/0) */
/* 2 0,0   */

/* DIVS.W (An),Dn */
void REGPARAM2 op_81d0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 61;
	CurrentInstrCycles = 8;  
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access2(opcode, srca, 1, 1);
		return;
	}
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	if (src == 0) {
		divbyzero_special(1, dst);
		m68k_incpci(2);
		do_cycles_ce000_internal(4);
		Exception_cpu(5);
		return;
	}
	int extra = 0;
	int cycles = getDivs68kCycles((uae_s32)dst, (uae_s16)src, &extra);
	if (extra) {
		cycles -= 2;
		do_cycles_ce000_internal(cycles);
		ipl_fetch_next();
		cycles = 2;
		do_cycles_ce000_internal(cycles);
	} else {
		do_cycles_ce000_internal(cycles);
		ipl_fetch_next();
	}
	if (dst == 0x80000000 && src == -1) {
		setdivsflags((uae_s32)dst, (uae_s16)src);
	} else {
		uae_s32 newv = (uae_s32)dst / (uae_s32)(uae_s16)src;
		uae_u16 rem = (uae_s32)dst % (uae_s32)(uae_s16)src;
		if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) {
			setdivsflags((uae_s32)dst, (uae_s16)src);
		} else {
			if (((uae_s16)rem < 0) != ((uae_s32)dst < 0)) rem = -rem;
			CLEAR_CZNV();
			SET_ZFLG(((uae_s16)(newv)) == 0);
			SET_NFLG(((uae_s16)(newv)) < 0);
			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
			m68k_dreg(regs, dstreg) = (newv);
		}
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 8+ (2/0) */
/* 2 0,0   */

/* DIVS.W (An)+,Dn */
void REGPARAM2 op_81d8_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 61;
	CurrentInstrCycles = 8;  
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_areg(regs, srcreg) += 2 + 0;
		m68k_incpci(2);
		exception3_read_access2(opcode, srca, 1, 1);
		return;
	}
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) += 2 + 0;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	m68k_areg(regs, srcreg) += 2;
	uae_s32 dst = m68k_dreg(regs, dstreg);
	if (src == 0) {
		divbyzero_special(1, dst);
		m68k_incpci(2);
		do_cycles_ce000_internal(4);
		Exception_cpu(5);
		return;
	}
	int extra = 0;
	int cycles = getDivs68kCycles((uae_s32)dst, (uae_s16)src, &extra);
	if (extra) {
		cycles -= 2;
		do_cycles_ce000_internal(cycles);
		ipl_fetch_next();
		cycles = 2;
		do_cycles_ce000_internal(cycles);
	} else {
		do_cycles_ce000_internal(cycles);
		ipl_fetch_next();
	}
	if (dst == 0x80000000 && src == -1) {
		setdivsflags((uae_s32)dst, (uae_s16)src);
	} else {
		uae_s32 newv = (uae_s32)dst / (uae_s32)(uae_s16)src;
		uae_u16 rem = (uae_s32)dst % (uae_s32)(uae_s16)src;
		if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) {
			setdivsflags((uae_s32)dst, (uae_s16)src);
		} else {
			if (((uae_s16)rem < 0) != ((uae_s32)dst < 0)) rem = -rem;
			CLEAR_CZNV();
			SET_ZFLG(((uae_s16)(newv)) == 0);
			SET_NFLG(((uae_s16)(newv)) < 0);
			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
			m68k_dreg(regs, dstreg) = (newv);
		}
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 8+ (2/0) */
/* 2 0,0   */

/* DIVS.W -(An),Dn */
void REGPARAM2 op_81e0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 61;
	CurrentInstrCycles = 10; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - 2;
	do_cycles_ce000_internal(2);
	if (srca & 1) {
		m68k_areg(regs, srcreg) = srca;
		m68k_incpci(2);
		exception3_read_access2(opcode, srca, 1, 1);
		return;
	}
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	m68k_areg(regs, srcreg) = srca;
	uae_s32 dst = m68k_dreg(regs, dstreg);
	if (src == 0) {
		divbyzero_special(1, dst);
		m68k_incpci(2);
		do_cycles_ce000_internal(4);
		Exception_cpu(5);
		return;
	}
	int extra = 0;
	int cycles = getDivs68kCycles((uae_s32)dst, (uae_s16)src, &extra);
	if (extra) {
		cycles -= 2;
		do_cycles_ce000_internal(cycles);
		ipl_fetch_next();
		cycles = 2;
		do_cycles_ce000_internal(cycles);
	} else {
		do_cycles_ce000_internal(cycles);
		ipl_fetch_next();
	}
	if (dst == 0x80000000 && src == -1) {
		setdivsflags((uae_s32)dst, (uae_s16)src);
	} else {
		uae_s32 newv = (uae_s32)dst / (uae_s32)(uae_s16)src;
		uae_u16 rem = (uae_s32)dst % (uae_s32)(uae_s16)src;
		if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) {
			setdivsflags((uae_s32)dst, (uae_s16)src);
		} else {
			if (((uae_s16)rem < 0) != ((uae_s32)dst < 0)) rem = -rem;
			CLEAR_CZNV();
			SET_ZFLG(((uae_s16)(newv)) == 0);
			SET_NFLG(((uae_s16)(newv)) < 0);
			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
			m68k_dreg(regs, dstreg) = (newv);
		}
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 10+ (2/0) */
/* 2 0,0   */

/* DIVS.W (d16,An),Dn */
void REGPARAM2 op_81e8_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 61;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	if (src == 0) {
		divbyzero_special(1, dst);
		m68k_incpci(4);
		do_cycles_ce000_internal(4);
		Exception_cpu(5);
		return;
	}
	int extra = 0;
	int cycles = getDivs68kCycles((uae_s32)dst, (uae_s16)src, &extra);
	if (extra) {
		cycles -= 2;
		do_cycles_ce000_internal(cycles);
		ipl_fetch_next();
		cycles = 2;
		do_cycles_ce000_internal(cycles);
	} else {
		do_cycles_ce000_internal(cycles);
		ipl_fetch_next();
	}
	if (dst == 0x80000000 && src == -1) {
		setdivsflags((uae_s32)dst, (uae_s16)src);
	} else {
		uae_s32 newv = (uae_s32)dst / (uae_s32)(uae_s16)src;
		uae_u16 rem = (uae_s32)dst % (uae_s32)(uae_s16)src;
		if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) {
			setdivsflags((uae_s32)dst, (uae_s16)src);
		} else {
			if (((uae_s16)rem < 0) != ((uae_s32)dst < 0)) rem = -rem;
			CLEAR_CZNV();
			SET_ZFLG(((uae_s16)(newv)) == 0);
			SET_NFLG(((uae_s16)(newv)) < 0);
			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
			m68k_dreg(regs, dstreg) = (newv);
		}
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 12+ (3/0) */
/* 4 0,0   */

/* DIVS.W (d8,An,Xn),Dn */
void REGPARAM2 op_81f0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 61;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	do_cycles_ce000_internal(2);
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	if (src == 0) {
		divbyzero_special(1, dst);
		m68k_incpci(4);
		do_cycles_ce000_internal(4);
		Exception_cpu(5);
		return;
	}
	int extra = 0;
	int cycles = getDivs68kCycles((uae_s32)dst, (uae_s16)src, &extra);
	if (extra) {
		cycles -= 2;
		do_cycles_ce000_internal(cycles);
		ipl_fetch_next();
		cycles = 2;
		do_cycles_ce000_internal(cycles);
	} else {
		do_cycles_ce000_internal(cycles);
		ipl_fetch_next();
	}
	if (dst == 0x80000000 && src == -1) {
		setdivsflags((uae_s32)dst, (uae_s16)src);
	} else {
		uae_s32 newv = (uae_s32)dst / (uae_s32)(uae_s16)src;
		uae_u16 rem = (uae_s32)dst % (uae_s32)(uae_s16)src;
		if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) {
			setdivsflags((uae_s32)dst, (uae_s16)src);
		} else {
			if (((uae_s16)rem < 0) != ((uae_s32)dst < 0)) rem = -rem;
			CLEAR_CZNV();
			SET_ZFLG(((uae_s16)(newv)) == 0);
			SET_NFLG(((uae_s16)(newv)) < 0);
			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
			m68k_dreg(regs, dstreg) = (newv);
		}
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 14+ (3/0) */
/* 4 4,0   */

/* DIVS.W (xxx).W,Dn */
void REGPARAM2 op_81f8_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 61;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	if (srca & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	if (src == 0) {
		divbyzero_special(1, dst);
		m68k_incpci(4);
		do_cycles_ce000_internal(4);
		Exception_cpu(5);
		return;
	}
	int extra = 0;
	int cycles = getDivs68kCycles((uae_s32)dst, (uae_s16)src, &extra);
	if (extra) {
		cycles -= 2;
		do_cycles_ce000_internal(cycles);
		ipl_fetch_next();
		cycles = 2;
		do_cycles_ce000_internal(cycles);
	} else {
		do_cycles_ce000_internal(cycles);
		ipl_fetch_next();
	}
	if (dst == 0x80000000 && src == -1) {
		setdivsflags((uae_s32)dst, (uae_s16)src);
	} else {
		uae_s32 newv = (uae_s32)dst / (uae_s32)(uae_s16)src;
		uae_u16 rem = (uae_s32)dst % (uae_s32)(uae_s16)src;
		if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) {
			setdivsflags((uae_s32)dst, (uae_s16)src);
		} else {
			if (((uae_s16)rem < 0) != ((uae_s32)dst < 0)) rem = -rem;
			CLEAR_CZNV();
			SET_ZFLG(((uae_s16)(newv)) == 0);
			SET_NFLG(((uae_s16)(newv)) < 0);
			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
			m68k_dreg(regs, dstreg) = (newv);
		}
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 12+ (3/0) */
/* 4 0,0   */

/* DIVS.W (xxx).L,Dn */
void REGPARAM2 op_81f9_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 61;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	srca |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	if (srca & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	if (src == 0) {
		divbyzero_special(1, dst);
		m68k_incpci(6);
		do_cycles_ce000_internal(4);
		Exception_cpu(5);
		return;
	}
	int extra = 0;
	int cycles = getDivs68kCycles((uae_s32)dst, (uae_s16)src, &extra);
	if (extra) {
		cycles -= 2;
		do_cycles_ce000_internal(cycles);
		ipl_fetch_next();
		cycles = 2;
		do_cycles_ce000_internal(cycles);
	} else {
		do_cycles_ce000_internal(cycles);
		ipl_fetch_next();
	}
	if (dst == 0x80000000 && src == -1) {
		setdivsflags((uae_s32)dst, (uae_s16)src);
	} else {
		uae_s32 newv = (uae_s32)dst / (uae_s32)(uae_s16)src;
		uae_u16 rem = (uae_s32)dst % (uae_s32)(uae_s16)src;
		if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) {
			setdivsflags((uae_s32)dst, (uae_s16)src);
		} else {
			if (((uae_s16)rem < 0) != ((uae_s32)dst < 0)) rem = -rem;
			CLEAR_CZNV();
			SET_ZFLG(((uae_s16)(newv)) == 0);
			SET_NFLG(((uae_s16)(newv)) < 0);
			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
			m68k_dreg(regs, dstreg) = (newv);
		}
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 16+ (4/0) */
/* 6 0,0   */

/* DIVS.W (d16,PC),Dn */
void REGPARAM2 op_81fa_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 61;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_getpci() + 2;
	srca += (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 2);
		return;
	}
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	if (src == 0) {
		divbyzero_special(1, dst);
		m68k_incpci(4);
		do_cycles_ce000_internal(4);
		Exception_cpu(5);
		return;
	}
	int extra = 0;
	int cycles = getDivs68kCycles((uae_s32)dst, (uae_s16)src, &extra);
	if (extra) {
		cycles -= 2;
		do_cycles_ce000_internal(cycles);
		ipl_fetch_next();
		cycles = 2;
		do_cycles_ce000_internal(cycles);
	} else {
		do_cycles_ce000_internal(cycles);
		ipl_fetch_next();
	}
	if (dst == 0x80000000 && src == -1) {
		setdivsflags((uae_s32)dst, (uae_s16)src);
	} else {
		uae_s32 newv = (uae_s32)dst / (uae_s32)(uae_s16)src;
		uae_u16 rem = (uae_s32)dst % (uae_s32)(uae_s16)src;
		if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) {
			setdivsflags((uae_s32)dst, (uae_s16)src);
		} else {
			if (((uae_s16)rem < 0) != ((uae_s32)dst < 0)) rem = -rem;
			CLEAR_CZNV();
			SET_ZFLG(((uae_s16)(newv)) == 0);
			SET_NFLG(((uae_s16)(newv)) < 0);
			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
			m68k_dreg(regs, dstreg) = (newv);
		}
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 12+ (3/0) */
/* 4 0,0   */

/* DIVS.W (d8,PC,Xn),Dn */
void REGPARAM2 op_81fb_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 61;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	uaecptr tmppc = m68k_getpci() + 2;
	do_cycles_ce000_internal(2);
	srca = get_disp_ea_000(tmppc, get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 2);
		return;
	}
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	if (src == 0) {
		divbyzero_special(1, dst);
		m68k_incpci(4);
		do_cycles_ce000_internal(4);
		Exception_cpu(5);
		return;
	}
	int extra = 0;
	int cycles = getDivs68kCycles((uae_s32)dst, (uae_s16)src, &extra);
	if (extra) {
		cycles -= 2;
		do_cycles_ce000_internal(cycles);
		ipl_fetch_next();
		cycles = 2;
		do_cycles_ce000_internal(cycles);
	} else {
		do_cycles_ce000_internal(cycles);
		ipl_fetch_next();
	}
	if (dst == 0x80000000 && src == -1) {
		setdivsflags((uae_s32)dst, (uae_s16)src);
	} else {
		uae_s32 newv = (uae_s32)dst / (uae_s32)(uae_s16)src;
		uae_u16 rem = (uae_s32)dst % (uae_s32)(uae_s16)src;
		if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) {
			setdivsflags((uae_s32)dst, (uae_s16)src);
		} else {
			if (((uae_s16)rem < 0) != ((uae_s32)dst < 0)) rem = -rem;
			CLEAR_CZNV();
			SET_ZFLG(((uae_s16)(newv)) == 0);
			SET_NFLG(((uae_s16)(newv)) < 0);
			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
			m68k_dreg(regs, dstreg) = (newv);
		}
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 14+ (3/0) */
/* 4 4,0   */

/* DIVS.W #<data>.W,Dn */
void REGPARAM2 op_81fc_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 61;
	CurrentInstrCycles = 8;  
	uae_s16 src = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	if (src == 0) {
		divbyzero_special(1, dst);
		m68k_incpci(4);
		do_cycles_ce000_internal(4);
		Exception_cpu(5);
		return;
	}
	int extra = 0;
	int cycles = getDivs68kCycles((uae_s32)dst, (uae_s16)src, &extra);
	if (extra) {
		cycles -= 2;
		do_cycles_ce000_internal(cycles);
		ipl_fetch_next();
		cycles = 2;
		do_cycles_ce000_internal(cycles);
	} else {
		do_cycles_ce000_internal(cycles);
		ipl_fetch_next();
	}
	if (dst == 0x80000000 && src == -1) {
		setdivsflags((uae_s32)dst, (uae_s16)src);
	} else {
		uae_s32 newv = (uae_s32)dst / (uae_s32)(uae_s16)src;
		uae_u16 rem = (uae_s32)dst % (uae_s32)(uae_s16)src;
		if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) {
			setdivsflags((uae_s32)dst, (uae_s16)src);
		} else {
			if (((uae_s16)rem < 0) != ((uae_s32)dst < 0)) rem = -rem;
			CLEAR_CZNV();
			SET_ZFLG(((uae_s16)(newv)) == 0);
			SET_NFLG(((uae_s16)(newv)) < 0);
			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
			m68k_dreg(regs, dstreg) = (newv);
		}
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 8+ (2/0) */
/* 4 0,0   */

/* SUB.B Dn,Dn */
void REGPARAM2 op_9000_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 4;  
	uae_s8 src = m68k_dreg(regs, srcreg);
	uae_s8 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 4 (1/0) */
/* 2 0,0   */

/* SUB.B (An),Dn */
void REGPARAM2 op_9010_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 8;  
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	uae_s8 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
	if(!loop_mode) {
		regs.ir = regs.irc;
		opcode = regs.ir;
		get_word_ce000_prefetch(4);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return;
		}
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	if (loop_mode) {
		do_cycles_ce000_internal(4);
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return;
}
/* 8 (2/0) */
/* 2 0,0   */

/* SUB.B (An)+,Dn */
void REGPARAM2 op_9018_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 8;  
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
	uae_s8 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
	if(!loop_mode) {
		regs.ir = regs.irc;
		opcode = regs.ir;
		get_word_ce000_prefetch(4);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return;
		}
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	if (loop_mode) {
		do_cycles_ce000_internal(4);
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return;
}
/* 8 (2/0) */
/* 2 0,0   */

/* SUB.B -(An),Dn */
void REGPARAM2 op_9020_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 10; 
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
	do_cycles_ce000_internal(2);
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	m68k_areg(regs, srcreg) = srca;
	uae_s8 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
	if(!loop_mode) {
		regs.ir = regs.irc;
		opcode = regs.ir;
		get_word_ce000_prefetch(4);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return;
		}
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	if (loop_mode) {
		do_cycles_ce000_internal(4);
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return;
}
/* 10 (2/0) */
/* 2 0,0   */

/* SUB.B (d16,An),Dn */
void REGPARAM2 op_9028_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	uae_s8 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 12 (3/0) */
/* 4 0,0   */

/* SUB.B (d8,An,Xn),Dn */
void REGPARAM2 op_9030_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	do_cycles_ce000_internal(2);
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	uae_s8 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 14 (3/0) */
/* 4 4,0   */

/* SUB.B (xxx).W,Dn */
void REGPARAM2 op_9038_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	uae_s8 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 12 (3/0) */
/* 4 0,0   */

/* SUB.B (xxx).L,Dn */
void REGPARAM2 op_9039_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	srca |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	uae_s8 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 16 (4/0) */
/* 6 0,0   */

/* SUB.B (d16,PC),Dn */
void REGPARAM2 op_903a_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_getpci() + 2;
	srca += (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 2);
		return;
	}
	uae_s8 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 12 (3/0) */
/* 4 0,0   */

/* SUB.B (d8,PC,Xn),Dn */
void REGPARAM2 op_903b_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	uaecptr tmppc = m68k_getpci() + 2;
	do_cycles_ce000_internal(2);
	srca = get_disp_ea_000(tmppc, get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 2);
		return;
	}
	uae_s8 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 14 (3/0) */
/* 4 4,0   */

/* SUB.B #<data>.B,Dn */
void REGPARAM2 op_903c_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 8;  
	uae_s8 src = (uae_u8)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uae_s8 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 8 (2/0) */
/* 4 0,0   */

/* SUB.W Dn,Dn */
void REGPARAM2 op_9040_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 4;  
	uae_s16 src = m68k_dreg(regs, srcreg);
	uae_s16 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 4 (1/0) */
/* 2 0,0   */

/* SUB.W An,Dn */
void REGPARAM2 op_9048_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 4;  
	uae_s16 src = m68k_areg(regs, srcreg);
	uae_s16 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 4 (1/0) */
/* 2 0,0   */

/* SUB.W (An),Dn */
void REGPARAM2 op_9050_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 8;  
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access2(opcode, srca, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
	if(!loop_mode) {
		regs.ir = regs.irc;
		opcode = regs.ir;
		get_word_ce000_prefetch(4);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return;
		}
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	if (loop_mode) {
		do_cycles_ce000_internal(4);
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return;
}
/* 8 (2/0) */
/* 2 0,0   */

/* SUB.W (An)+,Dn */
void REGPARAM2 op_9058_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 8;  
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_areg(regs, srcreg) += 2 + 0;
		m68k_incpci(2);
		exception3_read_access2(opcode, srca, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) += 2 + 0;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	m68k_areg(regs, srcreg) += 2;
	uae_s16 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
	if(!loop_mode) {
		regs.ir = regs.irc;
		opcode = regs.ir;
		get_word_ce000_prefetch(4);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return;
		}
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	if (loop_mode) {
		do_cycles_ce000_internal(4);
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return;
}
/* 8 (2/0) */
/* 2 0,0   */

/* SUB.W -(An),Dn */
void REGPARAM2 op_9060_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 10; 
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - 2;
	do_cycles_ce000_internal(2);
	if (srca & 1) {
		m68k_areg(regs, srcreg) = srca;
		m68k_incpci(2);
		exception3_read_access2(opcode, srca, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	m68k_areg(regs, srcreg) = srca;
	uae_s16 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
	if(!loop_mode) {
		regs.ir = regs.irc;
		opcode = regs.ir;
		get_word_ce000_prefetch(4);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return;
		}
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	if (loop_mode) {
		do_cycles_ce000_internal(4);
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return;
}
/* 10 (2/0) */
/* 2 0,0   */

/* SUB.W (d16,An),Dn */
void REGPARAM2 op_9068_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 12 (3/0) */
/* 4 0,0   */

/* SUB.W (d8,An,Xn),Dn */
void REGPARAM2 op_9070_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	do_cycles_ce000_internal(2);
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 14 (3/0) */
/* 4 4,0   */

/* SUB.W (xxx).W,Dn */
void REGPARAM2 op_9078_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	if (srca & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 12 (3/0) */
/* 4 0,0   */

/* SUB.W (xxx).L,Dn */
void REGPARAM2 op_9079_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	srca |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	if (srca & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 16 (4/0) */
/* 6 0,0   */

/* SUB.W (d16,PC),Dn */
void REGPARAM2 op_907a_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_getpci() + 2;
	srca += (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 2);
		return;
	}
	ipl_fetch_now();
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 12 (3/0) */
/* 4 0,0   */

/* SUB.W (d8,PC,Xn),Dn */
void REGPARAM2 op_907b_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	uaecptr tmppc = m68k_getpci() + 2;
	do_cycles_ce000_internal(2);
	srca = get_disp_ea_000(tmppc, get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 2);
		return;
	}
	ipl_fetch_now();
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 14 (3/0) */
/* 4 4,0   */

/* SUB.W #<data>.W,Dn */
void REGPARAM2 op_907c_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 8;  
	uae_s16 src = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 8 (2/0) */
/* 4 0,0   */

/* SUB.L Dn,Dn */
void REGPARAM2 op_9080_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 6;  
	uae_s32 src = m68k_dreg(regs, srcreg);
	uae_s32 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		uae_s16 bnewv = (uae_s16)dst - (uae_s16)src;
		int bflgs = ((uae_s16)(src)) < 0;
		int bflgo = ((uae_s16)(dst)) < 0;
		int bflgn = bnewv < 0;
		ccr_68000_long_move_ae_LZN(bnewv);
		SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
		SET_XFLG(GET_CFLG());
		SET_VFLG((bflgs ^ bflgo) & (bflgn ^ bflgo));
		dreg_68000_long_replace_low(dstreg, bnewv);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	do_cycles_ce000_internal(2);
	m68k_dreg(regs, dstreg) = (newv);
	m68k_incpci(2);
	return;
}
/* 6 (1/0) */
/* 2 0,0   */

/* SUB.L An,Dn */
void REGPARAM2 op_9088_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 6;  
	uae_s32 src = m68k_areg(regs, srcreg);
	uae_s32 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		uae_s16 bnewv = (uae_s16)dst - (uae_s16)src;
		int bflgs = ((uae_s16)(src)) < 0;
		int bflgo = ((uae_s16)(dst)) < 0;
		int bflgn = bnewv < 0;
		ccr_68000_long_move_ae_LZN(bnewv);
		SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
		SET_XFLG(GET_CFLG());
		SET_VFLG((bflgs ^ bflgo) & (bflgn ^ bflgo));
		dreg_68000_long_replace_low(dstreg, bnewv);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	do_cycles_ce000_internal(2);
	m68k_dreg(regs, dstreg) = (newv);
	m68k_incpci(2);
	return;
}
/* 6 (1/0) */
/* 2 0,0   */

/* SUB.L (An),Dn */
void REGPARAM2 op_9090_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 14; 
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_ce000_prefetch(4);
		if(hardware_bus_error) {
			int pcoffset = 0;
			dreg_68000_long_replace_low(dstreg, newv);
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return;
		}
		opcode = regs.ir;
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	do_cycles_ce000_internal(2);
	if(loop_mode & 0xfffe) {
		do_cycles_ce000_internal(loop_mode & 0xfffe);
		loop_mode = 1;
	}
	m68k_dreg(regs, dstreg) = (newv);
	if (loop_mode) {
		do_cycles_ce000_internal(4);
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return;
}
/* 14 (3/0) */
/* 2 0,0   */

/* SUB.L (An)+,Dn */
void REGPARAM2 op_9098_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 14; 
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	m68k_areg(regs, srcreg) += 4;
	uae_s32 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_ce000_prefetch(4);
		if(hardware_bus_error) {
			int pcoffset = 0;
			dreg_68000_long_replace_low(dstreg, newv);
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return;
		}
		opcode = regs.ir;
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	do_cycles_ce000_internal(2);
	if(loop_mode & 0xfffe) {
		do_cycles_ce000_internal(loop_mode & 0xfffe);
		loop_mode = 1;
	}
	m68k_dreg(regs, dstreg) = (newv);
	if (loop_mode) {
		do_cycles_ce000_internal(4);
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return;
}
/* 14 (3/0) */
/* 2 0,0   */

/* SUB.L -(An),Dn */
void REGPARAM2 op_90a0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 16; 
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - 4;
	do_cycles_ce000_internal(2);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	m68k_areg(regs, srcreg) = srca;
	uae_s32 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_ce000_prefetch(4);
		if(hardware_bus_error) {
			int pcoffset = 0;
			dreg_68000_long_replace_low(dstreg, newv);
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return;
		}
		opcode = regs.ir;
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	do_cycles_ce000_internal(2);
	if(loop_mode & 0xfffe) {
		do_cycles_ce000_internal(loop_mode & 0xfffe);
		loop_mode = 1;
	}
	m68k_dreg(regs, dstreg) = (newv);
	if (loop_mode) {
		do_cycles_ce000_internal(4);
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return;
}
/* 16 (3/0) */
/* 2 0,0   */

/* SUB.L (d16,An),Dn */
void REGPARAM2 op_90a8_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		dreg_68000_long_replace_low(dstreg, newv);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	do_cycles_ce000_internal(2);
	m68k_dreg(regs, dstreg) = (newv);
	m68k_incpci(4);
	return;
}
/* 18 (4/0) */
/* 4 0,0   */

/* SUB.L (d8,An,Xn),Dn */
void REGPARAM2 op_90b0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	do_cycles_ce000_internal(2);
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		dreg_68000_long_replace_low(dstreg, newv);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	do_cycles_ce000_internal(2);
	m68k_dreg(regs, dstreg) = (newv);
	m68k_incpci(4);
	return;
}
/* 20 (4/0) */
/* 4 4,0   */

/* SUB.L (xxx).W,Dn */
void REGPARAM2 op_90b8_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	if (srca & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		dreg_68000_long_replace_low(dstreg, newv);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	do_cycles_ce000_internal(2);
	m68k_dreg(regs, dstreg) = (newv);
	m68k_incpci(4);
	return;
}
/* 18 (4/0) */
/* 4 0,0   */

/* SUB.L (xxx).L,Dn */
void REGPARAM2 op_90b9_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 22; 
	uaecptr srca;
	srca = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	srca |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	if (srca & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		dreg_68000_long_replace_low(dstreg, newv);
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	opcode = regs.ir;
	do_cycles_ce000_internal(2);
	m68k_dreg(regs, dstreg) = (newv);
	m68k_incpci(6);
	return;
}
/* 22 (5/0) */
/* 6 0,0   */

/* SUB.L (d16,PC),Dn */
void REGPARAM2 op_90ba_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	srca = m68k_getpci() + 2;
	srca += (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 2);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return;
	}
	ipl_fetch_now();
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 2);
		return;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		dreg_68000_long_replace_low(dstreg, newv);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	do_cycles_ce000_internal(2);
	m68k_dreg(regs, dstreg) = (newv);
	m68k_incpci(4);
	return;
}
/* 18 (4/0) */
/* 4 0,0   */

/* SUB.L (d8,PC,Xn),Dn */
void REGPARAM2 op_90bb_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	uaecptr tmppc = m68k_getpci() + 2;
	do_cycles_ce000_internal(2);
	srca = get_disp_ea_000(tmppc, get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 2);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return;
	}
	ipl_fetch_now();
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 2);
		return;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		dreg_68000_long_replace_low(dstreg, newv);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	do_cycles_ce000_internal(2);
	m68k_dreg(regs, dstreg) = (newv);
	m68k_incpci(4);
	return;
}
/* 20 (4/0) */
/* 4 4,0   */

/* SUB.L #<data>.L,Dn */
void REGPARAM2 op_90bc_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 14; 
	uae_s32 src;
	src = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	ipl_fetch_now();
	src |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		uae_s16 bnewv = (uae_s16)dst - (uae_s16)src;
		int bflgs = ((uae_s16)(src)) < 0;
		int bflgo = ((uae_s16)(dst)) < 0;
		int bflgn = bnewv < 0;
		ccr_68000_long_move_ae_LZN(bnewv);
		SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
		SET_XFLG(GET_CFLG());
		SET_VFLG((bflgs ^ bflgo) & (bflgn ^ bflgo));
		dreg_68000_long_replace_low(dstreg, bnewv);
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	opcode = regs.ir;
	do_cycles_ce000_internal(2);
	m68k_dreg(regs, dstreg) = (newv);
	m68k_incpci(6);
	return;
}
/* 14 (3/0) */
/* 6 0,0   */

/* SUBA.W Dn,An */
void REGPARAM2 op_90c0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 8;
	CurrentInstrCycles = 8;  
	uae_s16 src = m68k_dreg(regs, srcreg);
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = dst - src;
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		areg_68000_long_replace_low(dstreg, newv);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	do_cycles_ce000_internal(4);
	m68k_areg(regs, dstreg) = (newv);
	m68k_incpci(2);
	return;
}
/* 8 (1/0) */
/* 2 0,0   */

/* SUBA.W An,An */
void REGPARAM2 op_90c8_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 8;
	CurrentInstrCycles = 8;  
	uae_s16 src = m68k_areg(regs, srcreg);
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = dst - src;
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		areg_68000_long_replace_low(dstreg, newv);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	do_cycles_ce000_internal(4);
	m68k_areg(regs, dstreg) = (newv);
	m68k_incpci(2);
	return;
}
/* 8 (1/0) */
/* 2 0,0   */

/* SUBA.W (An),An */
void REGPARAM2 op_90d0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 8;
	CurrentInstrCycles = 12; 
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access2(opcode, srca, 1, 1);
		return;
	}
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = dst - src;
	ipl_fetch_next_pre();
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_ce000_prefetch(4);
		if(hardware_bus_error) {
			int pcoffset = 0;
			areg_68000_long_replace_low(dstreg, newv);
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return;
		}
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	do_cycles_ce000_internal(4);
	if(loop_mode & 0xfffe) {
		do_cycles_ce000_internal(loop_mode & 0xfffe);
		loop_mode = 1;
	}
	m68k_areg(regs, dstreg) = (newv);
	if (loop_mode) {
		do_cycles_ce000_internal(2);
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return;
}
/* 12 (2/0) */
/* 2 0,0   */

/* SUBA.W (An)+,An */
void REGPARAM2 op_90d8_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 8;
	CurrentInstrCycles = 12; 
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_areg(regs, srcreg) += 2 + 0;
		m68k_incpci(2);
		exception3_read_access2(opcode, srca, 1, 1);
		return;
	}
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) += 2 + 0;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	m68k_areg(regs, srcreg) += 2;
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = dst - src;
	ipl_fetch_next_pre();
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_ce000_prefetch(4);
		if(hardware_bus_error) {
			int pcoffset = 0;
			areg_68000_long_replace_low(dstreg, newv);
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return;
		}
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	do_cycles_ce000_internal(4);
	if(loop_mode & 0xfffe) {
		do_cycles_ce000_internal(loop_mode & 0xfffe);
		loop_mode = 1;
	}
	m68k_areg(regs, dstreg) = (newv);
	if (loop_mode) {
		do_cycles_ce000_internal(2);
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return;
}
/* 12 (2/0) */
/* 2 0,0   */

/* SUBA.W -(An),An */
void REGPARAM2 op_90e0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 8;
	CurrentInstrCycles = 14; 
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - 2;
	do_cycles_ce000_internal(2);
	if (srca & 1) {
		m68k_areg(regs, srcreg) = srca;
		m68k_incpci(2);
		exception3_read_access2(opcode, srca, 1, 1);
		return;
	}
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	m68k_areg(regs, srcreg) = srca;
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = dst - src;
	ipl_fetch_next_pre();
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_ce000_prefetch(4);
		if(hardware_bus_error) {
			int pcoffset = 0;
			areg_68000_long_replace_low(dstreg, newv);
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return;
		}
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	do_cycles_ce000_internal(4);
	if(loop_mode & 0xfffe) {
		do_cycles_ce000_internal(loop_mode & 0xfffe);
		loop_mode = 1;
	}
	m68k_areg(regs, dstreg) = (newv);
	if (loop_mode) {
		do_cycles_ce000_internal(2);
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return;
}
/* 14 (2/0) */
/* 2 0,0   */

/* SUBA.W (d16,An),An */
void REGPARAM2 op_90e8_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 8;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = dst - src;
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		areg_68000_long_replace_low(dstreg, newv);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	do_cycles_ce000_internal(4);
	m68k_areg(regs, dstreg) = (newv);
	m68k_incpci(4);
	return;
}
/* 16 (3/0) */
/* 4 0,0   */

/* SUBA.W (d8,An,Xn),An */
void REGPARAM2 op_90f0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 8;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	do_cycles_ce000_internal(2);
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = dst - src;
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		areg_68000_long_replace_low(dstreg, newv);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	do_cycles_ce000_internal(4);
	m68k_areg(regs, dstreg) = (newv);
	m68k_incpci(4);
	return;
}
/* 18 (3/0) */
/* 4 4,0   */

/* SUBA.W (xxx).W,An */
void REGPARAM2 op_90f8_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 8;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	if (srca & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = dst - src;
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		areg_68000_long_replace_low(dstreg, newv);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	do_cycles_ce000_internal(4);
	m68k_areg(regs, dstreg) = (newv);
	m68k_incpci(4);
	return;
}
/* 16 (3/0) */
/* 4 0,0   */

/* SUBA.W (xxx).L,An */
void REGPARAM2 op_90f9_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 8;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	srca = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	srca |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	if (srca & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = dst - src;
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		areg_68000_long_replace_low(dstreg, newv);
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	do_cycles_ce000_internal(4);
	m68k_areg(regs, dstreg) = (newv);
	m68k_incpci(6);
	return;
}
/* 20 (4/0) */
/* 6 0,0   */

/* SUBA.W (d16,PC),An */
void REGPARAM2 op_90fa_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 8;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = m68k_getpci() + 2;
	srca += (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 2);
		return;
	}
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return;
	}
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = dst - src;
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		areg_68000_long_replace_low(dstreg, newv);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	do_cycles_ce000_internal(4);
	m68k_areg(regs, dstreg) = (newv);
	m68k_incpci(4);
	return;
}
/* 16 (3/0) */
/* 4 0,0   */

/* SUBA.W (d8,PC,Xn),An */
void REGPARAM2 op_90fb_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 8;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	uaecptr tmppc = m68k_getpci() + 2;
	do_cycles_ce000_internal(2);
	srca = get_disp_ea_000(tmppc, get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 2);
		return;
	}
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return;
	}
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = dst - src;
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		areg_68000_long_replace_low(dstreg, newv);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	do_cycles_ce000_internal(4);
	m68k_areg(regs, dstreg) = (newv);
	m68k_incpci(4);
	return;
}
/* 18 (3/0) */
/* 4 4,0   */

/* SUBA.W #<data>.W,An */
void REGPARAM2 op_90fc_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 8;
	CurrentInstrCycles = 12; 
	uae_s16 src = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = dst - src;
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		areg_68000_long_replace_low(dstreg, newv);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	do_cycles_ce000_internal(4);
	m68k_areg(regs, dstreg) = (newv);
	m68k_incpci(4);
	return;
}
/* 12 (2/0) */
/* 4 0,0   */

/* SUBX.B Dn,Dn */
void REGPARAM2 op_9100_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 9;
	CurrentInstrCycles = 4;  
	uae_s8 src = m68k_dreg(regs, srcreg);
	uae_s8 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = dst - src - (GET_XFLG() ? 1 : 0);
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_VFLG((flgs ^ flgo) & (flgo ^ flgn));
	SET_CFLG(flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
	COPY_CARRY();
	SET_ZFLG(GET_ZFLG() & (((uae_s8)(newv)) == 0));
	SET_NFLG(((uae_s8)(newv)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
	m68k_incpci(2);
	return;
}
/* 4 (1/0) */
/* 2 0,0   */

/* SUBX.B -(An),-(An) */
void REGPARAM2 op_9108_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 9;
	CurrentInstrCycles = 18; 
	int loop_mode = regs.loop_mode;
	do_cycles_ce000_internal(2);
	ipl_fetch_now();
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	m68k_areg(regs, srcreg) = srca;
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, dstreg) = dsta;
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	m68k_areg(regs, dstreg) = dsta;
	uae_u32 newv = dst - src - (GET_XFLG() ? 1 : 0);
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_VFLG((flgs ^ flgo) & (flgo ^ flgn));
	SET_CFLG(flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
	COPY_CARRY();
	SET_ZFLG(GET_ZFLG() & (((uae_s8)(newv)) == 0));
	SET_NFLG(((uae_s8)(newv)) < 0);
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_ce000_prefetch(4);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return;
		}
		opcode = regs.ir;
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	if(loop_mode & 0xfffe) {
		do_cycles_ce000_internal(loop_mode & 0xfffe);
		loop_mode = 1;
	}
	x_put_byte(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x0, newv, 1);
		return;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return;
}
/* 18 (3/1) */
/* 2 0,0   */

/* SUB.B Dn,(An) */
void REGPARAM2 op_9110_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 12; 
	int loop_mode = regs.loop_mode;
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_ce000_prefetch(4);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return;
		}
		opcode = regs.ir;
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	if(loop_mode & 0xfffe) {
		do_cycles_ce000_internal(loop_mode & 0xfffe);
		loop_mode = 1;
	}
	x_put_byte(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x0, newv, 1);
		return;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return;
}
/* 12 (2/1) */
/* 2 0,0   */

/* SUB.B Dn,(An)+ */
void REGPARAM2 op_9118_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 12; 
	int loop_mode = regs.loop_mode;
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
	uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_ce000_prefetch(4);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return;
		}
		opcode = regs.ir;
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	if(loop_mode & 0xfffe) {
		do_cycles_ce000_internal(loop_mode & 0xfffe);
		loop_mode = 1;
	}
	x_put_byte(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x0, newv, 1);
		return;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return;
}
/* 12 (2/1) */
/* 2 0,0   */

/* SUB.B Dn,-(An) */
void REGPARAM2 op_9120_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 14; 
	int loop_mode = regs.loop_mode;
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
	do_cycles_ce000_internal(2);
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, dstreg) = dsta;
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	m68k_areg(regs, dstreg) = dsta;
	uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_ce000_prefetch(4);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return;
		}
		opcode = regs.ir;
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	if(loop_mode & 0xfffe) {
		do_cycles_ce000_internal(loop_mode & 0xfffe);
		loop_mode = 1;
	}
	x_put_byte(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x0, newv, 1);
		return;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return;
}
/* 14 (2/1) */
/* 2 0,0   */

/* SUB.B Dn,(d16,An) */
void REGPARAM2 op_9128_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 16; 
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_byte(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x0, newv, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* SUB.B Dn,(d8,An,Xn) */
void REGPARAM2 op_9130_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 18; 
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	do_cycles_ce000_internal(2);
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_byte(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x0, newv, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 18 (3/1) */
/* 4 4,0   */

/* SUB.B Dn,(xxx).W */
void REGPARAM2 op_9138_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	OpcodeFamily = 7;
	CurrentInstrCycles = 16; 
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_byte(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x0, newv, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* SUB.B Dn,(xxx).L */
void REGPARAM2 op_9139_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	OpcodeFamily = 7;
	CurrentInstrCycles = 20; 
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	dsta |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_byte(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 0, 0x0, newv, 1);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 20 (4/1) */
/* 6 0,0   */

/* SUBX.W Dn,Dn */
void REGPARAM2 op_9140_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 9;
	CurrentInstrCycles = 4;  
	uae_s16 src = m68k_dreg(regs, srcreg);
	uae_s16 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = dst - src - (GET_XFLG() ? 1 : 0);
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_VFLG((flgs ^ flgo) & (flgo ^ flgn));
	SET_CFLG(flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
	COPY_CARRY();
	SET_ZFLG(GET_ZFLG() & (((uae_s16)(newv)) == 0));
	SET_NFLG(((uae_s16)(newv)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
	m68k_incpci(2);
	return;
}
/* 4 (1/0) */
/* 2 0,0   */

/* SUBX.W -(An),-(An) */
void REGPARAM2 op_9148_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 9;
	CurrentInstrCycles = 18; 
	int loop_mode = regs.loop_mode;
	do_cycles_ce000_internal(2);
	ipl_fetch_now();
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - 2;
	if (srca & 1) {
		m68k_areg(regs, srcreg) = srca;
		m68k_areg(regs, srcreg) = srca;
		m68k_incpci(2);
		exception3_read_access2(opcode, srca, 1, 1);
		return;
	}
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	m68k_areg(regs, srcreg) = srca;
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - 2;
	if (dsta & 1) {
		m68k_areg(regs, dstreg) = dsta;
		m68k_areg(regs, dstreg) = dsta;
		m68k_incpci(2);
		exception3_read_access2(opcode, dsta, 1, 1);
		return;
	}
	uae_s16 dst = x_get_word(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, dstreg) = dsta;
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	m68k_areg(regs, dstreg) = dsta;
	uae_u32 newv = dst - src - (GET_XFLG() ? 1 : 0);
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_VFLG((flgs ^ flgo) & (flgo ^ flgn));
	SET_CFLG(flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
	COPY_CARRY();
	SET_ZFLG(GET_ZFLG() & (((uae_s16)(newv)) == 0));
	SET_NFLG(((uae_s16)(newv)) < 0);
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_ce000_prefetch(4);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return;
		}
		opcode = regs.ir;
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	if(loop_mode & 0xfffe) {
		do_cycles_ce000_internal(loop_mode & 0xfffe);
		loop_mode = 1;
	}
	x_put_word(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x1, newv, 1);
		return;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return;
}
/* 18 (3/1) */
/* 2 0,0   */

/* SUB.W Dn,(An) */
void REGPARAM2 op_9150_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 12; 
	int loop_mode = regs.loop_mode;
	uae_s16 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	if (dsta & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dsta, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 dst = x_get_word(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_ce000_prefetch(4);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return;
		}
		opcode = regs.ir;
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	if(loop_mode & 0xfffe) {
		do_cycles_ce000_internal(loop_mode & 0xfffe);
		loop_mode = 1;
	}
	x_put_word(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x1, newv, 1);
		return;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return;
}
/* 12 (2/1) */
/* 2 0,0   */

/* SUB.W Dn,(An)+ */
void REGPARAM2 op_9158_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 12; 
	int loop_mode = regs.loop_mode;
	uae_s16 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	if (dsta & 1) {
		m68k_areg(regs, dstreg) += 2 + 0;
		m68k_incpci(2);
		exception3_read_access(opcode, dsta, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 dst = x_get_word(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, dstreg) += 2 + 0;
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	m68k_areg(regs, dstreg) += 2;
	uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_ce000_prefetch(4);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return;
		}
		opcode = regs.ir;
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	if(loop_mode & 0xfffe) {
		do_cycles_ce000_internal(loop_mode & 0xfffe);
		loop_mode = 1;
	}
	x_put_word(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x1, newv, 1);
		return;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return;
}
/* 12 (2/1) */
/* 2 0,0   */

/* SUB.W Dn,-(An) */
void REGPARAM2 op_9160_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 14; 
	int loop_mode = regs.loop_mode;
	uae_s16 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - 2;
	do_cycles_ce000_internal(2);
	if (dsta & 1) {
		m68k_areg(regs, dstreg) = dsta;
		m68k_incpci(2);
		exception3_read_access(opcode, dsta, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 dst = x_get_word(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, dstreg) = dsta;
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	m68k_areg(regs, dstreg) = dsta;
	uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_ce000_prefetch(4);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return;
		}
		opcode = regs.ir;
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	if(loop_mode & 0xfffe) {
		do_cycles_ce000_internal(loop_mode & 0xfffe);
		loop_mode = 1;
	}
	x_put_word(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x1, newv, 1);
		return;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return;
}
/* 14 (2/1) */
/* 2 0,0   */

/* SUB.W Dn,(d16,An) */
void REGPARAM2 op_9168_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 16; 
	uae_s16 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dsta, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 dst = x_get_word(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_word(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, newv, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* SUB.W Dn,(d8,An,Xn) */
void REGPARAM2 op_9170_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 18; 
	uae_s16 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	do_cycles_ce000_internal(2);
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dsta, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 dst = x_get_word(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_word(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, newv, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 18 (3/1) */
/* 4 4,0   */

/* SUB.W Dn,(xxx).W */
void REGPARAM2 op_9178_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	OpcodeFamily = 7;
	CurrentInstrCycles = 16; 
	uae_s16 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, dsta, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 dst = x_get_word(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_word(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, newv, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* SUB.W Dn,(xxx).L */
void REGPARAM2 op_9179_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	OpcodeFamily = 7;
	CurrentInstrCycles = 20; 
	uae_s16 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	dsta |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, dsta, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 dst = x_get_word(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_word(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 0, 0x1, newv, 1);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 20 (4/1) */
/* 6 0,0   */

/* SUBX.L Dn,Dn */
void REGPARAM2 op_9180_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 9;
	CurrentInstrCycles = 6;  
	uae_s32 src = m68k_dreg(regs, srcreg);
	uae_s32 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = dst - src - (GET_XFLG() ? 1 : 0);
	int oldz = GET_ZFLG();
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_VFLG((flgs ^ flgo) & (flgo ^ flgn));
	SET_CFLG(flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
	COPY_CARRY();
	SET_ZFLG(GET_ZFLG() & (((uae_s32)(newv)) == 0));
	SET_NFLG(((uae_s32)(newv)) < 0);
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		int bflgs = ((uae_s16)(src)) < 0;
		int bflgo = ((uae_s16)(dst)) < 0;
		int bflgn = ((uae_s16)(newv)) < 0;
		SET_VFLG((bflgs ^ bflgo) & (bflgo ^ bflgn));
		SET_CFLG(bflgs ^ ((bflgs ^ bflgn) & (bflgo ^ bflgn)));
		SET_XFLG(GET_CFLG());
		SET_ZFLG(oldz);
		if (newv & 0xffff) SET_ZFLG(0);
		SET_NFLG(newv & 0x8000); 
		dreg_68000_long_replace_low(dstreg, newv);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	do_cycles_ce000_internal(2);
	m68k_dreg(regs, dstreg) = (newv);
	m68k_incpci(2);
	return;
}
/* 6 (1/0) */
/* 2 0,0   */

/* SUBX.L -(An),-(An) */
void REGPARAM2 op_9188_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 9;
	CurrentInstrCycles = 30; 
	int loop_mode = regs.loop_mode;
	do_cycles_ce000_internal(2);
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - 4;
	if (srca & 1) {
		m68k_incpci(2);
		srca += 2;
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	src |= x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	m68k_areg(regs, srcreg) = srca;
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - 4;
	if (dsta & 1) {
		m68k_incpci(2);
		dsta += 2;
		exception3_read_access(opcode, dsta, 2, 1);
		return;
	}
	uae_s32 dst = x_get_word(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	dst |= x_get_word(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	m68k_areg(regs, dstreg) = dsta;
	uae_u32 newv = dst - src - (GET_XFLG() ? 1 : 0);
	int oldz = GET_ZFLG();
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_VFLG((flgs ^ flgo) & (flgo ^ flgn));
	SET_CFLG(flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
	COPY_CARRY();
	SET_ZFLG(GET_ZFLG() & (((uae_s32)(newv)) == 0));
	SET_NFLG(((uae_s32)(newv)) < 0);
	x_put_word(dsta + 2, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		int bflgs = ((uae_s16)(src)) < 0;
		int bflgo = ((uae_s16)(dst)) < 0;
		int bflgn = ((uae_s16)(newv)) < 0;
		SET_VFLG((bflgs ^ bflgo) & (bflgo ^ bflgn));
		SET_CFLG(bflgs ^ ((bflgs ^ bflgn) & (bflgo ^ bflgn)));
		COPY_CARRY();
		SET_ZFLG(GET_ZFLG() & (((uae_s16)(newv)) == 0));
		SET_NFLG(((uae_s16)(newv)) < 0);
		exception2_write(opcode, dsta + 2, 0x1, newv, 1);
		return;
	}
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_ce000_prefetch(4);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return;
		}
	} else {
		loop_mode = 0;
		loop_mode |= 2;
		loop_mode |= 2 << 16;
	}
	x_put_word(dsta, newv >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x1, newv >> 16, 1);
		return;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return;
}
/* 30 (5/2) */
/* 2 0,0   */

/* SUB.L Dn,(An) */
void REGPARAM2 op_9190_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 20; 
	int loop_mode = regs.loop_mode;
	uae_s32 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	if (dsta & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dsta, 2, 1);
		return;
	}
	uae_s32 dst = x_get_word(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	dst |= x_get_word(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return;
	}
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_ce000_prefetch(4);
		if(hardware_bus_error) {
			int pcoffset = 0;
			uae_s16 bnewv = (uae_s16)dst - (uae_s16)src;
			int bflgs = ((uae_s16)(src)) < 0;
			int bflgo = ((uae_s16)(dst)) < 0;
			int bflgn = bnewv < 0;
			ccr_68000_long_move_ae_LZN(bnewv);
			SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
			SET_XFLG(GET_CFLG());
			SET_VFLG((bflgs ^ bflgo) & (bflgn ^ bflgo));
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return;
		}
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	if(loop_mode & 0xfffe) {
		do_cycles_ce000_internal(loop_mode & 0xfffe);
		loop_mode = 1;
	}
	x_put_word(dsta + 2, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 2, 0x1, newv, 1);
		return;
	}
	x_put_word(dsta, newv >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x1, newv >> 16, 1);
		return;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return;
}
/* 20 (3/2) */
/* 2 0,0   */

/* SUB.L Dn,(An)+ */
void REGPARAM2 op_9198_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 20; 
	int loop_mode = regs.loop_mode;
	uae_s32 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	if (dsta & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dsta, 2, 1);
		return;
	}
	uae_s32 dst = x_get_word(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	dst |= x_get_word(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return;
	}
	m68k_areg(regs, dstreg) += 4;
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_ce000_prefetch(4);
		if(hardware_bus_error) {
			int pcoffset = 0;
			uae_s16 bnewv = (uae_s16)dst - (uae_s16)src;
			int bflgs = ((uae_s16)(src)) < 0;
			int bflgo = ((uae_s16)(dst)) < 0;
			int bflgn = bnewv < 0;
			ccr_68000_long_move_ae_LZN(bnewv);
			SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
			SET_XFLG(GET_CFLG());
			SET_VFLG((bflgs ^ bflgo) & (bflgn ^ bflgo));
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return;
		}
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	if(loop_mode & 0xfffe) {
		do_cycles_ce000_internal(loop_mode & 0xfffe);
		loop_mode = 1;
	}
	x_put_word(dsta + 2, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 2, 0x1, newv, 1);
		return;
	}
	x_put_word(dsta, newv >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x1, newv >> 16, 1);
		return;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return;
}
/* 20 (3/2) */
/* 2 0,0   */

/* SUB.L Dn,-(An) */
void REGPARAM2 op_91a0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 22; 
	int loop_mode = regs.loop_mode;
	uae_s32 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - 4;
	do_cycles_ce000_internal(2);
	if (dsta & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dsta, 2, 1);
		return;
	}
	uae_s32 dst = x_get_word(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	dst |= x_get_word(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, dstreg) = dsta;
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return;
	}
	m68k_areg(regs, dstreg) = dsta;
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_ce000_prefetch(4);
		if(hardware_bus_error) {
			int pcoffset = 0;
			uae_s16 bnewv = (uae_s16)dst - (uae_s16)src;
			int bflgs = ((uae_s16)(src)) < 0;
			int bflgo = ((uae_s16)(dst)) < 0;
			int bflgn = bnewv < 0;
			ccr_68000_long_move_ae_LZN(bnewv);
			SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
			SET_XFLG(GET_CFLG());
			SET_VFLG((bflgs ^ bflgo) & (bflgn ^ bflgo));
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return;
		}
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	if(loop_mode & 0xfffe) {
		do_cycles_ce000_internal(loop_mode & 0xfffe);
		loop_mode = 1;
	}
	x_put_word(dsta + 2, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 2, 0x1, newv, 1);
		return;
	}
	x_put_word(dsta, newv >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x1, newv >> 16, 1);
		return;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return;
}
/* 22 (3/2) */
/* 2 0,0   */

/* SUB.L Dn,(d16,An) */
void REGPARAM2 op_91a8_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 24; 
	uae_s32 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dsta, 2, 1);
		return;
	}
	uae_s32 dst = x_get_word(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	dst |= x_get_word(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return;
	}
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		uae_s16 bnewv = (uae_s16)dst - (uae_s16)src;
		int bflgs = ((uae_s16)(src)) < 0;
		int bflgo = ((uae_s16)(dst)) < 0;
		int bflgn = bnewv < 0;
		ccr_68000_long_move_ae_LZN(bnewv);
		SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
		SET_XFLG(GET_CFLG());
		SET_VFLG((bflgs ^ bflgo) & (bflgn ^ bflgo));
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	x_put_word(dsta + 2, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 2, 0x1, newv, 1);
		return;
	}
	x_put_word(dsta, newv >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, newv >> 16, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 24 (4/2) */
/* 4 0,0   */

/* SUB.L Dn,(d8,An,Xn) */
void REGPARAM2 op_91b0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 26; 
	uae_s32 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	do_cycles_ce000_internal(2);
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dsta, 2, 1);
		return;
	}
	uae_s32 dst = x_get_word(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	dst |= x_get_word(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return;
	}
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		uae_s16 bnewv = (uae_s16)dst - (uae_s16)src;
		int bflgs = ((uae_s16)(src)) < 0;
		int bflgo = ((uae_s16)(dst)) < 0;
		int bflgn = bnewv < 0;
		ccr_68000_long_move_ae_LZN(bnewv);
		SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
		SET_XFLG(GET_CFLG());
		SET_VFLG((bflgs ^ bflgo) & (bflgn ^ bflgo));
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	x_put_word(dsta + 2, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 2, 0x1, newv, 1);
		return;
	}
	x_put_word(dsta, newv >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, newv >> 16, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 26 (4/2) */
/* 4 4,0   */

/* SUB.L Dn,(xxx).W */
void REGPARAM2 op_91b8_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	OpcodeFamily = 7;
	CurrentInstrCycles = 24; 
	uae_s32 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, dsta, 2, 1);
		return;
	}
	uae_s32 dst = x_get_word(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	dst |= x_get_word(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return;
	}
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		uae_s16 bnewv = (uae_s16)dst - (uae_s16)src;
		int bflgs = ((uae_s16)(src)) < 0;
		int bflgo = ((uae_s16)(dst)) < 0;
		int bflgn = bnewv < 0;
		ccr_68000_long_move_ae_LZN(bnewv);
		SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
		SET_XFLG(GET_CFLG());
		SET_VFLG((bflgs ^ bflgo) & (bflgn ^ bflgo));
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	x_put_word(dsta + 2, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 2, 0x1, newv, 1);
		return;
	}
	x_put_word(dsta, newv >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, newv >> 16, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 24 (4/2) */
/* 4 0,0   */

/* SUB.L Dn,(xxx).L */
void REGPARAM2 op_91b9_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	OpcodeFamily = 7;
	CurrentInstrCycles = 28; 
	uae_s32 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	dsta |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, dsta, 2, 1);
		return;
	}
	uae_s32 dst = x_get_word(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	dst |= x_get_word(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return;
	}
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		uae_s16 bnewv = (uae_s16)dst - (uae_s16)src;
		int bflgs = ((uae_s16)(src)) < 0;
		int bflgo = ((uae_s16)(dst)) < 0;
		int bflgn = bnewv < 0;
		ccr_68000_long_move_ae_LZN(bnewv);
		SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
		SET_XFLG(GET_CFLG());
		SET_VFLG((bflgs ^ bflgo) & (bflgn ^ bflgo));
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	x_put_word(dsta + 2, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 2, 0x1, newv, 1);
		return;
	}
	x_put_word(dsta, newv >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 0, 0x1, newv >> 16, 1);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 28 (5/2) */
/* 6 0,0   */

/* SUBA.L Dn,An */
void REGPARAM2 op_91c0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 8;
	CurrentInstrCycles = 8;  
	uae_s32 src = m68k_dreg(regs, srcreg);
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = dst - src;
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		areg_68000_long_replace_low(dstreg, newv);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	do_cycles_ce000_internal(4);
	m68k_areg(regs, dstreg) = (newv);
	m68k_incpci(2);
	return;
}
/* 8 (1/0) */
/* 2 0,0   */

/* SUBA.L An,An */
void REGPARAM2 op_91c8_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 8;
	CurrentInstrCycles = 8;  
	uae_s32 src = m68k_areg(regs, srcreg);
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = dst - src;
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		areg_68000_long_replace_low(dstreg, newv);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	do_cycles_ce000_internal(4);
	m68k_areg(regs, dstreg) = (newv);
	m68k_incpci(2);
	return;
}
/* 8 (1/0) */
/* 2 0,0   */

/* SUBA.L (An),An */
void REGPARAM2 op_91d0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 8;
	CurrentInstrCycles = 14; 
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = dst - src;
	ipl_fetch_next_pre();
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_ce000_prefetch(4);
		if(hardware_bus_error) {
			int pcoffset = 0;
			areg_68000_long_replace_low(dstreg, newv);
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return;
		}
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	do_cycles_ce000_internal(2);
	if(loop_mode & 0xfffe) {
		do_cycles_ce000_internal(loop_mode & 0xfffe);
		loop_mode = 1;
	}
	m68k_areg(regs, dstreg) = (newv);
	if (loop_mode) {
		do_cycles_ce000_internal(4);
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return;
}
/* 14 (3/0) */
/* 2 0,0   */

/* SUBA.L (An)+,An */
void REGPARAM2 op_91d8_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 8;
	CurrentInstrCycles = 14; 
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	m68k_areg(regs, srcreg) += 4;
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = dst - src;
	ipl_fetch_next_pre();
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_ce000_prefetch(4);
		if(hardware_bus_error) {
			int pcoffset = 0;
			areg_68000_long_replace_low(dstreg, newv);
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return;
		}
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	do_cycles_ce000_internal(2);
	if(loop_mode & 0xfffe) {
		do_cycles_ce000_internal(loop_mode & 0xfffe);
		loop_mode = 1;
	}
	m68k_areg(regs, dstreg) = (newv);
	if (loop_mode) {
		do_cycles_ce000_internal(4);
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return;
}
/* 14 (3/0) */
/* 2 0,0   */

/* SUBA.L -(An),An */
void REGPARAM2 op_91e0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 8;
	CurrentInstrCycles = 16; 
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - 4;
	do_cycles_ce000_internal(2);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	m68k_areg(regs, srcreg) = srca;
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = dst - src;
	ipl_fetch_next_pre();
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_ce000_prefetch(4);
		if(hardware_bus_error) {
			int pcoffset = 0;
			areg_68000_long_replace_low(dstreg, newv);
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return;
		}
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	do_cycles_ce000_internal(2);
	if(loop_mode & 0xfffe) {
		do_cycles_ce000_internal(loop_mode & 0xfffe);
		loop_mode = 1;
	}
	m68k_areg(regs, dstreg) = (newv);
	if (loop_mode) {
		do_cycles_ce000_internal(4);
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return;
}
/* 16 (3/0) */
/* 2 0,0   */

/* SUBA.L (d16,An),An */
void REGPARAM2 op_91e8_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 8;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = dst - src;
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		areg_68000_long_replace_low(dstreg, newv);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	do_cycles_ce000_internal(2);
	m68k_areg(regs, dstreg) = (newv);
	m68k_incpci(4);
	return;
}
/* 18 (4/0) */
/* 4 0,0   */

/* SUBA.L (d8,An,Xn),An */
void REGPARAM2 op_91f0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 8;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	do_cycles_ce000_internal(2);
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = dst - src;
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		areg_68000_long_replace_low(dstreg, newv);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	do_cycles_ce000_internal(2);
	m68k_areg(regs, dstreg) = (newv);
	m68k_incpci(4);
	return;
}
/* 20 (4/0) */
/* 4 4,0   */

/* SUBA.L (xxx).W,An */
void REGPARAM2 op_91f8_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 8;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	if (srca & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = dst - src;
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		areg_68000_long_replace_low(dstreg, newv);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	do_cycles_ce000_internal(2);
	m68k_areg(regs, dstreg) = (newv);
	m68k_incpci(4);
	return;
}
/* 18 (4/0) */
/* 4 0,0   */

/* SUBA.L (xxx).L,An */
void REGPARAM2 op_91f9_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 8;
	CurrentInstrCycles = 22; 
	uaecptr srca;
	srca = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	srca |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	if (srca & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = dst - src;
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		areg_68000_long_replace_low(dstreg, newv);
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	do_cycles_ce000_internal(2);
	m68k_areg(regs, dstreg) = (newv);
	m68k_incpci(6);
	return;
}
/* 22 (5/0) */
/* 6 0,0   */

/* SUBA.L (d16,PC),An */
void REGPARAM2 op_91fa_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 8;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	srca = m68k_getpci() + 2;
	srca += (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 2);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return;
	}
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 2);
		return;
	}
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = dst - src;
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		areg_68000_long_replace_low(dstreg, newv);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	do_cycles_ce000_internal(2);
	m68k_areg(regs, dstreg) = (newv);
	m68k_incpci(4);
	return;
}
/* 18 (4/0) */
/* 4 0,0   */

/* SUBA.L (d8,PC,Xn),An */
void REGPARAM2 op_91fb_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 8;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	uaecptr tmppc = m68k_getpci() + 2;
	do_cycles_ce000_internal(2);
	srca = get_disp_ea_000(tmppc, get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 2);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return;
	}
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 2);
		return;
	}
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = dst - src;
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		areg_68000_long_replace_low(dstreg, newv);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	do_cycles_ce000_internal(2);
	m68k_areg(regs, dstreg) = (newv);
	m68k_incpci(4);
	return;
}
/* 20 (4/0) */
/* 4 4,0   */

/* SUBA.L #<data>.L,An */
void REGPARAM2 op_91fc_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 8;
	CurrentInstrCycles = 16; 
	uae_s32 src;
	src = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	src |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = dst - src;
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		areg_68000_long_replace_low(dstreg, newv);
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	do_cycles_ce000_internal(4);
	m68k_areg(regs, dstreg) = (newv);
	m68k_incpci(6);
	return;
}
/* 16 (3/0) */
/* 6 0,0   */

/* CMP.B Dn,Dn */
void REGPARAM2 op_b000_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 25;
	CurrentInstrCycles = 4;  
	uae_s8 src = m68k_dreg(regs, srcreg);
	uae_s8 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 4 (1/0) */
/* 2 0,0   */

/* CMP.B (An),Dn */
void REGPARAM2 op_b010_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 25;
	CurrentInstrCycles = 8;  
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	uae_s8 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
	SET_NFLG(flgn != 0);
	if(!loop_mode) {
		regs.ir = regs.irc;
		opcode = regs.ir;
		get_word_ce000_prefetch(4);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return;
		}
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return;
}
/* 8 (2/0) */
/* 2 0,0   */

/* CMP.B (An)+,Dn */
void REGPARAM2 op_b018_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 25;
	CurrentInstrCycles = 8;  
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
	uae_s8 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
	SET_NFLG(flgn != 0);
	if(!loop_mode) {
		regs.ir = regs.irc;
		opcode = regs.ir;
		get_word_ce000_prefetch(4);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return;
		}
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return;
}
/* 8 (2/0) */
/* 2 0,0   */

/* CMP.B -(An),Dn */
void REGPARAM2 op_b020_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 25;
	CurrentInstrCycles = 10; 
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
	do_cycles_ce000_internal(2);
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	m68k_areg(regs, srcreg) = srca;
	uae_s8 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
	SET_NFLG(flgn != 0);
	if(!loop_mode) {
		regs.ir = regs.irc;
		opcode = regs.ir;
		get_word_ce000_prefetch(4);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return;
		}
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return;
}
/* 10 (2/0) */
/* 2 0,0   */

/* CMP.B (d16,An),Dn */
void REGPARAM2 op_b028_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 25;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	uae_s8 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 12 (3/0) */
/* 4 0,0   */

/* CMP.B (d8,An,Xn),Dn */
void REGPARAM2 op_b030_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 25;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	do_cycles_ce000_internal(2);
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	uae_s8 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 14 (3/0) */
/* 4 4,0   */

/* CMP.B (xxx).W,Dn */
void REGPARAM2 op_b038_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 25;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	uae_s8 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 12 (3/0) */
/* 4 0,0   */

/* CMP.B (xxx).L,Dn */
void REGPARAM2 op_b039_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 25;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	srca |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	uae_s8 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 16 (4/0) */
/* 6 0,0   */

/* CMP.B (d16,PC),Dn */
void REGPARAM2 op_b03a_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 25;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_getpci() + 2;
	srca += (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 2);
		return;
	}
	uae_s8 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 12 (3/0) */
/* 4 0,0   */

/* CMP.B (d8,PC,Xn),Dn */
void REGPARAM2 op_b03b_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 25;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	uaecptr tmppc = m68k_getpci() + 2;
	do_cycles_ce000_internal(2);
	srca = get_disp_ea_000(tmppc, get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 2);
		return;
	}
	uae_s8 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 14 (3/0) */
/* 4 4,0   */

/* CMP.B #<data>.B,Dn */
void REGPARAM2 op_b03c_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 25;
	CurrentInstrCycles = 8;  
	uae_s8 src = (uae_u8)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uae_s8 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 8 (2/0) */
/* 4 0,0   */

/* CMP.W Dn,Dn */
void REGPARAM2 op_b040_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 25;
	CurrentInstrCycles = 4;  
	uae_s16 src = m68k_dreg(regs, srcreg);
	uae_s16 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 4 (1/0) */
/* 2 0,0   */

/* CMP.W An,Dn */
void REGPARAM2 op_b048_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 25;
	CurrentInstrCycles = 4;  
	uae_s16 src = m68k_areg(regs, srcreg);
	uae_s16 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 4 (1/0) */
/* 2 0,0   */

/* CMP.W (An),Dn */
void REGPARAM2 op_b050_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 25;
	CurrentInstrCycles = 8;  
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access2(opcode, srca, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
	SET_NFLG(flgn != 0);
	if(!loop_mode) {
		regs.ir = regs.irc;
		opcode = regs.ir;
		get_word_ce000_prefetch(4);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return;
		}
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return;
}
/* 8 (2/0) */
/* 2 0,0   */

/* CMP.W (An)+,Dn */
void REGPARAM2 op_b058_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 25;
	CurrentInstrCycles = 8;  
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_areg(regs, srcreg) += 2 + 0;
		m68k_incpci(2);
		exception3_read_access2(opcode, srca, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) += 2 + 0;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	m68k_areg(regs, srcreg) += 2;
	uae_s16 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
	SET_NFLG(flgn != 0);
	if(!loop_mode) {
		regs.ir = regs.irc;
		opcode = regs.ir;
		get_word_ce000_prefetch(4);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return;
		}
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return;
}
/* 8 (2/0) */
/* 2 0,0   */

/* CMP.W -(An),Dn */
void REGPARAM2 op_b060_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 25;
	CurrentInstrCycles = 10; 
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - 2;
	do_cycles_ce000_internal(2);
	if (srca & 1) {
		m68k_areg(regs, srcreg) = srca;
		m68k_incpci(2);
		exception3_read_access2(opcode, srca, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	m68k_areg(regs, srcreg) = srca;
	uae_s16 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
	SET_NFLG(flgn != 0);
	if(!loop_mode) {
		regs.ir = regs.irc;
		opcode = regs.ir;
		get_word_ce000_prefetch(4);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return;
		}
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return;
}
/* 10 (2/0) */
/* 2 0,0   */

/* CMP.W (d16,An),Dn */
void REGPARAM2 op_b068_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 25;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 12 (3/0) */
/* 4 0,0   */

/* CMP.W (d8,An,Xn),Dn */
void REGPARAM2 op_b070_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 25;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	do_cycles_ce000_internal(2);
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 14 (3/0) */
/* 4 4,0   */

/* CMP.W (xxx).W,Dn */
void REGPARAM2 op_b078_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 25;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	if (srca & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 12 (3/0) */
/* 4 0,0   */

/* CMP.W (xxx).L,Dn */
void REGPARAM2 op_b079_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 25;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	srca |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	if (srca & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 16 (4/0) */
/* 6 0,0   */

/* CMP.W (d16,PC),Dn */
void REGPARAM2 op_b07a_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 25;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_getpci() + 2;
	srca += (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 2);
		return;
	}
	ipl_fetch_now();
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 12 (3/0) */
/* 4 0,0   */

/* CMP.W (d8,PC,Xn),Dn */
void REGPARAM2 op_b07b_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 25;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	uaecptr tmppc = m68k_getpci() + 2;
	do_cycles_ce000_internal(2);
	srca = get_disp_ea_000(tmppc, get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 2);
		return;
	}
	ipl_fetch_now();
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 14 (3/0) */
/* 4 4,0   */

/* CMP.W #<data>.W,Dn */
void REGPARAM2 op_b07c_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 25;
	CurrentInstrCycles = 8;  
	uae_s16 src = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 8 (2/0) */
/* 4 0,0   */

/* CMP.L Dn,Dn */
void REGPARAM2 op_b080_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 25;
	CurrentInstrCycles = 6;  
	uae_s32 src = m68k_dreg(regs, srcreg);
	uae_s32 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	SET_NFLG(flgn != 0);
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	do_cycles_ce000_internal(2);
	m68k_incpci(2);
	return;
}
/* 6 (1/0) */
/* 2 0,0   */

/* CMP.L An,Dn */
void REGPARAM2 op_b088_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 25;
	CurrentInstrCycles = 6;  
	uae_s32 src = m68k_areg(regs, srcreg);
	uae_s32 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	SET_NFLG(flgn != 0);
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	do_cycles_ce000_internal(2);
	m68k_incpci(2);
	return;
}
/* 6 (1/0) */
/* 2 0,0   */

/* CMP.L (An),Dn */
void REGPARAM2 op_b090_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 25;
	CurrentInstrCycles = 14; 
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	SET_NFLG(flgn != 0);
	ipl_fetch_next_pre();
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_ce000_prefetch(4);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return;
		}
		opcode = regs.ir;
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 2 << 16;
	}
	do_cycles_ce000_internal(2);
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return;
}
/* 14 (3/0) */
/* 2 0,0   */

/* CMP.L (An)+,Dn */
void REGPARAM2 op_b098_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 25;
	CurrentInstrCycles = 14; 
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	m68k_areg(regs, srcreg) += 4;
	uae_s32 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	SET_NFLG(flgn != 0);
	ipl_fetch_next_pre();
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_ce000_prefetch(4);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return;
		}
		opcode = regs.ir;
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 2 << 16;
	}
	do_cycles_ce000_internal(2);
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return;
}
/* 14 (3/0) */
/* 2 0,0   */

/* CMP.L -(An),Dn */
void REGPARAM2 op_b0a0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 25;
	CurrentInstrCycles = 16; 
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - 4;
	do_cycles_ce000_internal(2);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	m68k_areg(regs, srcreg) = srca;
	uae_s32 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	SET_NFLG(flgn != 0);
	ipl_fetch_next_pre();
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_ce000_prefetch(4);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return;
		}
		opcode = regs.ir;
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 2 << 16;
	}
	do_cycles_ce000_internal(2);
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return;
}
/* 16 (3/0) */
/* 2 0,0   */

/* CMP.L (d16,An),Dn */
void REGPARAM2 op_b0a8_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 25;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	SET_NFLG(flgn != 0);
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	do_cycles_ce000_internal(2);
	m68k_incpci(4);
	return;
}
/* 18 (4/0) */
/* 4 0,0   */

/* CMP.L (d8,An,Xn),Dn */
void REGPARAM2 op_b0b0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 25;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	do_cycles_ce000_internal(2);
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	SET_NFLG(flgn != 0);
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	do_cycles_ce000_internal(2);
	m68k_incpci(4);
	return;
}
/* 20 (4/0) */
/* 4 4,0   */

/* CMP.L (xxx).W,Dn */
void REGPARAM2 op_b0b8_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 25;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	if (srca & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	SET_NFLG(flgn != 0);
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	do_cycles_ce000_internal(2);
	m68k_incpci(4);
	return;
}
/* 18 (4/0) */
/* 4 0,0   */

/* CMP.L (xxx).L,Dn */
void REGPARAM2 op_b0b9_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 25;
	CurrentInstrCycles = 22; 
	uaecptr srca;
	srca = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	srca |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	if (srca & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	SET_NFLG(flgn != 0);
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	opcode = regs.ir;
	do_cycles_ce000_internal(2);
	m68k_incpci(6);
	return;
}
/* 22 (5/0) */
/* 6 0,0   */

/* CMP.L (d16,PC),Dn */
void REGPARAM2 op_b0ba_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 25;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	srca = m68k_getpci() + 2;
	srca += (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 2);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return;
	}
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 2);
		return;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	SET_NFLG(flgn != 0);
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	do_cycles_ce000_internal(2);
	m68k_incpci(4);
	return;
}
/* 18 (4/0) */
/* 4 0,0   */

/* CMP.L (d8,PC,Xn),Dn */
void REGPARAM2 op_b0bb_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 25;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	uaecptr tmppc = m68k_getpci() + 2;
	do_cycles_ce000_internal(2);
	srca = get_disp_ea_000(tmppc, get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 2);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return;
	}
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 2);
		return;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	SET_NFLG(flgn != 0);
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	do_cycles_ce000_internal(2);
	m68k_incpci(4);
	return;
}
/* 20 (4/0) */
/* 4 4,0   */

/* CMP.L #<data>.L,Dn */
void REGPARAM2 op_b0bc_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 25;
	CurrentInstrCycles = 14; 
	uae_s32 src;
	src = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	src |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	SET_NFLG(flgn != 0);
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	opcode = regs.ir;
	do_cycles_ce000_internal(2);
	m68k_incpci(6);
	return;
}
/* 14 (3/0) */
/* 6 0,0   */

/* CMPA.W Dn,An */
void REGPARAM2 op_b0c0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 27;
	CurrentInstrCycles = 6;  
	uae_s16 src = m68k_dreg(regs, srcreg);
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	SET_NFLG(flgn != 0);
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	do_cycles_ce000_internal(2);
	m68k_incpci(2);
	return;
}
/* 6 (1/0) */
/* 2 0,0   */

/* CMPA.W An,An */
void REGPARAM2 op_b0c8_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 27;
	CurrentInstrCycles = 6;  
	uae_s16 src = m68k_areg(regs, srcreg);
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	SET_NFLG(flgn != 0);
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	do_cycles_ce000_internal(2);
	m68k_incpci(2);
	return;
}
/* 6 (1/0) */
/* 2 0,0   */

/* CMPA.W (An),An */
void REGPARAM2 op_b0d0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 27;
	CurrentInstrCycles = 10; 
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access2(opcode, srca, 1, 1);
		return;
	}
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	SET_NFLG(flgn != 0);
	ipl_fetch_next_pre();
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_ce000_prefetch(4);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return;
		}
		opcode = regs.ir;
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	do_cycles_ce000_internal(2);
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return;
}
/* 10 (2/0) */
/* 2 0,0   */

/* CMPA.W (An)+,An */
void REGPARAM2 op_b0d8_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 27;
	CurrentInstrCycles = 10; 
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_areg(regs, srcreg) += 2 + 0;
		m68k_incpci(2);
		exception3_read_access2(opcode, srca, 1, 1);
		return;
	}
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) += 2 + 0;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	m68k_areg(regs, srcreg) += 2;
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	SET_NFLG(flgn != 0);
	ipl_fetch_next_pre();
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_ce000_prefetch(4);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return;
		}
		opcode = regs.ir;
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	do_cycles_ce000_internal(2);
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return;
}
/* 10 (2/0) */
/* 2 0,0   */

/* CMPA.W -(An),An */
void REGPARAM2 op_b0e0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 27;
	CurrentInstrCycles = 12; 
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - 2;
	do_cycles_ce000_internal(2);
	if (srca & 1) {
		m68k_areg(regs, srcreg) = srca;
		m68k_incpci(2);
		exception3_read_access2(opcode, srca, 1, 1);
		return;
	}
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	m68k_areg(regs, srcreg) = srca;
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	SET_NFLG(flgn != 0);
	ipl_fetch_next_pre();
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_ce000_prefetch(4);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return;
		}
		opcode = regs.ir;
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	do_cycles_ce000_internal(2);
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return;
}
/* 12 (2/0) */
/* 2 0,0   */

/* CMPA.W (d16,An),An */
void REGPARAM2 op_b0e8_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 27;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	SET_NFLG(flgn != 0);
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	do_cycles_ce000_internal(2);
	m68k_incpci(4);
	return;
}
/* 14 (3/0) */
/* 4 0,0   */

/* CMPA.W (d8,An,Xn),An */
void REGPARAM2 op_b0f0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 27;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	do_cycles_ce000_internal(2);
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	SET_NFLG(flgn != 0);
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	do_cycles_ce000_internal(2);
	m68k_incpci(4);
	return;
}
/* 16 (3/0) */
/* 4 4,0   */

/* CMPA.W (xxx).W,An */
void REGPARAM2 op_b0f8_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 27;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	if (srca & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	SET_NFLG(flgn != 0);
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	do_cycles_ce000_internal(2);
	m68k_incpci(4);
	return;
}
/* 14 (3/0) */
/* 4 0,0   */

/* CMPA.W (xxx).L,An */
void REGPARAM2 op_b0f9_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 27;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	srca = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	srca |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	if (srca & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	SET_NFLG(flgn != 0);
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	opcode = regs.ir;
	do_cycles_ce000_internal(2);
	m68k_incpci(6);
	return;
}
/* 18 (4/0) */
/* 6 0,0   */

/* CMPA.W (d16,PC),An */
void REGPARAM2 op_b0fa_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 27;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	srca = m68k_getpci() + 2;
	srca += (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 2);
		return;
	}
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return;
	}
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	SET_NFLG(flgn != 0);
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	do_cycles_ce000_internal(2);
	m68k_incpci(4);
	return;
}
/* 14 (3/0) */
/* 4 0,0   */

/* CMPA.W (d8,PC,Xn),An */
void REGPARAM2 op_b0fb_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 27;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	uaecptr tmppc = m68k_getpci() + 2;
	do_cycles_ce000_internal(2);
	srca = get_disp_ea_000(tmppc, get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 2);
		return;
	}
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return;
	}
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	SET_NFLG(flgn != 0);
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	do_cycles_ce000_internal(2);
	m68k_incpci(4);
	return;
}
/* 16 (3/0) */
/* 4 4,0   */

/* CMPA.W #<data>.W,An */
void REGPARAM2 op_b0fc_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 27;
	CurrentInstrCycles = 10; 
	uae_s16 src = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	SET_NFLG(flgn != 0);
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	do_cycles_ce000_internal(2);
	m68k_incpci(4);
	return;
}
/* 10 (2/0) */
/* 4 0,0   */

/* EOR.B Dn,Dn */
void REGPARAM2 op_b100_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 3;
	CurrentInstrCycles = 4;  
	uae_s8 src = m68k_dreg(regs, srcreg);
	uae_s8 dst = m68k_dreg(regs, dstreg);
	src ^= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 4 (1/0) */
/* 2 0,0   */

/* CMPM.B (An)+,(An)+ */
void REGPARAM2 op_b108_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 26;
	CurrentInstrCycles = 12; 
	int loop_mode = regs.loop_mode;
	ipl_fetch_now();
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) += areg_byteinc[srcreg] + 0;
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
	uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
	SET_NFLG(flgn != 0);
	if(!loop_mode) {
		regs.ir = regs.irc;
		opcode = regs.ir;
		get_word_ce000_prefetch(4);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return;
		}
	} else {
		loop_mode = 0;
		loop_mode |= 2;
		loop_mode |= 2 << 16;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return;
}
/* 12 (3/0) */
/* 2 0,0   */

/* EOR.B Dn,(An) */
void REGPARAM2 op_b110_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 3;
	CurrentInstrCycles = 12; 
	int loop_mode = regs.loop_mode;
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	src ^= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_ce000_prefetch(4);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return;
		}
		opcode = regs.ir;
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	if(loop_mode & 0xfffe) {
		do_cycles_ce000_internal(loop_mode & 0xfffe);
		loop_mode = 1;
	}
	x_put_byte(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return;
}
/* 12 (2/1) */
/* 2 0,0   */

/* EOR.B Dn,(An)+ */
void REGPARAM2 op_b118_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 3;
	CurrentInstrCycles = 12; 
	int loop_mode = regs.loop_mode;
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
	src ^= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_ce000_prefetch(4);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return;
		}
		opcode = regs.ir;
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	if(loop_mode & 0xfffe) {
		do_cycles_ce000_internal(loop_mode & 0xfffe);
		loop_mode = 1;
	}
	x_put_byte(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return;
}
/* 12 (2/1) */
/* 2 0,0   */

/* EOR.B Dn,-(An) */
void REGPARAM2 op_b120_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 3;
	CurrentInstrCycles = 14; 
	int loop_mode = regs.loop_mode;
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
	do_cycles_ce000_internal(2);
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, dstreg) = dsta;
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	m68k_areg(regs, dstreg) = dsta;
	src ^= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_ce000_prefetch(4);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return;
		}
		opcode = regs.ir;
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	if(loop_mode & 0xfffe) {
		do_cycles_ce000_internal(loop_mode & 0xfffe);
		loop_mode = 1;
	}
	x_put_byte(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return;
}
/* 14 (2/1) */
/* 2 0,0   */

/* EOR.B Dn,(d16,An) */
void REGPARAM2 op_b128_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 3;
	CurrentInstrCycles = 16; 
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	src ^= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_byte(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* EOR.B Dn,(d8,An,Xn) */
void REGPARAM2 op_b130_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 3;
	CurrentInstrCycles = 18; 
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	do_cycles_ce000_internal(2);
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	src ^= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_byte(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 18 (3/1) */
/* 4 4,0   */

/* EOR.B Dn,(xxx).W */
void REGPARAM2 op_b138_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	OpcodeFamily = 3;
	CurrentInstrCycles = 16; 
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	src ^= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_byte(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* EOR.B Dn,(xxx).L */
void REGPARAM2 op_b139_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	OpcodeFamily = 3;
	CurrentInstrCycles = 20; 
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	dsta |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	src ^= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_byte(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 20 (4/1) */
/* 6 0,0   */

/* EOR.W Dn,Dn */
void REGPARAM2 op_b140_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 3;
	CurrentInstrCycles = 4;  
	uae_s16 src = m68k_dreg(regs, srcreg);
	uae_s16 dst = m68k_dreg(regs, dstreg);
	src ^= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 4 (1/0) */
/* 2 0,0   */

/* CMPM.W (An)+,(An)+ */
void REGPARAM2 op_b148_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 26;
	CurrentInstrCycles = 12; 
	int loop_mode = regs.loop_mode;
	ipl_fetch_now();
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_areg(regs, srcreg) += 2 + 0;
		m68k_incpci(2);
		exception3_read_access2(opcode, srca, 1, 1);
		return;
	}
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) += 2 + 0;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	m68k_areg(regs, srcreg) += 2;
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	if (dsta & 1) {
		m68k_areg(regs, dstreg) += 2 + 0;
		m68k_incpci(2);
		exception3_read_access2(opcode, dsta, 1, 1);
		return;
	}
	uae_s16 dst = x_get_word(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, dstreg) += 2 + 0;
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	m68k_areg(regs, dstreg) += 2;
	uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
	SET_NFLG(flgn != 0);
	if(!loop_mode) {
		regs.ir = regs.irc;
		opcode = regs.ir;
		get_word_ce000_prefetch(4);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return;
		}
	} else {
		loop_mode = 0;
		loop_mode |= 2;
		loop_mode |= 2 << 16;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return;
}
/* 12 (3/0) */
/* 2 0,0   */

/* EOR.W Dn,(An) */
void REGPARAM2 op_b150_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 3;
	CurrentInstrCycles = 12; 
	int loop_mode = regs.loop_mode;
	uae_s16 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	if (dsta & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dsta, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 dst = x_get_word(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	src ^= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_ce000_prefetch(4);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return;
		}
		opcode = regs.ir;
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	if(loop_mode & 0xfffe) {
		do_cycles_ce000_internal(loop_mode & 0xfffe);
		loop_mode = 1;
	}
	x_put_word(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return;
}
/* 12 (2/1) */
/* 2 0,0   */

/* EOR.W Dn,(An)+ */
void REGPARAM2 op_b158_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 3;
	CurrentInstrCycles = 12; 
	int loop_mode = regs.loop_mode;
	uae_s16 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	if (dsta & 1) {
		m68k_areg(regs, dstreg) += 2 + 0;
		m68k_incpci(2);
		exception3_read_access(opcode, dsta, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 dst = x_get_word(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, dstreg) += 2 + 0;
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	m68k_areg(regs, dstreg) += 2;
	src ^= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_ce000_prefetch(4);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return;
		}
		opcode = regs.ir;
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	if(loop_mode & 0xfffe) {
		do_cycles_ce000_internal(loop_mode & 0xfffe);
		loop_mode = 1;
	}
	x_put_word(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return;
}
/* 12 (2/1) */
/* 2 0,0   */

/* EOR.W Dn,-(An) */
void REGPARAM2 op_b160_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 3;
	CurrentInstrCycles = 14; 
	int loop_mode = regs.loop_mode;
	uae_s16 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - 2;
	do_cycles_ce000_internal(2);
	if (dsta & 1) {
		m68k_areg(regs, dstreg) = dsta;
		m68k_incpci(2);
		exception3_read_access(opcode, dsta, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 dst = x_get_word(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, dstreg) = dsta;
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	m68k_areg(regs, dstreg) = dsta;
	src ^= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_ce000_prefetch(4);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return;
		}
		opcode = regs.ir;
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	if(loop_mode & 0xfffe) {
		do_cycles_ce000_internal(loop_mode & 0xfffe);
		loop_mode = 1;
	}
	x_put_word(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return;
}
/* 14 (2/1) */
/* 2 0,0   */

/* EOR.W Dn,(d16,An) */
void REGPARAM2 op_b168_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 3;
	CurrentInstrCycles = 16; 
	uae_s16 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dsta, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 dst = x_get_word(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	src ^= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_word(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* EOR.W Dn,(d8,An,Xn) */
void REGPARAM2 op_b170_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 3;
	CurrentInstrCycles = 18; 
	uae_s16 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	do_cycles_ce000_internal(2);
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dsta, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 dst = x_get_word(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	src ^= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_word(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 18 (3/1) */
/* 4 4,0   */

/* EOR.W Dn,(xxx).W */
void REGPARAM2 op_b178_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	OpcodeFamily = 3;
	CurrentInstrCycles = 16; 
	uae_s16 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, dsta, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 dst = x_get_word(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	src ^= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_word(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* EOR.W Dn,(xxx).L */
void REGPARAM2 op_b179_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	OpcodeFamily = 3;
	CurrentInstrCycles = 20; 
	uae_s16 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	dsta |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, dsta, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 dst = x_get_word(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	src ^= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_word(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 20 (4/1) */
/* 6 0,0   */

/* EOR.L Dn,Dn */
void REGPARAM2 op_b180_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 3;
	CurrentInstrCycles = 6;  
	uae_s32 src = m68k_dreg(regs, srcreg);
	uae_s32 dst = m68k_dreg(regs, dstreg);
	src ^= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		m68k_dreg(regs, dstreg) = (src);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	do_cycles_ce000_internal(2);
	m68k_dreg(regs, dstreg) = (src);
	m68k_incpci(2);
	return;
}
/* 6 (1/0) */
/* 2 0,0   */

/* CMPM.L (An)+,(An)+ */
void REGPARAM2 op_b188_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 26;
	CurrentInstrCycles = 20; 
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_areg(regs, srcreg) += 2 + 0;
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) += 2 + 0;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) += 2 + 2;
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	m68k_areg(regs, srcreg) += 4;
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	if (dsta & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dsta, 2, 1);
		return;
	}
	uae_s32 dst = x_get_word(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	dst |= x_get_word(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return;
	}
	m68k_areg(regs, dstreg) += 4;
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	SET_NFLG(flgn != 0);
	if(!loop_mode) {
		regs.ir = regs.irc;
		opcode = regs.ir;
		get_word_ce000_prefetch(4);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return;
		}
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return;
}
/* 20 (5/0) */
/* 2 0,0   */

/* EOR.L Dn,(An) */
void REGPARAM2 op_b190_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 3;
	CurrentInstrCycles = 20; 
	int loop_mode = regs.loop_mode;
	uae_s32 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	if (dsta & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dsta, 2, 1);
		return;
	}
	uae_s32 dst = x_get_word(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	dst |= x_get_word(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return;
	}
	src ^= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_ce000_prefetch(4);
		if(hardware_bus_error) {
			int pcoffset = 0;
			ccr_68000_long_move_ae_LZN(src);
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return;
		}
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	if(loop_mode & 0xfffe) {
		do_cycles_ce000_internal(loop_mode & 0xfffe);
		loop_mode = 1;
	}
	x_put_word(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return;
	}
	x_put_word(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return;
}
/* 20 (3/2) */
/* 2 0,0   */

/* EOR.L Dn,(An)+ */
void REGPARAM2 op_b198_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 3;
	CurrentInstrCycles = 20; 
	int loop_mode = regs.loop_mode;
	uae_s32 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	if (dsta & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dsta, 2, 1);
		return;
	}
	uae_s32 dst = x_get_word(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	dst |= x_get_word(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return;
	}
	m68k_areg(regs, dstreg) += 4;
	src ^= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_ce000_prefetch(4);
		if(hardware_bus_error) {
			int pcoffset = 0;
			ccr_68000_long_move_ae_LZN(src);
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return;
		}
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	if(loop_mode & 0xfffe) {
		do_cycles_ce000_internal(loop_mode & 0xfffe);
		loop_mode = 1;
	}
	x_put_word(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return;
	}
	x_put_word(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return;
}
/* 20 (3/2) */
/* 2 0,0   */

/* EOR.L Dn,-(An) */
void REGPARAM2 op_b1a0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 3;
	CurrentInstrCycles = 22; 
	int loop_mode = regs.loop_mode;
	uae_s32 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - 4;
	do_cycles_ce000_internal(2);
	if (dsta & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dsta, 2, 1);
		return;
	}
	uae_s32 dst = x_get_word(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	dst |= x_get_word(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, dstreg) = dsta;
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return;
	}
	m68k_areg(regs, dstreg) = dsta;
	src ^= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_ce000_prefetch(4);
		if(hardware_bus_error) {
			int pcoffset = 0;
			ccr_68000_long_move_ae_LZN(src);
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return;
		}
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	if(loop_mode & 0xfffe) {
		do_cycles_ce000_internal(loop_mode & 0xfffe);
		loop_mode = 1;
	}
	x_put_word(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return;
	}
	x_put_word(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return;
}
/* 22 (3/2) */
/* 2 0,0   */

/* EOR.L Dn,(d16,An) */
void REGPARAM2 op_b1a8_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 3;
	CurrentInstrCycles = 24; 
	uae_s32 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dsta, 2, 1);
		return;
	}
	uae_s32 dst = x_get_word(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	dst |= x_get_word(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return;
	}
	src ^= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	x_put_word(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return;
	}
	x_put_word(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 24 (4/2) */
/* 4 0,0   */

/* EOR.L Dn,(d8,An,Xn) */
void REGPARAM2 op_b1b0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 3;
	CurrentInstrCycles = 26; 
	uae_s32 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	do_cycles_ce000_internal(2);
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dsta, 2, 1);
		return;
	}
	uae_s32 dst = x_get_word(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	dst |= x_get_word(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return;
	}
	src ^= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	x_put_word(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return;
	}
	x_put_word(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 26 (4/2) */
/* 4 4,0   */

/* EOR.L Dn,(xxx).W */
void REGPARAM2 op_b1b8_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	OpcodeFamily = 3;
	CurrentInstrCycles = 24; 
	uae_s32 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, dsta, 2, 1);
		return;
	}
	uae_s32 dst = x_get_word(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	dst |= x_get_word(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return;
	}
	src ^= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	x_put_word(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return;
	}
	x_put_word(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 24 (4/2) */
/* 4 0,0   */

/* EOR.L Dn,(xxx).L */
void REGPARAM2 op_b1b9_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	OpcodeFamily = 3;
	CurrentInstrCycles = 28; 
	uae_s32 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	dsta |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, dsta, 2, 1);
		return;
	}
	uae_s32 dst = x_get_word(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	dst |= x_get_word(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return;
	}
	src ^= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	x_put_word(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return;
	}
	x_put_word(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 28 (5/2) */
/* 6 0,0   */

/* CMPA.L Dn,An */
void REGPARAM2 op_b1c0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 27;
	CurrentInstrCycles = 6;  
	uae_s32 src = m68k_dreg(regs, srcreg);
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	SET_NFLG(flgn != 0);
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	do_cycles_ce000_internal(2);
	m68k_incpci(2);
	return;
}
/* 6 (1/0) */
/* 2 0,0   */

/* CMPA.L An,An */
void REGPARAM2 op_b1c8_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 27;
	CurrentInstrCycles = 6;  
	uae_s32 src = m68k_areg(regs, srcreg);
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	SET_NFLG(flgn != 0);
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	do_cycles_ce000_internal(2);
	m68k_incpci(2);
	return;
}
/* 6 (1/0) */
/* 2 0,0   */

/* CMPA.L (An),An */
void REGPARAM2 op_b1d0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 27;
	CurrentInstrCycles = 14; 
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	SET_NFLG(flgn != 0);
	ipl_fetch_next_pre();
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_ce000_prefetch(4);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return;
		}
		opcode = regs.ir;
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	do_cycles_ce000_internal(2);
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return;
}
/* 14 (3/0) */
/* 2 0,0   */

/* CMPA.L (An)+,An */
void REGPARAM2 op_b1d8_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 27;
	CurrentInstrCycles = 14; 
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	m68k_areg(regs, srcreg) += 4;
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	SET_NFLG(flgn != 0);
	ipl_fetch_next_pre();
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_ce000_prefetch(4);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return;
		}
		opcode = regs.ir;
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	do_cycles_ce000_internal(2);
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return;
}
/* 14 (3/0) */
/* 2 0,0   */

/* CMPA.L -(An),An */
void REGPARAM2 op_b1e0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 27;
	CurrentInstrCycles = 16; 
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - 4;
	do_cycles_ce000_internal(2);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	m68k_areg(regs, srcreg) = srca;
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	SET_NFLG(flgn != 0);
	ipl_fetch_next_pre();
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_ce000_prefetch(4);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return;
		}
		opcode = regs.ir;
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	do_cycles_ce000_internal(2);
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return;
}
/* 16 (3/0) */
/* 2 0,0   */

/* CMPA.L (d16,An),An */
void REGPARAM2 op_b1e8_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 27;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	SET_NFLG(flgn != 0);
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	do_cycles_ce000_internal(2);
	m68k_incpci(4);
	return;
}
/* 18 (4/0) */
/* 4 0,0   */

/* CMPA.L (d8,An,Xn),An */
void REGPARAM2 op_b1f0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 27;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	do_cycles_ce000_internal(2);
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	SET_NFLG(flgn != 0);
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	do_cycles_ce000_internal(2);
	m68k_incpci(4);
	return;
}
/* 20 (4/0) */
/* 4 4,0   */

/* CMPA.L (xxx).W,An */
void REGPARAM2 op_b1f8_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 27;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	if (srca & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	SET_NFLG(flgn != 0);
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	do_cycles_ce000_internal(2);
	m68k_incpci(4);
	return;
}
/* 18 (4/0) */
/* 4 0,0   */

/* CMPA.L (xxx).L,An */
void REGPARAM2 op_b1f9_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 27;
	CurrentInstrCycles = 22; 
	uaecptr srca;
	srca = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	srca |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	if (srca & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	SET_NFLG(flgn != 0);
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	opcode = regs.ir;
	do_cycles_ce000_internal(2);
	m68k_incpci(6);
	return;
}
/* 22 (5/0) */
/* 6 0,0   */

/* CMPA.L (d16,PC),An */
void REGPARAM2 op_b1fa_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 27;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	srca = m68k_getpci() + 2;
	srca += (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 2);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return;
	}
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 2);
		return;
	}
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	SET_NFLG(flgn != 0);
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	do_cycles_ce000_internal(2);
	m68k_incpci(4);
	return;
}
/* 18 (4/0) */
/* 4 0,0   */

/* CMPA.L (d8,PC,Xn),An */
void REGPARAM2 op_b1fb_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 27;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	uaecptr tmppc = m68k_getpci() + 2;
	do_cycles_ce000_internal(2);
	srca = get_disp_ea_000(tmppc, get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 2);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return;
	}
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 2);
		return;
	}
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	SET_NFLG(flgn != 0);
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	do_cycles_ce000_internal(2);
	m68k_incpci(4);
	return;
}
/* 20 (4/0) */
/* 4 4,0   */

/* CMPA.L #<data>.L,An */
void REGPARAM2 op_b1fc_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 27;
	CurrentInstrCycles = 14; 
	uae_s32 src;
	src = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	src |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	SET_NFLG(flgn != 0);
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	opcode = regs.ir;
	do_cycles_ce000_internal(2);
	m68k_incpci(6);
	return;
}
/* 14 (3/0) */
/* 6 0,0   */

/* AND.B Dn,Dn */
void REGPARAM2 op_c000_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 4;  
	uae_s8 src = m68k_dreg(regs, srcreg);
	uae_s8 dst = m68k_dreg(regs, dstreg);
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 4 (1/0) */
/* 2 0,0   */

/* AND.B (An),Dn */
void REGPARAM2 op_c010_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 8;  
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	uae_s8 dst = m68k_dreg(regs, dstreg);
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
	if(!loop_mode) {
		regs.ir = regs.irc;
		opcode = regs.ir;
		get_word_ce000_prefetch(4);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return;
		}
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	if (loop_mode) {
		do_cycles_ce000_internal(4);
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return;
}
/* 8 (2/0) */
/* 2 0,0   */

/* AND.B (An)+,Dn */
void REGPARAM2 op_c018_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 8;  
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
	uae_s8 dst = m68k_dreg(regs, dstreg);
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
	if(!loop_mode) {
		regs.ir = regs.irc;
		opcode = regs.ir;
		get_word_ce000_prefetch(4);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return;
		}
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	if (loop_mode) {
		do_cycles_ce000_internal(4);
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return;
}
/* 8 (2/0) */
/* 2 0,0   */

/* AND.B -(An),Dn */
void REGPARAM2 op_c020_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 10; 
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
	do_cycles_ce000_internal(2);
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	m68k_areg(regs, srcreg) = srca;
	uae_s8 dst = m68k_dreg(regs, dstreg);
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
	if(!loop_mode) {
		regs.ir = regs.irc;
		opcode = regs.ir;
		get_word_ce000_prefetch(4);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return;
		}
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	if (loop_mode) {
		do_cycles_ce000_internal(4);
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return;
}
/* 10 (2/0) */
/* 2 0,0   */

/* AND.B (d16,An),Dn */
void REGPARAM2 op_c028_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	uae_s8 dst = m68k_dreg(regs, dstreg);
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 12 (3/0) */
/* 4 0,0   */

/* AND.B (d8,An,Xn),Dn */
void REGPARAM2 op_c030_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	do_cycles_ce000_internal(2);
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	uae_s8 dst = m68k_dreg(regs, dstreg);
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 14 (3/0) */
/* 4 4,0   */

/* AND.B (xxx).W,Dn */
void REGPARAM2 op_c038_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	uae_s8 dst = m68k_dreg(regs, dstreg);
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 12 (3/0) */
/* 4 0,0   */

/* AND.B (xxx).L,Dn */
void REGPARAM2 op_c039_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	srca |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	uae_s8 dst = m68k_dreg(regs, dstreg);
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 16 (4/0) */
/* 6 0,0   */

/* AND.B (d16,PC),Dn */
void REGPARAM2 op_c03a_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_getpci() + 2;
	srca += (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 2);
		return;
	}
	uae_s8 dst = m68k_dreg(regs, dstreg);
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 12 (3/0) */
/* 4 0,0   */

/* AND.B (d8,PC,Xn),Dn */
void REGPARAM2 op_c03b_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	uaecptr tmppc = m68k_getpci() + 2;
	do_cycles_ce000_internal(2);
	srca = get_disp_ea_000(tmppc, get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 2);
		return;
	}
	uae_s8 dst = m68k_dreg(regs, dstreg);
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 14 (3/0) */
/* 4 4,0   */

/* AND.B #<data>.B,Dn */
void REGPARAM2 op_c03c_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 8;  
	uae_s8 src = (uae_u8)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uae_s8 dst = m68k_dreg(regs, dstreg);
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 8 (2/0) */
/* 4 0,0   */

/* AND.W Dn,Dn */
void REGPARAM2 op_c040_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 4;  
	uae_s16 src = m68k_dreg(regs, srcreg);
	uae_s16 dst = m68k_dreg(regs, dstreg);
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 4 (1/0) */
/* 2 0,0   */

/* AND.W (An),Dn */
void REGPARAM2 op_c050_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 8;  
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access2(opcode, srca, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
	if(!loop_mode) {
		regs.ir = regs.irc;
		opcode = regs.ir;
		get_word_ce000_prefetch(4);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return;
		}
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	if (loop_mode) {
		do_cycles_ce000_internal(4);
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return;
}
/* 8 (2/0) */
/* 2 0,0   */

/* AND.W (An)+,Dn */
void REGPARAM2 op_c058_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 8;  
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_areg(regs, srcreg) += 2 + 0;
		m68k_incpci(2);
		exception3_read_access2(opcode, srca, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) += 2 + 0;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	m68k_areg(regs, srcreg) += 2;
	uae_s16 dst = m68k_dreg(regs, dstreg);
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
	if(!loop_mode) {
		regs.ir = regs.irc;
		opcode = regs.ir;
		get_word_ce000_prefetch(4);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return;
		}
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	if (loop_mode) {
		do_cycles_ce000_internal(4);
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return;
}
/* 8 (2/0) */
/* 2 0,0   */

/* AND.W -(An),Dn */
void REGPARAM2 op_c060_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 10; 
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - 2;
	do_cycles_ce000_internal(2);
	if (srca & 1) {
		m68k_areg(regs, srcreg) = srca;
		m68k_incpci(2);
		exception3_read_access2(opcode, srca, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	m68k_areg(regs, srcreg) = srca;
	uae_s16 dst = m68k_dreg(regs, dstreg);
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
	if(!loop_mode) {
		regs.ir = regs.irc;
		opcode = regs.ir;
		get_word_ce000_prefetch(4);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return;
		}
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	if (loop_mode) {
		do_cycles_ce000_internal(4);
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return;
}
/* 10 (2/0) */
/* 2 0,0   */

/* AND.W (d16,An),Dn */
void REGPARAM2 op_c068_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 12 (3/0) */
/* 4 0,0   */

/* AND.W (d8,An,Xn),Dn */
void REGPARAM2 op_c070_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	do_cycles_ce000_internal(2);
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 14 (3/0) */
/* 4 4,0   */

/* AND.W (xxx).W,Dn */
void REGPARAM2 op_c078_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	if (srca & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 12 (3/0) */
/* 4 0,0   */

/* AND.W (xxx).L,Dn */
void REGPARAM2 op_c079_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	srca |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	if (srca & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 16 (4/0) */
/* 6 0,0   */

/* AND.W (d16,PC),Dn */
void REGPARAM2 op_c07a_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_getpci() + 2;
	srca += (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 2);
		return;
	}
	ipl_fetch_now();
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 12 (3/0) */
/* 4 0,0   */

/* AND.W (d8,PC,Xn),Dn */
void REGPARAM2 op_c07b_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	uaecptr tmppc = m68k_getpci() + 2;
	do_cycles_ce000_internal(2);
	srca = get_disp_ea_000(tmppc, get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 2);
		return;
	}
	ipl_fetch_now();
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 14 (3/0) */
/* 4 4,0   */

/* AND.W #<data>.W,Dn */
void REGPARAM2 op_c07c_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 8;  
	uae_s16 src = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 8 (2/0) */
/* 4 0,0   */

/* AND.L Dn,Dn */
void REGPARAM2 op_c080_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 6;  
	uae_s32 src = m68k_dreg(regs, srcreg);
	uae_s32 dst = m68k_dreg(regs, dstreg);
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		m68k_dreg(regs, dstreg) = (src);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	do_cycles_ce000_internal(2);
	m68k_dreg(regs, dstreg) = (src);
	m68k_incpci(2);
	return;
}
/* 6 (1/0) */
/* 2 0,0   */

/* AND.L (An),Dn */
void REGPARAM2 op_c090_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 14; 
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_ce000_prefetch(4);
		if(hardware_bus_error) {
			int pcoffset = 0;
			m68k_dreg(regs, dstreg) = (src);
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return;
		}
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	do_cycles_ce000_internal(2);
	if(loop_mode & 0xfffe) {
		do_cycles_ce000_internal(loop_mode & 0xfffe);
		loop_mode = 1;
	}
	m68k_dreg(regs, dstreg) = (src);
	if (loop_mode) {
		do_cycles_ce000_internal(4);
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return;
}
/* 14 (3/0) */
/* 2 0,0   */

/* AND.L (An)+,Dn */
void REGPARAM2 op_c098_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 14; 
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	m68k_areg(regs, srcreg) += 4;
	uae_s32 dst = m68k_dreg(regs, dstreg);
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_ce000_prefetch(4);
		if(hardware_bus_error) {
			int pcoffset = 0;
			m68k_dreg(regs, dstreg) = (src);
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return;
		}
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	do_cycles_ce000_internal(2);
	if(loop_mode & 0xfffe) {
		do_cycles_ce000_internal(loop_mode & 0xfffe);
		loop_mode = 1;
	}
	m68k_dreg(regs, dstreg) = (src);
	if (loop_mode) {
		do_cycles_ce000_internal(4);
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return;
}
/* 14 (3/0) */
/* 2 0,0   */

/* AND.L -(An),Dn */
void REGPARAM2 op_c0a0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 16; 
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - 4;
	do_cycles_ce000_internal(2);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	m68k_areg(regs, srcreg) = srca;
	uae_s32 dst = m68k_dreg(regs, dstreg);
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_ce000_prefetch(4);
		if(hardware_bus_error) {
			int pcoffset = 0;
			m68k_dreg(regs, dstreg) = (src);
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return;
		}
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	do_cycles_ce000_internal(2);
	if(loop_mode & 0xfffe) {
		do_cycles_ce000_internal(loop_mode & 0xfffe);
		loop_mode = 1;
	}
	m68k_dreg(regs, dstreg) = (src);
	if (loop_mode) {
		do_cycles_ce000_internal(4);
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return;
}
/* 16 (3/0) */
/* 2 0,0   */

/* AND.L (d16,An),Dn */
void REGPARAM2 op_c0a8_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		m68k_dreg(regs, dstreg) = (src);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	do_cycles_ce000_internal(2);
	m68k_dreg(regs, dstreg) = (src);
	m68k_incpci(4);
	return;
}
/* 18 (4/0) */
/* 4 0,0   */

/* AND.L (d8,An,Xn),Dn */
void REGPARAM2 op_c0b0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	do_cycles_ce000_internal(2);
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		m68k_dreg(regs, dstreg) = (src);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	do_cycles_ce000_internal(2);
	m68k_dreg(regs, dstreg) = (src);
	m68k_incpci(4);
	return;
}
/* 20 (4/0) */
/* 4 4,0   */

/* AND.L (xxx).W,Dn */
void REGPARAM2 op_c0b8_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	if (srca & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		m68k_dreg(regs, dstreg) = (src);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	do_cycles_ce000_internal(2);
	m68k_dreg(regs, dstreg) = (src);
	m68k_incpci(4);
	return;
}
/* 18 (4/0) */
/* 4 0,0   */

/* AND.L (xxx).L,Dn */
void REGPARAM2 op_c0b9_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 22; 
	uaecptr srca;
	srca = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	srca |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	if (srca & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		m68k_dreg(regs, dstreg) = (src);
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	do_cycles_ce000_internal(2);
	m68k_dreg(regs, dstreg) = (src);
	m68k_incpci(6);
	return;
}
/* 22 (5/0) */
/* 6 0,0   */

/* AND.L (d16,PC),Dn */
void REGPARAM2 op_c0ba_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	srca = m68k_getpci() + 2;
	srca += (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 2);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return;
	}
	ipl_fetch_now();
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 2);
		return;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		m68k_dreg(regs, dstreg) = (src);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	do_cycles_ce000_internal(2);
	m68k_dreg(regs, dstreg) = (src);
	m68k_incpci(4);
	return;
}
/* 18 (4/0) */
/* 4 0,0   */

/* AND.L (d8,PC,Xn),Dn */
void REGPARAM2 op_c0bb_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	uaecptr tmppc = m68k_getpci() + 2;
	do_cycles_ce000_internal(2);
	srca = get_disp_ea_000(tmppc, get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 2);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return;
	}
	ipl_fetch_now();
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 2);
		return;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		m68k_dreg(regs, dstreg) = (src);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	do_cycles_ce000_internal(2);
	m68k_dreg(regs, dstreg) = (src);
	m68k_incpci(4);
	return;
}
/* 20 (4/0) */
/* 4 4,0   */

/* AND.L #<data>.L,Dn */
void REGPARAM2 op_c0bc_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 16; 
	uae_s32 src;
	src = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	src |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		m68k_dreg(regs, dstreg) = (src);
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	do_cycles_ce000_internal(4);
	m68k_dreg(regs, dstreg) = (src);
	m68k_incpci(6);
	return;
}
/* 16 (3/0) */
/* 6 0,0   */

/* MULU.W Dn,Dn */
void REGPARAM2 op_c0c0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 62;
	CurrentInstrCycles = 4;  
	uae_s16 src = m68k_dreg(regs, srcreg);
	uae_s16 dst = m68k_dreg(regs, dstreg);
	regs.ir = regs.irc;
	ipl_fetch_next();
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();
		SET_ZFLG(1);
		pcoffset -= 2;
		m68k_dreg(regs, dstreg) &= 0xffff0000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	uae_u32 newv = (uae_u32)(uae_u16)dst * (uae_u32)(uae_u16)src;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_NFLG(((uae_s32)(newv)) < 0);
	int cycles = getMulu68kCycles(src);
	do_cycles_ce000_internal(cycles);
	m68k_dreg(regs, dstreg) = (newv);
	m68k_incpci(2);
	return;
}
/* 4+ (1/0) */
/* 2 0,0   */

/* MULU.W (An),Dn */
void REGPARAM2 op_c0d0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 62;
	CurrentInstrCycles = 8;  
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access2(opcode, srca, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();
		SET_ZFLG(1);
		pcoffset -= 2;
		m68k_dreg(regs, dstreg) &= 0xffff0000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	uae_u32 newv = (uae_u32)(uae_u16)dst * (uae_u32)(uae_u16)src;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_NFLG(((uae_s32)(newv)) < 0);
	int cycles = getMulu68kCycles(src);
	do_cycles_ce000_internal(cycles);
	m68k_dreg(regs, dstreg) = (newv);
	m68k_incpci(2);
	return;
}
/* 8+ (2/0) */
/* 2 0,0   */

/* MULU.W (An)+,Dn */
void REGPARAM2 op_c0d8_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 62;
	CurrentInstrCycles = 8;  
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_areg(regs, srcreg) += 2 + 0;
		m68k_incpci(2);
		exception3_read_access2(opcode, srca, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) += 2 + 0;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	m68k_areg(regs, srcreg) += 2;
	uae_s16 dst = m68k_dreg(regs, dstreg);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();
		SET_ZFLG(1);
		pcoffset -= 2;
		m68k_dreg(regs, dstreg) &= 0xffff0000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	uae_u32 newv = (uae_u32)(uae_u16)dst * (uae_u32)(uae_u16)src;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_NFLG(((uae_s32)(newv)) < 0);
	int cycles = getMulu68kCycles(src);
	do_cycles_ce000_internal(cycles);
	m68k_dreg(regs, dstreg) = (newv);
	m68k_incpci(2);
	return;
}
/* 8+ (2/0) */
/* 2 0,0   */

/* MULU.W -(An),Dn */
void REGPARAM2 op_c0e0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 62;
	CurrentInstrCycles = 10; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - 2;
	do_cycles_ce000_internal(2);
	if (srca & 1) {
		m68k_areg(regs, srcreg) = srca;
		m68k_incpci(2);
		exception3_read_access2(opcode, srca, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	m68k_areg(regs, srcreg) = srca;
	uae_s16 dst = m68k_dreg(regs, dstreg);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();
		SET_ZFLG(1);
		pcoffset -= 0;
		m68k_dreg(regs, dstreg) &= 0xffff0000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	uae_u32 newv = (uae_u32)(uae_u16)dst * (uae_u32)(uae_u16)src;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_NFLG(((uae_s32)(newv)) < 0);
	int cycles = getMulu68kCycles(src);
	do_cycles_ce000_internal(cycles);
	m68k_dreg(regs, dstreg) = (newv);
	m68k_incpci(2);
	return;
}
/* 10+ (2/0) */
/* 2 0,0   */

/* MULU.W (d16,An),Dn */
void REGPARAM2 op_c0e8_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 62;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();
		SET_ZFLG(1);
		pcoffset -= 4;
		m68k_dreg(regs, dstreg) &= 0xffff0000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	uae_u32 newv = (uae_u32)(uae_u16)dst * (uae_u32)(uae_u16)src;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_NFLG(((uae_s32)(newv)) < 0);
	int cycles = getMulu68kCycles(src);
	do_cycles_ce000_internal(cycles);
	m68k_dreg(regs, dstreg) = (newv);
	m68k_incpci(4);
	return;
}
/* 12+ (3/0) */
/* 4 0,0   */

/* MULU.W (d8,An,Xn),Dn */
void REGPARAM2 op_c0f0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 62;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	do_cycles_ce000_internal(2);
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();
		SET_ZFLG(1);
		pcoffset -= 4;
		m68k_dreg(regs, dstreg) &= 0xffff0000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	uae_u32 newv = (uae_u32)(uae_u16)dst * (uae_u32)(uae_u16)src;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_NFLG(((uae_s32)(newv)) < 0);
	int cycles = getMulu68kCycles(src);
	do_cycles_ce000_internal(cycles);
	m68k_dreg(regs, dstreg) = (newv);
	m68k_incpci(4);
	return;
}
/* 14+ (3/0) */
/* 4 4,0   */

/* MULU.W (xxx).W,Dn */
void REGPARAM2 op_c0f8_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 62;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	if (srca & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();
		SET_ZFLG(1);
		pcoffset -= 2;
		m68k_dreg(regs, dstreg) &= 0xffff0000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	uae_u32 newv = (uae_u32)(uae_u16)dst * (uae_u32)(uae_u16)src;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_NFLG(((uae_s32)(newv)) < 0);
	int cycles = getMulu68kCycles(src);
	do_cycles_ce000_internal(cycles);
	m68k_dreg(regs, dstreg) = (newv);
	m68k_incpci(4);
	return;
}
/* 12+ (3/0) */
/* 4 0,0   */

/* MULU.W (xxx).L,Dn */
void REGPARAM2 op_c0f9_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 62;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	srca |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	if (srca & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();
		SET_ZFLG(1);
		pcoffset -= 2;
		m68k_dreg(regs, dstreg) &= 0xffff0000;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	opcode = regs.ir;
	uae_u32 newv = (uae_u32)(uae_u16)dst * (uae_u32)(uae_u16)src;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_NFLG(((uae_s32)(newv)) < 0);
	int cycles = getMulu68kCycles(src);
	do_cycles_ce000_internal(cycles);
	m68k_dreg(regs, dstreg) = (newv);
	m68k_incpci(6);
	return;
}
/* 16+ (4/0) */
/* 6 0,0   */

/* MULU.W (d16,PC),Dn */
void REGPARAM2 op_c0fa_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 62;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_getpci() + 2;
	srca += (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 2);
		return;
	}
	ipl_fetch_now();
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();
		SET_ZFLG(1);
		pcoffset -= 4;
		m68k_dreg(regs, dstreg) &= 0xffff0000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	uae_u32 newv = (uae_u32)(uae_u16)dst * (uae_u32)(uae_u16)src;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_NFLG(((uae_s32)(newv)) < 0);
	int cycles = getMulu68kCycles(src);
	do_cycles_ce000_internal(cycles);
	m68k_dreg(regs, dstreg) = (newv);
	m68k_incpci(4);
	return;
}
/* 12+ (3/0) */
/* 4 0,0   */

/* MULU.W (d8,PC,Xn),Dn */
void REGPARAM2 op_c0fb_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 62;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	uaecptr tmppc = m68k_getpci() + 2;
	do_cycles_ce000_internal(2);
	srca = get_disp_ea_000(tmppc, get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 2);
		return;
	}
	ipl_fetch_now();
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();
		SET_ZFLG(1);
		pcoffset -= 4;
		m68k_dreg(regs, dstreg) &= 0xffff0000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	uae_u32 newv = (uae_u32)(uae_u16)dst * (uae_u32)(uae_u16)src;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_NFLG(((uae_s32)(newv)) < 0);
	int cycles = getMulu68kCycles(src);
	do_cycles_ce000_internal(cycles);
	m68k_dreg(regs, dstreg) = (newv);
	m68k_incpci(4);
	return;
}
/* 14+ (3/0) */
/* 4 4,0   */

/* MULU.W #<data>.W,Dn */
void REGPARAM2 op_c0fc_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 62;
	CurrentInstrCycles = 8;  
	uae_s16 src = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	regs.ir = regs.irc;
	ipl_fetch_next();
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();
		SET_ZFLG(1);
		pcoffset -= 2;
		m68k_dreg(regs, dstreg) &= 0xffff0000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	uae_u32 newv = (uae_u32)(uae_u16)dst * (uae_u32)(uae_u16)src;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_NFLG(((uae_s32)(newv)) < 0);
	int cycles = getMulu68kCycles(src);
	do_cycles_ce000_internal(cycles);
	m68k_dreg(regs, dstreg) = (newv);
	m68k_incpci(4);
	return;
}
/* 8+ (2/0) */
/* 4 0,0   */

/* ABCD.B Dn,Dn */
void REGPARAM2 op_c100_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 14;
	CurrentInstrCycles = 6;  
	uae_s8 src = m68k_dreg(regs, srcreg);
	uae_s8 dst = m68k_dreg(regs, dstreg);
	uae_u16 newv_lo = (src & 0xF) + (dst & 0xF) + (GET_XFLG() ? 1 : 0);
	uae_u16 newv_hi = (src & 0xF0) + (dst & 0xF0);
	uae_u16 newv, tmp_newv;
	int cflg;
	newv = tmp_newv = newv_hi + newv_lo;if (newv_lo > 9) { newv += 6; }
	cflg = (newv & 0x3F0) > 0x90;
	if (cflg) newv += 0x60;
	SET_CFLG(cflg);
	COPY_CARRY();
	SET_ZFLG(GET_ZFLG() & (((uae_s8)(newv)) == 0));
	SET_NFLG(((uae_s8)(newv)) < 0);
	SET_VFLG((tmp_newv & 0x80) == 0 && (newv & 0x80) != 0);
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	do_cycles_ce000_internal(2);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
	m68k_incpci(2);
	return;
}
/* 6 (1/0) */
/* 2 0,0   */

/* ABCD.B -(An),-(An) */
void REGPARAM2 op_c108_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 14;
	CurrentInstrCycles = 18; 
	int loop_mode = regs.loop_mode;
	do_cycles_ce000_internal(2);
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	m68k_areg(regs, srcreg) = srca;
	ipl_fetch_next_pre();
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, dstreg) = dsta;
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	m68k_areg(regs, dstreg) = dsta;
	uae_u16 newv_lo = (src & 0xF) + (dst & 0xF) + (GET_XFLG() ? 1 : 0);
	uae_u16 newv_hi = (src & 0xF0) + (dst & 0xF0);
	uae_u16 newv, tmp_newv;
	int cflg;
	newv = tmp_newv = newv_hi + newv_lo;if (newv_lo > 9) { newv += 6; }
	cflg = (newv & 0x3F0) > 0x90;
	if (cflg) newv += 0x60;
	SET_CFLG(cflg);
	COPY_CARRY();
	SET_ZFLG(GET_ZFLG() & (((uae_s8)(newv)) == 0));
	SET_NFLG(((uae_s8)(newv)) < 0);
	SET_VFLG((tmp_newv & 0x80) == 0 && (newv & 0x80) != 0);
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_ce000_prefetch(4);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return;
		}
		opcode = regs.ir;
	} else {
		loop_mode = 0;
		loop_mode |= 6;
		loop_mode |= 6 << 16;
	}
	if(loop_mode & 0xfffe) {
		do_cycles_ce000_internal(loop_mode & 0xfffe);
		loop_mode = 1;
	}
	x_put_byte(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x0, newv, 1);
		return;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return;
}
/* 18 (3/1) */
/* 2 0,0   */

/* AND.B Dn,(An) */
void REGPARAM2 op_c110_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 12; 
	int loop_mode = regs.loop_mode;
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_ce000_prefetch(4);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return;
		}
		opcode = regs.ir;
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	if(loop_mode & 0xfffe) {
		do_cycles_ce000_internal(loop_mode & 0xfffe);
		loop_mode = 1;
	}
	x_put_byte(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return;
}
/* 12 (2/1) */
/* 2 0,0   */

/* AND.B Dn,(An)+ */
void REGPARAM2 op_c118_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 12; 
	int loop_mode = regs.loop_mode;
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_ce000_prefetch(4);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return;
		}
		opcode = regs.ir;
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	if(loop_mode & 0xfffe) {
		do_cycles_ce000_internal(loop_mode & 0xfffe);
		loop_mode = 1;
	}
	x_put_byte(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return;
}
/* 12 (2/1) */
/* 2 0,0   */

/* AND.B Dn,-(An) */
void REGPARAM2 op_c120_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 14; 
	int loop_mode = regs.loop_mode;
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
	do_cycles_ce000_internal(2);
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, dstreg) = dsta;
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	m68k_areg(regs, dstreg) = dsta;
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_ce000_prefetch(4);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return;
		}
		opcode = regs.ir;
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	if(loop_mode & 0xfffe) {
		do_cycles_ce000_internal(loop_mode & 0xfffe);
		loop_mode = 1;
	}
	x_put_byte(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return;
}
/* 14 (2/1) */
/* 2 0,0   */

/* AND.B Dn,(d16,An) */
void REGPARAM2 op_c128_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 16; 
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_byte(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* AND.B Dn,(d8,An,Xn) */
void REGPARAM2 op_c130_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 18; 
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	do_cycles_ce000_internal(2);
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_byte(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 18 (3/1) */
/* 4 4,0   */

/* AND.B Dn,(xxx).W */
void REGPARAM2 op_c138_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	OpcodeFamily = 2;
	CurrentInstrCycles = 16; 
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_byte(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* AND.B Dn,(xxx).L */
void REGPARAM2 op_c139_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	OpcodeFamily = 2;
	CurrentInstrCycles = 20; 
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	dsta |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_byte(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 20 (4/1) */
/* 6 0,0   */

/* EXG.L Dn,Dn */
void REGPARAM2 op_c140_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 35;
	CurrentInstrCycles = 6;  
	uae_s32 src = m68k_dreg(regs, srcreg);
	uae_s32 dst = m68k_dreg(regs, dstreg);
	m68k_dreg(regs, srcreg) = (dst);
	m68k_dreg(regs, dstreg) = (src);
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	do_cycles_ce000_internal(2);
	m68k_incpci(2);
	return;
}
/* 6 (1/0) */
/* 2 0,0   */

/* EXG.L An,An */
void REGPARAM2 op_c148_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 35;
	CurrentInstrCycles = 6;  
	uae_s32 src = m68k_areg(regs, srcreg);
	uae_s32 dst = m68k_areg(regs, dstreg);
	m68k_areg(regs, srcreg) = (dst);
	m68k_areg(regs, dstreg) = (src);
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	do_cycles_ce000_internal(2);
	m68k_incpci(2);
	return;
}
/* 6 (1/0) */
/* 2 0,0   */

/* AND.W Dn,(An) */
void REGPARAM2 op_c150_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 12; 
	int loop_mode = regs.loop_mode;
	uae_s16 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	if (dsta & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dsta, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 dst = x_get_word(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_ce000_prefetch(4);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return;
		}
		opcode = regs.ir;
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	if(loop_mode & 0xfffe) {
		do_cycles_ce000_internal(loop_mode & 0xfffe);
		loop_mode = 1;
	}
	x_put_word(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return;
}
/* 12 (2/1) */
/* 2 0,0   */

/* AND.W Dn,(An)+ */
void REGPARAM2 op_c158_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 12; 
	int loop_mode = regs.loop_mode;
	uae_s16 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	if (dsta & 1) {
		m68k_areg(regs, dstreg) += 2 + 0;
		m68k_incpci(2);
		exception3_read_access(opcode, dsta, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 dst = x_get_word(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, dstreg) += 2 + 0;
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	m68k_areg(regs, dstreg) += 2;
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_ce000_prefetch(4);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return;
		}
		opcode = regs.ir;
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	if(loop_mode & 0xfffe) {
		do_cycles_ce000_internal(loop_mode & 0xfffe);
		loop_mode = 1;
	}
	x_put_word(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return;
}
/* 12 (2/1) */
/* 2 0,0   */

/* AND.W Dn,-(An) */
void REGPARAM2 op_c160_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 14; 
	int loop_mode = regs.loop_mode;
	uae_s16 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - 2;
	do_cycles_ce000_internal(2);
	if (dsta & 1) {
		m68k_areg(regs, dstreg) = dsta;
		m68k_incpci(2);
		exception3_read_access(opcode, dsta, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 dst = x_get_word(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, dstreg) = dsta;
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	m68k_areg(regs, dstreg) = dsta;
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_ce000_prefetch(4);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return;
		}
		opcode = regs.ir;
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	if(loop_mode & 0xfffe) {
		do_cycles_ce000_internal(loop_mode & 0xfffe);
		loop_mode = 1;
	}
	x_put_word(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return;
}
/* 14 (2/1) */
/* 2 0,0   */

/* AND.W Dn,(d16,An) */
void REGPARAM2 op_c168_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 16; 
	uae_s16 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dsta, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 dst = x_get_word(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_word(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* AND.W Dn,(d8,An,Xn) */
void REGPARAM2 op_c170_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 18; 
	uae_s16 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	do_cycles_ce000_internal(2);
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dsta, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 dst = x_get_word(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_word(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 18 (3/1) */
/* 4 4,0   */

/* AND.W Dn,(xxx).W */
void REGPARAM2 op_c178_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	OpcodeFamily = 2;
	CurrentInstrCycles = 16; 
	uae_s16 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, dsta, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 dst = x_get_word(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_word(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* AND.W Dn,(xxx).L */
void REGPARAM2 op_c179_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	OpcodeFamily = 2;
	CurrentInstrCycles = 20; 
	uae_s16 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	dsta |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, dsta, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 dst = x_get_word(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_word(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 20 (4/1) */
/* 6 0,0   */

/* EXG.L Dn,An */
void REGPARAM2 op_c188_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 35;
	CurrentInstrCycles = 6;  
	uae_s32 src = m68k_dreg(regs, srcreg);
	uae_s32 dst = m68k_areg(regs, dstreg);
	m68k_dreg(regs, srcreg) = (dst);
	m68k_areg(regs, dstreg) = (src);
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	do_cycles_ce000_internal(2);
	m68k_incpci(2);
	return;
}
/* 6 (1/0) */
/* 2 0,0   */

/* AND.L Dn,(An) */
void REGPARAM2 op_c190_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 20; 
	int loop_mode = regs.loop_mode;
	uae_s32 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	if (dsta & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dsta, 2, 1);
		return;
	}
	uae_s32 dst = x_get_word(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	dst |= x_get_word(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return;
	}
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_ce000_prefetch(4);
		if(hardware_bus_error) {
			int pcoffset = 0;
			ccr_68000_long_move_ae_LZN(src);
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return;
		}
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	if(loop_mode & 0xfffe) {
		do_cycles_ce000_internal(loop_mode & 0xfffe);
		loop_mode = 1;
	}
	x_put_word(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return;
	}
	x_put_word(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return;
}
/* 20 (3/2) */
/* 2 0,0   */

/* AND.L Dn,(An)+ */
void REGPARAM2 op_c198_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 20; 
	int loop_mode = regs.loop_mode;
	uae_s32 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	if (dsta & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dsta, 2, 1);
		return;
	}
	uae_s32 dst = x_get_word(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	dst |= x_get_word(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return;
	}
	m68k_areg(regs, dstreg) += 4;
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_ce000_prefetch(4);
		if(hardware_bus_error) {
			int pcoffset = 0;
			ccr_68000_long_move_ae_LZN(src);
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return;
		}
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	if(loop_mode & 0xfffe) {
		do_cycles_ce000_internal(loop_mode & 0xfffe);
		loop_mode = 1;
	}
	x_put_word(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return;
	}
	x_put_word(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return;
}
/* 20 (3/2) */
/* 2 0,0   */

/* AND.L Dn,-(An) */
void REGPARAM2 op_c1a0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 22; 
	int loop_mode = regs.loop_mode;
	uae_s32 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - 4;
	do_cycles_ce000_internal(2);
	if (dsta & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dsta, 2, 1);
		return;
	}
	uae_s32 dst = x_get_word(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	dst |= x_get_word(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, dstreg) = dsta;
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return;
	}
	m68k_areg(regs, dstreg) = dsta;
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_ce000_prefetch(4);
		if(hardware_bus_error) {
			int pcoffset = 0;
			ccr_68000_long_move_ae_LZN(src);
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return;
		}
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	if(loop_mode & 0xfffe) {
		do_cycles_ce000_internal(loop_mode & 0xfffe);
		loop_mode = 1;
	}
	x_put_word(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return;
	}
	x_put_word(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return;
}
/* 22 (3/2) */
/* 2 0,0   */

/* AND.L Dn,(d16,An) */
void REGPARAM2 op_c1a8_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 24; 
	uae_s32 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dsta, 2, 1);
		return;
	}
	uae_s32 dst = x_get_word(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	dst |= x_get_word(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return;
	}
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	x_put_word(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return;
	}
	x_put_word(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 24 (4/2) */
/* 4 0,0   */

/* AND.L Dn,(d8,An,Xn) */
void REGPARAM2 op_c1b0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 26; 
	uae_s32 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	do_cycles_ce000_internal(2);
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dsta, 2, 1);
		return;
	}
	uae_s32 dst = x_get_word(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	dst |= x_get_word(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return;
	}
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	x_put_word(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return;
	}
	x_put_word(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 26 (4/2) */
/* 4 4,0   */

/* AND.L Dn,(xxx).W */
void REGPARAM2 op_c1b8_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	OpcodeFamily = 2;
	CurrentInstrCycles = 24; 
	uae_s32 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, dsta, 2, 1);
		return;
	}
	uae_s32 dst = x_get_word(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	dst |= x_get_word(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return;
	}
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	x_put_word(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return;
	}
	x_put_word(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 24 (4/2) */
/* 4 0,0   */

/* AND.L Dn,(xxx).L */
void REGPARAM2 op_c1b9_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	OpcodeFamily = 2;
	CurrentInstrCycles = 28; 
	uae_s32 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	dsta |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, dsta, 2, 1);
		return;
	}
	uae_s32 dst = x_get_word(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	dst |= x_get_word(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return;
	}
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	x_put_word(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return;
	}
	x_put_word(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 28 (5/2) */
/* 6 0,0   */

/* MULS.W Dn,Dn */
void REGPARAM2 op_c1c0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 63;
	CurrentInstrCycles = 4;  
	uae_s16 src = m68k_dreg(regs, srcreg);
	uae_s16 dst = m68k_dreg(regs, dstreg);
	regs.ir = regs.irc;
	ipl_fetch_next();
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();
		SET_ZFLG(1);
		pcoffset -= 2;
		m68k_dreg(regs, dstreg) &= 0xffff0000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	uae_u32 newv = (uae_s32)(uae_s16)dst * (uae_s32)(uae_s16)src;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_NFLG(((uae_s32)(newv)) < 0);
	int cycles = getMuls68kCycles(src);
	do_cycles_ce000_internal(cycles);
	m68k_dreg(regs, dstreg) = (newv);
	m68k_incpci(2);
	return;
}
/* 4+ (1/0) */
/* 2 0,0   */

/* MULS.W (An),Dn */
void REGPARAM2 op_c1d0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 63;
	CurrentInstrCycles = 8;  
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access2(opcode, srca, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();
		SET_ZFLG(1);
		pcoffset -= 2;
		m68k_dreg(regs, dstreg) &= 0xffff0000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	uae_u32 newv = (uae_s32)(uae_s16)dst * (uae_s32)(uae_s16)src;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_NFLG(((uae_s32)(newv)) < 0);
	int cycles = getMuls68kCycles(src);
	do_cycles_ce000_internal(cycles);
	m68k_dreg(regs, dstreg) = (newv);
	m68k_incpci(2);
	return;
}
/* 8+ (2/0) */
/* 2 0,0   */

/* MULS.W (An)+,Dn */
void REGPARAM2 op_c1d8_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 63;
	CurrentInstrCycles = 8;  
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_areg(regs, srcreg) += 2 + 0;
		m68k_incpci(2);
		exception3_read_access2(opcode, srca, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) += 2 + 0;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	m68k_areg(regs, srcreg) += 2;
	uae_s16 dst = m68k_dreg(regs, dstreg);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();
		SET_ZFLG(1);
		pcoffset -= 2;
		m68k_dreg(regs, dstreg) &= 0xffff0000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	uae_u32 newv = (uae_s32)(uae_s16)dst * (uae_s32)(uae_s16)src;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_NFLG(((uae_s32)(newv)) < 0);
	int cycles = getMuls68kCycles(src);
	do_cycles_ce000_internal(cycles);
	m68k_dreg(regs, dstreg) = (newv);
	m68k_incpci(2);
	return;
}
/* 8+ (2/0) */
/* 2 0,0   */

/* MULS.W -(An),Dn */
void REGPARAM2 op_c1e0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 63;
	CurrentInstrCycles = 10; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - 2;
	do_cycles_ce000_internal(2);
	if (srca & 1) {
		m68k_areg(regs, srcreg) = srca;
		m68k_incpci(2);
		exception3_read_access2(opcode, srca, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	m68k_areg(regs, srcreg) = srca;
	uae_s16 dst = m68k_dreg(regs, dstreg);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();
		SET_ZFLG(1);
		pcoffset -= 0;
		m68k_dreg(regs, dstreg) &= 0xffff0000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	uae_u32 newv = (uae_s32)(uae_s16)dst * (uae_s32)(uae_s16)src;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_NFLG(((uae_s32)(newv)) < 0);
	int cycles = getMuls68kCycles(src);
	do_cycles_ce000_internal(cycles);
	m68k_dreg(regs, dstreg) = (newv);
	m68k_incpci(2);
	return;
}
/* 10+ (2/0) */
/* 2 0,0   */

/* MULS.W (d16,An),Dn */
void REGPARAM2 op_c1e8_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 63;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();
		SET_ZFLG(1);
		pcoffset -= 4;
		m68k_dreg(regs, dstreg) &= 0xffff0000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	uae_u32 newv = (uae_s32)(uae_s16)dst * (uae_s32)(uae_s16)src;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_NFLG(((uae_s32)(newv)) < 0);
	int cycles = getMuls68kCycles(src);
	do_cycles_ce000_internal(cycles);
	m68k_dreg(regs, dstreg) = (newv);
	m68k_incpci(4);
	return;
}
/* 12+ (3/0) */
/* 4 0,0   */

/* MULS.W (d8,An,Xn),Dn */
void REGPARAM2 op_c1f0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 63;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	do_cycles_ce000_internal(2);
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();
		SET_ZFLG(1);
		pcoffset -= 4;
		m68k_dreg(regs, dstreg) &= 0xffff0000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	uae_u32 newv = (uae_s32)(uae_s16)dst * (uae_s32)(uae_s16)src;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_NFLG(((uae_s32)(newv)) < 0);
	int cycles = getMuls68kCycles(src);
	do_cycles_ce000_internal(cycles);
	m68k_dreg(regs, dstreg) = (newv);
	m68k_incpci(4);
	return;
}
/* 14+ (3/0) */
/* 4 4,0   */

/* MULS.W (xxx).W,Dn */
void REGPARAM2 op_c1f8_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 63;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	if (srca & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();
		SET_ZFLG(1);
		pcoffset -= 2;
		m68k_dreg(regs, dstreg) &= 0xffff0000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	uae_u32 newv = (uae_s32)(uae_s16)dst * (uae_s32)(uae_s16)src;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_NFLG(((uae_s32)(newv)) < 0);
	int cycles = getMuls68kCycles(src);
	do_cycles_ce000_internal(cycles);
	m68k_dreg(regs, dstreg) = (newv);
	m68k_incpci(4);
	return;
}
/* 12+ (3/0) */
/* 4 0,0   */

/* MULS.W (xxx).L,Dn */
void REGPARAM2 op_c1f9_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 63;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	srca |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	if (srca & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();
		SET_ZFLG(1);
		pcoffset -= 2;
		m68k_dreg(regs, dstreg) &= 0xffff0000;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	opcode = regs.ir;
	uae_u32 newv = (uae_s32)(uae_s16)dst * (uae_s32)(uae_s16)src;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_NFLG(((uae_s32)(newv)) < 0);
	int cycles = getMuls68kCycles(src);
	do_cycles_ce000_internal(cycles);
	m68k_dreg(regs, dstreg) = (newv);
	m68k_incpci(6);
	return;
}
/* 16+ (4/0) */
/* 6 0,0   */

/* MULS.W (d16,PC),Dn */
void REGPARAM2 op_c1fa_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 63;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_getpci() + 2;
	srca += (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 2);
		return;
	}
	ipl_fetch_now();
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();
		SET_ZFLG(1);
		pcoffset -= 4;
		m68k_dreg(regs, dstreg) &= 0xffff0000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	uae_u32 newv = (uae_s32)(uae_s16)dst * (uae_s32)(uae_s16)src;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_NFLG(((uae_s32)(newv)) < 0);
	int cycles = getMuls68kCycles(src);
	do_cycles_ce000_internal(cycles);
	m68k_dreg(regs, dstreg) = (newv);
	m68k_incpci(4);
	return;
}
/* 12+ (3/0) */
/* 4 0,0   */

/* MULS.W (d8,PC,Xn),Dn */
void REGPARAM2 op_c1fb_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 63;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	uaecptr tmppc = m68k_getpci() + 2;
	do_cycles_ce000_internal(2);
	srca = get_disp_ea_000(tmppc, get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 2);
		return;
	}
	ipl_fetch_now();
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();
		SET_ZFLG(1);
		pcoffset -= 4;
		m68k_dreg(regs, dstreg) &= 0xffff0000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	uae_u32 newv = (uae_s32)(uae_s16)dst * (uae_s32)(uae_s16)src;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_NFLG(((uae_s32)(newv)) < 0);
	int cycles = getMuls68kCycles(src);
	do_cycles_ce000_internal(cycles);
	m68k_dreg(regs, dstreg) = (newv);
	m68k_incpci(4);
	return;
}
/* 14+ (3/0) */
/* 4 4,0   */

/* MULS.W #<data>.W,Dn */
void REGPARAM2 op_c1fc_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 63;
	CurrentInstrCycles = 8;  
	uae_s16 src = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	regs.ir = regs.irc;
	ipl_fetch_next();
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();
		SET_ZFLG(1);
		pcoffset -= 2;
		m68k_dreg(regs, dstreg) &= 0xffff0000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	uae_u32 newv = (uae_s32)(uae_s16)dst * (uae_s32)(uae_s16)src;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_NFLG(((uae_s32)(newv)) < 0);
	int cycles = getMuls68kCycles(src);
	do_cycles_ce000_internal(cycles);
	m68k_dreg(regs, dstreg) = (newv);
	m68k_incpci(4);
	return;
}
/* 8+ (2/0) */
/* 4 0,0   */

/* ADD.B Dn,Dn */
void REGPARAM2 op_d000_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 4;  
	uae_s8 src = m68k_dreg(regs, srcreg);
	uae_s8 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u8)(~dst)) < ((uae_u8)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 4 (1/0) */
/* 2 0,0   */

/* ADD.B (An),Dn */
void REGPARAM2 op_d010_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 8;  
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	uae_s8 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u8)(~dst)) < ((uae_u8)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
	if(!loop_mode) {
		regs.ir = regs.irc;
		opcode = regs.ir;
		get_word_ce000_prefetch(4);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return;
		}
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	if (loop_mode) {
		do_cycles_ce000_internal(4);
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return;
}
/* 8 (2/0) */
/* 2 0,0   */

/* ADD.B (An)+,Dn */
void REGPARAM2 op_d018_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 8;  
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
	uae_s8 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u8)(~dst)) < ((uae_u8)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
	if(!loop_mode) {
		regs.ir = regs.irc;
		opcode = regs.ir;
		get_word_ce000_prefetch(4);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return;
		}
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	if (loop_mode) {
		do_cycles_ce000_internal(4);
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return;
}
/* 8 (2/0) */
/* 2 0,0   */

/* ADD.B -(An),Dn */
void REGPARAM2 op_d020_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 10; 
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
	do_cycles_ce000_internal(2);
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	m68k_areg(regs, srcreg) = srca;
	uae_s8 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u8)(~dst)) < ((uae_u8)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
	if(!loop_mode) {
		regs.ir = regs.irc;
		opcode = regs.ir;
		get_word_ce000_prefetch(4);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return;
		}
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	if (loop_mode) {
		do_cycles_ce000_internal(4);
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return;
}
/* 10 (2/0) */
/* 2 0,0   */

/* ADD.B (d16,An),Dn */
void REGPARAM2 op_d028_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	uae_s8 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u8)(~dst)) < ((uae_u8)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 12 (3/0) */
/* 4 0,0   */

/* ADD.B (d8,An,Xn),Dn */
void REGPARAM2 op_d030_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	do_cycles_ce000_internal(2);
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	uae_s8 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u8)(~dst)) < ((uae_u8)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 14 (3/0) */
/* 4 4,0   */

/* ADD.B (xxx).W,Dn */
void REGPARAM2 op_d038_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	uae_s8 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u8)(~dst)) < ((uae_u8)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 12 (3/0) */
/* 4 0,0   */

/* ADD.B (xxx).L,Dn */
void REGPARAM2 op_d039_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	srca |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	uae_s8 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u8)(~dst)) < ((uae_u8)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 16 (4/0) */
/* 6 0,0   */

/* ADD.B (d16,PC),Dn */
void REGPARAM2 op_d03a_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_getpci() + 2;
	srca += (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 2);
		return;
	}
	uae_s8 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u8)(~dst)) < ((uae_u8)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 12 (3/0) */
/* 4 0,0   */

/* ADD.B (d8,PC,Xn),Dn */
void REGPARAM2 op_d03b_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	uaecptr tmppc = m68k_getpci() + 2;
	do_cycles_ce000_internal(2);
	srca = get_disp_ea_000(tmppc, get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 2);
		return;
	}
	uae_s8 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u8)(~dst)) < ((uae_u8)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 14 (3/0) */
/* 4 4,0   */

/* ADD.B #<data>.B,Dn */
void REGPARAM2 op_d03c_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 8;  
	uae_s8 src = (uae_u8)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uae_s8 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u8)(~dst)) < ((uae_u8)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 8 (2/0) */
/* 4 0,0   */

/* ADD.W Dn,Dn */
void REGPARAM2 op_d040_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 4;  
	uae_s16 src = m68k_dreg(regs, srcreg);
	uae_s16 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 4 (1/0) */
/* 2 0,0   */

/* ADD.W An,Dn */
void REGPARAM2 op_d048_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 4;  
	uae_s16 src = m68k_areg(regs, srcreg);
	uae_s16 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 4 (1/0) */
/* 2 0,0   */

/* ADD.W (An),Dn */
void REGPARAM2 op_d050_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 8;  
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access2(opcode, srca, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
	if(!loop_mode) {
		regs.ir = regs.irc;
		opcode = regs.ir;
		get_word_ce000_prefetch(4);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return;
		}
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	if (loop_mode) {
		do_cycles_ce000_internal(4);
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return;
}
/* 8 (2/0) */
/* 2 0,0   */

/* ADD.W (An)+,Dn */
void REGPARAM2 op_d058_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 8;  
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_areg(regs, srcreg) += 2 + 0;
		m68k_incpci(2);
		exception3_read_access2(opcode, srca, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) += 2 + 0;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	m68k_areg(regs, srcreg) += 2;
	uae_s16 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
	if(!loop_mode) {
		regs.ir = regs.irc;
		opcode = regs.ir;
		get_word_ce000_prefetch(4);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return;
		}
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	if (loop_mode) {
		do_cycles_ce000_internal(4);
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return;
}
/* 8 (2/0) */
/* 2 0,0   */

/* ADD.W -(An),Dn */
void REGPARAM2 op_d060_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 10; 
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - 2;
	do_cycles_ce000_internal(2);
	if (srca & 1) {
		m68k_areg(regs, srcreg) = srca;
		m68k_incpci(2);
		exception3_read_access2(opcode, srca, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	m68k_areg(regs, srcreg) = srca;
	uae_s16 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
	if(!loop_mode) {
		regs.ir = regs.irc;
		opcode = regs.ir;
		get_word_ce000_prefetch(4);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return;
		}
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	if (loop_mode) {
		do_cycles_ce000_internal(4);
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return;
}
/* 10 (2/0) */
/* 2 0,0   */

/* ADD.W (d16,An),Dn */
void REGPARAM2 op_d068_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 12 (3/0) */
/* 4 0,0   */

/* ADD.W (d8,An,Xn),Dn */
void REGPARAM2 op_d070_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	do_cycles_ce000_internal(2);
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 14 (3/0) */
/* 4 4,0   */

/* ADD.W (xxx).W,Dn */
void REGPARAM2 op_d078_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	if (srca & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 12 (3/0) */
/* 4 0,0   */

/* ADD.W (xxx).L,Dn */
void REGPARAM2 op_d079_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	srca |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	if (srca & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 16 (4/0) */
/* 6 0,0   */

/* ADD.W (d16,PC),Dn */
void REGPARAM2 op_d07a_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_getpci() + 2;
	srca += (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 2);
		return;
	}
	ipl_fetch_now();
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 12 (3/0) */
/* 4 0,0   */

/* ADD.W (d8,PC,Xn),Dn */
void REGPARAM2 op_d07b_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	uaecptr tmppc = m68k_getpci() + 2;
	do_cycles_ce000_internal(2);
	srca = get_disp_ea_000(tmppc, get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 2);
		return;
	}
	ipl_fetch_now();
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 14 (3/0) */
/* 4 4,0   */

/* ADD.W #<data>.W,Dn */
void REGPARAM2 op_d07c_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 8;  
	uae_s16 src = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 8 (2/0) */
/* 4 0,0   */

/* ADD.L Dn,Dn */
void REGPARAM2 op_d080_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 6;  
	uae_s32 src = m68k_dreg(regs, srcreg);
	uae_s32 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u32)(~dst)) < ((uae_u32)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		uae_s16 bnewv = (uae_s16)dst + (uae_s16)src;
		int bflgs = ((uae_s16)(src)) < 0;
		int bflgo = ((uae_s16)(dst)) < 0;
		int bflgn = bnewv < 0;
		ccr_68000_long_move_ae_LZN(bnewv);
		SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
		SET_XFLG(GET_CFLG());
		SET_VFLG((bflgs ^ bflgn) & (bflgo ^ bflgn));
		dreg_68000_long_replace_low(dstreg, bnewv);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	do_cycles_ce000_internal(2);
	m68k_dreg(regs, dstreg) = (newv);
	m68k_incpci(2);
	return;
}
/* 6 (1/0) */
/* 2 0,0   */

/* ADD.L An,Dn */
void REGPARAM2 op_d088_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 6;  
	uae_s32 src = m68k_areg(regs, srcreg);
	uae_s32 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u32)(~dst)) < ((uae_u32)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		uae_s16 bnewv = (uae_s16)dst + (uae_s16)src;
		int bflgs = ((uae_s16)(src)) < 0;
		int bflgo = ((uae_s16)(dst)) < 0;
		int bflgn = bnewv < 0;
		ccr_68000_long_move_ae_LZN(bnewv);
		SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
		SET_XFLG(GET_CFLG());
		SET_VFLG((bflgs ^ bflgn) & (bflgo ^ bflgn));
		dreg_68000_long_replace_low(dstreg, bnewv);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	do_cycles_ce000_internal(2);
	m68k_dreg(regs, dstreg) = (newv);
	m68k_incpci(2);
	return;
}
/* 6 (1/0) */
/* 2 0,0   */

/* ADD.L (An),Dn */
void REGPARAM2 op_d090_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 14; 
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u32)(~dst)) < ((uae_u32)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_ce000_prefetch(4);
		if(hardware_bus_error) {
			int pcoffset = 0;
			dreg_68000_long_replace_low(dstreg, newv);
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return;
		}
		opcode = regs.ir;
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	do_cycles_ce000_internal(2);
	if(loop_mode & 0xfffe) {
		do_cycles_ce000_internal(loop_mode & 0xfffe);
		loop_mode = 1;
	}
	m68k_dreg(regs, dstreg) = (newv);
	if (loop_mode) {
		do_cycles_ce000_internal(4);
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return;
}
/* 14 (3/0) */
/* 2 0,0   */

/* ADD.L (An)+,Dn */
void REGPARAM2 op_d098_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 14; 
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	m68k_areg(regs, srcreg) += 4;
	uae_s32 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u32)(~dst)) < ((uae_u32)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_ce000_prefetch(4);
		if(hardware_bus_error) {
			int pcoffset = 0;
			dreg_68000_long_replace_low(dstreg, newv);
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return;
		}
		opcode = regs.ir;
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	do_cycles_ce000_internal(2);
	if(loop_mode & 0xfffe) {
		do_cycles_ce000_internal(loop_mode & 0xfffe);
		loop_mode = 1;
	}
	m68k_dreg(regs, dstreg) = (newv);
	if (loop_mode) {
		do_cycles_ce000_internal(4);
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return;
}
/* 14 (3/0) */
/* 2 0,0   */

/* ADD.L -(An),Dn */
void REGPARAM2 op_d0a0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 16; 
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - 4;
	do_cycles_ce000_internal(2);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	m68k_areg(regs, srcreg) = srca;
	uae_s32 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u32)(~dst)) < ((uae_u32)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_ce000_prefetch(4);
		if(hardware_bus_error) {
			int pcoffset = 0;
			dreg_68000_long_replace_low(dstreg, newv);
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return;
		}
		opcode = regs.ir;
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	do_cycles_ce000_internal(2);
	if(loop_mode & 0xfffe) {
		do_cycles_ce000_internal(loop_mode & 0xfffe);
		loop_mode = 1;
	}
	m68k_dreg(regs, dstreg) = (newv);
	if (loop_mode) {
		do_cycles_ce000_internal(4);
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return;
}
/* 16 (3/0) */
/* 2 0,0   */

/* ADD.L (d16,An),Dn */
void REGPARAM2 op_d0a8_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u32)(~dst)) < ((uae_u32)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		dreg_68000_long_replace_low(dstreg, newv);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	do_cycles_ce000_internal(2);
	m68k_dreg(regs, dstreg) = (newv);
	m68k_incpci(4);
	return;
}
/* 18 (4/0) */
/* 4 0,0   */

/* ADD.L (d8,An,Xn),Dn */
void REGPARAM2 op_d0b0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	do_cycles_ce000_internal(2);
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u32)(~dst)) < ((uae_u32)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		dreg_68000_long_replace_low(dstreg, newv);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	do_cycles_ce000_internal(2);
	m68k_dreg(regs, dstreg) = (newv);
	m68k_incpci(4);
	return;
}
/* 20 (4/0) */
/* 4 4,0   */

/* ADD.L (xxx).W,Dn */
void REGPARAM2 op_d0b8_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	if (srca & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u32)(~dst)) < ((uae_u32)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		dreg_68000_long_replace_low(dstreg, newv);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	do_cycles_ce000_internal(2);
	m68k_dreg(regs, dstreg) = (newv);
	m68k_incpci(4);
	return;
}
/* 18 (4/0) */
/* 4 0,0   */

/* ADD.L (xxx).L,Dn */
void REGPARAM2 op_d0b9_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 22; 
	uaecptr srca;
	srca = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	srca |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	if (srca & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u32)(~dst)) < ((uae_u32)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		dreg_68000_long_replace_low(dstreg, newv);
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	opcode = regs.ir;
	do_cycles_ce000_internal(2);
	m68k_dreg(regs, dstreg) = (newv);
	m68k_incpci(6);
	return;
}
/* 22 (5/0) */
/* 6 0,0   */

/* ADD.L (d16,PC),Dn */
void REGPARAM2 op_d0ba_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	srca = m68k_getpci() + 2;
	srca += (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 2);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return;
	}
	ipl_fetch_now();
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 2);
		return;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u32)(~dst)) < ((uae_u32)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		dreg_68000_long_replace_low(dstreg, newv);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	do_cycles_ce000_internal(2);
	m68k_dreg(regs, dstreg) = (newv);
	m68k_incpci(4);
	return;
}
/* 18 (4/0) */
/* 4 0,0   */

/* ADD.L (d8,PC,Xn),Dn */
void REGPARAM2 op_d0bb_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	uaecptr tmppc = m68k_getpci() + 2;
	do_cycles_ce000_internal(2);
	srca = get_disp_ea_000(tmppc, get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 2);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return;
	}
	ipl_fetch_now();
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 2);
		return;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u32)(~dst)) < ((uae_u32)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		dreg_68000_long_replace_low(dstreg, newv);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	do_cycles_ce000_internal(2);
	m68k_dreg(regs, dstreg) = (newv);
	m68k_incpci(4);
	return;
}
/* 20 (4/0) */
/* 4 4,0   */

/* ADD.L #<data>.L,Dn */
void REGPARAM2 op_d0bc_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 14; 
	uae_s32 src;
	src = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	ipl_fetch_now();
	src |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u32)(~dst)) < ((uae_u32)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		uae_s16 bnewv = (uae_s16)dst + (uae_s16)src;
		int bflgs = ((uae_s16)(src)) < 0;
		int bflgo = ((uae_s16)(dst)) < 0;
		int bflgn = bnewv < 0;
		ccr_68000_long_move_ae_LZN(bnewv);
		SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
		SET_XFLG(GET_CFLG());
		SET_VFLG((bflgs ^ bflgn) & (bflgo ^ bflgn));
		dreg_68000_long_replace_low(dstreg, bnewv);
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	opcode = regs.ir;
	do_cycles_ce000_internal(2);
	m68k_dreg(regs, dstreg) = (newv);
	m68k_incpci(6);
	return;
}
/* 14 (3/0) */
/* 6 0,0   */

/* ADDA.W Dn,An */
void REGPARAM2 op_d0c0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 12;
	CurrentInstrCycles = 8;  
	uae_s16 src = m68k_dreg(regs, srcreg);
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = dst + src;
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		areg_68000_long_replace_low(dstreg, newv);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	do_cycles_ce000_internal(4);
	m68k_areg(regs, dstreg) = (newv);
	m68k_incpci(2);
	return;
}
/* 8 (1/0) */
/* 2 0,0   */

/* ADDA.W An,An */
void REGPARAM2 op_d0c8_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 12;
	CurrentInstrCycles = 8;  
	uae_s16 src = m68k_areg(regs, srcreg);
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = dst + src;
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		areg_68000_long_replace_low(dstreg, newv);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	do_cycles_ce000_internal(4);
	m68k_areg(regs, dstreg) = (newv);
	m68k_incpci(2);
	return;
}
/* 8 (1/0) */
/* 2 0,0   */

/* ADDA.W (An),An */
void REGPARAM2 op_d0d0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 12;
	CurrentInstrCycles = 12; 
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access2(opcode, srca, 1, 1);
		return;
	}
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = dst + src;
	ipl_fetch_next_pre();
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_ce000_prefetch(4);
		if(hardware_bus_error) {
			int pcoffset = 0;
			areg_68000_long_replace_low(dstreg, newv);
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return;
		}
		opcode = regs.ir;
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	do_cycles_ce000_internal(4);
	if(loop_mode & 0xfffe) {
		do_cycles_ce000_internal(loop_mode & 0xfffe);
		loop_mode = 1;
	}
	m68k_areg(regs, dstreg) = (newv);
	if (loop_mode) {
		do_cycles_ce000_internal(2);
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return;
}
/* 12 (2/0) */
/* 2 0,0   */

/* ADDA.W (An)+,An */
void REGPARAM2 op_d0d8_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 12;
	CurrentInstrCycles = 12; 
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_areg(regs, srcreg) += 2 + 0;
		m68k_incpci(2);
		exception3_read_access2(opcode, srca, 1, 1);
		return;
	}
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) += 2 + 0;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	m68k_areg(regs, srcreg) += 2;
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = dst + src;
	ipl_fetch_next_pre();
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_ce000_prefetch(4);
		if(hardware_bus_error) {
			int pcoffset = 0;
			areg_68000_long_replace_low(dstreg, newv);
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return;
		}
		opcode = regs.ir;
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	do_cycles_ce000_internal(4);
	if(loop_mode & 0xfffe) {
		do_cycles_ce000_internal(loop_mode & 0xfffe);
		loop_mode = 1;
	}
	m68k_areg(regs, dstreg) = (newv);
	if (loop_mode) {
		do_cycles_ce000_internal(2);
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return;
}
/* 12 (2/0) */
/* 2 0,0   */

/* ADDA.W -(An),An */
void REGPARAM2 op_d0e0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 12;
	CurrentInstrCycles = 14; 
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - 2;
	do_cycles_ce000_internal(2);
	if (srca & 1) {
		m68k_areg(regs, srcreg) = srca;
		m68k_incpci(2);
		exception3_read_access2(opcode, srca, 1, 1);
		return;
	}
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	m68k_areg(regs, srcreg) = srca;
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = dst + src;
	ipl_fetch_next_pre();
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_ce000_prefetch(4);
		if(hardware_bus_error) {
			int pcoffset = 0;
			areg_68000_long_replace_low(dstreg, newv);
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return;
		}
		opcode = regs.ir;
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	do_cycles_ce000_internal(4);
	if(loop_mode & 0xfffe) {
		do_cycles_ce000_internal(loop_mode & 0xfffe);
		loop_mode = 1;
	}
	m68k_areg(regs, dstreg) = (newv);
	if (loop_mode) {
		do_cycles_ce000_internal(2);
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return;
}
/* 14 (2/0) */
/* 2 0,0   */

/* ADDA.W (d16,An),An */
void REGPARAM2 op_d0e8_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 12;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = dst + src;
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		areg_68000_long_replace_low(dstreg, newv);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	do_cycles_ce000_internal(4);
	m68k_areg(regs, dstreg) = (newv);
	m68k_incpci(4);
	return;
}
/* 16 (3/0) */
/* 4 0,0   */

/* ADDA.W (d8,An,Xn),An */
void REGPARAM2 op_d0f0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 12;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	do_cycles_ce000_internal(2);
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = dst + src;
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		areg_68000_long_replace_low(dstreg, newv);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	do_cycles_ce000_internal(4);
	m68k_areg(regs, dstreg) = (newv);
	m68k_incpci(4);
	return;
}
/* 18 (3/0) */
/* 4 4,0   */

/* ADDA.W (xxx).W,An */
void REGPARAM2 op_d0f8_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 12;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	if (srca & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = dst + src;
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		areg_68000_long_replace_low(dstreg, newv);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	do_cycles_ce000_internal(4);
	m68k_areg(regs, dstreg) = (newv);
	m68k_incpci(4);
	return;
}
/* 16 (3/0) */
/* 4 0,0   */

/* ADDA.W (xxx).L,An */
void REGPARAM2 op_d0f9_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 12;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	srca = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	srca |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	if (srca & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = dst + src;
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		areg_68000_long_replace_low(dstreg, newv);
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	opcode = regs.ir;
	do_cycles_ce000_internal(4);
	m68k_areg(regs, dstreg) = (newv);
	m68k_incpci(6);
	return;
}
/* 20 (4/0) */
/* 6 0,0   */

/* ADDA.W (d16,PC),An */
void REGPARAM2 op_d0fa_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 12;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = m68k_getpci() + 2;
	srca += (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 2);
		return;
	}
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return;
	}
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = dst + src;
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		areg_68000_long_replace_low(dstreg, newv);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	do_cycles_ce000_internal(4);
	m68k_areg(regs, dstreg) = (newv);
	m68k_incpci(4);
	return;
}
/* 16 (3/0) */
/* 4 0,0   */

/* ADDA.W (d8,PC,Xn),An */
void REGPARAM2 op_d0fb_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 12;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	uaecptr tmppc = m68k_getpci() + 2;
	do_cycles_ce000_internal(2);
	srca = get_disp_ea_000(tmppc, get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 2);
		return;
	}
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return;
	}
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = dst + src;
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		areg_68000_long_replace_low(dstreg, newv);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	do_cycles_ce000_internal(4);
	m68k_areg(regs, dstreg) = (newv);
	m68k_incpci(4);
	return;
}
/* 18 (3/0) */
/* 4 4,0   */

/* ADDA.W #<data>.W,An */
void REGPARAM2 op_d0fc_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 12;
	CurrentInstrCycles = 12; 
	uae_s16 src = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = dst + src;
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		areg_68000_long_replace_low(dstreg, newv);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	do_cycles_ce000_internal(4);
	m68k_areg(regs, dstreg) = (newv);
	m68k_incpci(4);
	return;
}
/* 12 (2/0) */
/* 4 0,0   */

/* ADDX.B Dn,Dn */
void REGPARAM2 op_d100_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 13;
	CurrentInstrCycles = 4;  
	uae_s8 src = m68k_dreg(regs, srcreg);
	uae_s8 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = dst + src + (GET_XFLG() ? 1 : 0);
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(flgs ^ ((flgs ^ flgo) & (flgo ^ flgn)));
	COPY_CARRY();
	SET_ZFLG(GET_ZFLG() & (((uae_s8)(newv)) == 0));
	SET_NFLG(((uae_s8)(newv)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
	m68k_incpci(2);
	return;
}
/* 4 (1/0) */
/* 2 0,0   */

/* ADDX.B -(An),-(An) */
void REGPARAM2 op_d108_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 13;
	CurrentInstrCycles = 18; 
	int loop_mode = regs.loop_mode;
	do_cycles_ce000_internal(2);
	ipl_fetch_now();
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	m68k_areg(regs, srcreg) = srca;
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, dstreg) = dsta;
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	m68k_areg(regs, dstreg) = dsta;
	uae_u32 newv = dst + src + (GET_XFLG() ? 1 : 0);
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(flgs ^ ((flgs ^ flgo) & (flgo ^ flgn)));
	COPY_CARRY();
	SET_ZFLG(GET_ZFLG() & (((uae_s8)(newv)) == 0));
	SET_NFLG(((uae_s8)(newv)) < 0);
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_ce000_prefetch(4);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return;
		}
		opcode = regs.ir;
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	if(loop_mode & 0xfffe) {
		do_cycles_ce000_internal(loop_mode & 0xfffe);
		loop_mode = 1;
	}
	x_put_byte(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x0, newv, 1);
		return;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return;
}
/* 18 (3/1) */
/* 2 0,0   */

/* ADD.B Dn,(An) */
void REGPARAM2 op_d110_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 12; 
	int loop_mode = regs.loop_mode;
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u8)(~dst)) < ((uae_u8)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_ce000_prefetch(4);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return;
		}
		opcode = regs.ir;
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	if(loop_mode & 0xfffe) {
		do_cycles_ce000_internal(loop_mode & 0xfffe);
		loop_mode = 1;
	}
	x_put_byte(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x0, newv, 1);
		return;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return;
}
/* 12 (2/1) */
/* 2 0,0   */

/* ADD.B Dn,(An)+ */
void REGPARAM2 op_d118_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 12; 
	int loop_mode = regs.loop_mode;
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
	uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u8)(~dst)) < ((uae_u8)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_ce000_prefetch(4);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return;
		}
		opcode = regs.ir;
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	if(loop_mode & 0xfffe) {
		do_cycles_ce000_internal(loop_mode & 0xfffe);
		loop_mode = 1;
	}
	x_put_byte(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x0, newv, 1);
		return;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return;
}
/* 12 (2/1) */
/* 2 0,0   */

/* ADD.B Dn,-(An) */
void REGPARAM2 op_d120_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 14; 
	int loop_mode = regs.loop_mode;
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
	do_cycles_ce000_internal(2);
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, dstreg) = dsta;
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	m68k_areg(regs, dstreg) = dsta;
	uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u8)(~dst)) < ((uae_u8)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_ce000_prefetch(4);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return;
		}
		opcode = regs.ir;
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	if(loop_mode & 0xfffe) {
		do_cycles_ce000_internal(loop_mode & 0xfffe);
		loop_mode = 1;
	}
	x_put_byte(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x0, newv, 1);
		return;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return;
}
/* 14 (2/1) */
/* 2 0,0   */

/* ADD.B Dn,(d16,An) */
void REGPARAM2 op_d128_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 16; 
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u8)(~dst)) < ((uae_u8)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_byte(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x0, newv, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* ADD.B Dn,(d8,An,Xn) */
void REGPARAM2 op_d130_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 18; 
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	do_cycles_ce000_internal(2);
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u8)(~dst)) < ((uae_u8)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_byte(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x0, newv, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 18 (3/1) */
/* 4 4,0   */

/* ADD.B Dn,(xxx).W */
void REGPARAM2 op_d138_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	OpcodeFamily = 11;
	CurrentInstrCycles = 16; 
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u8)(~dst)) < ((uae_u8)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_byte(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x0, newv, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* ADD.B Dn,(xxx).L */
void REGPARAM2 op_d139_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	OpcodeFamily = 11;
	CurrentInstrCycles = 20; 
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	dsta |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u8)(~dst)) < ((uae_u8)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_byte(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 0, 0x0, newv, 1);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 20 (4/1) */
/* 6 0,0   */

/* ADDX.W Dn,Dn */
void REGPARAM2 op_d140_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 13;
	CurrentInstrCycles = 4;  
	uae_s16 src = m68k_dreg(regs, srcreg);
	uae_s16 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = dst + src + (GET_XFLG() ? 1 : 0);
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(flgs ^ ((flgs ^ flgo) & (flgo ^ flgn)));
	COPY_CARRY();
	SET_ZFLG(GET_ZFLG() & (((uae_s16)(newv)) == 0));
	SET_NFLG(((uae_s16)(newv)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
	m68k_incpci(2);
	return;
}
/* 4 (1/0) */
/* 2 0,0   */

/* ADDX.W -(An),-(An) */
void REGPARAM2 op_d148_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 13;
	CurrentInstrCycles = 18; 
	int loop_mode = regs.loop_mode;
	do_cycles_ce000_internal(2);
	ipl_fetch_now();
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - 2;
	if (srca & 1) {
		m68k_areg(regs, srcreg) = srca;
		m68k_areg(regs, srcreg) = srca;
		m68k_incpci(2);
		exception3_read_access2(opcode, srca, 1, 1);
		return;
	}
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	m68k_areg(regs, srcreg) = srca;
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - 2;
	if (dsta & 1) {
		m68k_areg(regs, dstreg) = dsta;
		m68k_areg(regs, dstreg) = dsta;
		m68k_incpci(2);
		exception3_read_access2(opcode, dsta, 1, 1);
		return;
	}
	uae_s16 dst = x_get_word(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, dstreg) = dsta;
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	m68k_areg(regs, dstreg) = dsta;
	uae_u32 newv = dst + src + (GET_XFLG() ? 1 : 0);
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(flgs ^ ((flgs ^ flgo) & (flgo ^ flgn)));
	COPY_CARRY();
	SET_ZFLG(GET_ZFLG() & (((uae_s16)(newv)) == 0));
	SET_NFLG(((uae_s16)(newv)) < 0);
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_ce000_prefetch(4);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return;
		}
		opcode = regs.ir;
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	if(loop_mode & 0xfffe) {
		do_cycles_ce000_internal(loop_mode & 0xfffe);
		loop_mode = 1;
	}
	x_put_word(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x1, newv, 1);
		return;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return;
}
/* 18 (3/1) */
/* 2 0,0   */

/* ADD.W Dn,(An) */
void REGPARAM2 op_d150_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 12; 
	int loop_mode = regs.loop_mode;
	uae_s16 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	if (dsta & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dsta, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 dst = x_get_word(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_ce000_prefetch(4);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return;
		}
		opcode = regs.ir;
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	if(loop_mode & 0xfffe) {
		do_cycles_ce000_internal(loop_mode & 0xfffe);
		loop_mode = 1;
	}
	x_put_word(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x1, newv, 1);
		return;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return;
}
/* 12 (2/1) */
/* 2 0,0   */

/* ADD.W Dn,(An)+ */
void REGPARAM2 op_d158_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 12; 
	int loop_mode = regs.loop_mode;
	uae_s16 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	if (dsta & 1) {
		m68k_areg(regs, dstreg) += 2 + 0;
		m68k_incpci(2);
		exception3_read_access(opcode, dsta, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 dst = x_get_word(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, dstreg) += 2 + 0;
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	m68k_areg(regs, dstreg) += 2;
	uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_ce000_prefetch(4);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return;
		}
		opcode = regs.ir;
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	if(loop_mode & 0xfffe) {
		do_cycles_ce000_internal(loop_mode & 0xfffe);
		loop_mode = 1;
	}
	x_put_word(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x1, newv, 1);
		return;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return;
}
/* 12 (2/1) */
/* 2 0,0   */

/* ADD.W Dn,-(An) */
void REGPARAM2 op_d160_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 14; 
	int loop_mode = regs.loop_mode;
	uae_s16 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - 2;
	do_cycles_ce000_internal(2);
	if (dsta & 1) {
		m68k_areg(regs, dstreg) = dsta;
		m68k_incpci(2);
		exception3_read_access(opcode, dsta, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 dst = x_get_word(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, dstreg) = dsta;
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	m68k_areg(regs, dstreg) = dsta;
	uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_ce000_prefetch(4);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return;
		}
		opcode = regs.ir;
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	if(loop_mode & 0xfffe) {
		do_cycles_ce000_internal(loop_mode & 0xfffe);
		loop_mode = 1;
	}
	x_put_word(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x1, newv, 1);
		return;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return;
}
/* 14 (2/1) */
/* 2 0,0   */

/* ADD.W Dn,(d16,An) */
void REGPARAM2 op_d168_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 16; 
	uae_s16 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dsta, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 dst = x_get_word(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_word(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, newv, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* ADD.W Dn,(d8,An,Xn) */
void REGPARAM2 op_d170_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 18; 
	uae_s16 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	do_cycles_ce000_internal(2);
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dsta, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 dst = x_get_word(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_word(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, newv, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 18 (3/1) */
/* 4 4,0   */

/* ADD.W Dn,(xxx).W */
void REGPARAM2 op_d178_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	OpcodeFamily = 11;
	CurrentInstrCycles = 16; 
	uae_s16 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, dsta, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 dst = x_get_word(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_word(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, newv, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* ADD.W Dn,(xxx).L */
void REGPARAM2 op_d179_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	OpcodeFamily = 11;
	CurrentInstrCycles = 20; 
	uae_s16 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	dsta |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, dsta, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 dst = x_get_word(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_word(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 0, 0x1, newv, 1);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 20 (4/1) */
/* 6 0,0   */

/* ADDX.L Dn,Dn */
void REGPARAM2 op_d180_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 13;
	CurrentInstrCycles = 6;  
	uae_s32 src = m68k_dreg(regs, srcreg);
	uae_s32 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = dst + src + (GET_XFLG() ? 1 : 0);
	int oldz = GET_ZFLG();
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(flgs ^ ((flgs ^ flgo) & (flgo ^ flgn)));
	COPY_CARRY();
	SET_ZFLG(GET_ZFLG() & (((uae_s32)(newv)) == 0));
	SET_NFLG(((uae_s32)(newv)) < 0);
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		int bflgs = ((uae_s16)(src)) < 0;
		int bflgo = ((uae_s16)(dst)) < 0;
		int bflgn = ((uae_s16)(newv)) < 0;
		SET_VFLG((bflgs ^ bflgn) & (bflgo ^ bflgn));
		SET_CFLG(bflgs ^ ((bflgs ^ bflgo) & (bflgo ^ bflgn)));
		SET_XFLG(GET_CFLG());
		SET_ZFLG(oldz);
		if (newv & 0xffff) SET_ZFLG(0);
		SET_NFLG(newv & 0x8000); 
		dreg_68000_long_replace_low(dstreg, newv);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	do_cycles_ce000_internal(2);
	m68k_dreg(regs, dstreg) = (newv);
	m68k_incpci(2);
	return;
}
/* 6 (1/0) */
/* 2 0,0   */

/* ADDX.L -(An),-(An) */
void REGPARAM2 op_d188_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 13;
	CurrentInstrCycles = 30; 
	int loop_mode = regs.loop_mode;
	do_cycles_ce000_internal(2);
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - 4;
	if (srca & 1) {
		m68k_incpci(2);
		srca += 2;
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	src |= x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	m68k_areg(regs, srcreg) = srca;
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - 4;
	if (dsta & 1) {
		m68k_incpci(2);
		dsta += 2;
		exception3_read_access(opcode, dsta, 2, 1);
		return;
	}
	uae_s32 dst = x_get_word(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	dst |= x_get_word(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	m68k_areg(regs, dstreg) = dsta;
	uae_u32 newv = dst + src + (GET_XFLG() ? 1 : 0);
	int oldz = GET_ZFLG();
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(flgs ^ ((flgs ^ flgo) & (flgo ^ flgn)));
	COPY_CARRY();
	SET_ZFLG(GET_ZFLG() & (((uae_s32)(newv)) == 0));
	SET_NFLG(((uae_s32)(newv)) < 0);
	x_put_word(dsta + 2, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		int bflgs = ((uae_s16)(src)) < 0;
		int bflgo = ((uae_s16)(dst)) < 0;
		int bflgn = ((uae_s16)(newv)) < 0;
		SET_VFLG((bflgs ^ bflgn) & (bflgo ^ bflgn));
		SET_CFLG(bflgs ^ ((bflgs ^ bflgo) & (bflgo ^ bflgn)));
		COPY_CARRY();
		SET_ZFLG(GET_ZFLG() & (((uae_s16)(newv)) == 0));
		SET_NFLG(((uae_s16)(newv)) < 0);
		exception2_write(opcode, dsta + 2, 0x1, newv, 1);
		return;
	}
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_ce000_prefetch(4);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return;
		}
	} else {
		loop_mode = 0;
		loop_mode |= 2;
		loop_mode |= 2 << 16;
	}
	x_put_word(dsta, newv >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x1, newv >> 16, 1);
		return;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return;
}
/* 30 (5/2) */
/* 2 0,0   */

/* ADD.L Dn,(An) */
void REGPARAM2 op_d190_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 20; 
	int loop_mode = regs.loop_mode;
	uae_s32 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	if (dsta & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dsta, 2, 1);
		return;
	}
	uae_s32 dst = x_get_word(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	dst |= x_get_word(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return;
	}
	uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u32)(~dst)) < ((uae_u32)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_ce000_prefetch(4);
		if(hardware_bus_error) {
			int pcoffset = 0;
			uae_s16 bnewv = (uae_s16)dst + (uae_s16)src;
			int bflgs = ((uae_s16)(src)) < 0;
			int bflgo = ((uae_s16)(dst)) < 0;
			int bflgn = bnewv < 0;
			ccr_68000_long_move_ae_LZN(bnewv);
			SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
			SET_XFLG(GET_CFLG());
			SET_VFLG((bflgs ^ bflgn) & (bflgo ^ bflgn));
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return;
		}
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	if(loop_mode & 0xfffe) {
		do_cycles_ce000_internal(loop_mode & 0xfffe);
		loop_mode = 1;
	}
	x_put_word(dsta + 2, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 2, 0x1, newv, 1);
		return;
	}
	x_put_word(dsta, newv >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x1, newv >> 16, 1);
		return;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return;
}
/* 20 (3/2) */
/* 2 0,0   */

/* ADD.L Dn,(An)+ */
void REGPARAM2 op_d198_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 20; 
	int loop_mode = regs.loop_mode;
	uae_s32 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	if (dsta & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dsta, 2, 1);
		return;
	}
	uae_s32 dst = x_get_word(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	dst |= x_get_word(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return;
	}
	m68k_areg(regs, dstreg) += 4;
	uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u32)(~dst)) < ((uae_u32)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_ce000_prefetch(4);
		if(hardware_bus_error) {
			int pcoffset = 0;
			uae_s16 bnewv = (uae_s16)dst + (uae_s16)src;
			int bflgs = ((uae_s16)(src)) < 0;
			int bflgo = ((uae_s16)(dst)) < 0;
			int bflgn = bnewv < 0;
			ccr_68000_long_move_ae_LZN(bnewv);
			SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
			SET_XFLG(GET_CFLG());
			SET_VFLG((bflgs ^ bflgn) & (bflgo ^ bflgn));
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return;
		}
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	if(loop_mode & 0xfffe) {
		do_cycles_ce000_internal(loop_mode & 0xfffe);
		loop_mode = 1;
	}
	x_put_word(dsta + 2, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 2, 0x1, newv, 1);
		return;
	}
	x_put_word(dsta, newv >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x1, newv >> 16, 1);
		return;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return;
}
/* 20 (3/2) */
/* 2 0,0   */

/* ADD.L Dn,-(An) */
void REGPARAM2 op_d1a0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 22; 
	int loop_mode = regs.loop_mode;
	uae_s32 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - 4;
	do_cycles_ce000_internal(2);
	if (dsta & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dsta, 2, 1);
		return;
	}
	uae_s32 dst = x_get_word(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	dst |= x_get_word(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, dstreg) = dsta;
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return;
	}
	m68k_areg(regs, dstreg) = dsta;
	uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u32)(~dst)) < ((uae_u32)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_ce000_prefetch(4);
		if(hardware_bus_error) {
			int pcoffset = 0;
			uae_s16 bnewv = (uae_s16)dst + (uae_s16)src;
			int bflgs = ((uae_s16)(src)) < 0;
			int bflgo = ((uae_s16)(dst)) < 0;
			int bflgn = bnewv < 0;
			ccr_68000_long_move_ae_LZN(bnewv);
			SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
			SET_XFLG(GET_CFLG());
			SET_VFLG((bflgs ^ bflgn) & (bflgo ^ bflgn));
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return;
		}
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	if(loop_mode & 0xfffe) {
		do_cycles_ce000_internal(loop_mode & 0xfffe);
		loop_mode = 1;
	}
	x_put_word(dsta + 2, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 2, 0x1, newv, 1);
		return;
	}
	x_put_word(dsta, newv >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x1, newv >> 16, 1);
		return;
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return;
}
/* 22 (3/2) */
/* 2 0,0   */

/* ADD.L Dn,(d16,An) */
void REGPARAM2 op_d1a8_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 24; 
	uae_s32 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dsta, 2, 1);
		return;
	}
	uae_s32 dst = x_get_word(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	dst |= x_get_word(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return;
	}
	uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u32)(~dst)) < ((uae_u32)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		uae_s16 bnewv = (uae_s16)dst + (uae_s16)src;
		int bflgs = ((uae_s16)(src)) < 0;
		int bflgo = ((uae_s16)(dst)) < 0;
		int bflgn = bnewv < 0;
		ccr_68000_long_move_ae_LZN(bnewv);
		SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
		SET_XFLG(GET_CFLG());
		SET_VFLG((bflgs ^ bflgn) & (bflgo ^ bflgn));
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	x_put_word(dsta + 2, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 2, 0x1, newv, 1);
		return;
	}
	x_put_word(dsta, newv >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, newv >> 16, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 24 (4/2) */
/* 4 0,0   */

/* ADD.L Dn,(d8,An,Xn) */
void REGPARAM2 op_d1b0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 26; 
	uae_s32 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	do_cycles_ce000_internal(2);
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dsta, 2, 1);
		return;
	}
	uae_s32 dst = x_get_word(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	dst |= x_get_word(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return;
	}
	uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u32)(~dst)) < ((uae_u32)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		uae_s16 bnewv = (uae_s16)dst + (uae_s16)src;
		int bflgs = ((uae_s16)(src)) < 0;
		int bflgo = ((uae_s16)(dst)) < 0;
		int bflgn = bnewv < 0;
		ccr_68000_long_move_ae_LZN(bnewv);
		SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
		SET_XFLG(GET_CFLG());
		SET_VFLG((bflgs ^ bflgn) & (bflgo ^ bflgn));
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	x_put_word(dsta + 2, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 2, 0x1, newv, 1);
		return;
	}
	x_put_word(dsta, newv >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, newv >> 16, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 26 (4/2) */
/* 4 4,0   */

/* ADD.L Dn,(xxx).W */
void REGPARAM2 op_d1b8_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	OpcodeFamily = 11;
	CurrentInstrCycles = 24; 
	uae_s32 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, dsta, 2, 1);
		return;
	}
	uae_s32 dst = x_get_word(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	dst |= x_get_word(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return;
	}
	uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u32)(~dst)) < ((uae_u32)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		uae_s16 bnewv = (uae_s16)dst + (uae_s16)src;
		int bflgs = ((uae_s16)(src)) < 0;
		int bflgo = ((uae_s16)(dst)) < 0;
		int bflgn = bnewv < 0;
		ccr_68000_long_move_ae_LZN(bnewv);
		SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
		SET_XFLG(GET_CFLG());
		SET_VFLG((bflgs ^ bflgn) & (bflgo ^ bflgn));
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	x_put_word(dsta + 2, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 2, 0x1, newv, 1);
		return;
	}
	x_put_word(dsta, newv >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, newv >> 16, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 24 (4/2) */
/* 4 0,0   */

/* ADD.L Dn,(xxx).L */
void REGPARAM2 op_d1b9_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	OpcodeFamily = 11;
	CurrentInstrCycles = 28; 
	uae_s32 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	dsta |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, dsta, 2, 1);
		return;
	}
	uae_s32 dst = x_get_word(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	dst |= x_get_word(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return;
	}
	uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u32)(~dst)) < ((uae_u32)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		uae_s16 bnewv = (uae_s16)dst + (uae_s16)src;
		int bflgs = ((uae_s16)(src)) < 0;
		int bflgo = ((uae_s16)(dst)) < 0;
		int bflgn = bnewv < 0;
		ccr_68000_long_move_ae_LZN(bnewv);
		SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
		SET_XFLG(GET_CFLG());
		SET_VFLG((bflgs ^ bflgn) & (bflgo ^ bflgn));
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	x_put_word(dsta + 2, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 2, 0x1, newv, 1);
		return;
	}
	x_put_word(dsta, newv >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 0, 0x1, newv >> 16, 1);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 28 (5/2) */
/* 6 0,0   */

/* ADDA.L Dn,An */
void REGPARAM2 op_d1c0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 12;
	CurrentInstrCycles = 8;  
	uae_s32 src = m68k_dreg(regs, srcreg);
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = dst + src;
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		areg_68000_long_replace_low(dstreg, newv);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	do_cycles_ce000_internal(4);
	m68k_areg(regs, dstreg) = (newv);
	m68k_incpci(2);
	return;
}
/* 8 (1/0) */
/* 2 0,0   */

/* ADDA.L An,An */
void REGPARAM2 op_d1c8_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 12;
	CurrentInstrCycles = 8;  
	uae_s32 src = m68k_areg(regs, srcreg);
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = dst + src;
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		areg_68000_long_replace_low(dstreg, newv);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	do_cycles_ce000_internal(4);
	m68k_areg(regs, dstreg) = (newv);
	m68k_incpci(2);
	return;
}
/* 8 (1/0) */
/* 2 0,0   */

/* ADDA.L (An),An */
void REGPARAM2 op_d1d0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 12;
	CurrentInstrCycles = 14; 
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = dst + src;
	ipl_fetch_next_pre();
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_ce000_prefetch(4);
		if(hardware_bus_error) {
			int pcoffset = 0;
			areg_68000_long_replace_low(dstreg, newv);
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return;
		}
		opcode = regs.ir;
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	do_cycles_ce000_internal(2);
	if(loop_mode & 0xfffe) {
		do_cycles_ce000_internal(loop_mode & 0xfffe);
		loop_mode = 1;
	}
	m68k_areg(regs, dstreg) = (newv);
	if (loop_mode) {
		do_cycles_ce000_internal(4);
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return;
}
/* 14 (3/0) */
/* 2 0,0   */

/* ADDA.L (An)+,An */
void REGPARAM2 op_d1d8_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 12;
	CurrentInstrCycles = 14; 
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	m68k_areg(regs, srcreg) += 4;
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = dst + src;
	ipl_fetch_next_pre();
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_ce000_prefetch(4);
		if(hardware_bus_error) {
			int pcoffset = 0;
			areg_68000_long_replace_low(dstreg, newv);
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return;
		}
		opcode = regs.ir;
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	do_cycles_ce000_internal(2);
	if(loop_mode & 0xfffe) {
		do_cycles_ce000_internal(loop_mode & 0xfffe);
		loop_mode = 1;
	}
	m68k_areg(regs, dstreg) = (newv);
	if (loop_mode) {
		do_cycles_ce000_internal(4);
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return;
}
/* 14 (3/0) */
/* 2 0,0   */

/* ADDA.L -(An),An */
void REGPARAM2 op_d1e0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 12;
	CurrentInstrCycles = 16; 
	int loop_mode = regs.loop_mode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - 4;
	do_cycles_ce000_internal(2);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	m68k_areg(regs, srcreg) = srca;
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = dst + src;
	ipl_fetch_next_pre();
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_ce000_prefetch(4);
		if(hardware_bus_error) {
			int pcoffset = 0;
			areg_68000_long_replace_low(dstreg, newv);
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return;
		}
		opcode = regs.ir;
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	do_cycles_ce000_internal(2);
	if(loop_mode & 0xfffe) {
		do_cycles_ce000_internal(loop_mode & 0xfffe);
		loop_mode = 1;
	}
	m68k_areg(regs, dstreg) = (newv);
	if (loop_mode) {
		do_cycles_ce000_internal(4);
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return;
}
/* 16 (3/0) */
/* 2 0,0   */

/* ADDA.L (d16,An),An */
void REGPARAM2 op_d1e8_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 12;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = dst + src;
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		areg_68000_long_replace_low(dstreg, newv);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	do_cycles_ce000_internal(2);
	m68k_areg(regs, dstreg) = (newv);
	m68k_incpci(4);
	return;
}
/* 18 (4/0) */
/* 4 0,0   */

/* ADDA.L (d8,An,Xn),An */
void REGPARAM2 op_d1f0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 12;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	do_cycles_ce000_internal(2);
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = dst + src;
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		areg_68000_long_replace_low(dstreg, newv);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	do_cycles_ce000_internal(2);
	m68k_areg(regs, dstreg) = (newv);
	m68k_incpci(4);
	return;
}
/* 20 (4/0) */
/* 4 4,0   */

/* ADDA.L (xxx).W,An */
void REGPARAM2 op_d1f8_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 12;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	if (srca & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = dst + src;
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		areg_68000_long_replace_low(dstreg, newv);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	do_cycles_ce000_internal(2);
	m68k_areg(regs, dstreg) = (newv);
	m68k_incpci(4);
	return;
}
/* 18 (4/0) */
/* 4 0,0   */

/* ADDA.L (xxx).L,An */
void REGPARAM2 op_d1f9_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 12;
	CurrentInstrCycles = 22; 
	uaecptr srca;
	srca = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	srca |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	if (srca & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = dst + src;
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		areg_68000_long_replace_low(dstreg, newv);
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	opcode = regs.ir;
	do_cycles_ce000_internal(2);
	m68k_areg(regs, dstreg) = (newv);
	m68k_incpci(6);
	return;
}
/* 22 (5/0) */
/* 6 0,0   */

/* ADDA.L (d16,PC),An */
void REGPARAM2 op_d1fa_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 12;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	srca = m68k_getpci() + 2;
	srca += (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 2);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return;
	}
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 2);
		return;
	}
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = dst + src;
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		areg_68000_long_replace_low(dstreg, newv);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	do_cycles_ce000_internal(2);
	m68k_areg(regs, dstreg) = (newv);
	m68k_incpci(4);
	return;
}
/* 18 (4/0) */
/* 4 0,0   */

/* ADDA.L (d8,PC,Xn),An */
void REGPARAM2 op_d1fb_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 12;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	uaecptr tmppc = m68k_getpci() + 2;
	do_cycles_ce000_internal(2);
	srca = get_disp_ea_000(tmppc, get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 2);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return;
	}
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 2);
		return;
	}
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = dst + src;
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		areg_68000_long_replace_low(dstreg, newv);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	do_cycles_ce000_internal(2);
	m68k_areg(regs, dstreg) = (newv);
	m68k_incpci(4);
	return;
}
/* 20 (4/0) */
/* 4 4,0   */

/* ADDA.L #<data>.L,An */
void REGPARAM2 op_d1fc_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 12;
	CurrentInstrCycles = 16; 
	uae_s32 src;
	src = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	src |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = dst + src;
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		areg_68000_long_replace_low(dstreg, newv);
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	opcode = regs.ir;
	do_cycles_ce000_internal(4);
	m68k_areg(regs, dstreg) = (newv);
	m68k_incpci(6);
	return;
}
/* 16 (3/0) */
/* 6 0,0   */

/* ASRQ.B #<data>,Dn */
void REGPARAM2 op_e000_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 64;
	CurrentInstrCycles = 6;  
	uae_u32 cnt = srcreg;
	uae_s8 data = m68k_dreg(regs, dstreg);
	uae_u32 val = (uae_u8)data;
	CLEAR_CZNV();
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		SET_ZFLG(!(val & 0xff));
		SET_NFLG(val & 0x80);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	uae_u32 sign = (0x80 & val) >> 7;
	int ccnt = cnt & 63;
	cnt &= 63;
	if (cnt >= 8) {
		val = 0xff & (uae_u32)(0 - sign);
		SET_CFLG(sign);
		COPY_CARRY();
	} else {
		val >>= cnt - 1;
		SET_CFLG(val & 1);
		COPY_CARRY();
		val >>= 1;
		val |= (0xff << (8 - cnt)) & (uae_u32)(0 - sign);
		val &= 0xff;
	}
	SET_ZFLG(((uae_s8)(val)) == 0);
	SET_NFLG(((uae_s8)(val)) < 0);
	{
		int cycles = 2;
		cycles += 2 * ccnt;
		do_cycles_ce000_internal(cycles);
	}
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((val) & 0xff);
	m68k_incpci(2);
	return;
}
/* 6+ (1/0) */
/* 2 0,0   */

/* LSRQ.B #<data>,Dn */
void REGPARAM2 op_e008_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 66;
	CurrentInstrCycles = 6;  
	uae_u32 cnt = srcreg;
	uae_s8 data = m68k_dreg(regs, dstreg);
	uae_u32 val = (uae_u8)data;
	CLEAR_CZNV();
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		SET_ZFLG(!(val & 0xff));
		SET_NFLG(val & 0x80);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	int ccnt = cnt & 63;
	cnt &= 63;
	if (cnt >= 8) {
		SET_CFLG((cnt == 8) & (val >> 7));
		COPY_CARRY();
		val = 0;
	} else {
		val >>= cnt - 1;
		SET_CFLG(val & 1);
		COPY_CARRY();
		val >>= 1;
	}
	SET_ZFLG(((uae_s8)(val)) == 0);
	SET_NFLG(((uae_s8)(val)) < 0);
	{
		int cycles = 2;
		cycles += 2 * ccnt;
		do_cycles_ce000_internal(cycles);
	}
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((val) & 0xff);
	m68k_incpci(2);
	return;
}
/* 6+ (1/0) */
/* 2 0,0   */

/* ROXRQ.B #<data>,Dn */
void REGPARAM2 op_e010_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 71;
	CurrentInstrCycles = 6;  
	uae_u32 cnt = srcreg;
	uae_s8 data = m68k_dreg(regs, dstreg);
	uae_u32 val = (uae_u8)data;
	CLEAR_CZNV();
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		SET_ZFLG(!(val & 0xff));
		SET_NFLG(val & 0x80);
		SET_CFLG(GET_XFLG());
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	int ccnt = cnt & 63;
	cnt &= 63;
	{
		cnt--;
		{
			uae_u32 carry;
			uae_u32 hival = (val << 1) | GET_XFLG();
			hival <<= (7 - cnt);
			val >>= cnt;
			carry = val & 1;
			val >>= 1;
			val |= hival;
			SET_XFLG(carry);
			val &= 0xff;
		}
	}
	SET_CFLG(GET_XFLG());
	SET_ZFLG(((uae_s8)(val)) == 0);
	SET_NFLG(((uae_s8)(val)) < 0);
	{
		int cycles = 2;
		cycles += 2 * ccnt;
		do_cycles_ce000_internal(cycles);
	}
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((val) & 0xff);
	m68k_incpci(2);
	return;
}
/* 6+ (1/0) */
/* 2 0,0   */

/* RORQ.B #<data>,Dn */
void REGPARAM2 op_e018_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 69;
	CurrentInstrCycles = 6;  
	uae_u32 cnt = srcreg;
	uae_s8 data = m68k_dreg(regs, dstreg);
	uae_u32 val = (uae_u8)data;
	CLEAR_CZNV();
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		SET_ZFLG(!(val & 0xff));
		SET_NFLG(val & 0x80);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	int ccnt = cnt & 63;
	cnt &= 63;
	{
		uae_u32 hival;
		cnt &= 7;
		hival = val << (8 - cnt);
		val >>= cnt;
		val |= hival;
		val &= 0xff;
		SET_CFLG((val & 0x80) >> 7);
	}
	SET_ZFLG(((uae_s8)(val)) == 0);
	SET_NFLG(((uae_s8)(val)) < 0);
	{
		int cycles = 2;
		cycles += 2 * ccnt;
		do_cycles_ce000_internal(cycles);
	}
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((val) & 0xff);
	m68k_incpci(2);
	return;
}
/* 6+ (1/0) */
/* 2 0,0   */

/* ASR.B Dn,Dn */
void REGPARAM2 op_e020_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 64;
	CurrentInstrCycles = 6;  
	uae_s8 cnt = m68k_dreg(regs, srcreg);
	uae_s8 data = m68k_dreg(regs, dstreg);
	uae_u32 val = (uae_u8)data;
	CLEAR_CZNV();
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		SET_ZFLG(!(val & 0xff));
		SET_NFLG(val & 0x80);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	uae_u32 sign = (0x80 & val) >> 7;
	int ccnt = cnt & 63;
	cnt &= 63;
	if (cnt >= 8) {
		val = 0xff & (uae_u32)(0 - sign);
		SET_CFLG(sign);
		COPY_CARRY();
	} else if (cnt > 0) {
		val >>= cnt - 1;
		SET_CFLG(val & 1);
		COPY_CARRY();
		val >>= 1;
		val |= (0xff << (8 - cnt)) & (uae_u32)(0 - sign);
		val &= 0xff;
	}
	SET_ZFLG(((uae_s8)(val)) == 0);
	SET_NFLG(((uae_s8)(val)) < 0);
	{
		int cycles = 2;
		cycles += 2 * ccnt;
		do_cycles_ce000_internal(cycles);
	}
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((val) & 0xff);
	m68k_incpci(2);
	return;
}
/* 6+ (1/0) */
/* 2 0,0   */

/* LSR.B Dn,Dn */
void REGPARAM2 op_e028_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 66;
	CurrentInstrCycles = 6;  
	uae_s8 cnt = m68k_dreg(regs, srcreg);
	uae_s8 data = m68k_dreg(regs, dstreg);
	uae_u32 val = (uae_u8)data;
	CLEAR_CZNV();
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		SET_ZFLG(!(val & 0xff));
		SET_NFLG(val & 0x80);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	int ccnt = cnt & 63;
	cnt &= 63;
	if (cnt >= 8) {
		SET_CFLG((cnt == 8) & (val >> 7));
		COPY_CARRY();
		val = 0;
	} else if (cnt > 0) {
		val >>= cnt - 1;
		SET_CFLG(val & 1);
		COPY_CARRY();
		val >>= 1;
	}
	SET_ZFLG(((uae_s8)(val)) == 0);
	SET_NFLG(((uae_s8)(val)) < 0);
	{
		int cycles = 2;
		cycles += 2 * ccnt;
		do_cycles_ce000_internal(cycles);
	}
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((val) & 0xff);
	m68k_incpci(2);
	return;
}
/* 6+ (1/0) */
/* 2 0,0   */

/* ROXR.B Dn,Dn */
void REGPARAM2 op_e030_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 71;
	CurrentInstrCycles = 6;  
	uae_s8 cnt = m68k_dreg(regs, srcreg);
	uae_s8 data = m68k_dreg(regs, dstreg);
	uae_u32 val = (uae_u8)data;
	CLEAR_CZNV();
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		SET_ZFLG(!(val & 0xff));
		SET_NFLG(val & 0x80);
		SET_CFLG(GET_XFLG());
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	int ccnt = cnt & 63;
	cnt &= 63;
	if (cnt >= 36) cnt -= 36;
	if (cnt >= 18) cnt -= 18;
	if (cnt >= 9) cnt -= 9;
	if (cnt > 0) {
		cnt--;
		{
			uae_u32 carry;
			uae_u32 hival = (val << 1) | GET_XFLG();
			hival <<= (7 - cnt);
			val >>= cnt;
			carry = val & 1;
			val >>= 1;
			val |= hival;
			SET_XFLG(carry);
			val &= 0xff;
		}
	}
	SET_CFLG(GET_XFLG());
	SET_ZFLG(((uae_s8)(val)) == 0);
	SET_NFLG(((uae_s8)(val)) < 0);
	{
		int cycles = 2;
		cycles += 2 * ccnt;
		do_cycles_ce000_internal(cycles);
	}
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((val) & 0xff);
	m68k_incpci(2);
	return;
}
/* 6+ (1/0) */
/* 2 0,0   */

/* ROR.B Dn,Dn */
void REGPARAM2 op_e038_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 69;
	CurrentInstrCycles = 6;  
	uae_s8 cnt = m68k_dreg(regs, srcreg);
	uae_s8 data = m68k_dreg(regs, dstreg);
	uae_u32 val = (uae_u8)data;
	CLEAR_CZNV();
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		SET_ZFLG(!(val & 0xff));
		SET_NFLG(val & 0x80);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	int ccnt = cnt & 63;
	cnt &= 63;
	if (cnt > 0) {
		uae_u32 hival;
		cnt &= 7;
		hival = val << (8 - cnt);
		val >>= cnt;
		val |= hival;
		val &= 0xff;
		SET_CFLG((val & 0x80) >> 7);
	}
	SET_ZFLG(((uae_s8)(val)) == 0);
	SET_NFLG(((uae_s8)(val)) < 0);
	{
		int cycles = 2;
		cycles += 2 * ccnt;
		do_cycles_ce000_internal(cycles);
	}
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((val) & 0xff);
	m68k_incpci(2);
	return;
}
/* 6+ (1/0) */
/* 2 0,0   */

/* ASRQ.W #<data>,Dn */
void REGPARAM2 op_e040_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 64;
	CurrentInstrCycles = 6;  
	uae_u32 cnt = srcreg;
	uae_s16 data = m68k_dreg(regs, dstreg);
	uae_u32 val = (uae_u16)data;
	CLEAR_CZNV();
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		SET_ZFLG(!(val & 0xffff));
		SET_NFLG(val & 0x8000);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	uae_u32 sign = (0x8000 & val) >> 15;
	int ccnt = cnt & 63;
	cnt &= 63;
	if (cnt >= 16) {
		val = 0xffff & (uae_u32)(0 - sign);
		SET_CFLG(sign);
		COPY_CARRY();
	} else {
		val >>= cnt - 1;
		SET_CFLG(val & 1);
		COPY_CARRY();
		val >>= 1;
		val |= (0xffff << (16 - cnt)) & (uae_u32)(0 - sign);
		val &= 0xffff;
	}
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	{
		int cycles = 2;
		cycles += 2 * ccnt;
		do_cycles_ce000_internal(cycles);
	}
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((val) & 0xffff);
	m68k_incpci(2);
	return;
}
/* 6+ (1/0) */
/* 2 0,0   */

/* LSRQ.W #<data>,Dn */
void REGPARAM2 op_e048_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 66;
	CurrentInstrCycles = 6;  
	uae_u32 cnt = srcreg;
	uae_s16 data = m68k_dreg(regs, dstreg);
	uae_u32 val = (uae_u16)data;
	CLEAR_CZNV();
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		SET_ZFLG(!(val & 0xffff));
		SET_NFLG(val & 0x8000);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	int ccnt = cnt & 63;
	cnt &= 63;
	if (cnt >= 16) {
		SET_CFLG((cnt == 16) & (val >> 15));
		COPY_CARRY();
		val = 0;
	} else {
		val >>= cnt - 1;
		SET_CFLG(val & 1);
		COPY_CARRY();
		val >>= 1;
	}
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	{
		int cycles = 2;
		cycles += 2 * ccnt;
		do_cycles_ce000_internal(cycles);
	}
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((val) & 0xffff);
	m68k_incpci(2);
	return;
}
/* 6+ (1/0) */
/* 2 0,0   */

/* ROXRQ.W #<data>,Dn */
void REGPARAM2 op_e050_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 71;
	CurrentInstrCycles = 6;  
	uae_u32 cnt = srcreg;
	uae_s16 data = m68k_dreg(regs, dstreg);
	uae_u32 val = (uae_u16)data;
	CLEAR_CZNV();
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		SET_ZFLG(!(val & 0xffff));
		SET_NFLG(val & 0x8000);
		SET_CFLG(GET_XFLG());
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	int ccnt = cnt & 63;
	cnt &= 63;
	{
		cnt--;
		{
			uae_u32 carry;
			uae_u32 hival = (val << 1) | GET_XFLG();
			hival <<= (15 - cnt);
			val >>= cnt;
			carry = val & 1;
			val >>= 1;
			val |= hival;
			SET_XFLG(carry);
			val &= 0xffff;
		}
	}
	SET_CFLG(GET_XFLG());
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	{
		int cycles = 2;
		cycles += 2 * ccnt;
		do_cycles_ce000_internal(cycles);
	}
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((val) & 0xffff);
	m68k_incpci(2);
	return;
}
/* 6+ (1/0) */
/* 2 0,0   */

/* RORQ.W #<data>,Dn */
void REGPARAM2 op_e058_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 69;
	CurrentInstrCycles = 6;  
	uae_u32 cnt = srcreg;
	uae_s16 data = m68k_dreg(regs, dstreg);
	uae_u32 val = (uae_u16)data;
	CLEAR_CZNV();
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		SET_ZFLG(!(val & 0xffff));
		SET_NFLG(val & 0x8000);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	int ccnt = cnt & 63;
	cnt &= 63;
	{
		uae_u32 hival;
		cnt &= 15;
		hival = val << (16 - cnt);
		val >>= cnt;
		val |= hival;
		val &= 0xffff;
		SET_CFLG((val & 0x8000) >> 15);
	}
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	{
		int cycles = 2;
		cycles += 2 * ccnt;
		do_cycles_ce000_internal(cycles);
	}
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((val) & 0xffff);
	m68k_incpci(2);
	return;
}
/* 6+ (1/0) */
/* 2 0,0   */

/* ASR.W Dn,Dn */
void REGPARAM2 op_e060_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 64;
	CurrentInstrCycles = 6;  
	uae_s16 cnt = m68k_dreg(regs, srcreg);
	uae_s16 data = m68k_dreg(regs, dstreg);
	uae_u32 val = (uae_u16)data;
	CLEAR_CZNV();
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		SET_ZFLG(!(val & 0xffff));
		SET_NFLG(val & 0x8000);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	uae_u32 sign = (0x8000 & val) >> 15;
	int ccnt = cnt & 63;
	cnt &= 63;
	if (cnt >= 16) {
		val = 0xffff & (uae_u32)(0 - sign);
		SET_CFLG(sign);
		COPY_CARRY();
	} else if (cnt > 0) {
		val >>= cnt - 1;
		SET_CFLG(val & 1);
		COPY_CARRY();
		val >>= 1;
		val |= (0xffff << (16 - cnt)) & (uae_u32)(0 - sign);
		val &= 0xffff;
	}
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	{
		int cycles = 2;
		cycles += 2 * ccnt;
		do_cycles_ce000_internal(cycles);
	}
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((val) & 0xffff);
	m68k_incpci(2);
	return;
}
/* 6+ (1/0) */
/* 2 0,0   */

/* LSR.W Dn,Dn */
void REGPARAM2 op_e068_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 66;
	CurrentInstrCycles = 6;  
	uae_s16 cnt = m68k_dreg(regs, srcreg);
	uae_s16 data = m68k_dreg(regs, dstreg);
	uae_u32 val = (uae_u16)data;
	CLEAR_CZNV();
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		SET_ZFLG(!(val & 0xffff));
		SET_NFLG(val & 0x8000);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	int ccnt = cnt & 63;
	cnt &= 63;
	if (cnt >= 16) {
		SET_CFLG((cnt == 16) & (val >> 15));
		COPY_CARRY();
		val = 0;
	} else if (cnt > 0) {
		val >>= cnt - 1;
		SET_CFLG(val & 1);
		COPY_CARRY();
		val >>= 1;
	}
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	{
		int cycles = 2;
		cycles += 2 * ccnt;
		do_cycles_ce000_internal(cycles);
	}
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((val) & 0xffff);
	m68k_incpci(2);
	return;
}
/* 6+ (1/0) */
/* 2 0,0   */

/* ROXR.W Dn,Dn */
void REGPARAM2 op_e070_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 71;
	CurrentInstrCycles = 6;  
	uae_s16 cnt = m68k_dreg(regs, srcreg);
	uae_s16 data = m68k_dreg(regs, dstreg);
	uae_u32 val = (uae_u16)data;
	CLEAR_CZNV();
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		SET_ZFLG(!(val & 0xffff));
		SET_NFLG(val & 0x8000);
		SET_CFLG(GET_XFLG());
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	int ccnt = cnt & 63;
	cnt &= 63;
	if (cnt >= 34) cnt -= 34;
	if (cnt >= 17) cnt -= 17;
	if (cnt > 0) {
		cnt--;
		{
			uae_u32 carry;
			uae_u32 hival = (val << 1) | GET_XFLG();
			hival <<= (15 - cnt);
			val >>= cnt;
			carry = val & 1;
			val >>= 1;
			val |= hival;
			SET_XFLG(carry);
			val &= 0xffff;
		}
	}
	SET_CFLG(GET_XFLG());
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	{
		int cycles = 2;
		cycles += 2 * ccnt;
		do_cycles_ce000_internal(cycles);
	}
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((val) & 0xffff);
	m68k_incpci(2);
	return;
}
/* 6+ (1/0) */
/* 2 0,0   */

/* ROR.W Dn,Dn */
void REGPARAM2 op_e078_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 69;
	CurrentInstrCycles = 6;  
	uae_s16 cnt = m68k_dreg(regs, srcreg);
	uae_s16 data = m68k_dreg(regs, dstreg);
	uae_u32 val = (uae_u16)data;
	CLEAR_CZNV();
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		SET_ZFLG(!(val & 0xffff));
		SET_NFLG(val & 0x8000);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	int ccnt = cnt & 63;
	cnt &= 63;
	if (cnt > 0) {
		uae_u32 hival;
		cnt &= 15;
		hival = val << (16 - cnt);
		val >>= cnt;
		val |= hival;
		val &= 0xffff;
		SET_CFLG((val & 0x8000) >> 15);
	}
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	{
		int cycles = 2;
		cycles += 2 * ccnt;
		do_cycles_ce000_internal(cycles);
	}
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((val) & 0xffff);
	m68k_incpci(2);
	return;
}
/* 6+ (1/0) */
/* 2 0,0   */

/* ASRQ.L #<data>,Dn */
void REGPARAM2 op_e080_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 64;
	CurrentInstrCycles = 8;  
	uae_u32 cnt = srcreg;
	uae_s32 data = m68k_dreg(regs, dstreg);
	uae_u32 val = data;
	CLEAR_CZNV();
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		SET_NFLG(val & 0x8000);
		SET_ZFLG(!(val & 0xffff));
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	uae_u32 sign = (0x80000000 & val) >> 31;
	int ccnt = cnt & 63;
	cnt &= 63;
	if (cnt >= 32) {
		val = 0xffffffff & (uae_u32)(0 - sign);
		SET_CFLG(sign);
		COPY_CARRY();
	} else {
		val >>= cnt - 1;
		SET_CFLG(val & 1);
		COPY_CARRY();
		val >>= 1;
		val |= (0xffffffff << (32 - cnt)) & (uae_u32)(0 - sign);
		val &= 0xffffffff;
	}
	SET_ZFLG(((uae_s32)(val)) == 0);
	SET_NFLG(((uae_s32)(val)) < 0);
	{
		int cycles = 4;
		cycles += 2 * ccnt;
		do_cycles_ce000_internal(cycles);
	}
	m68k_dreg(regs, dstreg) = (val);
	m68k_incpci(2);
	return;
}
/* 8+ (1/0) */
/* 2 0,0   */

/* LSRQ.L #<data>,Dn */
void REGPARAM2 op_e088_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 66;
	CurrentInstrCycles = 8;  
	uae_u32 cnt = srcreg;
	uae_s32 data = m68k_dreg(regs, dstreg);
	uae_u32 val = data;
	CLEAR_CZNV();
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		SET_NFLG(val & 0x8000);
		SET_ZFLG(!(val & 0xffff));
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	int ccnt = cnt & 63;
	cnt &= 63;
	if (cnt >= 32) {
		SET_CFLG((cnt == 32) & (val >> 31));
		COPY_CARRY();
		val = 0;
	} else {
		val >>= cnt - 1;
		SET_CFLG(val & 1);
		COPY_CARRY();
		val >>= 1;
	}
	SET_ZFLG(((uae_s32)(val)) == 0);
	SET_NFLG(((uae_s32)(val)) < 0);
	{
		int cycles = 4;
		cycles += 2 * ccnt;
		do_cycles_ce000_internal(cycles);
	}
	m68k_dreg(regs, dstreg) = (val);
	m68k_incpci(2);
	return;
}
/* 8+ (1/0) */
/* 2 0,0   */

/* ROXRQ.L #<data>,Dn */
void REGPARAM2 op_e090_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 71;
	CurrentInstrCycles = 8;  
	uae_u32 cnt = srcreg;
	uae_s32 data = m68k_dreg(regs, dstreg);
	uae_u32 val = data;
	CLEAR_CZNV();
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		SET_NFLG(val & 0x8000);
		SET_ZFLG(!(val & 0xffff));
		SET_CFLG(GET_XFLG());
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	int ccnt = cnt & 63;
	cnt &= 63;
	{
		cnt--;
		{
			uae_u32 carry;
			uae_u32 hival = (val << 1) | GET_XFLG();
			hival <<= (31 - cnt);
			val >>= cnt;
			carry = val & 1;
			val >>= 1;
			val |= hival;
			SET_XFLG(carry);
			val &= 0xffffffff;
		}
	}
	SET_CFLG(GET_XFLG());
	SET_ZFLG(((uae_s32)(val)) == 0);
	SET_NFLG(((uae_s32)(val)) < 0);
	{
		int cycles = 4;
		cycles += 2 * ccnt;
		do_cycles_ce000_internal(cycles);
	}
	m68k_dreg(regs, dstreg) = (val);
	m68k_incpci(2);
	return;
}
/* 8+ (1/0) */
/* 2 0,0   */

/* RORQ.L #<data>,Dn */
void REGPARAM2 op_e098_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 69;
	CurrentInstrCycles = 8;  
	uae_u32 cnt = srcreg;
	uae_s32 data = m68k_dreg(regs, dstreg);
	uae_u32 val = data;
	CLEAR_CZNV();
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		SET_NFLG(val & 0x8000);
		SET_ZFLG(!(val & 0xffff));
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	int ccnt = cnt & 63;
	cnt &= 63;
	{
		uae_u32 hival;
		cnt &= 31;
		hival = val << (32 - cnt);
		val >>= cnt;
		val |= hival;
		val &= 0xffffffff;
		SET_CFLG((val & 0x80000000) >> 31);
	}
	SET_ZFLG(((uae_s32)(val)) == 0);
	SET_NFLG(((uae_s32)(val)) < 0);
	{
		int cycles = 4;
		cycles += 2 * ccnt;
		do_cycles_ce000_internal(cycles);
	}
	m68k_dreg(regs, dstreg) = (val);
	m68k_incpci(2);
	return;
}
/* 8+ (1/0) */
/* 2 0,0   */

/* ASR.L Dn,Dn */
void REGPARAM2 op_e0a0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 64;
	CurrentInstrCycles = 8;  
	uae_s32 cnt = m68k_dreg(regs, srcreg);
	uae_s32 data = m68k_dreg(regs, dstreg);
	uae_u32 val = data;
	CLEAR_CZNV();
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		SET_NFLG(val & 0x8000);
		SET_ZFLG(!(val & 0xffff));
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	uae_u32 sign = (0x80000000 & val) >> 31;
	int ccnt = cnt & 63;
	cnt &= 63;
	if (cnt >= 32) {
		val = 0xffffffff & (uae_u32)(0 - sign);
		SET_CFLG(sign);
		COPY_CARRY();
	} else if (cnt > 0) {
		val >>= cnt - 1;
		SET_CFLG(val & 1);
		COPY_CARRY();
		val >>= 1;
		val |= (0xffffffff << (32 - cnt)) & (uae_u32)(0 - sign);
		val &= 0xffffffff;
	}
	SET_ZFLG(((uae_s32)(val)) == 0);
	SET_NFLG(((uae_s32)(val)) < 0);
	{
		int cycles = 4;
		cycles += 2 * ccnt;
		do_cycles_ce000_internal(cycles);
	}
	m68k_dreg(regs, dstreg) = (val);
	m68k_incpci(2);
	return;
}
/* 8+ (1/0) */
/* 2 0,0   */

/* LSR.L Dn,Dn */
void REGPARAM2 op_e0a8_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 66;
	CurrentInstrCycles = 8;  
	uae_s32 cnt = m68k_dreg(regs, srcreg);
	uae_s32 data = m68k_dreg(regs, dstreg);
	uae_u32 val = data;
	CLEAR_CZNV();
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		SET_NFLG(val & 0x8000);
		SET_ZFLG(!(val & 0xffff));
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	int ccnt = cnt & 63;
	cnt &= 63;
	if (cnt >= 32) {
		SET_CFLG((cnt == 32) & (val >> 31));
		COPY_CARRY();
		val = 0;
	} else if (cnt > 0) {
		val >>= cnt - 1;
		SET_CFLG(val & 1);
		COPY_CARRY();
		val >>= 1;
	}
	SET_ZFLG(((uae_s32)(val)) == 0);
	SET_NFLG(((uae_s32)(val)) < 0);
	{
		int cycles = 4;
		cycles += 2 * ccnt;
		do_cycles_ce000_internal(cycles);
	}
	m68k_dreg(regs, dstreg) = (val);
	m68k_incpci(2);
	return;
}
/* 8+ (1/0) */
/* 2 0,0   */

/* ROXR.L Dn,Dn */
void REGPARAM2 op_e0b0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 71;
	CurrentInstrCycles = 8;  
	uae_s32 cnt = m68k_dreg(regs, srcreg);
	uae_s32 data = m68k_dreg(regs, dstreg);
	uae_u32 val = data;
	CLEAR_CZNV();
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		SET_NFLG(val & 0x8000);
		SET_ZFLG(!(val & 0xffff));
		SET_CFLG(GET_XFLG());
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	int ccnt = cnt & 63;
	cnt &= 63;
	if (cnt >= 33) cnt -= 33;
	if (cnt > 0) {
		cnt--;
		{
			uae_u32 carry;
			uae_u32 hival = (val << 1) | GET_XFLG();
			hival <<= (31 - cnt);
			val >>= cnt;
			carry = val & 1;
			val >>= 1;
			val |= hival;
			SET_XFLG(carry);
			val &= 0xffffffff;
		}
	}
	SET_CFLG(GET_XFLG());
	SET_ZFLG(((uae_s32)(val)) == 0);
	SET_NFLG(((uae_s32)(val)) < 0);
	{
		int cycles = 4;
		cycles += 2 * ccnt;
		do_cycles_ce000_internal(cycles);
	}
	m68k_dreg(regs, dstreg) = (val);
	m68k_incpci(2);
	return;
}
/* 8+ (1/0) */
/* 2 0,0   */

/* ROR.L Dn,Dn */
void REGPARAM2 op_e0b8_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 69;
	CurrentInstrCycles = 8;  
	uae_s32 cnt = m68k_dreg(regs, srcreg);
	uae_s32 data = m68k_dreg(regs, dstreg);
	uae_u32 val = data;
	CLEAR_CZNV();
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		SET_NFLG(val & 0x8000);
		SET_ZFLG(!(val & 0xffff));
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	int ccnt = cnt & 63;
	cnt &= 63;
	if (cnt > 0) {
		uae_u32 hival;
		cnt &= 31;
		hival = val << (32 - cnt);
		val >>= cnt;
		val |= hival;
		val &= 0xffffffff;
		SET_CFLG((val & 0x80000000) >> 31);
	}
	SET_ZFLG(((uae_s32)(val)) == 0);
	SET_NFLG(((uae_s32)(val)) < 0);
	{
		int cycles = 4;
		cycles += 2 * ccnt;
		do_cycles_ce000_internal(cycles);
	}
	m68k_dreg(regs, dstreg) = (val);
	m68k_incpci(2);
	return;
}
/* 8+ (1/0) */
/* 2 0,0   */

/* ASRW.W (An) */
void REGPARAM2 op_e0d0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 72;
	CurrentInstrCycles = 12; 
	int loop_mode = regs.loop_mode;
	uaecptr dataa;
	dataa = m68k_areg(regs, srcreg);
	if (dataa & 1) {
		m68k_incpci(2);
		exception3_read_access2(opcode, dataa, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 data = x_get_word(dataa);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dataa + 0, 0x1, 1);
		return;
	}
	uae_u32 val = (uae_u16)data;
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_ce000_prefetch(4);
		if(hardware_bus_error) {
			int pcoffset = 0;
			CLEAR_CZNV();
			SET_CFLG(val & 1);
			SET_ZFLG(!(val >> 1));
			SET_NFLG(val & 0x8000);
			SET_XFLG(GET_CFLG());
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return;
		}
		opcode = regs.ir;
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	uae_u32 sign = 0x8000 & val;
	uae_u32 cflg = val & 1;
	val = (val >> 1) | sign;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	SET_CFLG(cflg);
	COPY_CARRY();
	if(loop_mode & 0xfffe) {
		do_cycles_ce000_internal(loop_mode & 0xfffe);
		loop_mode = 1;
	}
	x_put_word(dataa, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dataa + 0, 0x1, val, 1);
		return;
	}
	if (loop_mode) {
		do_cycles_ce000_internal(2);
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return;
}
/* 12 (2/1) */
/* 2 0,0   */

/* ASRW.W (An)+ */
void REGPARAM2 op_e0d8_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 72;
	CurrentInstrCycles = 12; 
	int loop_mode = regs.loop_mode;
	uaecptr dataa;
	dataa = m68k_areg(regs, srcreg);
	if (dataa & 1) {
		m68k_areg(regs, srcreg) += 2 + 0;
		m68k_incpci(2);
		exception3_read_access2(opcode, dataa, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 data = x_get_word(dataa);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) += 2 + 0;
		exception2_read(opcode, dataa + 0, 0x1, 1);
		return;
	}
	m68k_areg(regs, srcreg) += 2;
	uae_u32 val = (uae_u16)data;
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_ce000_prefetch(4);
		if(hardware_bus_error) {
			int pcoffset = 0;
			CLEAR_CZNV();
			SET_CFLG(val & 1);
			SET_ZFLG(!(val >> 1));
			SET_NFLG(val & 0x8000);
			SET_XFLG(GET_CFLG());
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return;
		}
		opcode = regs.ir;
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	uae_u32 sign = 0x8000 & val;
	uae_u32 cflg = val & 1;
	val = (val >> 1) | sign;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	SET_CFLG(cflg);
	COPY_CARRY();
	if(loop_mode & 0xfffe) {
		do_cycles_ce000_internal(loop_mode & 0xfffe);
		loop_mode = 1;
	}
	x_put_word(dataa, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dataa + 0, 0x1, val, 1);
		return;
	}
	if (loop_mode) {
		do_cycles_ce000_internal(2);
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return;
}
/* 12 (2/1) */
/* 2 0,0   */

/* ASRW.W -(An) */
void REGPARAM2 op_e0e0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 72;
	CurrentInstrCycles = 14; 
	int loop_mode = regs.loop_mode;
	uaecptr dataa;
	dataa = m68k_areg(regs, srcreg) - 2;
	do_cycles_ce000_internal(2);
	if (dataa & 1) {
		m68k_areg(regs, srcreg) = dataa;
		m68k_incpci(2);
		exception3_read_access2(opcode, dataa, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 data = x_get_word(dataa);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = dataa;
		exception2_read(opcode, dataa + 0, 0x1, 1);
		return;
	}
	m68k_areg(regs, srcreg) = dataa;
	uae_u32 val = (uae_u16)data;
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_ce000_prefetch(4);
		if(hardware_bus_error) {
			int pcoffset = 0;
			CLEAR_CZNV();
			SET_CFLG(val & 1);
			SET_ZFLG(!(val >> 1));
			SET_NFLG(val & 0x8000);
			SET_XFLG(GET_CFLG());
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return;
		}
		opcode = regs.ir;
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	uae_u32 sign = 0x8000 & val;
	uae_u32 cflg = val & 1;
	val = (val >> 1) | sign;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	SET_CFLG(cflg);
	COPY_CARRY();
	if(loop_mode & 0xfffe) {
		do_cycles_ce000_internal(loop_mode & 0xfffe);
		loop_mode = 1;
	}
	x_put_word(dataa, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dataa + 0, 0x1, val, 1);
		return;
	}
	if (loop_mode) {
		do_cycles_ce000_internal(2);
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return;
}
/* 14 (2/1) */
/* 2 0,0   */

/* ASRW.W (d16,An) */
void REGPARAM2 op_e0e8_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 72;
	CurrentInstrCycles = 16; 
	uaecptr dataa;
	dataa = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (dataa & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dataa, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 data = x_get_word(dataa);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dataa + 0, 0x1, 1);
		return;
	}
	uae_u32 val = (uae_u16)data;
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();
		SET_CFLG(val & 1);
		SET_ZFLG(!(val >> 1));
		SET_NFLG(val & 0x8000);
		SET_XFLG(GET_CFLG());
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	uae_u32 sign = 0x8000 & val;
	uae_u32 cflg = val & 1;
	val = (val >> 1) | sign;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	SET_CFLG(cflg);
	COPY_CARRY();
	x_put_word(dataa, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dataa + 0, 0x1, val, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* ASRW.W (d8,An,Xn) */
void REGPARAM2 op_e0f0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 72;
	CurrentInstrCycles = 18; 
	uaecptr dataa;
	do_cycles_ce000_internal(2);
	dataa = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (dataa & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dataa, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 data = x_get_word(dataa);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dataa + 0, 0x1, 1);
		return;
	}
	uae_u32 val = (uae_u16)data;
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();
		SET_CFLG(val & 1);
		SET_ZFLG(!(val >> 1));
		SET_NFLG(val & 0x8000);
		SET_XFLG(GET_CFLG());
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	uae_u32 sign = 0x8000 & val;
	uae_u32 cflg = val & 1;
	val = (val >> 1) | sign;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	SET_CFLG(cflg);
	COPY_CARRY();
	x_put_word(dataa, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dataa + 0, 0x1, val, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 18 (3/1) */
/* 4 4,0   */

/* ASRW.W (xxx).W */
void REGPARAM2 op_e0f8_13_ff(uae_u32 opcode)
{
	OpcodeFamily = 72;
	CurrentInstrCycles = 16; 
	uaecptr dataa;
	dataa = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	if (dataa & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, dataa, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 data = x_get_word(dataa);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dataa + 0, 0x1, 1);
		return;
	}
	uae_u32 val = (uae_u16)data;
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();
		SET_CFLG(val & 1);
		SET_ZFLG(!(val >> 1));
		SET_NFLG(val & 0x8000);
		SET_XFLG(GET_CFLG());
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	uae_u32 sign = 0x8000 & val;
	uae_u32 cflg = val & 1;
	val = (val >> 1) | sign;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	SET_CFLG(cflg);
	COPY_CARRY();
	x_put_word(dataa, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dataa + 0, 0x1, val, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* ASRW.W (xxx).L */
void REGPARAM2 op_e0f9_13_ff(uae_u32 opcode)
{
	OpcodeFamily = 72;
	CurrentInstrCycles = 20; 
	uaecptr dataa;
	dataa = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	dataa |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	if (dataa & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, dataa, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 data = x_get_word(dataa);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dataa + 0, 0x1, 1);
		return;
	}
	uae_u32 val = (uae_u16)data;
	regs.ir = regs.irc;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();
		SET_CFLG(val & 1);
		SET_ZFLG(!(val >> 1));
		SET_NFLG(val & 0x8000);
		SET_XFLG(GET_CFLG());
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	opcode = regs.ir;
	uae_u32 sign = 0x8000 & val;
	uae_u32 cflg = val & 1;
	val = (val >> 1) | sign;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	SET_CFLG(cflg);
	COPY_CARRY();
	x_put_word(dataa, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dataa + 0, 0x1, val, 1);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 20 (4/1) */
/* 6 0,0   */

/* ASLQ.B #<data>,Dn */
void REGPARAM2 op_e100_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 65;
	CurrentInstrCycles = 6;  
	uae_u32 cnt = srcreg;
	uae_s8 data = m68k_dreg(regs, dstreg);
	uae_u32 val = (uae_u8)data;
	CLEAR_CZNV();
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		SET_ZFLG(!(val & 0xff));
		SET_NFLG(val & 0x80);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	int ccnt = cnt & 63;
	cnt &= 63;
	if (cnt >= 8) {
		SET_VFLG(val != 0);
		SET_CFLG(cnt == 8 ? val & 1 : 0);
		COPY_CARRY();
		val = 0;
	} else {
		uae_u32 mask = (0xff << (7 - cnt)) & 0xff;
		SET_VFLG((val & mask) != mask && (val & mask) != 0);
		val <<= cnt - 1;
		SET_CFLG((val & 0x80) >> 7);
		COPY_CARRY();
		val <<= 1;
		val &= 0xff;
	}
	SET_ZFLG(((uae_s8)(val)) == 0);
	SET_NFLG(((uae_s8)(val)) < 0);
	{
		int cycles = 2;
		cycles += 2 * ccnt;
		do_cycles_ce000_internal(cycles);
	}
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((val) & 0xff);
	m68k_incpci(2);
	return;
}
/* 6+ (1/0) */
/* 2 0,0   */

/* LSLQ.B #<data>,Dn */
void REGPARAM2 op_e108_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 67;
	CurrentInstrCycles = 6;  
	uae_u32 cnt = srcreg;
	uae_s8 data = m68k_dreg(regs, dstreg);
	uae_u32 val = (uae_u8)data;
	CLEAR_CZNV();
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		SET_ZFLG(!(val & 0xff));
		SET_NFLG(val & 0x80);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	int ccnt = cnt & 63;
	cnt &= 63;
	if (cnt >= 8) {
		SET_CFLG(cnt == 8 ? val & 1 : 0);
		COPY_CARRY();
		val = 0;
	} else {
		val <<= (cnt - 1);
		SET_CFLG((val & 0x80) >> 7);
		COPY_CARRY();
		val <<= 1;
		val &= 0xff;
	}
	SET_ZFLG(((uae_s8)(val)) == 0);
	SET_NFLG(((uae_s8)(val)) < 0);
	{
		int cycles = 2;
		cycles += 2 * ccnt;
		do_cycles_ce000_internal(cycles);
	}
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((val) & 0xff);
	m68k_incpci(2);
	return;
}
/* 6+ (1/0) */
/* 2 0,0   */

/* ROXLQ.B #<data>,Dn */
void REGPARAM2 op_e110_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 70;
	CurrentInstrCycles = 6;  
	uae_u32 cnt = srcreg;
	uae_s8 data = m68k_dreg(regs, dstreg);
	uae_u32 val = (uae_u8)data;
	CLEAR_CZNV();
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		SET_ZFLG(!(val & 0xff));
		SET_NFLG(val & 0x80);
		SET_CFLG(GET_XFLG());
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	int ccnt = cnt & 63;
	cnt &= 63;
	{
		cnt--;
		{
			uae_u32 carry;
			uae_u32 loval = val >> (7 - cnt);
			carry = loval & 1;
			val = (((val << 1) | GET_XFLG()) << cnt) | (loval >> 1);
			SET_XFLG(carry);
			val &= 0xff;
		}
	}
	SET_CFLG(GET_XFLG());
	SET_ZFLG(((uae_s8)(val)) == 0);
	SET_NFLG(((uae_s8)(val)) < 0);
	{
		int cycles = 2;
		cycles += 2 * ccnt;
		do_cycles_ce000_internal(cycles);
	}
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((val) & 0xff);
	m68k_incpci(2);
	return;
}
/* 6+ (1/0) */
/* 2 0,0   */

/* ROLQ.B #<data>,Dn */
void REGPARAM2 op_e118_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 68;
	CurrentInstrCycles = 6;  
	uae_u32 cnt = srcreg;
	uae_s8 data = m68k_dreg(regs, dstreg);
	uae_u32 val = (uae_u8)data;
	CLEAR_CZNV();
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		SET_ZFLG(!(val & 0xff));
		SET_NFLG(val & 0x80);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	int ccnt = cnt & 63;
	cnt &= 63;
	{
		uae_u32 loval;
		cnt &= 7;
		loval = val >> (8 - cnt);
		val <<= cnt;
		val |= loval;
		val &= 0xff;
		SET_CFLG(val & 1);
	}
	SET_ZFLG(((uae_s8)(val)) == 0);
	SET_NFLG(((uae_s8)(val)) < 0);
	{
		int cycles = 2;
		cycles += 2 * ccnt;
		do_cycles_ce000_internal(cycles);
	}
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((val) & 0xff);
	m68k_incpci(2);
	return;
}
/* 6+ (1/0) */
/* 2 0,0   */

/* ASL.B Dn,Dn */
void REGPARAM2 op_e120_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 65;
	CurrentInstrCycles = 6;  
	uae_s8 cnt = m68k_dreg(regs, srcreg);
	uae_s8 data = m68k_dreg(regs, dstreg);
	uae_u32 val = (uae_u8)data;
	CLEAR_CZNV();
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		SET_ZFLG(!(val & 0xff));
		SET_NFLG(val & 0x80);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	int ccnt = cnt & 63;
	cnt &= 63;
	if (cnt >= 8) {
		SET_VFLG(val != 0);
		SET_CFLG(cnt == 8 ? val & 1 : 0);
		COPY_CARRY();
		val = 0;
	} else if (cnt > 0) {
		uae_u32 mask = (0xff << (7 - cnt)) & 0xff;
		SET_VFLG((val & mask) != mask && (val & mask) != 0);
		val <<= cnt - 1;
		SET_CFLG((val & 0x80) >> 7);
		COPY_CARRY();
		val <<= 1;
		val &= 0xff;
	}
	SET_ZFLG(((uae_s8)(val)) == 0);
	SET_NFLG(((uae_s8)(val)) < 0);
	{
		int cycles = 2;
		cycles += 2 * ccnt;
		do_cycles_ce000_internal(cycles);
	}
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((val) & 0xff);
	m68k_incpci(2);
	return;
}
/* 6+ (1/0) */
/* 2 0,0   */

/* LSL.B Dn,Dn */
void REGPARAM2 op_e128_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 67;
	CurrentInstrCycles = 6;  
	uae_s8 cnt = m68k_dreg(regs, srcreg);
	uae_s8 data = m68k_dreg(regs, dstreg);
	uae_u32 val = (uae_u8)data;
	CLEAR_CZNV();
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		SET_ZFLG(!(val & 0xff));
		SET_NFLG(val & 0x80);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	int ccnt = cnt & 63;
	cnt &= 63;
	if (cnt >= 8) {
		SET_CFLG(cnt == 8 ? val & 1 : 0);
		COPY_CARRY();
		val = 0;
	} else if (cnt > 0) {
		val <<= (cnt - 1);
		SET_CFLG((val & 0x80) >> 7);
		COPY_CARRY();
		val <<= 1;
		val &= 0xff;
	}
	SET_ZFLG(((uae_s8)(val)) == 0);
	SET_NFLG(((uae_s8)(val)) < 0);
	{
		int cycles = 2;
		cycles += 2 * ccnt;
		do_cycles_ce000_internal(cycles);
	}
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((val) & 0xff);
	m68k_incpci(2);
	return;
}
/* 6+ (1/0) */
/* 2 0,0   */

/* ROXL.B Dn,Dn */
void REGPARAM2 op_e130_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 70;
	CurrentInstrCycles = 6;  
	uae_s8 cnt = m68k_dreg(regs, srcreg);
	uae_s8 data = m68k_dreg(regs, dstreg);
	uae_u32 val = (uae_u8)data;
	CLEAR_CZNV();
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		SET_ZFLG(!(val & 0xff));
		SET_NFLG(val & 0x80);
		SET_CFLG(GET_XFLG());
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	int ccnt = cnt & 63;
	cnt &= 63;
	if (cnt >= 36) cnt -= 36;
	if (cnt >= 18) cnt -= 18;
	if (cnt >= 9) cnt -= 9;
	if (cnt > 0) {
		cnt--;
		{
			uae_u32 carry;
			uae_u32 loval = val >> (7 - cnt);
			carry = loval & 1;
			val = (((val << 1) | GET_XFLG()) << cnt) | (loval >> 1);
			SET_XFLG(carry);
			val &= 0xff;
		}
	}
	SET_CFLG(GET_XFLG());
	SET_ZFLG(((uae_s8)(val)) == 0);
	SET_NFLG(((uae_s8)(val)) < 0);
	{
		int cycles = 2;
		cycles += 2 * ccnt;
		do_cycles_ce000_internal(cycles);
	}
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((val) & 0xff);
	m68k_incpci(2);
	return;
}
/* 6+ (1/0) */
/* 2 0,0   */

/* ROL.B Dn,Dn */
void REGPARAM2 op_e138_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 68;
	CurrentInstrCycles = 6;  
	uae_s8 cnt = m68k_dreg(regs, srcreg);
	uae_s8 data = m68k_dreg(regs, dstreg);
	uae_u32 val = (uae_u8)data;
	CLEAR_CZNV();
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		SET_ZFLG(!(val & 0xff));
		SET_NFLG(val & 0x80);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	int ccnt = cnt & 63;
	cnt &= 63;
	if (cnt > 0) {
		uae_u32 loval;
		cnt &= 7;
		loval = val >> (8 - cnt);
		val <<= cnt;
		val |= loval;
		val &= 0xff;
		SET_CFLG(val & 1);
	}
	SET_ZFLG(((uae_s8)(val)) == 0);
	SET_NFLG(((uae_s8)(val)) < 0);
	{
		int cycles = 2;
		cycles += 2 * ccnt;
		do_cycles_ce000_internal(cycles);
	}
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((val) & 0xff);
	m68k_incpci(2);
	return;
}
/* 6+ (1/0) */
/* 2 0,0   */

/* ASLQ.W #<data>,Dn */
void REGPARAM2 op_e140_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 65;
	CurrentInstrCycles = 6;  
	uae_u32 cnt = srcreg;
	uae_s16 data = m68k_dreg(regs, dstreg);
	uae_u32 val = (uae_u16)data;
	CLEAR_CZNV();
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		SET_ZFLG(!(val & 0xffff));
		SET_NFLG(val & 0x8000);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	int ccnt = cnt & 63;
	cnt &= 63;
	if (cnt >= 16) {
		SET_VFLG(val != 0);
		SET_CFLG(cnt == 16 ? val & 1 : 0);
		COPY_CARRY();
		val = 0;
	} else {
		uae_u32 mask = (0xffff << (15 - cnt)) & 0xffff;
		SET_VFLG((val & mask) != mask && (val & mask) != 0);
		val <<= cnt - 1;
		SET_CFLG((val & 0x8000) >> 15);
		COPY_CARRY();
		val <<= 1;
		val &= 0xffff;
	}
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	{
		int cycles = 2;
		cycles += 2 * ccnt;
		do_cycles_ce000_internal(cycles);
	}
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((val) & 0xffff);
	m68k_incpci(2);
	return;
}
/* 6+ (1/0) */
/* 2 0,0   */

/* LSLQ.W #<data>,Dn */
void REGPARAM2 op_e148_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 67;
	CurrentInstrCycles = 6;  
	uae_u32 cnt = srcreg;
	uae_s16 data = m68k_dreg(regs, dstreg);
	uae_u32 val = (uae_u16)data;
	CLEAR_CZNV();
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		SET_ZFLG(!(val & 0xffff));
		SET_NFLG(val & 0x8000);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	int ccnt = cnt & 63;
	cnt &= 63;
	if (cnt >= 16) {
		SET_CFLG(cnt == 16 ? val & 1 : 0);
		COPY_CARRY();
		val = 0;
	} else {
		val <<= (cnt - 1);
		SET_CFLG((val & 0x8000) >> 15);
		COPY_CARRY();
		val <<= 1;
		val &= 0xffff;
	}
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	{
		int cycles = 2;
		cycles += 2 * ccnt;
		do_cycles_ce000_internal(cycles);
	}
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((val) & 0xffff);
	m68k_incpci(2);
	return;
}
/* 6+ (1/0) */
/* 2 0,0   */

/* ROXLQ.W #<data>,Dn */
void REGPARAM2 op_e150_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 70;
	CurrentInstrCycles = 6;  
	uae_u32 cnt = srcreg;
	uae_s16 data = m68k_dreg(regs, dstreg);
	uae_u32 val = (uae_u16)data;
	CLEAR_CZNV();
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		SET_ZFLG(!(val & 0xffff));
		SET_NFLG(val & 0x8000);
		SET_CFLG(GET_XFLG());
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	int ccnt = cnt & 63;
	cnt &= 63;
	{
		cnt--;
		{
			uae_u32 carry;
			uae_u32 loval = val >> (15 - cnt);
			carry = loval & 1;
			val = (((val << 1) | GET_XFLG()) << cnt) | (loval >> 1);
			SET_XFLG(carry);
			val &= 0xffff;
		}
	}
	SET_CFLG(GET_XFLG());
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	{
		int cycles = 2;
		cycles += 2 * ccnt;
		do_cycles_ce000_internal(cycles);
	}
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((val) & 0xffff);
	m68k_incpci(2);
	return;
}
/* 6+ (1/0) */
/* 2 0,0   */

/* ROLQ.W #<data>,Dn */
void REGPARAM2 op_e158_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 68;
	CurrentInstrCycles = 6;  
	uae_u32 cnt = srcreg;
	uae_s16 data = m68k_dreg(regs, dstreg);
	uae_u32 val = (uae_u16)data;
	CLEAR_CZNV();
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		SET_ZFLG(!(val & 0xffff));
		SET_NFLG(val & 0x8000);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	int ccnt = cnt & 63;
	cnt &= 63;
	{
		uae_u32 loval;
		cnt &= 15;
		loval = val >> (16 - cnt);
		val <<= cnt;
		val |= loval;
		val &= 0xffff;
		SET_CFLG(val & 1);
	}
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	{
		int cycles = 2;
		cycles += 2 * ccnt;
		do_cycles_ce000_internal(cycles);
	}
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((val) & 0xffff);
	m68k_incpci(2);
	return;
}
/* 6+ (1/0) */
/* 2 0,0   */

/* ASL.W Dn,Dn */
void REGPARAM2 op_e160_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 65;
	CurrentInstrCycles = 6;  
	uae_s16 cnt = m68k_dreg(regs, srcreg);
	uae_s16 data = m68k_dreg(regs, dstreg);
	uae_u32 val = (uae_u16)data;
	CLEAR_CZNV();
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		SET_ZFLG(!(val & 0xffff));
		SET_NFLG(val & 0x8000);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	int ccnt = cnt & 63;
	cnt &= 63;
	if (cnt >= 16) {
		SET_VFLG(val != 0);
		SET_CFLG(cnt == 16 ? val & 1 : 0);
		COPY_CARRY();
		val = 0;
	} else if (cnt > 0) {
		uae_u32 mask = (0xffff << (15 - cnt)) & 0xffff;
		SET_VFLG((val & mask) != mask && (val & mask) != 0);
		val <<= cnt - 1;
		SET_CFLG((val & 0x8000) >> 15);
		COPY_CARRY();
		val <<= 1;
		val &= 0xffff;
	}
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	{
		int cycles = 2;
		cycles += 2 * ccnt;
		do_cycles_ce000_internal(cycles);
	}
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((val) & 0xffff);
	m68k_incpci(2);
	return;
}
/* 6+ (1/0) */
/* 2 0,0   */

/* LSL.W Dn,Dn */
void REGPARAM2 op_e168_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 67;
	CurrentInstrCycles = 6;  
	uae_s16 cnt = m68k_dreg(regs, srcreg);
	uae_s16 data = m68k_dreg(regs, dstreg);
	uae_u32 val = (uae_u16)data;
	CLEAR_CZNV();
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		SET_ZFLG(!(val & 0xffff));
		SET_NFLG(val & 0x8000);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	int ccnt = cnt & 63;
	cnt &= 63;
	if (cnt >= 16) {
		SET_CFLG(cnt == 16 ? val & 1 : 0);
		COPY_CARRY();
		val = 0;
	} else if (cnt > 0) {
		val <<= (cnt - 1);
		SET_CFLG((val & 0x8000) >> 15);
		COPY_CARRY();
		val <<= 1;
		val &= 0xffff;
	}
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	{
		int cycles = 2;
		cycles += 2 * ccnt;
		do_cycles_ce000_internal(cycles);
	}
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((val) & 0xffff);
	m68k_incpci(2);
	return;
}
/* 6+ (1/0) */
/* 2 0,0   */

/* ROXL.W Dn,Dn */
void REGPARAM2 op_e170_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 70;
	CurrentInstrCycles = 6;  
	uae_s16 cnt = m68k_dreg(regs, srcreg);
	uae_s16 data = m68k_dreg(regs, dstreg);
	uae_u32 val = (uae_u16)data;
	CLEAR_CZNV();
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		SET_ZFLG(!(val & 0xffff));
		SET_NFLG(val & 0x8000);
		SET_CFLG(GET_XFLG());
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	int ccnt = cnt & 63;
	cnt &= 63;
	if (cnt >= 34) cnt -= 34;
	if (cnt >= 17) cnt -= 17;
	if (cnt > 0) {
		cnt--;
		{
			uae_u32 carry;
			uae_u32 loval = val >> (15 - cnt);
			carry = loval & 1;
			val = (((val << 1) | GET_XFLG()) << cnt) | (loval >> 1);
			SET_XFLG(carry);
			val &= 0xffff;
		}
	}
	SET_CFLG(GET_XFLG());
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	{
		int cycles = 2;
		cycles += 2 * ccnt;
		do_cycles_ce000_internal(cycles);
	}
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((val) & 0xffff);
	m68k_incpci(2);
	return;
}
/* 6+ (1/0) */
/* 2 0,0   */

/* ROL.W Dn,Dn */
void REGPARAM2 op_e178_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 68;
	CurrentInstrCycles = 6;  
	uae_s16 cnt = m68k_dreg(regs, srcreg);
	uae_s16 data = m68k_dreg(regs, dstreg);
	uae_u32 val = (uae_u16)data;
	CLEAR_CZNV();
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		SET_ZFLG(!(val & 0xffff));
		SET_NFLG(val & 0x8000);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	int ccnt = cnt & 63;
	cnt &= 63;
	if (cnt > 0) {
		uae_u32 loval;
		cnt &= 15;
		loval = val >> (16 - cnt);
		val <<= cnt;
		val |= loval;
		val &= 0xffff;
		SET_CFLG(val & 1);
	}
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	{
		int cycles = 2;
		cycles += 2 * ccnt;
		do_cycles_ce000_internal(cycles);
	}
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((val) & 0xffff);
	m68k_incpci(2);
	return;
}
/* 6+ (1/0) */
/* 2 0,0   */

/* ASLQ.L #<data>,Dn */
void REGPARAM2 op_e180_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 65;
	CurrentInstrCycles = 8;  
	uae_u32 cnt = srcreg;
	uae_s32 data = m68k_dreg(regs, dstreg);
	uae_u32 val = data;
	CLEAR_CZNV();
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		SET_NFLG(val & 0x8000);
		SET_ZFLG(!(val & 0xffff));
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	int ccnt = cnt & 63;
	cnt &= 63;
	if (cnt >= 32) {
		SET_VFLG(val != 0);
		SET_CFLG(cnt == 32 ? val & 1 : 0);
		COPY_CARRY();
		val = 0;
	} else {
		uae_u32 mask = (0xffffffff << (31 - cnt)) & 0xffffffff;
		SET_VFLG((val & mask) != mask && (val & mask) != 0);
		val <<= cnt - 1;
		SET_CFLG((val & 0x80000000) >> 31);
		COPY_CARRY();
		val <<= 1;
		val &= 0xffffffff;
	}
	SET_ZFLG(((uae_s32)(val)) == 0);
	SET_NFLG(((uae_s32)(val)) < 0);
	{
		int cycles = 4;
		cycles += 2 * ccnt;
		do_cycles_ce000_internal(cycles);
	}
	m68k_dreg(regs, dstreg) = (val);
	m68k_incpci(2);
	return;
}
/* 8+ (1/0) */
/* 2 0,0   */

/* LSLQ.L #<data>,Dn */
void REGPARAM2 op_e188_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 67;
	CurrentInstrCycles = 8;  
	uae_u32 cnt = srcreg;
	uae_s32 data = m68k_dreg(regs, dstreg);
	uae_u32 val = data;
	CLEAR_CZNV();
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		SET_NFLG(val & 0x8000);
		SET_ZFLG(!(val & 0xffff));
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	int ccnt = cnt & 63;
	cnt &= 63;
	if (cnt >= 32) {
		SET_CFLG(cnt == 32 ? val & 1 : 0);
		COPY_CARRY();
		val = 0;
	} else {
		val <<= (cnt - 1);
		SET_CFLG((val & 0x80000000) >> 31);
		COPY_CARRY();
		val <<= 1;
		val &= 0xffffffff;
	}
	SET_ZFLG(((uae_s32)(val)) == 0);
	SET_NFLG(((uae_s32)(val)) < 0);
	{
		int cycles = 4;
		cycles += 2 * ccnt;
		do_cycles_ce000_internal(cycles);
	}
	m68k_dreg(regs, dstreg) = (val);
	m68k_incpci(2);
	return;
}
/* 8+ (1/0) */
/* 2 0,0   */

/* ROXLQ.L #<data>,Dn */
void REGPARAM2 op_e190_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 70;
	CurrentInstrCycles = 8;  
	uae_u32 cnt = srcreg;
	uae_s32 data = m68k_dreg(regs, dstreg);
	uae_u32 val = data;
	CLEAR_CZNV();
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		SET_NFLG(val & 0x8000);
		SET_ZFLG(!(val & 0xffff));
		SET_CFLG(GET_XFLG());
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	int ccnt = cnt & 63;
	cnt &= 63;
	{
		cnt--;
		{
			uae_u32 carry;
			uae_u32 loval = val >> (31 - cnt);
			carry = loval & 1;
			val = (((val << 1) | GET_XFLG()) << cnt) | (loval >> 1);
			SET_XFLG(carry);
			val &= 0xffffffff;
		}
	}
	SET_CFLG(GET_XFLG());
	SET_ZFLG(((uae_s32)(val)) == 0);
	SET_NFLG(((uae_s32)(val)) < 0);
	{
		int cycles = 4;
		cycles += 2 * ccnt;
		do_cycles_ce000_internal(cycles);
	}
	m68k_dreg(regs, dstreg) = (val);
	m68k_incpci(2);
	return;
}
/* 8+ (1/0) */
/* 2 0,0   */

/* ROLQ.L #<data>,Dn */
void REGPARAM2 op_e198_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 68;
	CurrentInstrCycles = 8;  
	uae_u32 cnt = srcreg;
	uae_s32 data = m68k_dreg(regs, dstreg);
	uae_u32 val = data;
	CLEAR_CZNV();
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		SET_NFLG(val & 0x8000);
		SET_ZFLG(!(val & 0xffff));
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	int ccnt = cnt & 63;
	cnt &= 63;
	{
		uae_u32 loval;
		cnt &= 31;
		loval = val >> (32 - cnt);
		val <<= cnt;
		val |= loval;
		val &= 0xffffffff;
		SET_CFLG(val & 1);
	}
	SET_ZFLG(((uae_s32)(val)) == 0);
	SET_NFLG(((uae_s32)(val)) < 0);
	{
		int cycles = 4;
		cycles += 2 * ccnt;
		do_cycles_ce000_internal(cycles);
	}
	m68k_dreg(regs, dstreg) = (val);
	m68k_incpci(2);
	return;
}
/* 8+ (1/0) */
/* 2 0,0   */

/* ASL.L Dn,Dn */
void REGPARAM2 op_e1a0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 65;
	CurrentInstrCycles = 8;  
	uae_s32 cnt = m68k_dreg(regs, srcreg);
	uae_s32 data = m68k_dreg(regs, dstreg);
	uae_u32 val = data;
	CLEAR_CZNV();
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		SET_NFLG(val & 0x8000);
		SET_ZFLG(!(val & 0xffff));
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	int ccnt = cnt & 63;
	cnt &= 63;
	if (cnt >= 32) {
		SET_VFLG(val != 0);
		SET_CFLG(cnt == 32 ? val & 1 : 0);
		COPY_CARRY();
		val = 0;
	} else if (cnt > 0) {
		uae_u32 mask = (0xffffffff << (31 - cnt)) & 0xffffffff;
		SET_VFLG((val & mask) != mask && (val & mask) != 0);
		val <<= cnt - 1;
		SET_CFLG((val & 0x80000000) >> 31);
		COPY_CARRY();
		val <<= 1;
		val &= 0xffffffff;
	}
	SET_ZFLG(((uae_s32)(val)) == 0);
	SET_NFLG(((uae_s32)(val)) < 0);
	{
		int cycles = 4;
		cycles += 2 * ccnt;
		do_cycles_ce000_internal(cycles);
	}
	m68k_dreg(regs, dstreg) = (val);
	m68k_incpci(2);
	return;
}
/* 8+ (1/0) */
/* 2 0,0   */

/* LSL.L Dn,Dn */
void REGPARAM2 op_e1a8_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 67;
	CurrentInstrCycles = 8;  
	uae_s32 cnt = m68k_dreg(regs, srcreg);
	uae_s32 data = m68k_dreg(regs, dstreg);
	uae_u32 val = data;
	CLEAR_CZNV();
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		SET_NFLG(val & 0x8000);
		SET_ZFLG(!(val & 0xffff));
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	int ccnt = cnt & 63;
	cnt &= 63;
	if (cnt >= 32) {
		SET_CFLG(cnt == 32 ? val & 1 : 0);
		COPY_CARRY();
		val = 0;
	} else if (cnt > 0) {
		val <<= (cnt - 1);
		SET_CFLG((val & 0x80000000) >> 31);
		COPY_CARRY();
		val <<= 1;
		val &= 0xffffffff;
	}
	SET_ZFLG(((uae_s32)(val)) == 0);
	SET_NFLG(((uae_s32)(val)) < 0);
	{
		int cycles = 4;
		cycles += 2 * ccnt;
		do_cycles_ce000_internal(cycles);
	}
	m68k_dreg(regs, dstreg) = (val);
	m68k_incpci(2);
	return;
}
/* 8+ (1/0) */
/* 2 0,0   */

/* ROXL.L Dn,Dn */
void REGPARAM2 op_e1b0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 70;
	CurrentInstrCycles = 8;  
	uae_s32 cnt = m68k_dreg(regs, srcreg);
	uae_s32 data = m68k_dreg(regs, dstreg);
	uae_u32 val = data;
	CLEAR_CZNV();
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		SET_NFLG(val & 0x8000);
		SET_ZFLG(!(val & 0xffff));
		SET_CFLG(GET_XFLG());
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	int ccnt = cnt & 63;
	cnt &= 63;
	if (cnt >= 33) cnt -= 33;
	if (cnt > 0) {
		cnt--;
		{
			uae_u32 carry;
			uae_u32 loval = val >> (31 - cnt);
			carry = loval & 1;
			val = (((val << 1) | GET_XFLG()) << cnt) | (loval >> 1);
			SET_XFLG(carry);
			val &= 0xffffffff;
		}
	}
	SET_CFLG(GET_XFLG());
	SET_ZFLG(((uae_s32)(val)) == 0);
	SET_NFLG(((uae_s32)(val)) < 0);
	{
		int cycles = 4;
		cycles += 2 * ccnt;
		do_cycles_ce000_internal(cycles);
	}
	m68k_dreg(regs, dstreg) = (val);
	m68k_incpci(2);
	return;
}
/* 8+ (1/0) */
/* 2 0,0   */

/* ROL.L Dn,Dn */
void REGPARAM2 op_e1b8_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 68;
	CurrentInstrCycles = 8;  
	uae_s32 cnt = m68k_dreg(regs, srcreg);
	uae_s32 data = m68k_dreg(regs, dstreg);
	uae_u32 val = data;
	CLEAR_CZNV();
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		SET_NFLG(val & 0x8000);
		SET_ZFLG(!(val & 0xffff));
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	int ccnt = cnt & 63;
	cnt &= 63;
	if (cnt > 0) {
		uae_u32 loval;
		cnt &= 31;
		loval = val >> (32 - cnt);
		val <<= cnt;
		val |= loval;
		val &= 0xffffffff;
		SET_CFLG(val & 1);
	}
	SET_ZFLG(((uae_s32)(val)) == 0);
	SET_NFLG(((uae_s32)(val)) < 0);
	{
		int cycles = 4;
		cycles += 2 * ccnt;
		do_cycles_ce000_internal(cycles);
	}
	m68k_dreg(regs, dstreg) = (val);
	m68k_incpci(2);
	return;
}
/* 8+ (1/0) */
/* 2 0,0   */

/* ASLW.W (An) */
void REGPARAM2 op_e1d0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 73;
	CurrentInstrCycles = 12; 
	int loop_mode = regs.loop_mode;
	uaecptr dataa;
	dataa = m68k_areg(regs, srcreg);
	if (dataa & 1) {
		m68k_incpci(2);
		exception3_read_access2(opcode, dataa, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 data = x_get_word(dataa);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dataa + 0, 0x1, 1);
		return;
	}
	uae_u32 val = (uae_u16)data;
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_ce000_prefetch(4);
		if(hardware_bus_error) {
			int pcoffset = 0;
			CLEAR_CZNV();
			SET_CFLG(val & 0x8000);
			SET_ZFLG(!(val & 0x7fff));
			SET_NFLG(val & 0x4000);
			SET_XFLG(GET_CFLG());
			SET_VFLG((val & 0x8000) != ((val << 1) & 0x8000));
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return;
		}
		opcode = regs.ir;
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	uae_u32 sign = 0x8000 & val;
	uae_u32 sign2;
	val <<= 1;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	sign2 = 0x8000 & val;
	SET_CFLG(sign != 0);
	COPY_CARRY();
	SET_VFLG(GET_VFLG() | (sign2 != sign));
	if(loop_mode & 0xfffe) {
		do_cycles_ce000_internal(loop_mode & 0xfffe);
		loop_mode = 1;
	}
	x_put_word(dataa, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dataa + 0, 0x1, val, 1);
		return;
	}
	if (loop_mode) {
		do_cycles_ce000_internal(2);
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return;
}
/* 12 (2/1) */
/* 2 0,0   */

/* ASLW.W (An)+ */
void REGPARAM2 op_e1d8_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 73;
	CurrentInstrCycles = 12; 
	int loop_mode = regs.loop_mode;
	uaecptr dataa;
	dataa = m68k_areg(regs, srcreg);
	if (dataa & 1) {
		m68k_areg(regs, srcreg) += 2 + 0;
		m68k_incpci(2);
		exception3_read_access2(opcode, dataa, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 data = x_get_word(dataa);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) += 2 + 0;
		exception2_read(opcode, dataa + 0, 0x1, 1);
		return;
	}
	m68k_areg(regs, srcreg) += 2;
	uae_u32 val = (uae_u16)data;
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_ce000_prefetch(4);
		if(hardware_bus_error) {
			int pcoffset = 0;
			CLEAR_CZNV();
			SET_CFLG(val & 0x8000);
			SET_ZFLG(!(val & 0x7fff));
			SET_NFLG(val & 0x4000);
			SET_XFLG(GET_CFLG());
			SET_VFLG((val & 0x8000) != ((val << 1) & 0x8000));
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return;
		}
		opcode = regs.ir;
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	uae_u32 sign = 0x8000 & val;
	uae_u32 sign2;
	val <<= 1;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	sign2 = 0x8000 & val;
	SET_CFLG(sign != 0);
	COPY_CARRY();
	SET_VFLG(GET_VFLG() | (sign2 != sign));
	if(loop_mode & 0xfffe) {
		do_cycles_ce000_internal(loop_mode & 0xfffe);
		loop_mode = 1;
	}
	x_put_word(dataa, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dataa + 0, 0x1, val, 1);
		return;
	}
	if (loop_mode) {
		do_cycles_ce000_internal(2);
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return;
}
/* 12 (2/1) */
/* 2 0,0   */

/* ASLW.W -(An) */
void REGPARAM2 op_e1e0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 73;
	CurrentInstrCycles = 14; 
	int loop_mode = regs.loop_mode;
	uaecptr dataa;
	dataa = m68k_areg(regs, srcreg) - 2;
	do_cycles_ce000_internal(2);
	if (dataa & 1) {
		m68k_areg(regs, srcreg) = dataa;
		m68k_incpci(2);
		exception3_read_access2(opcode, dataa, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 data = x_get_word(dataa);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = dataa;
		exception2_read(opcode, dataa + 0, 0x1, 1);
		return;
	}
	m68k_areg(regs, srcreg) = dataa;
	uae_u32 val = (uae_u16)data;
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_ce000_prefetch(4);
		if(hardware_bus_error) {
			int pcoffset = 0;
			CLEAR_CZNV();
			SET_CFLG(val & 0x8000);
			SET_ZFLG(!(val & 0x7fff));
			SET_NFLG(val & 0x4000);
			SET_XFLG(GET_CFLG());
			SET_VFLG((val & 0x8000) != ((val << 1) & 0x8000));
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return;
		}
		opcode = regs.ir;
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	uae_u32 sign = 0x8000 & val;
	uae_u32 sign2;
	val <<= 1;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	sign2 = 0x8000 & val;
	SET_CFLG(sign != 0);
	COPY_CARRY();
	SET_VFLG(GET_VFLG() | (sign2 != sign));
	if(loop_mode & 0xfffe) {
		do_cycles_ce000_internal(loop_mode & 0xfffe);
		loop_mode = 1;
	}
	x_put_word(dataa, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dataa + 0, 0x1, val, 1);
		return;
	}
	if (loop_mode) {
		do_cycles_ce000_internal(2);
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return;
}
/* 14 (2/1) */
/* 2 0,0   */

/* ASLW.W (d16,An) */
void REGPARAM2 op_e1e8_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 73;
	CurrentInstrCycles = 16; 
	uaecptr dataa;
	dataa = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (dataa & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dataa, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 data = x_get_word(dataa);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dataa + 0, 0x1, 1);
		return;
	}
	uae_u32 val = (uae_u16)data;
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();
		SET_CFLG(val & 0x8000);
		SET_ZFLG(!(val & 0x7fff));
		SET_NFLG(val & 0x4000);
		SET_XFLG(GET_CFLG());
		SET_VFLG((val & 0x8000) != ((val << 1) & 0x8000));
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	uae_u32 sign = 0x8000 & val;
	uae_u32 sign2;
	val <<= 1;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	sign2 = 0x8000 & val;
	SET_CFLG(sign != 0);
	COPY_CARRY();
	SET_VFLG(GET_VFLG() | (sign2 != sign));
	x_put_word(dataa, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dataa + 0, 0x1, val, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* ASLW.W (d8,An,Xn) */
void REGPARAM2 op_e1f0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 73;
	CurrentInstrCycles = 18; 
	uaecptr dataa;
	do_cycles_ce000_internal(2);
	dataa = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (dataa & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dataa, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 data = x_get_word(dataa);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dataa + 0, 0x1, 1);
		return;
	}
	uae_u32 val = (uae_u16)data;
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();
		SET_CFLG(val & 0x8000);
		SET_ZFLG(!(val & 0x7fff));
		SET_NFLG(val & 0x4000);
		SET_XFLG(GET_CFLG());
		SET_VFLG((val & 0x8000) != ((val << 1) & 0x8000));
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	uae_u32 sign = 0x8000 & val;
	uae_u32 sign2;
	val <<= 1;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	sign2 = 0x8000 & val;
	SET_CFLG(sign != 0);
	COPY_CARRY();
	SET_VFLG(GET_VFLG() | (sign2 != sign));
	x_put_word(dataa, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dataa + 0, 0x1, val, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 18 (3/1) */
/* 4 4,0   */

/* ASLW.W (xxx).W */
void REGPARAM2 op_e1f8_13_ff(uae_u32 opcode)
{
	OpcodeFamily = 73;
	CurrentInstrCycles = 16; 
	uaecptr dataa;
	dataa = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	if (dataa & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, dataa, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 data = x_get_word(dataa);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dataa + 0, 0x1, 1);
		return;
	}
	uae_u32 val = (uae_u16)data;
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();
		SET_CFLG(val & 0x8000);
		SET_ZFLG(!(val & 0x7fff));
		SET_NFLG(val & 0x4000);
		SET_XFLG(GET_CFLG());
		SET_VFLG((val & 0x8000) != ((val << 1) & 0x8000));
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	uae_u32 sign = 0x8000 & val;
	uae_u32 sign2;
	val <<= 1;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	sign2 = 0x8000 & val;
	SET_CFLG(sign != 0);
	COPY_CARRY();
	SET_VFLG(GET_VFLG() | (sign2 != sign));
	x_put_word(dataa, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dataa + 0, 0x1, val, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* ASLW.W (xxx).L */
void REGPARAM2 op_e1f9_13_ff(uae_u32 opcode)
{
	OpcodeFamily = 73;
	CurrentInstrCycles = 20; 
	uaecptr dataa;
	dataa = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	dataa |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	if (dataa & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, dataa, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 data = x_get_word(dataa);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dataa + 0, 0x1, 1);
		return;
	}
	uae_u32 val = (uae_u16)data;
	regs.ir = regs.irc;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();
		SET_CFLG(val & 0x8000);
		SET_ZFLG(!(val & 0x7fff));
		SET_NFLG(val & 0x4000);
		SET_XFLG(GET_CFLG());
		SET_VFLG((val & 0x8000) != ((val << 1) & 0x8000));
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	opcode = regs.ir;
	uae_u32 sign = 0x8000 & val;
	uae_u32 sign2;
	val <<= 1;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	sign2 = 0x8000 & val;
	SET_CFLG(sign != 0);
	COPY_CARRY();
	SET_VFLG(GET_VFLG() | (sign2 != sign));
	x_put_word(dataa, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dataa + 0, 0x1, val, 1);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 20 (4/1) */
/* 6 0,0   */

/* LSRW.W (An) */
void REGPARAM2 op_e2d0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 74;
	CurrentInstrCycles = 12; 
	int loop_mode = regs.loop_mode;
	uaecptr dataa;
	dataa = m68k_areg(regs, srcreg);
	if (dataa & 1) {
		m68k_incpci(2);
		exception3_read_access2(opcode, dataa, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 data = x_get_word(dataa);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dataa + 0, 0x1, 1);
		return;
	}
	uae_u32 val = (uae_u16)data;
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_ce000_prefetch(4);
		if(hardware_bus_error) {
			int pcoffset = 0;
			CLEAR_CZNV();
			SET_CFLG(val & 1);
			SET_ZFLG(!(val & 0xfffe));
			SET_NFLG(0);
			SET_XFLG(GET_CFLG());
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return;
		}
		opcode = regs.ir;
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	uae_u32 carry = val & 1;
	val >>= 1;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	SET_CFLG(carry);
	COPY_CARRY();
	if(loop_mode & 0xfffe) {
		do_cycles_ce000_internal(loop_mode & 0xfffe);
		loop_mode = 1;
	}
	x_put_word(dataa, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dataa + 0, 0x1, val, 1);
		return;
	}
	if (loop_mode) {
		do_cycles_ce000_internal(2);
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return;
}
/* 12 (2/1) */
/* 2 0,0   */

/* LSRW.W (An)+ */
void REGPARAM2 op_e2d8_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 74;
	CurrentInstrCycles = 12; 
	int loop_mode = regs.loop_mode;
	uaecptr dataa;
	dataa = m68k_areg(regs, srcreg);
	if (dataa & 1) {
		m68k_areg(regs, srcreg) += 2 + 0;
		m68k_incpci(2);
		exception3_read_access2(opcode, dataa, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 data = x_get_word(dataa);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) += 2 + 0;
		exception2_read(opcode, dataa + 0, 0x1, 1);
		return;
	}
	m68k_areg(regs, srcreg) += 2;
	uae_u32 val = (uae_u16)data;
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_ce000_prefetch(4);
		if(hardware_bus_error) {
			int pcoffset = 0;
			CLEAR_CZNV();
			SET_CFLG(val & 1);
			SET_ZFLG(!(val & 0xfffe));
			SET_NFLG(0);
			SET_XFLG(GET_CFLG());
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return;
		}
		opcode = regs.ir;
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	uae_u32 carry = val & 1;
	val >>= 1;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	SET_CFLG(carry);
	COPY_CARRY();
	if(loop_mode & 0xfffe) {
		do_cycles_ce000_internal(loop_mode & 0xfffe);
		loop_mode = 1;
	}
	x_put_word(dataa, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dataa + 0, 0x1, val, 1);
		return;
	}
	if (loop_mode) {
		do_cycles_ce000_internal(2);
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return;
}
/* 12 (2/1) */
/* 2 0,0   */

/* LSRW.W -(An) */
void REGPARAM2 op_e2e0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 74;
	CurrentInstrCycles = 14; 
	int loop_mode = regs.loop_mode;
	uaecptr dataa;
	dataa = m68k_areg(regs, srcreg) - 2;
	do_cycles_ce000_internal(2);
	if (dataa & 1) {
		m68k_areg(regs, srcreg) = dataa;
		m68k_incpci(2);
		exception3_read_access2(opcode, dataa, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 data = x_get_word(dataa);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = dataa;
		exception2_read(opcode, dataa + 0, 0x1, 1);
		return;
	}
	m68k_areg(regs, srcreg) = dataa;
	uae_u32 val = (uae_u16)data;
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_ce000_prefetch(4);
		if(hardware_bus_error) {
			int pcoffset = 0;
			CLEAR_CZNV();
			SET_CFLG(val & 1);
			SET_ZFLG(!(val & 0xfffe));
			SET_NFLG(0);
			SET_XFLG(GET_CFLG());
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return;
		}
		opcode = regs.ir;
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	uae_u32 carry = val & 1;
	val >>= 1;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	SET_CFLG(carry);
	COPY_CARRY();
	if(loop_mode & 0xfffe) {
		do_cycles_ce000_internal(loop_mode & 0xfffe);
		loop_mode = 1;
	}
	x_put_word(dataa, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dataa + 0, 0x1, val, 1);
		return;
	}
	if (loop_mode) {
		do_cycles_ce000_internal(2);
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return;
}
/* 14 (2/1) */
/* 2 0,0   */

/* LSRW.W (d16,An) */
void REGPARAM2 op_e2e8_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 74;
	CurrentInstrCycles = 16; 
	uaecptr dataa;
	dataa = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (dataa & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dataa, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 data = x_get_word(dataa);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dataa + 0, 0x1, 1);
		return;
	}
	uae_u32 val = (uae_u16)data;
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();
		SET_CFLG(val & 1);
		SET_ZFLG(!(val & 0xfffe));
		SET_NFLG(0);
		SET_XFLG(GET_CFLG());
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	uae_u32 carry = val & 1;
	val >>= 1;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	SET_CFLG(carry);
	COPY_CARRY();
	x_put_word(dataa, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dataa + 0, 0x1, val, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* LSRW.W (d8,An,Xn) */
void REGPARAM2 op_e2f0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 74;
	CurrentInstrCycles = 18; 
	uaecptr dataa;
	do_cycles_ce000_internal(2);
	dataa = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (dataa & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dataa, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 data = x_get_word(dataa);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dataa + 0, 0x1, 1);
		return;
	}
	uae_u32 val = (uae_u16)data;
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();
		SET_CFLG(val & 1);
		SET_ZFLG(!(val & 0xfffe));
		SET_NFLG(0);
		SET_XFLG(GET_CFLG());
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	uae_u32 carry = val & 1;
	val >>= 1;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	SET_CFLG(carry);
	COPY_CARRY();
	x_put_word(dataa, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dataa + 0, 0x1, val, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 18 (3/1) */
/* 4 4,0   */

/* LSRW.W (xxx).W */
void REGPARAM2 op_e2f8_13_ff(uae_u32 opcode)
{
	OpcodeFamily = 74;
	CurrentInstrCycles = 16; 
	uaecptr dataa;
	dataa = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	if (dataa & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, dataa, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 data = x_get_word(dataa);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dataa + 0, 0x1, 1);
		return;
	}
	uae_u32 val = (uae_u16)data;
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();
		SET_CFLG(val & 1);
		SET_ZFLG(!(val & 0xfffe));
		SET_NFLG(0);
		SET_XFLG(GET_CFLG());
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	uae_u32 carry = val & 1;
	val >>= 1;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	SET_CFLG(carry);
	COPY_CARRY();
	x_put_word(dataa, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dataa + 0, 0x1, val, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* LSRW.W (xxx).L */
void REGPARAM2 op_e2f9_13_ff(uae_u32 opcode)
{
	OpcodeFamily = 74;
	CurrentInstrCycles = 20; 
	uaecptr dataa;
	dataa = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	dataa |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	if (dataa & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, dataa, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 data = x_get_word(dataa);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dataa + 0, 0x1, 1);
		return;
	}
	uae_u32 val = (uae_u16)data;
	regs.ir = regs.irc;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();
		SET_CFLG(val & 1);
		SET_ZFLG(!(val & 0xfffe));
		SET_NFLG(0);
		SET_XFLG(GET_CFLG());
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	opcode = regs.ir;
	uae_u32 carry = val & 1;
	val >>= 1;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	SET_CFLG(carry);
	COPY_CARRY();
	x_put_word(dataa, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dataa + 0, 0x1, val, 1);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 20 (4/1) */
/* 6 0,0   */

/* LSLW.W (An) */
void REGPARAM2 op_e3d0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 75;
	CurrentInstrCycles = 12; 
	int loop_mode = regs.loop_mode;
	uaecptr dataa;
	dataa = m68k_areg(regs, srcreg);
	if (dataa & 1) {
		m68k_incpci(2);
		exception3_read_access2(opcode, dataa, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 data = x_get_word(dataa);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dataa + 0, 0x1, 1);
		return;
	}
	uae_u16 val = data;
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_ce000_prefetch(4);
		if(hardware_bus_error) {
			int pcoffset = 0;
			CLEAR_CZNV();
			SET_CFLG(val & 0x8000);
			SET_ZFLG(!(val & 0x7fff));
			SET_NFLG(val & 0x4000);
			SET_XFLG(GET_CFLG());
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return;
		}
		opcode = regs.ir;
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	uae_u32 carry = val & 0x8000;
	val <<= 1;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	SET_CFLG(carry >> 15);
	COPY_CARRY();
	if(loop_mode & 0xfffe) {
		do_cycles_ce000_internal(loop_mode & 0xfffe);
		loop_mode = 1;
	}
	x_put_word(dataa, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dataa + 0, 0x1, val, 1);
		return;
	}
	if (loop_mode) {
		do_cycles_ce000_internal(2);
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return;
}
/* 12 (2/1) */
/* 2 0,0   */

/* LSLW.W (An)+ */
void REGPARAM2 op_e3d8_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 75;
	CurrentInstrCycles = 12; 
	int loop_mode = regs.loop_mode;
	uaecptr dataa;
	dataa = m68k_areg(regs, srcreg);
	if (dataa & 1) {
		m68k_areg(regs, srcreg) += 2 + 0;
		m68k_incpci(2);
		exception3_read_access2(opcode, dataa, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 data = x_get_word(dataa);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) += 2 + 0;
		exception2_read(opcode, dataa + 0, 0x1, 1);
		return;
	}
	m68k_areg(regs, srcreg) += 2;
	uae_u16 val = data;
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_ce000_prefetch(4);
		if(hardware_bus_error) {
			int pcoffset = 0;
			CLEAR_CZNV();
			SET_CFLG(val & 0x8000);
			SET_ZFLG(!(val & 0x7fff));
			SET_NFLG(val & 0x4000);
			SET_XFLG(GET_CFLG());
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return;
		}
		opcode = regs.ir;
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	uae_u32 carry = val & 0x8000;
	val <<= 1;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	SET_CFLG(carry >> 15);
	COPY_CARRY();
	if(loop_mode & 0xfffe) {
		do_cycles_ce000_internal(loop_mode & 0xfffe);
		loop_mode = 1;
	}
	x_put_word(dataa, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dataa + 0, 0x1, val, 1);
		return;
	}
	if (loop_mode) {
		do_cycles_ce000_internal(2);
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return;
}
/* 12 (2/1) */
/* 2 0,0   */

/* LSLW.W -(An) */
void REGPARAM2 op_e3e0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 75;
	CurrentInstrCycles = 14; 
	int loop_mode = regs.loop_mode;
	uaecptr dataa;
	dataa = m68k_areg(regs, srcreg) - 2;
	do_cycles_ce000_internal(2);
	if (dataa & 1) {
		m68k_areg(regs, srcreg) = dataa;
		m68k_incpci(2);
		exception3_read_access2(opcode, dataa, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 data = x_get_word(dataa);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = dataa;
		exception2_read(opcode, dataa + 0, 0x1, 1);
		return;
	}
	m68k_areg(regs, srcreg) = dataa;
	uae_u16 val = data;
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_ce000_prefetch(4);
		if(hardware_bus_error) {
			int pcoffset = 0;
			CLEAR_CZNV();
			SET_CFLG(val & 0x8000);
			SET_ZFLG(!(val & 0x7fff));
			SET_NFLG(val & 0x4000);
			SET_XFLG(GET_CFLG());
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return;
		}
		opcode = regs.ir;
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	uae_u32 carry = val & 0x8000;
	val <<= 1;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	SET_CFLG(carry >> 15);
	COPY_CARRY();
	if(loop_mode & 0xfffe) {
		do_cycles_ce000_internal(loop_mode & 0xfffe);
		loop_mode = 1;
	}
	x_put_word(dataa, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dataa + 0, 0x1, val, 1);
		return;
	}
	if (loop_mode) {
		do_cycles_ce000_internal(2);
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return;
}
/* 14 (2/1) */
/* 2 0,0   */

/* LSLW.W (d16,An) */
void REGPARAM2 op_e3e8_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 75;
	CurrentInstrCycles = 16; 
	uaecptr dataa;
	dataa = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (dataa & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dataa, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 data = x_get_word(dataa);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dataa + 0, 0x1, 1);
		return;
	}
	uae_u16 val = data;
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();
		SET_CFLG(val & 0x8000);
		SET_ZFLG(!(val & 0x7fff));
		SET_NFLG(val & 0x4000);
		SET_XFLG(GET_CFLG());
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	uae_u32 carry = val & 0x8000;
	val <<= 1;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	SET_CFLG(carry >> 15);
	COPY_CARRY();
	x_put_word(dataa, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dataa + 0, 0x1, val, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* LSLW.W (d8,An,Xn) */
void REGPARAM2 op_e3f0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 75;
	CurrentInstrCycles = 18; 
	uaecptr dataa;
	do_cycles_ce000_internal(2);
	dataa = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (dataa & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dataa, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 data = x_get_word(dataa);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dataa + 0, 0x1, 1);
		return;
	}
	uae_u16 val = data;
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();
		SET_CFLG(val & 0x8000);
		SET_ZFLG(!(val & 0x7fff));
		SET_NFLG(val & 0x4000);
		SET_XFLG(GET_CFLG());
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	uae_u32 carry = val & 0x8000;
	val <<= 1;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	SET_CFLG(carry >> 15);
	COPY_CARRY();
	x_put_word(dataa, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dataa + 0, 0x1, val, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 18 (3/1) */
/* 4 4,0   */

/* LSLW.W (xxx).W */
void REGPARAM2 op_e3f8_13_ff(uae_u32 opcode)
{
	OpcodeFamily = 75;
	CurrentInstrCycles = 16; 
	uaecptr dataa;
	dataa = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	if (dataa & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, dataa, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 data = x_get_word(dataa);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dataa + 0, 0x1, 1);
		return;
	}
	uae_u16 val = data;
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();
		SET_CFLG(val & 0x8000);
		SET_ZFLG(!(val & 0x7fff));
		SET_NFLG(val & 0x4000);
		SET_XFLG(GET_CFLG());
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	uae_u32 carry = val & 0x8000;
	val <<= 1;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	SET_CFLG(carry >> 15);
	COPY_CARRY();
	x_put_word(dataa, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dataa + 0, 0x1, val, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* LSLW.W (xxx).L */
void REGPARAM2 op_e3f9_13_ff(uae_u32 opcode)
{
	OpcodeFamily = 75;
	CurrentInstrCycles = 20; 
	uaecptr dataa;
	dataa = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	dataa |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	if (dataa & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, dataa, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 data = x_get_word(dataa);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dataa + 0, 0x1, 1);
		return;
	}
	uae_u16 val = data;
	regs.ir = regs.irc;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();
		SET_CFLG(val & 0x8000);
		SET_ZFLG(!(val & 0x7fff));
		SET_NFLG(val & 0x4000);
		SET_XFLG(GET_CFLG());
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	opcode = regs.ir;
	uae_u32 carry = val & 0x8000;
	val <<= 1;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	SET_CFLG(carry >> 15);
	COPY_CARRY();
	x_put_word(dataa, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dataa + 0, 0x1, val, 1);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 20 (4/1) */
/* 6 0,0   */

/* ROXRW.W (An) */
void REGPARAM2 op_e4d0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 79;
	CurrentInstrCycles = 12; 
	int loop_mode = regs.loop_mode;
	uaecptr dataa;
	dataa = m68k_areg(regs, srcreg);
	if (dataa & 1) {
		m68k_incpci(2);
		exception3_read_access2(opcode, dataa, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 data = x_get_word(dataa);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dataa + 0, 0x1, 1);
		return;
	}
	uae_u16 val = data;
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_ce000_prefetch(4);
		if(hardware_bus_error) {
			int pcoffset = 0;
			CLEAR_CZNV();SET_CFLG(val & 1);
			SET_ZFLG(!((val &0x7ffe) | GET_XFLG()))
			;SET_NFLG(GET_XFLG())
			;SET_XFLG(GET_CFLG());
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return;
		}
		opcode = regs.ir;
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	uae_u32 carry = val & 1;
	val >>= 1;
	if (GET_XFLG()) val |= 0x8000;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	SET_CFLG(carry);
	COPY_CARRY();
	if(loop_mode & 0xfffe) {
		do_cycles_ce000_internal(loop_mode & 0xfffe);
		loop_mode = 1;
	}
	x_put_word(dataa, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dataa + 0, 0x1, val, 1);
		return;
	}
	if (loop_mode) {
		do_cycles_ce000_internal(2);
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return;
}
/* 12 (2/1) */
/* 2 0,0   */

/* ROXRW.W (An)+ */
void REGPARAM2 op_e4d8_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 79;
	CurrentInstrCycles = 12; 
	int loop_mode = regs.loop_mode;
	uaecptr dataa;
	dataa = m68k_areg(regs, srcreg);
	if (dataa & 1) {
		m68k_areg(regs, srcreg) += 2 + 0;
		m68k_incpci(2);
		exception3_read_access2(opcode, dataa, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 data = x_get_word(dataa);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) += 2 + 0;
		exception2_read(opcode, dataa + 0, 0x1, 1);
		return;
	}
	m68k_areg(regs, srcreg) += 2;
	uae_u16 val = data;
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_ce000_prefetch(4);
		if(hardware_bus_error) {
			int pcoffset = 0;
			CLEAR_CZNV();SET_CFLG(val & 1);
			SET_ZFLG(!((val &0x7ffe) | GET_XFLG()))
			;SET_NFLG(GET_XFLG())
			;SET_XFLG(GET_CFLG());
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return;
		}
		opcode = regs.ir;
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	uae_u32 carry = val & 1;
	val >>= 1;
	if (GET_XFLG()) val |= 0x8000;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	SET_CFLG(carry);
	COPY_CARRY();
	if(loop_mode & 0xfffe) {
		do_cycles_ce000_internal(loop_mode & 0xfffe);
		loop_mode = 1;
	}
	x_put_word(dataa, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dataa + 0, 0x1, val, 1);
		return;
	}
	if (loop_mode) {
		do_cycles_ce000_internal(2);
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return;
}
/* 12 (2/1) */
/* 2 0,0   */

/* ROXRW.W -(An) */
void REGPARAM2 op_e4e0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 79;
	CurrentInstrCycles = 14; 
	int loop_mode = regs.loop_mode;
	uaecptr dataa;
	dataa = m68k_areg(regs, srcreg) - 2;
	do_cycles_ce000_internal(2);
	if (dataa & 1) {
		m68k_areg(regs, srcreg) = dataa;
		m68k_incpci(2);
		exception3_read_access2(opcode, dataa, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 data = x_get_word(dataa);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = dataa;
		exception2_read(opcode, dataa + 0, 0x1, 1);
		return;
	}
	m68k_areg(regs, srcreg) = dataa;
	uae_u16 val = data;
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_ce000_prefetch(4);
		if(hardware_bus_error) {
			int pcoffset = 0;
			CLEAR_CZNV();SET_CFLG(val & 1);
			SET_ZFLG(!((val &0x7ffe) | GET_XFLG()))
			;SET_NFLG(GET_XFLG())
			;SET_XFLG(GET_CFLG());
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return;
		}
		opcode = regs.ir;
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	uae_u32 carry = val & 1;
	val >>= 1;
	if (GET_XFLG()) val |= 0x8000;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	SET_CFLG(carry);
	COPY_CARRY();
	if(loop_mode & 0xfffe) {
		do_cycles_ce000_internal(loop_mode & 0xfffe);
		loop_mode = 1;
	}
	x_put_word(dataa, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dataa + 0, 0x1, val, 1);
		return;
	}
	if (loop_mode) {
		do_cycles_ce000_internal(2);
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return;
}
/* 14 (2/1) */
/* 2 0,0   */

/* ROXRW.W (d16,An) */
void REGPARAM2 op_e4e8_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 79;
	CurrentInstrCycles = 16; 
	uaecptr dataa;
	dataa = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (dataa & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dataa, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 data = x_get_word(dataa);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dataa + 0, 0x1, 1);
		return;
	}
	uae_u16 val = data;
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();SET_CFLG(val & 1);
		SET_ZFLG(!((val &0x7ffe) | GET_XFLG()))
		;SET_NFLG(GET_XFLG())
		;SET_XFLG(GET_CFLG());
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	uae_u32 carry = val & 1;
	val >>= 1;
	if (GET_XFLG()) val |= 0x8000;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	SET_CFLG(carry);
	COPY_CARRY();
	x_put_word(dataa, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dataa + 0, 0x1, val, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* ROXRW.W (d8,An,Xn) */
void REGPARAM2 op_e4f0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 79;
	CurrentInstrCycles = 18; 
	uaecptr dataa;
	do_cycles_ce000_internal(2);
	dataa = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (dataa & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dataa, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 data = x_get_word(dataa);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dataa + 0, 0x1, 1);
		return;
	}
	uae_u16 val = data;
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();SET_CFLG(val & 1);
		SET_ZFLG(!((val &0x7ffe) | GET_XFLG()))
		;SET_NFLG(GET_XFLG())
		;SET_XFLG(GET_CFLG());
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	uae_u32 carry = val & 1;
	val >>= 1;
	if (GET_XFLG()) val |= 0x8000;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	SET_CFLG(carry);
	COPY_CARRY();
	x_put_word(dataa, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dataa + 0, 0x1, val, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 18 (3/1) */
/* 4 4,0   */

/* ROXRW.W (xxx).W */
void REGPARAM2 op_e4f8_13_ff(uae_u32 opcode)
{
	OpcodeFamily = 79;
	CurrentInstrCycles = 16; 
	uaecptr dataa;
	dataa = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	if (dataa & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, dataa, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 data = x_get_word(dataa);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dataa + 0, 0x1, 1);
		return;
	}
	uae_u16 val = data;
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();SET_CFLG(val & 1);
		SET_ZFLG(!((val &0x7ffe) | GET_XFLG()))
		;SET_NFLG(GET_XFLG())
		;SET_XFLG(GET_CFLG());
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	uae_u32 carry = val & 1;
	val >>= 1;
	if (GET_XFLG()) val |= 0x8000;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	SET_CFLG(carry);
	COPY_CARRY();
	x_put_word(dataa, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dataa + 0, 0x1, val, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* ROXRW.W (xxx).L */
void REGPARAM2 op_e4f9_13_ff(uae_u32 opcode)
{
	OpcodeFamily = 79;
	CurrentInstrCycles = 20; 
	uaecptr dataa;
	dataa = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	dataa |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	if (dataa & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, dataa, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 data = x_get_word(dataa);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dataa + 0, 0x1, 1);
		return;
	}
	uae_u16 val = data;
	regs.ir = regs.irc;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();SET_CFLG(val & 1);
		SET_ZFLG(!((val &0x7ffe) | GET_XFLG()))
		;SET_NFLG(GET_XFLG())
		;SET_XFLG(GET_CFLG());
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	opcode = regs.ir;
	uae_u32 carry = val & 1;
	val >>= 1;
	if (GET_XFLG()) val |= 0x8000;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	SET_CFLG(carry);
	COPY_CARRY();
	x_put_word(dataa, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dataa + 0, 0x1, val, 1);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 20 (4/1) */
/* 6 0,0   */

/* ROXLW.W (An) */
void REGPARAM2 op_e5d0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 78;
	CurrentInstrCycles = 12; 
	int loop_mode = regs.loop_mode;
	uaecptr dataa;
	dataa = m68k_areg(regs, srcreg);
	if (dataa & 1) {
		m68k_incpci(2);
		exception3_read_access2(opcode, dataa, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 data = x_get_word(dataa);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dataa + 0, 0x1, 1);
		return;
	}
	uae_u16 val = data;
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_ce000_prefetch(4);
		if(hardware_bus_error) {
			int pcoffset = 0;
			CLEAR_CZNV();
			SET_CFLG(val & 0x8000);
			SET_ZFLG(!((val & 0x7fff) | GET_XFLG()));
			SET_NFLG(val & 0x4000);
			SET_XFLG(GET_CFLG());
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return;
		}
		opcode = regs.ir;
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	uae_u32 carry = val & 0x8000;
	val <<= 1;
	if (GET_XFLG()) val |= 1;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	SET_CFLG(carry >> 15);
	COPY_CARRY();
	if(loop_mode & 0xfffe) {
		do_cycles_ce000_internal(loop_mode & 0xfffe);
		loop_mode = 1;
	}
	x_put_word(dataa, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dataa + 0, 0x1, val, 1);
		return;
	}
	if (loop_mode) {
		do_cycles_ce000_internal(2);
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return;
}
/* 12 (2/1) */
/* 2 0,0   */

/* ROXLW.W (An)+ */
void REGPARAM2 op_e5d8_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 78;
	CurrentInstrCycles = 12; 
	int loop_mode = regs.loop_mode;
	uaecptr dataa;
	dataa = m68k_areg(regs, srcreg);
	if (dataa & 1) {
		m68k_areg(regs, srcreg) += 2 + 0;
		m68k_incpci(2);
		exception3_read_access2(opcode, dataa, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 data = x_get_word(dataa);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) += 2 + 0;
		exception2_read(opcode, dataa + 0, 0x1, 1);
		return;
	}
	m68k_areg(regs, srcreg) += 2;
	uae_u16 val = data;
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_ce000_prefetch(4);
		if(hardware_bus_error) {
			int pcoffset = 0;
			CLEAR_CZNV();
			SET_CFLG(val & 0x8000);
			SET_ZFLG(!((val & 0x7fff) | GET_XFLG()));
			SET_NFLG(val & 0x4000);
			SET_XFLG(GET_CFLG());
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return;
		}
		opcode = regs.ir;
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	uae_u32 carry = val & 0x8000;
	val <<= 1;
	if (GET_XFLG()) val |= 1;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	SET_CFLG(carry >> 15);
	COPY_CARRY();
	if(loop_mode & 0xfffe) {
		do_cycles_ce000_internal(loop_mode & 0xfffe);
		loop_mode = 1;
	}
	x_put_word(dataa, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dataa + 0, 0x1, val, 1);
		return;
	}
	if (loop_mode) {
		do_cycles_ce000_internal(2);
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return;
}
/* 12 (2/1) */
/* 2 0,0   */

/* ROXLW.W -(An) */
void REGPARAM2 op_e5e0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 78;
	CurrentInstrCycles = 14; 
	int loop_mode = regs.loop_mode;
	uaecptr dataa;
	dataa = m68k_areg(regs, srcreg) - 2;
	do_cycles_ce000_internal(2);
	if (dataa & 1) {
		m68k_areg(regs, srcreg) = dataa;
		m68k_incpci(2);
		exception3_read_access2(opcode, dataa, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 data = x_get_word(dataa);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = dataa;
		exception2_read(opcode, dataa + 0, 0x1, 1);
		return;
	}
	m68k_areg(regs, srcreg) = dataa;
	uae_u16 val = data;
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_ce000_prefetch(4);
		if(hardware_bus_error) {
			int pcoffset = 0;
			CLEAR_CZNV();
			SET_CFLG(val & 0x8000);
			SET_ZFLG(!((val & 0x7fff) | GET_XFLG()));
			SET_NFLG(val & 0x4000);
			SET_XFLG(GET_CFLG());
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return;
		}
		opcode = regs.ir;
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	uae_u32 carry = val & 0x8000;
	val <<= 1;
	if (GET_XFLG()) val |= 1;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	SET_CFLG(carry >> 15);
	COPY_CARRY();
	if(loop_mode & 0xfffe) {
		do_cycles_ce000_internal(loop_mode & 0xfffe);
		loop_mode = 1;
	}
	x_put_word(dataa, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dataa + 0, 0x1, val, 1);
		return;
	}
	if (loop_mode) {
		do_cycles_ce000_internal(2);
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return;
}
/* 14 (2/1) */
/* 2 0,0   */

/* ROXLW.W (d16,An) */
void REGPARAM2 op_e5e8_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 78;
	CurrentInstrCycles = 16; 
	uaecptr dataa;
	dataa = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (dataa & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dataa, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 data = x_get_word(dataa);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dataa + 0, 0x1, 1);
		return;
	}
	uae_u16 val = data;
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();
		SET_CFLG(val & 0x8000);
		SET_ZFLG(!((val & 0x7fff) | GET_XFLG()));
		SET_NFLG(val & 0x4000);
		SET_XFLG(GET_CFLG());
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	uae_u32 carry = val & 0x8000;
	val <<= 1;
	if (GET_XFLG()) val |= 1;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	SET_CFLG(carry >> 15);
	COPY_CARRY();
	x_put_word(dataa, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dataa + 0, 0x1, val, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* ROXLW.W (d8,An,Xn) */
void REGPARAM2 op_e5f0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 78;
	CurrentInstrCycles = 18; 
	uaecptr dataa;
	do_cycles_ce000_internal(2);
	dataa = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (dataa & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dataa, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 data = x_get_word(dataa);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dataa + 0, 0x1, 1);
		return;
	}
	uae_u16 val = data;
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();
		SET_CFLG(val & 0x8000);
		SET_ZFLG(!((val & 0x7fff) | GET_XFLG()));
		SET_NFLG(val & 0x4000);
		SET_XFLG(GET_CFLG());
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	uae_u32 carry = val & 0x8000;
	val <<= 1;
	if (GET_XFLG()) val |= 1;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	SET_CFLG(carry >> 15);
	COPY_CARRY();
	x_put_word(dataa, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dataa + 0, 0x1, val, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 18 (3/1) */
/* 4 4,0   */

/* ROXLW.W (xxx).W */
void REGPARAM2 op_e5f8_13_ff(uae_u32 opcode)
{
	OpcodeFamily = 78;
	CurrentInstrCycles = 16; 
	uaecptr dataa;
	dataa = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	if (dataa & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, dataa, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 data = x_get_word(dataa);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dataa + 0, 0x1, 1);
		return;
	}
	uae_u16 val = data;
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();
		SET_CFLG(val & 0x8000);
		SET_ZFLG(!((val & 0x7fff) | GET_XFLG()));
		SET_NFLG(val & 0x4000);
		SET_XFLG(GET_CFLG());
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	uae_u32 carry = val & 0x8000;
	val <<= 1;
	if (GET_XFLG()) val |= 1;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	SET_CFLG(carry >> 15);
	COPY_CARRY();
	x_put_word(dataa, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dataa + 0, 0x1, val, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* ROXLW.W (xxx).L */
void REGPARAM2 op_e5f9_13_ff(uae_u32 opcode)
{
	OpcodeFamily = 78;
	CurrentInstrCycles = 20; 
	uaecptr dataa;
	dataa = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	dataa |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	if (dataa & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, dataa, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 data = x_get_word(dataa);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dataa + 0, 0x1, 1);
		return;
	}
	uae_u16 val = data;
	regs.ir = regs.irc;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();
		SET_CFLG(val & 0x8000);
		SET_ZFLG(!((val & 0x7fff) | GET_XFLG()));
		SET_NFLG(val & 0x4000);
		SET_XFLG(GET_CFLG());
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	opcode = regs.ir;
	uae_u32 carry = val & 0x8000;
	val <<= 1;
	if (GET_XFLG()) val |= 1;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	SET_CFLG(carry >> 15);
	COPY_CARRY();
	x_put_word(dataa, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dataa + 0, 0x1, val, 1);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 20 (4/1) */
/* 6 0,0   */

/* RORW.W (An) */
void REGPARAM2 op_e6d0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 77;
	CurrentInstrCycles = 12; 
	int loop_mode = regs.loop_mode;
	uaecptr dataa;
	dataa = m68k_areg(regs, srcreg);
	if (dataa & 1) {
		m68k_incpci(2);
		exception3_read_access2(opcode, dataa, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 data = x_get_word(dataa);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dataa + 0, 0x1, 1);
		return;
	}
	uae_u16 val = data;
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_ce000_prefetch(4);
		if(hardware_bus_error) {
			int pcoffset = 0;
			CLEAR_CZNV();
			SET_CFLG(val & 1);
			SET_ZFLG(!val);
			SET_NFLG(val & 0x0001);
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return;
		}
		opcode = regs.ir;
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	uae_u32 carry = val & 1;
	val >>= 1;
	if (carry) val |= 0x8000;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	SET_CFLG(carry);
	if(loop_mode & 0xfffe) {
		do_cycles_ce000_internal(loop_mode & 0xfffe);
		loop_mode = 1;
	}
	x_put_word(dataa, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dataa + 0, 0x1, val, 1);
		return;
	}
	if (loop_mode) {
		do_cycles_ce000_internal(2);
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return;
}
/* 12 (2/1) */
/* 2 0,0   */

/* RORW.W (An)+ */
void REGPARAM2 op_e6d8_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 77;
	CurrentInstrCycles = 12; 
	int loop_mode = regs.loop_mode;
	uaecptr dataa;
	dataa = m68k_areg(regs, srcreg);
	if (dataa & 1) {
		m68k_areg(regs, srcreg) += 2 + 0;
		m68k_incpci(2);
		exception3_read_access2(opcode, dataa, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 data = x_get_word(dataa);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) += 2 + 0;
		exception2_read(opcode, dataa + 0, 0x1, 1);
		return;
	}
	m68k_areg(regs, srcreg) += 2;
	uae_u16 val = data;
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_ce000_prefetch(4);
		if(hardware_bus_error) {
			int pcoffset = 0;
			CLEAR_CZNV();
			SET_CFLG(val & 1);
			SET_ZFLG(!val);
			SET_NFLG(val & 0x0001);
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return;
		}
		opcode = regs.ir;
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	uae_u32 carry = val & 1;
	val >>= 1;
	if (carry) val |= 0x8000;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	SET_CFLG(carry);
	if(loop_mode & 0xfffe) {
		do_cycles_ce000_internal(loop_mode & 0xfffe);
		loop_mode = 1;
	}
	x_put_word(dataa, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dataa + 0, 0x1, val, 1);
		return;
	}
	if (loop_mode) {
		do_cycles_ce000_internal(2);
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return;
}
/* 12 (2/1) */
/* 2 0,0   */

/* RORW.W -(An) */
void REGPARAM2 op_e6e0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 77;
	CurrentInstrCycles = 14; 
	int loop_mode = regs.loop_mode;
	uaecptr dataa;
	dataa = m68k_areg(regs, srcreg) - 2;
	do_cycles_ce000_internal(2);
	if (dataa & 1) {
		m68k_areg(regs, srcreg) = dataa;
		m68k_incpci(2);
		exception3_read_access2(opcode, dataa, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 data = x_get_word(dataa);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = dataa;
		exception2_read(opcode, dataa + 0, 0x1, 1);
		return;
	}
	m68k_areg(regs, srcreg) = dataa;
	uae_u16 val = data;
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_ce000_prefetch(4);
		if(hardware_bus_error) {
			int pcoffset = 0;
			CLEAR_CZNV();
			SET_CFLG(val & 1);
			SET_ZFLG(!val);
			SET_NFLG(val & 0x0001);
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return;
		}
		opcode = regs.ir;
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	uae_u32 carry = val & 1;
	val >>= 1;
	if (carry) val |= 0x8000;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	SET_CFLG(carry);
	if(loop_mode & 0xfffe) {
		do_cycles_ce000_internal(loop_mode & 0xfffe);
		loop_mode = 1;
	}
	x_put_word(dataa, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dataa + 0, 0x1, val, 1);
		return;
	}
	if (loop_mode) {
		do_cycles_ce000_internal(2);
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return;
}
/* 14 (2/1) */
/* 2 0,0   */

/* RORW.W (d16,An) */
void REGPARAM2 op_e6e8_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 77;
	CurrentInstrCycles = 16; 
	uaecptr dataa;
	dataa = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (dataa & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dataa, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 data = x_get_word(dataa);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dataa + 0, 0x1, 1);
		return;
	}
	uae_u16 val = data;
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();
		SET_CFLG(val & 1);
		SET_ZFLG(!val);
		SET_NFLG(val & 0x0001);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	uae_u32 carry = val & 1;
	val >>= 1;
	if (carry) val |= 0x8000;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	SET_CFLG(carry);
	x_put_word(dataa, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dataa + 0, 0x1, val, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* RORW.W (d8,An,Xn) */
void REGPARAM2 op_e6f0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 77;
	CurrentInstrCycles = 18; 
	uaecptr dataa;
	do_cycles_ce000_internal(2);
	dataa = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (dataa & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dataa, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 data = x_get_word(dataa);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dataa + 0, 0x1, 1);
		return;
	}
	uae_u16 val = data;
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();
		SET_CFLG(val & 1);
		SET_ZFLG(!val);
		SET_NFLG(val & 0x0001);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	uae_u32 carry = val & 1;
	val >>= 1;
	if (carry) val |= 0x8000;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	SET_CFLG(carry);
	x_put_word(dataa, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dataa + 0, 0x1, val, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 18 (3/1) */
/* 4 4,0   */

/* RORW.W (xxx).W */
void REGPARAM2 op_e6f8_13_ff(uae_u32 opcode)
{
	OpcodeFamily = 77;
	CurrentInstrCycles = 16; 
	uaecptr dataa;
	dataa = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	if (dataa & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, dataa, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 data = x_get_word(dataa);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dataa + 0, 0x1, 1);
		return;
	}
	uae_u16 val = data;
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();
		SET_CFLG(val & 1);
		SET_ZFLG(!val);
		SET_NFLG(val & 0x0001);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	uae_u32 carry = val & 1;
	val >>= 1;
	if (carry) val |= 0x8000;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	SET_CFLG(carry);
	x_put_word(dataa, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dataa + 0, 0x1, val, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* RORW.W (xxx).L */
void REGPARAM2 op_e6f9_13_ff(uae_u32 opcode)
{
	OpcodeFamily = 77;
	CurrentInstrCycles = 20; 
	uaecptr dataa;
	dataa = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	dataa |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	if (dataa & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, dataa, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 data = x_get_word(dataa);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dataa + 0, 0x1, 1);
		return;
	}
	uae_u16 val = data;
	regs.ir = regs.irc;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();
		SET_CFLG(val & 1);
		SET_ZFLG(!val);
		SET_NFLG(val & 0x0001);
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	opcode = regs.ir;
	uae_u32 carry = val & 1;
	val >>= 1;
	if (carry) val |= 0x8000;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	SET_CFLG(carry);
	x_put_word(dataa, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dataa + 0, 0x1, val, 1);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 20 (4/1) */
/* 6 0,0   */

/* ROLW.W (An) */
void REGPARAM2 op_e7d0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 76;
	CurrentInstrCycles = 12; 
	int loop_mode = regs.loop_mode;
	uaecptr dataa;
	dataa = m68k_areg(regs, srcreg);
	if (dataa & 1) {
		m68k_incpci(2);
		exception3_read_access2(opcode, dataa, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 data = x_get_word(dataa);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dataa + 0, 0x1, 1);
		return;
	}
	uae_u16 val = data;
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_ce000_prefetch(4);
		if(hardware_bus_error) {
			int pcoffset = 0;
			CLEAR_CZNV();SET_CFLG(val & 0x8000);
			SET_ZFLG(!val);
			SET_NFLG(val & 0x4000);
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return;
		}
		opcode = regs.ir;
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	uae_u32 carry = val & 0x8000;
	val <<= 1;
	if (carry)  val |= 1;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	SET_CFLG(carry >> 15);
	if(loop_mode & 0xfffe) {
		do_cycles_ce000_internal(loop_mode & 0xfffe);
		loop_mode = 1;
	}
	x_put_word(dataa, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dataa + 0, 0x1, val, 1);
		return;
	}
	if (loop_mode) {
		do_cycles_ce000_internal(2);
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return;
}
/* 12 (2/1) */
/* 2 0,0   */

/* ROLW.W (An)+ */
void REGPARAM2 op_e7d8_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 76;
	CurrentInstrCycles = 12; 
	int loop_mode = regs.loop_mode;
	uaecptr dataa;
	dataa = m68k_areg(regs, srcreg);
	if (dataa & 1) {
		m68k_areg(regs, srcreg) += 2 + 0;
		m68k_incpci(2);
		exception3_read_access2(opcode, dataa, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 data = x_get_word(dataa);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) += 2 + 0;
		exception2_read(opcode, dataa + 0, 0x1, 1);
		return;
	}
	m68k_areg(regs, srcreg) += 2;
	uae_u16 val = data;
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_ce000_prefetch(4);
		if(hardware_bus_error) {
			int pcoffset = 0;
			CLEAR_CZNV();SET_CFLG(val & 0x8000);
			SET_ZFLG(!val);
			SET_NFLG(val & 0x4000);
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return;
		}
		opcode = regs.ir;
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	uae_u32 carry = val & 0x8000;
	val <<= 1;
	if (carry)  val |= 1;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	SET_CFLG(carry >> 15);
	if(loop_mode & 0xfffe) {
		do_cycles_ce000_internal(loop_mode & 0xfffe);
		loop_mode = 1;
	}
	x_put_word(dataa, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dataa + 0, 0x1, val, 1);
		return;
	}
	if (loop_mode) {
		do_cycles_ce000_internal(2);
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return;
}
/* 12 (2/1) */
/* 2 0,0   */

/* ROLW.W -(An) */
void REGPARAM2 op_e7e0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 76;
	CurrentInstrCycles = 14; 
	int loop_mode = regs.loop_mode;
	uaecptr dataa;
	dataa = m68k_areg(regs, srcreg) - 2;
	do_cycles_ce000_internal(2);
	if (dataa & 1) {
		m68k_areg(regs, srcreg) = dataa;
		m68k_incpci(2);
		exception3_read_access2(opcode, dataa, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 data = x_get_word(dataa);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = dataa;
		exception2_read(opcode, dataa + 0, 0x1, 1);
		return;
	}
	m68k_areg(regs, srcreg) = dataa;
	uae_u16 val = data;
	if(!loop_mode) {
		regs.ir = regs.irc;
		get_word_ce000_prefetch(4);
		if(hardware_bus_error) {
			int pcoffset = 0;
			CLEAR_CZNV();SET_CFLG(val & 0x8000);
			SET_ZFLG(!val);
			SET_NFLG(val & 0x4000);
			exception2_fetch_opcode(opcode, 4, pcoffset);
			return;
		}
		opcode = regs.ir;
	} else {
		loop_mode = 0;
		loop_mode |= 4;
		loop_mode |= 4 << 16;
	}
	uae_u32 carry = val & 0x8000;
	val <<= 1;
	if (carry)  val |= 1;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	SET_CFLG(carry >> 15);
	if(loop_mode & 0xfffe) {
		do_cycles_ce000_internal(loop_mode & 0xfffe);
		loop_mode = 1;
	}
	x_put_word(dataa, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dataa + 0, 0x1, val, 1);
		return;
	}
	if (loop_mode) {
		do_cycles_ce000_internal(2);
	}
	regs.loop_mode = loop_mode;
	m68k_incpci(2);
	return;
}
/* 14 (2/1) */
/* 2 0,0   */

/* ROLW.W (d16,An) */
void REGPARAM2 op_e7e8_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 76;
	CurrentInstrCycles = 16; 
	uaecptr dataa;
	dataa = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (dataa & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dataa, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 data = x_get_word(dataa);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dataa + 0, 0x1, 1);
		return;
	}
	uae_u16 val = data;
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();SET_CFLG(val & 0x8000);
		SET_ZFLG(!val);
		SET_NFLG(val & 0x4000);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	uae_u32 carry = val & 0x8000;
	val <<= 1;
	if (carry)  val |= 1;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	SET_CFLG(carry >> 15);
	x_put_word(dataa, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dataa + 0, 0x1, val, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* ROLW.W (d8,An,Xn) */
void REGPARAM2 op_e7f0_13_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 76;
	CurrentInstrCycles = 18; 
	uaecptr dataa;
	do_cycles_ce000_internal(2);
	dataa = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (dataa & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dataa, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 data = x_get_word(dataa);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dataa + 0, 0x1, 1);
		return;
	}
	uae_u16 val = data;
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();SET_CFLG(val & 0x8000);
		SET_ZFLG(!val);
		SET_NFLG(val & 0x4000);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	uae_u32 carry = val & 0x8000;
	val <<= 1;
	if (carry)  val |= 1;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	SET_CFLG(carry >> 15);
	x_put_word(dataa, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dataa + 0, 0x1, val, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 18 (3/1) */
/* 4 4,0   */

/* ROLW.W (xxx).W */
void REGPARAM2 op_e7f8_13_ff(uae_u32 opcode)
{
	OpcodeFamily = 76;
	CurrentInstrCycles = 16; 
	uaecptr dataa;
	dataa = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	if (dataa & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, dataa, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 data = x_get_word(dataa);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dataa + 0, 0x1, 1);
		return;
	}
	uae_u16 val = data;
	regs.ir = regs.irc;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();SET_CFLG(val & 0x8000);
		SET_ZFLG(!val);
		SET_NFLG(val & 0x4000);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	uae_u32 carry = val & 0x8000;
	val <<= 1;
	if (carry)  val |= 1;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	SET_CFLG(carry >> 15);
	x_put_word(dataa, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dataa + 0, 0x1, val, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* ROLW.W (xxx).L */
void REGPARAM2 op_e7f9_13_ff(uae_u32 opcode)
{
	OpcodeFamily = 76;
	CurrentInstrCycles = 20; 
	uaecptr dataa;
	dataa = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	dataa |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	if (dataa & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, dataa, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 data = x_get_word(dataa);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dataa + 0, 0x1, 1);
		return;
	}
	uae_u16 val = data;
	regs.ir = regs.irc;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();SET_CFLG(val & 0x8000);
		SET_ZFLG(!val);
		SET_NFLG(val & 0x4000);
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	opcode = regs.ir;
	uae_u32 carry = val & 0x8000;
	val <<= 1;
	if (carry)  val |= 1;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	SET_CFLG(carry >> 15);
	x_put_word(dataa, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dataa + 0, 0x1, val, 1);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 20 (4/1) */
/* 6 0,0   */

/* OR.B #<data>.B,Dn */
void REGPARAM2 op_0000_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 8;  
	uae_s8 src = (uae_u8)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uae_s8 dst = m68k_dreg(regs, dstreg);
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 8 (2/0) */
/* 4 0,0   */

/* OR.B #<data>.B,(An) */
void REGPARAM2 op_0010_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 16; 
	uae_s8 src = (uae_u8)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_byte(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* OR.B #<data>.B,(An)+ */
void REGPARAM2 op_0018_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 16; 
	uae_s8 src = (uae_u8)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_byte(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* OR.B #<data>.B,-(An) */
void REGPARAM2 op_0020_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 18; 
	uae_s8 src = (uae_u8)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
	do_cycles_ce000_internal(2);
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		m68k_areg(regs, dstreg) = dsta;
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	m68k_areg(regs, dstreg) = dsta;
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_byte(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 18 (3/1) */
/* 4 0,0   */

/* OR.B #<data>.B,(d16,An) */
void REGPARAM2 op_0028_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 20; 
	uae_s8 src = (uae_u8)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return;
	}
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_byte(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 20 (4/1) */
/* 6 0,0   */

/* OR.B #<data>.B,(d8,An,Xn) */
void REGPARAM2 op_0030_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 22; 
	uae_s8 src = (uae_u8)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr dsta;
	do_cycles_ce000_internal(2);
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_ce000_prefetch(6));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return;
	}
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_byte(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 22 (4/1) */
/* 6 4,0   */

/* OR.B #<data>.B,(xxx).W */
void REGPARAM2 op_0038_14_ff(uae_u32 opcode)
{
	OpcodeFamily = 1;
	CurrentInstrCycles = 20; 
	uae_s8 src = (uae_u8)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, 0);
		return;
	}
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_byte(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 20 (4/1) */
/* 6 0,0   */

/* OR.B #<data>.B,(xxx).L */
void REGPARAM2 op_0039_14_ff(uae_u32 opcode)
{
	OpcodeFamily = 1;
	CurrentInstrCycles = 24; 
	uae_s8 src = (uae_u8)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr dsta;
	dsta = get_word_ce000_prefetch(6) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return;
	}
	dsta |= get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 8, pcoffset);
		return;
	}
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(10);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 10, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_byte(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(10);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return;
	}
	m68k_incpci(8);
	return;
}
/* 24 (5/1) */
/* 8 0,0   */

/* ORSR.B #<data>.W */
void REGPARAM2 op_003c_14_ff(uae_u32 opcode)
{
	OpcodeFamily = 4;
	CurrentInstrCycles = 20; 
	MakeSR();
	int t1 = regs.t1;
	uae_s16 src = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	src &= 0xFF;
	do_cycles_ce000_internal(8);
	regs.sr |= src;
	MakeFromSR();
	m68k_incpci(4);
	get_word_ce000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, 0);
		return;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	if(t1) opcode |= 0x10000;
	ipl_fetch_next();
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 20 (3/0) */
/* 4 0,0   */

/* OR.W #<data>.W,Dn */
void REGPARAM2 op_0040_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 8;  
	uae_s16 src = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 8 (2/0) */
/* 4 0,0   */

/* OR.W #<data>.W,(An) */
void REGPARAM2 op_0050_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 16; 
	uae_s16 src = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	if (dsta & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, dsta, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 dst = x_get_word(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_word(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* OR.W #<data>.W,(An)+ */
void REGPARAM2 op_0058_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 16; 
	uae_s16 src = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	if (dsta & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, dsta, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 dst = x_get_word(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, dstreg) += 2 + 0;
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	m68k_areg(regs, dstreg) += 2;
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_word(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* OR.W #<data>.W,-(An) */
void REGPARAM2 op_0060_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 18; 
	uae_s16 src = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - 2;
	do_cycles_ce000_internal(2);
	if (dsta & 1) {
		m68k_incpci(6);
		m68k_areg(regs, dstreg) = dsta;
		exception3_read_access(opcode, dsta, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 dst = x_get_word(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		m68k_areg(regs, dstreg) = dsta;
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	m68k_areg(regs, dstreg) = dsta;
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_word(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 18 (3/1) */
/* 4 0,0   */

/* OR.W #<data>.W,(d16,An) */
void REGPARAM2 op_0068_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 20; 
	uae_s16 src = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, dsta, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 dst = x_get_word(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_word(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 20 (4/1) */
/* 6 0,0   */

/* OR.W #<data>.W,(d8,An,Xn) */
void REGPARAM2 op_0070_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 22; 
	uae_s16 src = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr dsta;
	do_cycles_ce000_internal(2);
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_ce000_prefetch(6));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, dsta, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 dst = x_get_word(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_word(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 22 (4/1) */
/* 6 4,0   */

/* OR.W #<data>.W,(xxx).W */
void REGPARAM2 op_0078_14_ff(uae_u32 opcode)
{
	OpcodeFamily = 1;
	CurrentInstrCycles = 20; 
	uae_s16 src = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, 0);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, dsta, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 dst = x_get_word(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_word(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 20 (4/1) */
/* 6 0,0   */

/* OR.W #<data>.W,(xxx).L */
void REGPARAM2 op_0079_14_ff(uae_u32 opcode)
{
	OpcodeFamily = 1;
	CurrentInstrCycles = 24; 
	uae_s16 src = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr dsta;
	dsta = get_word_ce000_prefetch(6) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return;
	}
	dsta |= get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 8, pcoffset);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(8);
		exception3_read_access(opcode, dsta, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 dst = x_get_word(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(10);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 10, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_word(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(10);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return;
	}
	m68k_incpci(8);
	return;
}
/* 24 (5/1) */
/* 8 0,0   */

/* ORSR.W #<data>.W */
void REGPARAM2 op_007c_14_ff(uae_u32 opcode)
{
	OpcodeFamily = 4;
	CurrentInstrCycles = 20; 
	if (!regs.s) {
		Exception(8);
		return;
	}
	MakeSR();
	int t1 = regs.t1;
	uae_s16 src = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	do_cycles_ce000_internal(8);
	regs.sr |= src;
	MakeFromSR();
	m68k_incpci(4);
	get_word_ce000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, 0);
		return;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	if(t1) opcode |= 0x10000;
	ipl_fetch_next();
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 20 (3/0) */
/* 4 0,0   */

/* OR.L #<data>.L,Dn */
void REGPARAM2 op_0080_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 16; 
	uae_s32 src;
	src = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	src |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		dreg_68000_long_replace_low(dstreg, src);
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	opcode = regs.ir;
	do_cycles_ce000_internal(4);
	m68k_dreg(regs, dstreg) = (src);
	m68k_incpci(6);
	return;
}
/* 16 (3/0) */
/* 6 0,0   */

/* OR.L #<data>.L,(An) */
void REGPARAM2 op_0090_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 28; 
	uae_s32 src;
	src = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	src |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	if (dsta & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, dsta, 2, 1);
		return;
	}
	uae_s32 dst = x_get_word(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	dst |= x_get_word(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return;
	}
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	x_put_word(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return;
	}
	x_put_word(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 28 (5/2) */
/* 6 0,0   */

/* OR.L #<data>.L,(An)+ */
void REGPARAM2 op_0098_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 28; 
	uae_s32 src;
	src = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	src |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	if (dsta & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, dsta, 2, 1);
		return;
	}
	uae_s32 dst = x_get_word(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	dst |= x_get_word(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return;
	}
	m68k_areg(regs, dstreg) += 4;
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	x_put_word(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return;
	}
	x_put_word(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 28 (5/2) */
/* 6 0,0   */

/* OR.L #<data>.L,-(An) */
void REGPARAM2 op_00a0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 30; 
	uae_s32 src;
	src = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	src |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - 4;
	do_cycles_ce000_internal(2);
	if (dsta & 1) {
		m68k_incpci(6);
		m68k_areg(regs, dstreg) = dsta;
		exception3_read_access(opcode, dsta, 2, 1);
		return;
	}
	uae_s32 dst = x_get_word(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		m68k_areg(regs, dstreg) = dsta;
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	dst |= x_get_word(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		m68k_areg(regs, dstreg) = dsta;
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return;
	}
	m68k_areg(regs, dstreg) = dsta;
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	x_put_word(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return;
	}
	x_put_word(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 30 (5/2) */
/* 6 0,0   */

/* OR.L #<data>.L,(d16,An) */
void REGPARAM2 op_00a8_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 32; 
	uae_s32 src;
	src = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	src |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 8, -2);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, dsta, 2, 1);
		return;
	}
	uae_s32 dst = x_get_word(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	dst |= x_get_word(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return;
	}
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(10);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch_opcode(opcode, 10, pcoffset);
		return;
	}
	x_put_word(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(10);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return;
	}
	x_put_word(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(10);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return;
	}
	m68k_incpci(8);
	return;
}
/* 32 (6/2) */
/* 8 0,0   */

/* OR.L #<data>.L,(d8,An,Xn) */
void REGPARAM2 op_00b0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 34; 
	uae_s32 src;
	src = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	src |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	uaecptr dsta;
	do_cycles_ce000_internal(2);
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_ce000_prefetch(8));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 8, -2);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, dsta, 2, 1);
		return;
	}
	uae_s32 dst = x_get_word(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	dst |= x_get_word(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return;
	}
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(10);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch_opcode(opcode, 10, pcoffset);
		return;
	}
	x_put_word(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(10);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return;
	}
	x_put_word(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(10);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return;
	}
	m68k_incpci(8);
	return;
}
/* 34 (6/2) */
/* 8 4,0   */

/* OR.L #<data>.L,(xxx).W */
void REGPARAM2 op_00b8_14_ff(uae_u32 opcode)
{
	OpcodeFamily = 1;
	CurrentInstrCycles = 32; 
	uae_s32 src;
	src = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	src |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 8, 0);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(8);
		exception3_read_access(opcode, dsta, 2, 1);
		return;
	}
	uae_s32 dst = x_get_word(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	dst |= x_get_word(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return;
	}
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(10);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch_opcode(opcode, 10, pcoffset);
		return;
	}
	x_put_word(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(10);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return;
	}
	x_put_word(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(10);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return;
	}
	m68k_incpci(8);
	return;
}
/* 32 (6/2) */
/* 8 0,0   */

/* OR.L #<data>.L,(xxx).L */
void REGPARAM2 op_00b9_14_ff(uae_u32 opcode)
{
	OpcodeFamily = 1;
	CurrentInstrCycles = 36; 
	uae_s32 src;
	src = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	src |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	uaecptr dsta;
	dsta = get_word_ce000_prefetch(8) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 8, -2);
		return;
	}
	dsta |= get_word_ce000_prefetch(10);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 10, pcoffset);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(10);
		exception3_read_access(opcode, dsta, 2, 1);
		return;
	}
	uae_s32 dst = x_get_word(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(10);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	dst |= x_get_word(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(10);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return;
	}
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(12);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch_opcode(opcode, 12, pcoffset);
		return;
	}
	x_put_word(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(12);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return;
	}
	x_put_word(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(12);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return;
	}
	m68k_incpci(10);
	return;
}
/* 36 (7/2) */
/* 10 0,0   */

/* BTST.L Dn,Dn */
void REGPARAM2 op_0100_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 21;
	CurrentInstrCycles = 6;  
	ipl_fetch_next_pre();
	uae_s32 src = m68k_dreg(regs, srcreg);
	uae_s32 dst = m68k_dreg(regs, dstreg);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	src &= 31;
	do_cycles_ce000_internal(2);
	SET_ZFLG(1 ^ ((dst >> src) & 1));
	m68k_incpci(2);
	return;
}
/* 6 (1/0) */
/* 2 0,0   */

/* MVPMR.W (d16,An),Dn */
void REGPARAM2 op_0108_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 29;
	CurrentInstrCycles = 16; 
	uaecptr mempa = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	ipl_fetch_now();
	uae_u16 val  = (x_get_byte(mempa) & 0xff) << 8;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, mempa + 0, 0x0, 1);
		return;
	}
	val |= (x_get_byte(mempa + 2) & 0xff);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, mempa + 2, 0x0, 1);
		return;
	}
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((val) & 0xffff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (4/0) */
/* 4 0,0   */

/* BTST.B Dn,(An) */
void REGPARAM2 op_0110_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 21;
	CurrentInstrCycles = 8;  
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	src &= 7;
	SET_ZFLG(1 ^ ((dst >> src) & 1));
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 8 (2/0) */
/* 2 0,0   */

/* BTST.B Dn,(An)+ */
void REGPARAM2 op_0118_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 21;
	CurrentInstrCycles = 8;  
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
	src &= 7;
	SET_ZFLG(1 ^ ((dst >> src) & 1));
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 8 (2/0) */
/* 2 0,0   */

/* BTST.B Dn,-(An) */
void REGPARAM2 op_0120_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 21;
	CurrentInstrCycles = 10; 
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
	do_cycles_ce000_internal(2);
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, dstreg) = dsta;
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	m68k_areg(regs, dstreg) = dsta;
	src &= 7;
	SET_ZFLG(1 ^ ((dst >> src) & 1));
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 10 (2/0) */
/* 2 0,0   */

/* BTST.B Dn,(d16,An) */
void REGPARAM2 op_0128_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 21;
	CurrentInstrCycles = 12; 
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	src &= 7;
	SET_ZFLG(1 ^ ((dst >> src) & 1));
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 12 (3/0) */
/* 4 0,0   */

/* BTST.B Dn,(d8,An,Xn) */
void REGPARAM2 op_0130_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 21;
	CurrentInstrCycles = 14; 
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	do_cycles_ce000_internal(2);
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	src &= 7;
	SET_ZFLG(1 ^ ((dst >> src) & 1));
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 14 (3/0) */
/* 4 4,0   */

/* BTST.B Dn,(xxx).W */
void REGPARAM2 op_0138_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	OpcodeFamily = 21;
	CurrentInstrCycles = 12; 
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	src &= 7;
	SET_ZFLG(1 ^ ((dst >> src) & 1));
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 12 (3/0) */
/* 4 0,0   */

/* BTST.B Dn,(xxx).L */
void REGPARAM2 op_0139_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	OpcodeFamily = 21;
	CurrentInstrCycles = 16; 
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	dsta |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	src &= 7;
	SET_ZFLG(1 ^ ((dst >> src) & 1));
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 16 (4/0) */
/* 6 0,0   */

/* BTST.B Dn,(d16,PC) */
void REGPARAM2 op_013a_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = 2;
	OpcodeFamily = 21;
	CurrentInstrCycles = 12; 
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_getpci() + 2;
	dsta += (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x0, 2);
		return;
	}
	src &= 7;
	SET_ZFLG(1 ^ ((dst >> src) & 1));
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 12 (3/0) */
/* 4 0,0   */

/* BTST.B Dn,(d8,PC,Xn) */
void REGPARAM2 op_013b_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = 3;
	OpcodeFamily = 21;
	CurrentInstrCycles = 14; 
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	uaecptr tmppc = m68k_getpci() + 2;
	do_cycles_ce000_internal(2);
	dsta = get_disp_ea_000(tmppc, get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x0, 2);
		return;
	}
	src &= 7;
	SET_ZFLG(1 ^ ((dst >> src) & 1));
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 14 (3/0) */
/* 4 4,0   */

/* BTST.B Dn,#<data>.B */
void REGPARAM2 op_013c_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	OpcodeFamily = 21;
	CurrentInstrCycles = 10; 
	uae_s8 src = m68k_dreg(regs, srcreg);
	uae_s8 dst = (uae_u8)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	src &= 7;
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	do_cycles_ce000_internal(2);
	SET_ZFLG(1 ^ ((dst >> src) & 1));
	m68k_incpci(4);
	return;
}
/* 10 (2/0) */
/* 4 0,0   */

/* BCHG.L Dn,Dn */
void REGPARAM2 op_0140_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 22;
	CurrentInstrCycles = 6;  
	uae_s32 src = m68k_dreg(regs, srcreg);
	uae_s32 dst = m68k_dreg(regs, dstreg);
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	src &= 31;
	do_cycles_ce000_internal(2);
	if (src > 15) do_cycles_ce000_internal(2);
	dst ^= (1 << src);
	SET_ZFLG(((uae_u32)dst & (1 << src)) >> src);
	m68k_dreg(regs, dstreg) = (dst);
	m68k_incpci(2);
	return;
}
/* 6 (1/0) */
/* 2 0,0   */

/* MVPMR.L (d16,An),Dn */
void REGPARAM2 op_0148_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 29;
	CurrentInstrCycles = 24; 
	uaecptr mempa = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	uae_u32 val  = (x_get_byte(mempa) & 0xff) << 24;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, mempa + 0, 0x0, 1);
		return;
	}
	val |= (x_get_byte(mempa + 2) & 0xff) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, mempa + 2, 0x0, 1);
		return;
	}
	ipl_fetch_now();
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & 0x0000ffff) | val;
	val |= (x_get_byte(mempa + 4) & 0xff) << 8;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, mempa + 4, 0x0, 1);
		return;
	}
	val |= (x_get_byte(mempa + 6) & 0xff);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, mempa + 6, 0x0, 1);
		return;
	}
	m68k_dreg(regs, dstreg) = (val);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 24 (6/0) */
/* 4 0,0   */

/* BCHG.B Dn,(An) */
void REGPARAM2 op_0150_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 22;
	CurrentInstrCycles = 12; 
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	src &= 7;
	dst ^= (1 << src);
	SET_ZFLG(((uae_u32)dst & (1 << src)) >> src);
	x_put_byte(dsta, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, dst, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 12 (2/1) */
/* 2 0,0   */

/* BCHG.B Dn,(An)+ */
void REGPARAM2 op_0158_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 22;
	CurrentInstrCycles = 12; 
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	src &= 7;
	dst ^= (1 << src);
	SET_ZFLG(((uae_u32)dst & (1 << src)) >> src);
	x_put_byte(dsta, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, dst, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 12 (2/1) */
/* 2 0,0   */

/* BCHG.B Dn,-(An) */
void REGPARAM2 op_0160_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 22;
	CurrentInstrCycles = 14; 
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
	do_cycles_ce000_internal(2);
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, dstreg) = dsta;
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	m68k_areg(regs, dstreg) = dsta;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	src &= 7;
	dst ^= (1 << src);
	SET_ZFLG(((uae_u32)dst & (1 << src)) >> src);
	x_put_byte(dsta, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, dst, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 14 (2/1) */
/* 2 0,0   */

/* BCHG.B Dn,(d16,An) */
void REGPARAM2 op_0168_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 22;
	CurrentInstrCycles = 16; 
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	src &= 7;
	dst ^= (1 << src);
	SET_ZFLG(((uae_u32)dst & (1 << src)) >> src);
	x_put_byte(dsta, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, dst, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* BCHG.B Dn,(d8,An,Xn) */
void REGPARAM2 op_0170_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 22;
	CurrentInstrCycles = 18; 
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	do_cycles_ce000_internal(2);
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	src &= 7;
	dst ^= (1 << src);
	SET_ZFLG(((uae_u32)dst & (1 << src)) >> src);
	x_put_byte(dsta, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, dst, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 18 (3/1) */
/* 4 4,0   */

/* BCHG.B Dn,(xxx).W */
void REGPARAM2 op_0178_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	OpcodeFamily = 22;
	CurrentInstrCycles = 16; 
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	src &= 7;
	dst ^= (1 << src);
	SET_ZFLG(((uae_u32)dst & (1 << src)) >> src);
	x_put_byte(dsta, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, dst, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* BCHG.B Dn,(xxx).L */
void REGPARAM2 op_0179_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	OpcodeFamily = 22;
	CurrentInstrCycles = 20; 
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	dsta |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	opcode = regs.ir;
	src &= 7;
	dst ^= (1 << src);
	SET_ZFLG(((uae_u32)dst & (1 << src)) >> src);
	x_put_byte(dsta, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, dst, 1);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 20 (4/1) */
/* 6 0,0   */

/* BCLR.L Dn,Dn */
void REGPARAM2 op_0180_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 23;
	CurrentInstrCycles = 8;  
	uae_s32 src = m68k_dreg(regs, srcreg);
	uae_s32 dst = m68k_dreg(regs, dstreg);
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	src &= 31;
	do_cycles_ce000_internal(2);
	if (src > 15) do_cycles_ce000_internal(2);
	do_cycles_ce000_internal(2);
	SET_ZFLG(1 ^ ((dst >> src) & 1));
	dst &= ~(1 << src);
	m68k_dreg(regs, dstreg) = (dst);
	m68k_incpci(2);
	return;
}
/* 8 (1/0) */
/* 2 0,0   */

/* MVPRM.W Dn,(d16,An) */
void REGPARAM2 op_0188_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 28;
	CurrentInstrCycles = 16; 
	uae_s16 src = m68k_dreg(regs, srcreg);
	uaecptr mempa = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	x_put_byte(mempa, src >> 8);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_write(opcode, mempa + 0, 0x0, src >> 8, 1);
		return;
	}
	x_put_byte(mempa + 2, src); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_write(opcode, mempa + 2, 0x0, src, 1);
		return;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (2/2) */
/* 4 0,0   */

/* BCLR.B Dn,(An) */
void REGPARAM2 op_0190_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 23;
	CurrentInstrCycles = 12; 
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	src &= 7;
	SET_ZFLG(1 ^ ((dst >> src) & 1));
	dst &= ~(1 << src);
	x_put_byte(dsta, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, dst, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 12 (2/1) */
/* 2 0,0   */

/* BCLR.B Dn,(An)+ */
void REGPARAM2 op_0198_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 23;
	CurrentInstrCycles = 12; 
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	src &= 7;
	SET_ZFLG(1 ^ ((dst >> src) & 1));
	dst &= ~(1 << src);
	x_put_byte(dsta, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, dst, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 12 (2/1) */
/* 2 0,0   */

/* BCLR.B Dn,-(An) */
void REGPARAM2 op_01a0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 23;
	CurrentInstrCycles = 14; 
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
	do_cycles_ce000_internal(2);
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, dstreg) = dsta;
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	m68k_areg(regs, dstreg) = dsta;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	src &= 7;
	SET_ZFLG(1 ^ ((dst >> src) & 1));
	dst &= ~(1 << src);
	x_put_byte(dsta, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, dst, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 14 (2/1) */
/* 2 0,0   */

/* BCLR.B Dn,(d16,An) */
void REGPARAM2 op_01a8_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 23;
	CurrentInstrCycles = 16; 
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	src &= 7;
	SET_ZFLG(1 ^ ((dst >> src) & 1));
	dst &= ~(1 << src);
	x_put_byte(dsta, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, dst, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* BCLR.B Dn,(d8,An,Xn) */
void REGPARAM2 op_01b0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 23;
	CurrentInstrCycles = 18; 
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	do_cycles_ce000_internal(2);
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	src &= 7;
	SET_ZFLG(1 ^ ((dst >> src) & 1));
	dst &= ~(1 << src);
	x_put_byte(dsta, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, dst, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 18 (3/1) */
/* 4 4,0   */

/* BCLR.B Dn,(xxx).W */
void REGPARAM2 op_01b8_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	OpcodeFamily = 23;
	CurrentInstrCycles = 16; 
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	src &= 7;
	SET_ZFLG(1 ^ ((dst >> src) & 1));
	dst &= ~(1 << src);
	x_put_byte(dsta, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, dst, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* BCLR.B Dn,(xxx).L */
void REGPARAM2 op_01b9_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	OpcodeFamily = 23;
	CurrentInstrCycles = 20; 
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	dsta |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	opcode = regs.ir;
	src &= 7;
	SET_ZFLG(1 ^ ((dst >> src) & 1));
	dst &= ~(1 << src);
	x_put_byte(dsta, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, dst, 1);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 20 (4/1) */
/* 6 0,0   */

/* BSET.L Dn,Dn */
void REGPARAM2 op_01c0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 24;
	CurrentInstrCycles = 6;  
	uae_s32 src = m68k_dreg(regs, srcreg);
	uae_s32 dst = m68k_dreg(regs, dstreg);
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	src &= 31;
	do_cycles_ce000_internal(2);
	if (src > 15) do_cycles_ce000_internal(2);
	SET_ZFLG(1 ^ ((dst >> src) & 1));
	dst |= (1 << src);
	m68k_dreg(regs, dstreg) = (dst);
	m68k_incpci(2);
	return;
}
/* 6 (1/0) */
/* 2 0,0   */

/* MVPRM.L Dn,(d16,An) */
void REGPARAM2 op_01c8_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 28;
	CurrentInstrCycles = 24; 
	uae_s32 src = m68k_dreg(regs, srcreg);
	uaecptr mempa = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	x_put_byte(mempa, src >> 24);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_write(opcode, mempa + 0, 0x0, src >> 24, 1);
		return;
	}
	x_put_byte(mempa + 2, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_write(opcode, mempa + 2, 0x0, src >> 16, 1);
		return;
	}
	x_put_byte(mempa + 4, src >> 8);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_write(opcode, mempa + 4, 0x0, src >> 8, 1);
		return;
	}
	x_put_byte(mempa + 6, src); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_write(opcode, mempa + 6, 0x0, src, 1);
		return;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 24 (2/4) */
/* 4 0,0   */

/* BSET.B Dn,(An) */
void REGPARAM2 op_01d0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 24;
	CurrentInstrCycles = 12; 
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	src &= 7;
	SET_ZFLG(1 ^ ((dst >> src) & 1));
	dst |= (1 << src);
	x_put_byte(dsta, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, dst, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 12 (2/1) */
/* 2 0,0   */

/* BSET.B Dn,(An)+ */
void REGPARAM2 op_01d8_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 24;
	CurrentInstrCycles = 12; 
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	src &= 7;
	SET_ZFLG(1 ^ ((dst >> src) & 1));
	dst |= (1 << src);
	x_put_byte(dsta, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, dst, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 12 (2/1) */
/* 2 0,0   */

/* BSET.B Dn,-(An) */
void REGPARAM2 op_01e0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 24;
	CurrentInstrCycles = 14; 
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
	do_cycles_ce000_internal(2);
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, dstreg) = dsta;
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	m68k_areg(regs, dstreg) = dsta;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	src &= 7;
	SET_ZFLG(1 ^ ((dst >> src) & 1));
	dst |= (1 << src);
	x_put_byte(dsta, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, dst, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 14 (2/1) */
/* 2 0,0   */

/* BSET.B Dn,(d16,An) */
void REGPARAM2 op_01e8_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 24;
	CurrentInstrCycles = 16; 
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	src &= 7;
	SET_ZFLG(1 ^ ((dst >> src) & 1));
	dst |= (1 << src);
	x_put_byte(dsta, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, dst, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* BSET.B Dn,(d8,An,Xn) */
void REGPARAM2 op_01f0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 24;
	CurrentInstrCycles = 18; 
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	do_cycles_ce000_internal(2);
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	src &= 7;
	SET_ZFLG(1 ^ ((dst >> src) & 1));
	dst |= (1 << src);
	x_put_byte(dsta, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, dst, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 18 (3/1) */
/* 4 4,0   */

/* BSET.B Dn,(xxx).W */
void REGPARAM2 op_01f8_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	OpcodeFamily = 24;
	CurrentInstrCycles = 16; 
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	src &= 7;
	SET_ZFLG(1 ^ ((dst >> src) & 1));
	dst |= (1 << src);
	x_put_byte(dsta, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, dst, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* BSET.B Dn,(xxx).L */
void REGPARAM2 op_01f9_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	OpcodeFamily = 24;
	CurrentInstrCycles = 20; 
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	dsta |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	opcode = regs.ir;
	src &= 7;
	SET_ZFLG(1 ^ ((dst >> src) & 1));
	dst |= (1 << src);
	x_put_byte(dsta, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, dst, 1);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 20 (4/1) */
/* 6 0,0   */

/* AND.B #<data>.B,Dn */
void REGPARAM2 op_0200_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 8;  
	uae_s8 src = (uae_u8)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uae_s8 dst = m68k_dreg(regs, dstreg);
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 8 (2/0) */
/* 4 0,0   */

/* AND.B #<data>.B,(An) */
void REGPARAM2 op_0210_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 16; 
	uae_s8 src = (uae_u8)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_byte(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* AND.B #<data>.B,(An)+ */
void REGPARAM2 op_0218_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 16; 
	uae_s8 src = (uae_u8)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_byte(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* AND.B #<data>.B,-(An) */
void REGPARAM2 op_0220_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 18; 
	uae_s8 src = (uae_u8)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
	do_cycles_ce000_internal(2);
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		m68k_areg(regs, dstreg) = dsta;
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	m68k_areg(regs, dstreg) = dsta;
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_byte(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 18 (3/1) */
/* 4 0,0   */

/* AND.B #<data>.B,(d16,An) */
void REGPARAM2 op_0228_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 20; 
	uae_s8 src = (uae_u8)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return;
	}
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_byte(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 20 (4/1) */
/* 6 0,0   */

/* AND.B #<data>.B,(d8,An,Xn) */
void REGPARAM2 op_0230_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 22; 
	uae_s8 src = (uae_u8)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr dsta;
	do_cycles_ce000_internal(2);
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_ce000_prefetch(6));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return;
	}
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_byte(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 22 (4/1) */
/* 6 4,0   */

/* AND.B #<data>.B,(xxx).W */
void REGPARAM2 op_0238_14_ff(uae_u32 opcode)
{
	OpcodeFamily = 2;
	CurrentInstrCycles = 20; 
	uae_s8 src = (uae_u8)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, 0);
		return;
	}
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_byte(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 20 (4/1) */
/* 6 0,0   */

/* AND.B #<data>.B,(xxx).L */
void REGPARAM2 op_0239_14_ff(uae_u32 opcode)
{
	OpcodeFamily = 2;
	CurrentInstrCycles = 24; 
	uae_s8 src = (uae_u8)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr dsta;
	dsta = get_word_ce000_prefetch(6) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return;
	}
	dsta |= get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 8, pcoffset);
		return;
	}
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(10);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 10, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_byte(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(10);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return;
	}
	m68k_incpci(8);
	return;
}
/* 24 (5/1) */
/* 8 0,0   */

/* ANDSR.B #<data>.W */
void REGPARAM2 op_023c_14_ff(uae_u32 opcode)
{
	OpcodeFamily = 5;
	CurrentInstrCycles = 20; 
	MakeSR();
	int t1 = regs.t1;
	uae_s16 src = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	src &= 0xFF;
	src |= 0xff00;
	do_cycles_ce000_internal(8);
	regs.sr &= src;
	MakeFromSR();
	m68k_incpci(4);
	get_word_ce000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, 0);
		return;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	if(t1) opcode |= 0x10000;
	ipl_fetch_next();
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 20 (3/0) */
/* 4 0,0   */

/* AND.W #<data>.W,Dn */
void REGPARAM2 op_0240_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 8;  
	uae_s16 src = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 8 (2/0) */
/* 4 0,0   */

/* AND.W #<data>.W,(An) */
void REGPARAM2 op_0250_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 16; 
	uae_s16 src = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	if (dsta & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, dsta, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 dst = x_get_word(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_word(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* AND.W #<data>.W,(An)+ */
void REGPARAM2 op_0258_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 16; 
	uae_s16 src = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	if (dsta & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, dsta, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 dst = x_get_word(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, dstreg) += 2 + 0;
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	m68k_areg(regs, dstreg) += 2;
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_word(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* AND.W #<data>.W,-(An) */
void REGPARAM2 op_0260_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 18; 
	uae_s16 src = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - 2;
	do_cycles_ce000_internal(2);
	if (dsta & 1) {
		m68k_incpci(6);
		m68k_areg(regs, dstreg) = dsta;
		exception3_read_access(opcode, dsta, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 dst = x_get_word(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		m68k_areg(regs, dstreg) = dsta;
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	m68k_areg(regs, dstreg) = dsta;
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_word(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 18 (3/1) */
/* 4 0,0   */

/* AND.W #<data>.W,(d16,An) */
void REGPARAM2 op_0268_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 20; 
	uae_s16 src = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, dsta, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 dst = x_get_word(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_word(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 20 (4/1) */
/* 6 0,0   */

/* AND.W #<data>.W,(d8,An,Xn) */
void REGPARAM2 op_0270_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 22; 
	uae_s16 src = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr dsta;
	do_cycles_ce000_internal(2);
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_ce000_prefetch(6));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, dsta, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 dst = x_get_word(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_word(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 22 (4/1) */
/* 6 4,0   */

/* AND.W #<data>.W,(xxx).W */
void REGPARAM2 op_0278_14_ff(uae_u32 opcode)
{
	OpcodeFamily = 2;
	CurrentInstrCycles = 20; 
	uae_s16 src = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, 0);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, dsta, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 dst = x_get_word(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_word(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 20 (4/1) */
/* 6 0,0   */

/* AND.W #<data>.W,(xxx).L */
void REGPARAM2 op_0279_14_ff(uae_u32 opcode)
{
	OpcodeFamily = 2;
	CurrentInstrCycles = 24; 
	uae_s16 src = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr dsta;
	dsta = get_word_ce000_prefetch(6) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return;
	}
	dsta |= get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 8, pcoffset);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(8);
		exception3_read_access(opcode, dsta, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 dst = x_get_word(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(10);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 10, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_word(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(10);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return;
	}
	m68k_incpci(8);
	return;
}
/* 24 (5/1) */
/* 8 0,0   */

/* ANDSR.W #<data>.W */
void REGPARAM2 op_027c_14_ff(uae_u32 opcode)
{
	OpcodeFamily = 5;
	CurrentInstrCycles = 20; 
	if (!regs.s) {
		Exception(8);
		return;
	}
	MakeSR();
	int t1 = regs.t1;
	uae_s16 src = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	do_cycles_ce000_internal(8);
	regs.sr &= src;
	MakeFromSR();
	m68k_incpci(4);
	get_word_ce000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, 0);
		return;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	if(t1) opcode |= 0x10000;
	ipl_fetch_next();
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 20 (3/0) */
/* 4 0,0   */

/* AND.L #<data>.L,Dn */
void REGPARAM2 op_0280_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 16; 
	uae_s32 src;
	src = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	src |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		dreg_68000_long_replace_low(dstreg, src);
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	opcode = regs.ir;
	do_cycles_ce000_internal(4);
	m68k_dreg(regs, dstreg) = (src);
	m68k_incpci(6);
	return;
}
/* 16 (3/0) */
/* 6 0,0   */

/* AND.L #<data>.L,(An) */
void REGPARAM2 op_0290_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 28; 
	uae_s32 src;
	src = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	src |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	if (dsta & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, dsta, 2, 1);
		return;
	}
	uae_s32 dst = x_get_word(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	dst |= x_get_word(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return;
	}
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	x_put_word(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return;
	}
	x_put_word(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 28 (5/2) */
/* 6 0,0   */

/* AND.L #<data>.L,(An)+ */
void REGPARAM2 op_0298_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 28; 
	uae_s32 src;
	src = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	src |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	if (dsta & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, dsta, 2, 1);
		return;
	}
	uae_s32 dst = x_get_word(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	dst |= x_get_word(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return;
	}
	m68k_areg(regs, dstreg) += 4;
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	x_put_word(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return;
	}
	x_put_word(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 28 (5/2) */
/* 6 0,0   */

/* AND.L #<data>.L,-(An) */
void REGPARAM2 op_02a0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 30; 
	uae_s32 src;
	src = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	src |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - 4;
	do_cycles_ce000_internal(2);
	if (dsta & 1) {
		m68k_incpci(6);
		m68k_areg(regs, dstreg) = dsta;
		exception3_read_access(opcode, dsta, 2, 1);
		return;
	}
	uae_s32 dst = x_get_word(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		m68k_areg(regs, dstreg) = dsta;
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	dst |= x_get_word(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		m68k_areg(regs, dstreg) = dsta;
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return;
	}
	m68k_areg(regs, dstreg) = dsta;
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	x_put_word(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return;
	}
	x_put_word(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 30 (5/2) */
/* 6 0,0   */

/* AND.L #<data>.L,(d16,An) */
void REGPARAM2 op_02a8_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 32; 
	uae_s32 src;
	src = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	src |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 8, -2);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, dsta, 2, 1);
		return;
	}
	uae_s32 dst = x_get_word(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	dst |= x_get_word(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return;
	}
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(10);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch_opcode(opcode, 10, pcoffset);
		return;
	}
	x_put_word(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(10);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return;
	}
	x_put_word(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(10);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return;
	}
	m68k_incpci(8);
	return;
}
/* 32 (6/2) */
/* 8 0,0   */

/* AND.L #<data>.L,(d8,An,Xn) */
void REGPARAM2 op_02b0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 34; 
	uae_s32 src;
	src = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	src |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	uaecptr dsta;
	do_cycles_ce000_internal(2);
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_ce000_prefetch(8));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 8, -2);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, dsta, 2, 1);
		return;
	}
	uae_s32 dst = x_get_word(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	dst |= x_get_word(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return;
	}
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(10);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch_opcode(opcode, 10, pcoffset);
		return;
	}
	x_put_word(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(10);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return;
	}
	x_put_word(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(10);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return;
	}
	m68k_incpci(8);
	return;
}
/* 34 (6/2) */
/* 8 4,0   */

/* AND.L #<data>.L,(xxx).W */
void REGPARAM2 op_02b8_14_ff(uae_u32 opcode)
{
	OpcodeFamily = 2;
	CurrentInstrCycles = 32; 
	uae_s32 src;
	src = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	src |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 8, 0);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(8);
		exception3_read_access(opcode, dsta, 2, 1);
		return;
	}
	uae_s32 dst = x_get_word(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	dst |= x_get_word(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return;
	}
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(10);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch_opcode(opcode, 10, pcoffset);
		return;
	}
	x_put_word(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(10);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return;
	}
	x_put_word(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(10);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return;
	}
	m68k_incpci(8);
	return;
}
/* 32 (6/2) */
/* 8 0,0   */

/* AND.L #<data>.L,(xxx).L */
void REGPARAM2 op_02b9_14_ff(uae_u32 opcode)
{
	OpcodeFamily = 2;
	CurrentInstrCycles = 36; 
	uae_s32 src;
	src = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	src |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	uaecptr dsta;
	dsta = get_word_ce000_prefetch(8) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 8, -2);
		return;
	}
	dsta |= get_word_ce000_prefetch(10);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 10, pcoffset);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(10);
		exception3_read_access(opcode, dsta, 2, 1);
		return;
	}
	uae_s32 dst = x_get_word(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(10);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	dst |= x_get_word(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(10);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return;
	}
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(12);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch_opcode(opcode, 12, pcoffset);
		return;
	}
	x_put_word(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(12);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return;
	}
	x_put_word(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(12);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return;
	}
	m68k_incpci(10);
	return;
}
/* 36 (7/2) */
/* 10 0,0   */

/* SUB.B #<data>.B,Dn */
void REGPARAM2 op_0400_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 8;  
	uae_s8 src = (uae_u8)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uae_s8 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 8 (2/0) */
/* 4 0,0   */

/* SUB.B #<data>.B,(An) */
void REGPARAM2 op_0410_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 16; 
	uae_s8 src = (uae_u8)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_byte(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, newv, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* SUB.B #<data>.B,(An)+ */
void REGPARAM2 op_0418_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 16; 
	uae_s8 src = (uae_u8)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
	uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_byte(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, newv, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* SUB.B #<data>.B,-(An) */
void REGPARAM2 op_0420_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 18; 
	uae_s8 src = (uae_u8)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
	do_cycles_ce000_internal(2);
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		m68k_areg(regs, dstreg) = dsta;
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	m68k_areg(regs, dstreg) = dsta;
	uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_byte(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, newv, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 18 (3/1) */
/* 4 0,0   */

/* SUB.B #<data>.B,(d16,An) */
void REGPARAM2 op_0428_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 20; 
	uae_s8 src = (uae_u8)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return;
	}
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_byte(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, newv, 1);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 20 (4/1) */
/* 6 0,0   */

/* SUB.B #<data>.B,(d8,An,Xn) */
void REGPARAM2 op_0430_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 22; 
	uae_s8 src = (uae_u8)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr dsta;
	do_cycles_ce000_internal(2);
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_ce000_prefetch(6));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return;
	}
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_byte(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, newv, 1);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 22 (4/1) */
/* 6 4,0   */

/* SUB.B #<data>.B,(xxx).W */
void REGPARAM2 op_0438_14_ff(uae_u32 opcode)
{
	OpcodeFamily = 7;
	CurrentInstrCycles = 20; 
	uae_s8 src = (uae_u8)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, 0);
		return;
	}
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_byte(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, newv, 1);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 20 (4/1) */
/* 6 0,0   */

/* SUB.B #<data>.B,(xxx).L */
void REGPARAM2 op_0439_14_ff(uae_u32 opcode)
{
	OpcodeFamily = 7;
	CurrentInstrCycles = 24; 
	uae_s8 src = (uae_u8)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr dsta;
	dsta = get_word_ce000_prefetch(6) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return;
	}
	dsta |= get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 8, pcoffset);
		return;
	}
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(10);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 10, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_byte(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(10);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, newv, 1);
		return;
	}
	m68k_incpci(8);
	return;
}
/* 24 (5/1) */
/* 8 0,0   */

/* SUB.W #<data>.W,Dn */
void REGPARAM2 op_0440_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 8;  
	uae_s16 src = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 8 (2/0) */
/* 4 0,0   */

/* SUB.W #<data>.W,(An) */
void REGPARAM2 op_0450_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 16; 
	uae_s16 src = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	if (dsta & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, dsta, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 dst = x_get_word(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_word(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x1, newv, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* SUB.W #<data>.W,(An)+ */
void REGPARAM2 op_0458_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 16; 
	uae_s16 src = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	if (dsta & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, dsta, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 dst = x_get_word(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, dstreg) += 2 + 0;
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	m68k_areg(regs, dstreg) += 2;
	uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_word(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x1, newv, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* SUB.W #<data>.W,-(An) */
void REGPARAM2 op_0460_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 18; 
	uae_s16 src = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - 2;
	do_cycles_ce000_internal(2);
	if (dsta & 1) {
		m68k_incpci(6);
		m68k_areg(regs, dstreg) = dsta;
		exception3_read_access(opcode, dsta, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 dst = x_get_word(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		m68k_areg(regs, dstreg) = dsta;
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	m68k_areg(regs, dstreg) = dsta;
	uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_word(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x1, newv, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 18 (3/1) */
/* 4 0,0   */

/* SUB.W #<data>.W,(d16,An) */
void REGPARAM2 op_0468_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 20; 
	uae_s16 src = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, dsta, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 dst = x_get_word(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_word(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x1, newv, 1);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 20 (4/1) */
/* 6 0,0   */

/* SUB.W #<data>.W,(d8,An,Xn) */
void REGPARAM2 op_0470_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 22; 
	uae_s16 src = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr dsta;
	do_cycles_ce000_internal(2);
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_ce000_prefetch(6));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, dsta, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 dst = x_get_word(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_word(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x1, newv, 1);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 22 (4/1) */
/* 6 4,0   */

/* SUB.W #<data>.W,(xxx).W */
void REGPARAM2 op_0478_14_ff(uae_u32 opcode)
{
	OpcodeFamily = 7;
	CurrentInstrCycles = 20; 
	uae_s16 src = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, 0);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, dsta, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 dst = x_get_word(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_word(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x1, newv, 1);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 20 (4/1) */
/* 6 0,0   */

/* SUB.W #<data>.W,(xxx).L */
void REGPARAM2 op_0479_14_ff(uae_u32 opcode)
{
	OpcodeFamily = 7;
	CurrentInstrCycles = 24; 
	uae_s16 src = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr dsta;
	dsta = get_word_ce000_prefetch(6) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return;
	}
	dsta |= get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 8, pcoffset);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(8);
		exception3_read_access(opcode, dsta, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 dst = x_get_word(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(10);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 10, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_word(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(10);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x1, newv, 1);
		return;
	}
	m68k_incpci(8);
	return;
}
/* 24 (5/1) */
/* 8 0,0   */

/* SUB.L #<data>.L,Dn */
void REGPARAM2 op_0480_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 16; 
	uae_s32 src;
	src = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	ipl_fetch_now();
	src |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		uae_s16 bnewv = (uae_s16)dst - (uae_s16)src;
		int bflgs = ((uae_s16)(src)) < 0;
		int bflgo = ((uae_s16)(dst)) < 0;
		int bflgn = bnewv < 0;
		ccr_68000_long_move_ae_LZN(bnewv);
		SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
		SET_XFLG(GET_CFLG());
		SET_VFLG((bflgs ^ bflgo) & (bflgn ^ bflgo));
		dreg_68000_long_replace_low(dstreg, bnewv);
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	opcode = regs.ir;
	do_cycles_ce000_internal(4);
	m68k_dreg(regs, dstreg) = (newv);
	m68k_incpci(6);
	return;
}
/* 16 (3/0) */
/* 6 0,0   */

/* SUB.L #<data>.L,(An) */
void REGPARAM2 op_0490_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 28; 
	uae_s32 src;
	src = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	src |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	if (dsta & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, dsta, 2, 1);
		return;
	}
	uae_s32 dst = x_get_word(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	dst |= x_get_word(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return;
	}
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		uae_s16 bnewv = (uae_s16)dst - (uae_s16)src;
		int bflgs = ((uae_s16)(src)) < 0;
		int bflgo = ((uae_s16)(dst)) < 0;
		int bflgn = bnewv < 0;
		ccr_68000_long_move_ae_LZN(bnewv);
		SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
		SET_XFLG(GET_CFLG());
		SET_VFLG((bflgs ^ bflgo) & (bflgn ^ bflgo));
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	x_put_word(dsta + 2, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 2, 0x1, newv, 1);
		return;
	}
	x_put_word(dsta, newv >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 0, 0x1, newv >> 16, 1);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 28 (5/2) */
/* 6 0,0   */

/* SUB.L #<data>.L,(An)+ */
void REGPARAM2 op_0498_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 28; 
	uae_s32 src;
	src = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	src |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	if (dsta & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, dsta, 2, 1);
		return;
	}
	uae_s32 dst = x_get_word(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	dst |= x_get_word(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return;
	}
	m68k_areg(regs, dstreg) += 4;
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		uae_s16 bnewv = (uae_s16)dst - (uae_s16)src;
		int bflgs = ((uae_s16)(src)) < 0;
		int bflgo = ((uae_s16)(dst)) < 0;
		int bflgn = bnewv < 0;
		ccr_68000_long_move_ae_LZN(bnewv);
		SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
		SET_XFLG(GET_CFLG());
		SET_VFLG((bflgs ^ bflgo) & (bflgn ^ bflgo));
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	x_put_word(dsta + 2, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 2, 0x1, newv, 1);
		return;
	}
	x_put_word(dsta, newv >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 0, 0x1, newv >> 16, 1);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 28 (5/2) */
/* 6 0,0   */

/* SUB.L #<data>.L,-(An) */
void REGPARAM2 op_04a0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 30; 
	uae_s32 src;
	src = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	src |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - 4;
	do_cycles_ce000_internal(2);
	if (dsta & 1) {
		m68k_incpci(6);
		m68k_areg(regs, dstreg) = dsta;
		exception3_read_access(opcode, dsta, 2, 1);
		return;
	}
	uae_s32 dst = x_get_word(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		m68k_areg(regs, dstreg) = dsta;
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	dst |= x_get_word(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		m68k_areg(regs, dstreg) = dsta;
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return;
	}
	m68k_areg(regs, dstreg) = dsta;
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		uae_s16 bnewv = (uae_s16)dst - (uae_s16)src;
		int bflgs = ((uae_s16)(src)) < 0;
		int bflgo = ((uae_s16)(dst)) < 0;
		int bflgn = bnewv < 0;
		ccr_68000_long_move_ae_LZN(bnewv);
		SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
		SET_XFLG(GET_CFLG());
		SET_VFLG((bflgs ^ bflgo) & (bflgn ^ bflgo));
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	x_put_word(dsta + 2, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 2, 0x1, newv, 1);
		return;
	}
	x_put_word(dsta, newv >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 0, 0x1, newv >> 16, 1);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 30 (5/2) */
/* 6 0,0   */

/* SUB.L #<data>.L,(d16,An) */
void REGPARAM2 op_04a8_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 32; 
	uae_s32 src;
	src = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	src |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 8, -2);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, dsta, 2, 1);
		return;
	}
	uae_s32 dst = x_get_word(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	dst |= x_get_word(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return;
	}
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(10);
	if(hardware_bus_error) {
		int pcoffset = 0;
		uae_s16 bnewv = (uae_s16)dst - (uae_s16)src;
		int bflgs = ((uae_s16)(src)) < 0;
		int bflgo = ((uae_s16)(dst)) < 0;
		int bflgn = bnewv < 0;
		ccr_68000_long_move_ae_LZN(bnewv);
		SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
		SET_XFLG(GET_CFLG());
		SET_VFLG((bflgs ^ bflgo) & (bflgn ^ bflgo));
		exception2_fetch_opcode(opcode, 10, pcoffset);
		return;
	}
	x_put_word(dsta + 2, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(10);
		exception2_write(opcode, dsta + 2, 0x1, newv, 1);
		return;
	}
	x_put_word(dsta, newv >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(10);
		exception2_write(opcode, dsta + 0, 0x1, newv >> 16, 1);
		return;
	}
	m68k_incpci(8);
	return;
}
/* 32 (6/2) */
/* 8 0,0   */

/* SUB.L #<data>.L,(d8,An,Xn) */
void REGPARAM2 op_04b0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 34; 
	uae_s32 src;
	src = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	src |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	uaecptr dsta;
	do_cycles_ce000_internal(2);
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_ce000_prefetch(8));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 8, -2);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, dsta, 2, 1);
		return;
	}
	uae_s32 dst = x_get_word(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	dst |= x_get_word(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return;
	}
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(10);
	if(hardware_bus_error) {
		int pcoffset = 0;
		uae_s16 bnewv = (uae_s16)dst - (uae_s16)src;
		int bflgs = ((uae_s16)(src)) < 0;
		int bflgo = ((uae_s16)(dst)) < 0;
		int bflgn = bnewv < 0;
		ccr_68000_long_move_ae_LZN(bnewv);
		SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
		SET_XFLG(GET_CFLG());
		SET_VFLG((bflgs ^ bflgo) & (bflgn ^ bflgo));
		exception2_fetch_opcode(opcode, 10, pcoffset);
		return;
	}
	x_put_word(dsta + 2, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(10);
		exception2_write(opcode, dsta + 2, 0x1, newv, 1);
		return;
	}
	x_put_word(dsta, newv >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(10);
		exception2_write(opcode, dsta + 0, 0x1, newv >> 16, 1);
		return;
	}
	m68k_incpci(8);
	return;
}
/* 34 (6/2) */
/* 8 4,0   */

/* SUB.L #<data>.L,(xxx).W */
void REGPARAM2 op_04b8_14_ff(uae_u32 opcode)
{
	OpcodeFamily = 7;
	CurrentInstrCycles = 32; 
	uae_s32 src;
	src = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	src |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 8, 0);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(8);
		exception3_read_access(opcode, dsta, 2, 1);
		return;
	}
	uae_s32 dst = x_get_word(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	dst |= x_get_word(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return;
	}
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(10);
	if(hardware_bus_error) {
		int pcoffset = 0;
		uae_s16 bnewv = (uae_s16)dst - (uae_s16)src;
		int bflgs = ((uae_s16)(src)) < 0;
		int bflgo = ((uae_s16)(dst)) < 0;
		int bflgn = bnewv < 0;
		ccr_68000_long_move_ae_LZN(bnewv);
		SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
		SET_XFLG(GET_CFLG());
		SET_VFLG((bflgs ^ bflgo) & (bflgn ^ bflgo));
		exception2_fetch_opcode(opcode, 10, pcoffset);
		return;
	}
	x_put_word(dsta + 2, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(10);
		exception2_write(opcode, dsta + 2, 0x1, newv, 1);
		return;
	}
	x_put_word(dsta, newv >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(10);
		exception2_write(opcode, dsta + 0, 0x1, newv >> 16, 1);
		return;
	}
	m68k_incpci(8);
	return;
}
/* 32 (6/2) */
/* 8 0,0   */

/* SUB.L #<data>.L,(xxx).L */
void REGPARAM2 op_04b9_14_ff(uae_u32 opcode)
{
	OpcodeFamily = 7;
	CurrentInstrCycles = 36; 
	uae_s32 src;
	src = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	src |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	uaecptr dsta;
	dsta = get_word_ce000_prefetch(8) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 8, -2);
		return;
	}
	dsta |= get_word_ce000_prefetch(10);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 10, pcoffset);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(10);
		exception3_read_access(opcode, dsta, 2, 1);
		return;
	}
	uae_s32 dst = x_get_word(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(10);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	dst |= x_get_word(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(10);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return;
	}
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(12);
	if(hardware_bus_error) {
		int pcoffset = 0;
		uae_s16 bnewv = (uae_s16)dst - (uae_s16)src;
		int bflgs = ((uae_s16)(src)) < 0;
		int bflgo = ((uae_s16)(dst)) < 0;
		int bflgn = bnewv < 0;
		ccr_68000_long_move_ae_LZN(bnewv);
		SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
		SET_XFLG(GET_CFLG());
		SET_VFLG((bflgs ^ bflgo) & (bflgn ^ bflgo));
		exception2_fetch_opcode(opcode, 12, pcoffset);
		return;
	}
	x_put_word(dsta + 2, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(12);
		exception2_write(opcode, dsta + 2, 0x1, newv, 1);
		return;
	}
	x_put_word(dsta, newv >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(12);
		exception2_write(opcode, dsta + 0, 0x1, newv >> 16, 1);
		return;
	}
	m68k_incpci(10);
	return;
}
/* 36 (7/2) */
/* 10 0,0   */

/* ADD.B #<data>.B,Dn */
void REGPARAM2 op_0600_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 8;  
	uae_s8 src = (uae_u8)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uae_s8 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u8)(~dst)) < ((uae_u8)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 8 (2/0) */
/* 4 0,0   */

/* ADD.B #<data>.B,(An) */
void REGPARAM2 op_0610_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 16; 
	uae_s8 src = (uae_u8)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u8)(~dst)) < ((uae_u8)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_byte(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, newv, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* ADD.B #<data>.B,(An)+ */
void REGPARAM2 op_0618_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 16; 
	uae_s8 src = (uae_u8)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
	uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u8)(~dst)) < ((uae_u8)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_byte(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, newv, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* ADD.B #<data>.B,-(An) */
void REGPARAM2 op_0620_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 18; 
	uae_s8 src = (uae_u8)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
	do_cycles_ce000_internal(2);
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		m68k_areg(regs, dstreg) = dsta;
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	m68k_areg(regs, dstreg) = dsta;
	uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u8)(~dst)) < ((uae_u8)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_byte(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, newv, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 18 (3/1) */
/* 4 0,0   */

/* ADD.B #<data>.B,(d16,An) */
void REGPARAM2 op_0628_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 20; 
	uae_s8 src = (uae_u8)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return;
	}
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u8)(~dst)) < ((uae_u8)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_byte(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, newv, 1);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 20 (4/1) */
/* 6 0,0   */

/* ADD.B #<data>.B,(d8,An,Xn) */
void REGPARAM2 op_0630_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 22; 
	uae_s8 src = (uae_u8)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr dsta;
	do_cycles_ce000_internal(2);
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_ce000_prefetch(6));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return;
	}
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u8)(~dst)) < ((uae_u8)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_byte(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, newv, 1);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 22 (4/1) */
/* 6 4,0   */

/* ADD.B #<data>.B,(xxx).W */
void REGPARAM2 op_0638_14_ff(uae_u32 opcode)
{
	OpcodeFamily = 11;
	CurrentInstrCycles = 20; 
	uae_s8 src = (uae_u8)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, 0);
		return;
	}
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u8)(~dst)) < ((uae_u8)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_byte(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, newv, 1);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 20 (4/1) */
/* 6 0,0   */

/* ADD.B #<data>.B,(xxx).L */
void REGPARAM2 op_0639_14_ff(uae_u32 opcode)
{
	OpcodeFamily = 11;
	CurrentInstrCycles = 24; 
	uae_s8 src = (uae_u8)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr dsta;
	dsta = get_word_ce000_prefetch(6) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return;
	}
	dsta |= get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 8, pcoffset);
		return;
	}
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u8)(~dst)) < ((uae_u8)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(10);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 10, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_byte(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(10);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, newv, 1);
		return;
	}
	m68k_incpci(8);
	return;
}
/* 24 (5/1) */
/* 8 0,0   */

/* ADD.W #<data>.W,Dn */
void REGPARAM2 op_0640_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 8;  
	uae_s16 src = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 8 (2/0) */
/* 4 0,0   */

/* ADD.W #<data>.W,(An) */
void REGPARAM2 op_0650_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 16; 
	uae_s16 src = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	if (dsta & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, dsta, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 dst = x_get_word(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_word(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x1, newv, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* ADD.W #<data>.W,(An)+ */
void REGPARAM2 op_0658_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 16; 
	uae_s16 src = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	if (dsta & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, dsta, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 dst = x_get_word(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, dstreg) += 2 + 0;
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	m68k_areg(regs, dstreg) += 2;
	uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_word(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x1, newv, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* ADD.W #<data>.W,-(An) */
void REGPARAM2 op_0660_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 18; 
	uae_s16 src = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - 2;
	do_cycles_ce000_internal(2);
	if (dsta & 1) {
		m68k_incpci(6);
		m68k_areg(regs, dstreg) = dsta;
		exception3_read_access(opcode, dsta, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 dst = x_get_word(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		m68k_areg(regs, dstreg) = dsta;
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	m68k_areg(regs, dstreg) = dsta;
	uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_word(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x1, newv, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 18 (3/1) */
/* 4 0,0   */

/* ADD.W #<data>.W,(d16,An) */
void REGPARAM2 op_0668_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 20; 
	uae_s16 src = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, dsta, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 dst = x_get_word(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_word(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x1, newv, 1);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 20 (4/1) */
/* 6 0,0   */

/* ADD.W #<data>.W,(d8,An,Xn) */
void REGPARAM2 op_0670_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 22; 
	uae_s16 src = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr dsta;
	do_cycles_ce000_internal(2);
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_ce000_prefetch(6));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, dsta, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 dst = x_get_word(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_word(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x1, newv, 1);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 22 (4/1) */
/* 6 4,0   */

/* ADD.W #<data>.W,(xxx).W */
void REGPARAM2 op_0678_14_ff(uae_u32 opcode)
{
	OpcodeFamily = 11;
	CurrentInstrCycles = 20; 
	uae_s16 src = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, 0);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, dsta, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 dst = x_get_word(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_word(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x1, newv, 1);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 20 (4/1) */
/* 6 0,0   */

/* ADD.W #<data>.W,(xxx).L */
void REGPARAM2 op_0679_14_ff(uae_u32 opcode)
{
	OpcodeFamily = 11;
	CurrentInstrCycles = 24; 
	uae_s16 src = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr dsta;
	dsta = get_word_ce000_prefetch(6) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return;
	}
	dsta |= get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 8, pcoffset);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(8);
		exception3_read_access(opcode, dsta, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 dst = x_get_word(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(10);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 10, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_word(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(10);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x1, newv, 1);
		return;
	}
	m68k_incpci(8);
	return;
}
/* 24 (5/1) */
/* 8 0,0   */

/* ADD.L #<data>.L,Dn */
void REGPARAM2 op_0680_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 16; 
	uae_s32 src;
	src = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	ipl_fetch_now();
	src |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u32)(~dst)) < ((uae_u32)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		uae_s16 bnewv = (uae_s16)dst + (uae_s16)src;
		int bflgs = ((uae_s16)(src)) < 0;
		int bflgo = ((uae_s16)(dst)) < 0;
		int bflgn = bnewv < 0;
		ccr_68000_long_move_ae_LZN(bnewv);
		SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
		SET_XFLG(GET_CFLG());
		SET_VFLG((bflgs ^ bflgn) & (bflgo ^ bflgn));
		dreg_68000_long_replace_low(dstreg, bnewv);
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	opcode = regs.ir;
	do_cycles_ce000_internal(4);
	m68k_dreg(regs, dstreg) = (newv);
	m68k_incpci(6);
	return;
}
/* 16 (3/0) */
/* 6 0,0   */

/* ADD.L #<data>.L,(An) */
void REGPARAM2 op_0690_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 28; 
	uae_s32 src;
	src = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	src |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	if (dsta & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, dsta, 2, 1);
		return;
	}
	uae_s32 dst = x_get_word(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	dst |= x_get_word(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return;
	}
	uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u32)(~dst)) < ((uae_u32)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		uae_s16 bnewv = (uae_s16)dst + (uae_s16)src;
		int bflgs = ((uae_s16)(src)) < 0;
		int bflgo = ((uae_s16)(dst)) < 0;
		int bflgn = bnewv < 0;
		ccr_68000_long_move_ae_LZN(bnewv);
		SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
		SET_XFLG(GET_CFLG());
		SET_VFLG((bflgs ^ bflgn) & (bflgo ^ bflgn));
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	x_put_word(dsta + 2, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 2, 0x1, newv, 1);
		return;
	}
	x_put_word(dsta, newv >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 0, 0x1, newv >> 16, 1);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 28 (5/2) */
/* 6 0,0   */

/* ADD.L #<data>.L,(An)+ */
void REGPARAM2 op_0698_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 28; 
	uae_s32 src;
	src = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	src |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	if (dsta & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, dsta, 2, 1);
		return;
	}
	uae_s32 dst = x_get_word(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	dst |= x_get_word(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return;
	}
	m68k_areg(regs, dstreg) += 4;
	uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u32)(~dst)) < ((uae_u32)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		uae_s16 bnewv = (uae_s16)dst + (uae_s16)src;
		int bflgs = ((uae_s16)(src)) < 0;
		int bflgo = ((uae_s16)(dst)) < 0;
		int bflgn = bnewv < 0;
		ccr_68000_long_move_ae_LZN(bnewv);
		SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
		SET_XFLG(GET_CFLG());
		SET_VFLG((bflgs ^ bflgn) & (bflgo ^ bflgn));
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	x_put_word(dsta + 2, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 2, 0x1, newv, 1);
		return;
	}
	x_put_word(dsta, newv >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 0, 0x1, newv >> 16, 1);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 28 (5/2) */
/* 6 0,0   */

/* ADD.L #<data>.L,-(An) */
void REGPARAM2 op_06a0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 30; 
	uae_s32 src;
	src = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	src |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - 4;
	do_cycles_ce000_internal(2);
	if (dsta & 1) {
		m68k_incpci(6);
		m68k_areg(regs, dstreg) = dsta;
		exception3_read_access(opcode, dsta, 2, 1);
		return;
	}
	uae_s32 dst = x_get_word(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		m68k_areg(regs, dstreg) = dsta;
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	dst |= x_get_word(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		m68k_areg(regs, dstreg) = dsta;
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return;
	}
	m68k_areg(regs, dstreg) = dsta;
	uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u32)(~dst)) < ((uae_u32)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		uae_s16 bnewv = (uae_s16)dst + (uae_s16)src;
		int bflgs = ((uae_s16)(src)) < 0;
		int bflgo = ((uae_s16)(dst)) < 0;
		int bflgn = bnewv < 0;
		ccr_68000_long_move_ae_LZN(bnewv);
		SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
		SET_XFLG(GET_CFLG());
		SET_VFLG((bflgs ^ bflgn) & (bflgo ^ bflgn));
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	x_put_word(dsta + 2, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 2, 0x1, newv, 1);
		return;
	}
	x_put_word(dsta, newv >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 0, 0x1, newv >> 16, 1);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 30 (5/2) */
/* 6 0,0   */

/* ADD.L #<data>.L,(d16,An) */
void REGPARAM2 op_06a8_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 32; 
	uae_s32 src;
	src = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	src |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 8, -2);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, dsta, 2, 1);
		return;
	}
	uae_s32 dst = x_get_word(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	dst |= x_get_word(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return;
	}
	uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u32)(~dst)) < ((uae_u32)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(10);
	if(hardware_bus_error) {
		int pcoffset = 0;
		uae_s16 bnewv = (uae_s16)dst + (uae_s16)src;
		int bflgs = ((uae_s16)(src)) < 0;
		int bflgo = ((uae_s16)(dst)) < 0;
		int bflgn = bnewv < 0;
		ccr_68000_long_move_ae_LZN(bnewv);
		SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
		SET_XFLG(GET_CFLG());
		SET_VFLG((bflgs ^ bflgn) & (bflgo ^ bflgn));
		exception2_fetch_opcode(opcode, 10, pcoffset);
		return;
	}
	x_put_word(dsta + 2, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(10);
		exception2_write(opcode, dsta + 2, 0x1, newv, 1);
		return;
	}
	x_put_word(dsta, newv >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(10);
		exception2_write(opcode, dsta + 0, 0x1, newv >> 16, 1);
		return;
	}
	m68k_incpci(8);
	return;
}
/* 32 (6/2) */
/* 8 0,0   */

/* ADD.L #<data>.L,(d8,An,Xn) */
void REGPARAM2 op_06b0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 34; 
	uae_s32 src;
	src = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	src |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	uaecptr dsta;
	do_cycles_ce000_internal(2);
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_ce000_prefetch(8));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 8, -2);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, dsta, 2, 1);
		return;
	}
	uae_s32 dst = x_get_word(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	dst |= x_get_word(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return;
	}
	uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u32)(~dst)) < ((uae_u32)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(10);
	if(hardware_bus_error) {
		int pcoffset = 0;
		uae_s16 bnewv = (uae_s16)dst + (uae_s16)src;
		int bflgs = ((uae_s16)(src)) < 0;
		int bflgo = ((uae_s16)(dst)) < 0;
		int bflgn = bnewv < 0;
		ccr_68000_long_move_ae_LZN(bnewv);
		SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
		SET_XFLG(GET_CFLG());
		SET_VFLG((bflgs ^ bflgn) & (bflgo ^ bflgn));
		exception2_fetch_opcode(opcode, 10, pcoffset);
		return;
	}
	x_put_word(dsta + 2, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(10);
		exception2_write(opcode, dsta + 2, 0x1, newv, 1);
		return;
	}
	x_put_word(dsta, newv >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(10);
		exception2_write(opcode, dsta + 0, 0x1, newv >> 16, 1);
		return;
	}
	m68k_incpci(8);
	return;
}
/* 34 (6/2) */
/* 8 4,0   */

/* ADD.L #<data>.L,(xxx).W */
void REGPARAM2 op_06b8_14_ff(uae_u32 opcode)
{
	OpcodeFamily = 11;
	CurrentInstrCycles = 32; 
	uae_s32 src;
	src = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	src |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 8, 0);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(8);
		exception3_read_access(opcode, dsta, 2, 1);
		return;
	}
	uae_s32 dst = x_get_word(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	dst |= x_get_word(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return;
	}
	uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u32)(~dst)) < ((uae_u32)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(10);
	if(hardware_bus_error) {
		int pcoffset = 0;
		uae_s16 bnewv = (uae_s16)dst + (uae_s16)src;
		int bflgs = ((uae_s16)(src)) < 0;
		int bflgo = ((uae_s16)(dst)) < 0;
		int bflgn = bnewv < 0;
		ccr_68000_long_move_ae_LZN(bnewv);
		SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
		SET_XFLG(GET_CFLG());
		SET_VFLG((bflgs ^ bflgn) & (bflgo ^ bflgn));
		exception2_fetch_opcode(opcode, 10, pcoffset);
		return;
	}
	x_put_word(dsta + 2, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(10);
		exception2_write(opcode, dsta + 2, 0x1, newv, 1);
		return;
	}
	x_put_word(dsta, newv >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(10);
		exception2_write(opcode, dsta + 0, 0x1, newv >> 16, 1);
		return;
	}
	m68k_incpci(8);
	return;
}
/* 32 (6/2) */
/* 8 0,0   */

/* ADD.L #<data>.L,(xxx).L */
void REGPARAM2 op_06b9_14_ff(uae_u32 opcode)
{
	OpcodeFamily = 11;
	CurrentInstrCycles = 36; 
	uae_s32 src;
	src = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	src |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	uaecptr dsta;
	dsta = get_word_ce000_prefetch(8) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 8, -2);
		return;
	}
	dsta |= get_word_ce000_prefetch(10);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 10, pcoffset);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(10);
		exception3_read_access(opcode, dsta, 2, 1);
		return;
	}
	uae_s32 dst = x_get_word(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(10);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	dst |= x_get_word(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(10);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return;
	}
	uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u32)(~dst)) < ((uae_u32)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(12);
	if(hardware_bus_error) {
		int pcoffset = 0;
		uae_s16 bnewv = (uae_s16)dst + (uae_s16)src;
		int bflgs = ((uae_s16)(src)) < 0;
		int bflgo = ((uae_s16)(dst)) < 0;
		int bflgn = bnewv < 0;
		ccr_68000_long_move_ae_LZN(bnewv);
		SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
		SET_XFLG(GET_CFLG());
		SET_VFLG((bflgs ^ bflgn) & (bflgo ^ bflgn));
		exception2_fetch_opcode(opcode, 12, pcoffset);
		return;
	}
	x_put_word(dsta + 2, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(12);
		exception2_write(opcode, dsta + 2, 0x1, newv, 1);
		return;
	}
	x_put_word(dsta, newv >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(12);
		exception2_write(opcode, dsta + 0, 0x1, newv >> 16, 1);
		return;
	}
	m68k_incpci(10);
	return;
}
/* 36 (7/2) */
/* 10 0,0   */

/* BTST.L #<data>.W,Dn */
void REGPARAM2 op_0800_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 21;
	CurrentInstrCycles = 10; 
	ipl_fetch_now();
	uae_s16 src = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	src &= 31;
	do_cycles_ce000_internal(2);
	SET_ZFLG(1 ^ ((dst >> src) & 1));
	m68k_incpci(4);
	return;
}
/* 10 (2/0) */
/* 4 0,0   */

/* BTST.B #<data>.W,(An) */
void REGPARAM2 op_0810_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 21;
	CurrentInstrCycles = 12; 
	uae_s16 src = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	src &= 7;
	SET_ZFLG(1 ^ ((dst >> src) & 1));
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 12 (3/0) */
/* 4 0,0   */

/* BTST.B #<data>.W,(An)+ */
void REGPARAM2 op_0818_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 21;
	CurrentInstrCycles = 12; 
	uae_s16 src = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
	src &= 7;
	SET_ZFLG(1 ^ ((dst >> src) & 1));
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 12 (3/0) */
/* 4 0,0   */

/* BTST.B #<data>.W,-(An) */
void REGPARAM2 op_0820_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 21;
	CurrentInstrCycles = 14; 
	uae_s16 src = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
	do_cycles_ce000_internal(2);
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		m68k_areg(regs, dstreg) = dsta;
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	m68k_areg(regs, dstreg) = dsta;
	src &= 7;
	SET_ZFLG(1 ^ ((dst >> src) & 1));
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 14 (3/0) */
/* 4 0,0   */

/* BTST.B #<data>.W,(d16,An) */
void REGPARAM2 op_0828_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 21;
	CurrentInstrCycles = 16; 
	uae_s16 src = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return;
	}
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	src &= 7;
	SET_ZFLG(1 ^ ((dst >> src) & 1));
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 16 (4/0) */
/* 6 0,0   */

/* BTST.B #<data>.W,(d8,An,Xn) */
void REGPARAM2 op_0830_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 21;
	CurrentInstrCycles = 18; 
	uae_s16 src = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr dsta;
	do_cycles_ce000_internal(2);
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_ce000_prefetch(6));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return;
	}
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	src &= 7;
	SET_ZFLG(1 ^ ((dst >> src) & 1));
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 18 (4/0) */
/* 6 4,0   */

/* BTST.B #<data>.W,(xxx).W */
void REGPARAM2 op_0838_14_ff(uae_u32 opcode)
{
	OpcodeFamily = 21;
	CurrentInstrCycles = 16; 
	uae_s16 src = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, 0);
		return;
	}
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	src &= 7;
	SET_ZFLG(1 ^ ((dst >> src) & 1));
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 16 (4/0) */
/* 6 0,0   */

/* BTST.B #<data>.W,(xxx).L */
void REGPARAM2 op_0839_14_ff(uae_u32 opcode)
{
	OpcodeFamily = 21;
	CurrentInstrCycles = 20; 
	uae_s16 src = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr dsta;
	dsta = get_word_ce000_prefetch(6) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return;
	}
	dsta |= get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 8, pcoffset);
		return;
	}
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	src &= 7;
	SET_ZFLG(1 ^ ((dst >> src) & 1));
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(10);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 10, pcoffset);
		return;
	}
	m68k_incpci(8);
	return;
}
/* 20 (5/0) */
/* 8 0,0   */

/* BTST.B #<data>.W,(d16,PC) */
void REGPARAM2 op_083a_14_ff(uae_u32 opcode)
{
	uae_u32 dstreg = 2;
	OpcodeFamily = 21;
	CurrentInstrCycles = 16; 
	uae_s16 src = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr dsta;
	dsta = m68k_getpci() + 4;
	dsta += (uae_s32)(uae_s16)get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return;
	}
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x0, 2);
		return;
	}
	src &= 7;
	SET_ZFLG(1 ^ ((dst >> src) & 1));
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 16 (4/0) */
/* 6 0,0   */

/* BTST.B #<data>.W,(d8,PC,Xn) */
void REGPARAM2 op_083b_14_ff(uae_u32 opcode)
{
	uae_u32 dstreg = 3;
	OpcodeFamily = 21;
	CurrentInstrCycles = 18; 
	uae_s16 src = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr dsta;
	uaecptr tmppc = m68k_getpci() + 4;
	do_cycles_ce000_internal(2);
	dsta = get_disp_ea_000(tmppc, get_word_ce000_prefetch(6));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return;
	}
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x0, 2);
		return;
	}
	src &= 7;
	SET_ZFLG(1 ^ ((dst >> src) & 1));
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 18 (4/0) */
/* 6 4,0   */

/* BCHG.L #<data>.W,Dn */
void REGPARAM2 op_0840_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 22;
	CurrentInstrCycles = 10; 
	uae_s16 src = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	src &= 31;
	do_cycles_ce000_internal(2);
	if (src > 15) do_cycles_ce000_internal(2);
	dst ^= (1 << src);
	SET_ZFLG(((uae_u32)dst & (1 << src)) >> src);
	m68k_dreg(regs, dstreg) = (dst);
	m68k_incpci(4);
	return;
}
/* 10 (2/0) */
/* 4 0,0   */

/* BCHG.B #<data>.W,(An) */
void REGPARAM2 op_0850_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 22;
	CurrentInstrCycles = 16; 
	uae_s16 src = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	src &= 7;
	dst ^= (1 << src);
	SET_ZFLG(((uae_u32)dst & (1 << src)) >> src);
	x_put_byte(dsta, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, dst, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* BCHG.B #<data>.W,(An)+ */
void REGPARAM2 op_0858_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 22;
	CurrentInstrCycles = 16; 
	uae_s16 src = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	src &= 7;
	dst ^= (1 << src);
	SET_ZFLG(((uae_u32)dst & (1 << src)) >> src);
	x_put_byte(dsta, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, dst, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* BCHG.B #<data>.W,-(An) */
void REGPARAM2 op_0860_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 22;
	CurrentInstrCycles = 18; 
	uae_s16 src = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
	do_cycles_ce000_internal(2);
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		m68k_areg(regs, dstreg) = dsta;
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	m68k_areg(regs, dstreg) = dsta;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	src &= 7;
	dst ^= (1 << src);
	SET_ZFLG(((uae_u32)dst & (1 << src)) >> src);
	x_put_byte(dsta, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, dst, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 18 (3/1) */
/* 4 0,0   */

/* BCHG.B #<data>.W,(d16,An) */
void REGPARAM2 op_0868_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 22;
	CurrentInstrCycles = 20; 
	uae_s16 src = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return;
	}
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	opcode = regs.ir;
	src &= 7;
	dst ^= (1 << src);
	SET_ZFLG(((uae_u32)dst & (1 << src)) >> src);
	x_put_byte(dsta, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, dst, 1);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 20 (4/1) */
/* 6 0,0   */

/* BCHG.B #<data>.W,(d8,An,Xn) */
void REGPARAM2 op_0870_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 22;
	CurrentInstrCycles = 22; 
	uae_s16 src = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr dsta;
	do_cycles_ce000_internal(2);
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_ce000_prefetch(6));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return;
	}
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	opcode = regs.ir;
	src &= 7;
	dst ^= (1 << src);
	SET_ZFLG(((uae_u32)dst & (1 << src)) >> src);
	x_put_byte(dsta, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, dst, 1);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 22 (4/1) */
/* 6 4,0   */

/* BCHG.B #<data>.W,(xxx).W */
void REGPARAM2 op_0878_14_ff(uae_u32 opcode)
{
	OpcodeFamily = 22;
	CurrentInstrCycles = 20; 
	uae_s16 src = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, 0);
		return;
	}
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	opcode = regs.ir;
	src &= 7;
	dst ^= (1 << src);
	SET_ZFLG(((uae_u32)dst & (1 << src)) >> src);
	x_put_byte(dsta, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, dst, 1);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 20 (4/1) */
/* 6 0,0   */

/* BCHG.B #<data>.W,(xxx).L */
void REGPARAM2 op_0879_14_ff(uae_u32 opcode)
{
	OpcodeFamily = 22;
	CurrentInstrCycles = 24; 
	uae_s16 src = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr dsta;
	dsta = get_word_ce000_prefetch(6) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return;
	}
	dsta |= get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 8, pcoffset);
		return;
	}
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(10);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 10, pcoffset);
		return;
	}
	opcode = regs.ir;
	src &= 7;
	dst ^= (1 << src);
	SET_ZFLG(((uae_u32)dst & (1 << src)) >> src);
	x_put_byte(dsta, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(10);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, dst, 1);
		return;
	}
	m68k_incpci(8);
	return;
}
/* 24 (5/1) */
/* 8 0,0   */

/* BCLR.L #<data>.W,Dn */
void REGPARAM2 op_0880_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 23;
	CurrentInstrCycles = 12; 
	uae_s16 src = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	src &= 31;
	do_cycles_ce000_internal(2);
	if (src > 15) do_cycles_ce000_internal(2);
	do_cycles_ce000_internal(2);
	SET_ZFLG(1 ^ ((dst >> src) & 1));
	dst &= ~(1 << src);
	m68k_dreg(regs, dstreg) = (dst);
	m68k_incpci(4);
	return;
}
/* 12 (2/0) */
/* 4 0,0   */

/* BCLR.B #<data>.W,(An) */
void REGPARAM2 op_0890_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 23;
	CurrentInstrCycles = 16; 
	uae_s16 src = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	src &= 7;
	SET_ZFLG(1 ^ ((dst >> src) & 1));
	dst &= ~(1 << src);
	x_put_byte(dsta, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, dst, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* BCLR.B #<data>.W,(An)+ */
void REGPARAM2 op_0898_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 23;
	CurrentInstrCycles = 16; 
	uae_s16 src = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	src &= 7;
	SET_ZFLG(1 ^ ((dst >> src) & 1));
	dst &= ~(1 << src);
	x_put_byte(dsta, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, dst, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* BCLR.B #<data>.W,-(An) */
void REGPARAM2 op_08a0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 23;
	CurrentInstrCycles = 18; 
	uae_s16 src = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
	do_cycles_ce000_internal(2);
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		m68k_areg(regs, dstreg) = dsta;
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	m68k_areg(regs, dstreg) = dsta;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	src &= 7;
	SET_ZFLG(1 ^ ((dst >> src) & 1));
	dst &= ~(1 << src);
	x_put_byte(dsta, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, dst, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 18 (3/1) */
/* 4 0,0   */

/* BCLR.B #<data>.W,(d16,An) */
void REGPARAM2 op_08a8_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 23;
	CurrentInstrCycles = 20; 
	uae_s16 src = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return;
	}
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	opcode = regs.ir;
	src &= 7;
	SET_ZFLG(1 ^ ((dst >> src) & 1));
	dst &= ~(1 << src);
	x_put_byte(dsta, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, dst, 1);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 20 (4/1) */
/* 6 0,0   */

/* BCLR.B #<data>.W,(d8,An,Xn) */
void REGPARAM2 op_08b0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 23;
	CurrentInstrCycles = 22; 
	uae_s16 src = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr dsta;
	do_cycles_ce000_internal(2);
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_ce000_prefetch(6));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return;
	}
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	opcode = regs.ir;
	src &= 7;
	SET_ZFLG(1 ^ ((dst >> src) & 1));
	dst &= ~(1 << src);
	x_put_byte(dsta, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, dst, 1);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 22 (4/1) */
/* 6 4,0   */

/* BCLR.B #<data>.W,(xxx).W */
void REGPARAM2 op_08b8_14_ff(uae_u32 opcode)
{
	OpcodeFamily = 23;
	CurrentInstrCycles = 20; 
	uae_s16 src = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, 0);
		return;
	}
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	opcode = regs.ir;
	src &= 7;
	SET_ZFLG(1 ^ ((dst >> src) & 1));
	dst &= ~(1 << src);
	x_put_byte(dsta, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, dst, 1);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 20 (4/1) */
/* 6 0,0   */

/* BCLR.B #<data>.W,(xxx).L */
void REGPARAM2 op_08b9_14_ff(uae_u32 opcode)
{
	OpcodeFamily = 23;
	CurrentInstrCycles = 24; 
	uae_s16 src = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr dsta;
	dsta = get_word_ce000_prefetch(6) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return;
	}
	dsta |= get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 8, pcoffset);
		return;
	}
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(10);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 10, pcoffset);
		return;
	}
	opcode = regs.ir;
	src &= 7;
	SET_ZFLG(1 ^ ((dst >> src) & 1));
	dst &= ~(1 << src);
	x_put_byte(dsta, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(10);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, dst, 1);
		return;
	}
	m68k_incpci(8);
	return;
}
/* 24 (5/1) */
/* 8 0,0   */

/* BSET.L #<data>.W,Dn */
void REGPARAM2 op_08c0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 24;
	CurrentInstrCycles = 10; 
	uae_s16 src = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	src &= 31;
	do_cycles_ce000_internal(2);
	if (src > 15) do_cycles_ce000_internal(2);
	SET_ZFLG(1 ^ ((dst >> src) & 1));
	dst |= (1 << src);
	m68k_dreg(regs, dstreg) = (dst);
	m68k_incpci(4);
	return;
}
/* 10 (2/0) */
/* 4 0,0   */

/* BSET.B #<data>.W,(An) */
void REGPARAM2 op_08d0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 24;
	CurrentInstrCycles = 16; 
	uae_s16 src = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	src &= 7;
	SET_ZFLG(1 ^ ((dst >> src) & 1));
	dst |= (1 << src);
	x_put_byte(dsta, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, dst, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* BSET.B #<data>.W,(An)+ */
void REGPARAM2 op_08d8_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 24;
	CurrentInstrCycles = 16; 
	uae_s16 src = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	src &= 7;
	SET_ZFLG(1 ^ ((dst >> src) & 1));
	dst |= (1 << src);
	x_put_byte(dsta, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, dst, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* BSET.B #<data>.W,-(An) */
void REGPARAM2 op_08e0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 24;
	CurrentInstrCycles = 18; 
	uae_s16 src = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
	do_cycles_ce000_internal(2);
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		m68k_areg(regs, dstreg) = dsta;
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	m68k_areg(regs, dstreg) = dsta;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	src &= 7;
	SET_ZFLG(1 ^ ((dst >> src) & 1));
	dst |= (1 << src);
	x_put_byte(dsta, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, dst, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 18 (3/1) */
/* 4 0,0   */

/* BSET.B #<data>.W,(d16,An) */
void REGPARAM2 op_08e8_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 24;
	CurrentInstrCycles = 20; 
	uae_s16 src = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return;
	}
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	opcode = regs.ir;
	src &= 7;
	SET_ZFLG(1 ^ ((dst >> src) & 1));
	dst |= (1 << src);
	x_put_byte(dsta, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, dst, 1);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 20 (4/1) */
/* 6 0,0   */

/* BSET.B #<data>.W,(d8,An,Xn) */
void REGPARAM2 op_08f0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 24;
	CurrentInstrCycles = 22; 
	uae_s16 src = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr dsta;
	do_cycles_ce000_internal(2);
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_ce000_prefetch(6));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return;
	}
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	opcode = regs.ir;
	src &= 7;
	SET_ZFLG(1 ^ ((dst >> src) & 1));
	dst |= (1 << src);
	x_put_byte(dsta, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, dst, 1);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 22 (4/1) */
/* 6 4,0   */

/* BSET.B #<data>.W,(xxx).W */
void REGPARAM2 op_08f8_14_ff(uae_u32 opcode)
{
	OpcodeFamily = 24;
	CurrentInstrCycles = 20; 
	uae_s16 src = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, 0);
		return;
	}
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	opcode = regs.ir;
	src &= 7;
	SET_ZFLG(1 ^ ((dst >> src) & 1));
	dst |= (1 << src);
	x_put_byte(dsta, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, dst, 1);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 20 (4/1) */
/* 6 0,0   */

/* BSET.B #<data>.W,(xxx).L */
void REGPARAM2 op_08f9_14_ff(uae_u32 opcode)
{
	OpcodeFamily = 24;
	CurrentInstrCycles = 24; 
	uae_s16 src = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr dsta;
	dsta = get_word_ce000_prefetch(6) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return;
	}
	dsta |= get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 8, pcoffset);
		return;
	}
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(10);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 10, pcoffset);
		return;
	}
	opcode = regs.ir;
	src &= 7;
	SET_ZFLG(1 ^ ((dst >> src) & 1));
	dst |= (1 << src);
	x_put_byte(dsta, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(10);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, dst, 1);
		return;
	}
	m68k_incpci(8);
	return;
}
/* 24 (5/1) */
/* 8 0,0   */

/* EOR.B #<data>.B,Dn */
void REGPARAM2 op_0a00_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 3;
	CurrentInstrCycles = 8;  
	uae_s8 src = (uae_u8)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uae_s8 dst = m68k_dreg(regs, dstreg);
	src ^= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 8 (2/0) */
/* 4 0,0   */

/* EOR.B #<data>.B,(An) */
void REGPARAM2 op_0a10_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 3;
	CurrentInstrCycles = 16; 
	uae_s8 src = (uae_u8)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	src ^= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_byte(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* EOR.B #<data>.B,(An)+ */
void REGPARAM2 op_0a18_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 3;
	CurrentInstrCycles = 16; 
	uae_s8 src = (uae_u8)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
	src ^= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_byte(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* EOR.B #<data>.B,-(An) */
void REGPARAM2 op_0a20_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 3;
	CurrentInstrCycles = 18; 
	uae_s8 src = (uae_u8)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
	do_cycles_ce000_internal(2);
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		m68k_areg(regs, dstreg) = dsta;
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	m68k_areg(regs, dstreg) = dsta;
	src ^= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_byte(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 18 (3/1) */
/* 4 0,0   */

/* EOR.B #<data>.B,(d16,An) */
void REGPARAM2 op_0a28_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 3;
	CurrentInstrCycles = 20; 
	uae_s8 src = (uae_u8)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return;
	}
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	src ^= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_byte(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 20 (4/1) */
/* 6 0,0   */

/* EOR.B #<data>.B,(d8,An,Xn) */
void REGPARAM2 op_0a30_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 3;
	CurrentInstrCycles = 22; 
	uae_s8 src = (uae_u8)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr dsta;
	do_cycles_ce000_internal(2);
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_ce000_prefetch(6));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return;
	}
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	src ^= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_byte(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 22 (4/1) */
/* 6 4,0   */

/* EOR.B #<data>.B,(xxx).W */
void REGPARAM2 op_0a38_14_ff(uae_u32 opcode)
{
	OpcodeFamily = 3;
	CurrentInstrCycles = 20; 
	uae_s8 src = (uae_u8)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, 0);
		return;
	}
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	src ^= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_byte(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 20 (4/1) */
/* 6 0,0   */

/* EOR.B #<data>.B,(xxx).L */
void REGPARAM2 op_0a39_14_ff(uae_u32 opcode)
{
	OpcodeFamily = 3;
	CurrentInstrCycles = 24; 
	uae_s8 src = (uae_u8)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr dsta;
	dsta = get_word_ce000_prefetch(6) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return;
	}
	dsta |= get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 8, pcoffset);
		return;
	}
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	src ^= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(10);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 10, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_byte(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(10);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return;
	}
	m68k_incpci(8);
	return;
}
/* 24 (5/1) */
/* 8 0,0   */

/* EORSR.B #<data>.W */
void REGPARAM2 op_0a3c_14_ff(uae_u32 opcode)
{
	OpcodeFamily = 6;
	CurrentInstrCycles = 20; 
	MakeSR();
	int t1 = regs.t1;
	uae_s16 src = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	src &= 0xFF;
	do_cycles_ce000_internal(8);
	regs.sr ^= src;
	MakeFromSR();
	m68k_incpci(4);
	get_word_ce000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, 0);
		return;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	if(t1) opcode |= 0x10000;
	ipl_fetch_next();
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 20 (3/0) */
/* 4 0,0   */

/* EOR.W #<data>.W,Dn */
void REGPARAM2 op_0a40_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 3;
	CurrentInstrCycles = 8;  
	uae_s16 src = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	src ^= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 8 (2/0) */
/* 4 0,0   */

/* EOR.W #<data>.W,(An) */
void REGPARAM2 op_0a50_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 3;
	CurrentInstrCycles = 16; 
	uae_s16 src = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	if (dsta & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, dsta, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 dst = x_get_word(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	src ^= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_word(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* EOR.W #<data>.W,(An)+ */
void REGPARAM2 op_0a58_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 3;
	CurrentInstrCycles = 16; 
	uae_s16 src = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	if (dsta & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, dsta, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 dst = x_get_word(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, dstreg) += 2 + 0;
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	m68k_areg(regs, dstreg) += 2;
	src ^= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_word(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* EOR.W #<data>.W,-(An) */
void REGPARAM2 op_0a60_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 3;
	CurrentInstrCycles = 18; 
	uae_s16 src = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - 2;
	do_cycles_ce000_internal(2);
	if (dsta & 1) {
		m68k_incpci(6);
		m68k_areg(regs, dstreg) = dsta;
		exception3_read_access(opcode, dsta, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 dst = x_get_word(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		m68k_areg(regs, dstreg) = dsta;
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	m68k_areg(regs, dstreg) = dsta;
	src ^= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_word(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 18 (3/1) */
/* 4 0,0   */

/* EOR.W #<data>.W,(d16,An) */
void REGPARAM2 op_0a68_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 3;
	CurrentInstrCycles = 20; 
	uae_s16 src = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, dsta, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 dst = x_get_word(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	src ^= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_word(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 20 (4/1) */
/* 6 0,0   */

/* EOR.W #<data>.W,(d8,An,Xn) */
void REGPARAM2 op_0a70_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 3;
	CurrentInstrCycles = 22; 
	uae_s16 src = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr dsta;
	do_cycles_ce000_internal(2);
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_ce000_prefetch(6));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, dsta, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 dst = x_get_word(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	src ^= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_word(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 22 (4/1) */
/* 6 4,0   */

/* EOR.W #<data>.W,(xxx).W */
void REGPARAM2 op_0a78_14_ff(uae_u32 opcode)
{
	OpcodeFamily = 3;
	CurrentInstrCycles = 20; 
	uae_s16 src = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, 0);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, dsta, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 dst = x_get_word(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	src ^= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_word(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 20 (4/1) */
/* 6 0,0   */

/* EOR.W #<data>.W,(xxx).L */
void REGPARAM2 op_0a79_14_ff(uae_u32 opcode)
{
	OpcodeFamily = 3;
	CurrentInstrCycles = 24; 
	uae_s16 src = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr dsta;
	dsta = get_word_ce000_prefetch(6) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return;
	}
	dsta |= get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 8, pcoffset);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(8);
		exception3_read_access(opcode, dsta, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 dst = x_get_word(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	src ^= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(10);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 10, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_word(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(10);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return;
	}
	m68k_incpci(8);
	return;
}
/* 24 (5/1) */
/* 8 0,0   */

/* EORSR.W #<data>.W */
void REGPARAM2 op_0a7c_14_ff(uae_u32 opcode)
{
	OpcodeFamily = 6;
	CurrentInstrCycles = 20; 
	if (!regs.s) {
		Exception(8);
		return;
	}
	MakeSR();
	int t1 = regs.t1;
	uae_s16 src = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	do_cycles_ce000_internal(8);
	regs.sr ^= src;
	MakeFromSR();
	m68k_incpci(4);
	get_word_ce000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, 0);
		return;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	if(t1) opcode |= 0x10000;
	ipl_fetch_next();
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 20 (3/0) */
/* 4 0,0   */

/* EOR.L #<data>.L,Dn */
void REGPARAM2 op_0a80_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 3;
	CurrentInstrCycles = 16; 
	uae_s32 src;
	src = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	src |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	src ^= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		dreg_68000_long_replace_low(dstreg, src);
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	opcode = regs.ir;
	do_cycles_ce000_internal(4);
	m68k_dreg(regs, dstreg) = (src);
	m68k_incpci(6);
	return;
}
/* 16 (3/0) */
/* 6 0,0   */

/* EOR.L #<data>.L,(An) */
void REGPARAM2 op_0a90_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 3;
	CurrentInstrCycles = 28; 
	uae_s32 src;
	src = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	src |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	if (dsta & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, dsta, 2, 1);
		return;
	}
	uae_s32 dst = x_get_word(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	dst |= x_get_word(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return;
	}
	src ^= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	x_put_word(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return;
	}
	x_put_word(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 28 (5/2) */
/* 6 0,0   */

/* EOR.L #<data>.L,(An)+ */
void REGPARAM2 op_0a98_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 3;
	CurrentInstrCycles = 28; 
	uae_s32 src;
	src = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	src |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	if (dsta & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, dsta, 2, 1);
		return;
	}
	uae_s32 dst = x_get_word(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	dst |= x_get_word(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return;
	}
	m68k_areg(regs, dstreg) += 4;
	src ^= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	x_put_word(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return;
	}
	x_put_word(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 28 (5/2) */
/* 6 0,0   */

/* EOR.L #<data>.L,-(An) */
void REGPARAM2 op_0aa0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 3;
	CurrentInstrCycles = 30; 
	uae_s32 src;
	src = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	src |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - 4;
	do_cycles_ce000_internal(2);
	if (dsta & 1) {
		m68k_incpci(6);
		m68k_areg(regs, dstreg) = dsta;
		exception3_read_access(opcode, dsta, 2, 1);
		return;
	}
	uae_s32 dst = x_get_word(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		m68k_areg(regs, dstreg) = dsta;
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	dst |= x_get_word(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		m68k_areg(regs, dstreg) = dsta;
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return;
	}
	m68k_areg(regs, dstreg) = dsta;
	src ^= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	x_put_word(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return;
	}
	x_put_word(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 30 (5/2) */
/* 6 0,0   */

/* EOR.L #<data>.L,(d16,An) */
void REGPARAM2 op_0aa8_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 3;
	CurrentInstrCycles = 32; 
	uae_s32 src;
	src = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	src |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 8, -2);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, dsta, 2, 1);
		return;
	}
	uae_s32 dst = x_get_word(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	dst |= x_get_word(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return;
	}
	src ^= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(10);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch_opcode(opcode, 10, pcoffset);
		return;
	}
	x_put_word(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(10);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return;
	}
	x_put_word(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(10);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return;
	}
	m68k_incpci(8);
	return;
}
/* 32 (6/2) */
/* 8 0,0   */

/* EOR.L #<data>.L,(d8,An,Xn) */
void REGPARAM2 op_0ab0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 3;
	CurrentInstrCycles = 34; 
	uae_s32 src;
	src = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	src |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	uaecptr dsta;
	do_cycles_ce000_internal(2);
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_ce000_prefetch(8));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 8, -2);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, dsta, 2, 1);
		return;
	}
	uae_s32 dst = x_get_word(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	dst |= x_get_word(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return;
	}
	src ^= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(10);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch_opcode(opcode, 10, pcoffset);
		return;
	}
	x_put_word(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(10);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return;
	}
	x_put_word(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(10);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return;
	}
	m68k_incpci(8);
	return;
}
/* 34 (6/2) */
/* 8 4,0   */

/* EOR.L #<data>.L,(xxx).W */
void REGPARAM2 op_0ab8_14_ff(uae_u32 opcode)
{
	OpcodeFamily = 3;
	CurrentInstrCycles = 32; 
	uae_s32 src;
	src = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	src |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 8, 0);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(8);
		exception3_read_access(opcode, dsta, 2, 1);
		return;
	}
	uae_s32 dst = x_get_word(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	dst |= x_get_word(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return;
	}
	src ^= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(10);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch_opcode(opcode, 10, pcoffset);
		return;
	}
	x_put_word(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(10);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return;
	}
	x_put_word(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(10);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return;
	}
	m68k_incpci(8);
	return;
}
/* 32 (6/2) */
/* 8 0,0   */

/* EOR.L #<data>.L,(xxx).L */
void REGPARAM2 op_0ab9_14_ff(uae_u32 opcode)
{
	OpcodeFamily = 3;
	CurrentInstrCycles = 36; 
	uae_s32 src;
	src = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	src |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	uaecptr dsta;
	dsta = get_word_ce000_prefetch(8) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 8, -2);
		return;
	}
	dsta |= get_word_ce000_prefetch(10);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 10, pcoffset);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(10);
		exception3_read_access(opcode, dsta, 2, 1);
		return;
	}
	uae_s32 dst = x_get_word(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(10);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	dst |= x_get_word(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(10);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return;
	}
	src ^= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(12);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch_opcode(opcode, 12, pcoffset);
		return;
	}
	x_put_word(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(12);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return;
	}
	x_put_word(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(12);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return;
	}
	m68k_incpci(10);
	return;
}
/* 36 (7/2) */
/* 10 0,0   */

/* CMP.B #<data>.B,Dn */
void REGPARAM2 op_0c00_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 25;
	CurrentInstrCycles = 8;  
	uae_s8 src = (uae_u8)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uae_s8 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 8 (2/0) */
/* 4 0,0   */

/* CMP.B #<data>.B,(An) */
void REGPARAM2 op_0c10_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 25;
	CurrentInstrCycles = 12; 
	uae_s8 src = (uae_u8)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 12 (3/0) */
/* 4 0,0   */

/* CMP.B #<data>.B,(An)+ */
void REGPARAM2 op_0c18_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 25;
	CurrentInstrCycles = 12; 
	uae_s8 src = (uae_u8)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
	uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 12 (3/0) */
/* 4 0,0   */

/* CMP.B #<data>.B,-(An) */
void REGPARAM2 op_0c20_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 25;
	CurrentInstrCycles = 14; 
	uae_s8 src = (uae_u8)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
	do_cycles_ce000_internal(2);
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		m68k_areg(regs, dstreg) = dsta;
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	m68k_areg(regs, dstreg) = dsta;
	uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 14 (3/0) */
/* 4 0,0   */

/* CMP.B #<data>.B,(d16,An) */
void REGPARAM2 op_0c28_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 25;
	CurrentInstrCycles = 16; 
	uae_s8 src = (uae_u8)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return;
	}
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 16 (4/0) */
/* 6 0,0   */

/* CMP.B #<data>.B,(d8,An,Xn) */
void REGPARAM2 op_0c30_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 25;
	CurrentInstrCycles = 18; 
	uae_s8 src = (uae_u8)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr dsta;
	do_cycles_ce000_internal(2);
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_ce000_prefetch(6));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return;
	}
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 18 (4/0) */
/* 6 4,0   */

/* CMP.B #<data>.B,(xxx).W */
void REGPARAM2 op_0c38_14_ff(uae_u32 opcode)
{
	OpcodeFamily = 25;
	CurrentInstrCycles = 16; 
	uae_s8 src = (uae_u8)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, 0);
		return;
	}
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 16 (4/0) */
/* 6 0,0   */

/* CMP.B #<data>.B,(xxx).L */
void REGPARAM2 op_0c39_14_ff(uae_u32 opcode)
{
	OpcodeFamily = 25;
	CurrentInstrCycles = 20; 
	uae_s8 src = (uae_u8)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr dsta;
	dsta = get_word_ce000_prefetch(6) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return;
	}
	dsta |= get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 8, pcoffset);
		return;
	}
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(10);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 10, pcoffset);
		return;
	}
	m68k_incpci(8);
	return;
}
/* 20 (5/0) */
/* 8 0,0   */

/* CMP.W #<data>.W,Dn */
void REGPARAM2 op_0c40_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 25;
	CurrentInstrCycles = 8;  
	uae_s16 src = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 8 (2/0) */
/* 4 0,0   */

/* CMP.W #<data>.W,(An) */
void REGPARAM2 op_0c50_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 25;
	CurrentInstrCycles = 12; 
	uae_s16 src = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	if (dsta & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, dsta, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 dst = x_get_word(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 12 (3/0) */
/* 4 0,0   */

/* CMP.W #<data>.W,(An)+ */
void REGPARAM2 op_0c58_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 25;
	CurrentInstrCycles = 12; 
	uae_s16 src = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	if (dsta & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, dsta, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 dst = x_get_word(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, dstreg) += 2 + 0;
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	m68k_areg(regs, dstreg) += 2;
	uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 12 (3/0) */
/* 4 0,0   */

/* CMP.W #<data>.W,-(An) */
void REGPARAM2 op_0c60_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 25;
	CurrentInstrCycles = 14; 
	uae_s16 src = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - 2;
	do_cycles_ce000_internal(2);
	if (dsta & 1) {
		m68k_incpci(6);
		m68k_areg(regs, dstreg) = dsta;
		exception3_read_access(opcode, dsta, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 dst = x_get_word(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		m68k_areg(regs, dstreg) = dsta;
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	m68k_areg(regs, dstreg) = dsta;
	uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 14 (3/0) */
/* 4 0,0   */

/* CMP.W #<data>.W,(d16,An) */
void REGPARAM2 op_0c68_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 25;
	CurrentInstrCycles = 16; 
	uae_s16 src = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, dsta, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 dst = x_get_word(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 16 (4/0) */
/* 6 0,0   */

/* CMP.W #<data>.W,(d8,An,Xn) */
void REGPARAM2 op_0c70_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 25;
	CurrentInstrCycles = 18; 
	uae_s16 src = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr dsta;
	do_cycles_ce000_internal(2);
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_ce000_prefetch(6));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, dsta, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 dst = x_get_word(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 18 (4/0) */
/* 6 4,0   */

/* CMP.W #<data>.W,(xxx).W */
void REGPARAM2 op_0c78_14_ff(uae_u32 opcode)
{
	OpcodeFamily = 25;
	CurrentInstrCycles = 16; 
	uae_s16 src = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, 0);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, dsta, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 dst = x_get_word(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 16 (4/0) */
/* 6 0,0   */

/* CMP.W #<data>.W,(xxx).L */
void REGPARAM2 op_0c79_14_ff(uae_u32 opcode)
{
	OpcodeFamily = 25;
	CurrentInstrCycles = 20; 
	uae_s16 src = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr dsta;
	dsta = get_word_ce000_prefetch(6) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return;
	}
	dsta |= get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 8, pcoffset);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(8);
		exception3_read_access(opcode, dsta, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 dst = x_get_word(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(10);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 10, pcoffset);
		return;
	}
	m68k_incpci(8);
	return;
}
/* 20 (5/0) */
/* 8 0,0   */

/* CMP.L #<data>.L,Dn */
void REGPARAM2 op_0c80_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 25;
	CurrentInstrCycles = 14; 
	uae_s32 src;
	src = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	src |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	SET_NFLG(flgn != 0);
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	opcode = regs.ir;
	do_cycles_ce000_internal(2);
	m68k_incpci(6);
	return;
}
/* 14 (3/0) */
/* 6 0,0   */

/* CMP.L #<data>.L,(An) */
void REGPARAM2 op_0c90_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 25;
	CurrentInstrCycles = 20; 
	uae_s32 src;
	src = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	src |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	if (dsta & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, dsta, 2, 1);
		return;
	}
	uae_s32 dst = x_get_word(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	dst |= x_get_word(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return;
	}
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 20 (5/0) */
/* 6 0,0   */

/* CMP.L #<data>.L,(An)+ */
void REGPARAM2 op_0c98_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 25;
	CurrentInstrCycles = 20; 
	uae_s32 src;
	src = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	src |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	if (dsta & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, dsta, 2, 1);
		return;
	}
	uae_s32 dst = x_get_word(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	dst |= x_get_word(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return;
	}
	m68k_areg(regs, dstreg) += 4;
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 20 (5/0) */
/* 6 0,0   */

/* CMP.L #<data>.L,-(An) */
void REGPARAM2 op_0ca0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 25;
	CurrentInstrCycles = 22; 
	uae_s32 src;
	src = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	src |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - 4;
	do_cycles_ce000_internal(2);
	if (dsta & 1) {
		m68k_incpci(6);
		m68k_areg(regs, dstreg) = dsta;
		exception3_read_access(opcode, dsta, 2, 1);
		return;
	}
	uae_s32 dst = x_get_word(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		m68k_areg(regs, dstreg) = dsta;
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	dst |= x_get_word(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		m68k_areg(regs, dstreg) = dsta;
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return;
	}
	m68k_areg(regs, dstreg) = dsta;
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 22 (5/0) */
/* 6 0,0   */

/* CMP.L #<data>.L,(d16,An) */
void REGPARAM2 op_0ca8_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 25;
	CurrentInstrCycles = 24; 
	uae_s32 src;
	src = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	src |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 8, -2);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, dsta, 2, 1);
		return;
	}
	uae_s32 dst = x_get_word(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	dst |= x_get_word(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return;
	}
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(10);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 10, pcoffset);
		return;
	}
	m68k_incpci(8);
	return;
}
/* 24 (6/0) */
/* 8 0,0   */

/* CMP.L #<data>.L,(d8,An,Xn) */
void REGPARAM2 op_0cb0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 25;
	CurrentInstrCycles = 26; 
	uae_s32 src;
	src = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	src |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	uaecptr dsta;
	do_cycles_ce000_internal(2);
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_ce000_prefetch(8));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 8, -2);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, dsta, 2, 1);
		return;
	}
	uae_s32 dst = x_get_word(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	dst |= x_get_word(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return;
	}
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(10);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 10, pcoffset);
		return;
	}
	m68k_incpci(8);
	return;
}
/* 26 (6/0) */
/* 8 4,0   */

/* CMP.L #<data>.L,(xxx).W */
void REGPARAM2 op_0cb8_14_ff(uae_u32 opcode)
{
	OpcodeFamily = 25;
	CurrentInstrCycles = 24; 
	uae_s32 src;
	src = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	src |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 8, 0);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(8);
		exception3_read_access(opcode, dsta, 2, 1);
		return;
	}
	uae_s32 dst = x_get_word(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	dst |= x_get_word(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return;
	}
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(10);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 10, pcoffset);
		return;
	}
	m68k_incpci(8);
	return;
}
/* 24 (6/0) */
/* 8 0,0   */

/* CMP.L #<data>.L,(xxx).L */
void REGPARAM2 op_0cb9_14_ff(uae_u32 opcode)
{
	OpcodeFamily = 25;
	CurrentInstrCycles = 28; 
	uae_s32 src;
	src = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	src |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	uaecptr dsta;
	dsta = get_word_ce000_prefetch(8) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 8, -2);
		return;
	}
	dsta |= get_word_ce000_prefetch(10);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 10, pcoffset);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(10);
		exception3_read_access(opcode, dsta, 2, 1);
		return;
	}
	uae_s32 dst = x_get_word(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(10);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	dst |= x_get_word(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(10);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return;
	}
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(12);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 12, pcoffset);
		return;
	}
	m68k_incpci(10);
	return;
}
/* 28 (7/0) */
/* 10 0,0   */

/* MOVE.B Dn,Dn */
void REGPARAM2 op_1000_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 4;  
	uae_s8 src = m68k_dreg(regs, srcreg);
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
	m68k_incpci(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 4 (1/0) */
/* 2 0,0   */

/* MOVE.B (An),Dn */
void REGPARAM2 op_1010_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 8;  
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
	m68k_incpci(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 8 (2/0) */
/* 2 0,0   */

/* MOVE.B (An)+,Dn */
void REGPARAM2 op_1018_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 8;  
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
	m68k_incpci(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 8 (2/0) */
/* 2 0,0   */

/* MOVE.B -(An),Dn */
void REGPARAM2 op_1020_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 10; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
	do_cycles_ce000_internal(2);
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	m68k_areg(regs, srcreg) = srca;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
	m68k_incpci(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 10 (2/0) */
/* 2 0,0   */

/* MOVE.B (d16,An),Dn */
void REGPARAM2 op_1028_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 12 (3/0) */
/* 4 0,0   */

/* MOVE.B (d8,An,Xn),Dn */
void REGPARAM2 op_1030_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	do_cycles_ce000_internal(2);
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 14 (3/0) */
/* 4 4,0   */

/* MOVE.B (xxx).W,Dn */
void REGPARAM2 op_1038_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 12 (3/0) */
/* 4 0,0   */

/* MOVE.B (xxx).L,Dn */
void REGPARAM2 op_1039_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	srca |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 16 (4/0) */
/* 6 0,0   */

/* MOVE.B (d16,PC),Dn */
void REGPARAM2 op_103a_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_getpci() + 2;
	srca += (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 2);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 12 (3/0) */
/* 4 0,0   */

/* MOVE.B (d8,PC,Xn),Dn */
void REGPARAM2 op_103b_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	uaecptr tmppc = m68k_getpci() + 2;
	do_cycles_ce000_internal(2);
	srca = get_disp_ea_000(tmppc, get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 2);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 14 (3/0) */
/* 4 4,0   */

/* MOVE.B #<data>.B,Dn */
void REGPARAM2 op_103c_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 8;  
	uae_s8 src = (uae_u8)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 8 (2/0) */
/* 4 0,0   */

/* MOVE.B Dn,(An) */
void REGPARAM2 op_1080_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 8;  
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	ipl_fetch_now();
	x_put_byte(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return;
	}
	m68k_incpci(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 8 (1/1) */
/* 2 0,0   */

/* MOVE.B (An),(An) */
void REGPARAM2 op_1090_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	ipl_fetch_now();
	x_put_byte(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return;
	}
	m68k_incpci(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 12 (2/1) */
/* 2 0,0   */

/* MOVE.B (An)+,(An) */
void REGPARAM2 op_1098_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	ipl_fetch_now();
	x_put_byte(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return;
	}
	m68k_incpci(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 12 (2/1) */
/* 2 0,0   */

/* MOVE.B -(An),(An) */
void REGPARAM2 op_10a0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
	do_cycles_ce000_internal(2);
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	m68k_areg(regs, srcreg) = srca;
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	ipl_fetch_now();
	x_put_byte(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return;
	}
	m68k_incpci(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 14 (2/1) */
/* 2 0,0   */

/* MOVE.B (d16,An),(An) */
void REGPARAM2 op_10a8_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	ipl_fetch_now();
	x_put_byte(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* MOVE.B (d8,An,Xn),(An) */
void REGPARAM2 op_10b0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	do_cycles_ce000_internal(2);
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	ipl_fetch_now();
	x_put_byte(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 18 (3/1) */
/* 4 4,0   */

/* MOVE.B (xxx).W,(An) */
void REGPARAM2 op_10b8_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	ipl_fetch_now();
	x_put_byte(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* MOVE.B (xxx).L,(An) */
void REGPARAM2 op_10b9_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	srca = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	srca |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	ipl_fetch_now();
	x_put_byte(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return;
	}
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 20 (4/1) */
/* 6 0,0   */

/* MOVE.B (d16,PC),(An) */
void REGPARAM2 op_10ba_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = m68k_getpci() + 2;
	srca += (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 2);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	ipl_fetch_now();
	x_put_byte(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* MOVE.B (d8,PC,Xn),(An) */
void REGPARAM2 op_10bb_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	uaecptr tmppc = m68k_getpci() + 2;
	do_cycles_ce000_internal(2);
	srca = get_disp_ea_000(tmppc, get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 2);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	ipl_fetch_now();
	x_put_byte(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 18 (3/1) */
/* 4 4,0   */

/* MOVE.B #<data>.B,(An) */
void REGPARAM2 op_10bc_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 12; 
	uae_s8 src = (uae_u8)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	ipl_fetch_now();
	x_put_byte(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 12 (2/1) */
/* 4 0,0   */

/* MOVE.B Dn,(An)+ */
void REGPARAM2 op_10c0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 8;  
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	ipl_fetch_next_pre();
	x_put_byte(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, dstreg) -= areg_byteinc[dstreg];
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return;
	}
	m68k_incpci(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 8 (1/1) */
/* 2 0,0   */

/* MOVE.B (An),(An)+ */
void REGPARAM2 op_10d0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	x_put_byte(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, dstreg) -= areg_byteinc[dstreg];
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return;
	}
	m68k_incpci(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 12 (2/1) */
/* 2 0,0   */

/* MOVE.B (An)+,(An)+ */
void REGPARAM2 op_10d8_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	x_put_byte(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, dstreg) -= areg_byteinc[dstreg];
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return;
	}
	m68k_incpci(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 12 (2/1) */
/* 2 0,0   */

/* MOVE.B -(An),(An)+ */
void REGPARAM2 op_10e0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
	do_cycles_ce000_internal(2);
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	m68k_areg(regs, srcreg) = srca;
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	x_put_byte(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, dstreg) -= areg_byteinc[dstreg];
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return;
	}
	m68k_incpci(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 14 (2/1) */
/* 2 0,0   */

/* MOVE.B (d16,An),(An)+ */
void REGPARAM2 op_10e8_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	x_put_byte(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, dstreg) -= areg_byteinc[dstreg];
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* MOVE.B (d8,An,Xn),(An)+ */
void REGPARAM2 op_10f0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	do_cycles_ce000_internal(2);
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	x_put_byte(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, dstreg) -= areg_byteinc[dstreg];
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 18 (3/1) */
/* 4 4,0   */

/* MOVE.B (xxx).W,(An)+ */
void REGPARAM2 op_10f8_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	x_put_byte(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, dstreg) -= areg_byteinc[dstreg];
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* MOVE.B (xxx).L,(An)+ */
void REGPARAM2 op_10f9_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	srca = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	srca |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	x_put_byte(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		m68k_areg(regs, dstreg) -= areg_byteinc[dstreg];
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return;
	}
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 20 (4/1) */
/* 6 0,0   */

/* MOVE.B (d16,PC),(An)+ */
void REGPARAM2 op_10fa_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = m68k_getpci() + 2;
	srca += (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 2);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	x_put_byte(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, dstreg) -= areg_byteinc[dstreg];
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* MOVE.B (d8,PC,Xn),(An)+ */
void REGPARAM2 op_10fb_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	uaecptr tmppc = m68k_getpci() + 2;
	do_cycles_ce000_internal(2);
	srca = get_disp_ea_000(tmppc, get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 2);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	x_put_byte(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, dstreg) -= areg_byteinc[dstreg];
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 18 (3/1) */
/* 4 4,0   */

/* MOVE.B #<data>.B,(An)+ */
void REGPARAM2 op_10fc_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 12; 
	ipl_fetch_now();
	uae_s8 src = (uae_u8)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	x_put_byte(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, dstreg) -= areg_byteinc[dstreg];
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 12 (2/1) */
/* 4 0,0   */

/* MOVE.B Dn,-(An) */
void REGPARAM2 op_1100_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 8;  
	ipl_fetch_next_pre();
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
	m68k_areg(regs, dstreg) = dsta;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	x_put_byte(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 8 (1/1) */
/* 2 0,0   */

/* MOVE.B (An),-(An) */
void REGPARAM2 op_1110_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
	m68k_areg(regs, dstreg) = dsta;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	x_put_byte(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 12 (2/1) */
/* 2 0,0   */

/* MOVE.B (An)+,-(An) */
void REGPARAM2 op_1118_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
	m68k_areg(regs, dstreg) = dsta;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	x_put_byte(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 12 (2/1) */
/* 2 0,0   */

/* MOVE.B -(An),-(An) */
void REGPARAM2 op_1120_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
	do_cycles_ce000_internal(2);
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	m68k_areg(regs, srcreg) = srca;
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
	m68k_areg(regs, dstreg) = dsta;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	x_put_byte(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 14 (2/1) */
/* 2 0,0   */

/* MOVE.B (d16,An),-(An) */
void REGPARAM2 op_1128_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
	m68k_areg(regs, dstreg) = dsta;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	x_put_byte(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* MOVE.B (d8,An,Xn),-(An) */
void REGPARAM2 op_1130_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	do_cycles_ce000_internal(2);
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
	m68k_areg(regs, dstreg) = dsta;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	x_put_byte(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 18 (3/1) */
/* 4 4,0   */

/* MOVE.B (xxx).W,-(An) */
void REGPARAM2 op_1138_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
	m68k_areg(regs, dstreg) = dsta;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	x_put_byte(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* MOVE.B (xxx).L,-(An) */
void REGPARAM2 op_1139_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	srca = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	srca |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
	m68k_areg(regs, dstreg) = dsta;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	opcode = regs.ir;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	x_put_byte(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 20 (4/1) */
/* 6 0,0   */

/* MOVE.B (d16,PC),-(An) */
void REGPARAM2 op_113a_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = m68k_getpci() + 2;
	srca += (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 2);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
	m68k_areg(regs, dstreg) = dsta;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	x_put_byte(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* MOVE.B (d8,PC,Xn),-(An) */
void REGPARAM2 op_113b_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	uaecptr tmppc = m68k_getpci() + 2;
	do_cycles_ce000_internal(2);
	srca = get_disp_ea_000(tmppc, get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 2);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
	m68k_areg(regs, dstreg) = dsta;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	x_put_byte(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 18 (3/1) */
/* 4 4,0   */

/* MOVE.B #<data>.B,-(An) */
void REGPARAM2 op_113c_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 12; 
	ipl_fetch_now();
	uae_s8 src = (uae_u8)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
	m68k_areg(regs, dstreg) = dsta;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	x_put_byte(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 12 (2/1) */
/* 4 0,0   */

/* MOVE.B Dn,(d16,An) */
void REGPARAM2 op_1140_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 12; 
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	ipl_fetch_now();
	x_put_byte(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 12 (2/1) */
/* 4 0,0   */

/* MOVE.B (An),(d16,An) */
void REGPARAM2 op_1150_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 4, 0);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	ipl_fetch_now();
	x_put_byte(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* MOVE.B (An)+,(d16,An) */
void REGPARAM2 op_1158_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 4, 0);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	ipl_fetch_now();
	x_put_byte(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* MOVE.B -(An),(d16,An) */
void REGPARAM2 op_1160_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
	do_cycles_ce000_internal(2);
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	m68k_areg(regs, srcreg) = srca;
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 4, 0);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	ipl_fetch_now();
	x_put_byte(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 18 (3/1) */
/* 4 0,0   */

/* MOVE.B (d16,An),(d16,An) */
void REGPARAM2 op_1168_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 6, 0);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	ipl_fetch_now();
	x_put_byte(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return;
	}
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 20 (4/1) */
/* 6 0,0   */

/* MOVE.B (d8,An,Xn),(d16,An) */
void REGPARAM2 op_1170_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 22; 
	uaecptr srca;
	do_cycles_ce000_internal(2);
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 6, 0);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	ipl_fetch_now();
	x_put_byte(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return;
	}
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 22 (4/1) */
/* 6 6,0   */

/* MOVE.B (xxx).W,(d16,An) */
void REGPARAM2 op_1178_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 6, 0);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	ipl_fetch_now();
	x_put_byte(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return;
	}
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 20 (4/1) */
/* 6 0,0   */

/* MOVE.B (xxx).L,(d16,An) */
void REGPARAM2 op_1179_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 24; 
	uaecptr srca;
	srca = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	srca |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 8, 0);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	ipl_fetch_now();
	x_put_byte(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return;
	}
	m68k_incpci(8);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 24 (5/1) */
/* 8 0,0   */

/* MOVE.B (d16,PC),(d16,An) */
void REGPARAM2 op_117a_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	srca = m68k_getpci() + 2;
	srca += (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 2);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 6, 0);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	ipl_fetch_now();
	x_put_byte(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return;
	}
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 20 (4/1) */
/* 6 0,0   */

/* MOVE.B (d8,PC,Xn),(d16,An) */
void REGPARAM2 op_117b_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 22; 
	uaecptr srca;
	uaecptr tmppc = m68k_getpci() + 2;
	do_cycles_ce000_internal(2);
	srca = get_disp_ea_000(tmppc, get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 2);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 6, 0);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	ipl_fetch_now();
	x_put_byte(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return;
	}
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 22 (4/1) */
/* 6 6,0   */

/* MOVE.B #<data>.B,(d16,An) */
void REGPARAM2 op_117c_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 16; 
	uae_s8 src = (uae_u8)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, 0);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	ipl_fetch_now();
	x_put_byte(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return;
	}
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 16 (3/1) */
/* 6 0,0   */

/* MOVE.B Dn,(d8,An,Xn) */
void REGPARAM2 op_1180_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 14; 
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	do_cycles_ce000_internal(2);
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	ipl_fetch_now();
	x_put_byte(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 14 (2/1) */
/* 4 4,0   */

/* MOVE.B (An),(d8,An,Xn) */
void REGPARAM2 op_1190_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	uaecptr dsta;
	do_cycles_ce000_internal(2);
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 4, 0);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	ipl_fetch_now();
	x_put_byte(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 18 (3/1) */
/* 4 4,0   */

/* MOVE.B (An)+,(d8,An,Xn) */
void REGPARAM2 op_1198_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
	uaecptr dsta;
	do_cycles_ce000_internal(2);
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 4, 0);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	ipl_fetch_now();
	x_put_byte(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 18 (3/1) */
/* 4 4,0   */

/* MOVE.B -(An),(d8,An,Xn) */
void REGPARAM2 op_11a0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
	do_cycles_ce000_internal(2);
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	m68k_areg(regs, srcreg) = srca;
	uaecptr dsta;
	do_cycles_ce000_internal(2);
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 4, 0);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	ipl_fetch_now();
	x_put_byte(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 20 (3/1) */
/* 4 4,0   */

/* MOVE.B (d16,An),(d8,An,Xn) */
void REGPARAM2 op_11a8_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 22; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	uaecptr dsta;
	do_cycles_ce000_internal(2);
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_ce000_prefetch(6));
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 6, 0);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	ipl_fetch_now();
	x_put_byte(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return;
	}
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 22 (4/1) */
/* 6 4,0   */

/* MOVE.B (d8,An,Xn),(d8,An,Xn) */
void REGPARAM2 op_11b0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 24; 
	uaecptr srca;
	do_cycles_ce000_internal(2);
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	uaecptr dsta;
	do_cycles_ce000_internal(2);
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_ce000_prefetch(6));
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 6, 0);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	ipl_fetch_now();
	x_put_byte(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return;
	}
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 24 (4/1) */
/* 6 6,4   */

/* MOVE.B (xxx).W,(d8,An,Xn) */
void REGPARAM2 op_11b8_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 22; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	uaecptr dsta;
	do_cycles_ce000_internal(2);
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_ce000_prefetch(6));
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 6, 0);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	ipl_fetch_now();
	x_put_byte(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return;
	}
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 22 (4/1) */
/* 6 4,0   */

/* MOVE.B (xxx).L,(d8,An,Xn) */
void REGPARAM2 op_11b9_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 26; 
	uaecptr srca;
	srca = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	srca |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	uaecptr dsta;
	do_cycles_ce000_internal(2);
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_ce000_prefetch(8));
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 8, 0);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	ipl_fetch_now();
	x_put_byte(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return;
	}
	m68k_incpci(8);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 26 (5/1) */
/* 8 4,0   */

/* MOVE.B (d16,PC),(d8,An,Xn) */
void REGPARAM2 op_11ba_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 22; 
	uaecptr srca;
	srca = m68k_getpci() + 2;
	srca += (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 2);
		return;
	}
	uaecptr dsta;
	do_cycles_ce000_internal(2);
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_ce000_prefetch(6));
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 6, 0);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	ipl_fetch_now();
	x_put_byte(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return;
	}
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 22 (4/1) */
/* 6 4,0   */

/* MOVE.B (d8,PC,Xn),(d8,An,Xn) */
void REGPARAM2 op_11bb_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 24; 
	uaecptr srca;
	uaecptr tmppc = m68k_getpci() + 2;
	do_cycles_ce000_internal(2);
	srca = get_disp_ea_000(tmppc, get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 2);
		return;
	}
	uaecptr dsta;
	do_cycles_ce000_internal(2);
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_ce000_prefetch(6));
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 6, 0);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	ipl_fetch_now();
	x_put_byte(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return;
	}
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 24 (4/1) */
/* 6 6,4   */

/* MOVE.B #<data>.B,(d8,An,Xn) */
void REGPARAM2 op_11bc_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 18; 
	uae_s8 src = (uae_u8)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr dsta;
	do_cycles_ce000_internal(2);
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_ce000_prefetch(6));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, 0);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	ipl_fetch_now();
	x_put_byte(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return;
	}
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 18 (3/1) */
/* 6 4,0   */

/* MOVE.B Dn,(xxx).W */
void REGPARAM2 op_11c0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 30;
	CurrentInstrCycles = 12; 
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 4, 0);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	x_put_byte(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return;
	}
	ipl_fetch_next();
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 12 (2/1) */
/* 4 0,0   */

/* MOVE.B (An),(xxx).W */
void REGPARAM2 op_11d0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 30;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 4, 0);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	x_put_byte(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return;
	}
	ipl_fetch_next();
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* MOVE.B (An)+,(xxx).W */
void REGPARAM2 op_11d8_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 30;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 4, 0);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	x_put_byte(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return;
	}
	ipl_fetch_next();
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* MOVE.B -(An),(xxx).W */
void REGPARAM2 op_11e0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 30;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
	do_cycles_ce000_internal(2);
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	m68k_areg(regs, srcreg) = srca;
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 4, 0);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	x_put_byte(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return;
	}
	ipl_fetch_next();
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 18 (3/1) */
/* 4 0,0   */

/* MOVE.B (d16,An),(xxx).W */
void REGPARAM2 op_11e8_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 30;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 6, 0);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	x_put_byte(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return;
	}
	ipl_fetch_next();
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 20 (4/1) */
/* 6 0,0   */

/* MOVE.B (d8,An,Xn),(xxx).W */
void REGPARAM2 op_11f0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 30;
	CurrentInstrCycles = 22; 
	uaecptr srca;
	do_cycles_ce000_internal(2);
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 6, 0);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	x_put_byte(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return;
	}
	ipl_fetch_next();
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 22 (4/1) */
/* 6 6,0   */

/* MOVE.B (xxx).W,(xxx).W */
void REGPARAM2 op_11f8_14_ff(uae_u32 opcode)
{
	OpcodeFamily = 30;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 6, 0);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	x_put_byte(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return;
	}
	ipl_fetch_next();
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 20 (4/1) */
/* 6 0,0   */

/* MOVE.B (xxx).L,(xxx).W */
void REGPARAM2 op_11f9_14_ff(uae_u32 opcode)
{
	OpcodeFamily = 30;
	CurrentInstrCycles = 24; 
	uaecptr srca;
	srca = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	srca |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 8, 0);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	x_put_byte(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return;
	}
	ipl_fetch_next();
	m68k_incpci(8);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 24 (5/1) */
/* 8 0,0   */

/* MOVE.B (d16,PC),(xxx).W */
void REGPARAM2 op_11fa_14_ff(uae_u32 opcode)
{
	OpcodeFamily = 30;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	srca = m68k_getpci() + 2;
	srca += (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 2);
		return;
	}
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 6, 0);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	x_put_byte(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return;
	}
	ipl_fetch_next();
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 20 (4/1) */
/* 6 0,0   */

/* MOVE.B (d8,PC,Xn),(xxx).W */
void REGPARAM2 op_11fb_14_ff(uae_u32 opcode)
{
	OpcodeFamily = 30;
	CurrentInstrCycles = 22; 
	uaecptr srca;
	uaecptr tmppc = m68k_getpci() + 2;
	do_cycles_ce000_internal(2);
	srca = get_disp_ea_000(tmppc, get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 2);
		return;
	}
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 6, 0);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	x_put_byte(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return;
	}
	ipl_fetch_next();
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 22 (4/1) */
/* 6 6,0   */

/* MOVE.B #<data>.B,(xxx).W */
void REGPARAM2 op_11fc_14_ff(uae_u32 opcode)
{
	OpcodeFamily = 30;
	CurrentInstrCycles = 16; 
	uae_s8 src = (uae_u8)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 6, 0);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	x_put_byte(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return;
	}
	ipl_fetch_next();
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 16 (3/1) */
/* 6 0,0   */

/* MOVE.B Dn,(xxx).L */
void REGPARAM2 op_13c0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 30;
	CurrentInstrCycles = 16; 
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	dsta |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	x_put_byte(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return;
	}
	ipl_fetch_next();
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 16 (3/1) */
/* 6 0,0   */

/* MOVE.B (An),(xxx).L */
void REGPARAM2 op_13d0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 30;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	uaecptr dsta;
	dsta = get_word_ce000_prefetch(4) << 16;
	dsta |= regs.irc;
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 4, 0);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	x_put_byte(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return;
	}
	ipl_fetch_now();
	m68k_incpci(6);
	get_word_ce000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, 0);
		return;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	if(regs.t1) opcode |= 0x10000;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 20 (4/1) */
/* 6 0,0   */

/* MOVE.B (An)+,(xxx).L */
void REGPARAM2 op_13d8_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 30;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
	uaecptr dsta;
	dsta = get_word_ce000_prefetch(4) << 16;
	dsta |= regs.irc;
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 4, 0);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	x_put_byte(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return;
	}
	ipl_fetch_now();
	m68k_incpci(6);
	get_word_ce000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, 0);
		return;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	if(regs.t1) opcode |= 0x10000;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 20 (4/1) */
/* 6 0,0   */

/* MOVE.B -(An),(xxx).L */
void REGPARAM2 op_13e0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 30;
	CurrentInstrCycles = 22; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
	do_cycles_ce000_internal(2);
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	m68k_areg(regs, srcreg) = srca;
	uaecptr dsta;
	dsta = get_word_ce000_prefetch(4) << 16;
	dsta |= regs.irc;
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 4, 0);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	x_put_byte(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return;
	}
	ipl_fetch_now();
	m68k_incpci(6);
	get_word_ce000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, 0);
		return;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	if(regs.t1) opcode |= 0x10000;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 22 (4/1) */
/* 6 0,0   */

/* MOVE.B (d16,An),(xxx).L */
void REGPARAM2 op_13e8_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 30;
	CurrentInstrCycles = 24; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	uaecptr dsta;
	dsta = get_word_ce000_prefetch(6) << 16;
	dsta |= regs.irc;
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 6, 0);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	x_put_byte(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return;
	}
	ipl_fetch_now();
	m68k_incpci(8);
	get_word_ce000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, 0);
		return;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	if(regs.t1) opcode |= 0x10000;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 24 (5/1) */
/* 8 0,0   */

/* MOVE.B (d8,An,Xn),(xxx).L */
void REGPARAM2 op_13f0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 30;
	CurrentInstrCycles = 26; 
	uaecptr srca;
	do_cycles_ce000_internal(2);
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	uaecptr dsta;
	dsta = get_word_ce000_prefetch(6) << 16;
	dsta |= regs.irc;
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 6, 0);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	x_put_byte(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return;
	}
	ipl_fetch_now();
	m68k_incpci(8);
	get_word_ce000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, 0);
		return;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	if(regs.t1) opcode |= 0x10000;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 26 (5/1) */
/* 8 8,0   */

/* MOVE.B (xxx).W,(xxx).L */
void REGPARAM2 op_13f8_14_ff(uae_u32 opcode)
{
	OpcodeFamily = 30;
	CurrentInstrCycles = 24; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	uaecptr dsta;
	dsta = get_word_ce000_prefetch(6) << 16;
	dsta |= regs.irc;
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 6, 0);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	x_put_byte(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return;
	}
	ipl_fetch_now();
	m68k_incpci(8);
	get_word_ce000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, 0);
		return;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	if(regs.t1) opcode |= 0x10000;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 24 (5/1) */
/* 8 0,0   */

/* MOVE.B (xxx).L,(xxx).L */
void REGPARAM2 op_13f9_14_ff(uae_u32 opcode)
{
	OpcodeFamily = 30;
	CurrentInstrCycles = 28; 
	uaecptr srca;
	srca = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	srca |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	uaecptr dsta;
	dsta = get_word_ce000_prefetch(8) << 16;
	dsta |= regs.irc;
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 8, 0);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	x_put_byte(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return;
	}
	ipl_fetch_now();
	m68k_incpci(10);
	get_word_ce000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, 0);
		return;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	if(regs.t1) opcode |= 0x10000;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 28 (6/1) */
/* 10 0,0   */

/* MOVE.B (d16,PC),(xxx).L */
void REGPARAM2 op_13fa_14_ff(uae_u32 opcode)
{
	OpcodeFamily = 30;
	CurrentInstrCycles = 24; 
	uaecptr srca;
	srca = m68k_getpci() + 2;
	srca += (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 2);
		return;
	}
	uaecptr dsta;
	dsta = get_word_ce000_prefetch(6) << 16;
	dsta |= regs.irc;
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 6, 0);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	x_put_byte(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return;
	}
	ipl_fetch_now();
	m68k_incpci(8);
	get_word_ce000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, 0);
		return;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	if(regs.t1) opcode |= 0x10000;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 24 (5/1) */
/* 8 0,0   */

/* MOVE.B (d8,PC,Xn),(xxx).L */
void REGPARAM2 op_13fb_14_ff(uae_u32 opcode)
{
	OpcodeFamily = 30;
	CurrentInstrCycles = 26; 
	uaecptr srca;
	uaecptr tmppc = m68k_getpci() + 2;
	do_cycles_ce000_internal(2);
	srca = get_disp_ea_000(tmppc, get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 2);
		return;
	}
	uaecptr dsta;
	dsta = get_word_ce000_prefetch(6) << 16;
	dsta |= regs.irc;
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 6, 0);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	x_put_byte(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return;
	}
	ipl_fetch_now();
	m68k_incpci(8);
	get_word_ce000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, 0);
		return;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	if(regs.t1) opcode |= 0x10000;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 26 (5/1) */
/* 8 8,0   */

/* MOVE.B #<data>.B,(xxx).L */
void REGPARAM2 op_13fc_14_ff(uae_u32 opcode)
{
	OpcodeFamily = 30;
	CurrentInstrCycles = 20; 
	uae_s8 src = (uae_u8)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr dsta;
	dsta = get_word_ce000_prefetch(6) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return;
	}
	dsta |= get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 8, pcoffset);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	x_put_byte(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return;
	}
	ipl_fetch_next();
	m68k_incpci(8);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 20 (4/1) */
/* 8 0,0   */

/* MOVE.L Dn,Dn */
void REGPARAM2 op_2000_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 4;  
	uae_s32 src = m68k_dreg(regs, srcreg);
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	m68k_dreg(regs, dstreg) = (src);
	m68k_incpci(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 4 (1/0) */
/* 2 0,0   */

/* MOVE.L An,Dn */
void REGPARAM2 op_2008_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 4;  
	uae_s32 src = m68k_areg(regs, srcreg);
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	m68k_dreg(regs, dstreg) = (src);
	m68k_incpci(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 4 (1/0) */
/* 2 0,0   */

/* MOVE.L (An),Dn */
void REGPARAM2 op_2010_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	m68k_dreg(regs, dstreg) = (src);
	m68k_incpci(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 12 (3/0) */
/* 2 0,0   */

/* MOVE.L (An)+,Dn */
void REGPARAM2 op_2018_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	m68k_areg(regs, srcreg) += 4;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	m68k_dreg(regs, dstreg) = (src);
	m68k_incpci(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 12 (3/0) */
/* 2 0,0   */

/* MOVE.L -(An),Dn */
void REGPARAM2 op_2020_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - 4;
	do_cycles_ce000_internal(2);
	if (srca & 1) {
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	m68k_areg(regs, srcreg) = srca;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	m68k_dreg(regs, dstreg) = (src);
	m68k_incpci(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 14 (3/0) */
/* 2 0,0   */

/* MOVE.L (d16,An),Dn */
void REGPARAM2 op_2028_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	m68k_dreg(regs, dstreg) = (src);
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 16 (4/0) */
/* 4 0,0   */

/* MOVE.L (d8,An,Xn),Dn */
void REGPARAM2 op_2030_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	do_cycles_ce000_internal(2);
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	m68k_dreg(regs, dstreg) = (src);
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 18 (4/0) */
/* 4 4,0   */

/* MOVE.L (xxx).W,Dn */
void REGPARAM2 op_2038_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	if (srca & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	m68k_dreg(regs, dstreg) = (src);
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 16 (4/0) */
/* 4 0,0   */

/* MOVE.L (xxx).L,Dn */
void REGPARAM2 op_2039_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	srca = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	srca |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	if (srca & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	m68k_dreg(regs, dstreg) = (src);
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 20 (5/0) */
/* 6 0,0   */

/* MOVE.L (d16,PC),Dn */
void REGPARAM2 op_203a_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = m68k_getpci() + 2;
	srca += (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 2);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return;
	}
	ipl_fetch_now();
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 2);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	m68k_dreg(regs, dstreg) = (src);
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 16 (4/0) */
/* 4 0,0   */

/* MOVE.L (d8,PC,Xn),Dn */
void REGPARAM2 op_203b_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	uaecptr tmppc = m68k_getpci() + 2;
	do_cycles_ce000_internal(2);
	srca = get_disp_ea_000(tmppc, get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 2);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return;
	}
	ipl_fetch_now();
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 2);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	m68k_dreg(regs, dstreg) = (src);
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 18 (4/0) */
/* 4 4,0   */

/* MOVE.L #<data>.L,Dn */
void REGPARAM2 op_203c_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 12; 
	uae_s32 src;
	src = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	src |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	m68k_dreg(regs, dstreg) = (src);
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 12 (3/0) */
/* 6 0,0   */

/* MOVEA.L Dn,An */
void REGPARAM2 op_2040_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 31;
	CurrentInstrCycles = 4;  
	uae_s32 src = m68k_dreg(regs, srcreg);
	m68k_areg(regs, dstreg) = (src);
	m68k_incpci(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 4 (1/0) */
/* 2 0,0   */

/* MOVEA.L An,An */
void REGPARAM2 op_2048_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 31;
	CurrentInstrCycles = 4;  
	uae_s32 src = m68k_areg(regs, srcreg);
	m68k_areg(regs, dstreg) = (src);
	m68k_incpci(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 4 (1/0) */
/* 2 0,0   */

/* MOVEA.L (An),An */
void REGPARAM2 op_2050_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 31;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	m68k_areg(regs, dstreg) = (src);
	m68k_incpci(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 12 (3/0) */
/* 2 0,0   */

/* MOVEA.L (An)+,An */
void REGPARAM2 op_2058_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 31;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	m68k_areg(regs, srcreg) += 4;
	m68k_areg(regs, dstreg) = (src);
	m68k_incpci(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 12 (3/0) */
/* 2 0,0   */

/* MOVEA.L -(An),An */
void REGPARAM2 op_2060_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 31;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - 4;
	do_cycles_ce000_internal(2);
	if (srca & 1) {
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	m68k_areg(regs, srcreg) = srca;
	m68k_areg(regs, dstreg) = (src);
	m68k_incpci(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 14 (3/0) */
/* 2 0,0   */

/* MOVEA.L (d16,An),An */
void REGPARAM2 op_2068_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 31;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	m68k_areg(regs, dstreg) = (src);
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 16 (4/0) */
/* 4 0,0   */

/* MOVEA.L (d8,An,Xn),An */
void REGPARAM2 op_2070_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 31;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	do_cycles_ce000_internal(2);
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	m68k_areg(regs, dstreg) = (src);
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 18 (4/0) */
/* 4 4,0   */

/* MOVEA.L (xxx).W,An */
void REGPARAM2 op_2078_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 31;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	if (srca & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	m68k_areg(regs, dstreg) = (src);
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 16 (4/0) */
/* 4 0,0   */

/* MOVEA.L (xxx).L,An */
void REGPARAM2 op_2079_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 31;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	srca = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	srca |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	if (srca & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	m68k_areg(regs, dstreg) = (src);
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 20 (5/0) */
/* 6 0,0   */

/* MOVEA.L (d16,PC),An */
void REGPARAM2 op_207a_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 31;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = m68k_getpci() + 2;
	srca += (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 2);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return;
	}
	ipl_fetch_now();
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 2);
		return;
	}
	m68k_areg(regs, dstreg) = (src);
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 16 (4/0) */
/* 4 0,0   */

/* MOVEA.L (d8,PC,Xn),An */
void REGPARAM2 op_207b_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 31;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	uaecptr tmppc = m68k_getpci() + 2;
	do_cycles_ce000_internal(2);
	srca = get_disp_ea_000(tmppc, get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 2);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return;
	}
	ipl_fetch_now();
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 2);
		return;
	}
	m68k_areg(regs, dstreg) = (src);
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 18 (4/0) */
/* 4 4,0   */

/* MOVEA.L #<data>.L,An */
void REGPARAM2 op_207c_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 31;
	CurrentInstrCycles = 12; 
	uae_s32 src;
	src = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	src |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	m68k_areg(regs, dstreg) = (src);
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 12 (3/0) */
/* 6 0,0   */

/* MOVE.L Dn,(An) */
void REGPARAM2 op_2080_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 12; 
	uae_s32 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	if (dsta & 1) {
		m68k_incpci(4);
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return;
	}
	ipl_fetch_now();
	x_put_word(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	x_put_word(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		ccr_68000_long_move_ae_LZN(src);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return;
	}
	m68k_incpci(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 12 (1/2) */
/* 2 0,0   */

/* MOVE.L An,(An) */
void REGPARAM2 op_2088_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 12; 
	uae_s32 src = m68k_areg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	if (dsta & 1) {
		m68k_incpci(4);
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return;
	}
	ipl_fetch_now();
	x_put_word(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	x_put_word(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		ccr_68000_long_move_ae_LZN(src);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return;
	}
	m68k_incpci(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 12 (1/2) */
/* 2 0,0   */

/* MOVE.L (An),(An) */
void REGPARAM2 op_2090_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	if (dsta & 1) {
		m68k_incpci(4);
		ccr_68000_long_move_ae_LZN(src);
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return;
	}
	x_put_word(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		ccr_68000_long_move_ae_LZN(src);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	ipl_fetch_now();
	x_put_word(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return;
	}
	m68k_incpci(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 20 (3/2) */
/* 2 0,0   */

/* MOVE.L (An)+,(An) */
void REGPARAM2 op_2098_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	m68k_areg(regs, srcreg) += 4;
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	if (dsta & 1) {
		m68k_incpci(4);
		ccr_68000_long_move_ae_LZN(src);
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return;
	}
	x_put_word(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		ccr_68000_long_move_ae_LZN(src);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	ipl_fetch_now();
	x_put_word(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return;
	}
	m68k_incpci(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 20 (3/2) */
/* 2 0,0   */

/* MOVE.L -(An),(An) */
void REGPARAM2 op_20a0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 22; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - 4;
	do_cycles_ce000_internal(2);
	if (srca & 1) {
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	m68k_areg(regs, srcreg) = srca;
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	if (dsta & 1) {
		m68k_incpci(4);
		ccr_68000_long_move_ae_LZN(src);
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return;
	}
	x_put_word(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		ccr_68000_long_move_ae_LZN(src);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	ipl_fetch_now();
	x_put_word(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return;
	}
	m68k_incpci(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 22 (3/2) */
/* 2 0,0   */

/* MOVE.L (d16,An),(An) */
void REGPARAM2 op_20a8_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 24; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	if (dsta & 1) {
		m68k_incpci(6);
		ccr_68000_long_move_ae_LZN(src);
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return;
	}
	x_put_word(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		ccr_68000_long_move_ae_LZN(src);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	ipl_fetch_now();
	x_put_word(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 24 (4/2) */
/* 4 0,0   */

/* MOVE.L (d8,An,Xn),(An) */
void REGPARAM2 op_20b0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 26; 
	uaecptr srca;
	do_cycles_ce000_internal(2);
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	if (dsta & 1) {
		m68k_incpci(6);
		ccr_68000_long_move_ae_LZN(src);
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return;
	}
	x_put_word(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		ccr_68000_long_move_ae_LZN(src);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	ipl_fetch_now();
	x_put_word(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 26 (4/2) */
/* 4 4,0   */

/* MOVE.L (xxx).W,(An) */
void REGPARAM2 op_20b8_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 24; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	if (srca & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	if (dsta & 1) {
		m68k_incpci(6);
		ccr_68000_long_move_ae_LZN(src);
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return;
	}
	x_put_word(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		ccr_68000_long_move_ae_LZN(src);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	ipl_fetch_now();
	x_put_word(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 24 (4/2) */
/* 4 0,0   */

/* MOVE.L (xxx).L,(An) */
void REGPARAM2 op_20b9_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 28; 
	uaecptr srca;
	srca = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	srca |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	if (srca & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	if (dsta & 1) {
		m68k_incpci(8);
		ccr_68000_long_move_ae_LZN(src);
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return;
	}
	x_put_word(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		ccr_68000_long_move_ae_LZN(src);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	x_put_word(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return;
	}
	ipl_fetch_next();
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 28 (5/2) */
/* 6 0,0   */

/* MOVE.L (d16,PC),(An) */
void REGPARAM2 op_20ba_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 24; 
	uaecptr srca;
	srca = m68k_getpci() + 2;
	srca += (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 2);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return;
	}
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 2);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	if (dsta & 1) {
		m68k_incpci(6);
		ccr_68000_long_move_ae_LZN(src);
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return;
	}
	x_put_word(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		ccr_68000_long_move_ae_LZN(src);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	ipl_fetch_now();
	x_put_word(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 24 (4/2) */
/* 4 0,0   */

/* MOVE.L (d8,PC,Xn),(An) */
void REGPARAM2 op_20bb_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 26; 
	uaecptr srca;
	uaecptr tmppc = m68k_getpci() + 2;
	do_cycles_ce000_internal(2);
	srca = get_disp_ea_000(tmppc, get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 2);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return;
	}
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 2);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	if (dsta & 1) {
		m68k_incpci(6);
		ccr_68000_long_move_ae_LZN(src);
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return;
	}
	x_put_word(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		ccr_68000_long_move_ae_LZN(src);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	ipl_fetch_now();
	x_put_word(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 26 (4/2) */
/* 4 4,0   */

/* MOVE.L #<data>.L,(An) */
void REGPARAM2 op_20bc_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 20; 
	uae_s32 src;
	src = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	src |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	ipl_fetch_now();
	if (dsta & 1) {
		m68k_incpci(8);
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return;
	}
	x_put_word(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	x_put_word(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		ccr_68000_long_move_ae_LZN(src);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return;
	}
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 20 (3/2) */
/* 6 0,0   */

/* MOVE.L Dn,(An)+ */
void REGPARAM2 op_20c0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 12; 
	uae_s32 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	m68k_areg(regs, dstreg) += 4;
	if (dsta & 1) {
		m68k_incpci(4);
		m68k_areg(regs, dstreg) -= 4;
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return;
	}
	ipl_fetch_now();
	x_put_word(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, dstreg) -= 4;
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	x_put_word(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		ccr_68000_long_move_ae_LZN(src);
		m68k_areg(regs, dstreg) -= 4;
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return;
	}
	m68k_incpci(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 12 (1/2) */
/* 2 0,0   */

/* MOVE.L An,(An)+ */
void REGPARAM2 op_20c8_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 12; 
	uae_s32 src = m68k_areg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	m68k_areg(regs, dstreg) += 4;
	if (dsta & 1) {
		m68k_incpci(4);
		m68k_areg(regs, dstreg) -= 4;
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return;
	}
	ipl_fetch_now();
	x_put_word(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, dstreg) -= 4;
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	x_put_word(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		ccr_68000_long_move_ae_LZN(src);
		m68k_areg(regs, dstreg) -= 4;
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return;
	}
	m68k_incpci(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 12 (1/2) */
/* 2 0,0   */

/* MOVE.L (An),(An)+ */
void REGPARAM2 op_20d0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	m68k_areg(regs, dstreg) += 4;
	ipl_fetch_now();
	if (dsta & 1) {
		m68k_incpci(4);
		m68k_areg(regs, dstreg) -= 4;
		ccr_68000_long_move_ae_LZN(src);
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return;
	}
	x_put_word(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		ccr_68000_long_move_ae_LZN(src);
		m68k_areg(regs, dstreg) -= 4;
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	x_put_word(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		ccr_68000_long_move_ae_normal(src);
		m68k_areg(regs, dstreg) -= 4;
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return;
	}
	m68k_incpci(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 20 (3/2) */
/* 2 0,0   */

/* MOVE.L (An)+,(An)+ */
void REGPARAM2 op_20d8_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	m68k_areg(regs, srcreg) += 4;
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	m68k_areg(regs, dstreg) += 4;
	ipl_fetch_now();
	if (dsta & 1) {
		m68k_incpci(4);
		m68k_areg(regs, dstreg) -= 4;
		ccr_68000_long_move_ae_LZN(src);
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return;
	}
	x_put_word(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		ccr_68000_long_move_ae_LZN(src);
		m68k_areg(regs, dstreg) -= 4;
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	x_put_word(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		ccr_68000_long_move_ae_normal(src);
		m68k_areg(regs, dstreg) -= 4;
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return;
	}
	m68k_incpci(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 20 (3/2) */
/* 2 0,0   */

/* MOVE.L -(An),(An)+ */
void REGPARAM2 op_20e0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 22; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - 4;
	do_cycles_ce000_internal(2);
	if (srca & 1) {
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	m68k_areg(regs, srcreg) = srca;
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	m68k_areg(regs, dstreg) += 4;
	ipl_fetch_now();
	if (dsta & 1) {
		m68k_incpci(4);
		m68k_areg(regs, dstreg) -= 4;
		ccr_68000_long_move_ae_LZN(src);
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return;
	}
	x_put_word(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		ccr_68000_long_move_ae_LZN(src);
		m68k_areg(regs, dstreg) -= 4;
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	x_put_word(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		ccr_68000_long_move_ae_normal(src);
		m68k_areg(regs, dstreg) -= 4;
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return;
	}
	m68k_incpci(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 22 (3/2) */
/* 2 0,0   */

/* MOVE.L (d16,An),(An)+ */
void REGPARAM2 op_20e8_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 24; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	m68k_areg(regs, dstreg) += 4;
	ipl_fetch_now();
	if (dsta & 1) {
		m68k_incpci(6);
		m68k_areg(regs, dstreg) -= 4;
		ccr_68000_long_move_ae_LZN(src);
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return;
	}
	x_put_word(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		ccr_68000_long_move_ae_LZN(src);
		m68k_areg(regs, dstreg) -= 4;
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	x_put_word(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		ccr_68000_long_move_ae_normal(src);
		m68k_areg(regs, dstreg) -= 4;
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 24 (4/2) */
/* 4 0,0   */

/* MOVE.L (d8,An,Xn),(An)+ */
void REGPARAM2 op_20f0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 26; 
	uaecptr srca;
	do_cycles_ce000_internal(2);
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	m68k_areg(regs, dstreg) += 4;
	ipl_fetch_now();
	if (dsta & 1) {
		m68k_incpci(6);
		m68k_areg(regs, dstreg) -= 4;
		ccr_68000_long_move_ae_LZN(src);
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return;
	}
	x_put_word(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		ccr_68000_long_move_ae_LZN(src);
		m68k_areg(regs, dstreg) -= 4;
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	x_put_word(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		ccr_68000_long_move_ae_normal(src);
		m68k_areg(regs, dstreg) -= 4;
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 26 (4/2) */
/* 4 4,0   */

/* MOVE.L (xxx).W,(An)+ */
void REGPARAM2 op_20f8_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 24; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	if (srca & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	m68k_areg(regs, dstreg) += 4;
	ipl_fetch_now();
	if (dsta & 1) {
		m68k_incpci(6);
		m68k_areg(regs, dstreg) -= 4;
		ccr_68000_long_move_ae_LZN(src);
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return;
	}
	x_put_word(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		ccr_68000_long_move_ae_LZN(src);
		m68k_areg(regs, dstreg) -= 4;
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	x_put_word(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		ccr_68000_long_move_ae_normal(src);
		m68k_areg(regs, dstreg) -= 4;
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 24 (4/2) */
/* 4 0,0   */

/* MOVE.L (xxx).L,(An)+ */
void REGPARAM2 op_20f9_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 28; 
	uaecptr srca;
	srca = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	srca |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	if (srca & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	m68k_areg(regs, dstreg) += 4;
	ipl_fetch_now();
	if (dsta & 1) {
		m68k_incpci(8);
		m68k_areg(regs, dstreg) -= 4;
		ccr_68000_long_move_ae_LZN(src);
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return;
	}
	x_put_word(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		ccr_68000_long_move_ae_LZN(src);
		m68k_areg(regs, dstreg) -= 4;
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	x_put_word(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		ccr_68000_long_move_ae_normal(src);
		m68k_areg(regs, dstreg) -= 4;
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return;
	}
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 28 (5/2) */
/* 6 0,0   */

/* MOVE.L (d16,PC),(An)+ */
void REGPARAM2 op_20fa_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 24; 
	uaecptr srca;
	srca = m68k_getpci() + 2;
	srca += (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 2);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return;
	}
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 2);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	m68k_areg(regs, dstreg) += 4;
	ipl_fetch_now();
	if (dsta & 1) {
		m68k_incpci(6);
		m68k_areg(regs, dstreg) -= 4;
		ccr_68000_long_move_ae_LZN(src);
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return;
	}
	x_put_word(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		ccr_68000_long_move_ae_LZN(src);
		m68k_areg(regs, dstreg) -= 4;
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	x_put_word(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		ccr_68000_long_move_ae_normal(src);
		m68k_areg(regs, dstreg) -= 4;
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 24 (4/2) */
/* 4 0,0   */

/* MOVE.L (d8,PC,Xn),(An)+ */
void REGPARAM2 op_20fb_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 26; 
	uaecptr srca;
	uaecptr tmppc = m68k_getpci() + 2;
	do_cycles_ce000_internal(2);
	srca = get_disp_ea_000(tmppc, get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 2);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return;
	}
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 2);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	m68k_areg(regs, dstreg) += 4;
	ipl_fetch_now();
	if (dsta & 1) {
		m68k_incpci(6);
		m68k_areg(regs, dstreg) -= 4;
		ccr_68000_long_move_ae_LZN(src);
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return;
	}
	x_put_word(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		ccr_68000_long_move_ae_LZN(src);
		m68k_areg(regs, dstreg) -= 4;
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	x_put_word(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		ccr_68000_long_move_ae_normal(src);
		m68k_areg(regs, dstreg) -= 4;
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 26 (4/2) */
/* 4 4,0   */

/* MOVE.L #<data>.L,(An)+ */
void REGPARAM2 op_20fc_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 20; 
	uae_s32 src;
	src = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	src |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	m68k_areg(regs, dstreg) += 4;
	ipl_fetch_now();
	if (dsta & 1) {
		m68k_incpci(8);
		m68k_areg(regs, dstreg) -= 4;
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return;
	}
	x_put_word(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		m68k_areg(regs, dstreg) -= 4;
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	x_put_word(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		ccr_68000_long_move_ae_LZN(src);
		m68k_areg(regs, dstreg) -= 4;
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return;
	}
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 20 (3/2) */
/* 6 0,0   */

/* MOVE.L Dn,-(An) */
void REGPARAM2 op_2100_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 12; 
	ipl_fetch_next_pre();
	uae_s32 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - 4;
	m68k_areg(regs, dstreg) = dsta;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		m68k_areg(regs, dstreg) += 4;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(4);
		do_cycles_ce000_internal(2);
		m68k_areg(regs, dstreg) += 4;
		regs.ir = opcode;
		ccr_68000_long_move_ae_normal(src);
		dsta += 2;
		exception3_write_access(opcode, dsta, 2, src, 1);
		return;
	}
	x_put_word(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		ccr_68000_long_move_ae_normal(src);
		m68k_areg(regs, dstreg) += 4;
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	x_put_word(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		ccr_68000_long_move_ae_normal(src);
		m68k_areg(regs, dstreg) += 4;
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 12 (1/2) */
/* 2 0,0   */

/* MOVE.L An,-(An) */
void REGPARAM2 op_2108_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 12; 
	ipl_fetch_next_pre();
	uae_s32 src = m68k_areg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - 4;
	m68k_areg(regs, dstreg) = dsta;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		m68k_areg(regs, dstreg) += 4;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(4);
		do_cycles_ce000_internal(2);
		m68k_areg(regs, dstreg) += 4;
		regs.ir = opcode;
		ccr_68000_long_move_ae_normal(src);
		dsta += 2;
		exception3_write_access(opcode, dsta, 2, src, 1);
		return;
	}
	x_put_word(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		ccr_68000_long_move_ae_normal(src);
		m68k_areg(regs, dstreg) += 4;
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	x_put_word(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		ccr_68000_long_move_ae_normal(src);
		m68k_areg(regs, dstreg) += 4;
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 12 (1/2) */
/* 2 0,0   */

/* MOVE.L (An),-(An) */
void REGPARAM2 op_2110_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - 4;
	m68k_areg(regs, dstreg) = dsta;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		m68k_areg(regs, dstreg) += 4;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(4);
		do_cycles_ce000_internal(2);
		m68k_areg(regs, dstreg) += 4;
		regs.ir = opcode;
		ccr_68000_long_move_ae_normal(src);
		dsta += 2;
		exception3_write_access(opcode, dsta, 2, src, 1);
		return;
	}
	x_put_word(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		ccr_68000_long_move_ae_normal(src);
		m68k_areg(regs, dstreg) += 4;
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	x_put_word(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		ccr_68000_long_move_ae_normal(src);
		m68k_areg(regs, dstreg) += 4;
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 20 (3/2) */
/* 2 0,0   */

/* MOVE.L (An)+,-(An) */
void REGPARAM2 op_2118_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	m68k_areg(regs, srcreg) += 4;
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - 4;
	m68k_areg(regs, dstreg) = dsta;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		m68k_areg(regs, dstreg) += 4;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(4);
		do_cycles_ce000_internal(2);
		m68k_areg(regs, dstreg) += 4;
		regs.ir = opcode;
		ccr_68000_long_move_ae_normal(src);
		dsta += 2;
		exception3_write_access(opcode, dsta, 2, src, 1);
		return;
	}
	x_put_word(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		ccr_68000_long_move_ae_normal(src);
		m68k_areg(regs, dstreg) += 4;
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	x_put_word(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		ccr_68000_long_move_ae_normal(src);
		m68k_areg(regs, dstreg) += 4;
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 20 (3/2) */
/* 2 0,0   */

/* MOVE.L -(An),-(An) */
void REGPARAM2 op_2120_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 22; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - 4;
	do_cycles_ce000_internal(2);
	if (srca & 1) {
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	m68k_areg(regs, srcreg) = srca;
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - 4;
	m68k_areg(regs, dstreg) = dsta;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		m68k_areg(regs, dstreg) += 4;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(4);
		do_cycles_ce000_internal(2);
		m68k_areg(regs, dstreg) += 4;
		regs.ir = opcode;
		ccr_68000_long_move_ae_normal(src);
		dsta += 2;
		exception3_write_access(opcode, dsta, 2, src, 1);
		return;
	}
	x_put_word(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		ccr_68000_long_move_ae_normal(src);
		m68k_areg(regs, dstreg) += 4;
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	x_put_word(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		ccr_68000_long_move_ae_normal(src);
		m68k_areg(regs, dstreg) += 4;
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 22 (3/2) */
/* 2 0,0   */

/* MOVE.L (d16,An),-(An) */
void REGPARAM2 op_2128_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 24; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - 4;
	m68k_areg(regs, dstreg) = dsta;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		m68k_areg(regs, dstreg) += 4;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(6);
		do_cycles_ce000_internal(2);
		m68k_areg(regs, dstreg) += 4;
		regs.ir = opcode;
		ccr_68000_long_move_ae_normal(src);
		dsta += 2;
		exception3_write_access(opcode, dsta, 2, src, 1);
		return;
	}
	x_put_word(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		ccr_68000_long_move_ae_normal(src);
		m68k_areg(regs, dstreg) += 4;
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	x_put_word(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		ccr_68000_long_move_ae_normal(src);
		m68k_areg(regs, dstreg) += 4;
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 24 (4/2) */
/* 4 0,0   */

/* MOVE.L (d8,An,Xn),-(An) */
void REGPARAM2 op_2130_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 26; 
	uaecptr srca;
	do_cycles_ce000_internal(2);
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - 4;
	m68k_areg(regs, dstreg) = dsta;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		m68k_areg(regs, dstreg) += 4;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(6);
		do_cycles_ce000_internal(2);
		m68k_areg(regs, dstreg) += 4;
		regs.ir = opcode;
		ccr_68000_long_move_ae_normal(src);
		dsta += 2;
		exception3_write_access(opcode, dsta, 2, src, 1);
		return;
	}
	x_put_word(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		ccr_68000_long_move_ae_normal(src);
		m68k_areg(regs, dstreg) += 4;
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	x_put_word(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		ccr_68000_long_move_ae_normal(src);
		m68k_areg(regs, dstreg) += 4;
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 26 (4/2) */
/* 4 4,0   */

/* MOVE.L (xxx).W,-(An) */
void REGPARAM2 op_2138_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 24; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	if (srca & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - 4;
	m68k_areg(regs, dstreg) = dsta;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		m68k_areg(regs, dstreg) += 4;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(6);
		do_cycles_ce000_internal(2);
		m68k_areg(regs, dstreg) += 4;
		regs.ir = opcode;
		ccr_68000_long_move_ae_normal(src);
		dsta += 2;
		exception3_write_access(opcode, dsta, 2, src, 1);
		return;
	}
	x_put_word(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		ccr_68000_long_move_ae_normal(src);
		m68k_areg(regs, dstreg) += 4;
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	x_put_word(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		ccr_68000_long_move_ae_normal(src);
		m68k_areg(regs, dstreg) += 4;
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 24 (4/2) */
/* 4 0,0   */

/* MOVE.L (xxx).L,-(An) */
void REGPARAM2 op_2139_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 28; 
	uaecptr srca;
	srca = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	srca |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	if (srca & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - 4;
	m68k_areg(regs, dstreg) = dsta;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		m68k_areg(regs, dstreg) += 4;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(8);
		do_cycles_ce000_internal(2);
		m68k_areg(regs, dstreg) += 4;
		regs.ir = opcode;
		ccr_68000_long_move_ae_normal(src);
		dsta += 2;
		exception3_write_access(opcode, dsta, 2, src, 1);
		return;
	}
	x_put_word(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		ccr_68000_long_move_ae_normal(src);
		m68k_areg(regs, dstreg) += 4;
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	x_put_word(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		ccr_68000_long_move_ae_normal(src);
		m68k_areg(regs, dstreg) += 4;
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 28 (5/2) */
/* 6 0,0   */

/* MOVE.L (d16,PC),-(An) */
void REGPARAM2 op_213a_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 24; 
	uaecptr srca;
	srca = m68k_getpci() + 2;
	srca += (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 2);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return;
	}
	ipl_fetch_now();
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 2);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - 4;
	m68k_areg(regs, dstreg) = dsta;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		m68k_areg(regs, dstreg) += 4;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(6);
		do_cycles_ce000_internal(2);
		m68k_areg(regs, dstreg) += 4;
		regs.ir = opcode;
		ccr_68000_long_move_ae_normal(src);
		dsta += 2;
		exception3_write_access(opcode, dsta, 2, src, 1);
		return;
	}
	x_put_word(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		ccr_68000_long_move_ae_normal(src);
		m68k_areg(regs, dstreg) += 4;
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	x_put_word(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		ccr_68000_long_move_ae_normal(src);
		m68k_areg(regs, dstreg) += 4;
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 24 (4/2) */
/* 4 0,0   */

/* MOVE.L (d8,PC,Xn),-(An) */
void REGPARAM2 op_213b_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 26; 
	uaecptr srca;
	uaecptr tmppc = m68k_getpci() + 2;
	do_cycles_ce000_internal(2);
	srca = get_disp_ea_000(tmppc, get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 2);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return;
	}
	ipl_fetch_now();
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 2);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - 4;
	m68k_areg(regs, dstreg) = dsta;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		m68k_areg(regs, dstreg) += 4;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(6);
		do_cycles_ce000_internal(2);
		m68k_areg(regs, dstreg) += 4;
		regs.ir = opcode;
		ccr_68000_long_move_ae_normal(src);
		dsta += 2;
		exception3_write_access(opcode, dsta, 2, src, 1);
		return;
	}
	x_put_word(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		ccr_68000_long_move_ae_normal(src);
		m68k_areg(regs, dstreg) += 4;
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	x_put_word(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		ccr_68000_long_move_ae_normal(src);
		m68k_areg(regs, dstreg) += 4;
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 26 (4/2) */
/* 4 4,0   */

/* MOVE.L #<data>.L,-(An) */
void REGPARAM2 op_213c_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 20; 
	uae_s32 src;
	src = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	ipl_fetch_now();
	src |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - 4;
	m68k_areg(regs, dstreg) = dsta;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		m68k_areg(regs, dstreg) += 4;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(8);
		do_cycles_ce000_internal(2);
		m68k_areg(regs, dstreg) += 4;
		regs.ir = opcode;
		ccr_68000_long_move_ae_normal(src);
		dsta += 2;
		exception3_write_access(opcode, dsta, 2, src, 1);
		return;
	}
	x_put_word(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		ccr_68000_long_move_ae_normal(src);
		m68k_areg(regs, dstreg) += 4;
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	x_put_word(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		ccr_68000_long_move_ae_normal(src);
		m68k_areg(regs, dstreg) += 4;
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 20 (3/2) */
/* 6 0,0   */

/* MOVE.L Dn,(d16,An) */
void REGPARAM2 op_2140_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 16; 
	uae_s32 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(4);
		ccr_68000_long_move_ae_HNZ(src);
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return;
	}
	ipl_fetch_now();
	x_put_word(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		SET_NFLG(src < 0);
		if((src & 0xffff0000)) SET_ZFLG(0);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	x_put_word(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		ccr_68000_long_move_ae_LZN(src);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 16 (2/2) */
/* 4 0,0   */

/* MOVE.L An,(d16,An) */
void REGPARAM2 op_2148_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 16; 
	uae_s32 src = m68k_areg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(4);
		ccr_68000_long_move_ae_HNZ(src);
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return;
	}
	ipl_fetch_now();
	x_put_word(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		SET_NFLG(src < 0);
		if((src & 0xffff0000)) SET_ZFLG(0);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	x_put_word(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		ccr_68000_long_move_ae_LZN(src);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 16 (2/2) */
/* 4 0,0   */

/* MOVE.L (An),(d16,An) */
void REGPARAM2 op_2150_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 24; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch(opcode, 4, 0);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(4);
		ccr_68000_long_move_ae_normal(src);
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return;
	}
	x_put_word(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	ipl_fetch_now();
	x_put_word(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 24 (4/2) */
/* 4 0,0   */

/* MOVE.L (An)+,(d16,An) */
void REGPARAM2 op_2158_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 24; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	m68k_areg(regs, srcreg) += 4;
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch(opcode, 4, 0);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(4);
		ccr_68000_long_move_ae_normal(src);
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return;
	}
	x_put_word(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	ipl_fetch_now();
	x_put_word(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 24 (4/2) */
/* 4 0,0   */

/* MOVE.L -(An),(d16,An) */
void REGPARAM2 op_2160_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 26; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - 4;
	do_cycles_ce000_internal(2);
	if (srca & 1) {
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	m68k_areg(regs, srcreg) = srca;
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch(opcode, 4, 0);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(4);
		ccr_68000_long_move_ae_normal(src);
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return;
	}
	x_put_word(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	ipl_fetch_now();
	x_put_word(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 26 (4/2) */
/* 4 0,0   */

/* MOVE.L (d16,An),(d16,An) */
void REGPARAM2 op_2168_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 28; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch(opcode, 6, 0);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(6);
		ccr_68000_long_move_ae_normal(src);
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return;
	}
	x_put_word(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	ipl_fetch_now();
	x_put_word(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return;
	}
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 28 (5/2) */
/* 6 0,0   */

/* MOVE.L (d8,An,Xn),(d16,An) */
void REGPARAM2 op_2170_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 30; 
	uaecptr srca;
	do_cycles_ce000_internal(2);
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch(opcode, 6, 0);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(6);
		ccr_68000_long_move_ae_normal(src);
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return;
	}
	x_put_word(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	ipl_fetch_now();
	x_put_word(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return;
	}
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 30 (5/2) */
/* 6 6,0   */

/* MOVE.L (xxx).W,(d16,An) */
void REGPARAM2 op_2178_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 28; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	if (srca & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch(opcode, 6, 0);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(6);
		ccr_68000_long_move_ae_normal(src);
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return;
	}
	x_put_word(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	ipl_fetch_now();
	x_put_word(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return;
	}
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 28 (5/2) */
/* 6 0,0   */

/* MOVE.L (xxx).L,(d16,An) */
void REGPARAM2 op_2179_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 32; 
	uaecptr srca;
	srca = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	srca |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	if (srca & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch(opcode, 8, 0);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(8);
		ccr_68000_long_move_ae_normal(src);
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return;
	}
	x_put_word(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	ipl_fetch_now();
	x_put_word(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return;
	}
	m68k_incpci(8);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 32 (6/2) */
/* 8 0,0   */

/* MOVE.L (d16,PC),(d16,An) */
void REGPARAM2 op_217a_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 28; 
	uaecptr srca;
	srca = m68k_getpci() + 2;
	srca += (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 2);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return;
	}
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 2);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch(opcode, 6, 0);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(6);
		ccr_68000_long_move_ae_normal(src);
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return;
	}
	x_put_word(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	ipl_fetch_now();
	x_put_word(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return;
	}
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 28 (5/2) */
/* 6 0,0   */

/* MOVE.L (d8,PC,Xn),(d16,An) */
void REGPARAM2 op_217b_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 30; 
	uaecptr srca;
	uaecptr tmppc = m68k_getpci() + 2;
	do_cycles_ce000_internal(2);
	srca = get_disp_ea_000(tmppc, get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 2);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return;
	}
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 2);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch(opcode, 6, 0);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(6);
		ccr_68000_long_move_ae_normal(src);
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return;
	}
	x_put_word(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	ipl_fetch_now();
	x_put_word(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return;
	}
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 30 (5/2) */
/* 6 6,0   */

/* MOVE.L #<data>.L,(d16,An) */
void REGPARAM2 op_217c_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 24; 
	uae_s32 src;
	src = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	src |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 8, 0);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(8);
		ccr_68000_long_move_ae_HNZ(src);
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return;
	}
	ipl_fetch_now();
	x_put_word(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		ccr_68000_long_move_ae_HNZ(src);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	x_put_word(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		ccr_68000_long_move_ae_LZN(src);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return;
	}
	m68k_incpci(8);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 24 (4/2) */
/* 8 0,0   */

/* MOVE.L Dn,(d8,An,Xn) */
void REGPARAM2 op_2180_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 18; 
	uae_s32 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	do_cycles_ce000_internal(2);
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(4);
		ccr_68000_long_move_ae_HNZ(src);
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return;
	}
	ipl_fetch_now();
	x_put_word(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		SET_NFLG(src < 0);
		if((src & 0xffff0000)) SET_ZFLG(0);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	x_put_word(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		ccr_68000_long_move_ae_LZN(src);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 18 (2/2) */
/* 4 4,0   */

/* MOVE.L An,(d8,An,Xn) */
void REGPARAM2 op_2188_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 18; 
	uae_s32 src = m68k_areg(regs, srcreg);
	uaecptr dsta;
	do_cycles_ce000_internal(2);
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(4);
		ccr_68000_long_move_ae_HNZ(src);
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return;
	}
	ipl_fetch_now();
	x_put_word(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		SET_NFLG(src < 0);
		if((src & 0xffff0000)) SET_ZFLG(0);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	x_put_word(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		ccr_68000_long_move_ae_LZN(src);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 18 (2/2) */
/* 4 4,0   */

/* MOVE.L (An),(d8,An,Xn) */
void REGPARAM2 op_2190_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 26; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	uaecptr dsta;
	do_cycles_ce000_internal(2);
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch(opcode, 4, 0);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(4);
		ccr_68000_long_move_ae_normal(src);
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return;
	}
	x_put_word(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	ipl_fetch_now();
	x_put_word(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 26 (4/2) */
/* 4 4,0   */

/* MOVE.L (An)+,(d8,An,Xn) */
void REGPARAM2 op_2198_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 26; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	m68k_areg(regs, srcreg) += 4;
	uaecptr dsta;
	do_cycles_ce000_internal(2);
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch(opcode, 4, 0);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(4);
		ccr_68000_long_move_ae_normal(src);
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return;
	}
	x_put_word(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	ipl_fetch_now();
	x_put_word(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 26 (4/2) */
/* 4 4,0   */

/* MOVE.L -(An),(d8,An,Xn) */
void REGPARAM2 op_21a0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 28; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - 4;
	do_cycles_ce000_internal(2);
	if (srca & 1) {
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	m68k_areg(regs, srcreg) = srca;
	uaecptr dsta;
	do_cycles_ce000_internal(2);
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch(opcode, 4, 0);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(4);
		ccr_68000_long_move_ae_normal(src);
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return;
	}
	x_put_word(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	ipl_fetch_now();
	x_put_word(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 28 (4/2) */
/* 4 4,0   */

/* MOVE.L (d16,An),(d8,An,Xn) */
void REGPARAM2 op_21a8_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 30; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	uaecptr dsta;
	do_cycles_ce000_internal(2);
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_ce000_prefetch(6));
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch(opcode, 6, 0);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(6);
		ccr_68000_long_move_ae_normal(src);
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return;
	}
	x_put_word(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	ipl_fetch_now();
	x_put_word(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return;
	}
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 30 (5/2) */
/* 6 4,0   */

/* MOVE.L (d8,An,Xn),(d8,An,Xn) */
void REGPARAM2 op_21b0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 32; 
	uaecptr srca;
	do_cycles_ce000_internal(2);
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	uaecptr dsta;
	do_cycles_ce000_internal(2);
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_ce000_prefetch(6));
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch(opcode, 6, 0);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(6);
		ccr_68000_long_move_ae_normal(src);
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return;
	}
	x_put_word(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	ipl_fetch_now();
	x_put_word(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return;
	}
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 32 (5/2) */
/* 6 6,4   */

/* MOVE.L (xxx).W,(d8,An,Xn) */
void REGPARAM2 op_21b8_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 30; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	if (srca & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	uaecptr dsta;
	do_cycles_ce000_internal(2);
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_ce000_prefetch(6));
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch(opcode, 6, 0);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(6);
		ccr_68000_long_move_ae_normal(src);
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return;
	}
	x_put_word(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	ipl_fetch_now();
	x_put_word(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return;
	}
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 30 (5/2) */
/* 6 4,0   */

/* MOVE.L (xxx).L,(d8,An,Xn) */
void REGPARAM2 op_21b9_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 34; 
	uaecptr srca;
	srca = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	srca |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	if (srca & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	uaecptr dsta;
	do_cycles_ce000_internal(2);
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_ce000_prefetch(8));
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch(opcode, 8, 0);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(8);
		ccr_68000_long_move_ae_normal(src);
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return;
	}
	x_put_word(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	ipl_fetch_now();
	x_put_word(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return;
	}
	m68k_incpci(8);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 34 (6/2) */
/* 8 4,0   */

/* MOVE.L (d16,PC),(d8,An,Xn) */
void REGPARAM2 op_21ba_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 30; 
	uaecptr srca;
	srca = m68k_getpci() + 2;
	srca += (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 2);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return;
	}
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 2);
		return;
	}
	uaecptr dsta;
	do_cycles_ce000_internal(2);
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_ce000_prefetch(6));
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch(opcode, 6, 0);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(6);
		ccr_68000_long_move_ae_normal(src);
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return;
	}
	x_put_word(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	ipl_fetch_now();
	x_put_word(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return;
	}
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 30 (5/2) */
/* 6 4,0   */

/* MOVE.L (d8,PC,Xn),(d8,An,Xn) */
void REGPARAM2 op_21bb_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 32; 
	uaecptr srca;
	uaecptr tmppc = m68k_getpci() + 2;
	do_cycles_ce000_internal(2);
	srca = get_disp_ea_000(tmppc, get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 2);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return;
	}
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 2);
		return;
	}
	uaecptr dsta;
	do_cycles_ce000_internal(2);
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_ce000_prefetch(6));
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch(opcode, 6, 0);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(6);
		ccr_68000_long_move_ae_normal(src);
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return;
	}
	x_put_word(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	ipl_fetch_now();
	x_put_word(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return;
	}
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 32 (5/2) */
/* 6 6,4   */

/* MOVE.L #<data>.L,(d8,An,Xn) */
void REGPARAM2 op_21bc_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 26; 
	uae_s32 src;
	src = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	src |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	uaecptr dsta;
	do_cycles_ce000_internal(2);
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_ce000_prefetch(8));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 8, 0);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(8);
		ccr_68000_long_move_ae_HNZ(src);
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return;
	}
	ipl_fetch_now();
	x_put_word(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		ccr_68000_long_move_ae_HNZ(src);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	x_put_word(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		ccr_68000_long_move_ae_LZN(src);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return;
	}
	m68k_incpci(8);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 26 (4/2) */
/* 8 4,0   */

/* MOVE.L Dn,(xxx).W */
void REGPARAM2 op_21c0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 30;
	CurrentInstrCycles = 16; 
	uae_s32 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch(opcode, 4, 0);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(4);
		ccr_68000_long_move_ae_normal(src);
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return;
	}
	x_put_word(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	ipl_fetch_now();
	x_put_word(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 16 (2/2) */
/* 4 0,0   */

/* MOVE.L An,(xxx).W */
void REGPARAM2 op_21c8_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 30;
	CurrentInstrCycles = 16; 
	uae_s32 src = m68k_areg(regs, srcreg);
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch(opcode, 4, 0);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(4);
		ccr_68000_long_move_ae_normal(src);
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return;
	}
	x_put_word(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	ipl_fetch_now();
	x_put_word(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 16 (2/2) */
/* 4 0,0   */

/* MOVE.L (An),(xxx).W */
void REGPARAM2 op_21d0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 30;
	CurrentInstrCycles = 24; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch(opcode, 4, 0);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(4);
		ccr_68000_long_move_ae_normal(src);
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return;
	}
	x_put_word(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		ccr_68000_long_move_ae_LZN(src);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	ipl_fetch_now();
	x_put_word(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 24 (4/2) */
/* 4 0,0   */

/* MOVE.L (An)+,(xxx).W */
void REGPARAM2 op_21d8_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 30;
	CurrentInstrCycles = 24; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	m68k_areg(regs, srcreg) += 4;
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch(opcode, 4, 0);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(4);
		ccr_68000_long_move_ae_normal(src);
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return;
	}
	x_put_word(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		ccr_68000_long_move_ae_LZN(src);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	ipl_fetch_now();
	x_put_word(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 24 (4/2) */
/* 4 0,0   */

/* MOVE.L -(An),(xxx).W */
void REGPARAM2 op_21e0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 30;
	CurrentInstrCycles = 26; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - 4;
	do_cycles_ce000_internal(2);
	if (srca & 1) {
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	m68k_areg(regs, srcreg) = srca;
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch(opcode, 4, 0);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(4);
		ccr_68000_long_move_ae_normal(src);
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return;
	}
	x_put_word(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		ccr_68000_long_move_ae_LZN(src);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	ipl_fetch_now();
	x_put_word(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 26 (4/2) */
/* 4 0,0   */

/* MOVE.L (d16,An),(xxx).W */
void REGPARAM2 op_21e8_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 30;
	CurrentInstrCycles = 28; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch(opcode, 6, 0);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(6);
		ccr_68000_long_move_ae_normal(src);
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return;
	}
	x_put_word(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		ccr_68000_long_move_ae_LZN(src);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	ipl_fetch_now();
	x_put_word(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return;
	}
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 28 (5/2) */
/* 6 0,0   */

/* MOVE.L (d8,An,Xn),(xxx).W */
void REGPARAM2 op_21f0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 30;
	CurrentInstrCycles = 30; 
	uaecptr srca;
	do_cycles_ce000_internal(2);
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch(opcode, 6, 0);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(6);
		ccr_68000_long_move_ae_normal(src);
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return;
	}
	x_put_word(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		ccr_68000_long_move_ae_LZN(src);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	ipl_fetch_now();
	x_put_word(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return;
	}
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 30 (5/2) */
/* 6 6,0   */

/* MOVE.L (xxx).W,(xxx).W */
void REGPARAM2 op_21f8_14_ff(uae_u32 opcode)
{
	OpcodeFamily = 30;
	CurrentInstrCycles = 28; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	if (srca & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch(opcode, 6, 0);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(6);
		ccr_68000_long_move_ae_normal(src);
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return;
	}
	x_put_word(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		ccr_68000_long_move_ae_LZN(src);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	ipl_fetch_now();
	x_put_word(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return;
	}
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 28 (5/2) */
/* 6 0,0   */

/* MOVE.L (xxx).L,(xxx).W */
void REGPARAM2 op_21f9_14_ff(uae_u32 opcode)
{
	OpcodeFamily = 30;
	CurrentInstrCycles = 32; 
	uaecptr srca;
	srca = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	srca |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	if (srca & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch(opcode, 8, 0);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(8);
		ccr_68000_long_move_ae_normal(src);
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return;
	}
	x_put_word(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		ccr_68000_long_move_ae_LZN(src);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	ipl_fetch_now();
	x_put_word(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return;
	}
	m68k_incpci(8);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 32 (6/2) */
/* 8 0,0   */

/* MOVE.L (d16,PC),(xxx).W */
void REGPARAM2 op_21fa_14_ff(uae_u32 opcode)
{
	OpcodeFamily = 30;
	CurrentInstrCycles = 28; 
	uaecptr srca;
	srca = m68k_getpci() + 2;
	srca += (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 2);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return;
	}
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 2);
		return;
	}
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch(opcode, 6, 0);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(6);
		ccr_68000_long_move_ae_normal(src);
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return;
	}
	x_put_word(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		ccr_68000_long_move_ae_LZN(src);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	ipl_fetch_now();
	x_put_word(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return;
	}
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 28 (5/2) */
/* 6 0,0   */

/* MOVE.L (d8,PC,Xn),(xxx).W */
void REGPARAM2 op_21fb_14_ff(uae_u32 opcode)
{
	OpcodeFamily = 30;
	CurrentInstrCycles = 30; 
	uaecptr srca;
	uaecptr tmppc = m68k_getpci() + 2;
	do_cycles_ce000_internal(2);
	srca = get_disp_ea_000(tmppc, get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 2);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return;
	}
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 2);
		return;
	}
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch(opcode, 6, 0);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(6);
		ccr_68000_long_move_ae_normal(src);
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return;
	}
	x_put_word(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		ccr_68000_long_move_ae_LZN(src);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	ipl_fetch_now();
	x_put_word(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return;
	}
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 30 (5/2) */
/* 6 6,0   */

/* MOVE.L #<data>.L,(xxx).W */
void REGPARAM2 op_21fc_14_ff(uae_u32 opcode)
{
	OpcodeFamily = 30;
	CurrentInstrCycles = 24; 
	uae_s32 src;
	src = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	src |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch(opcode, 8, 0);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(8);
		ccr_68000_long_move_ae_normal(src);
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return;
	}
	x_put_word(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	ipl_fetch_now();
	x_put_word(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return;
	}
	m68k_incpci(8);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 24 (4/2) */
/* 8 0,0   */

/* MOVE.L Dn,(xxx).L */
void REGPARAM2 op_23c0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 30;
	CurrentInstrCycles = 20; 
	uae_s32 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		// nothing;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	dsta |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(6);
		ccr_68000_long_move_ae_normal(src);
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return;
	}
	x_put_word(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	x_put_word(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return;
	}
	ipl_fetch_next();
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 20 (3/2) */
/* 6 0,0   */

/* MOVE.L An,(xxx).L */
void REGPARAM2 op_23c8_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 30;
	CurrentInstrCycles = 20; 
	uae_s32 src = m68k_areg(regs, srcreg);
	uaecptr dsta;
	dsta = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		// nothing;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	dsta |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(6);
		ccr_68000_long_move_ae_normal(src);
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return;
	}
	x_put_word(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	x_put_word(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return;
	}
	ipl_fetch_next();
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 20 (3/2) */
/* 6 0,0   */

/* MOVE.L (An),(xxx).L */
void REGPARAM2 op_23d0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 30;
	CurrentInstrCycles = 28; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	uaecptr dsta;
	dsta = get_word_ce000_prefetch(4) << 16;
	dsta |= regs.irc;
	if(hardware_bus_error) {
		int pcoffset = 0;
		// nothing;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(4);
		ccr_68000_long_move_ae_LZN(src);
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return;
	}
	x_put_word(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		ccr_68000_long_move_ae_LZN(src);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	x_put_word(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return;
	}
	ipl_fetch_now();
	m68k_incpci(6);
	get_word_ce000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, 0);
		return;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	if(regs.t1) opcode |= 0x10000;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 28 (5/2) */
/* 6 0,0   */

/* MOVE.L (An)+,(xxx).L */
void REGPARAM2 op_23d8_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 30;
	CurrentInstrCycles = 28; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	m68k_areg(regs, srcreg) += 4;
	uaecptr dsta;
	dsta = get_word_ce000_prefetch(4) << 16;
	dsta |= regs.irc;
	if(hardware_bus_error) {
		int pcoffset = 0;
		// nothing;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(4);
		ccr_68000_long_move_ae_LZN(src);
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return;
	}
	x_put_word(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		ccr_68000_long_move_ae_LZN(src);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	x_put_word(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return;
	}
	ipl_fetch_now();
	m68k_incpci(6);
	get_word_ce000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, 0);
		return;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	if(regs.t1) opcode |= 0x10000;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 28 (5/2) */
/* 6 0,0   */

/* MOVE.L -(An),(xxx).L */
void REGPARAM2 op_23e0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 30;
	CurrentInstrCycles = 30; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - 4;
	do_cycles_ce000_internal(2);
	if (srca & 1) {
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	m68k_areg(regs, srcreg) = srca;
	uaecptr dsta;
	dsta = get_word_ce000_prefetch(4) << 16;
	dsta |= regs.irc;
	if(hardware_bus_error) {
		int pcoffset = 0;
		// nothing;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(4);
		ccr_68000_long_move_ae_LZN(src);
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return;
	}
	x_put_word(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		ccr_68000_long_move_ae_LZN(src);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	x_put_word(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return;
	}
	ipl_fetch_now();
	m68k_incpci(6);
	get_word_ce000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, 0);
		return;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	if(regs.t1) opcode |= 0x10000;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 30 (5/2) */
/* 6 0,0   */

/* MOVE.L (d16,An),(xxx).L */
void REGPARAM2 op_23e8_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 30;
	CurrentInstrCycles = 32; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	uaecptr dsta;
	dsta = get_word_ce000_prefetch(6) << 16;
	dsta |= regs.irc;
	if(hardware_bus_error) {
		int pcoffset = 0;
		// nothing;
		exception2_fetch(opcode, 6, 0);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(6);
		ccr_68000_long_move_ae_LZN(src);
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return;
	}
	x_put_word(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		ccr_68000_long_move_ae_LZN(src);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	x_put_word(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return;
	}
	ipl_fetch_now();
	m68k_incpci(8);
	get_word_ce000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, 0);
		return;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	if(regs.t1) opcode |= 0x10000;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 32 (6/2) */
/* 8 0,0   */

/* MOVE.L (d8,An,Xn),(xxx).L */
void REGPARAM2 op_23f0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 30;
	CurrentInstrCycles = 34; 
	uaecptr srca;
	do_cycles_ce000_internal(2);
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	uaecptr dsta;
	dsta = get_word_ce000_prefetch(6) << 16;
	dsta |= regs.irc;
	if(hardware_bus_error) {
		int pcoffset = 0;
		// nothing;
		exception2_fetch(opcode, 6, 0);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(6);
		ccr_68000_long_move_ae_LZN(src);
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return;
	}
	x_put_word(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		ccr_68000_long_move_ae_LZN(src);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	x_put_word(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return;
	}
	ipl_fetch_now();
	m68k_incpci(8);
	get_word_ce000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, 0);
		return;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	if(regs.t1) opcode |= 0x10000;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 34 (6/2) */
/* 8 8,0   */

/* MOVE.L (xxx).W,(xxx).L */
void REGPARAM2 op_23f8_14_ff(uae_u32 opcode)
{
	OpcodeFamily = 30;
	CurrentInstrCycles = 32; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	if (srca & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	uaecptr dsta;
	dsta = get_word_ce000_prefetch(6) << 16;
	dsta |= regs.irc;
	if(hardware_bus_error) {
		int pcoffset = 0;
		// nothing;
		exception2_fetch(opcode, 6, 0);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(6);
		ccr_68000_long_move_ae_LZN(src);
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return;
	}
	x_put_word(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		ccr_68000_long_move_ae_LZN(src);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	x_put_word(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return;
	}
	ipl_fetch_now();
	m68k_incpci(8);
	get_word_ce000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, 0);
		return;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	if(regs.t1) opcode |= 0x10000;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 32 (6/2) */
/* 8 0,0   */

/* MOVE.L (xxx).L,(xxx).L */
void REGPARAM2 op_23f9_14_ff(uae_u32 opcode)
{
	OpcodeFamily = 30;
	CurrentInstrCycles = 36; 
	uaecptr srca;
	srca = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	srca |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	if (srca & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	uaecptr dsta;
	dsta = get_word_ce000_prefetch(8) << 16;
	dsta |= regs.irc;
	if(hardware_bus_error) {
		int pcoffset = 0;
		// nothing;
		exception2_fetch(opcode, 8, 0);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(8);
		ccr_68000_long_move_ae_LZN(src);
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return;
	}
	x_put_word(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		ccr_68000_long_move_ae_LZN(src);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	x_put_word(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return;
	}
	ipl_fetch_now();
	m68k_incpci(10);
	get_word_ce000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, 0);
		return;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	if(regs.t1) opcode |= 0x10000;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 36 (7/2) */
/* 10 0,0   */

/* MOVE.L (d16,PC),(xxx).L */
void REGPARAM2 op_23fa_14_ff(uae_u32 opcode)
{
	OpcodeFamily = 30;
	CurrentInstrCycles = 32; 
	uaecptr srca;
	srca = m68k_getpci() + 2;
	srca += (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 2);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return;
	}
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 2);
		return;
	}
	uaecptr dsta;
	dsta = get_word_ce000_prefetch(6) << 16;
	dsta |= regs.irc;
	if(hardware_bus_error) {
		int pcoffset = 0;
		// nothing;
		exception2_fetch(opcode, 6, 0);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(6);
		ccr_68000_long_move_ae_LZN(src);
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return;
	}
	x_put_word(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		ccr_68000_long_move_ae_LZN(src);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	x_put_word(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return;
	}
	ipl_fetch_now();
	m68k_incpci(8);
	get_word_ce000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, 0);
		return;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	if(regs.t1) opcode |= 0x10000;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 32 (6/2) */
/* 8 0,0   */

/* MOVE.L (d8,PC,Xn),(xxx).L */
void REGPARAM2 op_23fb_14_ff(uae_u32 opcode)
{
	OpcodeFamily = 30;
	CurrentInstrCycles = 34; 
	uaecptr srca;
	uaecptr tmppc = m68k_getpci() + 2;
	do_cycles_ce000_internal(2);
	srca = get_disp_ea_000(tmppc, get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 2);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return;
	}
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 2);
		return;
	}
	uaecptr dsta;
	dsta = get_word_ce000_prefetch(6) << 16;
	dsta |= regs.irc;
	if(hardware_bus_error) {
		int pcoffset = 0;
		// nothing;
		exception2_fetch(opcode, 6, 0);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(6);
		ccr_68000_long_move_ae_LZN(src);
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return;
	}
	x_put_word(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		ccr_68000_long_move_ae_LZN(src);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	x_put_word(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return;
	}
	ipl_fetch_now();
	m68k_incpci(8);
	get_word_ce000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, 0);
		return;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	if(regs.t1) opcode |= 0x10000;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 34 (6/2) */
/* 8 8,0   */

/* MOVE.L #<data>.L,(xxx).L */
void REGPARAM2 op_23fc_14_ff(uae_u32 opcode)
{
	OpcodeFamily = 30;
	CurrentInstrCycles = 28; 
	uae_s32 src;
	src = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	src |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	uaecptr dsta;
	dsta = get_word_ce000_prefetch(8) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 8, -2);
		return;
	}
	dsta |= get_word_ce000_prefetch(10);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch(opcode, 10, pcoffset);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(10);
		ccr_68000_long_move_ae_normal(src);
		exception3_write_access(opcode, dsta, 2, src >> 16, 1);
		return;
	}
	x_put_word(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(10);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	x_put_word(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(10);
		ccr_68000_long_move_ae_normal(src);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return;
	}
	ipl_fetch_next();
	m68k_incpci(10);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 28 (5/2) */
/* 10 0,0   */

/* MOVE.W Dn,Dn */
void REGPARAM2 op_3000_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 4;  
	uae_s16 src = m68k_dreg(regs, srcreg);
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
	m68k_incpci(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 4 (1/0) */
/* 2 0,0   */

/* MOVE.W An,Dn */
void REGPARAM2 op_3008_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 4;  
	uae_s16 src = m68k_areg(regs, srcreg);
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
	m68k_incpci(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 4 (1/0) */
/* 2 0,0   */

/* MOVE.W (An),Dn */
void REGPARAM2 op_3010_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 8;  
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
	m68k_incpci(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 8 (2/0) */
/* 2 0,0   */

/* MOVE.W (An)+,Dn */
void REGPARAM2 op_3018_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 8;  
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) += 2 + 0;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	m68k_areg(regs, srcreg) += 2;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
	m68k_incpci(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 8 (2/0) */
/* 2 0,0   */

/* MOVE.W -(An),Dn */
void REGPARAM2 op_3020_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 10; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - 2;
	do_cycles_ce000_internal(2);
	if (srca & 1) {
		m68k_incpci(4);
		m68k_areg(regs, srcreg) = srca;
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	m68k_areg(regs, srcreg) = srca;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
	m68k_incpci(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 10 (2/0) */
/* 2 0,0   */

/* MOVE.W (d16,An),Dn */
void REGPARAM2 op_3028_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 12 (3/0) */
/* 4 0,0   */

/* MOVE.W (d8,An,Xn),Dn */
void REGPARAM2 op_3030_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	do_cycles_ce000_internal(2);
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 14 (3/0) */
/* 4 4,0   */

/* MOVE.W (xxx).W,Dn */
void REGPARAM2 op_3038_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	if (srca & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 12 (3/0) */
/* 4 0,0   */

/* MOVE.W (xxx).L,Dn */
void REGPARAM2 op_3039_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	srca |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	if (srca & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 16 (4/0) */
/* 6 0,0   */

/* MOVE.W (d16,PC),Dn */
void REGPARAM2 op_303a_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_getpci() + 2;
	srca += (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 2);
		return;
	}
	ipl_fetch_now();
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 12 (3/0) */
/* 4 0,0   */

/* MOVE.W (d8,PC,Xn),Dn */
void REGPARAM2 op_303b_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	uaecptr tmppc = m68k_getpci() + 2;
	do_cycles_ce000_internal(2);
	srca = get_disp_ea_000(tmppc, get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 2);
		return;
	}
	ipl_fetch_now();
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 14 (3/0) */
/* 4 4,0   */

/* MOVE.W #<data>.W,Dn */
void REGPARAM2 op_303c_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 8;  
	uae_s16 src = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 8 (2/0) */
/* 4 0,0   */

/* MOVEA.W Dn,An */
void REGPARAM2 op_3040_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 31;
	CurrentInstrCycles = 4;  
	uae_s16 src = m68k_dreg(regs, srcreg);
	src = (uae_s32)(uae_s16)src;
	m68k_areg(regs, dstreg) = (uae_s32)(uae_s16)(src);
	m68k_incpci(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 4 (1/0) */
/* 2 0,0   */

/* MOVEA.W An,An */
void REGPARAM2 op_3048_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 31;
	CurrentInstrCycles = 4;  
	uae_s16 src = m68k_areg(regs, srcreg);
	src = (uae_s32)(uae_s16)src;
	m68k_areg(regs, dstreg) = (uae_s32)(uae_s16)(src);
	m68k_incpci(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 4 (1/0) */
/* 2 0,0   */

/* MOVEA.W (An),An */
void REGPARAM2 op_3050_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 31;
	CurrentInstrCycles = 8;  
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	src = (uae_s32)(uae_s16)src;
	m68k_areg(regs, dstreg) = (uae_s32)(uae_s16)(src);
	m68k_incpci(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 8 (2/0) */
/* 2 0,0   */

/* MOVEA.W (An)+,An */
void REGPARAM2 op_3058_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 31;
	CurrentInstrCycles = 8;  
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) += 2 + 0;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	m68k_areg(regs, srcreg) += 2;
	src = (uae_s32)(uae_s16)src;
	m68k_areg(regs, dstreg) = (uae_s32)(uae_s16)(src);
	m68k_incpci(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 8 (2/0) */
/* 2 0,0   */

/* MOVEA.W -(An),An */
void REGPARAM2 op_3060_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 31;
	CurrentInstrCycles = 10; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - 2;
	do_cycles_ce000_internal(2);
	if (srca & 1) {
		m68k_incpci(4);
		m68k_areg(regs, srcreg) = srca;
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	m68k_areg(regs, srcreg) = srca;
	src = (uae_s32)(uae_s16)src;
	m68k_areg(regs, dstreg) = (uae_s32)(uae_s16)(src);
	m68k_incpci(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 10 (2/0) */
/* 2 0,0   */

/* MOVEA.W (d16,An),An */
void REGPARAM2 op_3068_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 31;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	src = (uae_s32)(uae_s16)src;
	m68k_areg(regs, dstreg) = (uae_s32)(uae_s16)(src);
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 12 (3/0) */
/* 4 0,0   */

/* MOVEA.W (d8,An,Xn),An */
void REGPARAM2 op_3070_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 31;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	do_cycles_ce000_internal(2);
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	src = (uae_s32)(uae_s16)src;
	m68k_areg(regs, dstreg) = (uae_s32)(uae_s16)(src);
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 14 (3/0) */
/* 4 4,0   */

/* MOVEA.W (xxx).W,An */
void REGPARAM2 op_3078_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 31;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	if (srca & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	src = (uae_s32)(uae_s16)src;
	m68k_areg(regs, dstreg) = (uae_s32)(uae_s16)(src);
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 12 (3/0) */
/* 4 0,0   */

/* MOVEA.W (xxx).L,An */
void REGPARAM2 op_3079_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 31;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	srca |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	if (srca & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	src = (uae_s32)(uae_s16)src;
	m68k_areg(regs, dstreg) = (uae_s32)(uae_s16)(src);
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 16 (4/0) */
/* 6 0,0   */

/* MOVEA.W (d16,PC),An */
void REGPARAM2 op_307a_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 31;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_getpci() + 2;
	srca += (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 2);
		return;
	}
	ipl_fetch_now();
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return;
	}
	src = (uae_s32)(uae_s16)src;
	m68k_areg(regs, dstreg) = (uae_s32)(uae_s16)(src);
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 12 (3/0) */
/* 4 0,0   */

/* MOVEA.W (d8,PC,Xn),An */
void REGPARAM2 op_307b_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 31;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	uaecptr tmppc = m68k_getpci() + 2;
	do_cycles_ce000_internal(2);
	srca = get_disp_ea_000(tmppc, get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 2);
		return;
	}
	ipl_fetch_now();
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return;
	}
	src = (uae_s32)(uae_s16)src;
	m68k_areg(regs, dstreg) = (uae_s32)(uae_s16)(src);
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 14 (3/0) */
/* 4 4,0   */

/* MOVEA.W #<data>.W,An */
void REGPARAM2 op_307c_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 31;
	CurrentInstrCycles = 8;  
	uae_s16 src = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	src = (uae_s32)(uae_s16)src;
	m68k_areg(regs, dstreg) = (uae_s32)(uae_s16)(src);
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 8 (2/0) */
/* 4 0,0   */

/* MOVE.W Dn,(An) */
void REGPARAM2 op_3080_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 8;  
	uae_s16 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(4);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		exception3_write_access(opcode, dsta, 1, src, 1);
		return;
	}
	ipl_fetch_now();
	x_put_word(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return;
	}
	m68k_incpci(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 8 (1/1) */
/* 2 0,0   */

/* MOVE.W An,(An) */
void REGPARAM2 op_3088_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 8;  
	uae_s16 src = m68k_areg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(4);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		exception3_write_access(opcode, dsta, 1, src, 1);
		return;
	}
	ipl_fetch_now();
	x_put_word(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return;
	}
	m68k_incpci(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 8 (1/1) */
/* 2 0,0   */

/* MOVE.W (An),(An) */
void REGPARAM2 op_3090_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(4);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		exception3_write_access(opcode, dsta, 1, src, 1);
		return;
	}
	ipl_fetch_now();
	x_put_word(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return;
	}
	m68k_incpci(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 12 (2/1) */
/* 2 0,0   */

/* MOVE.W (An)+,(An) */
void REGPARAM2 op_3098_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) += 2 + 0;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	m68k_areg(regs, srcreg) += 2;
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(4);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		exception3_write_access(opcode, dsta, 1, src, 1);
		return;
	}
	ipl_fetch_now();
	x_put_word(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return;
	}
	m68k_incpci(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 12 (2/1) */
/* 2 0,0   */

/* MOVE.W -(An),(An) */
void REGPARAM2 op_30a0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - 2;
	do_cycles_ce000_internal(2);
	if (srca & 1) {
		m68k_incpci(4);
		m68k_areg(regs, srcreg) = srca;
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	m68k_areg(regs, srcreg) = srca;
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(4);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		exception3_write_access(opcode, dsta, 1, src, 1);
		return;
	}
	ipl_fetch_now();
	x_put_word(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return;
	}
	m68k_incpci(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 14 (2/1) */
/* 2 0,0   */

/* MOVE.W (d16,An),(An) */
void REGPARAM2 op_30a8_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(6);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		exception3_write_access(opcode, dsta, 1, src, 1);
		return;
	}
	ipl_fetch_now();
	x_put_word(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* MOVE.W (d8,An,Xn),(An) */
void REGPARAM2 op_30b0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	do_cycles_ce000_internal(2);
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(6);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		exception3_write_access(opcode, dsta, 1, src, 1);
		return;
	}
	ipl_fetch_now();
	x_put_word(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 18 (3/1) */
/* 4 4,0   */

/* MOVE.W (xxx).W,(An) */
void REGPARAM2 op_30b8_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	if (srca & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(6);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		exception3_write_access(opcode, dsta, 1, src, 1);
		return;
	}
	ipl_fetch_now();
	x_put_word(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* MOVE.W (xxx).L,(An) */
void REGPARAM2 op_30b9_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	srca = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	srca |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	if (srca & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(8);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		exception3_write_access(opcode, dsta, 1, src, 1);
		return;
	}
	ipl_fetch_now();
	x_put_word(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return;
	}
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 20 (4/1) */
/* 6 0,0   */

/* MOVE.W (d16,PC),(An) */
void REGPARAM2 op_30ba_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = m68k_getpci() + 2;
	srca += (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 2);
		return;
	}
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(6);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		exception3_write_access(opcode, dsta, 1, src, 1);
		return;
	}
	ipl_fetch_now();
	x_put_word(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* MOVE.W (d8,PC,Xn),(An) */
void REGPARAM2 op_30bb_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	uaecptr tmppc = m68k_getpci() + 2;
	do_cycles_ce000_internal(2);
	srca = get_disp_ea_000(tmppc, get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 2);
		return;
	}
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(6);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		exception3_write_access(opcode, dsta, 1, src, 1);
		return;
	}
	ipl_fetch_now();
	x_put_word(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 18 (3/1) */
/* 4 4,0   */

/* MOVE.W #<data>.W,(An) */
void REGPARAM2 op_30bc_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 12; 
	uae_s16 src = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(6);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		exception3_write_access(opcode, dsta, 1, src, 1);
		return;
	}
	ipl_fetch_now();
	x_put_word(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 12 (2/1) */
/* 4 0,0   */

/* MOVE.W Dn,(An)+ */
void REGPARAM2 op_30c0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 8;  
	uae_s16 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	m68k_areg(regs, dstreg) += 2;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	ipl_fetch_next_pre();
	if (dsta & 1) {
		m68k_incpci(4);
		m68k_areg(regs, dstreg) -= 2;
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		exception3_write_access(opcode, dsta, 1, src, 1);
		return;
	}
	x_put_word(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, dstreg) -= 2;
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return;
	}
	m68k_incpci(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 8 (1/1) */
/* 2 0,0   */

/* MOVE.W An,(An)+ */
void REGPARAM2 op_30c8_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 8;  
	uae_s16 src = m68k_areg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	m68k_areg(regs, dstreg) += 2;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	ipl_fetch_next_pre();
	if (dsta & 1) {
		m68k_incpci(4);
		m68k_areg(regs, dstreg) -= 2;
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		exception3_write_access(opcode, dsta, 1, src, 1);
		return;
	}
	x_put_word(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, dstreg) -= 2;
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return;
	}
	m68k_incpci(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 8 (1/1) */
/* 2 0,0   */

/* MOVE.W (An),(An)+ */
void REGPARAM2 op_30d0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	m68k_areg(regs, dstreg) += 2;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(4);
		m68k_areg(regs, dstreg) -= 2;
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		exception3_write_access(opcode, dsta, 1, src, 1);
		return;
	}
	x_put_word(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, dstreg) -= 2;
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return;
	}
	m68k_incpci(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 12 (2/1) */
/* 2 0,0   */

/* MOVE.W (An)+,(An)+ */
void REGPARAM2 op_30d8_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) += 2 + 0;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	m68k_areg(regs, srcreg) += 2;
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	m68k_areg(regs, dstreg) += 2;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(4);
		m68k_areg(regs, dstreg) -= 2;
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		exception3_write_access(opcode, dsta, 1, src, 1);
		return;
	}
	x_put_word(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, dstreg) -= 2;
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return;
	}
	m68k_incpci(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 12 (2/1) */
/* 2 0,0   */

/* MOVE.W -(An),(An)+ */
void REGPARAM2 op_30e0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - 2;
	do_cycles_ce000_internal(2);
	if (srca & 1) {
		m68k_incpci(4);
		m68k_areg(regs, srcreg) = srca;
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	m68k_areg(regs, srcreg) = srca;
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	m68k_areg(regs, dstreg) += 2;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(4);
		m68k_areg(regs, dstreg) -= 2;
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		exception3_write_access(opcode, dsta, 1, src, 1);
		return;
	}
	x_put_word(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, dstreg) -= 2;
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return;
	}
	m68k_incpci(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 14 (2/1) */
/* 2 0,0   */

/* MOVE.W (d16,An),(An)+ */
void REGPARAM2 op_30e8_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	m68k_areg(regs, dstreg) += 2;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(6);
		m68k_areg(regs, dstreg) -= 2;
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		exception3_write_access(opcode, dsta, 1, src, 1);
		return;
	}
	x_put_word(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, dstreg) -= 2;
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* MOVE.W (d8,An,Xn),(An)+ */
void REGPARAM2 op_30f0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	do_cycles_ce000_internal(2);
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	m68k_areg(regs, dstreg) += 2;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(6);
		m68k_areg(regs, dstreg) -= 2;
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		exception3_write_access(opcode, dsta, 1, src, 1);
		return;
	}
	x_put_word(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, dstreg) -= 2;
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 18 (3/1) */
/* 4 4,0   */

/* MOVE.W (xxx).W,(An)+ */
void REGPARAM2 op_30f8_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	if (srca & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	m68k_areg(regs, dstreg) += 2;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(6);
		m68k_areg(regs, dstreg) -= 2;
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		exception3_write_access(opcode, dsta, 1, src, 1);
		return;
	}
	x_put_word(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, dstreg) -= 2;
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* MOVE.W (xxx).L,(An)+ */
void REGPARAM2 op_30f9_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	srca = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	srca |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	if (srca & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	m68k_areg(regs, dstreg) += 2;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(8);
		m68k_areg(regs, dstreg) -= 2;
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		exception3_write_access(opcode, dsta, 1, src, 1);
		return;
	}
	x_put_word(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		m68k_areg(regs, dstreg) -= 2;
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return;
	}
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 20 (4/1) */
/* 6 0,0   */

/* MOVE.W (d16,PC),(An)+ */
void REGPARAM2 op_30fa_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = m68k_getpci() + 2;
	srca += (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 2);
		return;
	}
	ipl_fetch_now();
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	m68k_areg(regs, dstreg) += 2;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(6);
		m68k_areg(regs, dstreg) -= 2;
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		exception3_write_access(opcode, dsta, 1, src, 1);
		return;
	}
	x_put_word(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, dstreg) -= 2;
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* MOVE.W (d8,PC,Xn),(An)+ */
void REGPARAM2 op_30fb_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	uaecptr tmppc = m68k_getpci() + 2;
	do_cycles_ce000_internal(2);
	srca = get_disp_ea_000(tmppc, get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 2);
		return;
	}
	ipl_fetch_now();
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	m68k_areg(regs, dstreg) += 2;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(6);
		m68k_areg(regs, dstreg) -= 2;
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		exception3_write_access(opcode, dsta, 1, src, 1);
		return;
	}
	x_put_word(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, dstreg) -= 2;
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 18 (3/1) */
/* 4 4,0   */

/* MOVE.W #<data>.W,(An)+ */
void REGPARAM2 op_30fc_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 12; 
	ipl_fetch_now();
	uae_s16 src = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	m68k_areg(regs, dstreg) += 2;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(6);
		m68k_areg(regs, dstreg) -= 2;
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		exception3_write_access(opcode, dsta, 1, src, 1);
		return;
	}
	x_put_word(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, dstreg) -= 2;
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 12 (2/1) */
/* 4 0,0   */

/* MOVE.W Dn,-(An) */
void REGPARAM2 op_3100_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 8;  
	ipl_fetch_next_pre();
	uae_s16 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - 2;
	m68k_areg(regs, dstreg) = dsta;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		m68k_areg(regs, dstreg) += 2;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(4);
		do_cycles_ce000_internal(2);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		m68k_areg(regs, dstreg) = dsta;
		exception3_write_access(opcode, dsta, 1, src, 1);
		return;
	}
	x_put_word(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 8 (1/1) */
/* 2 0,0   */

/* MOVE.W An,-(An) */
void REGPARAM2 op_3108_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 8;  
	ipl_fetch_next_pre();
	uae_s16 src = m68k_areg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - 2;
	m68k_areg(regs, dstreg) = dsta;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		m68k_areg(regs, dstreg) += 2;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(4);
		do_cycles_ce000_internal(2);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		m68k_areg(regs, dstreg) = dsta;
		exception3_write_access(opcode, dsta, 1, src, 1);
		return;
	}
	x_put_word(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 8 (1/1) */
/* 2 0,0   */

/* MOVE.W (An),-(An) */
void REGPARAM2 op_3110_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - 2;
	m68k_areg(regs, dstreg) = dsta;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		m68k_areg(regs, dstreg) += 2;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(4);
		do_cycles_ce000_internal(2);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		m68k_areg(regs, dstreg) = dsta;
		exception3_write_access(opcode, dsta, 1, src, 1);
		return;
	}
	x_put_word(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 12 (2/1) */
/* 2 0,0   */

/* MOVE.W (An)+,-(An) */
void REGPARAM2 op_3118_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) += 2 + 0;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	m68k_areg(regs, srcreg) += 2;
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - 2;
	m68k_areg(regs, dstreg) = dsta;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		m68k_areg(regs, dstreg) += 2;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(4);
		do_cycles_ce000_internal(2);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		m68k_areg(regs, dstreg) = dsta;
		exception3_write_access(opcode, dsta, 1, src, 1);
		return;
	}
	x_put_word(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 12 (2/1) */
/* 2 0,0   */

/* MOVE.W -(An),-(An) */
void REGPARAM2 op_3120_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - 2;
	do_cycles_ce000_internal(2);
	if (srca & 1) {
		m68k_incpci(4);
		m68k_areg(regs, srcreg) = srca;
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	m68k_areg(regs, srcreg) = srca;
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - 2;
	m68k_areg(regs, dstreg) = dsta;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		m68k_areg(regs, dstreg) += 2;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(4);
		do_cycles_ce000_internal(2);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		m68k_areg(regs, dstreg) = dsta;
		exception3_write_access(opcode, dsta, 1, src, 1);
		return;
	}
	x_put_word(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 14 (2/1) */
/* 2 0,0   */

/* MOVE.W (d16,An),-(An) */
void REGPARAM2 op_3128_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - 2;
	m68k_areg(regs, dstreg) = dsta;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		m68k_areg(regs, dstreg) += 2;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(6);
		do_cycles_ce000_internal(2);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		m68k_areg(regs, dstreg) = dsta;
		exception3_write_access(opcode, dsta, 1, src, 1);
		return;
	}
	x_put_word(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* MOVE.W (d8,An,Xn),-(An) */
void REGPARAM2 op_3130_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	do_cycles_ce000_internal(2);
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - 2;
	m68k_areg(regs, dstreg) = dsta;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		m68k_areg(regs, dstreg) += 2;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(6);
		do_cycles_ce000_internal(2);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		m68k_areg(regs, dstreg) = dsta;
		exception3_write_access(opcode, dsta, 1, src, 1);
		return;
	}
	x_put_word(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 18 (3/1) */
/* 4 4,0   */

/* MOVE.W (xxx).W,-(An) */
void REGPARAM2 op_3138_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	if (srca & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - 2;
	m68k_areg(regs, dstreg) = dsta;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		m68k_areg(regs, dstreg) += 2;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(6);
		do_cycles_ce000_internal(2);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		m68k_areg(regs, dstreg) = dsta;
		exception3_write_access(opcode, dsta, 1, src, 1);
		return;
	}
	x_put_word(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* MOVE.W (xxx).L,-(An) */
void REGPARAM2 op_3139_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	srca = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	srca |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	if (srca & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - 2;
	m68k_areg(regs, dstreg) = dsta;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		m68k_areg(regs, dstreg) += 2;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	opcode = regs.ir;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(8);
		do_cycles_ce000_internal(2);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		m68k_areg(regs, dstreg) = dsta;
		exception3_write_access(opcode, dsta, 1, src, 1);
		return;
	}
	x_put_word(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 20 (4/1) */
/* 6 0,0   */

/* MOVE.W (d16,PC),-(An) */
void REGPARAM2 op_313a_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = m68k_getpci() + 2;
	srca += (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 2);
		return;
	}
	ipl_fetch_now();
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - 2;
	m68k_areg(regs, dstreg) = dsta;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		m68k_areg(regs, dstreg) += 2;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(6);
		do_cycles_ce000_internal(2);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		m68k_areg(regs, dstreg) = dsta;
		exception3_write_access(opcode, dsta, 1, src, 1);
		return;
	}
	x_put_word(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* MOVE.W (d8,PC,Xn),-(An) */
void REGPARAM2 op_313b_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	uaecptr tmppc = m68k_getpci() + 2;
	do_cycles_ce000_internal(2);
	srca = get_disp_ea_000(tmppc, get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 2);
		return;
	}
	ipl_fetch_now();
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - 2;
	m68k_areg(regs, dstreg) = dsta;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		m68k_areg(regs, dstreg) += 2;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(6);
		do_cycles_ce000_internal(2);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		m68k_areg(regs, dstreg) = dsta;
		exception3_write_access(opcode, dsta, 1, src, 1);
		return;
	}
	x_put_word(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 18 (3/1) */
/* 4 4,0   */

/* MOVE.W #<data>.W,-(An) */
void REGPARAM2 op_313c_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 12; 
	ipl_fetch_now();
	uae_s16 src = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - 2;
	m68k_areg(regs, dstreg) = dsta;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		m68k_areg(regs, dstreg) += 2;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(6);
		do_cycles_ce000_internal(2);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		m68k_areg(regs, dstreg) = dsta;
		exception3_write_access(opcode, dsta, 1, src, 1);
		return;
	}
	x_put_word(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 12 (2/1) */
/* 4 0,0   */

/* MOVE.W Dn,(d16,An) */
void REGPARAM2 op_3140_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 12; 
	uae_s16 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(4);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		exception3_write_access(opcode, dsta, 1, src, 1);
		return;
	}
	ipl_fetch_now();
	x_put_word(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 12 (2/1) */
/* 4 0,0   */

/* MOVE.W An,(d16,An) */
void REGPARAM2 op_3148_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 12; 
	uae_s16 src = m68k_areg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(4);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		exception3_write_access(opcode, dsta, 1, src, 1);
		return;
	}
	ipl_fetch_now();
	x_put_word(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 12 (2/1) */
/* 4 0,0   */

/* MOVE.W (An),(d16,An) */
void REGPARAM2 op_3150_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 4, 0);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(4);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		exception3_write_access(opcode, dsta, 1, src, 1);
		return;
	}
	ipl_fetch_now();
	x_put_word(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* MOVE.W (An)+,(d16,An) */
void REGPARAM2 op_3158_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) += 2 + 0;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	m68k_areg(regs, srcreg) += 2;
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 4, 0);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(4);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		exception3_write_access(opcode, dsta, 1, src, 1);
		return;
	}
	ipl_fetch_now();
	x_put_word(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* MOVE.W -(An),(d16,An) */
void REGPARAM2 op_3160_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - 2;
	do_cycles_ce000_internal(2);
	if (srca & 1) {
		m68k_incpci(4);
		m68k_areg(regs, srcreg) = srca;
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	m68k_areg(regs, srcreg) = srca;
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 4, 0);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(4);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		exception3_write_access(opcode, dsta, 1, src, 1);
		return;
	}
	ipl_fetch_now();
	x_put_word(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 18 (3/1) */
/* 4 0,0   */

/* MOVE.W (d16,An),(d16,An) */
void REGPARAM2 op_3168_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 6, 0);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(6);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		exception3_write_access(opcode, dsta, 1, src, 1);
		return;
	}
	ipl_fetch_now();
	x_put_word(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return;
	}
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 20 (4/1) */
/* 6 0,0   */

/* MOVE.W (d8,An,Xn),(d16,An) */
void REGPARAM2 op_3170_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 22; 
	uaecptr srca;
	do_cycles_ce000_internal(2);
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 6, 0);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(6);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		exception3_write_access(opcode, dsta, 1, src, 1);
		return;
	}
	ipl_fetch_now();
	x_put_word(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return;
	}
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 22 (4/1) */
/* 6 6,0   */

/* MOVE.W (xxx).W,(d16,An) */
void REGPARAM2 op_3178_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	if (srca & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 6, 0);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(6);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		exception3_write_access(opcode, dsta, 1, src, 1);
		return;
	}
	ipl_fetch_now();
	x_put_word(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return;
	}
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 20 (4/1) */
/* 6 0,0   */

/* MOVE.W (xxx).L,(d16,An) */
void REGPARAM2 op_3179_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 24; 
	uaecptr srca;
	srca = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	srca |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	if (srca & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 8, 0);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(8);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		exception3_write_access(opcode, dsta, 1, src, 1);
		return;
	}
	ipl_fetch_now();
	x_put_word(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return;
	}
	m68k_incpci(8);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 24 (5/1) */
/* 8 0,0   */

/* MOVE.W (d16,PC),(d16,An) */
void REGPARAM2 op_317a_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	srca = m68k_getpci() + 2;
	srca += (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 2);
		return;
	}
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 6, 0);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(6);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		exception3_write_access(opcode, dsta, 1, src, 1);
		return;
	}
	ipl_fetch_now();
	x_put_word(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return;
	}
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 20 (4/1) */
/* 6 0,0   */

/* MOVE.W (d8,PC,Xn),(d16,An) */
void REGPARAM2 op_317b_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 22; 
	uaecptr srca;
	uaecptr tmppc = m68k_getpci() + 2;
	do_cycles_ce000_internal(2);
	srca = get_disp_ea_000(tmppc, get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 2);
		return;
	}
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 6, 0);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(6);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		exception3_write_access(opcode, dsta, 1, src, 1);
		return;
	}
	ipl_fetch_now();
	x_put_word(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return;
	}
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 22 (4/1) */
/* 6 6,0   */

/* MOVE.W #<data>.W,(d16,An) */
void REGPARAM2 op_317c_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 16; 
	uae_s16 src = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, 0);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(6);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		exception3_write_access(opcode, dsta, 1, src, 1);
		return;
	}
	ipl_fetch_now();
	x_put_word(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return;
	}
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 16 (3/1) */
/* 6 0,0   */

/* MOVE.W Dn,(d8,An,Xn) */
void REGPARAM2 op_3180_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 14; 
	uae_s16 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	do_cycles_ce000_internal(2);
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(4);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		exception3_write_access(opcode, dsta, 1, src, 1);
		return;
	}
	ipl_fetch_now();
	x_put_word(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 14 (2/1) */
/* 4 4,0   */

/* MOVE.W An,(d8,An,Xn) */
void REGPARAM2 op_3188_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 14; 
	uae_s16 src = m68k_areg(regs, srcreg);
	uaecptr dsta;
	do_cycles_ce000_internal(2);
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(4);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		exception3_write_access(opcode, dsta, 1, src, 1);
		return;
	}
	ipl_fetch_now();
	x_put_word(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 14 (2/1) */
/* 4 4,0   */

/* MOVE.W (An),(d8,An,Xn) */
void REGPARAM2 op_3190_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	uaecptr dsta;
	do_cycles_ce000_internal(2);
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 4, 0);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(4);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		exception3_write_access(opcode, dsta, 1, src, 1);
		return;
	}
	ipl_fetch_now();
	x_put_word(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 18 (3/1) */
/* 4 4,0   */

/* MOVE.W (An)+,(d8,An,Xn) */
void REGPARAM2 op_3198_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) += 2 + 0;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	m68k_areg(regs, srcreg) += 2;
	uaecptr dsta;
	do_cycles_ce000_internal(2);
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 4, 0);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(4);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		exception3_write_access(opcode, dsta, 1, src, 1);
		return;
	}
	ipl_fetch_now();
	x_put_word(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 18 (3/1) */
/* 4 4,0   */

/* MOVE.W -(An),(d8,An,Xn) */
void REGPARAM2 op_31a0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - 2;
	do_cycles_ce000_internal(2);
	if (srca & 1) {
		m68k_incpci(4);
		m68k_areg(regs, srcreg) = srca;
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	m68k_areg(regs, srcreg) = srca;
	uaecptr dsta;
	do_cycles_ce000_internal(2);
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 4, 0);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(4);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		exception3_write_access(opcode, dsta, 1, src, 1);
		return;
	}
	ipl_fetch_now();
	x_put_word(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return;
	}
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 20 (3/1) */
/* 4 4,0   */

/* MOVE.W (d16,An),(d8,An,Xn) */
void REGPARAM2 op_31a8_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 22; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	uaecptr dsta;
	do_cycles_ce000_internal(2);
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_ce000_prefetch(6));
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 6, 0);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(6);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		exception3_write_access(opcode, dsta, 1, src, 1);
		return;
	}
	ipl_fetch_now();
	x_put_word(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return;
	}
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 22 (4/1) */
/* 6 4,0   */

/* MOVE.W (d8,An,Xn),(d8,An,Xn) */
void REGPARAM2 op_31b0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 24; 
	uaecptr srca;
	do_cycles_ce000_internal(2);
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	uaecptr dsta;
	do_cycles_ce000_internal(2);
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_ce000_prefetch(6));
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 6, 0);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(6);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		exception3_write_access(opcode, dsta, 1, src, 1);
		return;
	}
	ipl_fetch_now();
	x_put_word(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return;
	}
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 24 (4/1) */
/* 6 6,4   */

/* MOVE.W (xxx).W,(d8,An,Xn) */
void REGPARAM2 op_31b8_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 22; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	if (srca & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	uaecptr dsta;
	do_cycles_ce000_internal(2);
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_ce000_prefetch(6));
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 6, 0);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(6);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		exception3_write_access(opcode, dsta, 1, src, 1);
		return;
	}
	ipl_fetch_now();
	x_put_word(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return;
	}
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 22 (4/1) */
/* 6 4,0   */

/* MOVE.W (xxx).L,(d8,An,Xn) */
void REGPARAM2 op_31b9_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 26; 
	uaecptr srca;
	srca = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	srca |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	if (srca & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	uaecptr dsta;
	do_cycles_ce000_internal(2);
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_ce000_prefetch(8));
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 8, 0);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(8);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		exception3_write_access(opcode, dsta, 1, src, 1);
		return;
	}
	ipl_fetch_now();
	x_put_word(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return;
	}
	m68k_incpci(8);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 26 (5/1) */
/* 8 4,0   */

/* MOVE.W (d16,PC),(d8,An,Xn) */
void REGPARAM2 op_31ba_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 22; 
	uaecptr srca;
	srca = m68k_getpci() + 2;
	srca += (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 2);
		return;
	}
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return;
	}
	uaecptr dsta;
	do_cycles_ce000_internal(2);
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_ce000_prefetch(6));
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 6, 0);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(6);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		exception3_write_access(opcode, dsta, 1, src, 1);
		return;
	}
	ipl_fetch_now();
	x_put_word(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return;
	}
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 22 (4/1) */
/* 6 4,0   */

/* MOVE.W (d8,PC,Xn),(d8,An,Xn) */
void REGPARAM2 op_31bb_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 24; 
	uaecptr srca;
	uaecptr tmppc = m68k_getpci() + 2;
	do_cycles_ce000_internal(2);
	srca = get_disp_ea_000(tmppc, get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 2);
		return;
	}
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return;
	}
	uaecptr dsta;
	do_cycles_ce000_internal(2);
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_ce000_prefetch(6));
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 6, 0);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(6);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		exception3_write_access(opcode, dsta, 1, src, 1);
		return;
	}
	ipl_fetch_now();
	x_put_word(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return;
	}
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 24 (4/1) */
/* 6 6,4   */

/* MOVE.W #<data>.W,(d8,An,Xn) */
void REGPARAM2 op_31bc_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 18; 
	uae_s16 src = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr dsta;
	do_cycles_ce000_internal(2);
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_ce000_prefetch(6));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, 0);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(6);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		exception3_write_access(opcode, dsta, 1, src, 1);
		return;
	}
	ipl_fetch_now();
	x_put_word(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return;
	}
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 18 (3/1) */
/* 6 4,0   */

/* MOVE.W Dn,(xxx).W */
void REGPARAM2 op_31c0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 30;
	CurrentInstrCycles = 12; 
	uae_s16 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 4, 0);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(4);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		exception3_write_access(opcode, dsta, 1, src, 1);
		return;
	}
	x_put_word(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return;
	}
	ipl_fetch_next();
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 12 (2/1) */
/* 4 0,0   */

/* MOVE.W An,(xxx).W */
void REGPARAM2 op_31c8_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 30;
	CurrentInstrCycles = 12; 
	uae_s16 src = m68k_areg(regs, srcreg);
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 4, 0);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(4);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		exception3_write_access(opcode, dsta, 1, src, 1);
		return;
	}
	x_put_word(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return;
	}
	ipl_fetch_next();
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 12 (2/1) */
/* 4 0,0   */

/* MOVE.W (An),(xxx).W */
void REGPARAM2 op_31d0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 30;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 4, 0);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(4);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		exception3_write_access(opcode, dsta, 1, src, 1);
		return;
	}
	x_put_word(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return;
	}
	ipl_fetch_next();
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* MOVE.W (An)+,(xxx).W */
void REGPARAM2 op_31d8_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 30;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) += 2 + 0;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	m68k_areg(regs, srcreg) += 2;
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 4, 0);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(4);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		exception3_write_access(opcode, dsta, 1, src, 1);
		return;
	}
	x_put_word(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return;
	}
	ipl_fetch_next();
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* MOVE.W -(An),(xxx).W */
void REGPARAM2 op_31e0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 30;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - 2;
	do_cycles_ce000_internal(2);
	if (srca & 1) {
		m68k_incpci(4);
		m68k_areg(regs, srcreg) = srca;
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	m68k_areg(regs, srcreg) = srca;
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 4, 0);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(4);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		exception3_write_access(opcode, dsta, 1, src, 1);
		return;
	}
	x_put_word(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return;
	}
	ipl_fetch_next();
	m68k_incpci(4);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 18 (3/1) */
/* 4 0,0   */

/* MOVE.W (d16,An),(xxx).W */
void REGPARAM2 op_31e8_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 30;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 6, 0);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(6);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		exception3_write_access(opcode, dsta, 1, src, 1);
		return;
	}
	x_put_word(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return;
	}
	ipl_fetch_next();
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 20 (4/1) */
/* 6 0,0   */

/* MOVE.W (d8,An,Xn),(xxx).W */
void REGPARAM2 op_31f0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 30;
	CurrentInstrCycles = 22; 
	uaecptr srca;
	do_cycles_ce000_internal(2);
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 6, 0);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(6);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		exception3_write_access(opcode, dsta, 1, src, 1);
		return;
	}
	x_put_word(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return;
	}
	ipl_fetch_next();
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 22 (4/1) */
/* 6 6,0   */

/* MOVE.W (xxx).W,(xxx).W */
void REGPARAM2 op_31f8_14_ff(uae_u32 opcode)
{
	OpcodeFamily = 30;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	if (srca & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 6, 0);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(6);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		exception3_write_access(opcode, dsta, 1, src, 1);
		return;
	}
	x_put_word(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return;
	}
	ipl_fetch_next();
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 20 (4/1) */
/* 6 0,0   */

/* MOVE.W (xxx).L,(xxx).W */
void REGPARAM2 op_31f9_14_ff(uae_u32 opcode)
{
	OpcodeFamily = 30;
	CurrentInstrCycles = 24; 
	uaecptr srca;
	srca = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	srca |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	if (srca & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 8, 0);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(8);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		exception3_write_access(opcode, dsta, 1, src, 1);
		return;
	}
	x_put_word(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return;
	}
	ipl_fetch_next();
	m68k_incpci(8);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 24 (5/1) */
/* 8 0,0   */

/* MOVE.W (d16,PC),(xxx).W */
void REGPARAM2 op_31fa_14_ff(uae_u32 opcode)
{
	OpcodeFamily = 30;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	srca = m68k_getpci() + 2;
	srca += (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 2);
		return;
	}
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return;
	}
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 6, 0);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(6);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		exception3_write_access(opcode, dsta, 1, src, 1);
		return;
	}
	x_put_word(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return;
	}
	ipl_fetch_next();
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 20 (4/1) */
/* 6 0,0   */

/* MOVE.W (d8,PC,Xn),(xxx).W */
void REGPARAM2 op_31fb_14_ff(uae_u32 opcode)
{
	OpcodeFamily = 30;
	CurrentInstrCycles = 22; 
	uaecptr srca;
	uaecptr tmppc = m68k_getpci() + 2;
	do_cycles_ce000_internal(2);
	srca = get_disp_ea_000(tmppc, get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 2);
		return;
	}
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return;
	}
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 6, 0);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(6);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		exception3_write_access(opcode, dsta, 1, src, 1);
		return;
	}
	x_put_word(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return;
	}
	ipl_fetch_next();
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 22 (4/1) */
/* 6 6,0   */

/* MOVE.W #<data>.W,(xxx).W */
void REGPARAM2 op_31fc_14_ff(uae_u32 opcode)
{
	OpcodeFamily = 30;
	CurrentInstrCycles = 16; 
	uae_s16 src = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 6, 0);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(6);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		exception3_write_access(opcode, dsta, 1, src, 1);
		return;
	}
	x_put_word(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return;
	}
	ipl_fetch_next();
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 16 (3/1) */
/* 6 0,0   */

/* MOVE.W Dn,(xxx).L */
void REGPARAM2 op_33c0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 30;
	CurrentInstrCycles = 16; 
	uae_s16 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	dsta |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(6);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		exception3_write_access(opcode, dsta, 1, src, 1);
		return;
	}
	x_put_word(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return;
	}
	ipl_fetch_next();
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 16 (3/1) */
/* 6 0,0   */

/* MOVE.W An,(xxx).L */
void REGPARAM2 op_33c8_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 30;
	CurrentInstrCycles = 16; 
	uae_s16 src = m68k_areg(regs, srcreg);
	uaecptr dsta;
	dsta = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	dsta |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(6);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		exception3_write_access(opcode, dsta, 1, src, 1);
		return;
	}
	x_put_word(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return;
	}
	ipl_fetch_next();
	m68k_incpci(6);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 16 (3/1) */
/* 6 0,0   */

/* MOVE.W (An),(xxx).L */
void REGPARAM2 op_33d0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 30;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	uaecptr dsta;
	dsta = get_word_ce000_prefetch(4) << 16;
	dsta |= regs.irc;
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 4, 0);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(4);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		exception3_write_access(opcode, dsta, 1, src, 1);
		return;
	}
	x_put_word(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return;
	}
	ipl_fetch_now();
	m68k_incpci(6);
	get_word_ce000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, 0);
		return;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	if(regs.t1) opcode |= 0x10000;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 20 (4/1) */
/* 6 0,0   */

/* MOVE.W (An)+,(xxx).L */
void REGPARAM2 op_33d8_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 30;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) += 2 + 0;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	m68k_areg(regs, srcreg) += 2;
	uaecptr dsta;
	dsta = get_word_ce000_prefetch(4) << 16;
	dsta |= regs.irc;
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 4, 0);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(4);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		exception3_write_access(opcode, dsta, 1, src, 1);
		return;
	}
	x_put_word(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return;
	}
	ipl_fetch_now();
	m68k_incpci(6);
	get_word_ce000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, 0);
		return;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	if(regs.t1) opcode |= 0x10000;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 20 (4/1) */
/* 6 0,0   */

/* MOVE.W -(An),(xxx).L */
void REGPARAM2 op_33e0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 30;
	CurrentInstrCycles = 22; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - 2;
	do_cycles_ce000_internal(2);
	if (srca & 1) {
		m68k_incpci(4);
		m68k_areg(regs, srcreg) = srca;
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	m68k_areg(regs, srcreg) = srca;
	uaecptr dsta;
	dsta = get_word_ce000_prefetch(4) << 16;
	dsta |= regs.irc;
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 4, 0);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(4);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		exception3_write_access(opcode, dsta, 1, src, 1);
		return;
	}
	x_put_word(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return;
	}
	ipl_fetch_now();
	m68k_incpci(6);
	get_word_ce000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, 0);
		return;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	if(regs.t1) opcode |= 0x10000;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 22 (4/1) */
/* 6 0,0   */

/* MOVE.W (d16,An),(xxx).L */
void REGPARAM2 op_33e8_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 30;
	CurrentInstrCycles = 24; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	uaecptr dsta;
	dsta = get_word_ce000_prefetch(6) << 16;
	dsta |= regs.irc;
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 6, 0);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(6);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		exception3_write_access(opcode, dsta, 1, src, 1);
		return;
	}
	x_put_word(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return;
	}
	ipl_fetch_now();
	m68k_incpci(8);
	get_word_ce000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, 0);
		return;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	if(regs.t1) opcode |= 0x10000;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 24 (5/1) */
/* 8 0,0   */

/* MOVE.W (d8,An,Xn),(xxx).L */
void REGPARAM2 op_33f0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 30;
	CurrentInstrCycles = 26; 
	uaecptr srca;
	do_cycles_ce000_internal(2);
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	uaecptr dsta;
	dsta = get_word_ce000_prefetch(6) << 16;
	dsta |= regs.irc;
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 6, 0);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(6);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		exception3_write_access(opcode, dsta, 1, src, 1);
		return;
	}
	x_put_word(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return;
	}
	ipl_fetch_now();
	m68k_incpci(8);
	get_word_ce000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, 0);
		return;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	if(regs.t1) opcode |= 0x10000;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 26 (5/1) */
/* 8 8,0   */

/* MOVE.W (xxx).W,(xxx).L */
void REGPARAM2 op_33f8_14_ff(uae_u32 opcode)
{
	OpcodeFamily = 30;
	CurrentInstrCycles = 24; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	if (srca & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	uaecptr dsta;
	dsta = get_word_ce000_prefetch(6) << 16;
	dsta |= regs.irc;
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 6, 0);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(6);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		exception3_write_access(opcode, dsta, 1, src, 1);
		return;
	}
	x_put_word(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return;
	}
	ipl_fetch_now();
	m68k_incpci(8);
	get_word_ce000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, 0);
		return;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	if(regs.t1) opcode |= 0x10000;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 24 (5/1) */
/* 8 0,0   */

/* MOVE.W (xxx).L,(xxx).L */
void REGPARAM2 op_33f9_14_ff(uae_u32 opcode)
{
	OpcodeFamily = 30;
	CurrentInstrCycles = 28; 
	uaecptr srca;
	srca = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	srca |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	if (srca & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	uaecptr dsta;
	dsta = get_word_ce000_prefetch(8) << 16;
	dsta |= regs.irc;
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 8, 0);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(8);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		exception3_write_access(opcode, dsta, 1, src, 1);
		return;
	}
	x_put_word(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return;
	}
	ipl_fetch_now();
	m68k_incpci(10);
	get_word_ce000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, 0);
		return;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	if(regs.t1) opcode |= 0x10000;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 28 (6/1) */
/* 10 0,0   */

/* MOVE.W (d16,PC),(xxx).L */
void REGPARAM2 op_33fa_14_ff(uae_u32 opcode)
{
	OpcodeFamily = 30;
	CurrentInstrCycles = 24; 
	uaecptr srca;
	srca = m68k_getpci() + 2;
	srca += (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 2);
		return;
	}
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return;
	}
	uaecptr dsta;
	dsta = get_word_ce000_prefetch(6) << 16;
	dsta |= regs.irc;
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 6, 0);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(6);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		exception3_write_access(opcode, dsta, 1, src, 1);
		return;
	}
	x_put_word(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return;
	}
	ipl_fetch_now();
	m68k_incpci(8);
	get_word_ce000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, 0);
		return;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	if(regs.t1) opcode |= 0x10000;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 24 (5/1) */
/* 8 0,0   */

/* MOVE.W (d8,PC,Xn),(xxx).L */
void REGPARAM2 op_33fb_14_ff(uae_u32 opcode)
{
	OpcodeFamily = 30;
	CurrentInstrCycles = 26; 
	uaecptr srca;
	uaecptr tmppc = m68k_getpci() + 2;
	do_cycles_ce000_internal(2);
	srca = get_disp_ea_000(tmppc, get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 2);
		return;
	}
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return;
	}
	uaecptr dsta;
	dsta = get_word_ce000_prefetch(6) << 16;
	dsta |= regs.irc;
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 6, 0);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(6);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		exception3_write_access(opcode, dsta, 1, src, 1);
		return;
	}
	x_put_word(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return;
	}
	ipl_fetch_now();
	m68k_incpci(8);
	get_word_ce000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, 0);
		return;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	if(regs.t1) opcode |= 0x10000;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 26 (5/1) */
/* 8 8,0   */

/* MOVE.W #<data>.W,(xxx).L */
void REGPARAM2 op_33fc_14_ff(uae_u32 opcode)
{
	OpcodeFamily = 30;
	CurrentInstrCycles = 20; 
	uae_s16 src = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr dsta;
	dsta = get_word_ce000_prefetch(6) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return;
	}
	dsta |= get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_word_move_ae_normal((uae_s16)src);
		exception2_fetch(opcode, 8, pcoffset);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	if (dsta & 1) {
		m68k_incpci(8);
		ccr_68000_word_move_ae_normal((uae_s16)(src));
		exception3_write_access(opcode, dsta, 1, src, 1);
		return;
	}
	x_put_word(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return;
	}
	ipl_fetch_next();
	m68k_incpci(8);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 20 (4/1) */
/* 8 0,0   */

/* NEGX.B Dn */
void REGPARAM2 op_4000_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 16;
	CurrentInstrCycles = 4;  
	uae_s8 src = m68k_dreg(regs, srcreg);
	uae_u32 newv = 0 - src - (GET_XFLG() ? 1 : 0);
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(0)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_VFLG((flgs ^ flgo) & (flgo ^ flgn));
	SET_CFLG(flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
	COPY_CARRY();
	SET_ZFLG(GET_ZFLG() & (((uae_s8)(newv)) == 0));
	SET_NFLG(((uae_s8)(newv)) < 0);
	m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((newv) & 0xff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 4 (1/0) */
/* 2 0,0   */

/* NEGX.B (An) */
void REGPARAM2 op_4010_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 16;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	uae_u32 newv = 0 - src - (GET_XFLG() ? 1 : 0);
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(0)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_VFLG((flgs ^ flgo) & (flgo ^ flgn));
	SET_CFLG(flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
	COPY_CARRY();
	SET_ZFLG(GET_ZFLG() & (((uae_s8)(newv)) == 0));
	SET_NFLG(((uae_s8)(newv)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_byte(srca, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, newv, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 12 (2/1) */
/* 2 0,0   */

/* NEGX.B (An)+ */
void REGPARAM2 op_4018_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 16;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
	uae_u32 newv = 0 - src - (GET_XFLG() ? 1 : 0);
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(0)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_VFLG((flgs ^ flgo) & (flgo ^ flgn));
	SET_CFLG(flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
	COPY_CARRY();
	SET_ZFLG(GET_ZFLG() & (((uae_s8)(newv)) == 0));
	SET_NFLG(((uae_s8)(newv)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_byte(srca, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, newv, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 12 (2/1) */
/* 2 0,0   */

/* NEGX.B -(An) */
void REGPARAM2 op_4020_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 16;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
	do_cycles_ce000_internal(2);
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	m68k_areg(regs, srcreg) = srca;
	uae_u32 newv = 0 - src - (GET_XFLG() ? 1 : 0);
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(0)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_VFLG((flgs ^ flgo) & (flgo ^ flgn));
	SET_CFLG(flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
	COPY_CARRY();
	SET_ZFLG(GET_ZFLG() & (((uae_s8)(newv)) == 0));
	SET_NFLG(((uae_s8)(newv)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_byte(srca, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, newv, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 14 (2/1) */
/* 2 0,0   */

/* NEGX.B (d16,An) */
void REGPARAM2 op_4028_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 16;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	uae_u32 newv = 0 - src - (GET_XFLG() ? 1 : 0);
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(0)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_VFLG((flgs ^ flgo) & (flgo ^ flgn));
	SET_CFLG(flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
	COPY_CARRY();
	SET_ZFLG(GET_ZFLG() & (((uae_s8)(newv)) == 0));
	SET_NFLG(((uae_s8)(newv)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_byte(srca, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, newv, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* NEGX.B (d8,An,Xn) */
void REGPARAM2 op_4030_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 16;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	do_cycles_ce000_internal(2);
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	uae_u32 newv = 0 - src - (GET_XFLG() ? 1 : 0);
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(0)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_VFLG((flgs ^ flgo) & (flgo ^ flgn));
	SET_CFLG(flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
	COPY_CARRY();
	SET_ZFLG(GET_ZFLG() & (((uae_s8)(newv)) == 0));
	SET_NFLG(((uae_s8)(newv)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_byte(srca, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, newv, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 18 (3/1) */
/* 4 4,0   */

/* NEGX.B (xxx).W */
void REGPARAM2 op_4038_14_ff(uae_u32 opcode)
{
	OpcodeFamily = 16;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	uae_u32 newv = 0 - src - (GET_XFLG() ? 1 : 0);
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(0)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_VFLG((flgs ^ flgo) & (flgo ^ flgn));
	SET_CFLG(flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
	COPY_CARRY();
	SET_ZFLG(GET_ZFLG() & (((uae_s8)(newv)) == 0));
	SET_NFLG(((uae_s8)(newv)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_byte(srca, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, newv, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* NEGX.B (xxx).L */
void REGPARAM2 op_4039_14_ff(uae_u32 opcode)
{
	OpcodeFamily = 16;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	srca = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	srca |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	uae_u32 newv = 0 - src - (GET_XFLG() ? 1 : 0);
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(0)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_VFLG((flgs ^ flgo) & (flgo ^ flgn));
	SET_CFLG(flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
	COPY_CARRY();
	SET_ZFLG(GET_ZFLG() & (((uae_s8)(newv)) == 0));
	SET_NFLG(((uae_s8)(newv)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_byte(srca, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, newv, 1);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 20 (4/1) */
/* 6 0,0   */

/* NEGX.W Dn */
void REGPARAM2 op_4040_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 16;
	CurrentInstrCycles = 4;  
	uae_s16 src = m68k_dreg(regs, srcreg);
	uae_u32 newv = 0 - src - (GET_XFLG() ? 1 : 0);
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(0)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_VFLG((flgs ^ flgo) & (flgo ^ flgn));
	SET_CFLG(flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
	COPY_CARRY();
	SET_ZFLG(GET_ZFLG() & (((uae_s16)(newv)) == 0));
	SET_NFLG(((uae_s16)(newv)) < 0);
	m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | ((newv) & 0xffff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 4 (1/0) */
/* 2 0,0   */

/* NEGX.W (An) */
void REGPARAM2 op_4050_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 16;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	uae_u32 newv = 0 - src - (GET_XFLG() ? 1 : 0);
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(0)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_VFLG((flgs ^ flgo) & (flgo ^ flgn));
	SET_CFLG(flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
	COPY_CARRY();
	SET_ZFLG(GET_ZFLG() & (((uae_s16)(newv)) == 0));
	SET_NFLG(((uae_s16)(newv)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_word(srca, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x1, newv, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 12 (2/1) */
/* 2 0,0   */

/* NEGX.W (An)+ */
void REGPARAM2 op_4058_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 16;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) += 2 + 0;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	m68k_areg(regs, srcreg) += 2;
	uae_u32 newv = 0 - src - (GET_XFLG() ? 1 : 0);
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(0)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_VFLG((flgs ^ flgo) & (flgo ^ flgn));
	SET_CFLG(flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
	COPY_CARRY();
	SET_ZFLG(GET_ZFLG() & (((uae_s16)(newv)) == 0));
	SET_NFLG(((uae_s16)(newv)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_word(srca, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x1, newv, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 12 (2/1) */
/* 2 0,0   */

/* NEGX.W -(An) */
void REGPARAM2 op_4060_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 16;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - 2;
	do_cycles_ce000_internal(2);
	if (srca & 1) {
		m68k_incpci(4);
		m68k_areg(regs, srcreg) = srca;
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	m68k_areg(regs, srcreg) = srca;
	uae_u32 newv = 0 - src - (GET_XFLG() ? 1 : 0);
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(0)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_VFLG((flgs ^ flgo) & (flgo ^ flgn));
	SET_CFLG(flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
	COPY_CARRY();
	SET_ZFLG(GET_ZFLG() & (((uae_s16)(newv)) == 0));
	SET_NFLG(((uae_s16)(newv)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_word(srca, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x1, newv, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 14 (2/1) */
/* 2 0,0   */

/* NEGX.W (d16,An) */
void REGPARAM2 op_4068_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 16;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	uae_u32 newv = 0 - src - (GET_XFLG() ? 1 : 0);
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(0)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_VFLG((flgs ^ flgo) & (flgo ^ flgn));
	SET_CFLG(flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
	COPY_CARRY();
	SET_ZFLG(GET_ZFLG() & (((uae_s16)(newv)) == 0));
	SET_NFLG(((uae_s16)(newv)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_word(srca, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x1, newv, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* NEGX.W (d8,An,Xn) */
void REGPARAM2 op_4070_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 16;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	do_cycles_ce000_internal(2);
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	uae_u32 newv = 0 - src - (GET_XFLG() ? 1 : 0);
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(0)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_VFLG((flgs ^ flgo) & (flgo ^ flgn));
	SET_CFLG(flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
	COPY_CARRY();
	SET_ZFLG(GET_ZFLG() & (((uae_s16)(newv)) == 0));
	SET_NFLG(((uae_s16)(newv)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_word(srca, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x1, newv, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 18 (3/1) */
/* 4 4,0   */

/* NEGX.W (xxx).W */
void REGPARAM2 op_4078_14_ff(uae_u32 opcode)
{
	OpcodeFamily = 16;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	if (srca & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	uae_u32 newv = 0 - src - (GET_XFLG() ? 1 : 0);
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(0)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_VFLG((flgs ^ flgo) & (flgo ^ flgn));
	SET_CFLG(flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
	COPY_CARRY();
	SET_ZFLG(GET_ZFLG() & (((uae_s16)(newv)) == 0));
	SET_NFLG(((uae_s16)(newv)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_word(srca, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x1, newv, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* NEGX.W (xxx).L */
void REGPARAM2 op_4079_14_ff(uae_u32 opcode)
{
	OpcodeFamily = 16;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	srca = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	srca |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	if (srca & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	uae_u32 newv = 0 - src - (GET_XFLG() ? 1 : 0);
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(0)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_VFLG((flgs ^ flgo) & (flgo ^ flgn));
	SET_CFLG(flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
	COPY_CARRY();
	SET_ZFLG(GET_ZFLG() & (((uae_s16)(newv)) == 0));
	SET_NFLG(((uae_s16)(newv)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_word(srca, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x1, newv, 1);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 20 (4/1) */
/* 6 0,0   */

/* NEGX.L Dn */
void REGPARAM2 op_4080_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 16;
	CurrentInstrCycles = 6;  
	uae_s32 src = m68k_dreg(regs, srcreg);
	uae_u32 newv = 0 - src - (GET_XFLG() ? 1 : 0);
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(0)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_VFLG((flgs ^ flgo) & (flgo ^ flgn));
	SET_CFLG(flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
	COPY_CARRY();
	SET_ZFLG(GET_ZFLG() & (((uae_s32)(newv)) == 0));
	SET_NFLG(((uae_s32)(newv)) < 0);
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		dreg_68000_long_replace_low(srcreg, newv);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	m68k_dreg(regs, srcreg) = (newv);
	do_cycles_ce000_internal(2);
	m68k_incpci(2);
	return;
}
/* 6 (1/0) */
/* 2 0,0   */

/* NEGX.L (An) */
void REGPARAM2 op_4090_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 16;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	uae_u32 newv = 0 - src - (GET_XFLG() ? 1 : 0);
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(0)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_VFLG((flgs ^ flgo) & (flgo ^ flgn));
	SET_CFLG(flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
	COPY_CARRY();
	SET_ZFLG(GET_ZFLG() & (((uae_s32)(newv)) == 0));
	SET_NFLG(((uae_s32)(newv)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		int bflgs = ((uae_s16)(src)) < 0;
		int bflgo = ((uae_s16)(0)) < 0;
		int bflgn = ((uae_s16)(newv)) < 0;
		SET_VFLG((bflgs ^ bflgo) & (bflgo ^ bflgn));
		SET_CFLG(bflgs ^ ((bflgs ^ bflgn) & (bflgo ^ bflgn)));
		SET_ZFLG(GET_ZFLG() & (((uae_s16)(newv)) == 0));
		SET_NFLG(((uae_s16)(newv)) < 0);
		SET_XFLG(GET_CFLG());
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	x_put_word(srca + 2, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, srca + 2, 0x1, newv, 1);
		return;
	}
	x_put_word(srca, newv >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, srca + 0, 0x1, newv >> 16, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 20 (3/2) */
/* 2 0,0   */

/* NEGX.L (An)+ */
void REGPARAM2 op_4098_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 16;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	m68k_areg(regs, srcreg) += 4;
	uae_u32 newv = 0 - src - (GET_XFLG() ? 1 : 0);
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(0)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_VFLG((flgs ^ flgo) & (flgo ^ flgn));
	SET_CFLG(flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
	COPY_CARRY();
	SET_ZFLG(GET_ZFLG() & (((uae_s32)(newv)) == 0));
	SET_NFLG(((uae_s32)(newv)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		int bflgs = ((uae_s16)(src)) < 0;
		int bflgo = ((uae_s16)(0)) < 0;
		int bflgn = ((uae_s16)(newv)) < 0;
		SET_VFLG((bflgs ^ bflgo) & (bflgo ^ bflgn));
		SET_CFLG(bflgs ^ ((bflgs ^ bflgn) & (bflgo ^ bflgn)));
		SET_ZFLG(GET_ZFLG() & (((uae_s16)(newv)) == 0));
		SET_NFLG(((uae_s16)(newv)) < 0);
		SET_XFLG(GET_CFLG());
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	x_put_word(srca + 2, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, srca + 2, 0x1, newv, 1);
		return;
	}
	x_put_word(srca, newv >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, srca + 0, 0x1, newv >> 16, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 20 (3/2) */
/* 2 0,0   */

/* NEGX.L -(An) */
void REGPARAM2 op_40a0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 16;
	CurrentInstrCycles = 22; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - 4;
	do_cycles_ce000_internal(2);
	if (srca & 1) {
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	m68k_areg(regs, srcreg) = srca;
	uae_u32 newv = 0 - src - (GET_XFLG() ? 1 : 0);
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(0)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_VFLG((flgs ^ flgo) & (flgo ^ flgn));
	SET_CFLG(flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
	COPY_CARRY();
	SET_ZFLG(GET_ZFLG() & (((uae_s32)(newv)) == 0));
	SET_NFLG(((uae_s32)(newv)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		int bflgs = ((uae_s16)(src)) < 0;
		int bflgo = ((uae_s16)(0)) < 0;
		int bflgn = ((uae_s16)(newv)) < 0;
		SET_VFLG((bflgs ^ bflgo) & (bflgo ^ bflgn));
		SET_CFLG(bflgs ^ ((bflgs ^ bflgn) & (bflgo ^ bflgn)));
		SET_ZFLG(GET_ZFLG() & (((uae_s16)(newv)) == 0));
		SET_NFLG(((uae_s16)(newv)) < 0);
		SET_XFLG(GET_CFLG());
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	x_put_word(srca + 2, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, srca + 2, 0x1, newv, 1);
		return;
	}
	x_put_word(srca, newv >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, srca + 0, 0x1, newv >> 16, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 22 (3/2) */
/* 2 0,0   */

/* NEGX.L (d16,An) */
void REGPARAM2 op_40a8_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 16;
	CurrentInstrCycles = 24; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	uae_u32 newv = 0 - src - (GET_XFLG() ? 1 : 0);
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(0)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_VFLG((flgs ^ flgo) & (flgo ^ flgn));
	SET_CFLG(flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
	COPY_CARRY();
	SET_ZFLG(GET_ZFLG() & (((uae_s32)(newv)) == 0));
	SET_NFLG(((uae_s32)(newv)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		int bflgs = ((uae_s16)(src)) < 0;
		int bflgo = ((uae_s16)(0)) < 0;
		int bflgn = ((uae_s16)(newv)) < 0;
		SET_VFLG((bflgs ^ bflgo) & (bflgo ^ bflgn));
		SET_CFLG(bflgs ^ ((bflgs ^ bflgn) & (bflgo ^ bflgn)));
		SET_ZFLG(GET_ZFLG() & (((uae_s16)(newv)) == 0));
		SET_NFLG(((uae_s16)(newv)) < 0);
		SET_XFLG(GET_CFLG());
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	x_put_word(srca + 2, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, srca + 2, 0x1, newv, 1);
		return;
	}
	x_put_word(srca, newv >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, srca + 0, 0x1, newv >> 16, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 24 (4/2) */
/* 4 0,0   */

/* NEGX.L (d8,An,Xn) */
void REGPARAM2 op_40b0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 16;
	CurrentInstrCycles = 26; 
	uaecptr srca;
	do_cycles_ce000_internal(2);
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	uae_u32 newv = 0 - src - (GET_XFLG() ? 1 : 0);
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(0)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_VFLG((flgs ^ flgo) & (flgo ^ flgn));
	SET_CFLG(flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
	COPY_CARRY();
	SET_ZFLG(GET_ZFLG() & (((uae_s32)(newv)) == 0));
	SET_NFLG(((uae_s32)(newv)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		int bflgs = ((uae_s16)(src)) < 0;
		int bflgo = ((uae_s16)(0)) < 0;
		int bflgn = ((uae_s16)(newv)) < 0;
		SET_VFLG((bflgs ^ bflgo) & (bflgo ^ bflgn));
		SET_CFLG(bflgs ^ ((bflgs ^ bflgn) & (bflgo ^ bflgn)));
		SET_ZFLG(GET_ZFLG() & (((uae_s16)(newv)) == 0));
		SET_NFLG(((uae_s16)(newv)) < 0);
		SET_XFLG(GET_CFLG());
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	x_put_word(srca + 2, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, srca + 2, 0x1, newv, 1);
		return;
	}
	x_put_word(srca, newv >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, srca + 0, 0x1, newv >> 16, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 26 (4/2) */
/* 4 4,0   */

/* NEGX.L (xxx).W */
void REGPARAM2 op_40b8_14_ff(uae_u32 opcode)
{
	OpcodeFamily = 16;
	CurrentInstrCycles = 24; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	if (srca & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	uae_u32 newv = 0 - src - (GET_XFLG() ? 1 : 0);
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(0)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_VFLG((flgs ^ flgo) & (flgo ^ flgn));
	SET_CFLG(flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
	COPY_CARRY();
	SET_ZFLG(GET_ZFLG() & (((uae_s32)(newv)) == 0));
	SET_NFLG(((uae_s32)(newv)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		int bflgs = ((uae_s16)(src)) < 0;
		int bflgo = ((uae_s16)(0)) < 0;
		int bflgn = ((uae_s16)(newv)) < 0;
		SET_VFLG((bflgs ^ bflgo) & (bflgo ^ bflgn));
		SET_CFLG(bflgs ^ ((bflgs ^ bflgn) & (bflgo ^ bflgn)));
		SET_ZFLG(GET_ZFLG() & (((uae_s16)(newv)) == 0));
		SET_NFLG(((uae_s16)(newv)) < 0);
		SET_XFLG(GET_CFLG());
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	x_put_word(srca + 2, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, srca + 2, 0x1, newv, 1);
		return;
	}
	x_put_word(srca, newv >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, srca + 0, 0x1, newv >> 16, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 24 (4/2) */
/* 4 0,0   */

/* NEGX.L (xxx).L */
void REGPARAM2 op_40b9_14_ff(uae_u32 opcode)
{
	OpcodeFamily = 16;
	CurrentInstrCycles = 28; 
	uaecptr srca;
	srca = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	srca |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	if (srca & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	uae_u32 newv = 0 - src - (GET_XFLG() ? 1 : 0);
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(0)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_VFLG((flgs ^ flgo) & (flgo ^ flgn));
	SET_CFLG(flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
	COPY_CARRY();
	SET_ZFLG(GET_ZFLG() & (((uae_s32)(newv)) == 0));
	SET_NFLG(((uae_s32)(newv)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		int bflgs = ((uae_s16)(src)) < 0;
		int bflgo = ((uae_s16)(0)) < 0;
		int bflgn = ((uae_s16)(newv)) < 0;
		SET_VFLG((bflgs ^ bflgo) & (bflgo ^ bflgn));
		SET_CFLG(bflgs ^ ((bflgs ^ bflgn) & (bflgo ^ bflgn)));
		SET_ZFLG(GET_ZFLG() & (((uae_s16)(newv)) == 0));
		SET_NFLG(((uae_s16)(newv)) < 0);
		SET_XFLG(GET_CFLG());
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	x_put_word(srca + 2, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, srca + 2, 0x1, newv, 1);
		return;
	}
	x_put_word(srca, newv >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, srca + 0, 0x1, newv >> 16, 1);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 28 (5/2) */
/* 6 0,0   */

/* MVSR2.W Dn */
void REGPARAM2 op_40c0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 32;
	CurrentInstrCycles = 6;  
	MakeSR();
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		MakeSR();
		m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | ((regs.sr) & 0xffff);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	do_cycles_ce000_internal(2);
	m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | ((regs.sr) & 0xffff);
	m68k_incpci(2);
	return;
}
/* 6 (1/0) */
/* 2 0,0   */

/* MVSR2.W (An) */
void REGPARAM2 op_40d0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 32;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	ipl_fetch_now();
	MakeSR();
	x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_word(srca, regs.sr);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x1, regs.sr, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 12 (1/2) */
/* 2 0,0   */

/* MVSR2.W (An)+ */
void REGPARAM2 op_40d8_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 32;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	ipl_fetch_now();
	m68k_areg(regs, srcreg) += 2;
	MakeSR();
	x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_word(srca, regs.sr);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x1, regs.sr, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 12 (1/2) */
/* 2 0,0   */

/* MVSR2.W -(An) */
void REGPARAM2 op_40e0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 32;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - 2;
	do_cycles_ce000_internal(2);
	if (srca & 1) {
		m68k_incpci(4);
		m68k_areg(regs, srcreg) = srca;
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	ipl_fetch_now();
	m68k_areg(regs, srcreg) = srca;
	MakeSR();
	x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_word(srca, regs.sr);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x1, regs.sr, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 14 (1/2) */
/* 2 0,0   */

/* MVSR2.W (d16,An) */
void REGPARAM2 op_40e8_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 32;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	ipl_fetch_now();
	MakeSR();
	x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_word(srca, regs.sr);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x1, regs.sr, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (2/2) */
/* 4 0,0   */

/* MVSR2.W (d8,An,Xn) */
void REGPARAM2 op_40f0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 32;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	do_cycles_ce000_internal(2);
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	ipl_fetch_now();
	MakeSR();
	x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_word(srca, regs.sr);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x1, regs.sr, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 18 (2/2) */
/* 4 4,0   */

/* MVSR2.W (xxx).W */
void REGPARAM2 op_40f8_14_ff(uae_u32 opcode)
{
	OpcodeFamily = 32;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	if (srca & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	ipl_fetch_now();
	MakeSR();
	x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_word(srca, regs.sr);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x1, regs.sr, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (2/2) */
/* 4 0,0   */

/* MVSR2.W (xxx).L */
void REGPARAM2 op_40f9_14_ff(uae_u32 opcode)
{
	OpcodeFamily = 32;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	srca = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	srca |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	if (srca & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	ipl_fetch_now();
	MakeSR();
	x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_word(srca, regs.sr);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x1, regs.sr, 1);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 20 (3/2) */
/* 6 0,0   */

/* CHK.W Dn,Dn */
void REGPARAM2 op_4180_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 80;
	CurrentInstrCycles = 10; 
	uae_s16 src = m68k_dreg(regs, srcreg);
	uae_s16 dst = m68k_dreg(regs, dstreg);
	m68k_incpci(2);
	do_cycles_ce000_internal(4);
	if (dst > src) {
		setchkundefinedflags(src, dst, 1);
		Exception_cpu(6);
		return;
	}
	do_cycles_ce000_internal(2);
	if ((uae_s32)dst < 0) {
		setchkundefinedflags(src, dst, 1);
		Exception_cpu(6);
		return;
	}
	setchkundefinedflags(src, dst, 1);
	ipl_fetch_next();
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 10 (1/0) */
/* 2 0,0   */

/* CHK.W (An),Dn */
void REGPARAM2 op_4190_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 80;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	m68k_incpci(2);
	do_cycles_ce000_internal(4);
	if (dst > src) {
		setchkundefinedflags(src, dst, 1);
		Exception_cpu(6);
		return;
	}
	do_cycles_ce000_internal(2);
	if ((uae_s32)dst < 0) {
		setchkundefinedflags(src, dst, 1);
		Exception_cpu(6);
		return;
	}
	setchkundefinedflags(src, dst, 1);
	ipl_fetch_next();
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 14 (2/0) */
/* 2 0,0   */

/* CHK.W (An)+,Dn */
void REGPARAM2 op_4198_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 80;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) += 2 + 0;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	m68k_areg(regs, srcreg) += 2;
	uae_s16 dst = m68k_dreg(regs, dstreg);
	m68k_incpci(2);
	do_cycles_ce000_internal(4);
	if (dst > src) {
		setchkundefinedflags(src, dst, 1);
		Exception_cpu(6);
		return;
	}
	do_cycles_ce000_internal(2);
	if ((uae_s32)dst < 0) {
		setchkundefinedflags(src, dst, 1);
		Exception_cpu(6);
		return;
	}
	setchkundefinedflags(src, dst, 1);
	ipl_fetch_next();
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 14 (2/0) */
/* 2 0,0   */

/* CHK.W -(An),Dn */
void REGPARAM2 op_41a0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 80;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - 2;
	do_cycles_ce000_internal(2);
	if (srca & 1) {
		m68k_incpci(4);
		m68k_areg(regs, srcreg) = srca;
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	m68k_areg(regs, srcreg) = srca;
	uae_s16 dst = m68k_dreg(regs, dstreg);
	m68k_incpci(2);
	do_cycles_ce000_internal(4);
	if (dst > src) {
		setchkundefinedflags(src, dst, 1);
		Exception_cpu(6);
		return;
	}
	do_cycles_ce000_internal(2);
	if ((uae_s32)dst < 0) {
		setchkundefinedflags(src, dst, 1);
		Exception_cpu(6);
		return;
	}
	setchkundefinedflags(src, dst, 1);
	ipl_fetch_next();
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 16 (2/0) */
/* 2 0,0   */

/* CHK.W (d16,An),Dn */
void REGPARAM2 op_41a8_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 80;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	m68k_incpci(4);
	do_cycles_ce000_internal(4);
	if (dst > src) {
		setchkundefinedflags(src, dst, 1);
		Exception_cpu(6);
		return;
	}
	do_cycles_ce000_internal(2);
	if ((uae_s32)dst < 0) {
		setchkundefinedflags(src, dst, 1);
		Exception_cpu(6);
		return;
	}
	setchkundefinedflags(src, dst, 1);
	ipl_fetch_next();
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 18 (3/0) */
/* 4 0,0   */

/* CHK.W (d8,An,Xn),Dn */
void REGPARAM2 op_41b0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 80;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	do_cycles_ce000_internal(2);
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	m68k_incpci(4);
	do_cycles_ce000_internal(4);
	if (dst > src) {
		setchkundefinedflags(src, dst, 1);
		Exception_cpu(6);
		return;
	}
	do_cycles_ce000_internal(2);
	if ((uae_s32)dst < 0) {
		setchkundefinedflags(src, dst, 1);
		Exception_cpu(6);
		return;
	}
	setchkundefinedflags(src, dst, 1);
	ipl_fetch_next();
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 20 (3/0) */
/* 4 4,0   */

/* CHK.W (xxx).W,Dn */
void REGPARAM2 op_41b8_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 80;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	if (srca & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	m68k_incpci(4);
	do_cycles_ce000_internal(4);
	if (dst > src) {
		setchkundefinedflags(src, dst, 1);
		Exception_cpu(6);
		return;
	}
	do_cycles_ce000_internal(2);
	if ((uae_s32)dst < 0) {
		setchkundefinedflags(src, dst, 1);
		Exception_cpu(6);
		return;
	}
	setchkundefinedflags(src, dst, 1);
	ipl_fetch_next();
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 18 (3/0) */
/* 4 0,0   */

/* CHK.W (xxx).L,Dn */
void REGPARAM2 op_41b9_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 80;
	CurrentInstrCycles = 22; 
	uaecptr srca;
	srca = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	srca |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	if (srca & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	m68k_incpci(6);
	do_cycles_ce000_internal(4);
	if (dst > src) {
		setchkundefinedflags(src, dst, 1);
		Exception_cpu(6);
		return;
	}
	do_cycles_ce000_internal(2);
	if ((uae_s32)dst < 0) {
		setchkundefinedflags(src, dst, 1);
		Exception_cpu(6);
		return;
	}
	setchkundefinedflags(src, dst, 1);
	ipl_fetch_next();
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 22 (4/0) */
/* 6 0,0   */

/* CHK.W (d16,PC),Dn */
void REGPARAM2 op_41ba_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 80;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	srca = m68k_getpci() + 2;
	srca += (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 2);
		return;
	}
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	m68k_incpci(4);
	do_cycles_ce000_internal(4);
	if (dst > src) {
		setchkundefinedflags(src, dst, 1);
		Exception_cpu(6);
		return;
	}
	do_cycles_ce000_internal(2);
	if ((uae_s32)dst < 0) {
		setchkundefinedflags(src, dst, 1);
		Exception_cpu(6);
		return;
	}
	setchkundefinedflags(src, dst, 1);
	ipl_fetch_next();
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 18 (3/0) */
/* 4 0,0   */

/* CHK.W (d8,PC,Xn),Dn */
void REGPARAM2 op_41bb_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 80;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	uaecptr tmppc = m68k_getpci() + 2;
	do_cycles_ce000_internal(2);
	srca = get_disp_ea_000(tmppc, get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 2);
		return;
	}
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	m68k_incpci(4);
	do_cycles_ce000_internal(4);
	if (dst > src) {
		setchkundefinedflags(src, dst, 1);
		Exception_cpu(6);
		return;
	}
	do_cycles_ce000_internal(2);
	if ((uae_s32)dst < 0) {
		setchkundefinedflags(src, dst, 1);
		Exception_cpu(6);
		return;
	}
	setchkundefinedflags(src, dst, 1);
	ipl_fetch_next();
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 20 (3/0) */
/* 4 4,0   */

/* CHK.W #<data>.W,Dn */
void REGPARAM2 op_41bc_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 80;
	CurrentInstrCycles = 14; 
	uae_s16 src = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	m68k_incpci(4);
	do_cycles_ce000_internal(4);
	if (dst > src) {
		setchkundefinedflags(src, dst, 1);
		Exception_cpu(6);
		return;
	}
	do_cycles_ce000_internal(2);
	if ((uae_s32)dst < 0) {
		setchkundefinedflags(src, dst, 1);
		Exception_cpu(6);
		return;
	}
	setchkundefinedflags(src, dst, 1);
	ipl_fetch_next();
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 14 (2/0) */
/* 4 0,0   */

/* LEA.L (An),An */
void REGPARAM2 op_41d0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 56;
	CurrentInstrCycles = 4;  
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	m68k_areg(regs, dstreg) = (srca);
	ipl_fetch_next();
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		m68k_areg(regs, dstreg) = (srca);
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 4 (1/0) */
/* 2 0,0   */

/* LEA.L (d16,An),An */
void REGPARAM2 op_41e8_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 56;
	CurrentInstrCycles = 8;  
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		m68k_areg(regs, dstreg) = (srca);
		exception2_fetch(opcode, 4, -2);
		return;
	}
	m68k_areg(regs, dstreg) = (srca);
	ipl_fetch_next();
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 8 (2/0) */
/* 4 0,0   */

/* LEA.L (d8,An,Xn),An */
void REGPARAM2 op_41f0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 56;
	CurrentInstrCycles = 12; 
	do_cycles_ce000_internal(2);
	uaecptr srca;
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	do_cycles_ce000_internal(2);
	m68k_areg(regs, dstreg) = (srca);
	ipl_fetch_next();
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 12 (2/0) */
/* 4 4,0   */

/* LEA.L (xxx).W,An */
void REGPARAM2 op_41f8_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 56;
	CurrentInstrCycles = 8;  
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		m68k_areg(regs, dstreg) = (srca);
		exception2_fetch(opcode, 4, -2);
		return;
	}
	m68k_areg(regs, dstreg) = (srca);
	ipl_fetch_next();
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 8 (2/0) */
/* 4 0,0   */

/* LEA.L (xxx).L,An */
void REGPARAM2 op_41f9_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 56;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		m68k_areg(regs, dstreg) = (m68k_areg(regs, dstreg) & 0x0000ffff) | (srca & 0xffff0000);
		exception2_fetch(opcode, 4, -2);
		return;
	}
	srca |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		m68k_areg(regs, dstreg) = (srca);
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	m68k_areg(regs, dstreg) = (srca);
	ipl_fetch_next();
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 12 (3/0) */
/* 6 0,0   */

/* LEA.L (d16,PC),An */
void REGPARAM2 op_41fa_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 56;
	CurrentInstrCycles = 8;  
	uaecptr srca;
	srca = m68k_getpci() + 2;
	srca += (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		m68k_areg(regs, dstreg) = (srca);
		exception2_fetch(opcode, 4, -2);
		return;
	}
	m68k_areg(regs, dstreg) = (srca);
	ipl_fetch_next();
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 8 (2/0) */
/* 4 0,0   */

/* LEA.L (d8,PC,Xn),An */
void REGPARAM2 op_41fb_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 56;
	CurrentInstrCycles = 12; 
	do_cycles_ce000_internal(2);
	uaecptr srca;
	uaecptr tmppc = m68k_getpci() + 2;
	srca = get_disp_ea_000(tmppc, get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	do_cycles_ce000_internal(2);
	m68k_areg(regs, dstreg) = (srca);
	ipl_fetch_next();
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 12 (2/0) */
/* 4 4,0   */

/* CLR.B Dn */
void REGPARAM2 op_4200_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 18;
	CurrentInstrCycles = 4;  
	uae_s8 src = m68k_dreg(regs, srcreg);
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(0)) == 0);
	SET_NFLG(((uae_s8)(0)) < 0);
	m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((0) & 0xff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 4 (1/0) */
/* 2 0,0   */

/* CLR.B (An) */
void REGPARAM2 op_4210_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 18;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(0)) == 0);
	SET_NFLG(((uae_s8)(0)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_byte(srca, 0);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, 0, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 12 (2/1) */
/* 2 0,0   */

/* CLR.B (An)+ */
void REGPARAM2 op_4218_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 18;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(0)) == 0);
	SET_NFLG(((uae_s8)(0)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_byte(srca, 0);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, 0, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 12 (2/1) */
/* 2 0,0   */

/* CLR.B -(An) */
void REGPARAM2 op_4220_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 18;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
	do_cycles_ce000_internal(2);
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	m68k_areg(regs, srcreg) = srca;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(0)) == 0);
	SET_NFLG(((uae_s8)(0)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_byte(srca, 0);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, 0, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 14 (2/1) */
/* 2 0,0   */

/* CLR.B (d16,An) */
void REGPARAM2 op_4228_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 18;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(0)) == 0);
	SET_NFLG(((uae_s8)(0)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_byte(srca, 0);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, 0, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* CLR.B (d8,An,Xn) */
void REGPARAM2 op_4230_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 18;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	do_cycles_ce000_internal(2);
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(0)) == 0);
	SET_NFLG(((uae_s8)(0)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_byte(srca, 0);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, 0, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 18 (3/1) */
/* 4 4,0   */

/* CLR.B (xxx).W */
void REGPARAM2 op_4238_14_ff(uae_u32 opcode)
{
	OpcodeFamily = 18;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(0)) == 0);
	SET_NFLG(((uae_s8)(0)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_byte(srca, 0);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, 0, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* CLR.B (xxx).L */
void REGPARAM2 op_4239_14_ff(uae_u32 opcode)
{
	OpcodeFamily = 18;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	srca = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	srca |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(0)) == 0);
	SET_NFLG(((uae_s8)(0)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_byte(srca, 0);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, 0, 1);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 20 (4/1) */
/* 6 0,0   */

/* CLR.W Dn */
void REGPARAM2 op_4240_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 18;
	CurrentInstrCycles = 4;  
	uae_s16 src = m68k_dreg(regs, srcreg);
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(0)) == 0);
	SET_NFLG(((uae_s16)(0)) < 0);
	m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | ((0) & 0xffff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 4 (1/0) */
/* 2 0,0   */

/* CLR.W (An) */
void REGPARAM2 op_4250_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 18;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(0)) == 0);
	SET_NFLG(((uae_s16)(0)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_word(srca, 0);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x1, 0, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 12 (2/1) */
/* 2 0,0   */

/* CLR.W (An)+ */
void REGPARAM2 op_4258_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 18;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) += 2 + 0;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	m68k_areg(regs, srcreg) += 2;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(0)) == 0);
	SET_NFLG(((uae_s16)(0)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_word(srca, 0);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x1, 0, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 12 (2/1) */
/* 2 0,0   */

/* CLR.W -(An) */
void REGPARAM2 op_4260_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 18;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - 2;
	do_cycles_ce000_internal(2);
	if (srca & 1) {
		m68k_incpci(4);
		m68k_areg(regs, srcreg) = srca;
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	m68k_areg(regs, srcreg) = srca;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(0)) == 0);
	SET_NFLG(((uae_s16)(0)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_word(srca, 0);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x1, 0, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 14 (2/1) */
/* 2 0,0   */

/* CLR.W (d16,An) */
void REGPARAM2 op_4268_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 18;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(0)) == 0);
	SET_NFLG(((uae_s16)(0)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_word(srca, 0);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x1, 0, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* CLR.W (d8,An,Xn) */
void REGPARAM2 op_4270_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 18;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	do_cycles_ce000_internal(2);
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(0)) == 0);
	SET_NFLG(((uae_s16)(0)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_word(srca, 0);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x1, 0, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 18 (3/1) */
/* 4 4,0   */

/* CLR.W (xxx).W */
void REGPARAM2 op_4278_14_ff(uae_u32 opcode)
{
	OpcodeFamily = 18;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	if (srca & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(0)) == 0);
	SET_NFLG(((uae_s16)(0)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_word(srca, 0);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x1, 0, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* CLR.W (xxx).L */
void REGPARAM2 op_4279_14_ff(uae_u32 opcode)
{
	OpcodeFamily = 18;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	srca = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	srca |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	if (srca & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(0)) == 0);
	SET_NFLG(((uae_s16)(0)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_word(srca, 0);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x1, 0, 1);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 20 (4/1) */
/* 6 0,0   */

/* CLR.L Dn */
void REGPARAM2 op_4280_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 18;
	CurrentInstrCycles = 6;  
	uae_s32 src = m68k_dreg(regs, srcreg);
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(0)) == 0);
	SET_NFLG(((uae_s32)(0)) < 0);
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		m68k_dreg(regs, srcreg) = (src & 0xffff0000);
		SET_VFLG(0);SET_ZFLG(1);SET_NFLG(0);SET_CFLG(0);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	m68k_dreg(regs, srcreg) = (0);
	do_cycles_ce000_internal(2);
	m68k_incpci(2);
	return;
}
/* 6 (1/0) */
/* 2 0,0   */

/* CLR.L (An) */
void REGPARAM2 op_4290_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 18;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(0)) == 0);
	SET_NFLG(((uae_s32)(0)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		SET_VFLG(0);SET_ZFLG(1);SET_NFLG(0);SET_CFLG(0);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	x_put_word(srca + 2, 0);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, srca + 2, 0x1, 0, 1);
		return;
	}
	x_put_word(srca, 0 >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, srca + 0, 0x1, 0 >> 16, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 20 (3/2) */
/* 2 0,0   */

/* CLR.L (An)+ */
void REGPARAM2 op_4298_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 18;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	m68k_areg(regs, srcreg) += 4;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(0)) == 0);
	SET_NFLG(((uae_s32)(0)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		SET_VFLG(0);SET_ZFLG(1);SET_NFLG(0);SET_CFLG(0);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	x_put_word(srca + 2, 0);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, srca + 2, 0x1, 0, 1);
		return;
	}
	x_put_word(srca, 0 >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, srca + 0, 0x1, 0 >> 16, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 20 (3/2) */
/* 2 0,0   */

/* CLR.L -(An) */
void REGPARAM2 op_42a0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 18;
	CurrentInstrCycles = 22; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - 4;
	do_cycles_ce000_internal(2);
	if (srca & 1) {
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	m68k_areg(regs, srcreg) = srca;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(0)) == 0);
	SET_NFLG(((uae_s32)(0)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		SET_VFLG(0);SET_ZFLG(1);SET_NFLG(0);SET_CFLG(0);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	x_put_word(srca + 2, 0);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, srca + 2, 0x1, 0, 1);
		return;
	}
	x_put_word(srca, 0 >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, srca + 0, 0x1, 0 >> 16, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 22 (3/2) */
/* 2 0,0   */

/* CLR.L (d16,An) */
void REGPARAM2 op_42a8_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 18;
	CurrentInstrCycles = 24; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(0)) == 0);
	SET_NFLG(((uae_s32)(0)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		SET_VFLG(0);SET_ZFLG(1);SET_NFLG(0);SET_CFLG(0);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	x_put_word(srca + 2, 0);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, srca + 2, 0x1, 0, 1);
		return;
	}
	x_put_word(srca, 0 >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, srca + 0, 0x1, 0 >> 16, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 24 (4/2) */
/* 4 0,0   */

/* CLR.L (d8,An,Xn) */
void REGPARAM2 op_42b0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 18;
	CurrentInstrCycles = 26; 
	uaecptr srca;
	do_cycles_ce000_internal(2);
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(0)) == 0);
	SET_NFLG(((uae_s32)(0)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		SET_VFLG(0);SET_ZFLG(1);SET_NFLG(0);SET_CFLG(0);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	x_put_word(srca + 2, 0);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, srca + 2, 0x1, 0, 1);
		return;
	}
	x_put_word(srca, 0 >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, srca + 0, 0x1, 0 >> 16, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 26 (4/2) */
/* 4 4,0   */

/* CLR.L (xxx).W */
void REGPARAM2 op_42b8_14_ff(uae_u32 opcode)
{
	OpcodeFamily = 18;
	CurrentInstrCycles = 24; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	if (srca & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(0)) == 0);
	SET_NFLG(((uae_s32)(0)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		SET_VFLG(0);SET_ZFLG(1);SET_NFLG(0);SET_CFLG(0);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	x_put_word(srca + 2, 0);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, srca + 2, 0x1, 0, 1);
		return;
	}
	x_put_word(srca, 0 >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, srca + 0, 0x1, 0 >> 16, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 24 (4/2) */
/* 4 0,0   */

/* CLR.L (xxx).L */
void REGPARAM2 op_42b9_14_ff(uae_u32 opcode)
{
	OpcodeFamily = 18;
	CurrentInstrCycles = 28; 
	uaecptr srca;
	srca = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	srca |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	if (srca & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(0)) == 0);
	SET_NFLG(((uae_s32)(0)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		SET_VFLG(0);SET_ZFLG(1);SET_NFLG(0);SET_CFLG(0);
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	x_put_word(srca + 2, 0);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, srca + 2, 0x1, 0, 1);
		return;
	}
	x_put_word(srca, 0 >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, srca + 0, 0x1, 0 >> 16, 1);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 28 (5/2) */
/* 6 0,0   */

/* NEG.B Dn */
void REGPARAM2 op_4400_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 15;
	CurrentInstrCycles = 4;  
	uae_s8 src = m68k_dreg(regs, srcreg);
	uae_u32 dst = ((uae_u8)(0)) - ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(0)) < 0;
	int flgn = ((uae_s8)(dst)) < 0;
	SET_ZFLG(((uae_s8)(dst)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u8)(src)) > ((uae_u8)(0)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((dst) & 0xff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 4 (1/0) */
/* 2 0,0   */

/* NEG.B (An) */
void REGPARAM2 op_4410_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 15;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	uae_u32 dst = ((uae_u8)(0)) - ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(0)) < 0;
	int flgn = ((uae_s8)(dst)) < 0;
	SET_ZFLG(((uae_s8)(dst)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u8)(src)) > ((uae_u8)(0)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_byte(srca, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, dst, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 12 (2/1) */
/* 2 0,0   */

/* NEG.B (An)+ */
void REGPARAM2 op_4418_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 15;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
	uae_u32 dst = ((uae_u8)(0)) - ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(0)) < 0;
	int flgn = ((uae_s8)(dst)) < 0;
	SET_ZFLG(((uae_s8)(dst)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u8)(src)) > ((uae_u8)(0)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_byte(srca, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, dst, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 12 (2/1) */
/* 2 0,0   */

/* NEG.B -(An) */
void REGPARAM2 op_4420_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 15;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
	do_cycles_ce000_internal(2);
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	m68k_areg(regs, srcreg) = srca;
	uae_u32 dst = ((uae_u8)(0)) - ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(0)) < 0;
	int flgn = ((uae_s8)(dst)) < 0;
	SET_ZFLG(((uae_s8)(dst)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u8)(src)) > ((uae_u8)(0)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_byte(srca, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, dst, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 14 (2/1) */
/* 2 0,0   */

/* NEG.B (d16,An) */
void REGPARAM2 op_4428_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 15;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	uae_u32 dst = ((uae_u8)(0)) - ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(0)) < 0;
	int flgn = ((uae_s8)(dst)) < 0;
	SET_ZFLG(((uae_s8)(dst)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u8)(src)) > ((uae_u8)(0)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_byte(srca, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, dst, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* NEG.B (d8,An,Xn) */
void REGPARAM2 op_4430_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 15;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	do_cycles_ce000_internal(2);
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	uae_u32 dst = ((uae_u8)(0)) - ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(0)) < 0;
	int flgn = ((uae_s8)(dst)) < 0;
	SET_ZFLG(((uae_s8)(dst)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u8)(src)) > ((uae_u8)(0)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_byte(srca, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, dst, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 18 (3/1) */
/* 4 4,0   */

/* NEG.B (xxx).W */
void REGPARAM2 op_4438_14_ff(uae_u32 opcode)
{
	OpcodeFamily = 15;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	uae_u32 dst = ((uae_u8)(0)) - ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(0)) < 0;
	int flgn = ((uae_s8)(dst)) < 0;
	SET_ZFLG(((uae_s8)(dst)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u8)(src)) > ((uae_u8)(0)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_byte(srca, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, dst, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* NEG.B (xxx).L */
void REGPARAM2 op_4439_14_ff(uae_u32 opcode)
{
	OpcodeFamily = 15;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	srca = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	srca |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	uae_u32 dst = ((uae_u8)(0)) - ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(0)) < 0;
	int flgn = ((uae_s8)(dst)) < 0;
	SET_ZFLG(((uae_s8)(dst)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u8)(src)) > ((uae_u8)(0)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_byte(srca, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, dst, 1);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 20 (4/1) */
/* 6 0,0   */

/* NEG.W Dn */
void REGPARAM2 op_4440_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 15;
	CurrentInstrCycles = 4;  
	uae_s16 src = m68k_dreg(regs, srcreg);
	uae_u32 dst = ((uae_u16)(0)) - ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(0)) < 0;
	int flgn = ((uae_s16)(dst)) < 0;
	SET_ZFLG(((uae_s16)(dst)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u16)(src)) > ((uae_u16)(0)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | ((dst) & 0xffff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 4 (1/0) */
/* 2 0,0   */

/* NEG.W (An) */
void REGPARAM2 op_4450_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 15;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	uae_u32 dst = ((uae_u16)(0)) - ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(0)) < 0;
	int flgn = ((uae_s16)(dst)) < 0;
	SET_ZFLG(((uae_s16)(dst)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u16)(src)) > ((uae_u16)(0)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_word(srca, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x1, dst, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 12 (2/1) */
/* 2 0,0   */

/* NEG.W (An)+ */
void REGPARAM2 op_4458_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 15;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) += 2 + 0;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	m68k_areg(regs, srcreg) += 2;
	uae_u32 dst = ((uae_u16)(0)) - ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(0)) < 0;
	int flgn = ((uae_s16)(dst)) < 0;
	SET_ZFLG(((uae_s16)(dst)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u16)(src)) > ((uae_u16)(0)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_word(srca, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x1, dst, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 12 (2/1) */
/* 2 0,0   */

/* NEG.W -(An) */
void REGPARAM2 op_4460_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 15;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - 2;
	do_cycles_ce000_internal(2);
	if (srca & 1) {
		m68k_incpci(4);
		m68k_areg(regs, srcreg) = srca;
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	m68k_areg(regs, srcreg) = srca;
	uae_u32 dst = ((uae_u16)(0)) - ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(0)) < 0;
	int flgn = ((uae_s16)(dst)) < 0;
	SET_ZFLG(((uae_s16)(dst)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u16)(src)) > ((uae_u16)(0)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_word(srca, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x1, dst, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 14 (2/1) */
/* 2 0,0   */

/* NEG.W (d16,An) */
void REGPARAM2 op_4468_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 15;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	uae_u32 dst = ((uae_u16)(0)) - ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(0)) < 0;
	int flgn = ((uae_s16)(dst)) < 0;
	SET_ZFLG(((uae_s16)(dst)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u16)(src)) > ((uae_u16)(0)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_word(srca, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x1, dst, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* NEG.W (d8,An,Xn) */
void REGPARAM2 op_4470_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 15;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	do_cycles_ce000_internal(2);
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	uae_u32 dst = ((uae_u16)(0)) - ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(0)) < 0;
	int flgn = ((uae_s16)(dst)) < 0;
	SET_ZFLG(((uae_s16)(dst)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u16)(src)) > ((uae_u16)(0)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_word(srca, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x1, dst, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 18 (3/1) */
/* 4 4,0   */

/* NEG.W (xxx).W */
void REGPARAM2 op_4478_14_ff(uae_u32 opcode)
{
	OpcodeFamily = 15;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	if (srca & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	uae_u32 dst = ((uae_u16)(0)) - ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(0)) < 0;
	int flgn = ((uae_s16)(dst)) < 0;
	SET_ZFLG(((uae_s16)(dst)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u16)(src)) > ((uae_u16)(0)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_word(srca, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x1, dst, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* NEG.W (xxx).L */
void REGPARAM2 op_4479_14_ff(uae_u32 opcode)
{
	OpcodeFamily = 15;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	srca = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	srca |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	if (srca & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	uae_u32 dst = ((uae_u16)(0)) - ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(0)) < 0;
	int flgn = ((uae_s16)(dst)) < 0;
	SET_ZFLG(((uae_s16)(dst)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u16)(src)) > ((uae_u16)(0)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_word(srca, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x1, dst, 1);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 20 (4/1) */
/* 6 0,0   */

/* NEG.L Dn */
void REGPARAM2 op_4480_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 15;
	CurrentInstrCycles = 6;  
	uae_s32 src = m68k_dreg(regs, srcreg);
	uae_u32 dst = ((uae_u32)(0)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(0)) < 0;
	int flgn = ((uae_s32)(dst)) < 0;
	SET_ZFLG(((uae_s32)(dst)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(0)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		dreg_68000_long_replace_low(srcreg, dst);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	m68k_dreg(regs, srcreg) = (dst);
	do_cycles_ce000_internal(2);
	m68k_incpci(2);
	return;
}
/* 6 (1/0) */
/* 2 0,0   */

/* NEG.L (An) */
void REGPARAM2 op_4490_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 15;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	uae_u32 dst = ((uae_u32)(0)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(0)) < 0;
	int flgn = ((uae_s32)(dst)) < 0;
	SET_ZFLG(((uae_s32)(dst)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(0)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		int bflgs = ((uae_s16)(src)) < 0;
		int bflgo = ((uae_s16)(0)) < 0;
		int bflgn = ((uae_s16)(dst)) < 0;
		SET_ZFLG(((uae_s16)(dst)) == 0);
		SET_VFLG((bflgs ^ bflgo) & (bflgn ^ bflgo));
		SET_CFLG(((uae_u16)(src)) > ((uae_u16)(0)));
		SET_NFLG(bflgn != 0);
		SET_XFLG(GET_CFLG());
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	x_put_word(srca + 2, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, srca + 2, 0x1, dst, 1);
		return;
	}
	x_put_word(srca, dst >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, srca + 0, 0x1, dst >> 16, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 20 (3/2) */
/* 2 0,0   */

/* NEG.L (An)+ */
void REGPARAM2 op_4498_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 15;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	m68k_areg(regs, srcreg) += 4;
	uae_u32 dst = ((uae_u32)(0)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(0)) < 0;
	int flgn = ((uae_s32)(dst)) < 0;
	SET_ZFLG(((uae_s32)(dst)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(0)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		int bflgs = ((uae_s16)(src)) < 0;
		int bflgo = ((uae_s16)(0)) < 0;
		int bflgn = ((uae_s16)(dst)) < 0;
		SET_ZFLG(((uae_s16)(dst)) == 0);
		SET_VFLG((bflgs ^ bflgo) & (bflgn ^ bflgo));
		SET_CFLG(((uae_u16)(src)) > ((uae_u16)(0)));
		SET_NFLG(bflgn != 0);
		SET_XFLG(GET_CFLG());
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	x_put_word(srca + 2, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, srca + 2, 0x1, dst, 1);
		return;
	}
	x_put_word(srca, dst >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, srca + 0, 0x1, dst >> 16, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 20 (3/2) */
/* 2 0,0   */

/* NEG.L -(An) */
void REGPARAM2 op_44a0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 15;
	CurrentInstrCycles = 22; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - 4;
	do_cycles_ce000_internal(2);
	if (srca & 1) {
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	m68k_areg(regs, srcreg) = srca;
	uae_u32 dst = ((uae_u32)(0)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(0)) < 0;
	int flgn = ((uae_s32)(dst)) < 0;
	SET_ZFLG(((uae_s32)(dst)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(0)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		int bflgs = ((uae_s16)(src)) < 0;
		int bflgo = ((uae_s16)(0)) < 0;
		int bflgn = ((uae_s16)(dst)) < 0;
		SET_ZFLG(((uae_s16)(dst)) == 0);
		SET_VFLG((bflgs ^ bflgo) & (bflgn ^ bflgo));
		SET_CFLG(((uae_u16)(src)) > ((uae_u16)(0)));
		SET_NFLG(bflgn != 0);
		SET_XFLG(GET_CFLG());
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	x_put_word(srca + 2, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, srca + 2, 0x1, dst, 1);
		return;
	}
	x_put_word(srca, dst >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, srca + 0, 0x1, dst >> 16, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 22 (3/2) */
/* 2 0,0   */

/* NEG.L (d16,An) */
void REGPARAM2 op_44a8_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 15;
	CurrentInstrCycles = 24; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	uae_u32 dst = ((uae_u32)(0)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(0)) < 0;
	int flgn = ((uae_s32)(dst)) < 0;
	SET_ZFLG(((uae_s32)(dst)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(0)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		int bflgs = ((uae_s16)(src)) < 0;
		int bflgo = ((uae_s16)(0)) < 0;
		int bflgn = ((uae_s16)(dst)) < 0;
		SET_ZFLG(((uae_s16)(dst)) == 0);
		SET_VFLG((bflgs ^ bflgo) & (bflgn ^ bflgo));
		SET_CFLG(((uae_u16)(src)) > ((uae_u16)(0)));
		SET_NFLG(bflgn != 0);
		SET_XFLG(GET_CFLG());
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	x_put_word(srca + 2, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, srca + 2, 0x1, dst, 1);
		return;
	}
	x_put_word(srca, dst >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, srca + 0, 0x1, dst >> 16, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 24 (4/2) */
/* 4 0,0   */

/* NEG.L (d8,An,Xn) */
void REGPARAM2 op_44b0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 15;
	CurrentInstrCycles = 26; 
	uaecptr srca;
	do_cycles_ce000_internal(2);
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	uae_u32 dst = ((uae_u32)(0)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(0)) < 0;
	int flgn = ((uae_s32)(dst)) < 0;
	SET_ZFLG(((uae_s32)(dst)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(0)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		int bflgs = ((uae_s16)(src)) < 0;
		int bflgo = ((uae_s16)(0)) < 0;
		int bflgn = ((uae_s16)(dst)) < 0;
		SET_ZFLG(((uae_s16)(dst)) == 0);
		SET_VFLG((bflgs ^ bflgo) & (bflgn ^ bflgo));
		SET_CFLG(((uae_u16)(src)) > ((uae_u16)(0)));
		SET_NFLG(bflgn != 0);
		SET_XFLG(GET_CFLG());
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	x_put_word(srca + 2, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, srca + 2, 0x1, dst, 1);
		return;
	}
	x_put_word(srca, dst >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, srca + 0, 0x1, dst >> 16, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 26 (4/2) */
/* 4 4,0   */

/* NEG.L (xxx).W */
void REGPARAM2 op_44b8_14_ff(uae_u32 opcode)
{
	OpcodeFamily = 15;
	CurrentInstrCycles = 24; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	if (srca & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	uae_u32 dst = ((uae_u32)(0)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(0)) < 0;
	int flgn = ((uae_s32)(dst)) < 0;
	SET_ZFLG(((uae_s32)(dst)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(0)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		int bflgs = ((uae_s16)(src)) < 0;
		int bflgo = ((uae_s16)(0)) < 0;
		int bflgn = ((uae_s16)(dst)) < 0;
		SET_ZFLG(((uae_s16)(dst)) == 0);
		SET_VFLG((bflgs ^ bflgo) & (bflgn ^ bflgo));
		SET_CFLG(((uae_u16)(src)) > ((uae_u16)(0)));
		SET_NFLG(bflgn != 0);
		SET_XFLG(GET_CFLG());
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	x_put_word(srca + 2, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, srca + 2, 0x1, dst, 1);
		return;
	}
	x_put_word(srca, dst >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, srca + 0, 0x1, dst >> 16, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 24 (4/2) */
/* 4 0,0   */

/* NEG.L (xxx).L */
void REGPARAM2 op_44b9_14_ff(uae_u32 opcode)
{
	OpcodeFamily = 15;
	CurrentInstrCycles = 28; 
	uaecptr srca;
	srca = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	srca |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	if (srca & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	uae_u32 dst = ((uae_u32)(0)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(0)) < 0;
	int flgn = ((uae_s32)(dst)) < 0;
	SET_ZFLG(((uae_s32)(dst)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(0)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		int bflgs = ((uae_s16)(src)) < 0;
		int bflgo = ((uae_s16)(0)) < 0;
		int bflgn = ((uae_s16)(dst)) < 0;
		SET_ZFLG(((uae_s16)(dst)) == 0);
		SET_VFLG((bflgs ^ bflgo) & (bflgn ^ bflgo));
		SET_CFLG(((uae_u16)(src)) > ((uae_u16)(0)));
		SET_NFLG(bflgn != 0);
		SET_XFLG(GET_CFLG());
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	x_put_word(srca + 2, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, srca + 2, 0x1, dst, 1);
		return;
	}
	x_put_word(srca, dst >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, srca + 0, 0x1, dst >> 16, 1);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 28 (5/2) */
/* 6 0,0   */

/* MV2SR.B Dn */
void REGPARAM2 op_44c0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 33;
	CurrentInstrCycles = 12; 
	uae_s16 src = m68k_dreg(regs, srcreg);
	int t1 = regs.t1;
	do_cycles_ce000_internal(4);
	MakeSR();
	regs.sr &= 0xFF00;
	regs.sr |= src & 0xFF;
	MakeFromSR();
	m68k_incpci(2);
	get_word_ce000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, 0);
		return;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	if(t1) opcode |= 0x10000;
	ipl_fetch_next();
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 12 (2/0) */
/* 2 0,0   */

/* MV2SR.B (An) */
void REGPARAM2 op_44d0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 33;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	int t1 = regs.t1;
	do_cycles_ce000_internal(4);
	MakeSR();
	regs.sr &= 0xFF00;
	regs.sr |= src & 0xFF;
	MakeFromSR();
	m68k_incpci(2);
	get_word_ce000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, 0);
		return;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	if(t1) opcode |= 0x10000;
	ipl_fetch_next();
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 16 (3/0) */
/* 2 0,0   */

/* MV2SR.B (An)+ */
void REGPARAM2 op_44d8_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 33;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) += 2 + 0;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	m68k_areg(regs, srcreg) += 2;
	int t1 = regs.t1;
	do_cycles_ce000_internal(4);
	MakeSR();
	regs.sr &= 0xFF00;
	regs.sr |= src & 0xFF;
	MakeFromSR();
	m68k_incpci(2);
	get_word_ce000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, 0);
		return;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	if(t1) opcode |= 0x10000;
	ipl_fetch_next();
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 16 (3/0) */
/* 2 0,0   */

/* MV2SR.B -(An) */
void REGPARAM2 op_44e0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 33;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - 2;
	do_cycles_ce000_internal(2);
	if (srca & 1) {
		m68k_incpci(4);
		m68k_areg(regs, srcreg) = srca;
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	m68k_areg(regs, srcreg) = srca;
	int t1 = regs.t1;
	do_cycles_ce000_internal(4);
	MakeSR();
	regs.sr &= 0xFF00;
	regs.sr |= src & 0xFF;
	MakeFromSR();
	m68k_incpci(2);
	get_word_ce000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, 0);
		return;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	if(t1) opcode |= 0x10000;
	ipl_fetch_next();
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 18 (3/0) */
/* 2 0,0   */

/* MV2SR.B (d16,An) */
void REGPARAM2 op_44e8_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 33;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	int t1 = regs.t1;
	do_cycles_ce000_internal(4);
	MakeSR();
	regs.sr &= 0xFF00;
	regs.sr |= src & 0xFF;
	MakeFromSR();
	m68k_incpci(4);
	get_word_ce000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, 0);
		return;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	if(t1) opcode |= 0x10000;
	ipl_fetch_next();
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 20 (4/0) */
/* 4 0,0   */

/* MV2SR.B (d8,An,Xn) */
void REGPARAM2 op_44f0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 33;
	CurrentInstrCycles = 22; 
	uaecptr srca;
	do_cycles_ce000_internal(2);
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	int t1 = regs.t1;
	do_cycles_ce000_internal(4);
	MakeSR();
	regs.sr &= 0xFF00;
	regs.sr |= src & 0xFF;
	MakeFromSR();
	m68k_incpci(4);
	get_word_ce000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, 0);
		return;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	if(t1) opcode |= 0x10000;
	ipl_fetch_next();
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 22 (4/0) */
/* 4 4,0   */

/* MV2SR.B (xxx).W */
void REGPARAM2 op_44f8_14_ff(uae_u32 opcode)
{
	OpcodeFamily = 33;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	if (srca & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	int t1 = regs.t1;
	do_cycles_ce000_internal(4);
	MakeSR();
	regs.sr &= 0xFF00;
	regs.sr |= src & 0xFF;
	MakeFromSR();
	m68k_incpci(4);
	get_word_ce000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, 0);
		return;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	if(t1) opcode |= 0x10000;
	ipl_fetch_next();
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 20 (4/0) */
/* 4 0,0   */

/* MV2SR.B (xxx).L */
void REGPARAM2 op_44f9_14_ff(uae_u32 opcode)
{
	OpcodeFamily = 33;
	CurrentInstrCycles = 24; 
	uaecptr srca;
	srca = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	srca |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	if (srca & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	int t1 = regs.t1;
	do_cycles_ce000_internal(4);
	MakeSR();
	regs.sr &= 0xFF00;
	regs.sr |= src & 0xFF;
	MakeFromSR();
	m68k_incpci(6);
	get_word_ce000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, 0);
		return;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	if(t1) opcode |= 0x10000;
	ipl_fetch_next();
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 24 (5/0) */
/* 6 0,0   */

/* MV2SR.B (d16,PC) */
void REGPARAM2 op_44fa_14_ff(uae_u32 opcode)
{
	OpcodeFamily = 33;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	srca = m68k_getpci() + 2;
	srca += (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 2);
		return;
	}
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return;
	}
	int t1 = regs.t1;
	do_cycles_ce000_internal(4);
	MakeSR();
	regs.sr &= 0xFF00;
	regs.sr |= src & 0xFF;
	MakeFromSR();
	m68k_incpci(4);
	get_word_ce000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, 0);
		return;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	if(t1) opcode |= 0x10000;
	ipl_fetch_next();
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 20 (4/0) */
/* 4 0,0   */

/* MV2SR.B (d8,PC,Xn) */
void REGPARAM2 op_44fb_14_ff(uae_u32 opcode)
{
	OpcodeFamily = 33;
	CurrentInstrCycles = 22; 
	uaecptr srca;
	uaecptr tmppc = m68k_getpci() + 2;
	do_cycles_ce000_internal(2);
	srca = get_disp_ea_000(tmppc, get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 2);
		return;
	}
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return;
	}
	int t1 = regs.t1;
	do_cycles_ce000_internal(4);
	MakeSR();
	regs.sr &= 0xFF00;
	regs.sr |= src & 0xFF;
	MakeFromSR();
	m68k_incpci(4);
	get_word_ce000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, 0);
		return;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	if(t1) opcode |= 0x10000;
	ipl_fetch_next();
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 22 (4/0) */
/* 4 4,0   */

/* MV2SR.B #<data>.B */
void REGPARAM2 op_44fc_14_ff(uae_u32 opcode)
{
	OpcodeFamily = 33;
	CurrentInstrCycles = 16; 
	uae_s16 src = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	int t1 = regs.t1;
	do_cycles_ce000_internal(4);
	MakeSR();
	regs.sr &= 0xFF00;
	regs.sr |= src & 0xFF;
	MakeFromSR();
	m68k_incpci(4);
	get_word_ce000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, 0);
		return;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	if(t1) opcode |= 0x10000;
	ipl_fetch_next();
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 16 (3/0) */
/* 4 0,0   */

/* NOT.B Dn */
void REGPARAM2 op_4600_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 19;
	CurrentInstrCycles = 4;  
	uae_s8 src = m68k_dreg(regs, srcreg);
	uae_u32 dst = ~src;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(dst)) == 0);
	SET_NFLG(((uae_s8)(dst)) < 0);
	m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((dst) & 0xff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 4 (1/0) */
/* 2 0,0   */

/* NOT.B (An) */
void REGPARAM2 op_4610_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 19;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	uae_u32 dst = ~src;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(dst)) == 0);
	SET_NFLG(((uae_s8)(dst)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_byte(srca, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, dst, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 12 (2/1) */
/* 2 0,0   */

/* NOT.B (An)+ */
void REGPARAM2 op_4618_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 19;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
	uae_u32 dst = ~src;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(dst)) == 0);
	SET_NFLG(((uae_s8)(dst)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_byte(srca, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, dst, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 12 (2/1) */
/* 2 0,0   */

/* NOT.B -(An) */
void REGPARAM2 op_4620_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 19;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
	do_cycles_ce000_internal(2);
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	m68k_areg(regs, srcreg) = srca;
	uae_u32 dst = ~src;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(dst)) == 0);
	SET_NFLG(((uae_s8)(dst)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_byte(srca, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, dst, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 14 (2/1) */
/* 2 0,0   */

/* NOT.B (d16,An) */
void REGPARAM2 op_4628_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 19;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	uae_u32 dst = ~src;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(dst)) == 0);
	SET_NFLG(((uae_s8)(dst)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_byte(srca, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, dst, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* NOT.B (d8,An,Xn) */
void REGPARAM2 op_4630_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 19;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	do_cycles_ce000_internal(2);
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	uae_u32 dst = ~src;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(dst)) == 0);
	SET_NFLG(((uae_s8)(dst)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_byte(srca, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, dst, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 18 (3/1) */
/* 4 4,0   */

/* NOT.B (xxx).W */
void REGPARAM2 op_4638_14_ff(uae_u32 opcode)
{
	OpcodeFamily = 19;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	uae_u32 dst = ~src;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(dst)) == 0);
	SET_NFLG(((uae_s8)(dst)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_byte(srca, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, dst, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* NOT.B (xxx).L */
void REGPARAM2 op_4639_14_ff(uae_u32 opcode)
{
	OpcodeFamily = 19;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	srca = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	srca |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	uae_u32 dst = ~src;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(dst)) == 0);
	SET_NFLG(((uae_s8)(dst)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_byte(srca, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, dst, 1);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 20 (4/1) */
/* 6 0,0   */

/* NOT.W Dn */
void REGPARAM2 op_4640_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 19;
	CurrentInstrCycles = 4;  
	uae_s16 src = m68k_dreg(regs, srcreg);
	uae_u32 dst = ~src;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(dst)) == 0);
	SET_NFLG(((uae_s16)(dst)) < 0);
	m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | ((dst) & 0xffff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 4 (1/0) */
/* 2 0,0   */

/* NOT.W (An) */
void REGPARAM2 op_4650_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 19;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	uae_u32 dst = ~src;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(dst)) == 0);
	SET_NFLG(((uae_s16)(dst)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_word(srca, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x1, dst, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 12 (2/1) */
/* 2 0,0   */

/* NOT.W (An)+ */
void REGPARAM2 op_4658_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 19;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) += 2 + 0;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	m68k_areg(regs, srcreg) += 2;
	uae_u32 dst = ~src;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(dst)) == 0);
	SET_NFLG(((uae_s16)(dst)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_word(srca, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x1, dst, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 12 (2/1) */
/* 2 0,0   */

/* NOT.W -(An) */
void REGPARAM2 op_4660_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 19;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - 2;
	do_cycles_ce000_internal(2);
	if (srca & 1) {
		m68k_incpci(4);
		m68k_areg(regs, srcreg) = srca;
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	m68k_areg(regs, srcreg) = srca;
	uae_u32 dst = ~src;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(dst)) == 0);
	SET_NFLG(((uae_s16)(dst)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_word(srca, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x1, dst, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 14 (2/1) */
/* 2 0,0   */

/* NOT.W (d16,An) */
void REGPARAM2 op_4668_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 19;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	uae_u32 dst = ~src;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(dst)) == 0);
	SET_NFLG(((uae_s16)(dst)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_word(srca, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x1, dst, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* NOT.W (d8,An,Xn) */
void REGPARAM2 op_4670_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 19;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	do_cycles_ce000_internal(2);
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	uae_u32 dst = ~src;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(dst)) == 0);
	SET_NFLG(((uae_s16)(dst)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_word(srca, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x1, dst, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 18 (3/1) */
/* 4 4,0   */

/* NOT.W (xxx).W */
void REGPARAM2 op_4678_14_ff(uae_u32 opcode)
{
	OpcodeFamily = 19;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	if (srca & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	uae_u32 dst = ~src;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(dst)) == 0);
	SET_NFLG(((uae_s16)(dst)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_word(srca, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x1, dst, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* NOT.W (xxx).L */
void REGPARAM2 op_4679_14_ff(uae_u32 opcode)
{
	OpcodeFamily = 19;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	srca = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	srca |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	if (srca & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	uae_u32 dst = ~src;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(dst)) == 0);
	SET_NFLG(((uae_s16)(dst)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_word(srca, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x1, dst, 1);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 20 (4/1) */
/* 6 0,0   */

/* NOT.L Dn */
void REGPARAM2 op_4680_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 19;
	CurrentInstrCycles = 6;  
	uae_s32 src = m68k_dreg(regs, srcreg);
	uae_u32 dst = ~src;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(dst)) == 0);
	SET_NFLG(((uae_s32)(dst)) < 0);
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		dreg_68000_long_replace_low(srcreg, dst);
		SET_VFLG(0);SET_ZFLG(!dst);
		SET_NFLG(dst & 0x80000000);
		SET_CFLG(0);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	m68k_dreg(regs, srcreg) = (dst);
	do_cycles_ce000_internal(2);
	m68k_incpci(2);
	return;
}
/* 6 (1/0) */
/* 2 0,0   */

/* NOT.L (An) */
void REGPARAM2 op_4690_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 19;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	uae_u32 dst = ~src;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(dst)) == 0);
	SET_NFLG(((uae_s32)(dst)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		SET_VFLG(0);
		SET_ZFLG(!(dst & 0xffff));
		SET_NFLG(dst & 0x8000);
		SET_CFLG(0);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	x_put_word(srca + 2, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, srca + 2, 0x1, dst, 1);
		return;
	}
	x_put_word(srca, dst >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, srca + 0, 0x1, dst >> 16, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 20 (3/2) */
/* 2 0,0   */

/* NOT.L (An)+ */
void REGPARAM2 op_4698_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 19;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	m68k_areg(regs, srcreg) += 4;
	uae_u32 dst = ~src;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(dst)) == 0);
	SET_NFLG(((uae_s32)(dst)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		SET_VFLG(0);
		SET_ZFLG(!(dst & 0xffff));
		SET_NFLG(dst & 0x8000);
		SET_CFLG(0);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	x_put_word(srca + 2, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, srca + 2, 0x1, dst, 1);
		return;
	}
	x_put_word(srca, dst >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, srca + 0, 0x1, dst >> 16, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 20 (3/2) */
/* 2 0,0   */

/* NOT.L -(An) */
void REGPARAM2 op_46a0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 19;
	CurrentInstrCycles = 22; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - 4;
	do_cycles_ce000_internal(2);
	if (srca & 1) {
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	m68k_areg(regs, srcreg) = srca;
	uae_u32 dst = ~src;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(dst)) == 0);
	SET_NFLG(((uae_s32)(dst)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		SET_VFLG(0);
		SET_ZFLG(!(dst & 0xffff));
		SET_NFLG(dst & 0x8000);
		SET_CFLG(0);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	x_put_word(srca + 2, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, srca + 2, 0x1, dst, 1);
		return;
	}
	x_put_word(srca, dst >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, srca + 0, 0x1, dst >> 16, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 22 (3/2) */
/* 2 0,0   */

/* NOT.L (d16,An) */
void REGPARAM2 op_46a8_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 19;
	CurrentInstrCycles = 24; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	uae_u32 dst = ~src;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(dst)) == 0);
	SET_NFLG(((uae_s32)(dst)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		SET_VFLG(0);
		SET_ZFLG(!(dst & 0xffff));
		SET_NFLG(dst & 0x8000);
		SET_CFLG(0);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	x_put_word(srca + 2, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, srca + 2, 0x1, dst, 1);
		return;
	}
	x_put_word(srca, dst >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, srca + 0, 0x1, dst >> 16, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 24 (4/2) */
/* 4 0,0   */

/* NOT.L (d8,An,Xn) */
void REGPARAM2 op_46b0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 19;
	CurrentInstrCycles = 26; 
	uaecptr srca;
	do_cycles_ce000_internal(2);
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	uae_u32 dst = ~src;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(dst)) == 0);
	SET_NFLG(((uae_s32)(dst)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		SET_VFLG(0);
		SET_ZFLG(!(dst & 0xffff));
		SET_NFLG(dst & 0x8000);
		SET_CFLG(0);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	x_put_word(srca + 2, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, srca + 2, 0x1, dst, 1);
		return;
	}
	x_put_word(srca, dst >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, srca + 0, 0x1, dst >> 16, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 26 (4/2) */
/* 4 4,0   */

/* NOT.L (xxx).W */
void REGPARAM2 op_46b8_14_ff(uae_u32 opcode)
{
	OpcodeFamily = 19;
	CurrentInstrCycles = 24; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	if (srca & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	uae_u32 dst = ~src;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(dst)) == 0);
	SET_NFLG(((uae_s32)(dst)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		SET_VFLG(0);
		SET_ZFLG(!(dst & 0xffff));
		SET_NFLG(dst & 0x8000);
		SET_CFLG(0);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	x_put_word(srca + 2, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, srca + 2, 0x1, dst, 1);
		return;
	}
	x_put_word(srca, dst >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, srca + 0, 0x1, dst >> 16, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 24 (4/2) */
/* 4 0,0   */

/* NOT.L (xxx).L */
void REGPARAM2 op_46b9_14_ff(uae_u32 opcode)
{
	OpcodeFamily = 19;
	CurrentInstrCycles = 28; 
	uaecptr srca;
	srca = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	srca |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	if (srca & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	uae_u32 dst = ~src;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(dst)) == 0);
	SET_NFLG(((uae_s32)(dst)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		SET_VFLG(0);
		SET_ZFLG(!(dst & 0xffff));
		SET_NFLG(dst & 0x8000);
		SET_CFLG(0);
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	x_put_word(srca + 2, dst);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, srca + 2, 0x1, dst, 1);
		return;
	}
	x_put_word(srca, dst >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, srca + 0, 0x1, dst >> 16, 1);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 28 (5/2) */
/* 6 0,0   */

/* MV2SR.W Dn */
void REGPARAM2 op_46c0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 33;
	CurrentInstrCycles = 12; 
	if (!regs.s) {
		Exception(8);
		return;
	}
	uae_s16 src = m68k_dreg(regs, srcreg);
	int t1 = regs.t1;
	do_cycles_ce000_internal(4);
	regs.sr = src;
	MakeFromSR();
	m68k_incpci(2);
	get_word_ce000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, 0);
		return;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	if(t1) opcode |= 0x10000;
	ipl_fetch_next();
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 12 (2/0) */
/* 2 0,0   */

/* MV2SR.W (An) */
void REGPARAM2 op_46d0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 33;
	CurrentInstrCycles = 16; 
	if (!regs.s) {
		Exception(8);
		return;
	}
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	int t1 = regs.t1;
	do_cycles_ce000_internal(4);
	regs.sr = src;
	MakeFromSR();
	m68k_incpci(2);
	get_word_ce000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, 0);
		return;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	if(t1) opcode |= 0x10000;
	ipl_fetch_next();
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 16 (3/0) */
/* 2 0,0   */

/* MV2SR.W (An)+ */
void REGPARAM2 op_46d8_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 33;
	CurrentInstrCycles = 16; 
	if (!regs.s) {
		Exception(8);
		return;
	}
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) += 2 + 0;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	m68k_areg(regs, srcreg) += 2;
	int t1 = regs.t1;
	do_cycles_ce000_internal(4);
	regs.sr = src;
	MakeFromSR();
	m68k_incpci(2);
	get_word_ce000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, 0);
		return;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	if(t1) opcode |= 0x10000;
	ipl_fetch_next();
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 16 (3/0) */
/* 2 0,0   */

/* MV2SR.W -(An) */
void REGPARAM2 op_46e0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 33;
	CurrentInstrCycles = 18; 
	if (!regs.s) {
		Exception(8);
		return;
	}
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - 2;
	do_cycles_ce000_internal(2);
	if (srca & 1) {
		m68k_incpci(4);
		m68k_areg(regs, srcreg) = srca;
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	m68k_areg(regs, srcreg) = srca;
	int t1 = regs.t1;
	do_cycles_ce000_internal(4);
	regs.sr = src;
	MakeFromSR();
	m68k_incpci(2);
	get_word_ce000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, 0);
		return;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	if(t1) opcode |= 0x10000;
	ipl_fetch_next();
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 18 (3/0) */
/* 2 0,0   */

/* MV2SR.W (d16,An) */
void REGPARAM2 op_46e8_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 33;
	CurrentInstrCycles = 20; 
	if (!regs.s) {
		Exception(8);
		return;
	}
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	int t1 = regs.t1;
	do_cycles_ce000_internal(4);
	regs.sr = src;
	MakeFromSR();
	m68k_incpci(4);
	get_word_ce000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, 0);
		return;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	if(t1) opcode |= 0x10000;
	ipl_fetch_next();
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 20 (4/0) */
/* 4 0,0   */

/* MV2SR.W (d8,An,Xn) */
void REGPARAM2 op_46f0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 33;
	CurrentInstrCycles = 22; 
	if (!regs.s) {
		Exception(8);
		return;
	}
	uaecptr srca;
	do_cycles_ce000_internal(2);
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	int t1 = regs.t1;
	do_cycles_ce000_internal(4);
	regs.sr = src;
	MakeFromSR();
	m68k_incpci(4);
	get_word_ce000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, 0);
		return;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	if(t1) opcode |= 0x10000;
	ipl_fetch_next();
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 22 (4/0) */
/* 4 4,0   */

/* MV2SR.W (xxx).W */
void REGPARAM2 op_46f8_14_ff(uae_u32 opcode)
{
	OpcodeFamily = 33;
	CurrentInstrCycles = 20; 
	if (!regs.s) {
		Exception(8);
		return;
	}
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	if (srca & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	int t1 = regs.t1;
	do_cycles_ce000_internal(4);
	regs.sr = src;
	MakeFromSR();
	m68k_incpci(4);
	get_word_ce000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, 0);
		return;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	if(t1) opcode |= 0x10000;
	ipl_fetch_next();
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 20 (4/0) */
/* 4 0,0   */

/* MV2SR.W (xxx).L */
void REGPARAM2 op_46f9_14_ff(uae_u32 opcode)
{
	OpcodeFamily = 33;
	CurrentInstrCycles = 24; 
	if (!regs.s) {
		Exception(8);
		return;
	}
	uaecptr srca;
	srca = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	srca |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	if (srca & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	int t1 = regs.t1;
	do_cycles_ce000_internal(4);
	regs.sr = src;
	MakeFromSR();
	m68k_incpci(6);
	get_word_ce000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, 0);
		return;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	if(t1) opcode |= 0x10000;
	ipl_fetch_next();
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 24 (5/0) */
/* 6 0,0   */

/* MV2SR.W (d16,PC) */
void REGPARAM2 op_46fa_14_ff(uae_u32 opcode)
{
	OpcodeFamily = 33;
	CurrentInstrCycles = 20; 
	if (!regs.s) {
		Exception(8);
		return;
	}
	uaecptr srca;
	srca = m68k_getpci() + 2;
	srca += (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 2);
		return;
	}
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return;
	}
	int t1 = regs.t1;
	do_cycles_ce000_internal(4);
	regs.sr = src;
	MakeFromSR();
	m68k_incpci(4);
	get_word_ce000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, 0);
		return;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	if(t1) opcode |= 0x10000;
	ipl_fetch_next();
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 20 (4/0) */
/* 4 0,0   */

/* MV2SR.W (d8,PC,Xn) */
void REGPARAM2 op_46fb_14_ff(uae_u32 opcode)
{
	OpcodeFamily = 33;
	CurrentInstrCycles = 22; 
	if (!regs.s) {
		Exception(8);
		return;
	}
	uaecptr srca;
	uaecptr tmppc = m68k_getpci() + 2;
	do_cycles_ce000_internal(2);
	srca = get_disp_ea_000(tmppc, get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 2);
		return;
	}
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return;
	}
	int t1 = regs.t1;
	do_cycles_ce000_internal(4);
	regs.sr = src;
	MakeFromSR();
	m68k_incpci(4);
	get_word_ce000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, 0);
		return;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	if(t1) opcode |= 0x10000;
	ipl_fetch_next();
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 22 (4/0) */
/* 4 4,0   */

/* MV2SR.W #<data>.W */
void REGPARAM2 op_46fc_14_ff(uae_u32 opcode)
{
	OpcodeFamily = 33;
	CurrentInstrCycles = 16; 
	if (!regs.s) {
		Exception(8);
		return;
	}
	uae_s16 src = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	int t1 = regs.t1;
	do_cycles_ce000_internal(4);
	regs.sr = src;
	MakeFromSR();
	m68k_incpci(4);
	get_word_ce000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, 0);
		return;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	if(t1) opcode |= 0x10000;
	ipl_fetch_next();
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 16 (3/0) */
/* 4 0,0   */

/* NBCD.B Dn */
void REGPARAM2 op_4800_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 17;
	CurrentInstrCycles = 6;  
	uae_s8 src = m68k_dreg(regs, srcreg);
	uae_u16 newv_lo = - (src & 0xF) - (GET_XFLG() ? 1 : 0);
	uae_u16 newv_hi = - (src & 0xF0);
	uae_u16 newv;
	int cflg, tmp_newv;
	tmp_newv = newv_hi + newv_lo;
	if (newv_lo > 9) newv_lo -= 6;
	newv = newv_hi + newv_lo;
	cflg = (newv & 0x1F0) > 0x90;
	if (cflg) newv -= 0x60;
	SET_CFLG(cflg);
	COPY_CARRY();
	SET_ZFLG(GET_ZFLG() & (((uae_s8)(newv)) == 0));
	SET_NFLG(((uae_s8)(newv)) < 0);
	SET_VFLG((tmp_newv & 0x80) != 0 && (newv & 0x80) == 0);
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	do_cycles_ce000_internal(2);
	m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((newv) & 0xff);
	m68k_incpci(2);
	return;
}
/* 6 (1/0) */
/* 2 0,0   */

/* NBCD.B (An) */
void REGPARAM2 op_4810_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 17;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	uae_u16 newv_lo = - (src & 0xF) - (GET_XFLG() ? 1 : 0);
	uae_u16 newv_hi = - (src & 0xF0);
	uae_u16 newv;
	int cflg, tmp_newv;
	tmp_newv = newv_hi + newv_lo;
	if (newv_lo > 9) newv_lo -= 6;
	newv = newv_hi + newv_lo;
	cflg = (newv & 0x1F0) > 0x90;
	if (cflg) newv -= 0x60;
	SET_CFLG(cflg);
	COPY_CARRY();
	SET_ZFLG(GET_ZFLG() & (((uae_s8)(newv)) == 0));
	SET_NFLG(((uae_s8)(newv)) < 0);
	SET_VFLG((tmp_newv & 0x80) != 0 && (newv & 0x80) == 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_byte(srca, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, newv, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 12 (2/1) */
/* 2 0,0   */

/* NBCD.B (An)+ */
void REGPARAM2 op_4818_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 17;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
	uae_u16 newv_lo = - (src & 0xF) - (GET_XFLG() ? 1 : 0);
	uae_u16 newv_hi = - (src & 0xF0);
	uae_u16 newv;
	int cflg, tmp_newv;
	tmp_newv = newv_hi + newv_lo;
	if (newv_lo > 9) newv_lo -= 6;
	newv = newv_hi + newv_lo;
	cflg = (newv & 0x1F0) > 0x90;
	if (cflg) newv -= 0x60;
	SET_CFLG(cflg);
	COPY_CARRY();
	SET_ZFLG(GET_ZFLG() & (((uae_s8)(newv)) == 0));
	SET_NFLG(((uae_s8)(newv)) < 0);
	SET_VFLG((tmp_newv & 0x80) != 0 && (newv & 0x80) == 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_byte(srca, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, newv, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 12 (2/1) */
/* 2 0,0   */

/* NBCD.B -(An) */
void REGPARAM2 op_4820_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 17;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
	do_cycles_ce000_internal(2);
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	m68k_areg(regs, srcreg) = srca;
	uae_u16 newv_lo = - (src & 0xF) - (GET_XFLG() ? 1 : 0);
	uae_u16 newv_hi = - (src & 0xF0);
	uae_u16 newv;
	int cflg, tmp_newv;
	tmp_newv = newv_hi + newv_lo;
	if (newv_lo > 9) newv_lo -= 6;
	newv = newv_hi + newv_lo;
	cflg = (newv & 0x1F0) > 0x90;
	if (cflg) newv -= 0x60;
	SET_CFLG(cflg);
	COPY_CARRY();
	SET_ZFLG(GET_ZFLG() & (((uae_s8)(newv)) == 0));
	SET_NFLG(((uae_s8)(newv)) < 0);
	SET_VFLG((tmp_newv & 0x80) != 0 && (newv & 0x80) == 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_byte(srca, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, newv, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 14 (2/1) */
/* 2 0,0   */

/* NBCD.B (d16,An) */
void REGPARAM2 op_4828_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 17;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	uae_u16 newv_lo = - (src & 0xF) - (GET_XFLG() ? 1 : 0);
	uae_u16 newv_hi = - (src & 0xF0);
	uae_u16 newv;
	int cflg, tmp_newv;
	tmp_newv = newv_hi + newv_lo;
	if (newv_lo > 9) newv_lo -= 6;
	newv = newv_hi + newv_lo;
	cflg = (newv & 0x1F0) > 0x90;
	if (cflg) newv -= 0x60;
	SET_CFLG(cflg);
	COPY_CARRY();
	SET_ZFLG(GET_ZFLG() & (((uae_s8)(newv)) == 0));
	SET_NFLG(((uae_s8)(newv)) < 0);
	SET_VFLG((tmp_newv & 0x80) != 0 && (newv & 0x80) == 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_byte(srca, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, newv, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* NBCD.B (d8,An,Xn) */
void REGPARAM2 op_4830_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 17;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	do_cycles_ce000_internal(2);
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	uae_u16 newv_lo = - (src & 0xF) - (GET_XFLG() ? 1 : 0);
	uae_u16 newv_hi = - (src & 0xF0);
	uae_u16 newv;
	int cflg, tmp_newv;
	tmp_newv = newv_hi + newv_lo;
	if (newv_lo > 9) newv_lo -= 6;
	newv = newv_hi + newv_lo;
	cflg = (newv & 0x1F0) > 0x90;
	if (cflg) newv -= 0x60;
	SET_CFLG(cflg);
	COPY_CARRY();
	SET_ZFLG(GET_ZFLG() & (((uae_s8)(newv)) == 0));
	SET_NFLG(((uae_s8)(newv)) < 0);
	SET_VFLG((tmp_newv & 0x80) != 0 && (newv & 0x80) == 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_byte(srca, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, newv, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 18 (3/1) */
/* 4 4,0   */

/* NBCD.B (xxx).W */
void REGPARAM2 op_4838_14_ff(uae_u32 opcode)
{
	OpcodeFamily = 17;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	uae_u16 newv_lo = - (src & 0xF) - (GET_XFLG() ? 1 : 0);
	uae_u16 newv_hi = - (src & 0xF0);
	uae_u16 newv;
	int cflg, tmp_newv;
	tmp_newv = newv_hi + newv_lo;
	if (newv_lo > 9) newv_lo -= 6;
	newv = newv_hi + newv_lo;
	cflg = (newv & 0x1F0) > 0x90;
	if (cflg) newv -= 0x60;
	SET_CFLG(cflg);
	COPY_CARRY();
	SET_ZFLG(GET_ZFLG() & (((uae_s8)(newv)) == 0));
	SET_NFLG(((uae_s8)(newv)) < 0);
	SET_VFLG((tmp_newv & 0x80) != 0 && (newv & 0x80) == 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_byte(srca, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, newv, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* NBCD.B (xxx).L */
void REGPARAM2 op_4839_14_ff(uae_u32 opcode)
{
	OpcodeFamily = 17;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	srca = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	srca |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	uae_u16 newv_lo = - (src & 0xF) - (GET_XFLG() ? 1 : 0);
	uae_u16 newv_hi = - (src & 0xF0);
	uae_u16 newv;
	int cflg, tmp_newv;
	tmp_newv = newv_hi + newv_lo;
	if (newv_lo > 9) newv_lo -= 6;
	newv = newv_hi + newv_lo;
	cflg = (newv & 0x1F0) > 0x90;
	if (cflg) newv -= 0x60;
	SET_CFLG(cflg);
	COPY_CARRY();
	SET_ZFLG(GET_ZFLG() & (((uae_s8)(newv)) == 0));
	SET_NFLG(((uae_s8)(newv)) < 0);
	SET_VFLG((tmp_newv & 0x80) != 0 && (newv & 0x80) == 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_byte(srca, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, newv, 1);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 20 (4/1) */
/* 6 0,0   */

/* SWAP.W Dn */
void REGPARAM2 op_4840_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 34;
	CurrentInstrCycles = 4;  
	uae_s32 src = m68k_dreg(regs, srcreg);
	uae_u32 dst = ((src >> 16)&0xFFFF) | ((src&0xFFFF)<<16);
	m68k_dreg(regs, srcreg) = (dst);
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(dst)) == 0);
	SET_NFLG(((uae_s32)(dst)) < 0);
	regs.ir = regs.irc;
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 4 (1/0) */
/* 2 0,0   */

/* PEA.L (An) */
void REGPARAM2 op_4850_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 57;
	CurrentInstrCycles = 12; 
	uae_u16 old_opcode = opcode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, 7) - 4;
	m68k_areg(regs, 7) = dsta;
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		m68k_areg(regs, 7) += 4;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	if (dsta & 1) {
		regs.ir = old_opcode;
		m68k_incpci(4);
		exception3_write_access(old_opcode, dsta, sz_word, srca >> 16, 1);
		return;
	}
	x_put_word(dsta, srca >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x1, srca >> 16, 1);
		return;
	}
	x_put_word(dsta + 2, srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 2, 0x1, srca, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 12 (1/2) */
/* 2 0,0   */

/* PEA.L (d16,An) */
void REGPARAM2 op_4868_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 57;
	CurrentInstrCycles = 16; 
	uae_u16 old_opcode = opcode;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, 7) - 4;
	m68k_areg(regs, 7) = dsta;
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		m68k_areg(regs, 7) += 4;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	if (dsta & 1) {
		regs.ir = old_opcode;
		m68k_incpci(6);
		exception3_write_access(old_opcode, dsta, sz_word, srca >> 16, 1);
		return;
	}
	x_put_word(dsta, srca >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, srca >> 16, 1);
		return;
	}
	x_put_word(dsta + 2, srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 2, 0x1, srca, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (2/2) */
/* 4 0,0   */

/* PEA.L (d8,An,Xn) */
void REGPARAM2 op_4870_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 57;
	CurrentInstrCycles = 20; 
	do_cycles_ce000_internal(2);
	ipl_fetch_now();
	uae_u16 old_opcode = opcode;
	uaecptr srca;
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, 7) - 4;
	m68k_areg(regs, 7) = dsta;
	do_cycles_ce000_internal(2);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		m68k_areg(regs, 7) += 4;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	if (dsta & 1) {
		regs.ir = old_opcode;
		m68k_incpci(6);
		exception3_write_access(old_opcode, dsta, sz_word, srca >> 16, 1);
		return;
	}
	x_put_word(dsta, srca >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, srca >> 16, 1);
		return;
	}
	x_put_word(dsta + 2, srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 2, 0x1, srca, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 20 (2/2) */
/* 4 4,0   */

/* PEA.L (xxx).W */
void REGPARAM2 op_4878_14_ff(uae_u32 opcode)
{
	OpcodeFamily = 57;
	CurrentInstrCycles = 16; 
	uae_u16 old_opcode = opcode;
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, 7) - 4;
	m68k_areg(regs, 7) = dsta;
	if (dsta & 1) {
		regs.ir = old_opcode;
		m68k_incpci(4);
		exception3_write_access(old_opcode, dsta, sz_word, srca >> 16, 1);
		return;
	}
	x_put_word(dsta, srca >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, srca >> 16, 1);
		return;
	}
	x_put_word(dsta + 2, srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 2, 0x1, srca, 1);
		return;
	}
	ipl_fetch_next();
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (2/2) */
/* 4 0,0   */

/* PEA.L (xxx).L */
void REGPARAM2 op_4879_14_ff(uae_u32 opcode)
{
	OpcodeFamily = 57;
	CurrentInstrCycles = 20; 
	uae_u16 old_opcode = opcode;
	uaecptr srca;
	srca = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	srca |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, 7) - 4;
	m68k_areg(regs, 7) = dsta;
	if (dsta & 1) {
		regs.ir = old_opcode;
		m68k_incpci(6);
		exception3_write_access(old_opcode, dsta, sz_word, srca >> 16, 1);
		return;
	}
	x_put_word(dsta, srca >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 0, 0x1, srca >> 16, 1);
		return;
	}
	x_put_word(dsta + 2, srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 2, 0x1, srca, 1);
		return;
	}
	ipl_fetch_next();
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 20 (3/2) */
/* 6 0,0   */

/* PEA.L (d16,PC) */
void REGPARAM2 op_487a_14_ff(uae_u32 opcode)
{
	OpcodeFamily = 57;
	CurrentInstrCycles = 16; 
	uae_u16 old_opcode = opcode;
	uaecptr srca;
	srca = m68k_getpci() + 2;
	srca += (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, 7) - 4;
	m68k_areg(regs, 7) = dsta;
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		m68k_areg(regs, 7) += 4;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	if (dsta & 1) {
		regs.ir = old_opcode;
		m68k_incpci(6);
		exception3_write_access(old_opcode, dsta, sz_word, srca >> 16, 1);
		return;
	}
	x_put_word(dsta, srca >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, srca >> 16, 1);
		return;
	}
	x_put_word(dsta + 2, srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 2, 0x1, srca, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (2/2) */
/* 4 0,0   */

/* PEA.L (d8,PC,Xn) */
void REGPARAM2 op_487b_14_ff(uae_u32 opcode)
{
	OpcodeFamily = 57;
	CurrentInstrCycles = 20; 
	do_cycles_ce000_internal(2);
	ipl_fetch_now();
	uae_u16 old_opcode = opcode;
	uaecptr srca;
	uaecptr tmppc = m68k_getpci() + 2;
	srca = get_disp_ea_000(tmppc, get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	uaecptr dsta;
	dsta = m68k_areg(regs, 7) - 4;
	m68k_areg(regs, 7) = dsta;
	do_cycles_ce000_internal(2);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		m68k_areg(regs, 7) += 4;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	if (dsta & 1) {
		regs.ir = old_opcode;
		m68k_incpci(6);
		exception3_write_access(old_opcode, dsta, sz_word, srca >> 16, 1);
		return;
	}
	x_put_word(dsta, srca >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, srca >> 16, 1);
		return;
	}
	x_put_word(dsta + 2, srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 2, 0x1, srca, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 20 (2/2) */
/* 4 4,0   */

/* EXT.W Dn */
void REGPARAM2 op_4880_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 36;
	CurrentInstrCycles = 4;  
	uae_s32 src = m68k_dreg(regs, srcreg);
	uae_u16 dst = (uae_s16)(uae_s8)src;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(dst)) == 0);
	SET_NFLG(((uae_s16)(dst)) < 0);
	m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | ((dst) & 0xffff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 4 (1/0) */
/* 2 0,0   */

/* MVMLE.W #<data>.W,(An) */
void REGPARAM2 op_4890_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 38;
	CurrentInstrCycles = 8;  
	uae_u16 mask = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 2);
		return;
	}
	uaecptr srca;
	srca = m68k_areg(regs, dstreg);
	uae_u16 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
	if ((amask || dmask) && (srca & 1)) {
		uaecptr srcav = srca;
		m68k_incpci(6);
		exception3_write_access(opcode, srca, 1, srcav, 1);
		return;
	}
	while (dmask) {
		x_put_word(srca, m68k_dreg(regs, movem_index1[dmask]));
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(6);
			exception2_write(opcode, srca + 0, 0x1, m68k_dreg(regs, movem_index1[dmask]), 1);
			return;
		}
		srca += 2;
		dmask = movem_next[dmask];
	}
	while (amask) {
		x_put_word(srca, m68k_areg(regs, movem_index1[amask]));
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(6);
			exception2_write(opcode, srca + 0, 0x1, m68k_areg(regs, movem_index1[amask]), 1);
			return;
		}
		srca += 2;
		amask = movem_next[amask];
	}
	ipl_fetch_next();
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 8+ (2/0) */
/* 4 0,0   */

/* MVMLE.W #<data>.W,-(An) */
void REGPARAM2 op_48a0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 38;
	CurrentInstrCycles = 8;  
	uae_u16 mask = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 2);
		return;
	}
	uaecptr srca;
	srca = m68k_areg(regs, dstreg) - 0;
	uae_u16 amask = mask & 0xff, dmask = (mask >> 8) & 0xff;
	if ((amask || dmask) && (srca & 1)) {
		srca -= 2;
		uaecptr srcav = srca;
		m68k_incpci(6);
		exception3_write_access(opcode, srca, 1, srcav, 1);
		return;
	}
	while (amask) {
		srca -= 2;
		x_put_word(srca, m68k_areg(regs, movem_index2[amask]));
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(6);
			exception2_write(opcode, srca + 0, 0x1, m68k_areg(regs, movem_index2[amask]), 1);
			return;
		}
		amask = movem_next[amask];
	}
	while (dmask) {
		srca -= 2;
		x_put_word(srca, m68k_dreg(regs, movem_index2[dmask]));
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(6);
			exception2_write(opcode, srca + 0, 0x1, m68k_dreg(regs, movem_index2[dmask]), 1);
			return;
		}
		dmask = movem_next[dmask];
	}
	m68k_areg(regs, dstreg) = srca;
	ipl_fetch_next();
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 8+ (2/0) */
/* 4 0,0   */

/* MVMLE.W #<data>.W,(d16,An) */
void REGPARAM2 op_48a8_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 38;
	CurrentInstrCycles = 12; 
	uae_u16 mask = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr srca;
	srca = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, 2);
		return;
	}
	uae_u16 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
	if ((amask || dmask) && (srca & 1)) {
		uaecptr srcav = srca;
		m68k_incpci(8);
		exception3_write_access(opcode, srca, 1, srcav, 1);
		return;
	}
	while (dmask) {
		x_put_word(srca, m68k_dreg(regs, movem_index1[dmask]));
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(8);
			exception2_write(opcode, srca + 0, 0x1, m68k_dreg(regs, movem_index1[dmask]), 1);
			return;
		}
		srca += 2;
		dmask = movem_next[dmask];
	}
	while (amask) {
		x_put_word(srca, m68k_areg(regs, movem_index1[amask]));
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(8);
			exception2_write(opcode, srca + 0, 0x1, m68k_areg(regs, movem_index1[amask]), 1);
			return;
		}
		srca += 2;
		amask = movem_next[amask];
	}
	ipl_fetch_next();
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 12+ (3/0) */
/* 6 0,0   */

/* MVMLE.W #<data>.W,(d8,An,Xn) */
void REGPARAM2 op_48b0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 38;
	CurrentInstrCycles = 14; 
	uae_u16 mask = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	do_cycles_ce000_internal(2);
	uaecptr srca;
	srca = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_ce000_prefetch(6));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, 2);
		return;
	}
	uae_u16 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
	if ((amask || dmask) && (srca & 1)) {
		uaecptr srcav = srca;
		m68k_incpci(8);
		exception3_write_access(opcode, srca, 1, srcav, 1);
		return;
	}
	while (dmask) {
		x_put_word(srca, m68k_dreg(regs, movem_index1[dmask]));
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(8);
			exception2_write(opcode, srca + 0, 0x1, m68k_dreg(regs, movem_index1[dmask]), 1);
			return;
		}
		srca += 2;
		dmask = movem_next[dmask];
	}
	while (amask) {
		x_put_word(srca, m68k_areg(regs, movem_index1[amask]));
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(8);
			exception2_write(opcode, srca + 0, 0x1, m68k_areg(regs, movem_index1[amask]), 1);
			return;
		}
		srca += 2;
		amask = movem_next[amask];
	}
	ipl_fetch_next();
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 14+ (3/0) */
/* 6 4,0   */

/* MVMLE.W #<data>.W,(xxx).W */
void REGPARAM2 op_48b8_14_ff(uae_u32 opcode)
{
	OpcodeFamily = 38;
	CurrentInstrCycles = 12; 
	uae_u16 mask = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, 2);
		return;
	}
	uae_u16 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
	if ((amask || dmask) && (srca & 1)) {
		uaecptr srcav = srca;
		m68k_incpci(8);
		exception3_write_access(opcode, srca, 1, srcav, 1);
		return;
	}
	while (dmask) {
		x_put_word(srca, m68k_dreg(regs, movem_index1[dmask]));
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(8);
			exception2_write(opcode, srca + 0, 0x1, m68k_dreg(regs, movem_index1[dmask]), 1);
			return;
		}
		srca += 2;
		dmask = movem_next[dmask];
	}
	while (amask) {
		x_put_word(srca, m68k_areg(regs, movem_index1[amask]));
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(8);
			exception2_write(opcode, srca + 0, 0x1, m68k_areg(regs, movem_index1[amask]), 1);
			return;
		}
		srca += 2;
		amask = movem_next[amask];
	}
	ipl_fetch_next();
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 12+ (3/0) */
/* 6 0,0   */

/* MVMLE.W #<data>.W,(xxx).L */
void REGPARAM2 op_48b9_14_ff(uae_u32 opcode)
{
	OpcodeFamily = 38;
	CurrentInstrCycles = 16; 
	uae_u16 mask = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr srca;
	srca = get_word_ce000_prefetch(6) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return;
	}
	srca |= get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		pcoffset += 2;
		exception2_fetch(opcode, 8, pcoffset);
		return;
	}
	uae_u16 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
	if ((amask || dmask) && (srca & 1)) {
		uaecptr srcav = srca;
		m68k_incpci(10);
		exception3_write_access(opcode, srca, 1, srcav, 1);
		return;
	}
	while (dmask) {
		x_put_word(srca, m68k_dreg(regs, movem_index1[dmask]));
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(10);
			exception2_write(opcode, srca + 0, 0x1, m68k_dreg(regs, movem_index1[dmask]), 1);
			return;
		}
		srca += 2;
		dmask = movem_next[dmask];
	}
	while (amask) {
		x_put_word(srca, m68k_areg(regs, movem_index1[amask]));
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(10);
			exception2_write(opcode, srca + 0, 0x1, m68k_areg(regs, movem_index1[amask]), 1);
			return;
		}
		srca += 2;
		amask = movem_next[amask];
	}
	ipl_fetch_next();
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(10);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 10, pcoffset);
		return;
	}
	m68k_incpci(8);
	return;
}
/* 16+ (4/0) */
/* 8 0,0   */

/* EXT.L Dn */
void REGPARAM2 op_48c0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 36;
	CurrentInstrCycles = 4;  
	uae_s32 src = m68k_dreg(regs, srcreg);
	uae_u32 dst = (uae_s32)(uae_s16)src;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(dst)) == 0);
	SET_NFLG(((uae_s32)(dst)) < 0);
	m68k_dreg(regs, srcreg) = (dst);
	regs.ir = regs.irc;
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 4 (1/0) */
/* 2 0,0   */

/* MVMLE.L #<data>.W,(An) */
void REGPARAM2 op_48d0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 38;
	CurrentInstrCycles = 8;  
	uae_u16 mask = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 2);
		return;
	}
	uaecptr srca;
	srca = m68k_areg(regs, dstreg);
	uae_u16 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
	if ((amask || dmask) && (srca & 1)) {
		uaecptr srcav = srca;
		m68k_incpci(6);
		exception3_write_access(opcode, srca, 2, srcav, 1);
		return;
	}
	while (dmask) {
		x_put_word(srca, m68k_dreg(regs, movem_index1[dmask]) >> 16);
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(6);
			exception2_write(opcode, srca + 0, 0x1, m68k_dreg(regs, movem_index1[dmask]) >> 16, 1);
			return;
		}
		x_put_word(srca + 2, m68k_dreg(regs, movem_index1[dmask]));
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(6);
			exception2_write(opcode, srca + 2, 0x1, m68k_dreg(regs, movem_index1[dmask]), 1);
			return;
		}
		srca += 4;
		dmask = movem_next[dmask];
	}
	while (amask) {
		x_put_word(srca, m68k_areg(regs, movem_index1[amask]) >> 16);
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(6);
			exception2_write(opcode, srca + 0, 0x1, m68k_areg(regs, movem_index1[amask]) >> 16, 1);
			return;
		}
		x_put_word(srca + 2, m68k_areg(regs, movem_index1[amask]));
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(6);
			exception2_write(opcode, srca + 2, 0x1, m68k_areg(regs, movem_index1[amask]), 1);
			return;
		}
		srca += 4;
		amask = movem_next[amask];
	}
	ipl_fetch_next();
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 8+ (2/0) */
/* 4 0,0   */

/* MVMLE.L #<data>.W,-(An) */
void REGPARAM2 op_48e0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 38;
	CurrentInstrCycles = 8;  
	uae_u16 mask = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 2);
		return;
	}
	uaecptr srca;
	srca = m68k_areg(regs, dstreg) - 0;
	uae_u16 amask = mask & 0xff, dmask = (mask >> 8) & 0xff;
	if ((amask || dmask) && (srca & 1)) {
		srca -= 2;
		uaecptr srcav = srca;
		m68k_incpci(6);
		exception3_write_access(opcode, srca, 2, srcav, 1);
		return;
	}
	while (amask) {
		x_put_word(srca - 2, m68k_areg(regs, movem_index2[amask]));
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(6);
			exception2_write(opcode, srca + -2, 0x1, m68k_areg(regs, movem_index2[amask]), 1);
			return;
		}
		x_put_word(srca - 4, m68k_areg(regs, movem_index2[amask]) >> 16);
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(6);
			exception2_write(opcode, srca + -4, 0x1, m68k_areg(regs, movem_index2[amask]) >> 16, 1);
			return;
		}
		srca -= 4;
		amask = movem_next[amask];
	}
	while (dmask) {
		x_put_word(srca - 2, m68k_dreg(regs, movem_index2[dmask]));
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(6);
			exception2_write(opcode, srca + -2, 0x1, m68k_dreg(regs, movem_index2[dmask]), 1);
			return;
		}
		x_put_word(srca - 4, m68k_dreg(regs, movem_index2[dmask]) >> 16);
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(6);
			exception2_write(opcode, srca + -4, 0x1, m68k_dreg(regs, movem_index2[dmask]) >> 16, 1);
			return;
		}
		srca -= 4;
		dmask = movem_next[dmask];
	}
	m68k_areg(regs, dstreg) = srca;
	ipl_fetch_next();
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 8+ (2/0) */
/* 4 0,0   */

/* MVMLE.L #<data>.W,(d16,An) */
void REGPARAM2 op_48e8_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 38;
	CurrentInstrCycles = 12; 
	uae_u16 mask = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr srca;
	srca = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, 2);
		return;
	}
	uae_u16 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
	if ((amask || dmask) && (srca & 1)) {
		uaecptr srcav = srca;
		m68k_incpci(8);
		exception3_write_access(opcode, srca, 2, srcav, 1);
		return;
	}
	while (dmask) {
		x_put_word(srca, m68k_dreg(regs, movem_index1[dmask]) >> 16);
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(8);
			exception2_write(opcode, srca + 0, 0x1, m68k_dreg(regs, movem_index1[dmask]) >> 16, 1);
			return;
		}
		x_put_word(srca + 2, m68k_dreg(regs, movem_index1[dmask]));
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(8);
			exception2_write(opcode, srca + 2, 0x1, m68k_dreg(regs, movem_index1[dmask]), 1);
			return;
		}
		srca += 4;
		dmask = movem_next[dmask];
	}
	while (amask) {
		x_put_word(srca, m68k_areg(regs, movem_index1[amask]) >> 16);
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(8);
			exception2_write(opcode, srca + 0, 0x1, m68k_areg(regs, movem_index1[amask]) >> 16, 1);
			return;
		}
		x_put_word(srca + 2, m68k_areg(regs, movem_index1[amask]));
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(8);
			exception2_write(opcode, srca + 2, 0x1, m68k_areg(regs, movem_index1[amask]), 1);
			return;
		}
		srca += 4;
		amask = movem_next[amask];
	}
	ipl_fetch_next();
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 12+ (3/0) */
/* 6 0,0   */

/* MVMLE.L #<data>.W,(d8,An,Xn) */
void REGPARAM2 op_48f0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 38;
	CurrentInstrCycles = 14; 
	uae_u16 mask = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	do_cycles_ce000_internal(2);
	uaecptr srca;
	srca = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_ce000_prefetch(6));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, 2);
		return;
	}
	uae_u16 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
	if ((amask || dmask) && (srca & 1)) {
		uaecptr srcav = srca;
		m68k_incpci(8);
		exception3_write_access(opcode, srca, 2, srcav, 1);
		return;
	}
	while (dmask) {
		x_put_word(srca, m68k_dreg(regs, movem_index1[dmask]) >> 16);
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(8);
			exception2_write(opcode, srca + 0, 0x1, m68k_dreg(regs, movem_index1[dmask]) >> 16, 1);
			return;
		}
		x_put_word(srca + 2, m68k_dreg(regs, movem_index1[dmask]));
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(8);
			exception2_write(opcode, srca + 2, 0x1, m68k_dreg(regs, movem_index1[dmask]), 1);
			return;
		}
		srca += 4;
		dmask = movem_next[dmask];
	}
	while (amask) {
		x_put_word(srca, m68k_areg(regs, movem_index1[amask]) >> 16);
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(8);
			exception2_write(opcode, srca + 0, 0x1, m68k_areg(regs, movem_index1[amask]) >> 16, 1);
			return;
		}
		x_put_word(srca + 2, m68k_areg(regs, movem_index1[amask]));
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(8);
			exception2_write(opcode, srca + 2, 0x1, m68k_areg(regs, movem_index1[amask]), 1);
			return;
		}
		srca += 4;
		amask = movem_next[amask];
	}
	ipl_fetch_next();
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 14+ (3/0) */
/* 6 4,0   */

/* MVMLE.L #<data>.W,(xxx).W */
void REGPARAM2 op_48f8_14_ff(uae_u32 opcode)
{
	OpcodeFamily = 38;
	CurrentInstrCycles = 12; 
	uae_u16 mask = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, 2);
		return;
	}
	uae_u16 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
	if ((amask || dmask) && (srca & 1)) {
		uaecptr srcav = srca;
		m68k_incpci(8);
		exception3_write_access(opcode, srca, 2, srcav, 1);
		return;
	}
	while (dmask) {
		x_put_word(srca, m68k_dreg(regs, movem_index1[dmask]) >> 16);
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(8);
			exception2_write(opcode, srca + 0, 0x1, m68k_dreg(regs, movem_index1[dmask]) >> 16, 1);
			return;
		}
		x_put_word(srca + 2, m68k_dreg(regs, movem_index1[dmask]));
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(8);
			exception2_write(opcode, srca + 2, 0x1, m68k_dreg(regs, movem_index1[dmask]), 1);
			return;
		}
		srca += 4;
		dmask = movem_next[dmask];
	}
	while (amask) {
		x_put_word(srca, m68k_areg(regs, movem_index1[amask]) >> 16);
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(8);
			exception2_write(opcode, srca + 0, 0x1, m68k_areg(regs, movem_index1[amask]) >> 16, 1);
			return;
		}
		x_put_word(srca + 2, m68k_areg(regs, movem_index1[amask]));
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(8);
			exception2_write(opcode, srca + 2, 0x1, m68k_areg(regs, movem_index1[amask]), 1);
			return;
		}
		srca += 4;
		amask = movem_next[amask];
	}
	ipl_fetch_next();
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 12+ (3/0) */
/* 6 0,0   */

/* MVMLE.L #<data>.W,(xxx).L */
void REGPARAM2 op_48f9_14_ff(uae_u32 opcode)
{
	OpcodeFamily = 38;
	CurrentInstrCycles = 16; 
	uae_u16 mask = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uaecptr srca;
	srca = get_word_ce000_prefetch(6) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return;
	}
	srca |= get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		pcoffset += 2;
		exception2_fetch(opcode, 8, pcoffset);
		return;
	}
	uae_u16 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
	if ((amask || dmask) && (srca & 1)) {
		uaecptr srcav = srca;
		m68k_incpci(10);
		exception3_write_access(opcode, srca, 2, srcav, 1);
		return;
	}
	while (dmask) {
		x_put_word(srca, m68k_dreg(regs, movem_index1[dmask]) >> 16);
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(10);
			exception2_write(opcode, srca + 0, 0x1, m68k_dreg(regs, movem_index1[dmask]) >> 16, 1);
			return;
		}
		x_put_word(srca + 2, m68k_dreg(regs, movem_index1[dmask]));
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(10);
			exception2_write(opcode, srca + 2, 0x1, m68k_dreg(regs, movem_index1[dmask]), 1);
			return;
		}
		srca += 4;
		dmask = movem_next[dmask];
	}
	while (amask) {
		x_put_word(srca, m68k_areg(regs, movem_index1[amask]) >> 16);
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(10);
			exception2_write(opcode, srca + 0, 0x1, m68k_areg(regs, movem_index1[amask]) >> 16, 1);
			return;
		}
		x_put_word(srca + 2, m68k_areg(regs, movem_index1[amask]));
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(10);
			exception2_write(opcode, srca + 2, 0x1, m68k_areg(regs, movem_index1[amask]), 1);
			return;
		}
		srca += 4;
		amask = movem_next[amask];
	}
	ipl_fetch_next();
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(10);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 10, pcoffset);
		return;
	}
	m68k_incpci(8);
	return;
}
/* 16+ (4/0) */
/* 8 0,0   */

/* TST.B Dn */
void REGPARAM2 op_4a00_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 20;
	CurrentInstrCycles = 4;  
	uae_s8 src = m68k_dreg(regs, srcreg);
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	regs.ir = regs.irc;
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 4 (1/0) */
/* 2 0,0   */

/* TST.B (An) */
void REGPARAM2 op_4a10_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 20;
	CurrentInstrCycles = 8;  
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 8 (2/0) */
/* 2 0,0   */

/* TST.B (An)+ */
void REGPARAM2 op_4a18_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 20;
	CurrentInstrCycles = 8;  
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 8 (2/0) */
/* 2 0,0   */

/* TST.B -(An) */
void REGPARAM2 op_4a20_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 20;
	CurrentInstrCycles = 10; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
	do_cycles_ce000_internal(2);
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	m68k_areg(regs, srcreg) = srca;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 10 (2/0) */
/* 2 0,0   */

/* TST.B (d16,An) */
void REGPARAM2 op_4a28_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 20;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 12 (3/0) */
/* 4 0,0   */

/* TST.B (d8,An,Xn) */
void REGPARAM2 op_4a30_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 20;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	do_cycles_ce000_internal(2);
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 14 (3/0) */
/* 4 4,0   */

/* TST.B (xxx).W */
void REGPARAM2 op_4a38_14_ff(uae_u32 opcode)
{
	OpcodeFamily = 20;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 12 (3/0) */
/* 4 0,0   */

/* TST.B (xxx).L */
void REGPARAM2 op_4a39_14_ff(uae_u32 opcode)
{
	OpcodeFamily = 20;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	srca |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 16 (4/0) */
/* 6 0,0   */

/* TST.W Dn */
void REGPARAM2 op_4a40_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 20;
	CurrentInstrCycles = 4;  
	uae_s16 src = m68k_dreg(regs, srcreg);
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	regs.ir = regs.irc;
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 4 (1/0) */
/* 2 0,0   */

/* TST.W (An) */
void REGPARAM2 op_4a50_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 20;
	CurrentInstrCycles = 8;  
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 8 (2/0) */
/* 2 0,0   */

/* TST.W (An)+ */
void REGPARAM2 op_4a58_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 20;
	CurrentInstrCycles = 8;  
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) += 2 + 0;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	m68k_areg(regs, srcreg) += 2;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 8 (2/0) */
/* 2 0,0   */

/* TST.W -(An) */
void REGPARAM2 op_4a60_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 20;
	CurrentInstrCycles = 10; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - 2;
	do_cycles_ce000_internal(2);
	if (srca & 1) {
		m68k_incpci(4);
		m68k_areg(regs, srcreg) = srca;
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	m68k_areg(regs, srcreg) = srca;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 10 (2/0) */
/* 2 0,0   */

/* TST.W (d16,An) */
void REGPARAM2 op_4a68_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 20;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 12 (3/0) */
/* 4 0,0   */

/* TST.W (d8,An,Xn) */
void REGPARAM2 op_4a70_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 20;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	do_cycles_ce000_internal(2);
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 14 (3/0) */
/* 4 4,0   */

/* TST.W (xxx).W */
void REGPARAM2 op_4a78_14_ff(uae_u32 opcode)
{
	OpcodeFamily = 20;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	if (srca & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 12 (3/0) */
/* 4 0,0   */

/* TST.W (xxx).L */
void REGPARAM2 op_4a79_14_ff(uae_u32 opcode)
{
	OpcodeFamily = 20;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	srca |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	if (srca & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 16 (4/0) */
/* 6 0,0   */

/* TST.L Dn */
void REGPARAM2 op_4a80_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 20;
	CurrentInstrCycles = 4;  
	uae_s32 src = m68k_dreg(regs, srcreg);
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	regs.ir = regs.irc;
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 4 (1/0) */
/* 2 0,0   */

/* TST.L (An) */
void REGPARAM2 op_4a90_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 20;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 12 (3/0) */
/* 2 0,0   */

/* TST.L (An)+ */
void REGPARAM2 op_4a98_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 20;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	m68k_areg(regs, srcreg) += 4;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 12 (3/0) */
/* 2 0,0   */

/* TST.L -(An) */
void REGPARAM2 op_4aa0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 20;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - 4;
	do_cycles_ce000_internal(2);
	if (srca & 1) {
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	m68k_areg(regs, srcreg) = srca;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 14 (3/0) */
/* 2 0,0   */

/* TST.L (d16,An) */
void REGPARAM2 op_4aa8_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 20;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (4/0) */
/* 4 0,0   */

/* TST.L (d8,An,Xn) */
void REGPARAM2 op_4ab0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 20;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	do_cycles_ce000_internal(2);
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 18 (4/0) */
/* 4 4,0   */

/* TST.L (xxx).W */
void REGPARAM2 op_4ab8_14_ff(uae_u32 opcode)
{
	OpcodeFamily = 20;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	if (srca & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (4/0) */
/* 4 0,0   */

/* TST.L (xxx).L */
void REGPARAM2 op_4ab9_14_ff(uae_u32 opcode)
{
	OpcodeFamily = 20;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	srca = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	srca |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	if (srca & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 20 (5/0) */
/* 6 0,0   */

/* TAS.B Dn */
void REGPARAM2 op_4ac0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 98;
	CurrentInstrCycles = 4;  
	cpu_bus_rmw=true;
	uae_s8 src = m68k_dreg(regs, srcreg);
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	uae_u8 old_src = src;
	src |= 0x80;
	m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((src) & 0xff);
	cpu_bus_rmw=false;
	regs.ir = regs.irc;
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 4 (1/0) */
/* 2 0,0   */

/* TAS.B (An) */
void REGPARAM2 op_4ad0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 98;
	CurrentInstrCycles = 14; 
	cpu_bus_rmw=true;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		do_cycles_ce000_internal(2);
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	do_cycles_ce000_internal(2);
	uae_u8 old_src = src;
	src |= 0x80;
	if (!is_cycle_ce(srca)) {
		ipl_fetch_now();
		x_put_byte(srca, src);
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(4);
			if (regs.t1) opcode |= 0x10000;
			exception2_write(opcode, srca + 0, 0x0, src, 1);
			return;
		}
	} else {
		do_cycles_ce000_internal(4);
	}
	cpu_bus_rmw=false;
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 14 (2/1) */
/* 2 0,0   */

/* TAS.B (An)+ */
void REGPARAM2 op_4ad8_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 98;
	CurrentInstrCycles = 14; 
	cpu_bus_rmw=true;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		do_cycles_ce000_internal(2);
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	do_cycles_ce000_internal(2);
	uae_u8 old_src = src;
	src |= 0x80;
	if (!is_cycle_ce(srca)) {
		ipl_fetch_now();
		x_put_byte(srca, src);
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(4);
			if (regs.t1) opcode |= 0x10000;
			exception2_write(opcode, srca + 0, 0x0, src, 1);
			return;
		}
	} else {
		do_cycles_ce000_internal(4);
	}
	cpu_bus_rmw=false;
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 14 (2/1) */
/* 2 0,0   */

/* TAS.B -(An) */
void REGPARAM2 op_4ae0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 98;
	CurrentInstrCycles = 16; 
	cpu_bus_rmw=true;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
	do_cycles_ce000_internal(2);
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		do_cycles_ce000_internal(2);
		m68k_incpci(4);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	m68k_areg(regs, srcreg) = srca;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	do_cycles_ce000_internal(2);
	uae_u8 old_src = src;
	src |= 0x80;
	if (!is_cycle_ce(srca)) {
		ipl_fetch_now();
		x_put_byte(srca, src);
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(4);
			if (regs.t1) opcode |= 0x10000;
			exception2_write(opcode, srca + 0, 0x0, src, 1);
			return;
		}
	} else {
		do_cycles_ce000_internal(4);
	}
	cpu_bus_rmw=false;
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 16 (2/1) */
/* 2 0,0   */

/* TAS.B (d16,An) */
void REGPARAM2 op_4ae8_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 98;
	CurrentInstrCycles = 18; 
	cpu_bus_rmw=true;
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		do_cycles_ce000_internal(2);
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	do_cycles_ce000_internal(2);
	uae_u8 old_src = src;
	src |= 0x80;
	if (!is_cycle_ce(srca)) {
		ipl_fetch_now();
		x_put_byte(srca, src);
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(6);
			if (regs.t1) opcode |= 0x10000;
			exception2_write(opcode, srca + 0, 0x0, src, 1);
			return;
		}
	} else {
		do_cycles_ce000_internal(4);
	}
	cpu_bus_rmw=false;
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 18 (3/1) */
/* 4 0,0   */

/* TAS.B (d8,An,Xn) */
void REGPARAM2 op_4af0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 98;
	CurrentInstrCycles = 20; 
	cpu_bus_rmw=true;
	uaecptr srca;
	do_cycles_ce000_internal(2);
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		do_cycles_ce000_internal(2);
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	do_cycles_ce000_internal(2);
	uae_u8 old_src = src;
	src |= 0x80;
	if (!is_cycle_ce(srca)) {
		ipl_fetch_now();
		x_put_byte(srca, src);
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(6);
			if (regs.t1) opcode |= 0x10000;
			exception2_write(opcode, srca + 0, 0x0, src, 1);
			return;
		}
	} else {
		do_cycles_ce000_internal(4);
	}
	cpu_bus_rmw=false;
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 20 (3/1) */
/* 4 4,0   */

/* TAS.B (xxx).W */
void REGPARAM2 op_4af8_14_ff(uae_u32 opcode)
{
	OpcodeFamily = 98;
	CurrentInstrCycles = 18; 
	cpu_bus_rmw=true;
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		do_cycles_ce000_internal(2);
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	do_cycles_ce000_internal(2);
	uae_u8 old_src = src;
	src |= 0x80;
	if (!is_cycle_ce(srca)) {
		ipl_fetch_now();
		x_put_byte(srca, src);
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(6);
			if (regs.t1) opcode |= 0x10000;
			exception2_write(opcode, srca + 0, 0x0, src, 1);
			return;
		}
	} else {
		do_cycles_ce000_internal(4);
	}
	cpu_bus_rmw=false;
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 18 (3/1) */
/* 4 0,0   */

/* TAS.B (xxx).L */
void REGPARAM2 op_4af9_14_ff(uae_u32 opcode)
{
	OpcodeFamily = 98;
	CurrentInstrCycles = 22; 
	cpu_bus_rmw=true;
	uaecptr srca;
	srca = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	srca |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		do_cycles_ce000_internal(2);
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	do_cycles_ce000_internal(2);
	uae_u8 old_src = src;
	src |= 0x80;
	if (!is_cycle_ce(srca)) {
		ipl_fetch_now();
		x_put_byte(srca, src);
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(8);
			if (regs.t1) opcode |= 0x10000;
			exception2_write(opcode, srca + 0, 0x0, src, 1);
			return;
		}
	} else {
		do_cycles_ce000_internal(4);
	}
	cpu_bus_rmw=false;
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 22 (4/1) */
/* 6 0,0   */

/* MVMEL.W #<data>.W,(An) */
void REGPARAM2 op_4c90_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 37;
	CurrentInstrCycles = 12; 
	uae_u16 mask = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
	uaecptr srca;
	srca = m68k_areg(regs, dstreg);
	if (srca & 1) {
		uaecptr srcav = srca;
		m68k_incpci(6);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	while (dmask) {
		uae_u32 v = (uae_s32)(uae_s16)x_get_word(srca);
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(6);
			exception2_read(opcode, srca + 0, 0x1, 1);
			return;
		}
		m68k_dreg(regs, movem_index1[dmask]) = v;
		srca += 2;
		dmask = movem_next[dmask];
	}
	while (amask) {
		uae_u32 v = (uae_s32)(uae_s16)x_get_word(srca);
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(6);
			exception2_read(opcode, srca + 0, 0x1, 1);
			return;
		}
		m68k_areg(regs, movem_index1[amask]) = v;
		srca += 2;
		amask = movem_next[amask];
	}
	x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	ipl_fetch_next();
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 12+ (3/0) */
/* 4 0,0   */

/* MVMEL.W #<data>.W,(An)+ */
void REGPARAM2 op_4c98_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 37;
	CurrentInstrCycles = 12; 
	ipl_fetch_now();
	uae_u16 mask = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
	uaecptr srca;
	srca = m68k_areg(regs, dstreg);
	if (srca & 1) {
		uaecptr srcav = srca;
		m68k_incpci(6);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	while (dmask) {
		uae_u32 v = (uae_s32)(uae_s16)x_get_word(srca);
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(6);
			exception2_read(opcode, srca + 0, 0x1, 1);
			return;
		}
		m68k_dreg(regs, movem_index1[dmask]) = v;
		srca += 2;
		dmask = movem_next[dmask];
	}
	while (amask) {
		uae_u32 v = (uae_s32)(uae_s16)x_get_word(srca);
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(6);
			exception2_read(opcode, srca + 0, 0x1, 1);
			return;
		}
		m68k_areg(regs, movem_index1[amask]) = v;
		srca += 2;
		amask = movem_next[amask];
	}
	x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	m68k_areg(regs, dstreg) = srca;
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 12+ (3/0) */
/* 4 0,0   */

/* MVMEL.W #<data>.W,(d16,An) */
void REGPARAM2 op_4ca8_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 37;
	CurrentInstrCycles = 16; 
	uae_u16 mask = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
	uaecptr srca;
	srca = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return;
	}
	if (srca & 1) {
		uaecptr srcav = srca;
		m68k_incpci(8);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	while (dmask) {
		uae_u32 v = (uae_s32)(uae_s16)x_get_word(srca);
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(8);
			exception2_read(opcode, srca + 0, 0x1, 1);
			return;
		}
		m68k_dreg(regs, movem_index1[dmask]) = v;
		srca += 2;
		dmask = movem_next[dmask];
	}
	while (amask) {
		uae_u32 v = (uae_s32)(uae_s16)x_get_word(srca);
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(8);
			exception2_read(opcode, srca + 0, 0x1, 1);
			return;
		}
		m68k_areg(regs, movem_index1[amask]) = v;
		srca += 2;
		amask = movem_next[amask];
	}
	x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	ipl_fetch_next();
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 16+ (4/0) */
/* 6 0,0   */

/* MVMEL.W #<data>.W,(d8,An,Xn) */
void REGPARAM2 op_4cb0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 37;
	CurrentInstrCycles = 18; 
	uae_u16 mask = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
	do_cycles_ce000_internal(2);
	uaecptr srca;
	srca = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_ce000_prefetch(6));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return;
	}
	if (srca & 1) {
		uaecptr srcav = srca;
		m68k_incpci(4);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	while (dmask) {
		uae_u32 v = (uae_s32)(uae_s16)x_get_word(srca);
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(8);
			exception2_read(opcode, srca + 0, 0x1, 1);
			return;
		}
		m68k_dreg(regs, movem_index1[dmask]) = v;
		srca += 2;
		dmask = movem_next[dmask];
	}
	while (amask) {
		uae_u32 v = (uae_s32)(uae_s16)x_get_word(srca);
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(8);
			exception2_read(opcode, srca + 0, 0x1, 1);
			return;
		}
		m68k_areg(regs, movem_index1[amask]) = v;
		srca += 2;
		amask = movem_next[amask];
	}
	x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	ipl_fetch_next();
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 18+ (4/0) */
/* 6 4,0   */

/* MVMEL.W #<data>.W,(xxx).W */
void REGPARAM2 op_4cb8_14_ff(uae_u32 opcode)
{
	OpcodeFamily = 37;
	CurrentInstrCycles = 16; 
	uae_u16 mask = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return;
	}
	if (srca & 1) {
		uaecptr srcav = srca;
		m68k_incpci(8);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	while (dmask) {
		uae_u32 v = (uae_s32)(uae_s16)x_get_word(srca);
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(8);
			exception2_read(opcode, srca + 0, 0x1, 1);
			return;
		}
		m68k_dreg(regs, movem_index1[dmask]) = v;
		srca += 2;
		dmask = movem_next[dmask];
	}
	while (amask) {
		uae_u32 v = (uae_s32)(uae_s16)x_get_word(srca);
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(8);
			exception2_read(opcode, srca + 0, 0x1, 1);
			return;
		}
		m68k_areg(regs, movem_index1[amask]) = v;
		srca += 2;
		amask = movem_next[amask];
	}
	x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	ipl_fetch_next();
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 16+ (4/0) */
/* 6 0,0   */

/* MVMEL.W #<data>.W,(xxx).L */
void REGPARAM2 op_4cb9_14_ff(uae_u32 opcode)
{
	OpcodeFamily = 37;
	CurrentInstrCycles = 20; 
	uae_u16 mask = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
	uaecptr srca;
	srca = get_word_ce000_prefetch(6) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return;
	}
	srca |= get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 8, pcoffset);
		return;
	}
	if (srca & 1) {
		uaecptr srcav = srca;
		m68k_incpci(10);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	while (dmask) {
		uae_u32 v = (uae_s32)(uae_s16)x_get_word(srca);
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(10);
			exception2_read(opcode, srca + 0, 0x1, 1);
			return;
		}
		m68k_dreg(regs, movem_index1[dmask]) = v;
		srca += 2;
		dmask = movem_next[dmask];
	}
	while (amask) {
		uae_u32 v = (uae_s32)(uae_s16)x_get_word(srca);
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(10);
			exception2_read(opcode, srca + 0, 0x1, 1);
			return;
		}
		m68k_areg(regs, movem_index1[amask]) = v;
		srca += 2;
		amask = movem_next[amask];
	}
	x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(10);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	ipl_fetch_next();
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(10);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 10, pcoffset);
		return;
	}
	m68k_incpci(8);
	return;
}
/* 20+ (5/0) */
/* 8 0,0   */

/* MVMEL.W #<data>.W,(d16,PC) */
void REGPARAM2 op_4cba_14_ff(uae_u32 opcode)
{
	uae_u32 dstreg = 2;
	OpcodeFamily = 37;
	CurrentInstrCycles = 16; 
	uae_u16 mask = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
	uaecptr srca;
	srca = m68k_getpci() + 4;
	srca += (uae_s32)(uae_s16)get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return;
	}
	if (srca & 1) {
		opcode |= 0x00020000;
		uaecptr srcav = srca;
		m68k_incpci(8);
		exception3_read_access(opcode, srca, 1, 2);
		return;
	}
	while (dmask) {
		uae_u32 v = (uae_s32)(uae_s16)x_get_word(srca);
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(8);
			exception2_read(opcode, srca + 0, 0x1, 2);
			return;
		}
		m68k_dreg(regs, movem_index1[dmask]) = v;
		srca += 2;
		dmask = movem_next[dmask];
	}
	while (amask) {
		uae_u32 v = (uae_s32)(uae_s16)x_get_word(srca);
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(8);
			exception2_read(opcode, srca + 0, 0x1, 2);
			return;
		}
		m68k_areg(regs, movem_index1[amask]) = v;
		srca += 2;
		amask = movem_next[amask];
	}
	x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return;
	}
	ipl_fetch_next();
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 16+ (4/0) */
/* 6 0,0   */

/* MVMEL.W #<data>.W,(d8,PC,Xn) */
void REGPARAM2 op_4cbb_14_ff(uae_u32 opcode)
{
	uae_u32 dstreg = 3;
	OpcodeFamily = 37;
	CurrentInstrCycles = 18; 
	uae_u16 mask = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
	do_cycles_ce000_internal(2);
	uaecptr srca;
	uaecptr tmppc = m68k_getpci() + 4;
	srca = get_disp_ea_000(tmppc, get_word_ce000_prefetch(6));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return;
	}
	if (srca & 1) {
		opcode |= 0x00020000;
		uaecptr srcav = srca;
		m68k_incpci(4);
		exception3_read_access(opcode, srca, 1, 2);
		return;
	}
	while (dmask) {
		uae_u32 v = (uae_s32)(uae_s16)x_get_word(srca);
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(8);
			exception2_read(opcode, srca + 0, 0x1, 2);
			return;
		}
		m68k_dreg(regs, movem_index1[dmask]) = v;
		srca += 2;
		dmask = movem_next[dmask];
	}
	while (amask) {
		uae_u32 v = (uae_s32)(uae_s16)x_get_word(srca);
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(8);
			exception2_read(opcode, srca + 0, 0x1, 2);
			return;
		}
		m68k_areg(regs, movem_index1[amask]) = v;
		srca += 2;
		amask = movem_next[amask];
	}
	x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return;
	}
	ipl_fetch_next();
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 18+ (4/0) */
/* 6 4,0   */

/* MVMEL.L #<data>.W,(An) */
void REGPARAM2 op_4cd0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 37;
	CurrentInstrCycles = 12; 
	uae_u16 mask = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
	uaecptr srca;
	srca = m68k_areg(regs, dstreg);
	if (srca & 1) {
		uaecptr srcav = srca;
		m68k_incpci(6);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	while (dmask) {
		uae_u32 v = (x_get_word(srca) << 16) | (m68k_dreg(regs, movem_index1[dmask]) & 0xffff);
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(6);
			exception2_read(opcode, srca + 0, 0x1, 1);
			return;
		}
		m68k_dreg(regs, movem_index1[dmask]) = v;
		v &= 0xffff0000;
		v |= x_get_word(srca + 2); 
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(6);
			exception2_read(opcode, srca + 2, 0x1, 1);
			return;
		}
		m68k_dreg(regs, movem_index1[dmask]) = v;
		srca += 4;
		dmask = movem_next[dmask];
	}
	while (amask) {
		uae_u32 v = (x_get_word(srca) << 16) | (m68k_areg(regs, movem_index1[amask]) & 0xffff);
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(6);
			exception2_read(opcode, srca + 0, 0x1, 1);
			return;
		}
		m68k_areg(regs, movem_index1[amask]) = v;
		v &= 0xffff0000;
		v |= x_get_word(srca + 2);
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(6);
			exception2_read(opcode, srca + 2, 0x1, 1);
			return;
		}
		m68k_areg(regs, movem_index1[amask]) = v;
		srca += 4;
		amask = movem_next[amask];
	}
	x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	ipl_fetch_next();
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 12+ (3/0) */
/* 4 0,0   */

/* MVMEL.L #<data>.W,(An)+ */
void REGPARAM2 op_4cd8_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 37;
	CurrentInstrCycles = 12; 
	ipl_fetch_now();
	uae_u16 mask = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
	uaecptr srca;
	srca = m68k_areg(regs, dstreg);
	if (srca & 1) {
		uaecptr srcav = srca;
		m68k_incpci(6);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	while (dmask) {
		uae_u32 v = (x_get_word(srca) << 16) | (m68k_dreg(regs, movem_index1[dmask]) & 0xffff);
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(6);
			exception2_read(opcode, srca + 0, 0x1, 1);
			return;
		}
		m68k_dreg(regs, movem_index1[dmask]) = v;
		v &= 0xffff0000;
		v |= x_get_word(srca + 2); 
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(6);
			exception2_read(opcode, srca + 2, 0x1, 1);
			return;
		}
		m68k_dreg(regs, movem_index1[dmask]) = v;
		srca += 4;
		dmask = movem_next[dmask];
	}
	while (amask) {
		uae_u32 v = (x_get_word(srca) << 16) | (m68k_areg(regs, movem_index1[amask]) & 0xffff);
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(6);
			exception2_read(opcode, srca + 0, 0x1, 1);
			return;
		}
		m68k_areg(regs, movem_index1[amask]) = v;
		v &= 0xffff0000;
		v |= x_get_word(srca + 2);
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(6);
			exception2_read(opcode, srca + 2, 0x1, 1);
			return;
		}
		m68k_areg(regs, movem_index1[amask]) = v;
		srca += 4;
		amask = movem_next[amask];
	}
	x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	m68k_areg(regs, dstreg) = srca;
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 12+ (3/0) */
/* 4 0,0   */

/* MVMEL.L #<data>.W,(d16,An) */
void REGPARAM2 op_4ce8_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 37;
	CurrentInstrCycles = 16; 
	uae_u16 mask = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
	uaecptr srca;
	srca = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return;
	}
	if (srca & 1) {
		uaecptr srcav = srca;
		m68k_incpci(8);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	while (dmask) {
		uae_u32 v = (x_get_word(srca) << 16) | (m68k_dreg(regs, movem_index1[dmask]) & 0xffff);
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(8);
			exception2_read(opcode, srca + 0, 0x1, 1);
			return;
		}
		m68k_dreg(regs, movem_index1[dmask]) = v;
		v &= 0xffff0000;
		v |= x_get_word(srca + 2); 
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(8);
			exception2_read(opcode, srca + 2, 0x1, 1);
			return;
		}
		m68k_dreg(regs, movem_index1[dmask]) = v;
		srca += 4;
		dmask = movem_next[dmask];
	}
	while (amask) {
		uae_u32 v = (x_get_word(srca) << 16) | (m68k_areg(regs, movem_index1[amask]) & 0xffff);
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(8);
			exception2_read(opcode, srca + 0, 0x1, 1);
			return;
		}
		m68k_areg(regs, movem_index1[amask]) = v;
		v &= 0xffff0000;
		v |= x_get_word(srca + 2);
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(8);
			exception2_read(opcode, srca + 2, 0x1, 1);
			return;
		}
		m68k_areg(regs, movem_index1[amask]) = v;
		srca += 4;
		amask = movem_next[amask];
	}
	x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	ipl_fetch_next();
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 16+ (4/0) */
/* 6 0,0   */

/* MVMEL.L #<data>.W,(d8,An,Xn) */
void REGPARAM2 op_4cf0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 37;
	CurrentInstrCycles = 18; 
	uae_u16 mask = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
	do_cycles_ce000_internal(2);
	uaecptr srca;
	srca = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_ce000_prefetch(6));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return;
	}
	if (srca & 1) {
		uaecptr srcav = srca;
		m68k_incpci(4);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	while (dmask) {
		uae_u32 v = (x_get_word(srca) << 16) | (m68k_dreg(regs, movem_index1[dmask]) & 0xffff);
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(8);
			exception2_read(opcode, srca + 0, 0x1, 1);
			return;
		}
		m68k_dreg(regs, movem_index1[dmask]) = v;
		v &= 0xffff0000;
		v |= x_get_word(srca + 2); 
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(8);
			exception2_read(opcode, srca + 2, 0x1, 1);
			return;
		}
		m68k_dreg(regs, movem_index1[dmask]) = v;
		srca += 4;
		dmask = movem_next[dmask];
	}
	while (amask) {
		uae_u32 v = (x_get_word(srca) << 16) | (m68k_areg(regs, movem_index1[amask]) & 0xffff);
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(8);
			exception2_read(opcode, srca + 0, 0x1, 1);
			return;
		}
		m68k_areg(regs, movem_index1[amask]) = v;
		v &= 0xffff0000;
		v |= x_get_word(srca + 2);
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(8);
			exception2_read(opcode, srca + 2, 0x1, 1);
			return;
		}
		m68k_areg(regs, movem_index1[amask]) = v;
		srca += 4;
		amask = movem_next[amask];
	}
	x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	ipl_fetch_next();
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 18+ (4/0) */
/* 6 4,0   */

/* MVMEL.L #<data>.W,(xxx).W */
void REGPARAM2 op_4cf8_14_ff(uae_u32 opcode)
{
	OpcodeFamily = 37;
	CurrentInstrCycles = 16; 
	uae_u16 mask = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return;
	}
	if (srca & 1) {
		uaecptr srcav = srca;
		m68k_incpci(8);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	while (dmask) {
		uae_u32 v = (x_get_word(srca) << 16) | (m68k_dreg(regs, movem_index1[dmask]) & 0xffff);
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(8);
			exception2_read(opcode, srca + 0, 0x1, 1);
			return;
		}
		m68k_dreg(regs, movem_index1[dmask]) = v;
		v &= 0xffff0000;
		v |= x_get_word(srca + 2); 
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(8);
			exception2_read(opcode, srca + 2, 0x1, 1);
			return;
		}
		m68k_dreg(regs, movem_index1[dmask]) = v;
		srca += 4;
		dmask = movem_next[dmask];
	}
	while (amask) {
		uae_u32 v = (x_get_word(srca) << 16) | (m68k_areg(regs, movem_index1[amask]) & 0xffff);
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(8);
			exception2_read(opcode, srca + 0, 0x1, 1);
			return;
		}
		m68k_areg(regs, movem_index1[amask]) = v;
		v &= 0xffff0000;
		v |= x_get_word(srca + 2);
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(8);
			exception2_read(opcode, srca + 2, 0x1, 1);
			return;
		}
		m68k_areg(regs, movem_index1[amask]) = v;
		srca += 4;
		amask = movem_next[amask];
	}
	x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	ipl_fetch_next();
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 16+ (4/0) */
/* 6 0,0   */

/* MVMEL.L #<data>.W,(xxx).L */
void REGPARAM2 op_4cf9_14_ff(uae_u32 opcode)
{
	OpcodeFamily = 37;
	CurrentInstrCycles = 20; 
	uae_u16 mask = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
	uaecptr srca;
	srca = get_word_ce000_prefetch(6) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return;
	}
	srca |= get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 8, pcoffset);
		return;
	}
	if (srca & 1) {
		uaecptr srcav = srca;
		m68k_incpci(10);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	while (dmask) {
		uae_u32 v = (x_get_word(srca) << 16) | (m68k_dreg(regs, movem_index1[dmask]) & 0xffff);
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(10);
			exception2_read(opcode, srca + 0, 0x1, 1);
			return;
		}
		m68k_dreg(regs, movem_index1[dmask]) = v;
		v &= 0xffff0000;
		v |= x_get_word(srca + 2); 
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(10);
			exception2_read(opcode, srca + 2, 0x1, 1);
			return;
		}
		m68k_dreg(regs, movem_index1[dmask]) = v;
		srca += 4;
		dmask = movem_next[dmask];
	}
	while (amask) {
		uae_u32 v = (x_get_word(srca) << 16) | (m68k_areg(regs, movem_index1[amask]) & 0xffff);
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(10);
			exception2_read(opcode, srca + 0, 0x1, 1);
			return;
		}
		m68k_areg(regs, movem_index1[amask]) = v;
		v &= 0xffff0000;
		v |= x_get_word(srca + 2);
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(10);
			exception2_read(opcode, srca + 2, 0x1, 1);
			return;
		}
		m68k_areg(regs, movem_index1[amask]) = v;
		srca += 4;
		amask = movem_next[amask];
	}
	x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(10);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	ipl_fetch_next();
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(10);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 10, pcoffset);
		return;
	}
	m68k_incpci(8);
	return;
}
/* 20+ (5/0) */
/* 8 0,0   */

/* MVMEL.L #<data>.W,(d16,PC) */
void REGPARAM2 op_4cfa_14_ff(uae_u32 opcode)
{
	uae_u32 dstreg = 2;
	OpcodeFamily = 37;
	CurrentInstrCycles = 16; 
	uae_u16 mask = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
	uaecptr srca;
	srca = m68k_getpci() + 4;
	srca += (uae_s32)(uae_s16)get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return;
	}
	if (srca & 1) {
		opcode |= 0x00020000;
		uaecptr srcav = srca;
		m68k_incpci(8);
		exception3_read_access(opcode, srca, 2, 2);
		return;
	}
	while (dmask) {
		uae_u32 v = (x_get_word(srca) << 16) | (m68k_dreg(regs, movem_index1[dmask]) & 0xffff);
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(8);
			exception2_read(opcode, srca + 0, 0x1, 2);
			return;
		}
		m68k_dreg(regs, movem_index1[dmask]) = v;
		v &= 0xffff0000;
		v |= x_get_word(srca + 2); 
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(8);
			exception2_read(opcode, srca + 2, 0x1, 2);
			return;
		}
		m68k_dreg(regs, movem_index1[dmask]) = v;
		srca += 4;
		dmask = movem_next[dmask];
	}
	while (amask) {
		uae_u32 v = (x_get_word(srca) << 16) | (m68k_areg(regs, movem_index1[amask]) & 0xffff);
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(8);
			exception2_read(opcode, srca + 0, 0x1, 2);
			return;
		}
		m68k_areg(regs, movem_index1[amask]) = v;
		v &= 0xffff0000;
		v |= x_get_word(srca + 2);
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(8);
			exception2_read(opcode, srca + 2, 0x1, 2);
			return;
		}
		m68k_areg(regs, movem_index1[amask]) = v;
		srca += 4;
		amask = movem_next[amask];
	}
	x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return;
	}
	ipl_fetch_next();
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 16+ (4/0) */
/* 6 0,0   */

/* MVMEL.L #<data>.W,(d8,PC,Xn) */
void REGPARAM2 op_4cfb_14_ff(uae_u32 opcode)
{
	uae_u32 dstreg = 3;
	OpcodeFamily = 37;
	CurrentInstrCycles = 18; 
	uae_u16 mask = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
	do_cycles_ce000_internal(2);
	uaecptr srca;
	uaecptr tmppc = m68k_getpci() + 4;
	srca = get_disp_ea_000(tmppc, get_word_ce000_prefetch(6));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, -2);
		return;
	}
	if (srca & 1) {
		opcode |= 0x00020000;
		uaecptr srcav = srca;
		m68k_incpci(4);
		exception3_read_access(opcode, srca, 2, 2);
		return;
	}
	while (dmask) {
		uae_u32 v = (x_get_word(srca) << 16) | (m68k_dreg(regs, movem_index1[dmask]) & 0xffff);
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(8);
			exception2_read(opcode, srca + 0, 0x1, 2);
			return;
		}
		m68k_dreg(regs, movem_index1[dmask]) = v;
		v &= 0xffff0000;
		v |= x_get_word(srca + 2); 
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(8);
			exception2_read(opcode, srca + 2, 0x1, 2);
			return;
		}
		m68k_dreg(regs, movem_index1[dmask]) = v;
		srca += 4;
		dmask = movem_next[dmask];
	}
	while (amask) {
		uae_u32 v = (x_get_word(srca) << 16) | (m68k_areg(regs, movem_index1[amask]) & 0xffff);
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(8);
			exception2_read(opcode, srca + 0, 0x1, 2);
			return;
		}
		m68k_areg(regs, movem_index1[amask]) = v;
		v &= 0xffff0000;
		v |= x_get_word(srca + 2);
		if(hardware_bus_error) {
			cpu_bus_rmw=false;
			m68k_incpci(8);
			exception2_read(opcode, srca + 2, 0x1, 2);
			return;
		}
		m68k_areg(regs, movem_index1[amask]) = v;
		srca += 4;
		amask = movem_next[amask];
	}
	x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return;
	}
	ipl_fetch_next();
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 18+ (4/0) */
/* 6 4,0   */

/* LINK.W An,#<data>.W */
void REGPARAM2 op_4e50_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 47;
	CurrentInstrCycles = 16; 
	ipl_fetch_now();
	uae_s32 src = m68k_areg(regs, srcreg);
	uaecptr olda;
	olda = m68k_areg(regs, 7) - 4;
	m68k_areg(regs, 7) = olda;
	uae_s16 offs = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		m68k_areg(regs, 7) += 4;
		exception2_fetch(opcode, 4, 2);
		return;
	}
	if (olda & 1) {
		m68k_areg(regs, 7) += 4;
		m68k_areg(regs, srcreg) = olda;
		m68k_incpci(6);
		exception3_write_access(opcode, olda, sz_word, src >> 16, 1);
		return;
	}
	x_put_word(olda, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		m68k_areg(regs, 7) += 4;
		m68k_areg(regs, srcreg) = olda;
		exception2_write(opcode, olda + 0, 0x1, src >> 16, 1);
		return;
	}
	x_put_word(olda + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		m68k_areg(regs, 7) += 4;
		m68k_areg(regs, srcreg) = olda;
		exception2_write(opcode, olda + 2, 0x1, src, 1);
		return;
	}
	m68k_areg(regs, srcreg) = (m68k_areg(regs, 7));
	m68k_areg(regs, 7) += offs;
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (2/2) */
/* 4 0,0   */

/* UNLK.L An */
void REGPARAM2 op_4e58_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 48;
	CurrentInstrCycles = 12; 
	ipl_fetch_now();
	uae_s32 src = m68k_areg(regs, srcreg);
	uae_u32 olda = src;
	if (olda & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, olda, 2, 1);
		return;
	}
	uae_s32 old = x_get_word(olda) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, olda + 0, 0x1, 1);
		return;
	}
	old |= x_get_word(olda + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, olda + 2, 0x1, 1);
		return;
	}
	m68k_areg(regs, 7) = src + 4;
	m68k_areg(regs, srcreg) = (old);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 12 (3/0) */
/* 2 0,0   */

/* MVR2USP.L An */
void REGPARAM2 op_4e60_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 40;
	CurrentInstrCycles = 4;  
	if (!regs.s) {
		Exception(8);
		return;
	}
	uae_s32 src = m68k_areg(regs, srcreg);
	regs.usp = src;
	regs.ir = regs.irc;
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 4 (1/0) */
/* 2 0,0   */

/* MVUSP2R.L An */
void REGPARAM2 op_4e68_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 41;
	CurrentInstrCycles = 4;  
	if (!regs.s) {
		Exception(8);
		return;
	}
	m68k_areg(regs, srcreg) = (regs.usp);
	regs.ir = regs.irc;
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 4 (1/0) */
/* 2 0,0   */

/* RESET.L  */
void REGPARAM2 op_4e70_14_ff(uae_u32 opcode)
{
	OpcodeFamily = 42;
	CurrentInstrCycles = 132;
	if (!regs.s) {
		Exception(8);
		return;
	}
	bool r = cpureset();
	do_cycles_ce000_internal(128);
	if (r) {
		return;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 132 (1/0) */
/* 2 0,0   */

/* NOP.L  */
void REGPARAM2 op_4e71_14_ff(uae_u32 opcode)
{
	OpcodeFamily = 43;
	CurrentInstrCycles = 4;  
	regs.ir = regs.irc;
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 4 (1/0) */
/* 2 0,0   */

/* STOP.L #<data>.W */
void REGPARAM2 op_4e72_14_ff(uae_u32 opcode)
{
	OpcodeFamily = 44;
	CurrentInstrCycles = 4;  
	if (!regs.s) {
		Exception(8);
		return;
	}
	if (!regs.stopped) {
		uae_u16 src = regs.irc;
		regs.irc = src;
	}
	uae_u16 sr = regs.irc;
	ipl_fetch_next();
	checkint();
	regs.sr = sr;
	MakeFromSR_STOP();
	do_cycles_stop(4);
	m68k_setstopped(1);
	return;
}
/* 4 (0/0) */

/* RTE.L  */
void REGPARAM2 op_4e73_14_ff(uae_u32 opcode)
{
	OpcodeFamily = 45;
	CurrentInstrCycles = 20; 
	if (!regs.s) {
		Exception(8);
		return;
	}
	if (m68k_areg(regs, 7) & 1) {
		exception3_read_access(opcode, m68k_areg(regs, 7), 1, 1);
		return;
	}
	uaecptr oldpc = m68k_getpci();
	uaecptr a = m68k_areg(regs, 7);
	uae_u16 sr = x_get_word(a);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		exception2_read(opcode, a + 0, 0x1, 1);
		return;
	}
	m68k_areg(regs, 7) += 6;
	uae_u32 pc = x_get_word(a + 2) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		exception2_read(opcode, a + 2, 0x1, 1);
		return;
	}
	pc |= x_get_word(a + 2 + 2); 
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		exception2_read(opcode, a + 4, 0x1, 1);
		return;
	}
	uae_u16 oldt1 = regs.t1;
	regs.sr = sr;
	MakeFromSR();
	if (pc & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode | 0x20000, pc, 1, 2);
		return;
	}
	m68k_setpci_j(pc);
	opcode |= 0x20000;
	#ifdef DEBUGGER
	branch_stack_pop_rte(oldpc);
	#endif
	int pcadjust = oldpc - m68k_getpci() + 2;
	get_word_ce000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		pcoffset += pcadjust;
		exception2_fetch_opcode(opcode, 0, pcoffset);
		return;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	if(oldt1) opcode |= 0x10000;
	ipl_fetch_next();
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 20 (5/0) */
/* 2 0,0 B */

/* RTS.L  */
void REGPARAM2 op_4e75_14_ff(uae_u32 opcode)
{
	OpcodeFamily = 49;
	CurrentInstrCycles = 16; 
	uaecptr oldpc = m68k_getpci();
	if (m68k_areg(regs, 7) & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, m68k_areg(regs, 7), 1, 1);
		return;
	}
	uaecptr newpc, dsta = m68k_areg(regs, 7);
	newpc = x_get_word(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	newpc |= x_get_word(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return;
	}
	m68k_areg(regs, 7) += 4;
	m68k_setpci_j(newpc);
	#ifdef DEBUGGER
	if (debugmem_trace) {
		branch_stack_pop_rts(oldpc);
	}
	#endif
	if (m68k_getpci() & 1) {
		uaecptr faultpc = m68k_getpci();
		m68k_setpci_j(oldpc);
		m68k_incpci(2);
		exception3_read_prefetch_only(opcode, faultpc);
		return;
	}
	int pcadjust = oldpc - m68k_getpci() + 2;
	get_word_ce000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		pcoffset += pcadjust;
		exception2_fetch_opcode(opcode, 0, pcoffset);
		return;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	if(regs.t1) opcode |= 0x10000;
	ipl_fetch_next();
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 16 (4/0) */
/* 2 0,0 B */

/* TRAPV.L  */
void REGPARAM2 op_4e76_14_ff(uae_u32 opcode)
{
	OpcodeFamily = 50;
	CurrentInstrCycles = 4;  
	m68k_incpci(2);
	uae_u16 opcode_v = opcode;
	int ipl0 = regs.ipl[0];
	int ipl1 = regs.ipl[1];
	regs.ir = regs.irc;
	opcode |= 0x20000;
	ipl_fetch_next();
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (GET_VFLG()) {
			MakeSR();
			regs.sr |= 0x2000;
			regs.sr &= ~0x8000;
			MakeFromSR();
			pcoffset -= 2;
		} else {
			opcode = regs.ir | 0x20000;
			if(regs.t1) opcode |= 0x10000;
		}
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	opcode = regs.ir;
	if (GET_VFLG()) {
		regs.ipl[0] = ipl0;
		regs.ipl[1] = ipl1;
		regs.ir = opcode_v;
		Exception_cpu(7);
		return;
	}
	return;
}
/* 4 (1/0) */
/* 2 0,0   */

/* RTR.L  */
void REGPARAM2 op_4e77_14_ff(uae_u32 opcode)
{
	OpcodeFamily = 51;
	CurrentInstrCycles = 20; 
	if (m68k_areg(regs, 7) & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, m68k_areg(regs, 7), 1, 1);
		return;
	}
	uaecptr oldpc = m68k_getpci();
	MakeSR();
	uaecptr sra;
	sra = m68k_areg(regs, 7);
	if (sra & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, sra, 1, 1);
		return;
	}
	uae_s16 sr = x_get_word(sra);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, sra + 0, 0x1, 1);
		return;
	}
	m68k_areg(regs, 7) += 2;
	uaecptr pca;
	pca = m68k_areg(regs, 7);
	if (pca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, pca, 2, 1);
		return;
	}
	uae_s32 pc = x_get_word(pca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, pca + 0, 0x1, 1);
		return;
	}
	pc |= x_get_word(pca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, pca + 2, 0x1, 1);
		return;
	}
	m68k_areg(regs, 7) += 4;
	regs.sr &= 0xFF00; sr &= 0xFF;
	regs.sr |= sr;
	MakeFromSR();
	m68k_setpci_j(pc);
	if (m68k_getpci() & 1) {
		uaecptr faultpc = m68k_getpci();
		m68k_setpci_j(oldpc + 2);
		exception3_read_prefetch_only(opcode, faultpc);
		return;
	}
	int pcadjust = oldpc - m68k_getpci() + 2;
	get_word_ce000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		pcoffset += pcadjust;
		exception2_fetch_opcode(opcode, 0, pcoffset);
		return;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	if(regs.t1) opcode |= 0x10000;
	ipl_fetch_next();
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 20 (5/0) */
/* 2 0,0 B */

/* JSR.L (An) */
void REGPARAM2 op_4e90_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 52;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	ipl_fetch_now();
	uaecptr oldpc = m68k_getpci();
	uaecptr nextpc = oldpc + 2;
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_prefetch_only(opcode, srca);
		return;
	}
	m68k_setpci_j(srca);
	get_word_ce000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		pcoffset = (oldpc - srca) + 2;
		exception2_fetch_opcode(opcode, 0, pcoffset);
		return;
	}
	m68k_areg(regs, 7) -= 4;
	if (m68k_areg(regs, 7) & 1) {
		m68k_setpci_j(oldpc);
		m68k_incpci(2);
		exception3_write_access(opcode, m68k_areg(regs, 7), 1, m68k_areg(regs, 7) >> 16, 1);
		return;
	}
	uaecptr dsta = m68k_areg(regs, 7);
	x_put_word(dsta, nextpc >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_write(opcode, dsta + 0, 0x1, nextpc >> 16, 1);
		return;
	}
	x_put_word(dsta + 2, nextpc);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_write(opcode, dsta + 2, 0x1, nextpc, 1);
		return;
	}
	#ifdef DEBUGGER
	if (debugmem_trace) {
		branch_stack_push(oldpc, nextpc);
	}
	#endif
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, 0);
		return;
	}
	return;
}
/* 16 (2/2) */
/* 2 0,0 B */

/* JSR.L (d16,An) */
void REGPARAM2 op_4ea8_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 52;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)regs.irc;
	ipl_fetch_now();
	uaecptr oldpc = m68k_getpci();
	uaecptr nextpc = oldpc + 4;
	if (srca & 1) {
		do_cycles_ce000_internal(2);
		m68k_incpci(2);
		exception3_read_prefetch_only(opcode, srca);
		return;
	}
	do_cycles_ce000_internal(2);
	m68k_setpci_j(srca);
	get_word_ce000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		pcoffset = (oldpc - srca) + 4;
		exception2_fetch_opcode(opcode, 0, pcoffset);
		return;
	}
	m68k_areg(regs, 7) -= 4;
	if (m68k_areg(regs, 7) & 1) {
		m68k_setpci_j(oldpc);
		m68k_incpci(4);
		exception3_write_access(opcode, m68k_areg(regs, 7), 1, m68k_areg(regs, 7) >> 16, 1);
		return;
	}
	uaecptr dsta = m68k_areg(regs, 7);
	x_put_word(dsta, nextpc >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_write(opcode, dsta + 0, 0x1, nextpc >> 16, 1);
		return;
	}
	x_put_word(dsta + 2, nextpc);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_write(opcode, dsta + 2, 0x1, nextpc, 1);
		return;
	}
	#ifdef DEBUGGER
	if (debugmem_trace) {
		branch_stack_push(oldpc, nextpc);
	}
	#endif
	regs.ir = regs.irc;
	opcode = regs.ir;
	if(regs.t1) opcode |= 0x10000;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, 0);
		return;
	}
	return;
}
/* 18 (2/2) */
/* 4 0,0 B */

/* JSR.L (d8,An,Xn) */
void REGPARAM2 op_4eb0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 52;
	CurrentInstrCycles = 22; 
	uaecptr srca;
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), regs.irc);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, 0);
		return;
	}
	ipl_fetch_now();
	uaecptr oldpc = m68k_getpci();
	uaecptr nextpc = oldpc + 2;
	if (srca & 1) {
		do_cycles_ce000_internal(6);
		m68k_incpci(2);
		exception3_read_prefetch_only(opcode, srca);
		return;
	}
	do_cycles_ce000_internal(6);
	nextpc += 2;
	m68k_setpci_j(srca);
	get_word_ce000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		pcoffset = (oldpc - srca) + 4;
		exception2_fetch_opcode(opcode, 0, pcoffset);
		return;
	}
	m68k_areg(regs, 7) -= 4;
	if (m68k_areg(regs, 7) & 1) {
		m68k_setpci_j(oldpc);
		m68k_incpci(4);
		exception3_write_access(opcode, m68k_areg(regs, 7), 1, m68k_areg(regs, 7) >> 16, 1);
		return;
	}
	uaecptr dsta = m68k_areg(regs, 7);
	x_put_word(dsta, nextpc >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_write(opcode, dsta + 0, 0x1, nextpc >> 16, 1);
		return;
	}
	x_put_word(dsta + 2, nextpc);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_write(opcode, dsta + 2, 0x1, nextpc, 1);
		return;
	}
	#ifdef DEBUGGER
	if (debugmem_trace) {
		branch_stack_push(oldpc, nextpc);
	}
	#endif
	regs.ir = regs.irc;
	opcode = regs.ir;
	if(regs.t1) opcode |= 0x10000;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, 0);
		return;
	}
	return;
}
/* 22 (2/2) */
/* 2 2,0 B */

/* JSR.L (xxx).W */
void REGPARAM2 op_4eb8_14_ff(uae_u32 opcode)
{
	OpcodeFamily = 52;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)regs.irc;
	ipl_fetch_now();
	uaecptr oldpc = m68k_getpci();
	uaecptr nextpc = oldpc + 4;
	if (srca & 1) {
		do_cycles_ce000_internal(2);
		m68k_incpci(4);
		exception3_read_prefetch_only(opcode, srca);
		return;
	}
	do_cycles_ce000_internal(2);
	m68k_setpci_j(srca);
	get_word_ce000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		pcoffset = (oldpc - srca) + 4;
		exception2_fetch_opcode(opcode, 0, pcoffset);
		return;
	}
	m68k_areg(regs, 7) -= 4;
	if (m68k_areg(regs, 7) & 1) {
		m68k_setpci_j(oldpc);
		m68k_incpci(4);
		exception3_write_access(opcode, m68k_areg(regs, 7), 1, m68k_areg(regs, 7) >> 16, 1);
		return;
	}
	uaecptr dsta = m68k_areg(regs, 7);
	x_put_word(dsta, nextpc >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x1, nextpc >> 16, 1);
		return;
	}
	x_put_word(dsta + 2, nextpc);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 2, 0x1, nextpc, 1);
		return;
	}
	#ifdef DEBUGGER
	if (debugmem_trace) {
		branch_stack_push(oldpc, nextpc);
	}
	#endif
	regs.ir = regs.irc;
	opcode = regs.ir;
	if(regs.t1) opcode |= 0x10000;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, 0);
		return;
	}
	return;
}
/* 18 (2/2) */
/* 4 0,0 B */

/* JSR.L (xxx).L */
void REGPARAM2 op_4eb9_14_ff(uae_u32 opcode)
{
	OpcodeFamily = 52;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	srca = get_word_ce000_prefetch(4) << 16;
	srca |= regs.irc;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	ipl_fetch_now();
	uaecptr oldpc = m68k_getpci();
	uaecptr nextpc = oldpc + 6;
	if (srca & 1) {
		m68k_incpci(6);
		exception3_read_prefetch_only(opcode, srca);
		return;
	}
	m68k_setpci_j(srca);
	get_word_ce000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		pcoffset = (oldpc - srca) + 6;
		exception2_fetch_opcode(opcode, 0, pcoffset);
		return;
	}
	m68k_areg(regs, 7) -= 4;
	if (m68k_areg(regs, 7) & 1) {
		m68k_setpci_j(oldpc);
		m68k_incpci(6);
		exception3_write_access(opcode, m68k_areg(regs, 7), 1, m68k_areg(regs, 7) >> 16, 1);
		return;
	}
	uaecptr dsta = m68k_areg(regs, 7);
	x_put_word(dsta, nextpc >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, nextpc >> 16, 1);
		return;
	}
	x_put_word(dsta + 2, nextpc);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 2, 0x1, nextpc, 1);
		return;
	}
	#ifdef DEBUGGER
	if (debugmem_trace) {
		branch_stack_push(oldpc, nextpc);
	}
	#endif
	regs.ir = regs.irc;
	opcode = regs.ir;
	if(regs.t1) opcode |= 0x10000;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, 0);
		return;
	}
	return;
}
/* 20 (3/2) */
/* 6 0,0 B */

/* JSR.L (d16,PC) */
void REGPARAM2 op_4eba_14_ff(uae_u32 opcode)
{
	OpcodeFamily = 52;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	srca = m68k_getpci() + 2;
	srca += (uae_s32)(uae_s16)regs.irc;
	ipl_fetch_now();
	uaecptr oldpc = m68k_getpci();
	uaecptr nextpc = oldpc + 4;
	if (srca & 1) {
		do_cycles_ce000_internal(2);
		m68k_incpci(2);
		exception3_read_prefetch_only(opcode, srca);
		return;
	}
	do_cycles_ce000_internal(2);
	m68k_setpci_j(srca);
	get_word_ce000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		pcoffset = (oldpc - srca) + 4;
		exception2_fetch_opcode(opcode, 0, pcoffset);
		return;
	}
	m68k_areg(regs, 7) -= 4;
	if (m68k_areg(regs, 7) & 1) {
		m68k_setpci_j(oldpc);
		m68k_incpci(4);
		exception3_write_access(opcode, m68k_areg(regs, 7), 1, m68k_areg(regs, 7) >> 16, 1);
		return;
	}
	uaecptr dsta = m68k_areg(regs, 7);
	x_put_word(dsta, nextpc >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_write(opcode, dsta + 0, 0x1, nextpc >> 16, 1);
		return;
	}
	x_put_word(dsta + 2, nextpc);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_write(opcode, dsta + 2, 0x1, nextpc, 1);
		return;
	}
	#ifdef DEBUGGER
	if (debugmem_trace) {
		branch_stack_push(oldpc, nextpc);
	}
	#endif
	regs.ir = regs.irc;
	opcode = regs.ir;
	if(regs.t1) opcode |= 0x10000;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, 0);
		return;
	}
	return;
}
/* 18 (2/2) */
/* 4 0,0 B */

/* JSR.L (d8,PC,Xn) */
void REGPARAM2 op_4ebb_14_ff(uae_u32 opcode)
{
	OpcodeFamily = 52;
	CurrentInstrCycles = 22; 
	uaecptr srca;
	uaecptr tmppc = m68k_getpci() + 2;
	srca = get_disp_ea_000(tmppc, regs.irc);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, 0);
		return;
	}
	ipl_fetch_now();
	uaecptr oldpc = m68k_getpci();
	uaecptr nextpc = oldpc + 2;
	if (srca & 1) {
		do_cycles_ce000_internal(6);
		m68k_incpci(2);
		exception3_read_prefetch_only(opcode, srca);
		return;
	}
	do_cycles_ce000_internal(6);
	nextpc += 2;
	m68k_setpci_j(srca);
	get_word_ce000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		pcoffset = (oldpc - srca) + 4;
		exception2_fetch_opcode(opcode, 0, pcoffset);
		return;
	}
	m68k_areg(regs, 7) -= 4;
	if (m68k_areg(regs, 7) & 1) {
		m68k_setpci_j(oldpc);
		m68k_incpci(4);
		exception3_write_access(opcode, m68k_areg(regs, 7), 1, m68k_areg(regs, 7) >> 16, 1);
		return;
	}
	uaecptr dsta = m68k_areg(regs, 7);
	x_put_word(dsta, nextpc >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_write(opcode, dsta + 0, 0x1, nextpc >> 16, 1);
		return;
	}
	x_put_word(dsta + 2, nextpc);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_write(opcode, dsta + 2, 0x1, nextpc, 1);
		return;
	}
	#ifdef DEBUGGER
	if (debugmem_trace) {
		branch_stack_push(oldpc, nextpc);
	}
	#endif
	regs.ir = regs.irc;
	opcode = regs.ir;
	if(regs.t1) opcode |= 0x10000;
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, 0);
		return;
	}
	return;
}
/* 22 (2/2) */
/* 2 2,0 B */

/* JMP.L (An) */
void REGPARAM2 op_4ed0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 53;
	CurrentInstrCycles = 8;  
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	ipl_fetch_now();
	uaecptr oldpc = m68k_getpci();
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_prefetch_only(opcode, srca);
		return;
	}
	m68k_setpci_j(srca);
	get_word_ce000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		pcoffset = (oldpc - srca) + 2;
		exception2_fetch_opcode(opcode, 0, pcoffset);
		return;
	}
	regs.ir = regs.irc;
	get_word_ce000_prefetch(2);
	opcode = regs.ir;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, 0);
		return;
	}
	return;
}
/* 8 (2/0) */
/* 2 0,0 B */

/* JMP.L (d16,An) */
void REGPARAM2 op_4ee8_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 53;
	CurrentInstrCycles = 10; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)regs.irc;
	ipl_fetch_now();
	uaecptr oldpc = m68k_getpci();
	if (srca & 1) {
		do_cycles_ce000_internal(2);
		m68k_incpci(2);
		exception3_read_prefetch_only(opcode, srca);
		return;
	}
	do_cycles_ce000_internal(2);
	m68k_setpci_j(srca);
	get_word_ce000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		pcoffset = (oldpc - srca) + 2;
		exception2_fetch_opcode(opcode, 0, pcoffset);
		return;
	}
	regs.ir = regs.irc;
	get_word_ce000_prefetch(2);
	opcode = regs.ir;
	if(regs.t1) opcode |= 0x10000;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, 0);
		return;
	}
	return;
}
/* 10 (2/0) */
/* 4 0,0 B */

/* JMP.L (d8,An,Xn) */
void REGPARAM2 op_4ef0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 53;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), regs.irc);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, 0);
		return;
	}
	ipl_fetch_now();
	uaecptr oldpc = m68k_getpci();
	if (srca & 1) {
		do_cycles_ce000_internal(6);
		m68k_incpci(2);
		exception3_read_prefetch_only(opcode, srca);
		return;
	}
	do_cycles_ce000_internal(6);
	m68k_setpci_j(srca);
	get_word_ce000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		pcoffset = (oldpc - srca) + 2;
		exception2_fetch_opcode(opcode, 0, pcoffset);
		return;
	}
	regs.ir = regs.irc;
	get_word_ce000_prefetch(2);
	opcode = regs.ir;
	if(regs.t1) opcode |= 0x10000;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, 0);
		return;
	}
	return;
}
/* 14 (2/0) */
/* 2 2,0 B */

/* JMP.L (xxx).W */
void REGPARAM2 op_4ef8_14_ff(uae_u32 opcode)
{
	OpcodeFamily = 53;
	CurrentInstrCycles = 10; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)regs.irc;
	ipl_fetch_now();
	uaecptr oldpc = m68k_getpci();
	if (srca & 1) {
		do_cycles_ce000_internal(2);
		m68k_incpci(2);
		exception3_read_prefetch_only(opcode, srca);
		return;
	}
	do_cycles_ce000_internal(2);
	m68k_setpci_j(srca);
	get_word_ce000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		pcoffset = (oldpc - srca) + 2;
		exception2_fetch_opcode(opcode, 0, pcoffset);
		return;
	}
	regs.ir = regs.irc;
	get_word_ce000_prefetch(2);
	opcode = regs.ir;
	if(regs.t1) opcode |= 0x10000;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, 0);
		return;
	}
	return;
}
/* 10 (2/0) */
/* 4 0,0 B */

/* JMP.L (xxx).L */
void REGPARAM2 op_4ef9_14_ff(uae_u32 opcode)
{
	OpcodeFamily = 53;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = get_word_ce000_prefetch(4) << 16;
	srca |= regs.irc;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	ipl_fetch_now();
	uaecptr oldpc = m68k_getpci();
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_prefetch_only(opcode, srca);
		return;
	}
	m68k_setpci_j(srca);
	get_word_ce000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		pcoffset = (oldpc - srca) + 2;
		exception2_fetch_opcode(opcode, 0, pcoffset);
		return;
	}
	regs.ir = regs.irc;
	get_word_ce000_prefetch(2);
	opcode = regs.ir;
	if(regs.t1) opcode |= 0x10000;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, 0);
		return;
	}
	return;
}
/* 12 (3/0) */
/* 6 0,0 B */

/* JMP.L (d16,PC) */
void REGPARAM2 op_4efa_14_ff(uae_u32 opcode)
{
	OpcodeFamily = 53;
	CurrentInstrCycles = 10; 
	uaecptr srca;
	srca = m68k_getpci() + 2;
	srca += (uae_s32)(uae_s16)regs.irc;
	ipl_fetch_now();
	uaecptr oldpc = m68k_getpci();
	if (srca & 1) {
		do_cycles_ce000_internal(2);
		m68k_incpci(2);
		exception3_read_prefetch_only(opcode, srca);
		return;
	}
	do_cycles_ce000_internal(2);
	m68k_setpci_j(srca);
	get_word_ce000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		pcoffset = (oldpc - srca) + 2;
		exception2_fetch_opcode(opcode, 0, pcoffset);
		return;
	}
	regs.ir = regs.irc;
	get_word_ce000_prefetch(2);
	opcode = regs.ir;
	if(regs.t1) opcode |= 0x10000;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, 0);
		return;
	}
	return;
}
/* 10 (2/0) */
/* 4 0,0 B */

/* JMP.L (d8,PC,Xn) */
void REGPARAM2 op_4efb_14_ff(uae_u32 opcode)
{
	OpcodeFamily = 53;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	uaecptr tmppc = m68k_getpci() + 2;
	srca = get_disp_ea_000(tmppc, regs.irc);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, 0);
		return;
	}
	ipl_fetch_now();
	uaecptr oldpc = m68k_getpci();
	if (srca & 1) {
		do_cycles_ce000_internal(6);
		m68k_incpci(2);
		exception3_read_prefetch_only(opcode, srca);
		return;
	}
	do_cycles_ce000_internal(6);
	m68k_setpci_j(srca);
	get_word_ce000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		pcoffset = (oldpc - srca) + 2;
		exception2_fetch_opcode(opcode, 0, pcoffset);
		return;
	}
	regs.ir = regs.irc;
	get_word_ce000_prefetch(2);
	opcode = regs.ir;
	if(regs.t1) opcode |= 0x10000;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, 0);
		return;
	}
	return;
}
/* 14 (2/0) */
/* 2 2,0 B */

/* ADDQ.B #<data>,Dn */
void REGPARAM2 op_5000_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 4;  
	uae_u32 src = srcreg;
	uae_s8 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u8)(~dst)) < ((uae_u8)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 4 (1/0) */
/* 2 0,0   */

/* ADDQ.B #<data>,(An) */
void REGPARAM2 op_5010_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 12; 
	uae_u32 src = srcreg;
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u8)(~dst)) < ((uae_u8)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_byte(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, newv, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 12 (2/1) */
/* 2 0,0   */

/* ADDQ.B #<data>,(An)+ */
void REGPARAM2 op_5018_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 12; 
	uae_u32 src = srcreg;
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
	uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u8)(~dst)) < ((uae_u8)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_byte(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, newv, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 12 (2/1) */
/* 2 0,0   */

/* ADDQ.B #<data>,-(An) */
void REGPARAM2 op_5020_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 14; 
	uae_u32 src = srcreg;
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
	do_cycles_ce000_internal(2);
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, dstreg) = dsta;
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	m68k_areg(regs, dstreg) = dsta;
	uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u8)(~dst)) < ((uae_u8)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_byte(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, newv, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 14 (2/1) */
/* 2 0,0   */

/* ADDQ.B #<data>,(d16,An) */
void REGPARAM2 op_5028_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 16; 
	uae_u32 src = srcreg;
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u8)(~dst)) < ((uae_u8)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_byte(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, newv, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* ADDQ.B #<data>,(d8,An,Xn) */
void REGPARAM2 op_5030_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 18; 
	uae_u32 src = srcreg;
	uaecptr dsta;
	do_cycles_ce000_internal(2);
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u8)(~dst)) < ((uae_u8)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_byte(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, newv, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 18 (3/1) */
/* 4 4,0   */

/* ADDQ.B #<data>,(xxx).W */
void REGPARAM2 op_5038_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	OpcodeFamily = 11;
	CurrentInstrCycles = 16; 
	uae_u32 src = srcreg;
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u8)(~dst)) < ((uae_u8)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_byte(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, newv, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* ADDQ.B #<data>,(xxx).L */
void REGPARAM2 op_5039_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	OpcodeFamily = 11;
	CurrentInstrCycles = 20; 
	uae_u32 src = srcreg;
	uaecptr dsta;
	dsta = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	dsta |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u8)(~dst)) < ((uae_u8)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_byte(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, newv, 1);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 20 (4/1) */
/* 6 0,0   */

/* ADDQ.W #<data>,Dn */
void REGPARAM2 op_5040_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 4;  
	uae_u32 src = srcreg;
	uae_s16 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 4 (1/0) */
/* 2 0,0   */

/* ADDAQ.W #<data>,An */
void REGPARAM2 op_5048_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 12;
	CurrentInstrCycles = 8;  
	uae_u32 src = srcreg;
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = dst + src;
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		areg_68000_long_replace_low(dstreg, newv);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	do_cycles_ce000_internal(4);
	m68k_areg(regs, dstreg) = (newv);
	m68k_incpci(2);
	return;
}
/* 8 (1/0) */
/* 2 0,0   */

/* ADDQ.W #<data>,(An) */
void REGPARAM2 op_5050_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 12; 
	uae_u32 src = srcreg;
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	if (dsta & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dsta, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 dst = x_get_word(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_word(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x1, newv, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 12 (2/1) */
/* 2 0,0   */

/* ADDQ.W #<data>,(An)+ */
void REGPARAM2 op_5058_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 12; 
	uae_u32 src = srcreg;
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	if (dsta & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dsta, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 dst = x_get_word(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, dstreg) += 2 + 0;
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	m68k_areg(regs, dstreg) += 2;
	uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_word(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x1, newv, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 12 (2/1) */
/* 2 0,0   */

/* ADDQ.W #<data>,-(An) */
void REGPARAM2 op_5060_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 14; 
	uae_u32 src = srcreg;
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - 2;
	do_cycles_ce000_internal(2);
	if (dsta & 1) {
		m68k_incpci(4);
		m68k_areg(regs, dstreg) = dsta;
		exception3_read_access(opcode, dsta, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 dst = x_get_word(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, dstreg) = dsta;
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	m68k_areg(regs, dstreg) = dsta;
	uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_word(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x1, newv, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 14 (2/1) */
/* 2 0,0   */

/* ADDQ.W #<data>,(d16,An) */
void REGPARAM2 op_5068_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 16; 
	uae_u32 src = srcreg;
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dsta, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 dst = x_get_word(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_word(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x1, newv, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* ADDQ.W #<data>,(d8,An,Xn) */
void REGPARAM2 op_5070_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 18; 
	uae_u32 src = srcreg;
	uaecptr dsta;
	do_cycles_ce000_internal(2);
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dsta, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 dst = x_get_word(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_word(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x1, newv, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 18 (3/1) */
/* 4 4,0   */

/* ADDQ.W #<data>,(xxx).W */
void REGPARAM2 op_5078_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	OpcodeFamily = 11;
	CurrentInstrCycles = 16; 
	uae_u32 src = srcreg;
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, dsta, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 dst = x_get_word(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_word(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x1, newv, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* ADDQ.W #<data>,(xxx).L */
void REGPARAM2 op_5079_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	OpcodeFamily = 11;
	CurrentInstrCycles = 20; 
	uae_u32 src = srcreg;
	uaecptr dsta;
	dsta = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	dsta |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, dsta, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 dst = x_get_word(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_word(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x1, newv, 1);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 20 (4/1) */
/* 6 0,0   */

/* ADDQ.L #<data>,Dn */
void REGPARAM2 op_5080_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 8;  
	uae_u32 src = srcreg;
	uae_s32 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u32)(~dst)) < ((uae_u32)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		uae_s16 bnewv = (uae_s16)dst + (uae_s16)src;
		int bflgs = ((uae_s16)(src)) < 0;
		int bflgo = ((uae_s16)(dst)) < 0;
		int bflgn = bnewv < 0;
		ccr_68000_long_move_ae_LZN(bnewv);
		SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
		SET_XFLG(GET_CFLG());
		SET_VFLG((bflgs ^ bflgn) & (bflgo ^ bflgn));
		dreg_68000_long_replace_low(dstreg, bnewv);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	do_cycles_ce000_internal(4);
	m68k_dreg(regs, dstreg) = (newv);
	m68k_incpci(2);
	return;
}
/* 8 (1/0) */
/* 2 0,0   */

/* ADDAQ.L #<data>,An */
void REGPARAM2 op_5088_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 12;
	CurrentInstrCycles = 8;  
	uae_u32 src = srcreg;
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = dst + src;
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		areg_68000_long_replace_low(dstreg, newv);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	do_cycles_ce000_internal(4);
	m68k_areg(regs, dstreg) = (newv);
	m68k_incpci(2);
	return;
}
/* 8 (1/0) */
/* 2 0,0   */

/* ADDQ.L #<data>,(An) */
void REGPARAM2 op_5090_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 20; 
	uae_u32 src = srcreg;
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	if (dsta & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dsta, 2, 1);
		return;
	}
	uae_s32 dst = x_get_word(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	dst |= x_get_word(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return;
	}
	uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u32)(~dst)) < ((uae_u32)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		uae_s16 bnewv = (uae_s16)dst + (uae_s16)src;
		int bflgs = ((uae_s16)(src)) < 0;
		int bflgo = ((uae_s16)(dst)) < 0;
		int bflgn = bnewv < 0;
		ccr_68000_long_move_ae_LZN(bnewv);
		SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
		SET_XFLG(GET_CFLG());
		SET_VFLG((bflgs ^ bflgn) & (bflgo ^ bflgn));
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	x_put_word(dsta + 2, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 2, 0x1, newv, 1);
		return;
	}
	x_put_word(dsta, newv >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x1, newv >> 16, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 20 (3/2) */
/* 2 0,0   */

/* ADDQ.L #<data>,(An)+ */
void REGPARAM2 op_5098_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 20; 
	uae_u32 src = srcreg;
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	if (dsta & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dsta, 2, 1);
		return;
	}
	uae_s32 dst = x_get_word(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	dst |= x_get_word(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return;
	}
	m68k_areg(regs, dstreg) += 4;
	uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u32)(~dst)) < ((uae_u32)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		uae_s16 bnewv = (uae_s16)dst + (uae_s16)src;
		int bflgs = ((uae_s16)(src)) < 0;
		int bflgo = ((uae_s16)(dst)) < 0;
		int bflgn = bnewv < 0;
		ccr_68000_long_move_ae_LZN(bnewv);
		SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
		SET_XFLG(GET_CFLG());
		SET_VFLG((bflgs ^ bflgn) & (bflgo ^ bflgn));
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	x_put_word(dsta + 2, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 2, 0x1, newv, 1);
		return;
	}
	x_put_word(dsta, newv >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x1, newv >> 16, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 20 (3/2) */
/* 2 0,0   */

/* ADDQ.L #<data>,-(An) */
void REGPARAM2 op_50a0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 22; 
	uae_u32 src = srcreg;
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - 4;
	do_cycles_ce000_internal(2);
	if (dsta & 1) {
		m68k_incpci(2);
		m68k_areg(regs, dstreg) = dsta;
		exception3_read_access(opcode, dsta, 2, 1);
		return;
	}
	uae_s32 dst = x_get_word(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, dstreg) = dsta;
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	dst |= x_get_word(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, dstreg) = dsta;
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return;
	}
	m68k_areg(regs, dstreg) = dsta;
	uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u32)(~dst)) < ((uae_u32)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		uae_s16 bnewv = (uae_s16)dst + (uae_s16)src;
		int bflgs = ((uae_s16)(src)) < 0;
		int bflgo = ((uae_s16)(dst)) < 0;
		int bflgn = bnewv < 0;
		ccr_68000_long_move_ae_LZN(bnewv);
		SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
		SET_XFLG(GET_CFLG());
		SET_VFLG((bflgs ^ bflgn) & (bflgo ^ bflgn));
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	x_put_word(dsta + 2, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 2, 0x1, newv, 1);
		return;
	}
	x_put_word(dsta, newv >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x1, newv >> 16, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 22 (3/2) */
/* 2 0,0   */

/* ADDQ.L #<data>,(d16,An) */
void REGPARAM2 op_50a8_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 24; 
	uae_u32 src = srcreg;
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dsta, 2, 1);
		return;
	}
	uae_s32 dst = x_get_word(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	dst |= x_get_word(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return;
	}
	uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u32)(~dst)) < ((uae_u32)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		uae_s16 bnewv = (uae_s16)dst + (uae_s16)src;
		int bflgs = ((uae_s16)(src)) < 0;
		int bflgo = ((uae_s16)(dst)) < 0;
		int bflgn = bnewv < 0;
		ccr_68000_long_move_ae_LZN(bnewv);
		SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
		SET_XFLG(GET_CFLG());
		SET_VFLG((bflgs ^ bflgn) & (bflgo ^ bflgn));
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	x_put_word(dsta + 2, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 2, 0x1, newv, 1);
		return;
	}
	x_put_word(dsta, newv >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, newv >> 16, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 24 (4/2) */
/* 4 0,0   */

/* ADDQ.L #<data>,(d8,An,Xn) */
void REGPARAM2 op_50b0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 26; 
	uae_u32 src = srcreg;
	uaecptr dsta;
	do_cycles_ce000_internal(2);
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dsta, 2, 1);
		return;
	}
	uae_s32 dst = x_get_word(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	dst |= x_get_word(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return;
	}
	uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u32)(~dst)) < ((uae_u32)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		uae_s16 bnewv = (uae_s16)dst + (uae_s16)src;
		int bflgs = ((uae_s16)(src)) < 0;
		int bflgo = ((uae_s16)(dst)) < 0;
		int bflgn = bnewv < 0;
		ccr_68000_long_move_ae_LZN(bnewv);
		SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
		SET_XFLG(GET_CFLG());
		SET_VFLG((bflgs ^ bflgn) & (bflgo ^ bflgn));
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	x_put_word(dsta + 2, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 2, 0x1, newv, 1);
		return;
	}
	x_put_word(dsta, newv >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, newv >> 16, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 26 (4/2) */
/* 4 4,0   */

/* ADDQ.L #<data>,(xxx).W */
void REGPARAM2 op_50b8_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	OpcodeFamily = 11;
	CurrentInstrCycles = 24; 
	uae_u32 src = srcreg;
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, dsta, 2, 1);
		return;
	}
	uae_s32 dst = x_get_word(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	dst |= x_get_word(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return;
	}
	uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u32)(~dst)) < ((uae_u32)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		uae_s16 bnewv = (uae_s16)dst + (uae_s16)src;
		int bflgs = ((uae_s16)(src)) < 0;
		int bflgo = ((uae_s16)(dst)) < 0;
		int bflgn = bnewv < 0;
		ccr_68000_long_move_ae_LZN(bnewv);
		SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
		SET_XFLG(GET_CFLG());
		SET_VFLG((bflgs ^ bflgn) & (bflgo ^ bflgn));
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	x_put_word(dsta + 2, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 2, 0x1, newv, 1);
		return;
	}
	x_put_word(dsta, newv >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, newv >> 16, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 24 (4/2) */
/* 4 0,0   */

/* ADDQ.L #<data>,(xxx).L */
void REGPARAM2 op_50b9_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	OpcodeFamily = 11;
	CurrentInstrCycles = 28; 
	uae_u32 src = srcreg;
	uaecptr dsta;
	dsta = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	dsta |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, dsta, 2, 1);
		return;
	}
	uae_s32 dst = x_get_word(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	dst |= x_get_word(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return;
	}
	uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u32)(~dst)) < ((uae_u32)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		uae_s16 bnewv = (uae_s16)dst + (uae_s16)src;
		int bflgs = ((uae_s16)(src)) < 0;
		int bflgo = ((uae_s16)(dst)) < 0;
		int bflgn = bnewv < 0;
		ccr_68000_long_move_ae_LZN(bnewv);
		SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
		SET_XFLG(GET_CFLG());
		SET_VFLG((bflgs ^ bflgn) & (bflgo ^ bflgn));
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	x_put_word(dsta + 2, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 2, 0x1, newv, 1);
		return;
	}
	x_put_word(dsta, newv >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 0, 0x1, newv >> 16, 1);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 28 (5/2) */
/* 6 0,0   */

/* Scc.B Dn (T) */
void REGPARAM2 op_50c0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 4;  
	uae_s8 src = m68k_dreg(regs, srcreg);
	int val = cctrue(0) ? 0xff : 0x00;
	int cycles = val ? 2 : 0;
	if (!val) {
		m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff);
	}
	opcode |= 0x20000;
	regs.ir = regs.irc;
	if (!val)
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if(!val && regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff);
	if (cycles > 0) do_cycles_ce000_internal(cycles);
	m68k_incpci(2);
	return;
}
/* 4+ (1/0) */
/* 2 0,0   */

/* DBcc.W Dn,#<data>.W (T) */
void REGPARAM2 op_50c8_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 58;
	CurrentInstrCycles = 12; 
	int pcadjust = -2;
	uae_s16 src = m68k_dreg(regs, srcreg);
	uae_s16 offs = regs.irc;
	uaecptr oldpc = m68k_getpci();
	do_cycles_ce000_internal(2);
	if (!cctrue(0)) {
		m68k_incpci((uae_s32)offs + 2);
		if (offs & 1) {
			exception3_read_prefetch(opcode, m68k_getpci());
			return;
		}
		get_word_ce000_prefetch(0);
		if(hardware_bus_error) {
			int pcoffset = 0;
			pcoffset = oldpc - m68k_getpci() + 4;
			exception2_fetch_opcode(opcode, 0, pcoffset);
			return;
		}
		if (src) {
			m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
			regs.ir = regs.irc;
			opcode = regs.ir;
			if(regs.t1) opcode |= 0x10000;
			ipl_fetch_next();
			get_word_ce000_prefetch(2);
			if(hardware_bus_error) {
				int pcoffset = 0;
				exception2_fetch_opcode(opcode, 2, 0);
				return;
			}
			return;
		}
		pcadjust = 0;
	} else {
		do_cycles_ce000_internal(2);
	}
	m68k_setpci_j(oldpc + 4);
	get_word_ce000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		pcoffset += pcadjust;
		exception2_fetch_opcode(opcode, 0, pcoffset);
		return;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	if(regs.t1) opcode |= 0x10000;
	if (!cctrue(0)) {
		m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
	}
	ipl_fetch_next();
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 12 (2/0) */
/* 4 0,0 B */

/* Scc.B (An) (T) */
void REGPARAM2 op_50d0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	int val = cctrue(0) ? 0xff : 0x00;
	x_put_byte(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 12 (2/1) */
/* 2 0,0   */

/* Scc.B (An)+ (T) */
void REGPARAM2 op_50d8_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	int val = cctrue(0) ? 0xff : 0x00;
	x_put_byte(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 12 (2/1) */
/* 2 0,0   */

/* Scc.B -(An) (T) */
void REGPARAM2 op_50e0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
	do_cycles_ce000_internal(2);
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	m68k_areg(regs, srcreg) = srca;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	int val = cctrue(0) ? 0xff : 0x00;
	x_put_byte(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 14 (2/1) */
/* 2 0,0   */

/* Scc.B (d16,An) (T) */
void REGPARAM2 op_50e8_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	int val = cctrue(0) ? 0xff : 0x00;
	x_put_byte(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* Scc.B (d8,An,Xn) (T) */
void REGPARAM2 op_50f0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	do_cycles_ce000_internal(2);
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	int val = cctrue(0) ? 0xff : 0x00;
	x_put_byte(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 18 (3/1) */
/* 4 4,0   */

/* Scc.B (xxx).W (T) */
void REGPARAM2 op_50f8_14_ff(uae_u32 opcode)
{
	OpcodeFamily = 59;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	int val = cctrue(0) ? 0xff : 0x00;
	x_put_byte(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* Scc.B (xxx).L (T) */
void REGPARAM2 op_50f9_14_ff(uae_u32 opcode)
{
	OpcodeFamily = 59;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	srca = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	srca |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	opcode = regs.ir;
	int val = cctrue(0) ? 0xff : 0x00;
	x_put_byte(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 20 (4/1) */
/* 6 0,0   */

/* SUBQ.B #<data>,Dn */
void REGPARAM2 op_5100_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 4;  
	uae_u32 src = srcreg;
	uae_s8 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 4 (1/0) */
/* 2 0,0   */

/* SUBQ.B #<data>,(An) */
void REGPARAM2 op_5110_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 12; 
	uae_u32 src = srcreg;
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_byte(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, newv, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 12 (2/1) */
/* 2 0,0   */

/* SUBQ.B #<data>,(An)+ */
void REGPARAM2 op_5118_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 12; 
	uae_u32 src = srcreg;
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
	uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_byte(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, newv, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 12 (2/1) */
/* 2 0,0   */

/* SUBQ.B #<data>,-(An) */
void REGPARAM2 op_5120_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 14; 
	uae_u32 src = srcreg;
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
	do_cycles_ce000_internal(2);
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, dstreg) = dsta;
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	m68k_areg(regs, dstreg) = dsta;
	uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_byte(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, newv, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 14 (2/1) */
/* 2 0,0   */

/* SUBQ.B #<data>,(d16,An) */
void REGPARAM2 op_5128_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 16; 
	uae_u32 src = srcreg;
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_byte(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, newv, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* SUBQ.B #<data>,(d8,An,Xn) */
void REGPARAM2 op_5130_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 18; 
	uae_u32 src = srcreg;
	uaecptr dsta;
	do_cycles_ce000_internal(2);
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_byte(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, newv, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 18 (3/1) */
/* 4 4,0   */

/* SUBQ.B #<data>,(xxx).W */
void REGPARAM2 op_5138_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	OpcodeFamily = 7;
	CurrentInstrCycles = 16; 
	uae_u32 src = srcreg;
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_byte(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, newv, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* SUBQ.B #<data>,(xxx).L */
void REGPARAM2 op_5139_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	OpcodeFamily = 7;
	CurrentInstrCycles = 20; 
	uae_u32 src = srcreg;
	uaecptr dsta;
	dsta = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	dsta |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_byte(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, newv, 1);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 20 (4/1) */
/* 6 0,0   */

/* SUBQ.W #<data>,Dn */
void REGPARAM2 op_5140_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 4;  
	uae_u32 src = srcreg;
	uae_s16 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 4 (1/0) */
/* 2 0,0   */

/* SUBAQ.W #<data>,An */
void REGPARAM2 op_5148_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 8;
	CurrentInstrCycles = 8;  
	uae_u32 src = srcreg;
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = dst - src;
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		areg_68000_long_replace_low(dstreg, newv);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	do_cycles_ce000_internal(4);
	m68k_areg(regs, dstreg) = (newv);
	m68k_incpci(2);
	return;
}
/* 8 (1/0) */
/* 2 0,0   */

/* SUBQ.W #<data>,(An) */
void REGPARAM2 op_5150_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 12; 
	uae_u32 src = srcreg;
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	if (dsta & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dsta, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 dst = x_get_word(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_word(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x1, newv, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 12 (2/1) */
/* 2 0,0   */

/* SUBQ.W #<data>,(An)+ */
void REGPARAM2 op_5158_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 12; 
	uae_u32 src = srcreg;
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	if (dsta & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dsta, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 dst = x_get_word(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, dstreg) += 2 + 0;
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	m68k_areg(regs, dstreg) += 2;
	uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_word(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x1, newv, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 12 (2/1) */
/* 2 0,0   */

/* SUBQ.W #<data>,-(An) */
void REGPARAM2 op_5160_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 14; 
	uae_u32 src = srcreg;
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - 2;
	do_cycles_ce000_internal(2);
	if (dsta & 1) {
		m68k_incpci(4);
		m68k_areg(regs, dstreg) = dsta;
		exception3_read_access(opcode, dsta, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 dst = x_get_word(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, dstreg) = dsta;
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	m68k_areg(regs, dstreg) = dsta;
	uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_word(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x1, newv, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 14 (2/1) */
/* 2 0,0   */

/* SUBQ.W #<data>,(d16,An) */
void REGPARAM2 op_5168_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 16; 
	uae_u32 src = srcreg;
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dsta, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 dst = x_get_word(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_word(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x1, newv, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* SUBQ.W #<data>,(d8,An,Xn) */
void REGPARAM2 op_5170_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 18; 
	uae_u32 src = srcreg;
	uaecptr dsta;
	do_cycles_ce000_internal(2);
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dsta, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 dst = x_get_word(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_word(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x1, newv, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 18 (3/1) */
/* 4 4,0   */

/* SUBQ.W #<data>,(xxx).W */
void REGPARAM2 op_5178_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	OpcodeFamily = 7;
	CurrentInstrCycles = 16; 
	uae_u32 src = srcreg;
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, dsta, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 dst = x_get_word(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_word(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x1, newv, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* SUBQ.W #<data>,(xxx).L */
void REGPARAM2 op_5179_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	OpcodeFamily = 7;
	CurrentInstrCycles = 20; 
	uae_u32 src = srcreg;
	uaecptr dsta;
	dsta = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	dsta |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, dsta, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 dst = x_get_word(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_word(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x1, newv, 1);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 20 (4/1) */
/* 6 0,0   */

/* SUBQ.L #<data>,Dn */
void REGPARAM2 op_5180_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 8;  
	uae_u32 src = srcreg;
	uae_s32 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		uae_s16 bnewv = (uae_s16)dst - (uae_s16)src;
		int bflgs = ((uae_s16)(src)) < 0;
		int bflgo = ((uae_s16)(dst)) < 0;
		int bflgn = bnewv < 0;
		ccr_68000_long_move_ae_LZN(bnewv);
		SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
		SET_XFLG(GET_CFLG());
		SET_VFLG((bflgs ^ bflgo) & (bflgn ^ bflgo));
		dreg_68000_long_replace_low(dstreg, bnewv);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	do_cycles_ce000_internal(4);
	m68k_dreg(regs, dstreg) = (newv);
	m68k_incpci(2);
	return;
}
/* 8 (1/0) */
/* 2 0,0   */

/* SUBAQ.L #<data>,An */
void REGPARAM2 op_5188_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 8;
	CurrentInstrCycles = 8;  
	uae_u32 src = srcreg;
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = dst - src;
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		areg_68000_long_replace_low(dstreg, newv);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	do_cycles_ce000_internal(4);
	m68k_areg(regs, dstreg) = (newv);
	m68k_incpci(2);
	return;
}
/* 8 (1/0) */
/* 2 0,0   */

/* SUBQ.L #<data>,(An) */
void REGPARAM2 op_5190_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 20; 
	uae_u32 src = srcreg;
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	if (dsta & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dsta, 2, 1);
		return;
	}
	uae_s32 dst = x_get_word(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	dst |= x_get_word(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return;
	}
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		uae_s16 bnewv = (uae_s16)dst - (uae_s16)src;
		int bflgs = ((uae_s16)(src)) < 0;
		int bflgo = ((uae_s16)(dst)) < 0;
		int bflgn = bnewv < 0;
		ccr_68000_long_move_ae_LZN(bnewv);
		SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
		SET_XFLG(GET_CFLG());
		SET_VFLG((bflgs ^ bflgo) & (bflgn ^ bflgo));
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	x_put_word(dsta + 2, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 2, 0x1, newv, 1);
		return;
	}
	x_put_word(dsta, newv >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x1, newv >> 16, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 20 (3/2) */
/* 2 0,0   */

/* SUBQ.L #<data>,(An)+ */
void REGPARAM2 op_5198_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 20; 
	uae_u32 src = srcreg;
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	if (dsta & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dsta, 2, 1);
		return;
	}
	uae_s32 dst = x_get_word(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	dst |= x_get_word(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return;
	}
	m68k_areg(regs, dstreg) += 4;
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		uae_s16 bnewv = (uae_s16)dst - (uae_s16)src;
		int bflgs = ((uae_s16)(src)) < 0;
		int bflgo = ((uae_s16)(dst)) < 0;
		int bflgn = bnewv < 0;
		ccr_68000_long_move_ae_LZN(bnewv);
		SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
		SET_XFLG(GET_CFLG());
		SET_VFLG((bflgs ^ bflgo) & (bflgn ^ bflgo));
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	x_put_word(dsta + 2, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 2, 0x1, newv, 1);
		return;
	}
	x_put_word(dsta, newv >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x1, newv >> 16, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 20 (3/2) */
/* 2 0,0   */

/* SUBQ.L #<data>,-(An) */
void REGPARAM2 op_51a0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 22; 
	uae_u32 src = srcreg;
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - 4;
	do_cycles_ce000_internal(2);
	if (dsta & 1) {
		m68k_incpci(2);
		m68k_areg(regs, dstreg) = dsta;
		exception3_read_access(opcode, dsta, 2, 1);
		return;
	}
	uae_s32 dst = x_get_word(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, dstreg) = dsta;
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	dst |= x_get_word(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, dstreg) = dsta;
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return;
	}
	m68k_areg(regs, dstreg) = dsta;
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		uae_s16 bnewv = (uae_s16)dst - (uae_s16)src;
		int bflgs = ((uae_s16)(src)) < 0;
		int bflgo = ((uae_s16)(dst)) < 0;
		int bflgn = bnewv < 0;
		ccr_68000_long_move_ae_LZN(bnewv);
		SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
		SET_XFLG(GET_CFLG());
		SET_VFLG((bflgs ^ bflgo) & (bflgn ^ bflgo));
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	x_put_word(dsta + 2, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 2, 0x1, newv, 1);
		return;
	}
	x_put_word(dsta, newv >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x1, newv >> 16, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 22 (3/2) */
/* 2 0,0   */

/* SUBQ.L #<data>,(d16,An) */
void REGPARAM2 op_51a8_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 24; 
	uae_u32 src = srcreg;
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dsta, 2, 1);
		return;
	}
	uae_s32 dst = x_get_word(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	dst |= x_get_word(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return;
	}
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		uae_s16 bnewv = (uae_s16)dst - (uae_s16)src;
		int bflgs = ((uae_s16)(src)) < 0;
		int bflgo = ((uae_s16)(dst)) < 0;
		int bflgn = bnewv < 0;
		ccr_68000_long_move_ae_LZN(bnewv);
		SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
		SET_XFLG(GET_CFLG());
		SET_VFLG((bflgs ^ bflgo) & (bflgn ^ bflgo));
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	x_put_word(dsta + 2, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 2, 0x1, newv, 1);
		return;
	}
	x_put_word(dsta, newv >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, newv >> 16, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 24 (4/2) */
/* 4 0,0   */

/* SUBQ.L #<data>,(d8,An,Xn) */
void REGPARAM2 op_51b0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 26; 
	uae_u32 src = srcreg;
	uaecptr dsta;
	do_cycles_ce000_internal(2);
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dsta, 2, 1);
		return;
	}
	uae_s32 dst = x_get_word(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	dst |= x_get_word(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return;
	}
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		uae_s16 bnewv = (uae_s16)dst - (uae_s16)src;
		int bflgs = ((uae_s16)(src)) < 0;
		int bflgo = ((uae_s16)(dst)) < 0;
		int bflgn = bnewv < 0;
		ccr_68000_long_move_ae_LZN(bnewv);
		SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
		SET_XFLG(GET_CFLG());
		SET_VFLG((bflgs ^ bflgo) & (bflgn ^ bflgo));
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	x_put_word(dsta + 2, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 2, 0x1, newv, 1);
		return;
	}
	x_put_word(dsta, newv >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, newv >> 16, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 26 (4/2) */
/* 4 4,0   */

/* SUBQ.L #<data>,(xxx).W */
void REGPARAM2 op_51b8_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	OpcodeFamily = 7;
	CurrentInstrCycles = 24; 
	uae_u32 src = srcreg;
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, dsta, 2, 1);
		return;
	}
	uae_s32 dst = x_get_word(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	dst |= x_get_word(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return;
	}
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		uae_s16 bnewv = (uae_s16)dst - (uae_s16)src;
		int bflgs = ((uae_s16)(src)) < 0;
		int bflgo = ((uae_s16)(dst)) < 0;
		int bflgn = bnewv < 0;
		ccr_68000_long_move_ae_LZN(bnewv);
		SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
		SET_XFLG(GET_CFLG());
		SET_VFLG((bflgs ^ bflgo) & (bflgn ^ bflgo));
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	x_put_word(dsta + 2, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 2, 0x1, newv, 1);
		return;
	}
	x_put_word(dsta, newv >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, newv >> 16, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 24 (4/2) */
/* 4 0,0   */

/* SUBQ.L #<data>,(xxx).L */
void REGPARAM2 op_51b9_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	OpcodeFamily = 7;
	CurrentInstrCycles = 28; 
	uae_u32 src = srcreg;
	uaecptr dsta;
	dsta = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	dsta |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, dsta, 2, 1);
		return;
	}
	uae_s32 dst = x_get_word(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	dst |= x_get_word(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return;
	}
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		uae_s16 bnewv = (uae_s16)dst - (uae_s16)src;
		int bflgs = ((uae_s16)(src)) < 0;
		int bflgo = ((uae_s16)(dst)) < 0;
		int bflgn = bnewv < 0;
		ccr_68000_long_move_ae_LZN(bnewv);
		SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
		SET_XFLG(GET_CFLG());
		SET_VFLG((bflgs ^ bflgo) & (bflgn ^ bflgo));
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	x_put_word(dsta + 2, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 2, 0x1, newv, 1);
		return;
	}
	x_put_word(dsta, newv >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 0, 0x1, newv >> 16, 1);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 28 (5/2) */
/* 6 0,0   */

/* Scc.B Dn (F) */
void REGPARAM2 op_51c0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 4;  
	uae_s8 src = m68k_dreg(regs, srcreg);
	int val = cctrue(1) ? 0xff : 0x00;
	int cycles = val ? 2 : 0;
	if (!val) {
		m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff);
	}
	opcode |= 0x20000;
	regs.ir = regs.irc;
	if (!val)
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if(!val && regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff);
	if (cycles > 0) do_cycles_ce000_internal(cycles);
	m68k_incpci(2);
	return;
}
/* 4+ (1/0) */
/* 2 0,0   */

/* DBcc.W Dn,#<data>.W (F) */
void REGPARAM2 op_51c8_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 58;
	CurrentInstrCycles = 12; 
	int pcadjust = -2;
	uae_s16 src = m68k_dreg(regs, srcreg);
	uae_s16 offs = regs.irc;
	uaecptr oldpc = m68k_getpci();
	do_cycles_ce000_internal(2);
	if (!cctrue(1)) {
		m68k_incpci((uae_s32)offs + 2);
		if (offs & 1) {
			exception3_read_prefetch(opcode, m68k_getpci());
			return;
		}
		get_word_ce000_prefetch(0);
		if(hardware_bus_error) {
			int pcoffset = 0;
			pcoffset = oldpc - m68k_getpci() + 4;
			exception2_fetch_opcode(opcode, 0, pcoffset);
			return;
		}
		if (src) {
			m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
			regs.ir = regs.irc;
			opcode = regs.ir;
			if(regs.t1) opcode |= 0x10000;
			ipl_fetch_next();
			get_word_ce000_prefetch(2);
			if(hardware_bus_error) {
				int pcoffset = 0;
				exception2_fetch_opcode(opcode, 2, 0);
				return;
			}
			return;
		}
		pcadjust = 0;
	} else {
		do_cycles_ce000_internal(2);
	}
	m68k_setpci_j(oldpc + 4);
	get_word_ce000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		pcoffset += pcadjust;
		exception2_fetch_opcode(opcode, 0, pcoffset);
		return;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	if(regs.t1) opcode |= 0x10000;
	if (!cctrue(1)) {
		m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
	}
	ipl_fetch_next();
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 12 (2/0) */
/* 4 0,0 B */

/* Scc.B (An) (F) */
void REGPARAM2 op_51d0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	int val = cctrue(1) ? 0xff : 0x00;
	x_put_byte(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 12 (2/1) */
/* 2 0,0   */

/* Scc.B (An)+ (F) */
void REGPARAM2 op_51d8_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	int val = cctrue(1) ? 0xff : 0x00;
	x_put_byte(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 12 (2/1) */
/* 2 0,0   */

/* Scc.B -(An) (F) */
void REGPARAM2 op_51e0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
	do_cycles_ce000_internal(2);
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	m68k_areg(regs, srcreg) = srca;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	int val = cctrue(1) ? 0xff : 0x00;
	x_put_byte(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 14 (2/1) */
/* 2 0,0   */

/* Scc.B (d16,An) (F) */
void REGPARAM2 op_51e8_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	int val = cctrue(1) ? 0xff : 0x00;
	x_put_byte(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* Scc.B (d8,An,Xn) (F) */
void REGPARAM2 op_51f0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	do_cycles_ce000_internal(2);
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	int val = cctrue(1) ? 0xff : 0x00;
	x_put_byte(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 18 (3/1) */
/* 4 4,0   */

/* Scc.B (xxx).W (F) */
void REGPARAM2 op_51f8_14_ff(uae_u32 opcode)
{
	OpcodeFamily = 59;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	int val = cctrue(1) ? 0xff : 0x00;
	x_put_byte(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* Scc.B (xxx).L (F) */
void REGPARAM2 op_51f9_14_ff(uae_u32 opcode)
{
	OpcodeFamily = 59;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	srca = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	srca |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	opcode = regs.ir;
	int val = cctrue(1) ? 0xff : 0x00;
	x_put_byte(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 20 (4/1) */
/* 6 0,0   */

/* Scc.B Dn (HI) */
void REGPARAM2 op_52c0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 4;  
	uae_s8 src = m68k_dreg(regs, srcreg);
	int val = cctrue(2) ? 0xff : 0x00;
	int cycles = val ? 2 : 0;
	if (!val) {
		m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff);
	}
	opcode |= 0x20000;
	regs.ir = regs.irc;
	if (!val)
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if(!val && regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff);
	if (cycles > 0) do_cycles_ce000_internal(cycles);
	m68k_incpci(2);
	return;
}
/* 4+ (1/0) */
/* 2 0,0   */

/* DBcc.W Dn,#<data>.W (HI) */
void REGPARAM2 op_52c8_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 58;
	CurrentInstrCycles = 12; 
	int pcadjust = -2;
	uae_s16 src = m68k_dreg(regs, srcreg);
	uae_s16 offs = regs.irc;
	uaecptr oldpc = m68k_getpci();
	do_cycles_ce000_internal(2);
	if (!cctrue(2)) {
		m68k_incpci((uae_s32)offs + 2);
		if (offs & 1) {
			exception3_read_prefetch(opcode, m68k_getpci());
			return;
		}
		get_word_ce000_prefetch(0);
		if(hardware_bus_error) {
			int pcoffset = 0;
			pcoffset = oldpc - m68k_getpci() + 4;
			exception2_fetch_opcode(opcode, 0, pcoffset);
			return;
		}
		if (src) {
			m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
			regs.ir = regs.irc;
			opcode = regs.ir;
			if(regs.t1) opcode |= 0x10000;
			ipl_fetch_next();
			get_word_ce000_prefetch(2);
			if(hardware_bus_error) {
				int pcoffset = 0;
				exception2_fetch_opcode(opcode, 2, 0);
				return;
			}
			return;
		}
		pcadjust = 0;
	} else {
		do_cycles_ce000_internal(2);
	}
	m68k_setpci_j(oldpc + 4);
	get_word_ce000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		pcoffset += pcadjust;
		exception2_fetch_opcode(opcode, 0, pcoffset);
		return;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	if(regs.t1) opcode |= 0x10000;
	if (!cctrue(2)) {
		m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
	}
	ipl_fetch_next();
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 12 (2/0) */
/* 4 0,0 B */

/* Scc.B (An) (HI) */
void REGPARAM2 op_52d0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	int val = cctrue(2) ? 0xff : 0x00;
	x_put_byte(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 12 (2/1) */
/* 2 0,0   */

/* Scc.B (An)+ (HI) */
void REGPARAM2 op_52d8_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	int val = cctrue(2) ? 0xff : 0x00;
	x_put_byte(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 12 (2/1) */
/* 2 0,0   */

/* Scc.B -(An) (HI) */
void REGPARAM2 op_52e0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
	do_cycles_ce000_internal(2);
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	m68k_areg(regs, srcreg) = srca;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	int val = cctrue(2) ? 0xff : 0x00;
	x_put_byte(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 14 (2/1) */
/* 2 0,0   */

/* Scc.B (d16,An) (HI) */
void REGPARAM2 op_52e8_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	int val = cctrue(2) ? 0xff : 0x00;
	x_put_byte(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* Scc.B (d8,An,Xn) (HI) */
void REGPARAM2 op_52f0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	do_cycles_ce000_internal(2);
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	int val = cctrue(2) ? 0xff : 0x00;
	x_put_byte(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 18 (3/1) */
/* 4 4,0   */

/* Scc.B (xxx).W (HI) */
void REGPARAM2 op_52f8_14_ff(uae_u32 opcode)
{
	OpcodeFamily = 59;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	int val = cctrue(2) ? 0xff : 0x00;
	x_put_byte(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* Scc.B (xxx).L (HI) */
void REGPARAM2 op_52f9_14_ff(uae_u32 opcode)
{
	OpcodeFamily = 59;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	srca = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	srca |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	opcode = regs.ir;
	int val = cctrue(2) ? 0xff : 0x00;
	x_put_byte(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 20 (4/1) */
/* 6 0,0   */

/* Scc.B Dn (LS) */
void REGPARAM2 op_53c0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 4;  
	uae_s8 src = m68k_dreg(regs, srcreg);
	int val = cctrue(3) ? 0xff : 0x00;
	int cycles = val ? 2 : 0;
	if (!val) {
		m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff);
	}
	opcode |= 0x20000;
	regs.ir = regs.irc;
	if (!val)
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if(!val && regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff);
	if (cycles > 0) do_cycles_ce000_internal(cycles);
	m68k_incpci(2);
	return;
}
/* 4+ (1/0) */
/* 2 0,0   */

/* DBcc.W Dn,#<data>.W (LS) */
void REGPARAM2 op_53c8_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 58;
	CurrentInstrCycles = 12; 
	int pcadjust = -2;
	uae_s16 src = m68k_dreg(regs, srcreg);
	uae_s16 offs = regs.irc;
	uaecptr oldpc = m68k_getpci();
	do_cycles_ce000_internal(2);
	if (!cctrue(3)) {
		m68k_incpci((uae_s32)offs + 2);
		if (offs & 1) {
			exception3_read_prefetch(opcode, m68k_getpci());
			return;
		}
		get_word_ce000_prefetch(0);
		if(hardware_bus_error) {
			int pcoffset = 0;
			pcoffset = oldpc - m68k_getpci() + 4;
			exception2_fetch_opcode(opcode, 0, pcoffset);
			return;
		}
		if (src) {
			m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
			regs.ir = regs.irc;
			opcode = regs.ir;
			if(regs.t1) opcode |= 0x10000;
			ipl_fetch_next();
			get_word_ce000_prefetch(2);
			if(hardware_bus_error) {
				int pcoffset = 0;
				exception2_fetch_opcode(opcode, 2, 0);
				return;
			}
			return;
		}
		pcadjust = 0;
	} else {
		do_cycles_ce000_internal(2);
	}
	m68k_setpci_j(oldpc + 4);
	get_word_ce000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		pcoffset += pcadjust;
		exception2_fetch_opcode(opcode, 0, pcoffset);
		return;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	if(regs.t1) opcode |= 0x10000;
	if (!cctrue(3)) {
		m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
	}
	ipl_fetch_next();
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 12 (2/0) */
/* 4 0,0 B */

/* Scc.B (An) (LS) */
void REGPARAM2 op_53d0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	int val = cctrue(3) ? 0xff : 0x00;
	x_put_byte(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 12 (2/1) */
/* 2 0,0   */

/* Scc.B (An)+ (LS) */
void REGPARAM2 op_53d8_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	int val = cctrue(3) ? 0xff : 0x00;
	x_put_byte(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 12 (2/1) */
/* 2 0,0   */

/* Scc.B -(An) (LS) */
void REGPARAM2 op_53e0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
	do_cycles_ce000_internal(2);
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	m68k_areg(regs, srcreg) = srca;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	int val = cctrue(3) ? 0xff : 0x00;
	x_put_byte(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 14 (2/1) */
/* 2 0,0   */

/* Scc.B (d16,An) (LS) */
void REGPARAM2 op_53e8_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	int val = cctrue(3) ? 0xff : 0x00;
	x_put_byte(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* Scc.B (d8,An,Xn) (LS) */
void REGPARAM2 op_53f0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	do_cycles_ce000_internal(2);
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	int val = cctrue(3) ? 0xff : 0x00;
	x_put_byte(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 18 (3/1) */
/* 4 4,0   */

/* Scc.B (xxx).W (LS) */
void REGPARAM2 op_53f8_14_ff(uae_u32 opcode)
{
	OpcodeFamily = 59;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	int val = cctrue(3) ? 0xff : 0x00;
	x_put_byte(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* Scc.B (xxx).L (LS) */
void REGPARAM2 op_53f9_14_ff(uae_u32 opcode)
{
	OpcodeFamily = 59;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	srca = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	srca |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	opcode = regs.ir;
	int val = cctrue(3) ? 0xff : 0x00;
	x_put_byte(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 20 (4/1) */
/* 6 0,0   */

/* Scc.B Dn (CC) */
void REGPARAM2 op_54c0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 4;  
	uae_s8 src = m68k_dreg(regs, srcreg);
	int val = cctrue(4) ? 0xff : 0x00;
	int cycles = val ? 2 : 0;
	if (!val) {
		m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff);
	}
	opcode |= 0x20000;
	regs.ir = regs.irc;
	if (!val)
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if(!val && regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff);
	if (cycles > 0) do_cycles_ce000_internal(cycles);
	m68k_incpci(2);
	return;
}
/* 4+ (1/0) */
/* 2 0,0   */

/* DBcc.W Dn,#<data>.W (CC) */
void REGPARAM2 op_54c8_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 58;
	CurrentInstrCycles = 12; 
	int pcadjust = -2;
	uae_s16 src = m68k_dreg(regs, srcreg);
	uae_s16 offs = regs.irc;
	uaecptr oldpc = m68k_getpci();
	do_cycles_ce000_internal(2);
	if (!cctrue(4)) {
		m68k_incpci((uae_s32)offs + 2);
		if (offs & 1) {
			exception3_read_prefetch(opcode, m68k_getpci());
			return;
		}
		get_word_ce000_prefetch(0);
		if(hardware_bus_error) {
			int pcoffset = 0;
			pcoffset = oldpc - m68k_getpci() + 4;
			exception2_fetch_opcode(opcode, 0, pcoffset);
			return;
		}
		if (src) {
			m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
			regs.ir = regs.irc;
			opcode = regs.ir;
			if(regs.t1) opcode |= 0x10000;
			ipl_fetch_next();
			get_word_ce000_prefetch(2);
			if(hardware_bus_error) {
				int pcoffset = 0;
				exception2_fetch_opcode(opcode, 2, 0);
				return;
			}
			return;
		}
		pcadjust = 0;
	} else {
		do_cycles_ce000_internal(2);
	}
	m68k_setpci_j(oldpc + 4);
	get_word_ce000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		pcoffset += pcadjust;
		exception2_fetch_opcode(opcode, 0, pcoffset);
		return;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	if(regs.t1) opcode |= 0x10000;
	if (!cctrue(4)) {
		m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
	}
	ipl_fetch_next();
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 12 (2/0) */
/* 4 0,0 B */

/* Scc.B (An) (CC) */
void REGPARAM2 op_54d0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	int val = cctrue(4) ? 0xff : 0x00;
	x_put_byte(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 12 (2/1) */
/* 2 0,0   */

/* Scc.B (An)+ (CC) */
void REGPARAM2 op_54d8_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	int val = cctrue(4) ? 0xff : 0x00;
	x_put_byte(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 12 (2/1) */
/* 2 0,0   */

/* Scc.B -(An) (CC) */
void REGPARAM2 op_54e0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
	do_cycles_ce000_internal(2);
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	m68k_areg(regs, srcreg) = srca;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	int val = cctrue(4) ? 0xff : 0x00;
	x_put_byte(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 14 (2/1) */
/* 2 0,0   */

/* Scc.B (d16,An) (CC) */
void REGPARAM2 op_54e8_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	int val = cctrue(4) ? 0xff : 0x00;
	x_put_byte(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* Scc.B (d8,An,Xn) (CC) */
void REGPARAM2 op_54f0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	do_cycles_ce000_internal(2);
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	int val = cctrue(4) ? 0xff : 0x00;
	x_put_byte(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 18 (3/1) */
/* 4 4,0   */

/* Scc.B (xxx).W (CC) */
void REGPARAM2 op_54f8_14_ff(uae_u32 opcode)
{
	OpcodeFamily = 59;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	int val = cctrue(4) ? 0xff : 0x00;
	x_put_byte(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* Scc.B (xxx).L (CC) */
void REGPARAM2 op_54f9_14_ff(uae_u32 opcode)
{
	OpcodeFamily = 59;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	srca = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	srca |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	opcode = regs.ir;
	int val = cctrue(4) ? 0xff : 0x00;
	x_put_byte(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 20 (4/1) */
/* 6 0,0   */

/* Scc.B Dn (CS) */
void REGPARAM2 op_55c0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 4;  
	uae_s8 src = m68k_dreg(regs, srcreg);
	int val = cctrue(5) ? 0xff : 0x00;
	int cycles = val ? 2 : 0;
	if (!val) {
		m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff);
	}
	opcode |= 0x20000;
	regs.ir = regs.irc;
	if (!val)
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if(!val && regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff);
	if (cycles > 0) do_cycles_ce000_internal(cycles);
	m68k_incpci(2);
	return;
}
/* 4+ (1/0) */
/* 2 0,0   */

/* DBcc.W Dn,#<data>.W (CS) */
void REGPARAM2 op_55c8_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 58;
	CurrentInstrCycles = 12; 
	int pcadjust = -2;
	uae_s16 src = m68k_dreg(regs, srcreg);
	uae_s16 offs = regs.irc;
	uaecptr oldpc = m68k_getpci();
	do_cycles_ce000_internal(2);
	if (!cctrue(5)) {
		m68k_incpci((uae_s32)offs + 2);
		if (offs & 1) {
			exception3_read_prefetch(opcode, m68k_getpci());
			return;
		}
		get_word_ce000_prefetch(0);
		if(hardware_bus_error) {
			int pcoffset = 0;
			pcoffset = oldpc - m68k_getpci() + 4;
			exception2_fetch_opcode(opcode, 0, pcoffset);
			return;
		}
		if (src) {
			m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
			regs.ir = regs.irc;
			opcode = regs.ir;
			if(regs.t1) opcode |= 0x10000;
			ipl_fetch_next();
			get_word_ce000_prefetch(2);
			if(hardware_bus_error) {
				int pcoffset = 0;
				exception2_fetch_opcode(opcode, 2, 0);
				return;
			}
			return;
		}
		pcadjust = 0;
	} else {
		do_cycles_ce000_internal(2);
	}
	m68k_setpci_j(oldpc + 4);
	get_word_ce000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		pcoffset += pcadjust;
		exception2_fetch_opcode(opcode, 0, pcoffset);
		return;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	if(regs.t1) opcode |= 0x10000;
	if (!cctrue(5)) {
		m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
	}
	ipl_fetch_next();
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 12 (2/0) */
/* 4 0,0 B */

/* Scc.B (An) (CS) */
void REGPARAM2 op_55d0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	int val = cctrue(5) ? 0xff : 0x00;
	x_put_byte(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 12 (2/1) */
/* 2 0,0   */

/* Scc.B (An)+ (CS) */
void REGPARAM2 op_55d8_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	int val = cctrue(5) ? 0xff : 0x00;
	x_put_byte(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 12 (2/1) */
/* 2 0,0   */

/* Scc.B -(An) (CS) */
void REGPARAM2 op_55e0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
	do_cycles_ce000_internal(2);
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	m68k_areg(regs, srcreg) = srca;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	int val = cctrue(5) ? 0xff : 0x00;
	x_put_byte(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 14 (2/1) */
/* 2 0,0   */

/* Scc.B (d16,An) (CS) */
void REGPARAM2 op_55e8_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	int val = cctrue(5) ? 0xff : 0x00;
	x_put_byte(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* Scc.B (d8,An,Xn) (CS) */
void REGPARAM2 op_55f0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	do_cycles_ce000_internal(2);
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	int val = cctrue(5) ? 0xff : 0x00;
	x_put_byte(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 18 (3/1) */
/* 4 4,0   */

/* Scc.B (xxx).W (CS) */
void REGPARAM2 op_55f8_14_ff(uae_u32 opcode)
{
	OpcodeFamily = 59;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	int val = cctrue(5) ? 0xff : 0x00;
	x_put_byte(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* Scc.B (xxx).L (CS) */
void REGPARAM2 op_55f9_14_ff(uae_u32 opcode)
{
	OpcodeFamily = 59;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	srca = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	srca |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	opcode = regs.ir;
	int val = cctrue(5) ? 0xff : 0x00;
	x_put_byte(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 20 (4/1) */
/* 6 0,0   */

/* Scc.B Dn (NE) */
void REGPARAM2 op_56c0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 4;  
	uae_s8 src = m68k_dreg(regs, srcreg);
	int val = cctrue(6) ? 0xff : 0x00;
	int cycles = val ? 2 : 0;
	if (!val) {
		m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff);
	}
	opcode |= 0x20000;
	regs.ir = regs.irc;
	if (!val)
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if(!val && regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff);
	if (cycles > 0) do_cycles_ce000_internal(cycles);
	m68k_incpci(2);
	return;
}
/* 4+ (1/0) */
/* 2 0,0   */

/* DBcc.W Dn,#<data>.W (NE) */
void REGPARAM2 op_56c8_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 58;
	CurrentInstrCycles = 12; 
	int pcadjust = -2;
	uae_s16 src = m68k_dreg(regs, srcreg);
	uae_s16 offs = regs.irc;
	uaecptr oldpc = m68k_getpci();
	do_cycles_ce000_internal(2);
	if (!cctrue(6)) {
		m68k_incpci((uae_s32)offs + 2);
		if (offs & 1) {
			exception3_read_prefetch(opcode, m68k_getpci());
			return;
		}
		get_word_ce000_prefetch(0);
		if(hardware_bus_error) {
			int pcoffset = 0;
			pcoffset = oldpc - m68k_getpci() + 4;
			exception2_fetch_opcode(opcode, 0, pcoffset);
			return;
		}
		if (src) {
			m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
			regs.ir = regs.irc;
			opcode = regs.ir;
			if(regs.t1) opcode |= 0x10000;
			ipl_fetch_next();
			get_word_ce000_prefetch(2);
			if(hardware_bus_error) {
				int pcoffset = 0;
				exception2_fetch_opcode(opcode, 2, 0);
				return;
			}
			return;
		}
		pcadjust = 0;
	} else {
		do_cycles_ce000_internal(2);
	}
	m68k_setpci_j(oldpc + 4);
	get_word_ce000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		pcoffset += pcadjust;
		exception2_fetch_opcode(opcode, 0, pcoffset);
		return;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	if(regs.t1) opcode |= 0x10000;
	if (!cctrue(6)) {
		m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
	}
	ipl_fetch_next();
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 12 (2/0) */
/* 4 0,0 B */

/* Scc.B (An) (NE) */
void REGPARAM2 op_56d0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	int val = cctrue(6) ? 0xff : 0x00;
	x_put_byte(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 12 (2/1) */
/* 2 0,0   */

/* Scc.B (An)+ (NE) */
void REGPARAM2 op_56d8_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	int val = cctrue(6) ? 0xff : 0x00;
	x_put_byte(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 12 (2/1) */
/* 2 0,0   */

/* Scc.B -(An) (NE) */
void REGPARAM2 op_56e0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
	do_cycles_ce000_internal(2);
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	m68k_areg(regs, srcreg) = srca;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	int val = cctrue(6) ? 0xff : 0x00;
	x_put_byte(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 14 (2/1) */
/* 2 0,0   */

/* Scc.B (d16,An) (NE) */
void REGPARAM2 op_56e8_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	int val = cctrue(6) ? 0xff : 0x00;
	x_put_byte(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* Scc.B (d8,An,Xn) (NE) */
void REGPARAM2 op_56f0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	do_cycles_ce000_internal(2);
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	int val = cctrue(6) ? 0xff : 0x00;
	x_put_byte(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 18 (3/1) */
/* 4 4,0   */

/* Scc.B (xxx).W (NE) */
void REGPARAM2 op_56f8_14_ff(uae_u32 opcode)
{
	OpcodeFamily = 59;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	int val = cctrue(6) ? 0xff : 0x00;
	x_put_byte(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* Scc.B (xxx).L (NE) */
void REGPARAM2 op_56f9_14_ff(uae_u32 opcode)
{
	OpcodeFamily = 59;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	srca = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	srca |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	opcode = regs.ir;
	int val = cctrue(6) ? 0xff : 0x00;
	x_put_byte(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 20 (4/1) */
/* 6 0,0   */

/* Scc.B Dn (EQ) */
void REGPARAM2 op_57c0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 4;  
	uae_s8 src = m68k_dreg(regs, srcreg);
	int val = cctrue(7) ? 0xff : 0x00;
	int cycles = val ? 2 : 0;
	if (!val) {
		m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff);
	}
	opcode |= 0x20000;
	regs.ir = regs.irc;
	if (!val)
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if(!val && regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff);
	if (cycles > 0) do_cycles_ce000_internal(cycles);
	m68k_incpci(2);
	return;
}
/* 4+ (1/0) */
/* 2 0,0   */

/* DBcc.W Dn,#<data>.W (EQ) */
void REGPARAM2 op_57c8_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 58;
	CurrentInstrCycles = 12; 
	int pcadjust = -2;
	uae_s16 src = m68k_dreg(regs, srcreg);
	uae_s16 offs = regs.irc;
	uaecptr oldpc = m68k_getpci();
	do_cycles_ce000_internal(2);
	if (!cctrue(7)) {
		m68k_incpci((uae_s32)offs + 2);
		if (offs & 1) {
			exception3_read_prefetch(opcode, m68k_getpci());
			return;
		}
		get_word_ce000_prefetch(0);
		if(hardware_bus_error) {
			int pcoffset = 0;
			pcoffset = oldpc - m68k_getpci() + 4;
			exception2_fetch_opcode(opcode, 0, pcoffset);
			return;
		}
		if (src) {
			m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
			regs.ir = regs.irc;
			opcode = regs.ir;
			if(regs.t1) opcode |= 0x10000;
			ipl_fetch_next();
			get_word_ce000_prefetch(2);
			if(hardware_bus_error) {
				int pcoffset = 0;
				exception2_fetch_opcode(opcode, 2, 0);
				return;
			}
			return;
		}
		pcadjust = 0;
	} else {
		do_cycles_ce000_internal(2);
	}
	m68k_setpci_j(oldpc + 4);
	get_word_ce000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		pcoffset += pcadjust;
		exception2_fetch_opcode(opcode, 0, pcoffset);
		return;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	if(regs.t1) opcode |= 0x10000;
	if (!cctrue(7)) {
		m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
	}
	ipl_fetch_next();
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 12 (2/0) */
/* 4 0,0 B */

/* Scc.B (An) (EQ) */
void REGPARAM2 op_57d0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	int val = cctrue(7) ? 0xff : 0x00;
	x_put_byte(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 12 (2/1) */
/* 2 0,0   */

/* Scc.B (An)+ (EQ) */
void REGPARAM2 op_57d8_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	int val = cctrue(7) ? 0xff : 0x00;
	x_put_byte(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 12 (2/1) */
/* 2 0,0   */

/* Scc.B -(An) (EQ) */
void REGPARAM2 op_57e0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
	do_cycles_ce000_internal(2);
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	m68k_areg(regs, srcreg) = srca;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	int val = cctrue(7) ? 0xff : 0x00;
	x_put_byte(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 14 (2/1) */
/* 2 0,0   */

/* Scc.B (d16,An) (EQ) */
void REGPARAM2 op_57e8_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	int val = cctrue(7) ? 0xff : 0x00;
	x_put_byte(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* Scc.B (d8,An,Xn) (EQ) */
void REGPARAM2 op_57f0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	do_cycles_ce000_internal(2);
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	int val = cctrue(7) ? 0xff : 0x00;
	x_put_byte(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 18 (3/1) */
/* 4 4,0   */

/* Scc.B (xxx).W (EQ) */
void REGPARAM2 op_57f8_14_ff(uae_u32 opcode)
{
	OpcodeFamily = 59;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	int val = cctrue(7) ? 0xff : 0x00;
	x_put_byte(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* Scc.B (xxx).L (EQ) */
void REGPARAM2 op_57f9_14_ff(uae_u32 opcode)
{
	OpcodeFamily = 59;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	srca = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	srca |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	opcode = regs.ir;
	int val = cctrue(7) ? 0xff : 0x00;
	x_put_byte(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 20 (4/1) */
/* 6 0,0   */

/* Scc.B Dn (VC) */
void REGPARAM2 op_58c0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 4;  
	uae_s8 src = m68k_dreg(regs, srcreg);
	int val = cctrue(8) ? 0xff : 0x00;
	int cycles = val ? 2 : 0;
	if (!val) {
		m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff);
	}
	opcode |= 0x20000;
	regs.ir = regs.irc;
	if (!val)
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if(!val && regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff);
	if (cycles > 0) do_cycles_ce000_internal(cycles);
	m68k_incpci(2);
	return;
}
/* 4+ (1/0) */
/* 2 0,0   */

/* DBcc.W Dn,#<data>.W (VC) */
void REGPARAM2 op_58c8_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 58;
	CurrentInstrCycles = 12; 
	int pcadjust = -2;
	uae_s16 src = m68k_dreg(regs, srcreg);
	uae_s16 offs = regs.irc;
	uaecptr oldpc = m68k_getpci();
	do_cycles_ce000_internal(2);
	if (!cctrue(8)) {
		m68k_incpci((uae_s32)offs + 2);
		if (offs & 1) {
			exception3_read_prefetch(opcode, m68k_getpci());
			return;
		}
		get_word_ce000_prefetch(0);
		if(hardware_bus_error) {
			int pcoffset = 0;
			pcoffset = oldpc - m68k_getpci() + 4;
			exception2_fetch_opcode(opcode, 0, pcoffset);
			return;
		}
		if (src) {
			m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
			regs.ir = regs.irc;
			opcode = regs.ir;
			if(regs.t1) opcode |= 0x10000;
			ipl_fetch_next();
			get_word_ce000_prefetch(2);
			if(hardware_bus_error) {
				int pcoffset = 0;
				exception2_fetch_opcode(opcode, 2, 0);
				return;
			}
			return;
		}
		pcadjust = 0;
	} else {
		do_cycles_ce000_internal(2);
	}
	m68k_setpci_j(oldpc + 4);
	get_word_ce000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		pcoffset += pcadjust;
		exception2_fetch_opcode(opcode, 0, pcoffset);
		return;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	if(regs.t1) opcode |= 0x10000;
	if (!cctrue(8)) {
		m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
	}
	ipl_fetch_next();
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 12 (2/0) */
/* 4 0,0 B */

/* Scc.B (An) (VC) */
void REGPARAM2 op_58d0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	int val = cctrue(8) ? 0xff : 0x00;
	x_put_byte(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 12 (2/1) */
/* 2 0,0   */

/* Scc.B (An)+ (VC) */
void REGPARAM2 op_58d8_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	int val = cctrue(8) ? 0xff : 0x00;
	x_put_byte(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 12 (2/1) */
/* 2 0,0   */

/* Scc.B -(An) (VC) */
void REGPARAM2 op_58e0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
	do_cycles_ce000_internal(2);
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	m68k_areg(regs, srcreg) = srca;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	int val = cctrue(8) ? 0xff : 0x00;
	x_put_byte(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 14 (2/1) */
/* 2 0,0   */

/* Scc.B (d16,An) (VC) */
void REGPARAM2 op_58e8_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	int val = cctrue(8) ? 0xff : 0x00;
	x_put_byte(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* Scc.B (d8,An,Xn) (VC) */
void REGPARAM2 op_58f0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	do_cycles_ce000_internal(2);
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	int val = cctrue(8) ? 0xff : 0x00;
	x_put_byte(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 18 (3/1) */
/* 4 4,0   */

/* Scc.B (xxx).W (VC) */
void REGPARAM2 op_58f8_14_ff(uae_u32 opcode)
{
	OpcodeFamily = 59;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	int val = cctrue(8) ? 0xff : 0x00;
	x_put_byte(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* Scc.B (xxx).L (VC) */
void REGPARAM2 op_58f9_14_ff(uae_u32 opcode)
{
	OpcodeFamily = 59;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	srca = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	srca |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	opcode = regs.ir;
	int val = cctrue(8) ? 0xff : 0x00;
	x_put_byte(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 20 (4/1) */
/* 6 0,0   */

/* Scc.B Dn (VS) */
void REGPARAM2 op_59c0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 4;  
	uae_s8 src = m68k_dreg(regs, srcreg);
	int val = cctrue(9) ? 0xff : 0x00;
	int cycles = val ? 2 : 0;
	if (!val) {
		m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff);
	}
	opcode |= 0x20000;
	regs.ir = regs.irc;
	if (!val)
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if(!val && regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff);
	if (cycles > 0) do_cycles_ce000_internal(cycles);
	m68k_incpci(2);
	return;
}
/* 4+ (1/0) */
/* 2 0,0   */

/* DBcc.W Dn,#<data>.W (VS) */
void REGPARAM2 op_59c8_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 58;
	CurrentInstrCycles = 12; 
	int pcadjust = -2;
	uae_s16 src = m68k_dreg(regs, srcreg);
	uae_s16 offs = regs.irc;
	uaecptr oldpc = m68k_getpci();
	do_cycles_ce000_internal(2);
	if (!cctrue(9)) {
		m68k_incpci((uae_s32)offs + 2);
		if (offs & 1) {
			exception3_read_prefetch(opcode, m68k_getpci());
			return;
		}
		get_word_ce000_prefetch(0);
		if(hardware_bus_error) {
			int pcoffset = 0;
			pcoffset = oldpc - m68k_getpci() + 4;
			exception2_fetch_opcode(opcode, 0, pcoffset);
			return;
		}
		if (src) {
			m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
			regs.ir = regs.irc;
			opcode = regs.ir;
			if(regs.t1) opcode |= 0x10000;
			ipl_fetch_next();
			get_word_ce000_prefetch(2);
			if(hardware_bus_error) {
				int pcoffset = 0;
				exception2_fetch_opcode(opcode, 2, 0);
				return;
			}
			return;
		}
		pcadjust = 0;
	} else {
		do_cycles_ce000_internal(2);
	}
	m68k_setpci_j(oldpc + 4);
	get_word_ce000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		pcoffset += pcadjust;
		exception2_fetch_opcode(opcode, 0, pcoffset);
		return;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	if(regs.t1) opcode |= 0x10000;
	if (!cctrue(9)) {
		m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
	}
	ipl_fetch_next();
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 12 (2/0) */
/* 4 0,0 B */

/* Scc.B (An) (VS) */
void REGPARAM2 op_59d0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	int val = cctrue(9) ? 0xff : 0x00;
	x_put_byte(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 12 (2/1) */
/* 2 0,0   */

/* Scc.B (An)+ (VS) */
void REGPARAM2 op_59d8_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	int val = cctrue(9) ? 0xff : 0x00;
	x_put_byte(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 12 (2/1) */
/* 2 0,0   */

/* Scc.B -(An) (VS) */
void REGPARAM2 op_59e0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
	do_cycles_ce000_internal(2);
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	m68k_areg(regs, srcreg) = srca;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	int val = cctrue(9) ? 0xff : 0x00;
	x_put_byte(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 14 (2/1) */
/* 2 0,0   */

/* Scc.B (d16,An) (VS) */
void REGPARAM2 op_59e8_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	int val = cctrue(9) ? 0xff : 0x00;
	x_put_byte(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* Scc.B (d8,An,Xn) (VS) */
void REGPARAM2 op_59f0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	do_cycles_ce000_internal(2);
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	int val = cctrue(9) ? 0xff : 0x00;
	x_put_byte(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 18 (3/1) */
/* 4 4,0   */

/* Scc.B (xxx).W (VS) */
void REGPARAM2 op_59f8_14_ff(uae_u32 opcode)
{
	OpcodeFamily = 59;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	int val = cctrue(9) ? 0xff : 0x00;
	x_put_byte(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* Scc.B (xxx).L (VS) */
void REGPARAM2 op_59f9_14_ff(uae_u32 opcode)
{
	OpcodeFamily = 59;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	srca = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	srca |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	opcode = regs.ir;
	int val = cctrue(9) ? 0xff : 0x00;
	x_put_byte(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 20 (4/1) */
/* 6 0,0   */

/* Scc.B Dn (PL) */
void REGPARAM2 op_5ac0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 4;  
	uae_s8 src = m68k_dreg(regs, srcreg);
	int val = cctrue(10) ? 0xff : 0x00;
	int cycles = val ? 2 : 0;
	if (!val) {
		m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff);
	}
	opcode |= 0x20000;
	regs.ir = regs.irc;
	if (!val)
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if(!val && regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff);
	if (cycles > 0) do_cycles_ce000_internal(cycles);
	m68k_incpci(2);
	return;
}
/* 4+ (1/0) */
/* 2 0,0   */

/* DBcc.W Dn,#<data>.W (PL) */
void REGPARAM2 op_5ac8_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 58;
	CurrentInstrCycles = 12; 
	int pcadjust = -2;
	uae_s16 src = m68k_dreg(regs, srcreg);
	uae_s16 offs = regs.irc;
	uaecptr oldpc = m68k_getpci();
	do_cycles_ce000_internal(2);
	if (!cctrue(10)) {
		m68k_incpci((uae_s32)offs + 2);
		if (offs & 1) {
			exception3_read_prefetch(opcode, m68k_getpci());
			return;
		}
		get_word_ce000_prefetch(0);
		if(hardware_bus_error) {
			int pcoffset = 0;
			pcoffset = oldpc - m68k_getpci() + 4;
			exception2_fetch_opcode(opcode, 0, pcoffset);
			return;
		}
		if (src) {
			m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
			regs.ir = regs.irc;
			opcode = regs.ir;
			if(regs.t1) opcode |= 0x10000;
			ipl_fetch_next();
			get_word_ce000_prefetch(2);
			if(hardware_bus_error) {
				int pcoffset = 0;
				exception2_fetch_opcode(opcode, 2, 0);
				return;
			}
			return;
		}
		pcadjust = 0;
	} else {
		do_cycles_ce000_internal(2);
	}
	m68k_setpci_j(oldpc + 4);
	get_word_ce000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		pcoffset += pcadjust;
		exception2_fetch_opcode(opcode, 0, pcoffset);
		return;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	if(regs.t1) opcode |= 0x10000;
	if (!cctrue(10)) {
		m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
	}
	ipl_fetch_next();
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 12 (2/0) */
/* 4 0,0 B */

/* Scc.B (An) (PL) */
void REGPARAM2 op_5ad0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	int val = cctrue(10) ? 0xff : 0x00;
	x_put_byte(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 12 (2/1) */
/* 2 0,0   */

/* Scc.B (An)+ (PL) */
void REGPARAM2 op_5ad8_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	int val = cctrue(10) ? 0xff : 0x00;
	x_put_byte(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 12 (2/1) */
/* 2 0,0   */

/* Scc.B -(An) (PL) */
void REGPARAM2 op_5ae0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
	do_cycles_ce000_internal(2);
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	m68k_areg(regs, srcreg) = srca;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	int val = cctrue(10) ? 0xff : 0x00;
	x_put_byte(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 14 (2/1) */
/* 2 0,0   */

/* Scc.B (d16,An) (PL) */
void REGPARAM2 op_5ae8_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	int val = cctrue(10) ? 0xff : 0x00;
	x_put_byte(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* Scc.B (d8,An,Xn) (PL) */
void REGPARAM2 op_5af0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	do_cycles_ce000_internal(2);
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	int val = cctrue(10) ? 0xff : 0x00;
	x_put_byte(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 18 (3/1) */
/* 4 4,0   */

/* Scc.B (xxx).W (PL) */
void REGPARAM2 op_5af8_14_ff(uae_u32 opcode)
{
	OpcodeFamily = 59;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	int val = cctrue(10) ? 0xff : 0x00;
	x_put_byte(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* Scc.B (xxx).L (PL) */
void REGPARAM2 op_5af9_14_ff(uae_u32 opcode)
{
	OpcodeFamily = 59;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	srca = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	srca |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	opcode = regs.ir;
	int val = cctrue(10) ? 0xff : 0x00;
	x_put_byte(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 20 (4/1) */
/* 6 0,0   */

/* Scc.B Dn (MI) */
void REGPARAM2 op_5bc0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 4;  
	uae_s8 src = m68k_dreg(regs, srcreg);
	int val = cctrue(11) ? 0xff : 0x00;
	int cycles = val ? 2 : 0;
	if (!val) {
		m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff);
	}
	opcode |= 0x20000;
	regs.ir = regs.irc;
	if (!val)
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if(!val && regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff);
	if (cycles > 0) do_cycles_ce000_internal(cycles);
	m68k_incpci(2);
	return;
}
/* 4+ (1/0) */
/* 2 0,0   */

/* DBcc.W Dn,#<data>.W (MI) */
void REGPARAM2 op_5bc8_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 58;
	CurrentInstrCycles = 12; 
	int pcadjust = -2;
	uae_s16 src = m68k_dreg(regs, srcreg);
	uae_s16 offs = regs.irc;
	uaecptr oldpc = m68k_getpci();
	do_cycles_ce000_internal(2);
	if (!cctrue(11)) {
		m68k_incpci((uae_s32)offs + 2);
		if (offs & 1) {
			exception3_read_prefetch(opcode, m68k_getpci());
			return;
		}
		get_word_ce000_prefetch(0);
		if(hardware_bus_error) {
			int pcoffset = 0;
			pcoffset = oldpc - m68k_getpci() + 4;
			exception2_fetch_opcode(opcode, 0, pcoffset);
			return;
		}
		if (src) {
			m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
			regs.ir = regs.irc;
			opcode = regs.ir;
			if(regs.t1) opcode |= 0x10000;
			ipl_fetch_next();
			get_word_ce000_prefetch(2);
			if(hardware_bus_error) {
				int pcoffset = 0;
				exception2_fetch_opcode(opcode, 2, 0);
				return;
			}
			return;
		}
		pcadjust = 0;
	} else {
		do_cycles_ce000_internal(2);
	}
	m68k_setpci_j(oldpc + 4);
	get_word_ce000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		pcoffset += pcadjust;
		exception2_fetch_opcode(opcode, 0, pcoffset);
		return;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	if(regs.t1) opcode |= 0x10000;
	if (!cctrue(11)) {
		m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
	}
	ipl_fetch_next();
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 12 (2/0) */
/* 4 0,0 B */

/* Scc.B (An) (MI) */
void REGPARAM2 op_5bd0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	int val = cctrue(11) ? 0xff : 0x00;
	x_put_byte(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 12 (2/1) */
/* 2 0,0   */

/* Scc.B (An)+ (MI) */
void REGPARAM2 op_5bd8_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	int val = cctrue(11) ? 0xff : 0x00;
	x_put_byte(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 12 (2/1) */
/* 2 0,0   */

/* Scc.B -(An) (MI) */
void REGPARAM2 op_5be0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
	do_cycles_ce000_internal(2);
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	m68k_areg(regs, srcreg) = srca;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	int val = cctrue(11) ? 0xff : 0x00;
	x_put_byte(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 14 (2/1) */
/* 2 0,0   */

/* Scc.B (d16,An) (MI) */
void REGPARAM2 op_5be8_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	int val = cctrue(11) ? 0xff : 0x00;
	x_put_byte(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* Scc.B (d8,An,Xn) (MI) */
void REGPARAM2 op_5bf0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	do_cycles_ce000_internal(2);
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	int val = cctrue(11) ? 0xff : 0x00;
	x_put_byte(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 18 (3/1) */
/* 4 4,0   */

/* Scc.B (xxx).W (MI) */
void REGPARAM2 op_5bf8_14_ff(uae_u32 opcode)
{
	OpcodeFamily = 59;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	int val = cctrue(11) ? 0xff : 0x00;
	x_put_byte(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* Scc.B (xxx).L (MI) */
void REGPARAM2 op_5bf9_14_ff(uae_u32 opcode)
{
	OpcodeFamily = 59;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	srca = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	srca |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	opcode = regs.ir;
	int val = cctrue(11) ? 0xff : 0x00;
	x_put_byte(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 20 (4/1) */
/* 6 0,0   */

/* Scc.B Dn (GE) */
void REGPARAM2 op_5cc0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 4;  
	uae_s8 src = m68k_dreg(regs, srcreg);
	int val = cctrue(12) ? 0xff : 0x00;
	int cycles = val ? 2 : 0;
	if (!val) {
		m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff);
	}
	opcode |= 0x20000;
	regs.ir = regs.irc;
	if (!val)
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if(!val && regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff);
	if (cycles > 0) do_cycles_ce000_internal(cycles);
	m68k_incpci(2);
	return;
}
/* 4+ (1/0) */
/* 2 0,0   */

/* DBcc.W Dn,#<data>.W (GE) */
void REGPARAM2 op_5cc8_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 58;
	CurrentInstrCycles = 12; 
	int pcadjust = -2;
	uae_s16 src = m68k_dreg(regs, srcreg);
	uae_s16 offs = regs.irc;
	uaecptr oldpc = m68k_getpci();
	do_cycles_ce000_internal(2);
	if (!cctrue(12)) {
		m68k_incpci((uae_s32)offs + 2);
		if (offs & 1) {
			exception3_read_prefetch(opcode, m68k_getpci());
			return;
		}
		get_word_ce000_prefetch(0);
		if(hardware_bus_error) {
			int pcoffset = 0;
			pcoffset = oldpc - m68k_getpci() + 4;
			exception2_fetch_opcode(opcode, 0, pcoffset);
			return;
		}
		if (src) {
			m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
			regs.ir = regs.irc;
			opcode = regs.ir;
			if(regs.t1) opcode |= 0x10000;
			ipl_fetch_next();
			get_word_ce000_prefetch(2);
			if(hardware_bus_error) {
				int pcoffset = 0;
				exception2_fetch_opcode(opcode, 2, 0);
				return;
			}
			return;
		}
		pcadjust = 0;
	} else {
		do_cycles_ce000_internal(2);
	}
	m68k_setpci_j(oldpc + 4);
	get_word_ce000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		pcoffset += pcadjust;
		exception2_fetch_opcode(opcode, 0, pcoffset);
		return;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	if(regs.t1) opcode |= 0x10000;
	if (!cctrue(12)) {
		m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
	}
	ipl_fetch_next();
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 12 (2/0) */
/* 4 0,0 B */

/* Scc.B (An) (GE) */
void REGPARAM2 op_5cd0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	int val = cctrue(12) ? 0xff : 0x00;
	x_put_byte(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 12 (2/1) */
/* 2 0,0   */

/* Scc.B (An)+ (GE) */
void REGPARAM2 op_5cd8_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	int val = cctrue(12) ? 0xff : 0x00;
	x_put_byte(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 12 (2/1) */
/* 2 0,0   */

/* Scc.B -(An) (GE) */
void REGPARAM2 op_5ce0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
	do_cycles_ce000_internal(2);
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	m68k_areg(regs, srcreg) = srca;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	int val = cctrue(12) ? 0xff : 0x00;
	x_put_byte(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 14 (2/1) */
/* 2 0,0   */

/* Scc.B (d16,An) (GE) */
void REGPARAM2 op_5ce8_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	int val = cctrue(12) ? 0xff : 0x00;
	x_put_byte(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* Scc.B (d8,An,Xn) (GE) */
void REGPARAM2 op_5cf0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	do_cycles_ce000_internal(2);
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	int val = cctrue(12) ? 0xff : 0x00;
	x_put_byte(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 18 (3/1) */
/* 4 4,0   */

/* Scc.B (xxx).W (GE) */
void REGPARAM2 op_5cf8_14_ff(uae_u32 opcode)
{
	OpcodeFamily = 59;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	int val = cctrue(12) ? 0xff : 0x00;
	x_put_byte(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* Scc.B (xxx).L (GE) */
void REGPARAM2 op_5cf9_14_ff(uae_u32 opcode)
{
	OpcodeFamily = 59;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	srca = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	srca |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	opcode = regs.ir;
	int val = cctrue(12) ? 0xff : 0x00;
	x_put_byte(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 20 (4/1) */
/* 6 0,0   */

/* Scc.B Dn (LT) */
void REGPARAM2 op_5dc0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 4;  
	uae_s8 src = m68k_dreg(regs, srcreg);
	int val = cctrue(13) ? 0xff : 0x00;
	int cycles = val ? 2 : 0;
	if (!val) {
		m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff);
	}
	opcode |= 0x20000;
	regs.ir = regs.irc;
	if (!val)
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if(!val && regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff);
	if (cycles > 0) do_cycles_ce000_internal(cycles);
	m68k_incpci(2);
	return;
}
/* 4+ (1/0) */
/* 2 0,0   */

/* DBcc.W Dn,#<data>.W (LT) */
void REGPARAM2 op_5dc8_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 58;
	CurrentInstrCycles = 12; 
	int pcadjust = -2;
	uae_s16 src = m68k_dreg(regs, srcreg);
	uae_s16 offs = regs.irc;
	uaecptr oldpc = m68k_getpci();
	do_cycles_ce000_internal(2);
	if (!cctrue(13)) {
		m68k_incpci((uae_s32)offs + 2);
		if (offs & 1) {
			exception3_read_prefetch(opcode, m68k_getpci());
			return;
		}
		get_word_ce000_prefetch(0);
		if(hardware_bus_error) {
			int pcoffset = 0;
			pcoffset = oldpc - m68k_getpci() + 4;
			exception2_fetch_opcode(opcode, 0, pcoffset);
			return;
		}
		if (src) {
			m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
			regs.ir = regs.irc;
			opcode = regs.ir;
			if(regs.t1) opcode |= 0x10000;
			ipl_fetch_next();
			get_word_ce000_prefetch(2);
			if(hardware_bus_error) {
				int pcoffset = 0;
				exception2_fetch_opcode(opcode, 2, 0);
				return;
			}
			return;
		}
		pcadjust = 0;
	} else {
		do_cycles_ce000_internal(2);
	}
	m68k_setpci_j(oldpc + 4);
	get_word_ce000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		pcoffset += pcadjust;
		exception2_fetch_opcode(opcode, 0, pcoffset);
		return;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	if(regs.t1) opcode |= 0x10000;
	if (!cctrue(13)) {
		m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
	}
	ipl_fetch_next();
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 12 (2/0) */
/* 4 0,0 B */

/* Scc.B (An) (LT) */
void REGPARAM2 op_5dd0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	int val = cctrue(13) ? 0xff : 0x00;
	x_put_byte(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 12 (2/1) */
/* 2 0,0   */

/* Scc.B (An)+ (LT) */
void REGPARAM2 op_5dd8_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	int val = cctrue(13) ? 0xff : 0x00;
	x_put_byte(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 12 (2/1) */
/* 2 0,0   */

/* Scc.B -(An) (LT) */
void REGPARAM2 op_5de0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
	do_cycles_ce000_internal(2);
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	m68k_areg(regs, srcreg) = srca;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	int val = cctrue(13) ? 0xff : 0x00;
	x_put_byte(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 14 (2/1) */
/* 2 0,0   */

/* Scc.B (d16,An) (LT) */
void REGPARAM2 op_5de8_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	int val = cctrue(13) ? 0xff : 0x00;
	x_put_byte(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* Scc.B (d8,An,Xn) (LT) */
void REGPARAM2 op_5df0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	do_cycles_ce000_internal(2);
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	int val = cctrue(13) ? 0xff : 0x00;
	x_put_byte(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 18 (3/1) */
/* 4 4,0   */

/* Scc.B (xxx).W (LT) */
void REGPARAM2 op_5df8_14_ff(uae_u32 opcode)
{
	OpcodeFamily = 59;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	int val = cctrue(13) ? 0xff : 0x00;
	x_put_byte(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* Scc.B (xxx).L (LT) */
void REGPARAM2 op_5df9_14_ff(uae_u32 opcode)
{
	OpcodeFamily = 59;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	srca = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	srca |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	opcode = regs.ir;
	int val = cctrue(13) ? 0xff : 0x00;
	x_put_byte(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 20 (4/1) */
/* 6 0,0   */

/* Scc.B Dn (GT) */
void REGPARAM2 op_5ec0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 4;  
	uae_s8 src = m68k_dreg(regs, srcreg);
	int val = cctrue(14) ? 0xff : 0x00;
	int cycles = val ? 2 : 0;
	if (!val) {
		m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff);
	}
	opcode |= 0x20000;
	regs.ir = regs.irc;
	if (!val)
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if(!val && regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff);
	if (cycles > 0) do_cycles_ce000_internal(cycles);
	m68k_incpci(2);
	return;
}
/* 4+ (1/0) */
/* 2 0,0   */

/* DBcc.W Dn,#<data>.W (GT) */
void REGPARAM2 op_5ec8_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 58;
	CurrentInstrCycles = 12; 
	int pcadjust = -2;
	uae_s16 src = m68k_dreg(regs, srcreg);
	uae_s16 offs = regs.irc;
	uaecptr oldpc = m68k_getpci();
	do_cycles_ce000_internal(2);
	if (!cctrue(14)) {
		m68k_incpci((uae_s32)offs + 2);
		if (offs & 1) {
			exception3_read_prefetch(opcode, m68k_getpci());
			return;
		}
		get_word_ce000_prefetch(0);
		if(hardware_bus_error) {
			int pcoffset = 0;
			pcoffset = oldpc - m68k_getpci() + 4;
			exception2_fetch_opcode(opcode, 0, pcoffset);
			return;
		}
		if (src) {
			m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
			regs.ir = regs.irc;
			opcode = regs.ir;
			if(regs.t1) opcode |= 0x10000;
			ipl_fetch_next();
			get_word_ce000_prefetch(2);
			if(hardware_bus_error) {
				int pcoffset = 0;
				exception2_fetch_opcode(opcode, 2, 0);
				return;
			}
			return;
		}
		pcadjust = 0;
	} else {
		do_cycles_ce000_internal(2);
	}
	m68k_setpci_j(oldpc + 4);
	get_word_ce000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		pcoffset += pcadjust;
		exception2_fetch_opcode(opcode, 0, pcoffset);
		return;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	if(regs.t1) opcode |= 0x10000;
	if (!cctrue(14)) {
		m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
	}
	ipl_fetch_next();
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 12 (2/0) */
/* 4 0,0 B */

/* Scc.B (An) (GT) */
void REGPARAM2 op_5ed0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	int val = cctrue(14) ? 0xff : 0x00;
	x_put_byte(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 12 (2/1) */
/* 2 0,0   */

/* Scc.B (An)+ (GT) */
void REGPARAM2 op_5ed8_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	int val = cctrue(14) ? 0xff : 0x00;
	x_put_byte(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 12 (2/1) */
/* 2 0,0   */

/* Scc.B -(An) (GT) */
void REGPARAM2 op_5ee0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
	do_cycles_ce000_internal(2);
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	m68k_areg(regs, srcreg) = srca;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	int val = cctrue(14) ? 0xff : 0x00;
	x_put_byte(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 14 (2/1) */
/* 2 0,0   */

/* Scc.B (d16,An) (GT) */
void REGPARAM2 op_5ee8_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	int val = cctrue(14) ? 0xff : 0x00;
	x_put_byte(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* Scc.B (d8,An,Xn) (GT) */
void REGPARAM2 op_5ef0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	do_cycles_ce000_internal(2);
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	int val = cctrue(14) ? 0xff : 0x00;
	x_put_byte(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 18 (3/1) */
/* 4 4,0   */

/* Scc.B (xxx).W (GT) */
void REGPARAM2 op_5ef8_14_ff(uae_u32 opcode)
{
	OpcodeFamily = 59;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	int val = cctrue(14) ? 0xff : 0x00;
	x_put_byte(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* Scc.B (xxx).L (GT) */
void REGPARAM2 op_5ef9_14_ff(uae_u32 opcode)
{
	OpcodeFamily = 59;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	srca = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	srca |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	opcode = regs.ir;
	int val = cctrue(14) ? 0xff : 0x00;
	x_put_byte(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 20 (4/1) */
/* 6 0,0   */

/* Scc.B Dn (LE) */
void REGPARAM2 op_5fc0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 4;  
	uae_s8 src = m68k_dreg(regs, srcreg);
	int val = cctrue(15) ? 0xff : 0x00;
	int cycles = val ? 2 : 0;
	if (!val) {
		m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff);
	}
	opcode |= 0x20000;
	regs.ir = regs.irc;
	if (!val)
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if(!val && regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff);
	if (cycles > 0) do_cycles_ce000_internal(cycles);
	m68k_incpci(2);
	return;
}
/* 4+ (1/0) */
/* 2 0,0   */

/* DBcc.W Dn,#<data>.W (LE) */
void REGPARAM2 op_5fc8_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 58;
	CurrentInstrCycles = 12; 
	int pcadjust = -2;
	uae_s16 src = m68k_dreg(regs, srcreg);
	uae_s16 offs = regs.irc;
	uaecptr oldpc = m68k_getpci();
	do_cycles_ce000_internal(2);
	if (!cctrue(15)) {
		m68k_incpci((uae_s32)offs + 2);
		if (offs & 1) {
			exception3_read_prefetch(opcode, m68k_getpci());
			return;
		}
		get_word_ce000_prefetch(0);
		if(hardware_bus_error) {
			int pcoffset = 0;
			pcoffset = oldpc - m68k_getpci() + 4;
			exception2_fetch_opcode(opcode, 0, pcoffset);
			return;
		}
		if (src) {
			m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
			regs.ir = regs.irc;
			opcode = regs.ir;
			if(regs.t1) opcode |= 0x10000;
			ipl_fetch_next();
			get_word_ce000_prefetch(2);
			if(hardware_bus_error) {
				int pcoffset = 0;
				exception2_fetch_opcode(opcode, 2, 0);
				return;
			}
			return;
		}
		pcadjust = 0;
	} else {
		do_cycles_ce000_internal(2);
	}
	m68k_setpci_j(oldpc + 4);
	get_word_ce000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		pcoffset += pcadjust;
		exception2_fetch_opcode(opcode, 0, pcoffset);
		return;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	if(regs.t1) opcode |= 0x10000;
	if (!cctrue(15)) {
		m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
	}
	ipl_fetch_next();
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 12 (2/0) */
/* 4 0,0 B */

/* Scc.B (An) (LE) */
void REGPARAM2 op_5fd0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	int val = cctrue(15) ? 0xff : 0x00;
	x_put_byte(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 12 (2/1) */
/* 2 0,0   */

/* Scc.B (An)+ (LE) */
void REGPARAM2 op_5fd8_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	int val = cctrue(15) ? 0xff : 0x00;
	x_put_byte(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 12 (2/1) */
/* 2 0,0   */

/* Scc.B -(An) (LE) */
void REGPARAM2 op_5fe0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
	do_cycles_ce000_internal(2);
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	m68k_areg(regs, srcreg) = srca;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	int val = cctrue(15) ? 0xff : 0x00;
	x_put_byte(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 14 (2/1) */
/* 2 0,0   */

/* Scc.B (d16,An) (LE) */
void REGPARAM2 op_5fe8_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	int val = cctrue(15) ? 0xff : 0x00;
	x_put_byte(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* Scc.B (d8,An,Xn) (LE) */
void REGPARAM2 op_5ff0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 59;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	do_cycles_ce000_internal(2);
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	int val = cctrue(15) ? 0xff : 0x00;
	x_put_byte(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 18 (3/1) */
/* 4 4,0   */

/* Scc.B (xxx).W (LE) */
void REGPARAM2 op_5ff8_14_ff(uae_u32 opcode)
{
	OpcodeFamily = 59;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	int val = cctrue(15) ? 0xff : 0x00;
	x_put_byte(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* Scc.B (xxx).L (LE) */
void REGPARAM2 op_5ff9_14_ff(uae_u32 opcode)
{
	OpcodeFamily = 59;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	srca = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	srca |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	opcode = regs.ir;
	int val = cctrue(15) ? 0xff : 0x00;
	x_put_byte(srca, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, srca + 0, 0x0, val, 1);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 20 (4/1) */
/* 6 0,0   */

/* Bcc.W #<data>.W (T) */
void REGPARAM2 op_6000_14_ff(uae_u32 opcode)
{
	OpcodeFamily = 55;
	CurrentInstrCycles = 12; 
	uaecptr oldpc = m68k_getpci();
	uae_s16 src = regs.irc;
	do_cycles_ce000_internal(2);
	if (cctrue(0)) {
		if (src & 1) {
			uaecptr addr = m68k_getpci() + (uae_s32)src + 2;
			exception3_read_prefetch(opcode, addr);
			return;
		}
		m68k_incpci((uae_s32)src + 2);
		int pcadjust = oldpc - m68k_getpci() + 2;
		get_word_ce000_prefetch(0);
		if(hardware_bus_error) {
			int pcoffset = 0;
			pcoffset += pcadjust;
			exception2_fetch_opcode(opcode, 0, pcoffset);
			return;
		}
		regs.ir = regs.irc;
		opcode = regs.ir;
		if(regs.t1) opcode |= 0x10000;
		ipl_fetch_next();
		get_word_ce000_prefetch(2);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 2, pcoffset);
			return;
		}
		return;
	}
	m68k_incpci(4);
	do_cycles_ce000_internal(2);
	get_word_ce000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, pcoffset);
		return;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	if(regs.t1) opcode |= 0x10000;
	ipl_fetch_next();
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 12 (2/0) */
/* 4 0,0 B */

/* BccQ.B #<data> (T) */
void REGPARAM2 op_6001_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (uae_s32)(uae_s8)(real_opcode & 255);
	OpcodeFamily = 55;
	CurrentInstrCycles = 8;  
	uaecptr oldpc = m68k_getpci();
	uae_u32 src = srcreg;
	do_cycles_ce000_internal(2);
	if (cctrue(0)) {
		if (src & 1) {
			uaecptr addr = m68k_getpci() + (uae_s32)src + 2;
			exception3_read_prefetch(opcode, addr);
			return;
		}
		m68k_incpci((uae_s32)src + 2);
		int pcadjust = oldpc - m68k_getpci() + 2;
		get_word_ce000_prefetch(0);
		if(hardware_bus_error) {
			int pcoffset = 0;
			pcoffset += pcadjust;
			exception2_fetch_opcode(opcode, 0, pcoffset);
			return;
		}
		regs.ir = regs.irc;
		opcode = regs.ir;
		if(regs.t1) opcode |= 0x10000;
		ipl_fetch_next();
		get_word_ce000_prefetch(2);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 2, pcoffset);
			return;
		}
		return;
	}
	m68k_incpci(2);
	do_cycles_ce000_internal(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	if(regs.t1) opcode |= 0x10000;
	ipl_fetch_next();
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 8 (1/0) */
/* 2 0,0 B */

/* Bcc.L #<data>.L (T) */
void REGPARAM2 op_60ff_14_ff(uae_u32 opcode)
{
	OpcodeFamily = 55;
	CurrentInstrCycles = 8;  
	uaecptr oldpc = m68k_getpci();
	do_cycles_ce000_internal(2);
	if (cctrue(0)) {
		exception3_read_prefetch(opcode, m68k_getpci() + 1);
		return;
	}
	m68k_incpci(2);
	do_cycles_ce000_internal(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	if(regs.t1) opcode |= 0x10000;
	ipl_fetch_next();
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 8 (1/0) */
/* 2 0,0   */

/* BSR.W #<data>.W */
void REGPARAM2 op_6100_14_ff(uae_u32 opcode)
{
	OpcodeFamily = 54;
	CurrentInstrCycles = 18; 
	uae_s32 s;
	uae_s16 src = regs.irc;
	s = (uae_s32)src + 2;
	do_cycles_ce000_internal(2);
	uaecptr oldpc = m68k_getpci();
	uaecptr nextpc = oldpc + 4;
	if (m68k_areg(regs, 7) & 1) {
		m68k_areg(regs, 7) -= 4;
		m68k_incpci(2);
		exception3_write_access(opcode, m68k_areg(regs, 7), sz_word, oldpc, 1);
		return;
	}
	m68k_areg(regs, 7) -= 4;
	uaecptr dsta = m68k_areg(regs, 7);
	x_put_word(dsta, nextpc >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		exception2_write(opcode, dsta + 0, 0x1, nextpc >> 16, 1);
		return;
	}
	x_put_word(dsta + 2, nextpc);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		exception2_write(opcode, dsta + 2, 0x1, nextpc, 1);
		return;
	}
	m68k_incpci(s);
	if (m68k_getpci() & 1) {
		uaecptr addr = m68k_getpci();
		m68k_incpci(-2);
		exception3_read_prefetch(opcode, addr);
		return;
	}
	#ifdef DEBUGGER
	if (debugmem_trace) {
		branch_stack_push(oldpc, nextpc);
	}
	#endif
	get_word_ce000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, pcoffset);
		return;
	}
	regs.ir = regs.irc;
	ipl_fetch_next();
	opcode = regs.ir;
	if(regs.t1) opcode |= 0x10000;
	ipl_fetch_next();
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 18 (2/2) */
/* 4 0,0 B */

/* BSRQ.B #<data> */
void REGPARAM2 op_6101_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (uae_s32)(uae_s8)(real_opcode & 255);
	OpcodeFamily = 54;
	CurrentInstrCycles = 18; 
	uae_s32 s;
	uae_u32 src = srcreg;
	s = (uae_s32)src + 2;
	do_cycles_ce000_internal(2);
	uaecptr oldpc = m68k_getpci();
	uaecptr nextpc = oldpc + 2;
	if (m68k_areg(regs, 7) & 1) {
		m68k_areg(regs, 7) -= 4;
		m68k_incpci(2);
		exception3_write_access(opcode, m68k_areg(regs, 7), sz_word, oldpc, 1);
		return;
	}
	m68k_areg(regs, 7) -= 4;
	uaecptr dsta = m68k_areg(regs, 7);
	x_put_word(dsta, nextpc >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		exception2_write(opcode, dsta + 0, 0x1, nextpc >> 16, 1);
		return;
	}
	x_put_word(dsta + 2, nextpc);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		exception2_write(opcode, dsta + 2, 0x1, nextpc, 1);
		return;
	}
	m68k_incpci(s);
	if (m68k_getpci() & 1) {
		uaecptr addr = m68k_getpci();
		m68k_incpci(-2);
		exception3_read_prefetch(opcode, addr);
		return;
	}
	#ifdef DEBUGGER
	if (debugmem_trace) {
		branch_stack_push(oldpc, nextpc);
	}
	#endif
	get_word_ce000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, pcoffset);
		return;
	}
	regs.ir = regs.irc;
	ipl_fetch_next();
	opcode = regs.ir;
	if(regs.t1) opcode |= 0x10000;
	ipl_fetch_next();
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 18 (2/2) */
/* 2 0,0 B */

/* BSR.L #<data>.L */
void REGPARAM2 op_61ff_14_ff(uae_u32 opcode)
{
	OpcodeFamily = 54;
	CurrentInstrCycles = 18; 
	uae_s32 s;
	uae_u32 src = 0xffffffff;
	s = (uae_s32)src + 2;
	do_cycles_ce000_internal(2);
	uaecptr oldpc = m68k_getpci();
	uaecptr nextpc = oldpc + 2;
	if (m68k_areg(regs, 7) & 1) {
		m68k_areg(regs, 7) -= 4;
		m68k_incpci(2);
		exception3_write_access(opcode, m68k_areg(regs, 7), sz_word, oldpc, 1);
		return;
	}
	m68k_areg(regs, 7) -= 4;
	uaecptr dsta = m68k_areg(regs, 7);
	x_put_word(dsta, nextpc >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		exception2_write(opcode, dsta + 0, 0x1, nextpc >> 16, 1);
		return;
	}
	x_put_word(dsta + 2, nextpc);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		exception2_write(opcode, dsta + 2, 0x1, nextpc, 1);
		return;
	}
	m68k_incpci(s);
	if (m68k_getpci() & 1) {
		uaecptr addr = m68k_getpci();
		m68k_incpci(-2);
		exception3_read_prefetch(opcode, addr);
		return;
	}
	#ifdef DEBUGGER
	if (debugmem_trace) {
		branch_stack_push(oldpc, nextpc);
	}
	#endif
	get_word_ce000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, pcoffset);
		return;
	}
	regs.ir = regs.irc;
	ipl_fetch_next();
	opcode = regs.ir;
	if(regs.t1) opcode |= 0x10000;
	ipl_fetch_next();
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 18 (2/2) */
/* 2 0,0 B */

/* Bcc.W #<data>.W (HI) */
void REGPARAM2 op_6200_14_ff(uae_u32 opcode)
{
	OpcodeFamily = 55;
	CurrentInstrCycles = 12; 
	uaecptr oldpc = m68k_getpci();
	uae_s16 src = regs.irc;
	do_cycles_ce000_internal(2);
	if (cctrue(2)) {
		if (src & 1) {
			uaecptr addr = m68k_getpci() + (uae_s32)src + 2;
			exception3_read_prefetch(opcode, addr);
			return;
		}
		m68k_incpci((uae_s32)src + 2);
		int pcadjust = oldpc - m68k_getpci() + 2;
		get_word_ce000_prefetch(0);
		if(hardware_bus_error) {
			int pcoffset = 0;
			pcoffset += pcadjust;
			exception2_fetch_opcode(opcode, 0, pcoffset);
			return;
		}
		regs.ir = regs.irc;
		opcode = regs.ir;
		if(regs.t1) opcode |= 0x10000;
		ipl_fetch_next();
		get_word_ce000_prefetch(2);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 2, pcoffset);
			return;
		}
		return;
	}
	m68k_incpci(4);
	do_cycles_ce000_internal(2);
	get_word_ce000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, pcoffset);
		return;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	if(regs.t1) opcode |= 0x10000;
	ipl_fetch_next();
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 12 (2/0) */
/* 4 0,0 B */

/* BccQ.B #<data> (HI) */
void REGPARAM2 op_6201_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (uae_s32)(uae_s8)(real_opcode & 255);
	OpcodeFamily = 55;
	CurrentInstrCycles = 8;  
	uaecptr oldpc = m68k_getpci();
	uae_u32 src = srcreg;
	do_cycles_ce000_internal(2);
	if (cctrue(2)) {
		if (src & 1) {
			uaecptr addr = m68k_getpci() + (uae_s32)src + 2;
			exception3_read_prefetch(opcode, addr);
			return;
		}
		m68k_incpci((uae_s32)src + 2);
		int pcadjust = oldpc - m68k_getpci() + 2;
		get_word_ce000_prefetch(0);
		if(hardware_bus_error) {
			int pcoffset = 0;
			pcoffset += pcadjust;
			exception2_fetch_opcode(opcode, 0, pcoffset);
			return;
		}
		regs.ir = regs.irc;
		opcode = regs.ir;
		if(regs.t1) opcode |= 0x10000;
		ipl_fetch_next();
		get_word_ce000_prefetch(2);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 2, pcoffset);
			return;
		}
		return;
	}
	m68k_incpci(2);
	do_cycles_ce000_internal(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	if(regs.t1) opcode |= 0x10000;
	ipl_fetch_next();
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 8 (1/0) */
/* 2 0,0 B */

/* Bcc.L #<data>.L (HI) */
void REGPARAM2 op_62ff_14_ff(uae_u32 opcode)
{
	OpcodeFamily = 55;
	CurrentInstrCycles = 8;  
	uaecptr oldpc = m68k_getpci();
	do_cycles_ce000_internal(2);
	if (cctrue(2)) {
		exception3_read_prefetch(opcode, m68k_getpci() + 1);
		return;
	}
	m68k_incpci(2);
	do_cycles_ce000_internal(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	if(regs.t1) opcode |= 0x10000;
	ipl_fetch_next();
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 8 (1/0) */
/* 2 0,0   */

/* Bcc.W #<data>.W (LS) */
void REGPARAM2 op_6300_14_ff(uae_u32 opcode)
{
	OpcodeFamily = 55;
	CurrentInstrCycles = 12; 
	uaecptr oldpc = m68k_getpci();
	uae_s16 src = regs.irc;
	do_cycles_ce000_internal(2);
	if (cctrue(3)) {
		if (src & 1) {
			uaecptr addr = m68k_getpci() + (uae_s32)src + 2;
			exception3_read_prefetch(opcode, addr);
			return;
		}
		m68k_incpci((uae_s32)src + 2);
		int pcadjust = oldpc - m68k_getpci() + 2;
		get_word_ce000_prefetch(0);
		if(hardware_bus_error) {
			int pcoffset = 0;
			pcoffset += pcadjust;
			exception2_fetch_opcode(opcode, 0, pcoffset);
			return;
		}
		regs.ir = regs.irc;
		opcode = regs.ir;
		if(regs.t1) opcode |= 0x10000;
		ipl_fetch_next();
		get_word_ce000_prefetch(2);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 2, pcoffset);
			return;
		}
		return;
	}
	m68k_incpci(4);
	do_cycles_ce000_internal(2);
	get_word_ce000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, pcoffset);
		return;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	if(regs.t1) opcode |= 0x10000;
	ipl_fetch_next();
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 12 (2/0) */
/* 4 0,0 B */

/* BccQ.B #<data> (LS) */
void REGPARAM2 op_6301_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (uae_s32)(uae_s8)(real_opcode & 255);
	OpcodeFamily = 55;
	CurrentInstrCycles = 8;  
	uaecptr oldpc = m68k_getpci();
	uae_u32 src = srcreg;
	do_cycles_ce000_internal(2);
	if (cctrue(3)) {
		if (src & 1) {
			uaecptr addr = m68k_getpci() + (uae_s32)src + 2;
			exception3_read_prefetch(opcode, addr);
			return;
		}
		m68k_incpci((uae_s32)src + 2);
		int pcadjust = oldpc - m68k_getpci() + 2;
		get_word_ce000_prefetch(0);
		if(hardware_bus_error) {
			int pcoffset = 0;
			pcoffset += pcadjust;
			exception2_fetch_opcode(opcode, 0, pcoffset);
			return;
		}
		regs.ir = regs.irc;
		opcode = regs.ir;
		if(regs.t1) opcode |= 0x10000;
		ipl_fetch_next();
		get_word_ce000_prefetch(2);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 2, pcoffset);
			return;
		}
		return;
	}
	m68k_incpci(2);
	do_cycles_ce000_internal(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	if(regs.t1) opcode |= 0x10000;
	ipl_fetch_next();
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 8 (1/0) */
/* 2 0,0 B */

/* Bcc.L #<data>.L (LS) */
void REGPARAM2 op_63ff_14_ff(uae_u32 opcode)
{
	OpcodeFamily = 55;
	CurrentInstrCycles = 8;  
	uaecptr oldpc = m68k_getpci();
	do_cycles_ce000_internal(2);
	if (cctrue(3)) {
		exception3_read_prefetch(opcode, m68k_getpci() + 1);
		return;
	}
	m68k_incpci(2);
	do_cycles_ce000_internal(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	if(regs.t1) opcode |= 0x10000;
	ipl_fetch_next();
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 8 (1/0) */
/* 2 0,0   */

/* Bcc.W #<data>.W (CC) */
void REGPARAM2 op_6400_14_ff(uae_u32 opcode)
{
	OpcodeFamily = 55;
	CurrentInstrCycles = 12; 
	uaecptr oldpc = m68k_getpci();
	uae_s16 src = regs.irc;
	do_cycles_ce000_internal(2);
	if (cctrue(4)) {
		if (src & 1) {
			uaecptr addr = m68k_getpci() + (uae_s32)src + 2;
			exception3_read_prefetch(opcode, addr);
			return;
		}
		m68k_incpci((uae_s32)src + 2);
		int pcadjust = oldpc - m68k_getpci() + 2;
		get_word_ce000_prefetch(0);
		if(hardware_bus_error) {
			int pcoffset = 0;
			pcoffset += pcadjust;
			exception2_fetch_opcode(opcode, 0, pcoffset);
			return;
		}
		regs.ir = regs.irc;
		opcode = regs.ir;
		if(regs.t1) opcode |= 0x10000;
		ipl_fetch_next();
		get_word_ce000_prefetch(2);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 2, pcoffset);
			return;
		}
		return;
	}
	m68k_incpci(4);
	do_cycles_ce000_internal(2);
	get_word_ce000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, pcoffset);
		return;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	if(regs.t1) opcode |= 0x10000;
	ipl_fetch_next();
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 12 (2/0) */
/* 4 0,0 B */

/* BccQ.B #<data> (CC) */
void REGPARAM2 op_6401_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (uae_s32)(uae_s8)(real_opcode & 255);
	OpcodeFamily = 55;
	CurrentInstrCycles = 8;  
	uaecptr oldpc = m68k_getpci();
	uae_u32 src = srcreg;
	do_cycles_ce000_internal(2);
	if (cctrue(4)) {
		if (src & 1) {
			uaecptr addr = m68k_getpci() + (uae_s32)src + 2;
			exception3_read_prefetch(opcode, addr);
			return;
		}
		m68k_incpci((uae_s32)src + 2);
		int pcadjust = oldpc - m68k_getpci() + 2;
		get_word_ce000_prefetch(0);
		if(hardware_bus_error) {
			int pcoffset = 0;
			pcoffset += pcadjust;
			exception2_fetch_opcode(opcode, 0, pcoffset);
			return;
		}
		regs.ir = regs.irc;
		opcode = regs.ir;
		if(regs.t1) opcode |= 0x10000;
		ipl_fetch_next();
		get_word_ce000_prefetch(2);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 2, pcoffset);
			return;
		}
		return;
	}
	m68k_incpci(2);
	do_cycles_ce000_internal(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	if(regs.t1) opcode |= 0x10000;
	ipl_fetch_next();
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 8 (1/0) */
/* 2 0,0 B */

/* Bcc.L #<data>.L (CC) */
void REGPARAM2 op_64ff_14_ff(uae_u32 opcode)
{
	OpcodeFamily = 55;
	CurrentInstrCycles = 8;  
	uaecptr oldpc = m68k_getpci();
	do_cycles_ce000_internal(2);
	if (cctrue(4)) {
		exception3_read_prefetch(opcode, m68k_getpci() + 1);
		return;
	}
	m68k_incpci(2);
	do_cycles_ce000_internal(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	if(regs.t1) opcode |= 0x10000;
	ipl_fetch_next();
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 8 (1/0) */
/* 2 0,0   */

/* Bcc.W #<data>.W (CS) */
void REGPARAM2 op_6500_14_ff(uae_u32 opcode)
{
	OpcodeFamily = 55;
	CurrentInstrCycles = 12; 
	uaecptr oldpc = m68k_getpci();
	uae_s16 src = regs.irc;
	do_cycles_ce000_internal(2);
	if (cctrue(5)) {
		if (src & 1) {
			uaecptr addr = m68k_getpci() + (uae_s32)src + 2;
			exception3_read_prefetch(opcode, addr);
			return;
		}
		m68k_incpci((uae_s32)src + 2);
		int pcadjust = oldpc - m68k_getpci() + 2;
		get_word_ce000_prefetch(0);
		if(hardware_bus_error) {
			int pcoffset = 0;
			pcoffset += pcadjust;
			exception2_fetch_opcode(opcode, 0, pcoffset);
			return;
		}
		regs.ir = regs.irc;
		opcode = regs.ir;
		if(regs.t1) opcode |= 0x10000;
		ipl_fetch_next();
		get_word_ce000_prefetch(2);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 2, pcoffset);
			return;
		}
		return;
	}
	m68k_incpci(4);
	do_cycles_ce000_internal(2);
	get_word_ce000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, pcoffset);
		return;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	if(regs.t1) opcode |= 0x10000;
	ipl_fetch_next();
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 12 (2/0) */
/* 4 0,0 B */

/* BccQ.B #<data> (CS) */
void REGPARAM2 op_6501_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (uae_s32)(uae_s8)(real_opcode & 255);
	OpcodeFamily = 55;
	CurrentInstrCycles = 8;  
	uaecptr oldpc = m68k_getpci();
	uae_u32 src = srcreg;
	do_cycles_ce000_internal(2);
	if (cctrue(5)) {
		if (src & 1) {
			uaecptr addr = m68k_getpci() + (uae_s32)src + 2;
			exception3_read_prefetch(opcode, addr);
			return;
		}
		m68k_incpci((uae_s32)src + 2);
		int pcadjust = oldpc - m68k_getpci() + 2;
		get_word_ce000_prefetch(0);
		if(hardware_bus_error) {
			int pcoffset = 0;
			pcoffset += pcadjust;
			exception2_fetch_opcode(opcode, 0, pcoffset);
			return;
		}
		regs.ir = regs.irc;
		opcode = regs.ir;
		if(regs.t1) opcode |= 0x10000;
		ipl_fetch_next();
		get_word_ce000_prefetch(2);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 2, pcoffset);
			return;
		}
		return;
	}
	m68k_incpci(2);
	do_cycles_ce000_internal(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	if(regs.t1) opcode |= 0x10000;
	ipl_fetch_next();
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 8 (1/0) */
/* 2 0,0 B */

/* Bcc.L #<data>.L (CS) */
void REGPARAM2 op_65ff_14_ff(uae_u32 opcode)
{
	OpcodeFamily = 55;
	CurrentInstrCycles = 8;  
	uaecptr oldpc = m68k_getpci();
	do_cycles_ce000_internal(2);
	if (cctrue(5)) {
		exception3_read_prefetch(opcode, m68k_getpci() + 1);
		return;
	}
	m68k_incpci(2);
	do_cycles_ce000_internal(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	if(regs.t1) opcode |= 0x10000;
	ipl_fetch_next();
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 8 (1/0) */
/* 2 0,0   */

/* Bcc.W #<data>.W (NE) */
void REGPARAM2 op_6600_14_ff(uae_u32 opcode)
{
	OpcodeFamily = 55;
	CurrentInstrCycles = 12; 
	uaecptr oldpc = m68k_getpci();
	uae_s16 src = regs.irc;
	do_cycles_ce000_internal(2);
	if (cctrue(6)) {
		if (src & 1) {
			uaecptr addr = m68k_getpci() + (uae_s32)src + 2;
			exception3_read_prefetch(opcode, addr);
			return;
		}
		m68k_incpci((uae_s32)src + 2);
		int pcadjust = oldpc - m68k_getpci() + 2;
		get_word_ce000_prefetch(0);
		if(hardware_bus_error) {
			int pcoffset = 0;
			pcoffset += pcadjust;
			exception2_fetch_opcode(opcode, 0, pcoffset);
			return;
		}
		regs.ir = regs.irc;
		opcode = regs.ir;
		if(regs.t1) opcode |= 0x10000;
		ipl_fetch_next();
		get_word_ce000_prefetch(2);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 2, pcoffset);
			return;
		}
		return;
	}
	m68k_incpci(4);
	do_cycles_ce000_internal(2);
	get_word_ce000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, pcoffset);
		return;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	if(regs.t1) opcode |= 0x10000;
	ipl_fetch_next();
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 12 (2/0) */
/* 4 0,0 B */

/* BccQ.B #<data> (NE) */
void REGPARAM2 op_6601_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (uae_s32)(uae_s8)(real_opcode & 255);
	OpcodeFamily = 55;
	CurrentInstrCycles = 8;  
	uaecptr oldpc = m68k_getpci();
	uae_u32 src = srcreg;
	do_cycles_ce000_internal(2);
	if (cctrue(6)) {
		if (src & 1) {
			uaecptr addr = m68k_getpci() + (uae_s32)src + 2;
			exception3_read_prefetch(opcode, addr);
			return;
		}
		m68k_incpci((uae_s32)src + 2);
		int pcadjust = oldpc - m68k_getpci() + 2;
		get_word_ce000_prefetch(0);
		if(hardware_bus_error) {
			int pcoffset = 0;
			pcoffset += pcadjust;
			exception2_fetch_opcode(opcode, 0, pcoffset);
			return;
		}
		regs.ir = regs.irc;
		opcode = regs.ir;
		if(regs.t1) opcode |= 0x10000;
		ipl_fetch_next();
		get_word_ce000_prefetch(2);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 2, pcoffset);
			return;
		}
		return;
	}
	m68k_incpci(2);
	do_cycles_ce000_internal(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	if(regs.t1) opcode |= 0x10000;
	ipl_fetch_next();
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 8 (1/0) */
/* 2 0,0 B */

/* Bcc.L #<data>.L (NE) */
void REGPARAM2 op_66ff_14_ff(uae_u32 opcode)
{
	OpcodeFamily = 55;
	CurrentInstrCycles = 8;  
	uaecptr oldpc = m68k_getpci();
	do_cycles_ce000_internal(2);
	if (cctrue(6)) {
		exception3_read_prefetch(opcode, m68k_getpci() + 1);
		return;
	}
	m68k_incpci(2);
	do_cycles_ce000_internal(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	if(regs.t1) opcode |= 0x10000;
	ipl_fetch_next();
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 8 (1/0) */
/* 2 0,0   */

/* Bcc.W #<data>.W (EQ) */
void REGPARAM2 op_6700_14_ff(uae_u32 opcode)
{
	OpcodeFamily = 55;
	CurrentInstrCycles = 12; 
	uaecptr oldpc = m68k_getpci();
	uae_s16 src = regs.irc;
	do_cycles_ce000_internal(2);
	if (cctrue(7)) {
		if (src & 1) {
			uaecptr addr = m68k_getpci() + (uae_s32)src + 2;
			exception3_read_prefetch(opcode, addr);
			return;
		}
		m68k_incpci((uae_s32)src + 2);
		int pcadjust = oldpc - m68k_getpci() + 2;
		get_word_ce000_prefetch(0);
		if(hardware_bus_error) {
			int pcoffset = 0;
			pcoffset += pcadjust;
			exception2_fetch_opcode(opcode, 0, pcoffset);
			return;
		}
		regs.ir = regs.irc;
		opcode = regs.ir;
		if(regs.t1) opcode |= 0x10000;
		ipl_fetch_next();
		get_word_ce000_prefetch(2);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 2, pcoffset);
			return;
		}
		return;
	}
	m68k_incpci(4);
	do_cycles_ce000_internal(2);
	get_word_ce000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, pcoffset);
		return;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	if(regs.t1) opcode |= 0x10000;
	ipl_fetch_next();
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 12 (2/0) */
/* 4 0,0 B */

/* BccQ.B #<data> (EQ) */
void REGPARAM2 op_6701_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (uae_s32)(uae_s8)(real_opcode & 255);
	OpcodeFamily = 55;
	CurrentInstrCycles = 8;  
	uaecptr oldpc = m68k_getpci();
	uae_u32 src = srcreg;
	do_cycles_ce000_internal(2);
	if (cctrue(7)) {
		if (src & 1) {
			uaecptr addr = m68k_getpci() + (uae_s32)src + 2;
			exception3_read_prefetch(opcode, addr);
			return;
		}
		m68k_incpci((uae_s32)src + 2);
		int pcadjust = oldpc - m68k_getpci() + 2;
		get_word_ce000_prefetch(0);
		if(hardware_bus_error) {
			int pcoffset = 0;
			pcoffset += pcadjust;
			exception2_fetch_opcode(opcode, 0, pcoffset);
			return;
		}
		regs.ir = regs.irc;
		opcode = regs.ir;
		if(regs.t1) opcode |= 0x10000;
		ipl_fetch_next();
		get_word_ce000_prefetch(2);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 2, pcoffset);
			return;
		}
		return;
	}
	m68k_incpci(2);
	do_cycles_ce000_internal(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	if(regs.t1) opcode |= 0x10000;
	ipl_fetch_next();
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 8 (1/0) */
/* 2 0,0 B */

/* Bcc.L #<data>.L (EQ) */
void REGPARAM2 op_67ff_14_ff(uae_u32 opcode)
{
	OpcodeFamily = 55;
	CurrentInstrCycles = 8;  
	uaecptr oldpc = m68k_getpci();
	do_cycles_ce000_internal(2);
	if (cctrue(7)) {
		exception3_read_prefetch(opcode, m68k_getpci() + 1);
		return;
	}
	m68k_incpci(2);
	do_cycles_ce000_internal(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	if(regs.t1) opcode |= 0x10000;
	ipl_fetch_next();
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 8 (1/0) */
/* 2 0,0   */

/* Bcc.W #<data>.W (VC) */
void REGPARAM2 op_6800_14_ff(uae_u32 opcode)
{
	OpcodeFamily = 55;
	CurrentInstrCycles = 12; 
	uaecptr oldpc = m68k_getpci();
	uae_s16 src = regs.irc;
	do_cycles_ce000_internal(2);
	if (cctrue(8)) {
		if (src & 1) {
			uaecptr addr = m68k_getpci() + (uae_s32)src + 2;
			exception3_read_prefetch(opcode, addr);
			return;
		}
		m68k_incpci((uae_s32)src + 2);
		int pcadjust = oldpc - m68k_getpci() + 2;
		get_word_ce000_prefetch(0);
		if(hardware_bus_error) {
			int pcoffset = 0;
			pcoffset += pcadjust;
			exception2_fetch_opcode(opcode, 0, pcoffset);
			return;
		}
		regs.ir = regs.irc;
		opcode = regs.ir;
		if(regs.t1) opcode |= 0x10000;
		ipl_fetch_next();
		get_word_ce000_prefetch(2);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 2, pcoffset);
			return;
		}
		return;
	}
	m68k_incpci(4);
	do_cycles_ce000_internal(2);
	get_word_ce000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, pcoffset);
		return;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	if(regs.t1) opcode |= 0x10000;
	ipl_fetch_next();
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 12 (2/0) */
/* 4 0,0 B */

/* BccQ.B #<data> (VC) */
void REGPARAM2 op_6801_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (uae_s32)(uae_s8)(real_opcode & 255);
	OpcodeFamily = 55;
	CurrentInstrCycles = 8;  
	uaecptr oldpc = m68k_getpci();
	uae_u32 src = srcreg;
	do_cycles_ce000_internal(2);
	if (cctrue(8)) {
		if (src & 1) {
			uaecptr addr = m68k_getpci() + (uae_s32)src + 2;
			exception3_read_prefetch(opcode, addr);
			return;
		}
		m68k_incpci((uae_s32)src + 2);
		int pcadjust = oldpc - m68k_getpci() + 2;
		get_word_ce000_prefetch(0);
		if(hardware_bus_error) {
			int pcoffset = 0;
			pcoffset += pcadjust;
			exception2_fetch_opcode(opcode, 0, pcoffset);
			return;
		}
		regs.ir = regs.irc;
		opcode = regs.ir;
		if(regs.t1) opcode |= 0x10000;
		ipl_fetch_next();
		get_word_ce000_prefetch(2);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 2, pcoffset);
			return;
		}
		return;
	}
	m68k_incpci(2);
	do_cycles_ce000_internal(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	if(regs.t1) opcode |= 0x10000;
	ipl_fetch_next();
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 8 (1/0) */
/* 2 0,0 B */

/* Bcc.L #<data>.L (VC) */
void REGPARAM2 op_68ff_14_ff(uae_u32 opcode)
{
	OpcodeFamily = 55;
	CurrentInstrCycles = 8;  
	uaecptr oldpc = m68k_getpci();
	do_cycles_ce000_internal(2);
	if (cctrue(8)) {
		exception3_read_prefetch(opcode, m68k_getpci() + 1);
		return;
	}
	m68k_incpci(2);
	do_cycles_ce000_internal(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	if(regs.t1) opcode |= 0x10000;
	ipl_fetch_next();
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 8 (1/0) */
/* 2 0,0   */

/* Bcc.W #<data>.W (VS) */
void REGPARAM2 op_6900_14_ff(uae_u32 opcode)
{
	OpcodeFamily = 55;
	CurrentInstrCycles = 12; 
	uaecptr oldpc = m68k_getpci();
	uae_s16 src = regs.irc;
	do_cycles_ce000_internal(2);
	if (cctrue(9)) {
		if (src & 1) {
			uaecptr addr = m68k_getpci() + (uae_s32)src + 2;
			exception3_read_prefetch(opcode, addr);
			return;
		}
		m68k_incpci((uae_s32)src + 2);
		int pcadjust = oldpc - m68k_getpci() + 2;
		get_word_ce000_prefetch(0);
		if(hardware_bus_error) {
			int pcoffset = 0;
			pcoffset += pcadjust;
			exception2_fetch_opcode(opcode, 0, pcoffset);
			return;
		}
		regs.ir = regs.irc;
		opcode = regs.ir;
		if(regs.t1) opcode |= 0x10000;
		ipl_fetch_next();
		get_word_ce000_prefetch(2);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 2, pcoffset);
			return;
		}
		return;
	}
	m68k_incpci(4);
	do_cycles_ce000_internal(2);
	get_word_ce000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, pcoffset);
		return;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	if(regs.t1) opcode |= 0x10000;
	ipl_fetch_next();
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 12 (2/0) */
/* 4 0,0 B */

/* BccQ.B #<data> (VS) */
void REGPARAM2 op_6901_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (uae_s32)(uae_s8)(real_opcode & 255);
	OpcodeFamily = 55;
	CurrentInstrCycles = 8;  
	uaecptr oldpc = m68k_getpci();
	uae_u32 src = srcreg;
	do_cycles_ce000_internal(2);
	if (cctrue(9)) {
		if (src & 1) {
			uaecptr addr = m68k_getpci() + (uae_s32)src + 2;
			exception3_read_prefetch(opcode, addr);
			return;
		}
		m68k_incpci((uae_s32)src + 2);
		int pcadjust = oldpc - m68k_getpci() + 2;
		get_word_ce000_prefetch(0);
		if(hardware_bus_error) {
			int pcoffset = 0;
			pcoffset += pcadjust;
			exception2_fetch_opcode(opcode, 0, pcoffset);
			return;
		}
		regs.ir = regs.irc;
		opcode = regs.ir;
		if(regs.t1) opcode |= 0x10000;
		ipl_fetch_next();
		get_word_ce000_prefetch(2);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 2, pcoffset);
			return;
		}
		return;
	}
	m68k_incpci(2);
	do_cycles_ce000_internal(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	if(regs.t1) opcode |= 0x10000;
	ipl_fetch_next();
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 8 (1/0) */
/* 2 0,0 B */

/* Bcc.L #<data>.L (VS) */
void REGPARAM2 op_69ff_14_ff(uae_u32 opcode)
{
	OpcodeFamily = 55;
	CurrentInstrCycles = 8;  
	uaecptr oldpc = m68k_getpci();
	do_cycles_ce000_internal(2);
	if (cctrue(9)) {
		exception3_read_prefetch(opcode, m68k_getpci() + 1);
		return;
	}
	m68k_incpci(2);
	do_cycles_ce000_internal(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	if(regs.t1) opcode |= 0x10000;
	ipl_fetch_next();
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 8 (1/0) */
/* 2 0,0   */

/* Bcc.W #<data>.W (PL) */
void REGPARAM2 op_6a00_14_ff(uae_u32 opcode)
{
	OpcodeFamily = 55;
	CurrentInstrCycles = 12; 
	uaecptr oldpc = m68k_getpci();
	uae_s16 src = regs.irc;
	do_cycles_ce000_internal(2);
	if (cctrue(10)) {
		if (src & 1) {
			uaecptr addr = m68k_getpci() + (uae_s32)src + 2;
			exception3_read_prefetch(opcode, addr);
			return;
		}
		m68k_incpci((uae_s32)src + 2);
		int pcadjust = oldpc - m68k_getpci() + 2;
		get_word_ce000_prefetch(0);
		if(hardware_bus_error) {
			int pcoffset = 0;
			pcoffset += pcadjust;
			exception2_fetch_opcode(opcode, 0, pcoffset);
			return;
		}
		regs.ir = regs.irc;
		opcode = regs.ir;
		if(regs.t1) opcode |= 0x10000;
		ipl_fetch_next();
		get_word_ce000_prefetch(2);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 2, pcoffset);
			return;
		}
		return;
	}
	m68k_incpci(4);
	do_cycles_ce000_internal(2);
	get_word_ce000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, pcoffset);
		return;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	if(regs.t1) opcode |= 0x10000;
	ipl_fetch_next();
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 12 (2/0) */
/* 4 0,0 B */

/* BccQ.B #<data> (PL) */
void REGPARAM2 op_6a01_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (uae_s32)(uae_s8)(real_opcode & 255);
	OpcodeFamily = 55;
	CurrentInstrCycles = 8;  
	uaecptr oldpc = m68k_getpci();
	uae_u32 src = srcreg;
	do_cycles_ce000_internal(2);
	if (cctrue(10)) {
		if (src & 1) {
			uaecptr addr = m68k_getpci() + (uae_s32)src + 2;
			exception3_read_prefetch(opcode, addr);
			return;
		}
		m68k_incpci((uae_s32)src + 2);
		int pcadjust = oldpc - m68k_getpci() + 2;
		get_word_ce000_prefetch(0);
		if(hardware_bus_error) {
			int pcoffset = 0;
			pcoffset += pcadjust;
			exception2_fetch_opcode(opcode, 0, pcoffset);
			return;
		}
		regs.ir = regs.irc;
		opcode = regs.ir;
		if(regs.t1) opcode |= 0x10000;
		ipl_fetch_next();
		get_word_ce000_prefetch(2);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 2, pcoffset);
			return;
		}
		return;
	}
	m68k_incpci(2);
	do_cycles_ce000_internal(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	if(regs.t1) opcode |= 0x10000;
	ipl_fetch_next();
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 8 (1/0) */
/* 2 0,0 B */

/* Bcc.L #<data>.L (PL) */
void REGPARAM2 op_6aff_14_ff(uae_u32 opcode)
{
	OpcodeFamily = 55;
	CurrentInstrCycles = 8;  
	uaecptr oldpc = m68k_getpci();
	do_cycles_ce000_internal(2);
	if (cctrue(10)) {
		exception3_read_prefetch(opcode, m68k_getpci() + 1);
		return;
	}
	m68k_incpci(2);
	do_cycles_ce000_internal(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	if(regs.t1) opcode |= 0x10000;
	ipl_fetch_next();
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 8 (1/0) */
/* 2 0,0   */

/* Bcc.W #<data>.W (MI) */
void REGPARAM2 op_6b00_14_ff(uae_u32 opcode)
{
	OpcodeFamily = 55;
	CurrentInstrCycles = 12; 
	uaecptr oldpc = m68k_getpci();
	uae_s16 src = regs.irc;
	do_cycles_ce000_internal(2);
	if (cctrue(11)) {
		if (src & 1) {
			uaecptr addr = m68k_getpci() + (uae_s32)src + 2;
			exception3_read_prefetch(opcode, addr);
			return;
		}
		m68k_incpci((uae_s32)src + 2);
		int pcadjust = oldpc - m68k_getpci() + 2;
		get_word_ce000_prefetch(0);
		if(hardware_bus_error) {
			int pcoffset = 0;
			pcoffset += pcadjust;
			exception2_fetch_opcode(opcode, 0, pcoffset);
			return;
		}
		regs.ir = regs.irc;
		opcode = regs.ir;
		if(regs.t1) opcode |= 0x10000;
		ipl_fetch_next();
		get_word_ce000_prefetch(2);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 2, pcoffset);
			return;
		}
		return;
	}
	m68k_incpci(4);
	do_cycles_ce000_internal(2);
	get_word_ce000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, pcoffset);
		return;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	if(regs.t1) opcode |= 0x10000;
	ipl_fetch_next();
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 12 (2/0) */
/* 4 0,0 B */

/* BccQ.B #<data> (MI) */
void REGPARAM2 op_6b01_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (uae_s32)(uae_s8)(real_opcode & 255);
	OpcodeFamily = 55;
	CurrentInstrCycles = 8;  
	uaecptr oldpc = m68k_getpci();
	uae_u32 src = srcreg;
	do_cycles_ce000_internal(2);
	if (cctrue(11)) {
		if (src & 1) {
			uaecptr addr = m68k_getpci() + (uae_s32)src + 2;
			exception3_read_prefetch(opcode, addr);
			return;
		}
		m68k_incpci((uae_s32)src + 2);
		int pcadjust = oldpc - m68k_getpci() + 2;
		get_word_ce000_prefetch(0);
		if(hardware_bus_error) {
			int pcoffset = 0;
			pcoffset += pcadjust;
			exception2_fetch_opcode(opcode, 0, pcoffset);
			return;
		}
		regs.ir = regs.irc;
		opcode = regs.ir;
		if(regs.t1) opcode |= 0x10000;
		ipl_fetch_next();
		get_word_ce000_prefetch(2);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 2, pcoffset);
			return;
		}
		return;
	}
	m68k_incpci(2);
	do_cycles_ce000_internal(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	if(regs.t1) opcode |= 0x10000;
	ipl_fetch_next();
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 8 (1/0) */
/* 2 0,0 B */

/* Bcc.L #<data>.L (MI) */
void REGPARAM2 op_6bff_14_ff(uae_u32 opcode)
{
	OpcodeFamily = 55;
	CurrentInstrCycles = 8;  
	uaecptr oldpc = m68k_getpci();
	do_cycles_ce000_internal(2);
	if (cctrue(11)) {
		exception3_read_prefetch(opcode, m68k_getpci() + 1);
		return;
	}
	m68k_incpci(2);
	do_cycles_ce000_internal(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	if(regs.t1) opcode |= 0x10000;
	ipl_fetch_next();
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 8 (1/0) */
/* 2 0,0   */

/* Bcc.W #<data>.W (GE) */
void REGPARAM2 op_6c00_14_ff(uae_u32 opcode)
{
	OpcodeFamily = 55;
	CurrentInstrCycles = 12; 
	uaecptr oldpc = m68k_getpci();
	uae_s16 src = regs.irc;
	do_cycles_ce000_internal(2);
	if (cctrue(12)) {
		if (src & 1) {
			uaecptr addr = m68k_getpci() + (uae_s32)src + 2;
			exception3_read_prefetch(opcode, addr);
			return;
		}
		m68k_incpci((uae_s32)src + 2);
		int pcadjust = oldpc - m68k_getpci() + 2;
		get_word_ce000_prefetch(0);
		if(hardware_bus_error) {
			int pcoffset = 0;
			pcoffset += pcadjust;
			exception2_fetch_opcode(opcode, 0, pcoffset);
			return;
		}
		regs.ir = regs.irc;
		opcode = regs.ir;
		if(regs.t1) opcode |= 0x10000;
		ipl_fetch_next();
		get_word_ce000_prefetch(2);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 2, pcoffset);
			return;
		}
		return;
	}
	m68k_incpci(4);
	do_cycles_ce000_internal(2);
	get_word_ce000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, pcoffset);
		return;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	if(regs.t1) opcode |= 0x10000;
	ipl_fetch_next();
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 12 (2/0) */
/* 4 0,0 B */

/* BccQ.B #<data> (GE) */
void REGPARAM2 op_6c01_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (uae_s32)(uae_s8)(real_opcode & 255);
	OpcodeFamily = 55;
	CurrentInstrCycles = 8;  
	uaecptr oldpc = m68k_getpci();
	uae_u32 src = srcreg;
	do_cycles_ce000_internal(2);
	if (cctrue(12)) {
		if (src & 1) {
			uaecptr addr = m68k_getpci() + (uae_s32)src + 2;
			exception3_read_prefetch(opcode, addr);
			return;
		}
		m68k_incpci((uae_s32)src + 2);
		int pcadjust = oldpc - m68k_getpci() + 2;
		get_word_ce000_prefetch(0);
		if(hardware_bus_error) {
			int pcoffset = 0;
			pcoffset += pcadjust;
			exception2_fetch_opcode(opcode, 0, pcoffset);
			return;
		}
		regs.ir = regs.irc;
		opcode = regs.ir;
		if(regs.t1) opcode |= 0x10000;
		ipl_fetch_next();
		get_word_ce000_prefetch(2);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 2, pcoffset);
			return;
		}
		return;
	}
	m68k_incpci(2);
	do_cycles_ce000_internal(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	if(regs.t1) opcode |= 0x10000;
	ipl_fetch_next();
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 8 (1/0) */
/* 2 0,0 B */

/* Bcc.L #<data>.L (GE) */
void REGPARAM2 op_6cff_14_ff(uae_u32 opcode)
{
	OpcodeFamily = 55;
	CurrentInstrCycles = 8;  
	uaecptr oldpc = m68k_getpci();
	do_cycles_ce000_internal(2);
	if (cctrue(12)) {
		exception3_read_prefetch(opcode, m68k_getpci() + 1);
		return;
	}
	m68k_incpci(2);
	do_cycles_ce000_internal(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	if(regs.t1) opcode |= 0x10000;
	ipl_fetch_next();
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 8 (1/0) */
/* 2 0,0   */

/* Bcc.W #<data>.W (LT) */
void REGPARAM2 op_6d00_14_ff(uae_u32 opcode)
{
	OpcodeFamily = 55;
	CurrentInstrCycles = 12; 
	uaecptr oldpc = m68k_getpci();
	uae_s16 src = regs.irc;
	do_cycles_ce000_internal(2);
	if (cctrue(13)) {
		if (src & 1) {
			uaecptr addr = m68k_getpci() + (uae_s32)src + 2;
			exception3_read_prefetch(opcode, addr);
			return;
		}
		m68k_incpci((uae_s32)src + 2);
		int pcadjust = oldpc - m68k_getpci() + 2;
		get_word_ce000_prefetch(0);
		if(hardware_bus_error) {
			int pcoffset = 0;
			pcoffset += pcadjust;
			exception2_fetch_opcode(opcode, 0, pcoffset);
			return;
		}
		regs.ir = regs.irc;
		opcode = regs.ir;
		if(regs.t1) opcode |= 0x10000;
		ipl_fetch_next();
		get_word_ce000_prefetch(2);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 2, pcoffset);
			return;
		}
		return;
	}
	m68k_incpci(4);
	do_cycles_ce000_internal(2);
	get_word_ce000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, pcoffset);
		return;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	if(regs.t1) opcode |= 0x10000;
	ipl_fetch_next();
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 12 (2/0) */
/* 4 0,0 B */

/* BccQ.B #<data> (LT) */
void REGPARAM2 op_6d01_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (uae_s32)(uae_s8)(real_opcode & 255);
	OpcodeFamily = 55;
	CurrentInstrCycles = 8;  
	uaecptr oldpc = m68k_getpci();
	uae_u32 src = srcreg;
	do_cycles_ce000_internal(2);
	if (cctrue(13)) {
		if (src & 1) {
			uaecptr addr = m68k_getpci() + (uae_s32)src + 2;
			exception3_read_prefetch(opcode, addr);
			return;
		}
		m68k_incpci((uae_s32)src + 2);
		int pcadjust = oldpc - m68k_getpci() + 2;
		get_word_ce000_prefetch(0);
		if(hardware_bus_error) {
			int pcoffset = 0;
			pcoffset += pcadjust;
			exception2_fetch_opcode(opcode, 0, pcoffset);
			return;
		}
		regs.ir = regs.irc;
		opcode = regs.ir;
		if(regs.t1) opcode |= 0x10000;
		ipl_fetch_next();
		get_word_ce000_prefetch(2);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 2, pcoffset);
			return;
		}
		return;
	}
	m68k_incpci(2);
	do_cycles_ce000_internal(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	if(regs.t1) opcode |= 0x10000;
	ipl_fetch_next();
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 8 (1/0) */
/* 2 0,0 B */

/* Bcc.L #<data>.L (LT) */
void REGPARAM2 op_6dff_14_ff(uae_u32 opcode)
{
	OpcodeFamily = 55;
	CurrentInstrCycles = 8;  
	uaecptr oldpc = m68k_getpci();
	do_cycles_ce000_internal(2);
	if (cctrue(13)) {
		exception3_read_prefetch(opcode, m68k_getpci() + 1);
		return;
	}
	m68k_incpci(2);
	do_cycles_ce000_internal(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	if(regs.t1) opcode |= 0x10000;
	ipl_fetch_next();
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 8 (1/0) */
/* 2 0,0   */

/* Bcc.W #<data>.W (GT) */
void REGPARAM2 op_6e00_14_ff(uae_u32 opcode)
{
	OpcodeFamily = 55;
	CurrentInstrCycles = 12; 
	uaecptr oldpc = m68k_getpci();
	uae_s16 src = regs.irc;
	do_cycles_ce000_internal(2);
	if (cctrue(14)) {
		if (src & 1) {
			uaecptr addr = m68k_getpci() + (uae_s32)src + 2;
			exception3_read_prefetch(opcode, addr);
			return;
		}
		m68k_incpci((uae_s32)src + 2);
		int pcadjust = oldpc - m68k_getpci() + 2;
		get_word_ce000_prefetch(0);
		if(hardware_bus_error) {
			int pcoffset = 0;
			pcoffset += pcadjust;
			exception2_fetch_opcode(opcode, 0, pcoffset);
			return;
		}
		regs.ir = regs.irc;
		opcode = regs.ir;
		if(regs.t1) opcode |= 0x10000;
		ipl_fetch_next();
		get_word_ce000_prefetch(2);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 2, pcoffset);
			return;
		}
		return;
	}
	m68k_incpci(4);
	do_cycles_ce000_internal(2);
	get_word_ce000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, pcoffset);
		return;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	if(regs.t1) opcode |= 0x10000;
	ipl_fetch_next();
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 12 (2/0) */
/* 4 0,0 B */

/* BccQ.B #<data> (GT) */
void REGPARAM2 op_6e01_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (uae_s32)(uae_s8)(real_opcode & 255);
	OpcodeFamily = 55;
	CurrentInstrCycles = 8;  
	uaecptr oldpc = m68k_getpci();
	uae_u32 src = srcreg;
	do_cycles_ce000_internal(2);
	if (cctrue(14)) {
		if (src & 1) {
			uaecptr addr = m68k_getpci() + (uae_s32)src + 2;
			exception3_read_prefetch(opcode, addr);
			return;
		}
		m68k_incpci((uae_s32)src + 2);
		int pcadjust = oldpc - m68k_getpci() + 2;
		get_word_ce000_prefetch(0);
		if(hardware_bus_error) {
			int pcoffset = 0;
			pcoffset += pcadjust;
			exception2_fetch_opcode(opcode, 0, pcoffset);
			return;
		}
		regs.ir = regs.irc;
		opcode = regs.ir;
		if(regs.t1) opcode |= 0x10000;
		ipl_fetch_next();
		get_word_ce000_prefetch(2);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 2, pcoffset);
			return;
		}
		return;
	}
	m68k_incpci(2);
	do_cycles_ce000_internal(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	if(regs.t1) opcode |= 0x10000;
	ipl_fetch_next();
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 8 (1/0) */
/* 2 0,0 B */

/* Bcc.L #<data>.L (GT) */
void REGPARAM2 op_6eff_14_ff(uae_u32 opcode)
{
	OpcodeFamily = 55;
	CurrentInstrCycles = 8;  
	uaecptr oldpc = m68k_getpci();
	do_cycles_ce000_internal(2);
	if (cctrue(14)) {
		exception3_read_prefetch(opcode, m68k_getpci() + 1);
		return;
	}
	m68k_incpci(2);
	do_cycles_ce000_internal(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	if(regs.t1) opcode |= 0x10000;
	ipl_fetch_next();
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 8 (1/0) */
/* 2 0,0   */

/* Bcc.W #<data>.W (LE) */
void REGPARAM2 op_6f00_14_ff(uae_u32 opcode)
{
	OpcodeFamily = 55;
	CurrentInstrCycles = 12; 
	uaecptr oldpc = m68k_getpci();
	uae_s16 src = regs.irc;
	do_cycles_ce000_internal(2);
	if (cctrue(15)) {
		if (src & 1) {
			uaecptr addr = m68k_getpci() + (uae_s32)src + 2;
			exception3_read_prefetch(opcode, addr);
			return;
		}
		m68k_incpci((uae_s32)src + 2);
		int pcadjust = oldpc - m68k_getpci() + 2;
		get_word_ce000_prefetch(0);
		if(hardware_bus_error) {
			int pcoffset = 0;
			pcoffset += pcadjust;
			exception2_fetch_opcode(opcode, 0, pcoffset);
			return;
		}
		regs.ir = regs.irc;
		opcode = regs.ir;
		if(regs.t1) opcode |= 0x10000;
		ipl_fetch_next();
		get_word_ce000_prefetch(2);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 2, pcoffset);
			return;
		}
		return;
	}
	m68k_incpci(4);
	do_cycles_ce000_internal(2);
	get_word_ce000_prefetch(0);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 0, pcoffset);
		return;
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	if(regs.t1) opcode |= 0x10000;
	ipl_fetch_next();
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 12 (2/0) */
/* 4 0,0 B */

/* BccQ.B #<data> (LE) */
void REGPARAM2 op_6f01_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (uae_s32)(uae_s8)(real_opcode & 255);
	OpcodeFamily = 55;
	CurrentInstrCycles = 8;  
	uaecptr oldpc = m68k_getpci();
	uae_u32 src = srcreg;
	do_cycles_ce000_internal(2);
	if (cctrue(15)) {
		if (src & 1) {
			uaecptr addr = m68k_getpci() + (uae_s32)src + 2;
			exception3_read_prefetch(opcode, addr);
			return;
		}
		m68k_incpci((uae_s32)src + 2);
		int pcadjust = oldpc - m68k_getpci() + 2;
		get_word_ce000_prefetch(0);
		if(hardware_bus_error) {
			int pcoffset = 0;
			pcoffset += pcadjust;
			exception2_fetch_opcode(opcode, 0, pcoffset);
			return;
		}
		regs.ir = regs.irc;
		opcode = regs.ir;
		if(regs.t1) opcode |= 0x10000;
		ipl_fetch_next();
		get_word_ce000_prefetch(2);
		if(hardware_bus_error) {
			int pcoffset = 0;
			exception2_fetch_opcode(opcode, 2, pcoffset);
			return;
		}
		return;
	}
	m68k_incpci(2);
	do_cycles_ce000_internal(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	if(regs.t1) opcode |= 0x10000;
	ipl_fetch_next();
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 8 (1/0) */
/* 2 0,0 B */

/* Bcc.L #<data>.L (LE) */
void REGPARAM2 op_6fff_14_ff(uae_u32 opcode)
{
	OpcodeFamily = 55;
	CurrentInstrCycles = 8;  
	uaecptr oldpc = m68k_getpci();
	do_cycles_ce000_internal(2);
	if (cctrue(15)) {
		exception3_read_prefetch(opcode, m68k_getpci() + 1);
		return;
	}
	m68k_incpci(2);
	do_cycles_ce000_internal(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	if(regs.t1) opcode |= 0x10000;
	ipl_fetch_next();
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 8 (1/0) */
/* 2 0,0   */

/* MOVEQ.L #<data>,Dn */
void REGPARAM2 op_7000_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (uae_s32)(uae_s8)(real_opcode & 255);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 30;
	CurrentInstrCycles = 4;  
	uae_u32 src = srcreg;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	m68k_dreg(regs, dstreg) = (src);
	m68k_incpci(2);
	regs.ir = regs.irc;
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(2);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 2, pcoffset);
		return;
	}
	return;
}
/* 4 (1/0) */
/* 2 0,0   */

/* OR.B Dn,Dn */
void REGPARAM2 op_8000_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 4;  
	uae_s8 src = m68k_dreg(regs, srcreg);
	uae_s8 dst = m68k_dreg(regs, dstreg);
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 4 (1/0) */
/* 2 0,0   */

/* OR.B (An),Dn */
void REGPARAM2 op_8010_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 8;  
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	uae_s8 dst = m68k_dreg(regs, dstreg);
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 8 (2/0) */
/* 2 0,0   */

/* OR.B (An)+,Dn */
void REGPARAM2 op_8018_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 8;  
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
	uae_s8 dst = m68k_dreg(regs, dstreg);
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 8 (2/0) */
/* 2 0,0   */

/* OR.B -(An),Dn */
void REGPARAM2 op_8020_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 10; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
	do_cycles_ce000_internal(2);
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	m68k_areg(regs, srcreg) = srca;
	uae_s8 dst = m68k_dreg(regs, dstreg);
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 10 (2/0) */
/* 2 0,0   */

/* OR.B (d16,An),Dn */
void REGPARAM2 op_8028_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	uae_s8 dst = m68k_dreg(regs, dstreg);
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 12 (3/0) */
/* 4 0,0   */

/* OR.B (d8,An,Xn),Dn */
void REGPARAM2 op_8030_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	do_cycles_ce000_internal(2);
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	uae_s8 dst = m68k_dreg(regs, dstreg);
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 14 (3/0) */
/* 4 4,0   */

/* OR.B (xxx).W,Dn */
void REGPARAM2 op_8038_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	uae_s8 dst = m68k_dreg(regs, dstreg);
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 12 (3/0) */
/* 4 0,0   */

/* OR.B (xxx).L,Dn */
void REGPARAM2 op_8039_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	srca |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	uae_s8 dst = m68k_dreg(regs, dstreg);
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 16 (4/0) */
/* 6 0,0   */

/* OR.B (d16,PC),Dn */
void REGPARAM2 op_803a_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_getpci() + 2;
	srca += (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 2);
		return;
	}
	uae_s8 dst = m68k_dreg(regs, dstreg);
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 12 (3/0) */
/* 4 0,0   */

/* OR.B (d8,PC,Xn),Dn */
void REGPARAM2 op_803b_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	uaecptr tmppc = m68k_getpci() + 2;
	do_cycles_ce000_internal(2);
	srca = get_disp_ea_000(tmppc, get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 2);
		return;
	}
	uae_s8 dst = m68k_dreg(regs, dstreg);
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 14 (3/0) */
/* 4 4,0   */

/* OR.B #<data>.B,Dn */
void REGPARAM2 op_803c_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 8;  
	uae_s8 src = (uae_u8)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uae_s8 dst = m68k_dreg(regs, dstreg);
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 8 (2/0) */
/* 4 0,0   */

/* OR.W Dn,Dn */
void REGPARAM2 op_8040_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 4;  
	uae_s16 src = m68k_dreg(regs, srcreg);
	uae_s16 dst = m68k_dreg(regs, dstreg);
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 4 (1/0) */
/* 2 0,0   */

/* OR.W (An),Dn */
void REGPARAM2 op_8050_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 8;  
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 8 (2/0) */
/* 2 0,0   */

/* OR.W (An)+,Dn */
void REGPARAM2 op_8058_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 8;  
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) += 2 + 0;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	m68k_areg(regs, srcreg) += 2;
	uae_s16 dst = m68k_dreg(regs, dstreg);
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 8 (2/0) */
/* 2 0,0   */

/* OR.W -(An),Dn */
void REGPARAM2 op_8060_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 10; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - 2;
	do_cycles_ce000_internal(2);
	if (srca & 1) {
		m68k_incpci(4);
		m68k_areg(regs, srcreg) = srca;
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	m68k_areg(regs, srcreg) = srca;
	uae_s16 dst = m68k_dreg(regs, dstreg);
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 10 (2/0) */
/* 2 0,0   */

/* OR.W (d16,An),Dn */
void REGPARAM2 op_8068_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 12 (3/0) */
/* 4 0,0   */

/* OR.W (d8,An,Xn),Dn */
void REGPARAM2 op_8070_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	do_cycles_ce000_internal(2);
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 14 (3/0) */
/* 4 4,0   */

/* OR.W (xxx).W,Dn */
void REGPARAM2 op_8078_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	if (srca & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 12 (3/0) */
/* 4 0,0   */

/* OR.W (xxx).L,Dn */
void REGPARAM2 op_8079_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	srca |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	if (srca & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 16 (4/0) */
/* 6 0,0   */

/* OR.W (d16,PC),Dn */
void REGPARAM2 op_807a_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_getpci() + 2;
	srca += (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 2);
		return;
	}
	ipl_fetch_now();
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 12 (3/0) */
/* 4 0,0   */

/* OR.W (d8,PC,Xn),Dn */
void REGPARAM2 op_807b_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	uaecptr tmppc = m68k_getpci() + 2;
	do_cycles_ce000_internal(2);
	srca = get_disp_ea_000(tmppc, get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 2);
		return;
	}
	ipl_fetch_now();
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 14 (3/0) */
/* 4 4,0   */

/* OR.W #<data>.W,Dn */
void REGPARAM2 op_807c_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 8;  
	uae_s16 src = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 8 (2/0) */
/* 4 0,0   */

/* OR.L Dn,Dn */
void REGPARAM2 op_8080_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 8;  
	uae_s32 src = m68k_dreg(regs, srcreg);
	uae_s32 dst = m68k_dreg(regs, dstreg);
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		dreg_68000_long_replace_low(dstreg, src);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	do_cycles_ce000_internal(4);
	m68k_dreg(regs, dstreg) = (src);
	m68k_incpci(2);
	return;
}
/* 8 (1/0) */
/* 2 0,0   */

/* OR.L (An),Dn */
void REGPARAM2 op_8090_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		dreg_68000_long_replace_low(dstreg, src);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	do_cycles_ce000_internal(2);
	m68k_dreg(regs, dstreg) = (src);
	m68k_incpci(2);
	return;
}
/* 14 (3/0) */
/* 2 0,0   */

/* OR.L (An)+,Dn */
void REGPARAM2 op_8098_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	m68k_areg(regs, srcreg) += 4;
	uae_s32 dst = m68k_dreg(regs, dstreg);
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		dreg_68000_long_replace_low(dstreg, src);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	do_cycles_ce000_internal(2);
	m68k_dreg(regs, dstreg) = (src);
	m68k_incpci(2);
	return;
}
/* 14 (3/0) */
/* 2 0,0   */

/* OR.L -(An),Dn */
void REGPARAM2 op_80a0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - 4;
	do_cycles_ce000_internal(2);
	if (srca & 1) {
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	m68k_areg(regs, srcreg) = srca;
	uae_s32 dst = m68k_dreg(regs, dstreg);
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		dreg_68000_long_replace_low(dstreg, src);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	do_cycles_ce000_internal(2);
	m68k_dreg(regs, dstreg) = (src);
	m68k_incpci(2);
	return;
}
/* 16 (3/0) */
/* 2 0,0   */

/* OR.L (d16,An),Dn */
void REGPARAM2 op_80a8_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		dreg_68000_long_replace_low(dstreg, src);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	do_cycles_ce000_internal(2);
	m68k_dreg(regs, dstreg) = (src);
	m68k_incpci(4);
	return;
}
/* 18 (4/0) */
/* 4 0,0   */

/* OR.L (d8,An,Xn),Dn */
void REGPARAM2 op_80b0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	do_cycles_ce000_internal(2);
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		dreg_68000_long_replace_low(dstreg, src);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	do_cycles_ce000_internal(2);
	m68k_dreg(regs, dstreg) = (src);
	m68k_incpci(4);
	return;
}
/* 20 (4/0) */
/* 4 4,0   */

/* OR.L (xxx).W,Dn */
void REGPARAM2 op_80b8_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	if (srca & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		dreg_68000_long_replace_low(dstreg, src);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	do_cycles_ce000_internal(2);
	m68k_dreg(regs, dstreg) = (src);
	m68k_incpci(4);
	return;
}
/* 18 (4/0) */
/* 4 0,0   */

/* OR.L (xxx).L,Dn */
void REGPARAM2 op_80b9_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 22; 
	uaecptr srca;
	srca = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	srca |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	if (srca & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		dreg_68000_long_replace_low(dstreg, src);
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	opcode = regs.ir;
	do_cycles_ce000_internal(2);
	m68k_dreg(regs, dstreg) = (src);
	m68k_incpci(6);
	return;
}
/* 22 (5/0) */
/* 6 0,0   */

/* OR.L (d16,PC),Dn */
void REGPARAM2 op_80ba_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	srca = m68k_getpci() + 2;
	srca += (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 2);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return;
	}
	ipl_fetch_now();
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 2);
		return;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		dreg_68000_long_replace_low(dstreg, src);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	do_cycles_ce000_internal(2);
	m68k_dreg(regs, dstreg) = (src);
	m68k_incpci(4);
	return;
}
/* 18 (4/0) */
/* 4 0,0   */

/* OR.L (d8,PC,Xn),Dn */
void REGPARAM2 op_80bb_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	uaecptr tmppc = m68k_getpci() + 2;
	do_cycles_ce000_internal(2);
	srca = get_disp_ea_000(tmppc, get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 2);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return;
	}
	ipl_fetch_now();
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 2);
		return;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		dreg_68000_long_replace_low(dstreg, src);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	do_cycles_ce000_internal(2);
	m68k_dreg(regs, dstreg) = (src);
	m68k_incpci(4);
	return;
}
/* 20 (4/0) */
/* 4 4,0   */

/* OR.L #<data>.L,Dn */
void REGPARAM2 op_80bc_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 16; 
	uae_s32 src;
	src = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	src |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		dreg_68000_long_replace_low(dstreg, src);
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	opcode = regs.ir;
	do_cycles_ce000_internal(4);
	m68k_dreg(regs, dstreg) = (src);
	m68k_incpci(6);
	return;
}
/* 16 (3/0) */
/* 6 0,0   */

/* DIVU.W Dn,Dn */
void REGPARAM2 op_80c0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 60;
	CurrentInstrCycles = 4;  
	uae_s16 src = m68k_dreg(regs, srcreg);
	uae_s32 dst = m68k_dreg(regs, dstreg);
	if (src == 0) {
		divbyzero_special(0, dst);
		m68k_incpci(2);
		do_cycles_ce000_internal(4);
		Exception_cpu(5);
		return;
	}
	uae_u32 newv = (uae_u32)dst / (uae_u32)(uae_u16)src;
	uae_u32 rem = (uae_u32)dst % (uae_u32)(uae_u16)src;
	int cycles = getDivu68kCycles((uae_u32)dst, (uae_u16)src);
	do_cycles_ce000_internal(cycles);
	if (newv > 0xffff) {
		setdivuflags((uae_u32)dst, (uae_u16)src);
	} else {
		CLEAR_CZNV();
		SET_ZFLG(((uae_s16)(newv)) == 0);
		SET_NFLG(((uae_s16)(newv)) < 0);
		newv = (newv & 0xffff) | ((uae_u32)rem << 16);
		m68k_dreg(regs, dstreg) = (newv);
	}
	ipl_fetch_next();
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 4+ (1/0) */
/* 2 0,0   */

/* DIVU.W (An),Dn */
void REGPARAM2 op_80d0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 60;
	CurrentInstrCycles = 8;  
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	if (src == 0) {
		divbyzero_special(0, dst);
		m68k_incpci(2);
		do_cycles_ce000_internal(4);
		Exception_cpu(5);
		return;
	}
	uae_u32 newv = (uae_u32)dst / (uae_u32)(uae_u16)src;
	uae_u32 rem = (uae_u32)dst % (uae_u32)(uae_u16)src;
	int cycles = getDivu68kCycles((uae_u32)dst, (uae_u16)src);
	do_cycles_ce000_internal(cycles);
	if (newv > 0xffff) {
		setdivuflags((uae_u32)dst, (uae_u16)src);
	} else {
		CLEAR_CZNV();
		SET_ZFLG(((uae_s16)(newv)) == 0);
		SET_NFLG(((uae_s16)(newv)) < 0);
		newv = (newv & 0xffff) | ((uae_u32)rem << 16);
		m68k_dreg(regs, dstreg) = (newv);
	}
	ipl_fetch_next();
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 8+ (2/0) */
/* 2 0,0   */

/* DIVU.W (An)+,Dn */
void REGPARAM2 op_80d8_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 60;
	CurrentInstrCycles = 8;  
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) += 2 + 0;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	m68k_areg(regs, srcreg) += 2;
	uae_s32 dst = m68k_dreg(regs, dstreg);
	if (src == 0) {
		divbyzero_special(0, dst);
		m68k_incpci(2);
		do_cycles_ce000_internal(4);
		Exception_cpu(5);
		return;
	}
	uae_u32 newv = (uae_u32)dst / (uae_u32)(uae_u16)src;
	uae_u32 rem = (uae_u32)dst % (uae_u32)(uae_u16)src;
	int cycles = getDivu68kCycles((uae_u32)dst, (uae_u16)src);
	do_cycles_ce000_internal(cycles);
	if (newv > 0xffff) {
		setdivuflags((uae_u32)dst, (uae_u16)src);
	} else {
		CLEAR_CZNV();
		SET_ZFLG(((uae_s16)(newv)) == 0);
		SET_NFLG(((uae_s16)(newv)) < 0);
		newv = (newv & 0xffff) | ((uae_u32)rem << 16);
		m68k_dreg(regs, dstreg) = (newv);
	}
	ipl_fetch_next();
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 8+ (2/0) */
/* 2 0,0   */

/* DIVU.W -(An),Dn */
void REGPARAM2 op_80e0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 60;
	CurrentInstrCycles = 10; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - 2;
	do_cycles_ce000_internal(2);
	if (srca & 1) {
		m68k_incpci(4);
		m68k_areg(regs, srcreg) = srca;
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	m68k_areg(regs, srcreg) = srca;
	uae_s32 dst = m68k_dreg(regs, dstreg);
	if (src == 0) {
		divbyzero_special(0, dst);
		m68k_incpci(2);
		do_cycles_ce000_internal(4);
		Exception_cpu(5);
		return;
	}
	uae_u32 newv = (uae_u32)dst / (uae_u32)(uae_u16)src;
	uae_u32 rem = (uae_u32)dst % (uae_u32)(uae_u16)src;
	int cycles = getDivu68kCycles((uae_u32)dst, (uae_u16)src);
	do_cycles_ce000_internal(cycles);
	if (newv > 0xffff) {
		setdivuflags((uae_u32)dst, (uae_u16)src);
	} else {
		CLEAR_CZNV();
		SET_ZFLG(((uae_s16)(newv)) == 0);
		SET_NFLG(((uae_s16)(newv)) < 0);
		newv = (newv & 0xffff) | ((uae_u32)rem << 16);
		m68k_dreg(regs, dstreg) = (newv);
	}
	ipl_fetch_next();
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 10+ (2/0) */
/* 2 0,0   */

/* DIVU.W (d16,An),Dn */
void REGPARAM2 op_80e8_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 60;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	if (src == 0) {
		divbyzero_special(0, dst);
		m68k_incpci(4);
		do_cycles_ce000_internal(4);
		Exception_cpu(5);
		return;
	}
	uae_u32 newv = (uae_u32)dst / (uae_u32)(uae_u16)src;
	uae_u32 rem = (uae_u32)dst % (uae_u32)(uae_u16)src;
	int cycles = getDivu68kCycles((uae_u32)dst, (uae_u16)src);
	do_cycles_ce000_internal(cycles);
	if (newv > 0xffff) {
		setdivuflags((uae_u32)dst, (uae_u16)src);
	} else {
		CLEAR_CZNV();
		SET_ZFLG(((uae_s16)(newv)) == 0);
		SET_NFLG(((uae_s16)(newv)) < 0);
		newv = (newv & 0xffff) | ((uae_u32)rem << 16);
		m68k_dreg(regs, dstreg) = (newv);
	}
	ipl_fetch_next();
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 12+ (3/0) */
/* 4 0,0   */

/* DIVU.W (d8,An,Xn),Dn */
void REGPARAM2 op_80f0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 60;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	do_cycles_ce000_internal(2);
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	if (src == 0) {
		divbyzero_special(0, dst);
		m68k_incpci(4);
		do_cycles_ce000_internal(4);
		Exception_cpu(5);
		return;
	}
	uae_u32 newv = (uae_u32)dst / (uae_u32)(uae_u16)src;
	uae_u32 rem = (uae_u32)dst % (uae_u32)(uae_u16)src;
	int cycles = getDivu68kCycles((uae_u32)dst, (uae_u16)src);
	do_cycles_ce000_internal(cycles);
	if (newv > 0xffff) {
		setdivuflags((uae_u32)dst, (uae_u16)src);
	} else {
		CLEAR_CZNV();
		SET_ZFLG(((uae_s16)(newv)) == 0);
		SET_NFLG(((uae_s16)(newv)) < 0);
		newv = (newv & 0xffff) | ((uae_u32)rem << 16);
		m68k_dreg(regs, dstreg) = (newv);
	}
	ipl_fetch_next();
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 14+ (3/0) */
/* 4 4,0   */

/* DIVU.W (xxx).W,Dn */
void REGPARAM2 op_80f8_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 60;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	if (srca & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	if (src == 0) {
		divbyzero_special(0, dst);
		m68k_incpci(4);
		do_cycles_ce000_internal(4);
		Exception_cpu(5);
		return;
	}
	uae_u32 newv = (uae_u32)dst / (uae_u32)(uae_u16)src;
	uae_u32 rem = (uae_u32)dst % (uae_u32)(uae_u16)src;
	int cycles = getDivu68kCycles((uae_u32)dst, (uae_u16)src);
	do_cycles_ce000_internal(cycles);
	if (newv > 0xffff) {
		setdivuflags((uae_u32)dst, (uae_u16)src);
	} else {
		CLEAR_CZNV();
		SET_ZFLG(((uae_s16)(newv)) == 0);
		SET_NFLG(((uae_s16)(newv)) < 0);
		newv = (newv & 0xffff) | ((uae_u32)rem << 16);
		m68k_dreg(regs, dstreg) = (newv);
	}
	ipl_fetch_next();
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 12+ (3/0) */
/* 4 0,0   */

/* DIVU.W (xxx).L,Dn */
void REGPARAM2 op_80f9_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 60;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	srca |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	if (srca & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	if (src == 0) {
		divbyzero_special(0, dst);
		m68k_incpci(6);
		do_cycles_ce000_internal(4);
		Exception_cpu(5);
		return;
	}
	uae_u32 newv = (uae_u32)dst / (uae_u32)(uae_u16)src;
	uae_u32 rem = (uae_u32)dst % (uae_u32)(uae_u16)src;
	int cycles = getDivu68kCycles((uae_u32)dst, (uae_u16)src);
	do_cycles_ce000_internal(cycles);
	if (newv > 0xffff) {
		setdivuflags((uae_u32)dst, (uae_u16)src);
	} else {
		CLEAR_CZNV();
		SET_ZFLG(((uae_s16)(newv)) == 0);
		SET_NFLG(((uae_s16)(newv)) < 0);
		newv = (newv & 0xffff) | ((uae_u32)rem << 16);
		m68k_dreg(regs, dstreg) = (newv);
	}
	ipl_fetch_next();
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 16+ (4/0) */
/* 6 0,0   */

/* DIVU.W (d16,PC),Dn */
void REGPARAM2 op_80fa_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 60;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_getpci() + 2;
	srca += (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 2);
		return;
	}
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	if (src == 0) {
		divbyzero_special(0, dst);
		m68k_incpci(4);
		do_cycles_ce000_internal(4);
		Exception_cpu(5);
		return;
	}
	uae_u32 newv = (uae_u32)dst / (uae_u32)(uae_u16)src;
	uae_u32 rem = (uae_u32)dst % (uae_u32)(uae_u16)src;
	int cycles = getDivu68kCycles((uae_u32)dst, (uae_u16)src);
	do_cycles_ce000_internal(cycles);
	if (newv > 0xffff) {
		setdivuflags((uae_u32)dst, (uae_u16)src);
	} else {
		CLEAR_CZNV();
		SET_ZFLG(((uae_s16)(newv)) == 0);
		SET_NFLG(((uae_s16)(newv)) < 0);
		newv = (newv & 0xffff) | ((uae_u32)rem << 16);
		m68k_dreg(regs, dstreg) = (newv);
	}
	ipl_fetch_next();
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 12+ (3/0) */
/* 4 0,0   */

/* DIVU.W (d8,PC,Xn),Dn */
void REGPARAM2 op_80fb_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 60;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	uaecptr tmppc = m68k_getpci() + 2;
	do_cycles_ce000_internal(2);
	srca = get_disp_ea_000(tmppc, get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 2);
		return;
	}
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	if (src == 0) {
		divbyzero_special(0, dst);
		m68k_incpci(4);
		do_cycles_ce000_internal(4);
		Exception_cpu(5);
		return;
	}
	uae_u32 newv = (uae_u32)dst / (uae_u32)(uae_u16)src;
	uae_u32 rem = (uae_u32)dst % (uae_u32)(uae_u16)src;
	int cycles = getDivu68kCycles((uae_u32)dst, (uae_u16)src);
	do_cycles_ce000_internal(cycles);
	if (newv > 0xffff) {
		setdivuflags((uae_u32)dst, (uae_u16)src);
	} else {
		CLEAR_CZNV();
		SET_ZFLG(((uae_s16)(newv)) == 0);
		SET_NFLG(((uae_s16)(newv)) < 0);
		newv = (newv & 0xffff) | ((uae_u32)rem << 16);
		m68k_dreg(regs, dstreg) = (newv);
	}
	ipl_fetch_next();
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 14+ (3/0) */
/* 4 4,0   */

/* DIVU.W #<data>.W,Dn */
void REGPARAM2 op_80fc_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 60;
	CurrentInstrCycles = 8;  
	uae_s16 src = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	if (src == 0) {
		divbyzero_special(0, dst);
		m68k_incpci(4);
		do_cycles_ce000_internal(4);
		Exception_cpu(5);
		return;
	}
	uae_u32 newv = (uae_u32)dst / (uae_u32)(uae_u16)src;
	uae_u32 rem = (uae_u32)dst % (uae_u32)(uae_u16)src;
	int cycles = getDivu68kCycles((uae_u32)dst, (uae_u16)src);
	do_cycles_ce000_internal(cycles);
	if (newv > 0xffff) {
		setdivuflags((uae_u32)dst, (uae_u16)src);
	} else {
		CLEAR_CZNV();
		SET_ZFLG(((uae_s16)(newv)) == 0);
		SET_NFLG(((uae_s16)(newv)) < 0);
		newv = (newv & 0xffff) | ((uae_u32)rem << 16);
		m68k_dreg(regs, dstreg) = (newv);
	}
	ipl_fetch_next();
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 8+ (2/0) */
/* 4 0,0   */

/* SBCD.B Dn,Dn */
void REGPARAM2 op_8100_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 10;
	CurrentInstrCycles = 6;  
	uae_s8 src = m68k_dreg(regs, srcreg);
	uae_s8 dst = m68k_dreg(regs, dstreg);
	uae_u16 newv_lo = (dst & 0xF) - (src & 0xF) - (GET_XFLG() ? 1 : 0);
	uae_u16 newv_hi = (dst & 0xF0) - (src & 0xF0);
	uae_u16 newv, tmp_newv;
	int bcd = 0;
	newv = tmp_newv = newv_hi + newv_lo;
if (newv_lo & 0xF0) { newv -= 6; bcd = 6; };
if ((((dst & 0xFF) - (src & 0xFF) - (GET_XFLG() ? 1 : 0)) & 0x100) > 0xFF) { newv -= 0x60; }
	SET_CFLG((((dst & 0xFF) - (src & 0xFF) - bcd - (GET_XFLG() ? 1 : 0)) & 0x300) > 0xFF);
	COPY_CARRY();
	SET_ZFLG(GET_ZFLG() & (((uae_s8)(newv)) == 0));
	SET_NFLG(((uae_s8)(newv)) < 0);
	SET_VFLG((tmp_newv & 0x80) != 0 && (newv & 0x80) == 0);
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	do_cycles_ce000_internal(2);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
	m68k_incpci(2);
	return;
}
/* 6 (1/0) */
/* 2 0,0   */

/* SBCD.B -(An),-(An) */
void REGPARAM2 op_8108_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 10;
	CurrentInstrCycles = 18; 
	do_cycles_ce000_internal(2);
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	m68k_areg(regs, srcreg) = srca;
	ipl_fetch_next_pre();
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, dstreg) = dsta;
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	m68k_areg(regs, dstreg) = dsta;
	uae_u16 newv_lo = (dst & 0xF) - (src & 0xF) - (GET_XFLG() ? 1 : 0);
	uae_u16 newv_hi = (dst & 0xF0) - (src & 0xF0);
	uae_u16 newv, tmp_newv;
	int bcd = 0;
	newv = tmp_newv = newv_hi + newv_lo;
if (newv_lo & 0xF0) { newv -= 6; bcd = 6; };
if ((((dst & 0xFF) - (src & 0xFF) - (GET_XFLG() ? 1 : 0)) & 0x100) > 0xFF) { newv -= 0x60; }
	SET_CFLG((((dst & 0xFF) - (src & 0xFF) - bcd - (GET_XFLG() ? 1 : 0)) & 0x300) > 0xFF);
	COPY_CARRY();
	SET_ZFLG(GET_ZFLG() & (((uae_s8)(newv)) == 0));
	SET_NFLG(((uae_s8)(newv)) < 0);
	SET_VFLG((tmp_newv & 0x80) != 0 && (newv & 0x80) == 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_byte(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, newv, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 18 (3/1) */
/* 2 0,0   */

/* OR.B Dn,(An) */
void REGPARAM2 op_8110_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 12; 
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_byte(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 12 (2/1) */
/* 2 0,0   */

/* OR.B Dn,(An)+ */
void REGPARAM2 op_8118_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 12; 
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_byte(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 12 (2/1) */
/* 2 0,0   */

/* OR.B Dn,-(An) */
void REGPARAM2 op_8120_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 14; 
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
	do_cycles_ce000_internal(2);
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, dstreg) = dsta;
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	m68k_areg(regs, dstreg) = dsta;
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_byte(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 14 (2/1) */
/* 2 0,0   */

/* OR.B Dn,(d16,An) */
void REGPARAM2 op_8128_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 16; 
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_byte(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* OR.B Dn,(d8,An,Xn) */
void REGPARAM2 op_8130_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 18; 
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	do_cycles_ce000_internal(2);
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_byte(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 18 (3/1) */
/* 4 4,0   */

/* OR.B Dn,(xxx).W */
void REGPARAM2 op_8138_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	OpcodeFamily = 1;
	CurrentInstrCycles = 16; 
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_byte(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* OR.B Dn,(xxx).L */
void REGPARAM2 op_8139_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	OpcodeFamily = 1;
	CurrentInstrCycles = 20; 
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	dsta |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_byte(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 20 (4/1) */
/* 6 0,0   */

/* OR.W Dn,(An) */
void REGPARAM2 op_8150_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 12; 
	uae_s16 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	if (dsta & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dsta, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 dst = x_get_word(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_word(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 12 (2/1) */
/* 2 0,0   */

/* OR.W Dn,(An)+ */
void REGPARAM2 op_8158_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 12; 
	uae_s16 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	if (dsta & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dsta, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 dst = x_get_word(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, dstreg) += 2 + 0;
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	m68k_areg(regs, dstreg) += 2;
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_word(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 12 (2/1) */
/* 2 0,0   */

/* OR.W Dn,-(An) */
void REGPARAM2 op_8160_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 14; 
	uae_s16 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - 2;
	do_cycles_ce000_internal(2);
	if (dsta & 1) {
		m68k_incpci(4);
		m68k_areg(regs, dstreg) = dsta;
		exception3_read_access(opcode, dsta, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 dst = x_get_word(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, dstreg) = dsta;
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	m68k_areg(regs, dstreg) = dsta;
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_word(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 14 (2/1) */
/* 2 0,0   */

/* OR.W Dn,(d16,An) */
void REGPARAM2 op_8168_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 16; 
	uae_s16 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dsta, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 dst = x_get_word(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_word(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* OR.W Dn,(d8,An,Xn) */
void REGPARAM2 op_8170_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 18; 
	uae_s16 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	do_cycles_ce000_internal(2);
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dsta, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 dst = x_get_word(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_word(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 18 (3/1) */
/* 4 4,0   */

/* OR.W Dn,(xxx).W */
void REGPARAM2 op_8178_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	OpcodeFamily = 1;
	CurrentInstrCycles = 16; 
	uae_s16 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, dsta, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 dst = x_get_word(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_word(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* OR.W Dn,(xxx).L */
void REGPARAM2 op_8179_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	OpcodeFamily = 1;
	CurrentInstrCycles = 20; 
	uae_s16 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	dsta |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, dsta, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 dst = x_get_word(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_word(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 20 (4/1) */
/* 6 0,0   */

/* OR.L Dn,(An) */
void REGPARAM2 op_8190_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 20; 
	uae_s32 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	if (dsta & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dsta, 2, 1);
		return;
	}
	uae_s32 dst = x_get_word(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	dst |= x_get_word(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return;
	}
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	x_put_word(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return;
	}
	x_put_word(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 20 (3/2) */
/* 2 0,0   */

/* OR.L Dn,(An)+ */
void REGPARAM2 op_8198_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 20; 
	uae_s32 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	if (dsta & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dsta, 2, 1);
		return;
	}
	uae_s32 dst = x_get_word(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	dst |= x_get_word(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return;
	}
	m68k_areg(regs, dstreg) += 4;
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	x_put_word(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return;
	}
	x_put_word(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 20 (3/2) */
/* 2 0,0   */

/* OR.L Dn,-(An) */
void REGPARAM2 op_81a0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 22; 
	uae_s32 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - 4;
	do_cycles_ce000_internal(2);
	if (dsta & 1) {
		m68k_incpci(2);
		m68k_areg(regs, dstreg) = dsta;
		exception3_read_access(opcode, dsta, 2, 1);
		return;
	}
	uae_s32 dst = x_get_word(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, dstreg) = dsta;
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	dst |= x_get_word(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, dstreg) = dsta;
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return;
	}
	m68k_areg(regs, dstreg) = dsta;
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	x_put_word(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return;
	}
	x_put_word(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 22 (3/2) */
/* 2 0,0   */

/* OR.L Dn,(d16,An) */
void REGPARAM2 op_81a8_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 24; 
	uae_s32 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dsta, 2, 1);
		return;
	}
	uae_s32 dst = x_get_word(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	dst |= x_get_word(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return;
	}
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	x_put_word(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return;
	}
	x_put_word(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 24 (4/2) */
/* 4 0,0   */

/* OR.L Dn,(d8,An,Xn) */
void REGPARAM2 op_81b0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 1;
	CurrentInstrCycles = 26; 
	uae_s32 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	do_cycles_ce000_internal(2);
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dsta, 2, 1);
		return;
	}
	uae_s32 dst = x_get_word(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	dst |= x_get_word(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return;
	}
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	x_put_word(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return;
	}
	x_put_word(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 26 (4/2) */
/* 4 4,0   */

/* OR.L Dn,(xxx).W */
void REGPARAM2 op_81b8_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	OpcodeFamily = 1;
	CurrentInstrCycles = 24; 
	uae_s32 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, dsta, 2, 1);
		return;
	}
	uae_s32 dst = x_get_word(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	dst |= x_get_word(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return;
	}
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	x_put_word(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return;
	}
	x_put_word(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 24 (4/2) */
/* 4 0,0   */

/* OR.L Dn,(xxx).L */
void REGPARAM2 op_81b9_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	OpcodeFamily = 1;
	CurrentInstrCycles = 28; 
	uae_s32 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	dsta |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, dsta, 2, 1);
		return;
	}
	uae_s32 dst = x_get_word(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	dst |= x_get_word(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return;
	}
	src |= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	x_put_word(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return;
	}
	x_put_word(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 28 (5/2) */
/* 6 0,0   */

/* DIVS.W Dn,Dn */
void REGPARAM2 op_81c0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 61;
	CurrentInstrCycles = 4;  
	uae_s16 src = m68k_dreg(regs, srcreg);
	uae_s32 dst = m68k_dreg(regs, dstreg);
	if (src == 0) {
		divbyzero_special(1, dst);
		m68k_incpci(2);
		do_cycles_ce000_internal(4);
		Exception_cpu(5);
		return;
	}
	int extra = 0;
	int cycles = getDivs68kCycles((uae_s32)dst, (uae_s16)src, &extra);
	if (extra) {
		cycles -= 2;
		do_cycles_ce000_internal(cycles);
		ipl_fetch_next();
		cycles = 2;
		do_cycles_ce000_internal(cycles);
	} else {
		do_cycles_ce000_internal(cycles);
		ipl_fetch_next();
	}
	if (dst == 0x80000000 && src == -1) {
		setdivsflags((uae_s32)dst, (uae_s16)src);
	} else {
		uae_s32 newv = (uae_s32)dst / (uae_s32)(uae_s16)src;
		uae_u16 rem = (uae_s32)dst % (uae_s32)(uae_s16)src;
		if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) {
			setdivsflags((uae_s32)dst, (uae_s16)src);
		} else {
			if (((uae_s16)rem < 0) != ((uae_s32)dst < 0)) rem = -rem;
			CLEAR_CZNV();
			SET_ZFLG(((uae_s16)(newv)) == 0);
			SET_NFLG(((uae_s16)(newv)) < 0);
			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
			m68k_dreg(regs, dstreg) = (newv);
		}
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 4+ (1/0) */
/* 2 0,0   */

/* DIVS.W (An),Dn */
void REGPARAM2 op_81d0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 61;
	CurrentInstrCycles = 8;  
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	if (src == 0) {
		divbyzero_special(1, dst);
		m68k_incpci(2);
		do_cycles_ce000_internal(4);
		Exception_cpu(5);
		return;
	}
	int extra = 0;
	int cycles = getDivs68kCycles((uae_s32)dst, (uae_s16)src, &extra);
	if (extra) {
		cycles -= 2;
		do_cycles_ce000_internal(cycles);
		ipl_fetch_next();
		cycles = 2;
		do_cycles_ce000_internal(cycles);
	} else {
		do_cycles_ce000_internal(cycles);
		ipl_fetch_next();
	}
	if (dst == 0x80000000 && src == -1) {
		setdivsflags((uae_s32)dst, (uae_s16)src);
	} else {
		uae_s32 newv = (uae_s32)dst / (uae_s32)(uae_s16)src;
		uae_u16 rem = (uae_s32)dst % (uae_s32)(uae_s16)src;
		if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) {
			setdivsflags((uae_s32)dst, (uae_s16)src);
		} else {
			if (((uae_s16)rem < 0) != ((uae_s32)dst < 0)) rem = -rem;
			CLEAR_CZNV();
			SET_ZFLG(((uae_s16)(newv)) == 0);
			SET_NFLG(((uae_s16)(newv)) < 0);
			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
			m68k_dreg(regs, dstreg) = (newv);
		}
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 8+ (2/0) */
/* 2 0,0   */

/* DIVS.W (An)+,Dn */
void REGPARAM2 op_81d8_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 61;
	CurrentInstrCycles = 8;  
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) += 2 + 0;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	m68k_areg(regs, srcreg) += 2;
	uae_s32 dst = m68k_dreg(regs, dstreg);
	if (src == 0) {
		divbyzero_special(1, dst);
		m68k_incpci(2);
		do_cycles_ce000_internal(4);
		Exception_cpu(5);
		return;
	}
	int extra = 0;
	int cycles = getDivs68kCycles((uae_s32)dst, (uae_s16)src, &extra);
	if (extra) {
		cycles -= 2;
		do_cycles_ce000_internal(cycles);
		ipl_fetch_next();
		cycles = 2;
		do_cycles_ce000_internal(cycles);
	} else {
		do_cycles_ce000_internal(cycles);
		ipl_fetch_next();
	}
	if (dst == 0x80000000 && src == -1) {
		setdivsflags((uae_s32)dst, (uae_s16)src);
	} else {
		uae_s32 newv = (uae_s32)dst / (uae_s32)(uae_s16)src;
		uae_u16 rem = (uae_s32)dst % (uae_s32)(uae_s16)src;
		if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) {
			setdivsflags((uae_s32)dst, (uae_s16)src);
		} else {
			if (((uae_s16)rem < 0) != ((uae_s32)dst < 0)) rem = -rem;
			CLEAR_CZNV();
			SET_ZFLG(((uae_s16)(newv)) == 0);
			SET_NFLG(((uae_s16)(newv)) < 0);
			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
			m68k_dreg(regs, dstreg) = (newv);
		}
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 8+ (2/0) */
/* 2 0,0   */

/* DIVS.W -(An),Dn */
void REGPARAM2 op_81e0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 61;
	CurrentInstrCycles = 10; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - 2;
	do_cycles_ce000_internal(2);
	if (srca & 1) {
		m68k_incpci(4);
		m68k_areg(regs, srcreg) = srca;
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	m68k_areg(regs, srcreg) = srca;
	uae_s32 dst = m68k_dreg(regs, dstreg);
	if (src == 0) {
		divbyzero_special(1, dst);
		m68k_incpci(2);
		do_cycles_ce000_internal(4);
		Exception_cpu(5);
		return;
	}
	int extra = 0;
	int cycles = getDivs68kCycles((uae_s32)dst, (uae_s16)src, &extra);
	if (extra) {
		cycles -= 2;
		do_cycles_ce000_internal(cycles);
		ipl_fetch_next();
		cycles = 2;
		do_cycles_ce000_internal(cycles);
	} else {
		do_cycles_ce000_internal(cycles);
		ipl_fetch_next();
	}
	if (dst == 0x80000000 && src == -1) {
		setdivsflags((uae_s32)dst, (uae_s16)src);
	} else {
		uae_s32 newv = (uae_s32)dst / (uae_s32)(uae_s16)src;
		uae_u16 rem = (uae_s32)dst % (uae_s32)(uae_s16)src;
		if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) {
			setdivsflags((uae_s32)dst, (uae_s16)src);
		} else {
			if (((uae_s16)rem < 0) != ((uae_s32)dst < 0)) rem = -rem;
			CLEAR_CZNV();
			SET_ZFLG(((uae_s16)(newv)) == 0);
			SET_NFLG(((uae_s16)(newv)) < 0);
			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
			m68k_dreg(regs, dstreg) = (newv);
		}
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 10+ (2/0) */
/* 2 0,0   */

/* DIVS.W (d16,An),Dn */
void REGPARAM2 op_81e8_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 61;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	if (src == 0) {
		divbyzero_special(1, dst);
		m68k_incpci(4);
		do_cycles_ce000_internal(4);
		Exception_cpu(5);
		return;
	}
	int extra = 0;
	int cycles = getDivs68kCycles((uae_s32)dst, (uae_s16)src, &extra);
	if (extra) {
		cycles -= 2;
		do_cycles_ce000_internal(cycles);
		ipl_fetch_next();
		cycles = 2;
		do_cycles_ce000_internal(cycles);
	} else {
		do_cycles_ce000_internal(cycles);
		ipl_fetch_next();
	}
	if (dst == 0x80000000 && src == -1) {
		setdivsflags((uae_s32)dst, (uae_s16)src);
	} else {
		uae_s32 newv = (uae_s32)dst / (uae_s32)(uae_s16)src;
		uae_u16 rem = (uae_s32)dst % (uae_s32)(uae_s16)src;
		if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) {
			setdivsflags((uae_s32)dst, (uae_s16)src);
		} else {
			if (((uae_s16)rem < 0) != ((uae_s32)dst < 0)) rem = -rem;
			CLEAR_CZNV();
			SET_ZFLG(((uae_s16)(newv)) == 0);
			SET_NFLG(((uae_s16)(newv)) < 0);
			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
			m68k_dreg(regs, dstreg) = (newv);
		}
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 12+ (3/0) */
/* 4 0,0   */

/* DIVS.W (d8,An,Xn),Dn */
void REGPARAM2 op_81f0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 61;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	do_cycles_ce000_internal(2);
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	if (src == 0) {
		divbyzero_special(1, dst);
		m68k_incpci(4);
		do_cycles_ce000_internal(4);
		Exception_cpu(5);
		return;
	}
	int extra = 0;
	int cycles = getDivs68kCycles((uae_s32)dst, (uae_s16)src, &extra);
	if (extra) {
		cycles -= 2;
		do_cycles_ce000_internal(cycles);
		ipl_fetch_next();
		cycles = 2;
		do_cycles_ce000_internal(cycles);
	} else {
		do_cycles_ce000_internal(cycles);
		ipl_fetch_next();
	}
	if (dst == 0x80000000 && src == -1) {
		setdivsflags((uae_s32)dst, (uae_s16)src);
	} else {
		uae_s32 newv = (uae_s32)dst / (uae_s32)(uae_s16)src;
		uae_u16 rem = (uae_s32)dst % (uae_s32)(uae_s16)src;
		if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) {
			setdivsflags((uae_s32)dst, (uae_s16)src);
		} else {
			if (((uae_s16)rem < 0) != ((uae_s32)dst < 0)) rem = -rem;
			CLEAR_CZNV();
			SET_ZFLG(((uae_s16)(newv)) == 0);
			SET_NFLG(((uae_s16)(newv)) < 0);
			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
			m68k_dreg(regs, dstreg) = (newv);
		}
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 14+ (3/0) */
/* 4 4,0   */

/* DIVS.W (xxx).W,Dn */
void REGPARAM2 op_81f8_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 61;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	if (srca & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	if (src == 0) {
		divbyzero_special(1, dst);
		m68k_incpci(4);
		do_cycles_ce000_internal(4);
		Exception_cpu(5);
		return;
	}
	int extra = 0;
	int cycles = getDivs68kCycles((uae_s32)dst, (uae_s16)src, &extra);
	if (extra) {
		cycles -= 2;
		do_cycles_ce000_internal(cycles);
		ipl_fetch_next();
		cycles = 2;
		do_cycles_ce000_internal(cycles);
	} else {
		do_cycles_ce000_internal(cycles);
		ipl_fetch_next();
	}
	if (dst == 0x80000000 && src == -1) {
		setdivsflags((uae_s32)dst, (uae_s16)src);
	} else {
		uae_s32 newv = (uae_s32)dst / (uae_s32)(uae_s16)src;
		uae_u16 rem = (uae_s32)dst % (uae_s32)(uae_s16)src;
		if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) {
			setdivsflags((uae_s32)dst, (uae_s16)src);
		} else {
			if (((uae_s16)rem < 0) != ((uae_s32)dst < 0)) rem = -rem;
			CLEAR_CZNV();
			SET_ZFLG(((uae_s16)(newv)) == 0);
			SET_NFLG(((uae_s16)(newv)) < 0);
			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
			m68k_dreg(regs, dstreg) = (newv);
		}
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 12+ (3/0) */
/* 4 0,0   */

/* DIVS.W (xxx).L,Dn */
void REGPARAM2 op_81f9_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 61;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	srca |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	if (srca & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	if (src == 0) {
		divbyzero_special(1, dst);
		m68k_incpci(6);
		do_cycles_ce000_internal(4);
		Exception_cpu(5);
		return;
	}
	int extra = 0;
	int cycles = getDivs68kCycles((uae_s32)dst, (uae_s16)src, &extra);
	if (extra) {
		cycles -= 2;
		do_cycles_ce000_internal(cycles);
		ipl_fetch_next();
		cycles = 2;
		do_cycles_ce000_internal(cycles);
	} else {
		do_cycles_ce000_internal(cycles);
		ipl_fetch_next();
	}
	if (dst == 0x80000000 && src == -1) {
		setdivsflags((uae_s32)dst, (uae_s16)src);
	} else {
		uae_s32 newv = (uae_s32)dst / (uae_s32)(uae_s16)src;
		uae_u16 rem = (uae_s32)dst % (uae_s32)(uae_s16)src;
		if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) {
			setdivsflags((uae_s32)dst, (uae_s16)src);
		} else {
			if (((uae_s16)rem < 0) != ((uae_s32)dst < 0)) rem = -rem;
			CLEAR_CZNV();
			SET_ZFLG(((uae_s16)(newv)) == 0);
			SET_NFLG(((uae_s16)(newv)) < 0);
			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
			m68k_dreg(regs, dstreg) = (newv);
		}
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 16+ (4/0) */
/* 6 0,0   */

/* DIVS.W (d16,PC),Dn */
void REGPARAM2 op_81fa_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 61;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_getpci() + 2;
	srca += (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 2);
		return;
	}
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	if (src == 0) {
		divbyzero_special(1, dst);
		m68k_incpci(4);
		do_cycles_ce000_internal(4);
		Exception_cpu(5);
		return;
	}
	int extra = 0;
	int cycles = getDivs68kCycles((uae_s32)dst, (uae_s16)src, &extra);
	if (extra) {
		cycles -= 2;
		do_cycles_ce000_internal(cycles);
		ipl_fetch_next();
		cycles = 2;
		do_cycles_ce000_internal(cycles);
	} else {
		do_cycles_ce000_internal(cycles);
		ipl_fetch_next();
	}
	if (dst == 0x80000000 && src == -1) {
		setdivsflags((uae_s32)dst, (uae_s16)src);
	} else {
		uae_s32 newv = (uae_s32)dst / (uae_s32)(uae_s16)src;
		uae_u16 rem = (uae_s32)dst % (uae_s32)(uae_s16)src;
		if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) {
			setdivsflags((uae_s32)dst, (uae_s16)src);
		} else {
			if (((uae_s16)rem < 0) != ((uae_s32)dst < 0)) rem = -rem;
			CLEAR_CZNV();
			SET_ZFLG(((uae_s16)(newv)) == 0);
			SET_NFLG(((uae_s16)(newv)) < 0);
			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
			m68k_dreg(regs, dstreg) = (newv);
		}
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 12+ (3/0) */
/* 4 0,0   */

/* DIVS.W (d8,PC,Xn),Dn */
void REGPARAM2 op_81fb_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 61;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	uaecptr tmppc = m68k_getpci() + 2;
	do_cycles_ce000_internal(2);
	srca = get_disp_ea_000(tmppc, get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 2);
		return;
	}
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	if (src == 0) {
		divbyzero_special(1, dst);
		m68k_incpci(4);
		do_cycles_ce000_internal(4);
		Exception_cpu(5);
		return;
	}
	int extra = 0;
	int cycles = getDivs68kCycles((uae_s32)dst, (uae_s16)src, &extra);
	if (extra) {
		cycles -= 2;
		do_cycles_ce000_internal(cycles);
		ipl_fetch_next();
		cycles = 2;
		do_cycles_ce000_internal(cycles);
	} else {
		do_cycles_ce000_internal(cycles);
		ipl_fetch_next();
	}
	if (dst == 0x80000000 && src == -1) {
		setdivsflags((uae_s32)dst, (uae_s16)src);
	} else {
		uae_s32 newv = (uae_s32)dst / (uae_s32)(uae_s16)src;
		uae_u16 rem = (uae_s32)dst % (uae_s32)(uae_s16)src;
		if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) {
			setdivsflags((uae_s32)dst, (uae_s16)src);
		} else {
			if (((uae_s16)rem < 0) != ((uae_s32)dst < 0)) rem = -rem;
			CLEAR_CZNV();
			SET_ZFLG(((uae_s16)(newv)) == 0);
			SET_NFLG(((uae_s16)(newv)) < 0);
			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
			m68k_dreg(regs, dstreg) = (newv);
		}
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 14+ (3/0) */
/* 4 4,0   */

/* DIVS.W #<data>.W,Dn */
void REGPARAM2 op_81fc_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 61;
	CurrentInstrCycles = 8;  
	uae_s16 src = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	if (src == 0) {
		divbyzero_special(1, dst);
		m68k_incpci(4);
		do_cycles_ce000_internal(4);
		Exception_cpu(5);
		return;
	}
	int extra = 0;
	int cycles = getDivs68kCycles((uae_s32)dst, (uae_s16)src, &extra);
	if (extra) {
		cycles -= 2;
		do_cycles_ce000_internal(cycles);
		ipl_fetch_next();
		cycles = 2;
		do_cycles_ce000_internal(cycles);
	} else {
		do_cycles_ce000_internal(cycles);
		ipl_fetch_next();
	}
	if (dst == 0x80000000 && src == -1) {
		setdivsflags((uae_s32)dst, (uae_s16)src);
	} else {
		uae_s32 newv = (uae_s32)dst / (uae_s32)(uae_s16)src;
		uae_u16 rem = (uae_s32)dst % (uae_s32)(uae_s16)src;
		if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) {
			setdivsflags((uae_s32)dst, (uae_s16)src);
		} else {
			if (((uae_s16)rem < 0) != ((uae_s32)dst < 0)) rem = -rem;
			CLEAR_CZNV();
			SET_ZFLG(((uae_s16)(newv)) == 0);
			SET_NFLG(((uae_s16)(newv)) < 0);
			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
			m68k_dreg(regs, dstreg) = (newv);
		}
	}
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 8+ (2/0) */
/* 4 0,0   */

/* SUB.B Dn,Dn */
void REGPARAM2 op_9000_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 4;  
	uae_s8 src = m68k_dreg(regs, srcreg);
	uae_s8 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 4 (1/0) */
/* 2 0,0   */

/* SUB.B (An),Dn */
void REGPARAM2 op_9010_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 8;  
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	uae_s8 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 8 (2/0) */
/* 2 0,0   */

/* SUB.B (An)+,Dn */
void REGPARAM2 op_9018_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 8;  
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
	uae_s8 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 8 (2/0) */
/* 2 0,0   */

/* SUB.B -(An),Dn */
void REGPARAM2 op_9020_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 10; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
	do_cycles_ce000_internal(2);
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	m68k_areg(regs, srcreg) = srca;
	uae_s8 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 10 (2/0) */
/* 2 0,0   */

/* SUB.B (d16,An),Dn */
void REGPARAM2 op_9028_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	uae_s8 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 12 (3/0) */
/* 4 0,0   */

/* SUB.B (d8,An,Xn),Dn */
void REGPARAM2 op_9030_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	do_cycles_ce000_internal(2);
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	uae_s8 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 14 (3/0) */
/* 4 4,0   */

/* SUB.B (xxx).W,Dn */
void REGPARAM2 op_9038_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	uae_s8 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 12 (3/0) */
/* 4 0,0   */

/* SUB.B (xxx).L,Dn */
void REGPARAM2 op_9039_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	srca |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	uae_s8 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 16 (4/0) */
/* 6 0,0   */

/* SUB.B (d16,PC),Dn */
void REGPARAM2 op_903a_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_getpci() + 2;
	srca += (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 2);
		return;
	}
	uae_s8 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 12 (3/0) */
/* 4 0,0   */

/* SUB.B (d8,PC,Xn),Dn */
void REGPARAM2 op_903b_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	uaecptr tmppc = m68k_getpci() + 2;
	do_cycles_ce000_internal(2);
	srca = get_disp_ea_000(tmppc, get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 2);
		return;
	}
	uae_s8 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 14 (3/0) */
/* 4 4,0   */

/* SUB.B #<data>.B,Dn */
void REGPARAM2 op_903c_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 8;  
	uae_s8 src = (uae_u8)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uae_s8 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 8 (2/0) */
/* 4 0,0   */

/* SUB.W Dn,Dn */
void REGPARAM2 op_9040_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 4;  
	uae_s16 src = m68k_dreg(regs, srcreg);
	uae_s16 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 4 (1/0) */
/* 2 0,0   */

/* SUB.W An,Dn */
void REGPARAM2 op_9048_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 4;  
	uae_s16 src = m68k_areg(regs, srcreg);
	uae_s16 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 4 (1/0) */
/* 2 0,0   */

/* SUB.W (An),Dn */
void REGPARAM2 op_9050_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 8;  
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 8 (2/0) */
/* 2 0,0   */

/* SUB.W (An)+,Dn */
void REGPARAM2 op_9058_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 8;  
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) += 2 + 0;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	m68k_areg(regs, srcreg) += 2;
	uae_s16 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 8 (2/0) */
/* 2 0,0   */

/* SUB.W -(An),Dn */
void REGPARAM2 op_9060_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 10; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - 2;
	do_cycles_ce000_internal(2);
	if (srca & 1) {
		m68k_incpci(4);
		m68k_areg(regs, srcreg) = srca;
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	m68k_areg(regs, srcreg) = srca;
	uae_s16 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 10 (2/0) */
/* 2 0,0   */

/* SUB.W (d16,An),Dn */
void REGPARAM2 op_9068_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 12 (3/0) */
/* 4 0,0   */

/* SUB.W (d8,An,Xn),Dn */
void REGPARAM2 op_9070_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	do_cycles_ce000_internal(2);
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 14 (3/0) */
/* 4 4,0   */

/* SUB.W (xxx).W,Dn */
void REGPARAM2 op_9078_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	if (srca & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 12 (3/0) */
/* 4 0,0   */

/* SUB.W (xxx).L,Dn */
void REGPARAM2 op_9079_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	srca |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	if (srca & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 16 (4/0) */
/* 6 0,0   */

/* SUB.W (d16,PC),Dn */
void REGPARAM2 op_907a_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_getpci() + 2;
	srca += (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 2);
		return;
	}
	ipl_fetch_now();
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 12 (3/0) */
/* 4 0,0   */

/* SUB.W (d8,PC,Xn),Dn */
void REGPARAM2 op_907b_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	uaecptr tmppc = m68k_getpci() + 2;
	do_cycles_ce000_internal(2);
	srca = get_disp_ea_000(tmppc, get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 2);
		return;
	}
	ipl_fetch_now();
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 14 (3/0) */
/* 4 4,0   */

/* SUB.W #<data>.W,Dn */
void REGPARAM2 op_907c_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 8;  
	uae_s16 src = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 8 (2/0) */
/* 4 0,0   */

/* SUB.L Dn,Dn */
void REGPARAM2 op_9080_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 8;  
	uae_s32 src = m68k_dreg(regs, srcreg);
	uae_s32 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		uae_s16 bnewv = (uae_s16)dst - (uae_s16)src;
		int bflgs = ((uae_s16)(src)) < 0;
		int bflgo = ((uae_s16)(dst)) < 0;
		int bflgn = bnewv < 0;
		ccr_68000_long_move_ae_LZN(bnewv);
		SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
		SET_XFLG(GET_CFLG());
		SET_VFLG((bflgs ^ bflgo) & (bflgn ^ bflgo));
		dreg_68000_long_replace_low(dstreg, bnewv);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	do_cycles_ce000_internal(4);
	m68k_dreg(regs, dstreg) = (newv);
	m68k_incpci(2);
	return;
}
/* 8 (1/0) */
/* 2 0,0   */

/* SUB.L An,Dn */
void REGPARAM2 op_9088_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 8;  
	uae_s32 src = m68k_areg(regs, srcreg);
	uae_s32 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		uae_s16 bnewv = (uae_s16)dst - (uae_s16)src;
		int bflgs = ((uae_s16)(src)) < 0;
		int bflgo = ((uae_s16)(dst)) < 0;
		int bflgn = bnewv < 0;
		ccr_68000_long_move_ae_LZN(bnewv);
		SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
		SET_XFLG(GET_CFLG());
		SET_VFLG((bflgs ^ bflgo) & (bflgn ^ bflgo));
		dreg_68000_long_replace_low(dstreg, bnewv);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	do_cycles_ce000_internal(4);
	m68k_dreg(regs, dstreg) = (newv);
	m68k_incpci(2);
	return;
}
/* 8 (1/0) */
/* 2 0,0   */

/* SUB.L (An),Dn */
void REGPARAM2 op_9090_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		dreg_68000_long_replace_low(dstreg, newv);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	do_cycles_ce000_internal(2);
	m68k_dreg(regs, dstreg) = (newv);
	m68k_incpci(2);
	return;
}
/* 14 (3/0) */
/* 2 0,0   */

/* SUB.L (An)+,Dn */
void REGPARAM2 op_9098_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	m68k_areg(regs, srcreg) += 4;
	uae_s32 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		dreg_68000_long_replace_low(dstreg, newv);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	do_cycles_ce000_internal(2);
	m68k_dreg(regs, dstreg) = (newv);
	m68k_incpci(2);
	return;
}
/* 14 (3/0) */
/* 2 0,0   */

/* SUB.L -(An),Dn */
void REGPARAM2 op_90a0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - 4;
	do_cycles_ce000_internal(2);
	if (srca & 1) {
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	m68k_areg(regs, srcreg) = srca;
	uae_s32 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		dreg_68000_long_replace_low(dstreg, newv);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	do_cycles_ce000_internal(2);
	m68k_dreg(regs, dstreg) = (newv);
	m68k_incpci(2);
	return;
}
/* 16 (3/0) */
/* 2 0,0   */

/* SUB.L (d16,An),Dn */
void REGPARAM2 op_90a8_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		dreg_68000_long_replace_low(dstreg, newv);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	do_cycles_ce000_internal(2);
	m68k_dreg(regs, dstreg) = (newv);
	m68k_incpci(4);
	return;
}
/* 18 (4/0) */
/* 4 0,0   */

/* SUB.L (d8,An,Xn),Dn */
void REGPARAM2 op_90b0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	do_cycles_ce000_internal(2);
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		dreg_68000_long_replace_low(dstreg, newv);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	do_cycles_ce000_internal(2);
	m68k_dreg(regs, dstreg) = (newv);
	m68k_incpci(4);
	return;
}
/* 20 (4/0) */
/* 4 4,0   */

/* SUB.L (xxx).W,Dn */
void REGPARAM2 op_90b8_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	if (srca & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		dreg_68000_long_replace_low(dstreg, newv);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	do_cycles_ce000_internal(2);
	m68k_dreg(regs, dstreg) = (newv);
	m68k_incpci(4);
	return;
}
/* 18 (4/0) */
/* 4 0,0   */

/* SUB.L (xxx).L,Dn */
void REGPARAM2 op_90b9_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 22; 
	uaecptr srca;
	srca = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	srca |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	if (srca & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		dreg_68000_long_replace_low(dstreg, newv);
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	opcode = regs.ir;
	do_cycles_ce000_internal(2);
	m68k_dreg(regs, dstreg) = (newv);
	m68k_incpci(6);
	return;
}
/* 22 (5/0) */
/* 6 0,0   */

/* SUB.L (d16,PC),Dn */
void REGPARAM2 op_90ba_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	srca = m68k_getpci() + 2;
	srca += (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 2);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return;
	}
	ipl_fetch_now();
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 2);
		return;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		dreg_68000_long_replace_low(dstreg, newv);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	do_cycles_ce000_internal(2);
	m68k_dreg(regs, dstreg) = (newv);
	m68k_incpci(4);
	return;
}
/* 18 (4/0) */
/* 4 0,0   */

/* SUB.L (d8,PC,Xn),Dn */
void REGPARAM2 op_90bb_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	uaecptr tmppc = m68k_getpci() + 2;
	do_cycles_ce000_internal(2);
	srca = get_disp_ea_000(tmppc, get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 2);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return;
	}
	ipl_fetch_now();
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 2);
		return;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		dreg_68000_long_replace_low(dstreg, newv);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	do_cycles_ce000_internal(2);
	m68k_dreg(regs, dstreg) = (newv);
	m68k_incpci(4);
	return;
}
/* 20 (4/0) */
/* 4 4,0   */

/* SUB.L #<data>.L,Dn */
void REGPARAM2 op_90bc_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 16; 
	uae_s32 src;
	src = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	ipl_fetch_now();
	src |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		uae_s16 bnewv = (uae_s16)dst - (uae_s16)src;
		int bflgs = ((uae_s16)(src)) < 0;
		int bflgo = ((uae_s16)(dst)) < 0;
		int bflgn = bnewv < 0;
		ccr_68000_long_move_ae_LZN(bnewv);
		SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
		SET_XFLG(GET_CFLG());
		SET_VFLG((bflgs ^ bflgo) & (bflgn ^ bflgo));
		dreg_68000_long_replace_low(dstreg, bnewv);
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	opcode = regs.ir;
	do_cycles_ce000_internal(4);
	m68k_dreg(regs, dstreg) = (newv);
	m68k_incpci(6);
	return;
}
/* 16 (3/0) */
/* 6 0,0   */

/* SUBA.W Dn,An */
void REGPARAM2 op_90c0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 8;
	CurrentInstrCycles = 8;  
	uae_s16 src = m68k_dreg(regs, srcreg);
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = dst - src;
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		areg_68000_long_replace_low(dstreg, newv);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	do_cycles_ce000_internal(4);
	m68k_areg(regs, dstreg) = (newv);
	m68k_incpci(2);
	return;
}
/* 8 (1/0) */
/* 2 0,0   */

/* SUBA.W An,An */
void REGPARAM2 op_90c8_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 8;
	CurrentInstrCycles = 8;  
	uae_s16 src = m68k_areg(regs, srcreg);
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = dst - src;
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		areg_68000_long_replace_low(dstreg, newv);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	do_cycles_ce000_internal(4);
	m68k_areg(regs, dstreg) = (newv);
	m68k_incpci(2);
	return;
}
/* 8 (1/0) */
/* 2 0,0   */

/* SUBA.W (An),An */
void REGPARAM2 op_90d0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 8;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = dst - src;
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		areg_68000_long_replace_low(dstreg, newv);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	do_cycles_ce000_internal(4);
	m68k_areg(regs, dstreg) = (newv);
	m68k_incpci(2);
	return;
}
/* 12 (2/0) */
/* 2 0,0   */

/* SUBA.W (An)+,An */
void REGPARAM2 op_90d8_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 8;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) += 2 + 0;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	m68k_areg(regs, srcreg) += 2;
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = dst - src;
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		areg_68000_long_replace_low(dstreg, newv);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	do_cycles_ce000_internal(4);
	m68k_areg(regs, dstreg) = (newv);
	m68k_incpci(2);
	return;
}
/* 12 (2/0) */
/* 2 0,0   */

/* SUBA.W -(An),An */
void REGPARAM2 op_90e0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 8;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - 2;
	do_cycles_ce000_internal(2);
	if (srca & 1) {
		m68k_incpci(4);
		m68k_areg(regs, srcreg) = srca;
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	m68k_areg(regs, srcreg) = srca;
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = dst - src;
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		areg_68000_long_replace_low(dstreg, newv);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	do_cycles_ce000_internal(4);
	m68k_areg(regs, dstreg) = (newv);
	m68k_incpci(2);
	return;
}
/* 14 (2/0) */
/* 2 0,0   */

/* SUBA.W (d16,An),An */
void REGPARAM2 op_90e8_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 8;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = dst - src;
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		areg_68000_long_replace_low(dstreg, newv);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	do_cycles_ce000_internal(4);
	m68k_areg(regs, dstreg) = (newv);
	m68k_incpci(4);
	return;
}
/* 16 (3/0) */
/* 4 0,0   */

/* SUBA.W (d8,An,Xn),An */
void REGPARAM2 op_90f0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 8;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	do_cycles_ce000_internal(2);
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = dst - src;
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		areg_68000_long_replace_low(dstreg, newv);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	do_cycles_ce000_internal(4);
	m68k_areg(regs, dstreg) = (newv);
	m68k_incpci(4);
	return;
}
/* 18 (3/0) */
/* 4 4,0   */

/* SUBA.W (xxx).W,An */
void REGPARAM2 op_90f8_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 8;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	if (srca & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = dst - src;
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		areg_68000_long_replace_low(dstreg, newv);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	do_cycles_ce000_internal(4);
	m68k_areg(regs, dstreg) = (newv);
	m68k_incpci(4);
	return;
}
/* 16 (3/0) */
/* 4 0,0   */

/* SUBA.W (xxx).L,An */
void REGPARAM2 op_90f9_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 8;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	srca = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	srca |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	if (srca & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = dst - src;
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		areg_68000_long_replace_low(dstreg, newv);
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	do_cycles_ce000_internal(4);
	m68k_areg(regs, dstreg) = (newv);
	m68k_incpci(6);
	return;
}
/* 20 (4/0) */
/* 6 0,0   */

/* SUBA.W (d16,PC),An */
void REGPARAM2 op_90fa_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 8;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = m68k_getpci() + 2;
	srca += (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 2);
		return;
	}
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return;
	}
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = dst - src;
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		areg_68000_long_replace_low(dstreg, newv);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	do_cycles_ce000_internal(4);
	m68k_areg(regs, dstreg) = (newv);
	m68k_incpci(4);
	return;
}
/* 16 (3/0) */
/* 4 0,0   */

/* SUBA.W (d8,PC,Xn),An */
void REGPARAM2 op_90fb_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 8;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	uaecptr tmppc = m68k_getpci() + 2;
	do_cycles_ce000_internal(2);
	srca = get_disp_ea_000(tmppc, get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 2);
		return;
	}
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return;
	}
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = dst - src;
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		areg_68000_long_replace_low(dstreg, newv);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	do_cycles_ce000_internal(4);
	m68k_areg(regs, dstreg) = (newv);
	m68k_incpci(4);
	return;
}
/* 18 (3/0) */
/* 4 4,0   */

/* SUBA.W #<data>.W,An */
void REGPARAM2 op_90fc_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 8;
	CurrentInstrCycles = 12; 
	uae_s16 src = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = dst - src;
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		areg_68000_long_replace_low(dstreg, newv);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	do_cycles_ce000_internal(4);
	m68k_areg(regs, dstreg) = (newv);
	m68k_incpci(4);
	return;
}
/* 12 (2/0) */
/* 4 0,0   */

/* SUBX.B Dn,Dn */
void REGPARAM2 op_9100_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 9;
	CurrentInstrCycles = 4;  
	uae_s8 src = m68k_dreg(regs, srcreg);
	uae_s8 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = dst - src - (GET_XFLG() ? 1 : 0);
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_VFLG((flgs ^ flgo) & (flgo ^ flgn));
	SET_CFLG(flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
	COPY_CARRY();
	SET_ZFLG(GET_ZFLG() & (((uae_s8)(newv)) == 0));
	SET_NFLG(((uae_s8)(newv)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
	m68k_incpci(2);
	return;
}
/* 4 (1/0) */
/* 2 0,0   */

/* SUBX.B -(An),-(An) */
void REGPARAM2 op_9108_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 9;
	CurrentInstrCycles = 18; 
	do_cycles_ce000_internal(2);
	ipl_fetch_now();
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	m68k_areg(regs, srcreg) = srca;
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, dstreg) = dsta;
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	m68k_areg(regs, dstreg) = dsta;
	uae_u32 newv = dst - src - (GET_XFLG() ? 1 : 0);
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_VFLG((flgs ^ flgo) & (flgo ^ flgn));
	SET_CFLG(flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
	COPY_CARRY();
	SET_ZFLG(GET_ZFLG() & (((uae_s8)(newv)) == 0));
	SET_NFLG(((uae_s8)(newv)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_byte(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, newv, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 18 (3/1) */
/* 2 0,0   */

/* SUB.B Dn,(An) */
void REGPARAM2 op_9110_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 12; 
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_byte(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, newv, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 12 (2/1) */
/* 2 0,0   */

/* SUB.B Dn,(An)+ */
void REGPARAM2 op_9118_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 12; 
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
	uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_byte(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, newv, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 12 (2/1) */
/* 2 0,0   */

/* SUB.B Dn,-(An) */
void REGPARAM2 op_9120_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 14; 
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
	do_cycles_ce000_internal(2);
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, dstreg) = dsta;
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	m68k_areg(regs, dstreg) = dsta;
	uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_byte(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, newv, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 14 (2/1) */
/* 2 0,0   */

/* SUB.B Dn,(d16,An) */
void REGPARAM2 op_9128_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 16; 
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_byte(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, newv, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* SUB.B Dn,(d8,An,Xn) */
void REGPARAM2 op_9130_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 18; 
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	do_cycles_ce000_internal(2);
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_byte(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, newv, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 18 (3/1) */
/* 4 4,0   */

/* SUB.B Dn,(xxx).W */
void REGPARAM2 op_9138_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	OpcodeFamily = 7;
	CurrentInstrCycles = 16; 
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_byte(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, newv, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* SUB.B Dn,(xxx).L */
void REGPARAM2 op_9139_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	OpcodeFamily = 7;
	CurrentInstrCycles = 20; 
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	dsta |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_byte(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, newv, 1);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 20 (4/1) */
/* 6 0,0   */

/* SUBX.W Dn,Dn */
void REGPARAM2 op_9140_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 9;
	CurrentInstrCycles = 4;  
	uae_s16 src = m68k_dreg(regs, srcreg);
	uae_s16 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = dst - src - (GET_XFLG() ? 1 : 0);
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_VFLG((flgs ^ flgo) & (flgo ^ flgn));
	SET_CFLG(flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
	COPY_CARRY();
	SET_ZFLG(GET_ZFLG() & (((uae_s16)(newv)) == 0));
	SET_NFLG(((uae_s16)(newv)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
	m68k_incpci(2);
	return;
}
/* 4 (1/0) */
/* 2 0,0   */

/* SUBX.W -(An),-(An) */
void REGPARAM2 op_9148_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 9;
	CurrentInstrCycles = 18; 
	do_cycles_ce000_internal(2);
	ipl_fetch_now();
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - 2;
	if (srca & 1) {
		m68k_areg(regs, srcreg) = srca;
		m68k_incpci(4);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	m68k_areg(regs, srcreg) = srca;
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - 2;
	if (dsta & 1) {
		m68k_areg(regs, dstreg) = dsta;
		m68k_incpci(4);
		exception3_read_access(opcode, dsta, 1, 1);
		return;
	}
	uae_s16 dst = x_get_word(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, dstreg) = dsta;
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	m68k_areg(regs, dstreg) = dsta;
	uae_u32 newv = dst - src - (GET_XFLG() ? 1 : 0);
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_VFLG((flgs ^ flgo) & (flgo ^ flgn));
	SET_CFLG(flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
	COPY_CARRY();
	SET_ZFLG(GET_ZFLG() & (((uae_s16)(newv)) == 0));
	SET_NFLG(((uae_s16)(newv)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_word(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x1, newv, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 18 (3/1) */
/* 2 0,0   */

/* SUB.W Dn,(An) */
void REGPARAM2 op_9150_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 12; 
	uae_s16 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	if (dsta & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dsta, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 dst = x_get_word(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_word(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x1, newv, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 12 (2/1) */
/* 2 0,0   */

/* SUB.W Dn,(An)+ */
void REGPARAM2 op_9158_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 12; 
	uae_s16 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	if (dsta & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dsta, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 dst = x_get_word(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, dstreg) += 2 + 0;
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	m68k_areg(regs, dstreg) += 2;
	uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_word(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x1, newv, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 12 (2/1) */
/* 2 0,0   */

/* SUB.W Dn,-(An) */
void REGPARAM2 op_9160_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 14; 
	uae_s16 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - 2;
	do_cycles_ce000_internal(2);
	if (dsta & 1) {
		m68k_incpci(4);
		m68k_areg(regs, dstreg) = dsta;
		exception3_read_access(opcode, dsta, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 dst = x_get_word(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, dstreg) = dsta;
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	m68k_areg(regs, dstreg) = dsta;
	uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_word(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x1, newv, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 14 (2/1) */
/* 2 0,0   */

/* SUB.W Dn,(d16,An) */
void REGPARAM2 op_9168_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 16; 
	uae_s16 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dsta, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 dst = x_get_word(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_word(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x1, newv, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* SUB.W Dn,(d8,An,Xn) */
void REGPARAM2 op_9170_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 18; 
	uae_s16 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	do_cycles_ce000_internal(2);
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dsta, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 dst = x_get_word(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_word(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x1, newv, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 18 (3/1) */
/* 4 4,0   */

/* SUB.W Dn,(xxx).W */
void REGPARAM2 op_9178_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	OpcodeFamily = 7;
	CurrentInstrCycles = 16; 
	uae_s16 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, dsta, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 dst = x_get_word(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_word(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x1, newv, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* SUB.W Dn,(xxx).L */
void REGPARAM2 op_9179_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	OpcodeFamily = 7;
	CurrentInstrCycles = 20; 
	uae_s16 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	dsta |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, dsta, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 dst = x_get_word(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_word(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x1, newv, 1);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 20 (4/1) */
/* 6 0,0   */

/* SUBX.L Dn,Dn */
void REGPARAM2 op_9180_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 9;
	CurrentInstrCycles = 8;  
	uae_s32 src = m68k_dreg(regs, srcreg);
	uae_s32 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = dst - src - (GET_XFLG() ? 1 : 0);
	int oldz = GET_ZFLG();
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_VFLG((flgs ^ flgo) & (flgo ^ flgn));
	SET_CFLG(flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
	COPY_CARRY();
	SET_ZFLG(GET_ZFLG() & (((uae_s32)(newv)) == 0));
	SET_NFLG(((uae_s32)(newv)) < 0);
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		int bflgs = ((uae_s16)(src)) < 0;
		int bflgo = ((uae_s16)(dst)) < 0;
		int bflgn = ((uae_s16)(newv)) < 0;
		SET_VFLG((bflgs ^ bflgo) & (bflgo ^ bflgn));
		SET_CFLG(bflgs ^ ((bflgs ^ bflgn) & (bflgo ^ bflgn)));
		SET_XFLG(GET_CFLG());
		SET_ZFLG(oldz);
		if (newv & 0xffff) SET_ZFLG(0);
		SET_NFLG(newv & 0x8000); 
		dreg_68000_long_replace_low(dstreg, newv);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	do_cycles_ce000_internal(4);
	m68k_dreg(regs, dstreg) = (newv);
	m68k_incpci(2);
	return;
}
/* 8 (1/0) */
/* 2 0,0   */

/* SUBX.L -(An),-(An) */
void REGPARAM2 op_9188_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 9;
	CurrentInstrCycles = 30; 
	do_cycles_ce000_internal(2);
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - 4;
	if (srca & 1) {
		m68k_incpci(4);
		srca += 2;
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	src |= x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	m68k_areg(regs, srcreg) = srca;
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - 4;
	if (dsta & 1) {
		m68k_incpci(4);
		dsta += 2;
		exception3_read_access(opcode, dsta, 2, 1);
		return;
	}
	uae_s32 dst = x_get_word(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	dst |= x_get_word(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	m68k_areg(regs, dstreg) = dsta;
	uae_u32 newv = dst - src - (GET_XFLG() ? 1 : 0);
	int oldz = GET_ZFLG();
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_VFLG((flgs ^ flgo) & (flgo ^ flgn));
	SET_CFLG(flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
	COPY_CARRY();
	SET_ZFLG(GET_ZFLG() & (((uae_s32)(newv)) == 0));
	SET_NFLG(((uae_s32)(newv)) < 0);
	x_put_word(dsta + 2, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		int bflgs = ((uae_s16)(src)) < 0;
		int bflgo = ((uae_s16)(dst)) < 0;
		int bflgn = ((uae_s16)(newv)) < 0;
		SET_VFLG((bflgs ^ bflgo) & (bflgo ^ bflgn));
		SET_CFLG(bflgs ^ ((bflgs ^ bflgn) & (bflgo ^ bflgn)));
		COPY_CARRY();
		SET_ZFLG(GET_ZFLG() & (((uae_s16)(newv)) == 0));
		SET_NFLG(((uae_s16)(newv)) < 0);
		exception2_write(opcode, dsta + 2, 0x1, newv, 1);
		return;
	}
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	x_put_word(dsta, newv >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x1, newv >> 16, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 30 (5/2) */
/* 2 0,0   */

/* SUB.L Dn,(An) */
void REGPARAM2 op_9190_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 20; 
	uae_s32 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	if (dsta & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dsta, 2, 1);
		return;
	}
	uae_s32 dst = x_get_word(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	dst |= x_get_word(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return;
	}
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		uae_s16 bnewv = (uae_s16)dst - (uae_s16)src;
		int bflgs = ((uae_s16)(src)) < 0;
		int bflgo = ((uae_s16)(dst)) < 0;
		int bflgn = bnewv < 0;
		ccr_68000_long_move_ae_LZN(bnewv);
		SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
		SET_XFLG(GET_CFLG());
		SET_VFLG((bflgs ^ bflgo) & (bflgn ^ bflgo));
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	x_put_word(dsta + 2, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 2, 0x1, newv, 1);
		return;
	}
	x_put_word(dsta, newv >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x1, newv >> 16, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 20 (3/2) */
/* 2 0,0   */

/* SUB.L Dn,(An)+ */
void REGPARAM2 op_9198_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 20; 
	uae_s32 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	if (dsta & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dsta, 2, 1);
		return;
	}
	uae_s32 dst = x_get_word(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	dst |= x_get_word(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return;
	}
	m68k_areg(regs, dstreg) += 4;
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		uae_s16 bnewv = (uae_s16)dst - (uae_s16)src;
		int bflgs = ((uae_s16)(src)) < 0;
		int bflgo = ((uae_s16)(dst)) < 0;
		int bflgn = bnewv < 0;
		ccr_68000_long_move_ae_LZN(bnewv);
		SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
		SET_XFLG(GET_CFLG());
		SET_VFLG((bflgs ^ bflgo) & (bflgn ^ bflgo));
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	x_put_word(dsta + 2, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 2, 0x1, newv, 1);
		return;
	}
	x_put_word(dsta, newv >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x1, newv >> 16, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 20 (3/2) */
/* 2 0,0   */

/* SUB.L Dn,-(An) */
void REGPARAM2 op_91a0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 22; 
	uae_s32 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - 4;
	do_cycles_ce000_internal(2);
	if (dsta & 1) {
		m68k_incpci(2);
		m68k_areg(regs, dstreg) = dsta;
		exception3_read_access(opcode, dsta, 2, 1);
		return;
	}
	uae_s32 dst = x_get_word(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, dstreg) = dsta;
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	dst |= x_get_word(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, dstreg) = dsta;
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return;
	}
	m68k_areg(regs, dstreg) = dsta;
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		uae_s16 bnewv = (uae_s16)dst - (uae_s16)src;
		int bflgs = ((uae_s16)(src)) < 0;
		int bflgo = ((uae_s16)(dst)) < 0;
		int bflgn = bnewv < 0;
		ccr_68000_long_move_ae_LZN(bnewv);
		SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
		SET_XFLG(GET_CFLG());
		SET_VFLG((bflgs ^ bflgo) & (bflgn ^ bflgo));
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	x_put_word(dsta + 2, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 2, 0x1, newv, 1);
		return;
	}
	x_put_word(dsta, newv >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x1, newv >> 16, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 22 (3/2) */
/* 2 0,0   */

/* SUB.L Dn,(d16,An) */
void REGPARAM2 op_91a8_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 24; 
	uae_s32 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dsta, 2, 1);
		return;
	}
	uae_s32 dst = x_get_word(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	dst |= x_get_word(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return;
	}
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		uae_s16 bnewv = (uae_s16)dst - (uae_s16)src;
		int bflgs = ((uae_s16)(src)) < 0;
		int bflgo = ((uae_s16)(dst)) < 0;
		int bflgn = bnewv < 0;
		ccr_68000_long_move_ae_LZN(bnewv);
		SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
		SET_XFLG(GET_CFLG());
		SET_VFLG((bflgs ^ bflgo) & (bflgn ^ bflgo));
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	x_put_word(dsta + 2, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 2, 0x1, newv, 1);
		return;
	}
	x_put_word(dsta, newv >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, newv >> 16, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 24 (4/2) */
/* 4 0,0   */

/* SUB.L Dn,(d8,An,Xn) */
void REGPARAM2 op_91b0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 7;
	CurrentInstrCycles = 26; 
	uae_s32 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	do_cycles_ce000_internal(2);
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dsta, 2, 1);
		return;
	}
	uae_s32 dst = x_get_word(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	dst |= x_get_word(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return;
	}
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		uae_s16 bnewv = (uae_s16)dst - (uae_s16)src;
		int bflgs = ((uae_s16)(src)) < 0;
		int bflgo = ((uae_s16)(dst)) < 0;
		int bflgn = bnewv < 0;
		ccr_68000_long_move_ae_LZN(bnewv);
		SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
		SET_XFLG(GET_CFLG());
		SET_VFLG((bflgs ^ bflgo) & (bflgn ^ bflgo));
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	x_put_word(dsta + 2, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 2, 0x1, newv, 1);
		return;
	}
	x_put_word(dsta, newv >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, newv >> 16, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 26 (4/2) */
/* 4 4,0   */

/* SUB.L Dn,(xxx).W */
void REGPARAM2 op_91b8_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	OpcodeFamily = 7;
	CurrentInstrCycles = 24; 
	uae_s32 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, dsta, 2, 1);
		return;
	}
	uae_s32 dst = x_get_word(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	dst |= x_get_word(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return;
	}
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		uae_s16 bnewv = (uae_s16)dst - (uae_s16)src;
		int bflgs = ((uae_s16)(src)) < 0;
		int bflgo = ((uae_s16)(dst)) < 0;
		int bflgn = bnewv < 0;
		ccr_68000_long_move_ae_LZN(bnewv);
		SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
		SET_XFLG(GET_CFLG());
		SET_VFLG((bflgs ^ bflgo) & (bflgn ^ bflgo));
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	x_put_word(dsta + 2, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 2, 0x1, newv, 1);
		return;
	}
	x_put_word(dsta, newv >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, newv >> 16, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 24 (4/2) */
/* 4 0,0   */

/* SUB.L Dn,(xxx).L */
void REGPARAM2 op_91b9_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	OpcodeFamily = 7;
	CurrentInstrCycles = 28; 
	uae_s32 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	dsta |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, dsta, 2, 1);
		return;
	}
	uae_s32 dst = x_get_word(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	dst |= x_get_word(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return;
	}
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		uae_s16 bnewv = (uae_s16)dst - (uae_s16)src;
		int bflgs = ((uae_s16)(src)) < 0;
		int bflgo = ((uae_s16)(dst)) < 0;
		int bflgn = bnewv < 0;
		ccr_68000_long_move_ae_LZN(bnewv);
		SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
		SET_XFLG(GET_CFLG());
		SET_VFLG((bflgs ^ bflgo) & (bflgn ^ bflgo));
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	x_put_word(dsta + 2, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 2, 0x1, newv, 1);
		return;
	}
	x_put_word(dsta, newv >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 0, 0x1, newv >> 16, 1);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 28 (5/2) */
/* 6 0,0   */

/* SUBA.L Dn,An */
void REGPARAM2 op_91c0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 8;
	CurrentInstrCycles = 8;  
	uae_s32 src = m68k_dreg(regs, srcreg);
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = dst - src;
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		areg_68000_long_replace_low(dstreg, newv);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	do_cycles_ce000_internal(4);
	m68k_areg(regs, dstreg) = (newv);
	m68k_incpci(2);
	return;
}
/* 8 (1/0) */
/* 2 0,0   */

/* SUBA.L An,An */
void REGPARAM2 op_91c8_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 8;
	CurrentInstrCycles = 8;  
	uae_s32 src = m68k_areg(regs, srcreg);
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = dst - src;
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		areg_68000_long_replace_low(dstreg, newv);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	do_cycles_ce000_internal(4);
	m68k_areg(regs, dstreg) = (newv);
	m68k_incpci(2);
	return;
}
/* 8 (1/0) */
/* 2 0,0   */

/* SUBA.L (An),An */
void REGPARAM2 op_91d0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 8;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = dst - src;
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		areg_68000_long_replace_low(dstreg, newv);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	do_cycles_ce000_internal(2);
	m68k_areg(regs, dstreg) = (newv);
	m68k_incpci(2);
	return;
}
/* 14 (3/0) */
/* 2 0,0   */

/* SUBA.L (An)+,An */
void REGPARAM2 op_91d8_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 8;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	m68k_areg(regs, srcreg) += 4;
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = dst - src;
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		areg_68000_long_replace_low(dstreg, newv);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	do_cycles_ce000_internal(2);
	m68k_areg(regs, dstreg) = (newv);
	m68k_incpci(2);
	return;
}
/* 14 (3/0) */
/* 2 0,0   */

/* SUBA.L -(An),An */
void REGPARAM2 op_91e0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 8;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - 4;
	do_cycles_ce000_internal(2);
	if (srca & 1) {
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	m68k_areg(regs, srcreg) = srca;
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = dst - src;
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		areg_68000_long_replace_low(dstreg, newv);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	do_cycles_ce000_internal(2);
	m68k_areg(regs, dstreg) = (newv);
	m68k_incpci(2);
	return;
}
/* 16 (3/0) */
/* 2 0,0   */

/* SUBA.L (d16,An),An */
void REGPARAM2 op_91e8_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 8;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = dst - src;
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		areg_68000_long_replace_low(dstreg, newv);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	do_cycles_ce000_internal(2);
	m68k_areg(regs, dstreg) = (newv);
	m68k_incpci(4);
	return;
}
/* 18 (4/0) */
/* 4 0,0   */

/* SUBA.L (d8,An,Xn),An */
void REGPARAM2 op_91f0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 8;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	do_cycles_ce000_internal(2);
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = dst - src;
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		areg_68000_long_replace_low(dstreg, newv);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	do_cycles_ce000_internal(2);
	m68k_areg(regs, dstreg) = (newv);
	m68k_incpci(4);
	return;
}
/* 20 (4/0) */
/* 4 4,0   */

/* SUBA.L (xxx).W,An */
void REGPARAM2 op_91f8_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 8;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	if (srca & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = dst - src;
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		areg_68000_long_replace_low(dstreg, newv);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	do_cycles_ce000_internal(2);
	m68k_areg(regs, dstreg) = (newv);
	m68k_incpci(4);
	return;
}
/* 18 (4/0) */
/* 4 0,0   */

/* SUBA.L (xxx).L,An */
void REGPARAM2 op_91f9_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 8;
	CurrentInstrCycles = 22; 
	uaecptr srca;
	srca = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	srca |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	if (srca & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = dst - src;
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		areg_68000_long_replace_low(dstreg, newv);
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	do_cycles_ce000_internal(2);
	m68k_areg(regs, dstreg) = (newv);
	m68k_incpci(6);
	return;
}
/* 22 (5/0) */
/* 6 0,0   */

/* SUBA.L (d16,PC),An */
void REGPARAM2 op_91fa_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 8;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	srca = m68k_getpci() + 2;
	srca += (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 2);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return;
	}
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 2);
		return;
	}
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = dst - src;
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		areg_68000_long_replace_low(dstreg, newv);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	do_cycles_ce000_internal(2);
	m68k_areg(regs, dstreg) = (newv);
	m68k_incpci(4);
	return;
}
/* 18 (4/0) */
/* 4 0,0   */

/* SUBA.L (d8,PC,Xn),An */
void REGPARAM2 op_91fb_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 8;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	uaecptr tmppc = m68k_getpci() + 2;
	do_cycles_ce000_internal(2);
	srca = get_disp_ea_000(tmppc, get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 2);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return;
	}
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 2);
		return;
	}
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = dst - src;
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		areg_68000_long_replace_low(dstreg, newv);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	do_cycles_ce000_internal(2);
	m68k_areg(regs, dstreg) = (newv);
	m68k_incpci(4);
	return;
}
/* 20 (4/0) */
/* 4 4,0   */

/* SUBA.L #<data>.L,An */
void REGPARAM2 op_91fc_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 8;
	CurrentInstrCycles = 16; 
	uae_s32 src;
	src = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	src |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = dst - src;
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		areg_68000_long_replace_low(dstreg, newv);
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	do_cycles_ce000_internal(4);
	m68k_areg(regs, dstreg) = (newv);
	m68k_incpci(6);
	return;
}
/* 16 (3/0) */
/* 6 0,0   */

/* CMP.B Dn,Dn */
void REGPARAM2 op_b000_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 25;
	CurrentInstrCycles = 4;  
	uae_s8 src = m68k_dreg(regs, srcreg);
	uae_s8 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 4 (1/0) */
/* 2 0,0   */

/* CMP.B (An),Dn */
void REGPARAM2 op_b010_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 25;
	CurrentInstrCycles = 8;  
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	uae_s8 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 8 (2/0) */
/* 2 0,0   */

/* CMP.B (An)+,Dn */
void REGPARAM2 op_b018_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 25;
	CurrentInstrCycles = 8;  
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
	uae_s8 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 8 (2/0) */
/* 2 0,0   */

/* CMP.B -(An),Dn */
void REGPARAM2 op_b020_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 25;
	CurrentInstrCycles = 10; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
	do_cycles_ce000_internal(2);
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	m68k_areg(regs, srcreg) = srca;
	uae_s8 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 10 (2/0) */
/* 2 0,0   */

/* CMP.B (d16,An),Dn */
void REGPARAM2 op_b028_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 25;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	uae_s8 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 12 (3/0) */
/* 4 0,0   */

/* CMP.B (d8,An,Xn),Dn */
void REGPARAM2 op_b030_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 25;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	do_cycles_ce000_internal(2);
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	uae_s8 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 14 (3/0) */
/* 4 4,0   */

/* CMP.B (xxx).W,Dn */
void REGPARAM2 op_b038_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 25;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	uae_s8 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 12 (3/0) */
/* 4 0,0   */

/* CMP.B (xxx).L,Dn */
void REGPARAM2 op_b039_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 25;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	srca |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	uae_s8 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 16 (4/0) */
/* 6 0,0   */

/* CMP.B (d16,PC),Dn */
void REGPARAM2 op_b03a_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 25;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_getpci() + 2;
	srca += (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 2);
		return;
	}
	uae_s8 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 12 (3/0) */
/* 4 0,0   */

/* CMP.B (d8,PC,Xn),Dn */
void REGPARAM2 op_b03b_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 25;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	uaecptr tmppc = m68k_getpci() + 2;
	do_cycles_ce000_internal(2);
	srca = get_disp_ea_000(tmppc, get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 2);
		return;
	}
	uae_s8 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 14 (3/0) */
/* 4 4,0   */

/* CMP.B #<data>.B,Dn */
void REGPARAM2 op_b03c_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 25;
	CurrentInstrCycles = 8;  
	uae_s8 src = (uae_u8)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uae_s8 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 8 (2/0) */
/* 4 0,0   */

/* CMP.W Dn,Dn */
void REGPARAM2 op_b040_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 25;
	CurrentInstrCycles = 4;  
	uae_s16 src = m68k_dreg(regs, srcreg);
	uae_s16 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 4 (1/0) */
/* 2 0,0   */

/* CMP.W An,Dn */
void REGPARAM2 op_b048_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 25;
	CurrentInstrCycles = 4;  
	uae_s16 src = m68k_areg(regs, srcreg);
	uae_s16 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 4 (1/0) */
/* 2 0,0   */

/* CMP.W (An),Dn */
void REGPARAM2 op_b050_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 25;
	CurrentInstrCycles = 8;  
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 8 (2/0) */
/* 2 0,0   */

/* CMP.W (An)+,Dn */
void REGPARAM2 op_b058_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 25;
	CurrentInstrCycles = 8;  
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) += 2 + 0;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	m68k_areg(regs, srcreg) += 2;
	uae_s16 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 8 (2/0) */
/* 2 0,0   */

/* CMP.W -(An),Dn */
void REGPARAM2 op_b060_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 25;
	CurrentInstrCycles = 10; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - 2;
	do_cycles_ce000_internal(2);
	if (srca & 1) {
		m68k_incpci(4);
		m68k_areg(regs, srcreg) = srca;
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	m68k_areg(regs, srcreg) = srca;
	uae_s16 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 10 (2/0) */
/* 2 0,0   */

/* CMP.W (d16,An),Dn */
void REGPARAM2 op_b068_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 25;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 12 (3/0) */
/* 4 0,0   */

/* CMP.W (d8,An,Xn),Dn */
void REGPARAM2 op_b070_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 25;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	do_cycles_ce000_internal(2);
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 14 (3/0) */
/* 4 4,0   */

/* CMP.W (xxx).W,Dn */
void REGPARAM2 op_b078_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 25;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	if (srca & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 12 (3/0) */
/* 4 0,0   */

/* CMP.W (xxx).L,Dn */
void REGPARAM2 op_b079_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 25;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	srca |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	if (srca & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 16 (4/0) */
/* 6 0,0   */

/* CMP.W (d16,PC),Dn */
void REGPARAM2 op_b07a_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 25;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_getpci() + 2;
	srca += (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 2);
		return;
	}
	ipl_fetch_now();
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 12 (3/0) */
/* 4 0,0   */

/* CMP.W (d8,PC,Xn),Dn */
void REGPARAM2 op_b07b_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 25;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	uaecptr tmppc = m68k_getpci() + 2;
	do_cycles_ce000_internal(2);
	srca = get_disp_ea_000(tmppc, get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 2);
		return;
	}
	ipl_fetch_now();
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 14 (3/0) */
/* 4 4,0   */

/* CMP.W #<data>.W,Dn */
void REGPARAM2 op_b07c_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 25;
	CurrentInstrCycles = 8;  
	uae_s16 src = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 8 (2/0) */
/* 4 0,0   */

/* CMP.L Dn,Dn */
void REGPARAM2 op_b080_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 25;
	CurrentInstrCycles = 6;  
	uae_s32 src = m68k_dreg(regs, srcreg);
	uae_s32 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	SET_NFLG(flgn != 0);
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	do_cycles_ce000_internal(2);
	m68k_incpci(2);
	return;
}
/* 6 (1/0) */
/* 2 0,0   */

/* CMP.L An,Dn */
void REGPARAM2 op_b088_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 25;
	CurrentInstrCycles = 6;  
	uae_s32 src = m68k_areg(regs, srcreg);
	uae_s32 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	SET_NFLG(flgn != 0);
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	do_cycles_ce000_internal(2);
	m68k_incpci(2);
	return;
}
/* 6 (1/0) */
/* 2 0,0   */

/* CMP.L (An),Dn */
void REGPARAM2 op_b090_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 25;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	SET_NFLG(flgn != 0);
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	do_cycles_ce000_internal(2);
	m68k_incpci(2);
	return;
}
/* 14 (3/0) */
/* 2 0,0   */

/* CMP.L (An)+,Dn */
void REGPARAM2 op_b098_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 25;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	m68k_areg(regs, srcreg) += 4;
	uae_s32 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	SET_NFLG(flgn != 0);
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	do_cycles_ce000_internal(2);
	m68k_incpci(2);
	return;
}
/* 14 (3/0) */
/* 2 0,0   */

/* CMP.L -(An),Dn */
void REGPARAM2 op_b0a0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 25;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - 4;
	do_cycles_ce000_internal(2);
	if (srca & 1) {
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	m68k_areg(regs, srcreg) = srca;
	uae_s32 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	SET_NFLG(flgn != 0);
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	do_cycles_ce000_internal(2);
	m68k_incpci(2);
	return;
}
/* 16 (3/0) */
/* 2 0,0   */

/* CMP.L (d16,An),Dn */
void REGPARAM2 op_b0a8_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 25;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	SET_NFLG(flgn != 0);
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	do_cycles_ce000_internal(2);
	m68k_incpci(4);
	return;
}
/* 18 (4/0) */
/* 4 0,0   */

/* CMP.L (d8,An,Xn),Dn */
void REGPARAM2 op_b0b0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 25;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	do_cycles_ce000_internal(2);
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	SET_NFLG(flgn != 0);
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	do_cycles_ce000_internal(2);
	m68k_incpci(4);
	return;
}
/* 20 (4/0) */
/* 4 4,0   */

/* CMP.L (xxx).W,Dn */
void REGPARAM2 op_b0b8_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 25;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	if (srca & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	SET_NFLG(flgn != 0);
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	do_cycles_ce000_internal(2);
	m68k_incpci(4);
	return;
}
/* 18 (4/0) */
/* 4 0,0   */

/* CMP.L (xxx).L,Dn */
void REGPARAM2 op_b0b9_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 25;
	CurrentInstrCycles = 22; 
	uaecptr srca;
	srca = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	srca |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	if (srca & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	SET_NFLG(flgn != 0);
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	opcode = regs.ir;
	do_cycles_ce000_internal(2);
	m68k_incpci(6);
	return;
}
/* 22 (5/0) */
/* 6 0,0   */

/* CMP.L (d16,PC),Dn */
void REGPARAM2 op_b0ba_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 25;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	srca = m68k_getpci() + 2;
	srca += (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 2);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return;
	}
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 2);
		return;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	SET_NFLG(flgn != 0);
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	do_cycles_ce000_internal(2);
	m68k_incpci(4);
	return;
}
/* 18 (4/0) */
/* 4 0,0   */

/* CMP.L (d8,PC,Xn),Dn */
void REGPARAM2 op_b0bb_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 25;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	uaecptr tmppc = m68k_getpci() + 2;
	do_cycles_ce000_internal(2);
	srca = get_disp_ea_000(tmppc, get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 2);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return;
	}
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 2);
		return;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	SET_NFLG(flgn != 0);
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	do_cycles_ce000_internal(2);
	m68k_incpci(4);
	return;
}
/* 20 (4/0) */
/* 4 4,0   */

/* CMP.L #<data>.L,Dn */
void REGPARAM2 op_b0bc_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 25;
	CurrentInstrCycles = 14; 
	uae_s32 src;
	src = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	src |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	SET_NFLG(flgn != 0);
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	opcode = regs.ir;
	do_cycles_ce000_internal(2);
	m68k_incpci(6);
	return;
}
/* 14 (3/0) */
/* 6 0,0   */

/* CMPA.W Dn,An */
void REGPARAM2 op_b0c0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 27;
	CurrentInstrCycles = 6;  
	uae_s16 src = m68k_dreg(regs, srcreg);
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	SET_NFLG(flgn != 0);
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	do_cycles_ce000_internal(2);
	m68k_incpci(2);
	return;
}
/* 6 (1/0) */
/* 2 0,0   */

/* CMPA.W An,An */
void REGPARAM2 op_b0c8_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 27;
	CurrentInstrCycles = 6;  
	uae_s16 src = m68k_areg(regs, srcreg);
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	SET_NFLG(flgn != 0);
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	do_cycles_ce000_internal(2);
	m68k_incpci(2);
	return;
}
/* 6 (1/0) */
/* 2 0,0   */

/* CMPA.W (An),An */
void REGPARAM2 op_b0d0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 27;
	CurrentInstrCycles = 10; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	SET_NFLG(flgn != 0);
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	do_cycles_ce000_internal(2);
	m68k_incpci(2);
	return;
}
/* 10 (2/0) */
/* 2 0,0   */

/* CMPA.W (An)+,An */
void REGPARAM2 op_b0d8_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 27;
	CurrentInstrCycles = 10; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) += 2 + 0;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	m68k_areg(regs, srcreg) += 2;
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	SET_NFLG(flgn != 0);
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	do_cycles_ce000_internal(2);
	m68k_incpci(2);
	return;
}
/* 10 (2/0) */
/* 2 0,0   */

/* CMPA.W -(An),An */
void REGPARAM2 op_b0e0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 27;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - 2;
	do_cycles_ce000_internal(2);
	if (srca & 1) {
		m68k_incpci(4);
		m68k_areg(regs, srcreg) = srca;
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	m68k_areg(regs, srcreg) = srca;
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	SET_NFLG(flgn != 0);
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	do_cycles_ce000_internal(2);
	m68k_incpci(2);
	return;
}
/* 12 (2/0) */
/* 2 0,0   */

/* CMPA.W (d16,An),An */
void REGPARAM2 op_b0e8_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 27;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	SET_NFLG(flgn != 0);
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	do_cycles_ce000_internal(2);
	m68k_incpci(4);
	return;
}
/* 14 (3/0) */
/* 4 0,0   */

/* CMPA.W (d8,An,Xn),An */
void REGPARAM2 op_b0f0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 27;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	do_cycles_ce000_internal(2);
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	SET_NFLG(flgn != 0);
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	do_cycles_ce000_internal(2);
	m68k_incpci(4);
	return;
}
/* 16 (3/0) */
/* 4 4,0   */

/* CMPA.W (xxx).W,An */
void REGPARAM2 op_b0f8_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 27;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	if (srca & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	SET_NFLG(flgn != 0);
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	do_cycles_ce000_internal(2);
	m68k_incpci(4);
	return;
}
/* 14 (3/0) */
/* 4 0,0   */

/* CMPA.W (xxx).L,An */
void REGPARAM2 op_b0f9_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 27;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	srca = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	srca |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	if (srca & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	SET_NFLG(flgn != 0);
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	opcode = regs.ir;
	do_cycles_ce000_internal(2);
	m68k_incpci(6);
	return;
}
/* 18 (4/0) */
/* 6 0,0   */

/* CMPA.W (d16,PC),An */
void REGPARAM2 op_b0fa_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 27;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	srca = m68k_getpci() + 2;
	srca += (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 2);
		return;
	}
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return;
	}
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	SET_NFLG(flgn != 0);
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	do_cycles_ce000_internal(2);
	m68k_incpci(4);
	return;
}
/* 14 (3/0) */
/* 4 0,0   */

/* CMPA.W (d8,PC,Xn),An */
void REGPARAM2 op_b0fb_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 27;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	uaecptr tmppc = m68k_getpci() + 2;
	do_cycles_ce000_internal(2);
	srca = get_disp_ea_000(tmppc, get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 2);
		return;
	}
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return;
	}
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	SET_NFLG(flgn != 0);
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	do_cycles_ce000_internal(2);
	m68k_incpci(4);
	return;
}
/* 16 (3/0) */
/* 4 4,0   */

/* CMPA.W #<data>.W,An */
void REGPARAM2 op_b0fc_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 27;
	CurrentInstrCycles = 10; 
	uae_s16 src = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	SET_NFLG(flgn != 0);
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	do_cycles_ce000_internal(2);
	m68k_incpci(4);
	return;
}
/* 10 (2/0) */
/* 4 0,0   */

/* EOR.B Dn,Dn */
void REGPARAM2 op_b100_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 3;
	CurrentInstrCycles = 4;  
	uae_s8 src = m68k_dreg(regs, srcreg);
	uae_s8 dst = m68k_dreg(regs, dstreg);
	src ^= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 4 (1/0) */
/* 2 0,0   */

/* CMPM.B (An)+,(An)+ */
void REGPARAM2 op_b108_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 26;
	CurrentInstrCycles = 12; 
	ipl_fetch_now();
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, srcreg) += areg_byteinc[srcreg] + 0;
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
	uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 12 (3/0) */
/* 2 0,0   */

/* EOR.B Dn,(An) */
void REGPARAM2 op_b110_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 3;
	CurrentInstrCycles = 12; 
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	src ^= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_byte(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 12 (2/1) */
/* 2 0,0   */

/* EOR.B Dn,(An)+ */
void REGPARAM2 op_b118_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 3;
	CurrentInstrCycles = 12; 
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
	src ^= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_byte(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 12 (2/1) */
/* 2 0,0   */

/* EOR.B Dn,-(An) */
void REGPARAM2 op_b120_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 3;
	CurrentInstrCycles = 14; 
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
	do_cycles_ce000_internal(2);
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, dstreg) = dsta;
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	m68k_areg(regs, dstreg) = dsta;
	src ^= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_byte(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 14 (2/1) */
/* 2 0,0   */

/* EOR.B Dn,(d16,An) */
void REGPARAM2 op_b128_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 3;
	CurrentInstrCycles = 16; 
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	src ^= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_byte(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* EOR.B Dn,(d8,An,Xn) */
void REGPARAM2 op_b130_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 3;
	CurrentInstrCycles = 18; 
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	do_cycles_ce000_internal(2);
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	src ^= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_byte(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 18 (3/1) */
/* 4 4,0   */

/* EOR.B Dn,(xxx).W */
void REGPARAM2 op_b138_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	OpcodeFamily = 3;
	CurrentInstrCycles = 16; 
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	src ^= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_byte(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* EOR.B Dn,(xxx).L */
void REGPARAM2 op_b139_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	OpcodeFamily = 3;
	CurrentInstrCycles = 20; 
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	dsta |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	src ^= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_byte(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 20 (4/1) */
/* 6 0,0   */

/* EOR.W Dn,Dn */
void REGPARAM2 op_b140_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 3;
	CurrentInstrCycles = 4;  
	uae_s16 src = m68k_dreg(regs, srcreg);
	uae_s16 dst = m68k_dreg(regs, dstreg);
	src ^= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 4 (1/0) */
/* 2 0,0   */

/* CMPM.W (An)+,(An)+ */
void REGPARAM2 op_b148_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 26;
	CurrentInstrCycles = 12; 
	ipl_fetch_now();
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, srcreg) += 2 + 0;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	m68k_areg(regs, srcreg) += 2;
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	if (dsta & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, dsta, 1, 1);
		return;
	}
	uae_s16 dst = x_get_word(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, dstreg) += 2 + 0;
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	m68k_areg(regs, dstreg) += 2;
	uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 12 (3/0) */
/* 2 0,0   */

/* EOR.W Dn,(An) */
void REGPARAM2 op_b150_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 3;
	CurrentInstrCycles = 12; 
	uae_s16 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	if (dsta & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dsta, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 dst = x_get_word(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	src ^= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_word(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 12 (2/1) */
/* 2 0,0   */

/* EOR.W Dn,(An)+ */
void REGPARAM2 op_b158_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 3;
	CurrentInstrCycles = 12; 
	uae_s16 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	if (dsta & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dsta, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 dst = x_get_word(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, dstreg) += 2 + 0;
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	m68k_areg(regs, dstreg) += 2;
	src ^= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_word(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 12 (2/1) */
/* 2 0,0   */

/* EOR.W Dn,-(An) */
void REGPARAM2 op_b160_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 3;
	CurrentInstrCycles = 14; 
	uae_s16 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - 2;
	do_cycles_ce000_internal(2);
	if (dsta & 1) {
		m68k_incpci(4);
		m68k_areg(regs, dstreg) = dsta;
		exception3_read_access(opcode, dsta, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 dst = x_get_word(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, dstreg) = dsta;
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	m68k_areg(regs, dstreg) = dsta;
	src ^= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_word(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 14 (2/1) */
/* 2 0,0   */

/* EOR.W Dn,(d16,An) */
void REGPARAM2 op_b168_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 3;
	CurrentInstrCycles = 16; 
	uae_s16 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dsta, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 dst = x_get_word(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	src ^= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_word(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* EOR.W Dn,(d8,An,Xn) */
void REGPARAM2 op_b170_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 3;
	CurrentInstrCycles = 18; 
	uae_s16 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	do_cycles_ce000_internal(2);
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dsta, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 dst = x_get_word(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	src ^= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_word(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 18 (3/1) */
/* 4 4,0   */

/* EOR.W Dn,(xxx).W */
void REGPARAM2 op_b178_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	OpcodeFamily = 3;
	CurrentInstrCycles = 16; 
	uae_s16 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, dsta, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 dst = x_get_word(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	src ^= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_word(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* EOR.W Dn,(xxx).L */
void REGPARAM2 op_b179_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	OpcodeFamily = 3;
	CurrentInstrCycles = 20; 
	uae_s16 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	dsta |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, dsta, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 dst = x_get_word(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	src ^= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_word(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 20 (4/1) */
/* 6 0,0   */

/* EOR.L Dn,Dn */
void REGPARAM2 op_b180_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 3;
	CurrentInstrCycles = 8;  
	uae_s32 src = m68k_dreg(regs, srcreg);
	uae_s32 dst = m68k_dreg(regs, dstreg);
	src ^= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		dreg_68000_long_replace_low(dstreg, src);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	do_cycles_ce000_internal(4);
	m68k_dreg(regs, dstreg) = (src);
	m68k_incpci(2);
	return;
}
/* 8 (1/0) */
/* 2 0,0   */

/* CMPM.L (An)+,(An)+ */
void REGPARAM2 op_b188_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 26;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, srcreg) += 2 + 0;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, srcreg) += 2 + 2;
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	m68k_areg(regs, srcreg) += 4;
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	if (dsta & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, dsta, 2, 1);
		return;
	}
	uae_s32 dst = x_get_word(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	dst |= x_get_word(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return;
	}
	m68k_areg(regs, dstreg) += 4;
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 20 (5/0) */
/* 2 0,0   */

/* EOR.L Dn,(An) */
void REGPARAM2 op_b190_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 3;
	CurrentInstrCycles = 20; 
	uae_s32 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	if (dsta & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dsta, 2, 1);
		return;
	}
	uae_s32 dst = x_get_word(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	dst |= x_get_word(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return;
	}
	src ^= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	x_put_word(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return;
	}
	x_put_word(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 20 (3/2) */
/* 2 0,0   */

/* EOR.L Dn,(An)+ */
void REGPARAM2 op_b198_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 3;
	CurrentInstrCycles = 20; 
	uae_s32 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	if (dsta & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dsta, 2, 1);
		return;
	}
	uae_s32 dst = x_get_word(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	dst |= x_get_word(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return;
	}
	m68k_areg(regs, dstreg) += 4;
	src ^= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	x_put_word(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return;
	}
	x_put_word(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 20 (3/2) */
/* 2 0,0   */

/* EOR.L Dn,-(An) */
void REGPARAM2 op_b1a0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 3;
	CurrentInstrCycles = 22; 
	uae_s32 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - 4;
	do_cycles_ce000_internal(2);
	if (dsta & 1) {
		m68k_incpci(2);
		m68k_areg(regs, dstreg) = dsta;
		exception3_read_access(opcode, dsta, 2, 1);
		return;
	}
	uae_s32 dst = x_get_word(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, dstreg) = dsta;
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	dst |= x_get_word(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, dstreg) = dsta;
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return;
	}
	m68k_areg(regs, dstreg) = dsta;
	src ^= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	x_put_word(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return;
	}
	x_put_word(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 22 (3/2) */
/* 2 0,0   */

/* EOR.L Dn,(d16,An) */
void REGPARAM2 op_b1a8_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 3;
	CurrentInstrCycles = 24; 
	uae_s32 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dsta, 2, 1);
		return;
	}
	uae_s32 dst = x_get_word(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	dst |= x_get_word(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return;
	}
	src ^= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	x_put_word(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return;
	}
	x_put_word(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 24 (4/2) */
/* 4 0,0   */

/* EOR.L Dn,(d8,An,Xn) */
void REGPARAM2 op_b1b0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 3;
	CurrentInstrCycles = 26; 
	uae_s32 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	do_cycles_ce000_internal(2);
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dsta, 2, 1);
		return;
	}
	uae_s32 dst = x_get_word(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	dst |= x_get_word(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return;
	}
	src ^= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	x_put_word(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return;
	}
	x_put_word(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 26 (4/2) */
/* 4 4,0   */

/* EOR.L Dn,(xxx).W */
void REGPARAM2 op_b1b8_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	OpcodeFamily = 3;
	CurrentInstrCycles = 24; 
	uae_s32 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, dsta, 2, 1);
		return;
	}
	uae_s32 dst = x_get_word(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	dst |= x_get_word(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return;
	}
	src ^= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	x_put_word(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return;
	}
	x_put_word(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 24 (4/2) */
/* 4 0,0   */

/* EOR.L Dn,(xxx).L */
void REGPARAM2 op_b1b9_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	OpcodeFamily = 3;
	CurrentInstrCycles = 28; 
	uae_s32 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	dsta |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, dsta, 2, 1);
		return;
	}
	uae_s32 dst = x_get_word(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	dst |= x_get_word(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return;
	}
	src ^= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	x_put_word(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return;
	}
	x_put_word(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 28 (5/2) */
/* 6 0,0   */

/* CMPA.L Dn,An */
void REGPARAM2 op_b1c0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 27;
	CurrentInstrCycles = 6;  
	uae_s32 src = m68k_dreg(regs, srcreg);
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	SET_NFLG(flgn != 0);
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	do_cycles_ce000_internal(2);
	m68k_incpci(2);
	return;
}
/* 6 (1/0) */
/* 2 0,0   */

/* CMPA.L An,An */
void REGPARAM2 op_b1c8_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 27;
	CurrentInstrCycles = 6;  
	uae_s32 src = m68k_areg(regs, srcreg);
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	SET_NFLG(flgn != 0);
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	do_cycles_ce000_internal(2);
	m68k_incpci(2);
	return;
}
/* 6 (1/0) */
/* 2 0,0   */

/* CMPA.L (An),An */
void REGPARAM2 op_b1d0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 27;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	SET_NFLG(flgn != 0);
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	do_cycles_ce000_internal(2);
	m68k_incpci(2);
	return;
}
/* 14 (3/0) */
/* 2 0,0   */

/* CMPA.L (An)+,An */
void REGPARAM2 op_b1d8_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 27;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	m68k_areg(regs, srcreg) += 4;
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	SET_NFLG(flgn != 0);
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	do_cycles_ce000_internal(2);
	m68k_incpci(2);
	return;
}
/* 14 (3/0) */
/* 2 0,0   */

/* CMPA.L -(An),An */
void REGPARAM2 op_b1e0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 27;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - 4;
	do_cycles_ce000_internal(2);
	if (srca & 1) {
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	m68k_areg(regs, srcreg) = srca;
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	SET_NFLG(flgn != 0);
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	do_cycles_ce000_internal(2);
	m68k_incpci(2);
	return;
}
/* 16 (3/0) */
/* 2 0,0   */

/* CMPA.L (d16,An),An */
void REGPARAM2 op_b1e8_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 27;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	SET_NFLG(flgn != 0);
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	do_cycles_ce000_internal(2);
	m68k_incpci(4);
	return;
}
/* 18 (4/0) */
/* 4 0,0   */

/* CMPA.L (d8,An,Xn),An */
void REGPARAM2 op_b1f0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 27;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	do_cycles_ce000_internal(2);
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	SET_NFLG(flgn != 0);
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	do_cycles_ce000_internal(2);
	m68k_incpci(4);
	return;
}
/* 20 (4/0) */
/* 4 4,0   */

/* CMPA.L (xxx).W,An */
void REGPARAM2 op_b1f8_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 27;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	if (srca & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	SET_NFLG(flgn != 0);
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	do_cycles_ce000_internal(2);
	m68k_incpci(4);
	return;
}
/* 18 (4/0) */
/* 4 0,0   */

/* CMPA.L (xxx).L,An */
void REGPARAM2 op_b1f9_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 27;
	CurrentInstrCycles = 22; 
	uaecptr srca;
	srca = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	srca |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	if (srca & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	SET_NFLG(flgn != 0);
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	opcode = regs.ir;
	do_cycles_ce000_internal(2);
	m68k_incpci(6);
	return;
}
/* 22 (5/0) */
/* 6 0,0   */

/* CMPA.L (d16,PC),An */
void REGPARAM2 op_b1fa_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 27;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	srca = m68k_getpci() + 2;
	srca += (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 2);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return;
	}
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 2);
		return;
	}
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	SET_NFLG(flgn != 0);
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	do_cycles_ce000_internal(2);
	m68k_incpci(4);
	return;
}
/* 18 (4/0) */
/* 4 0,0   */

/* CMPA.L (d8,PC,Xn),An */
void REGPARAM2 op_b1fb_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 27;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	uaecptr tmppc = m68k_getpci() + 2;
	do_cycles_ce000_internal(2);
	srca = get_disp_ea_000(tmppc, get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 2);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return;
	}
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 2);
		return;
	}
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	SET_NFLG(flgn != 0);
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	do_cycles_ce000_internal(2);
	m68k_incpci(4);
	return;
}
/* 20 (4/0) */
/* 4 4,0   */

/* CMPA.L #<data>.L,An */
void REGPARAM2 op_b1fc_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 27;
	CurrentInstrCycles = 14; 
	uae_s32 src;
	src = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	src |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs != flgo) && (flgn != flgo));
	SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
	SET_NFLG(flgn != 0);
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	opcode = regs.ir;
	do_cycles_ce000_internal(2);
	m68k_incpci(6);
	return;
}
/* 14 (3/0) */
/* 6 0,0   */

/* AND.B Dn,Dn */
void REGPARAM2 op_c000_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 4;  
	uae_s8 src = m68k_dreg(regs, srcreg);
	uae_s8 dst = m68k_dreg(regs, dstreg);
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 4 (1/0) */
/* 2 0,0   */

/* AND.B (An),Dn */
void REGPARAM2 op_c010_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 8;  
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	uae_s8 dst = m68k_dreg(regs, dstreg);
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 8 (2/0) */
/* 2 0,0   */

/* AND.B (An)+,Dn */
void REGPARAM2 op_c018_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 8;  
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
	uae_s8 dst = m68k_dreg(regs, dstreg);
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 8 (2/0) */
/* 2 0,0   */

/* AND.B -(An),Dn */
void REGPARAM2 op_c020_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 10; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
	do_cycles_ce000_internal(2);
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	m68k_areg(regs, srcreg) = srca;
	uae_s8 dst = m68k_dreg(regs, dstreg);
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 10 (2/0) */
/* 2 0,0   */

/* AND.B (d16,An),Dn */
void REGPARAM2 op_c028_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	uae_s8 dst = m68k_dreg(regs, dstreg);
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 12 (3/0) */
/* 4 0,0   */

/* AND.B (d8,An,Xn),Dn */
void REGPARAM2 op_c030_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	do_cycles_ce000_internal(2);
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	uae_s8 dst = m68k_dreg(regs, dstreg);
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 14 (3/0) */
/* 4 4,0   */

/* AND.B (xxx).W,Dn */
void REGPARAM2 op_c038_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	uae_s8 dst = m68k_dreg(regs, dstreg);
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 12 (3/0) */
/* 4 0,0   */

/* AND.B (xxx).L,Dn */
void REGPARAM2 op_c039_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	srca |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	uae_s8 dst = m68k_dreg(regs, dstreg);
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 16 (4/0) */
/* 6 0,0   */

/* AND.B (d16,PC),Dn */
void REGPARAM2 op_c03a_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_getpci() + 2;
	srca += (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 2);
		return;
	}
	uae_s8 dst = m68k_dreg(regs, dstreg);
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 12 (3/0) */
/* 4 0,0   */

/* AND.B (d8,PC,Xn),Dn */
void REGPARAM2 op_c03b_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	uaecptr tmppc = m68k_getpci() + 2;
	do_cycles_ce000_internal(2);
	srca = get_disp_ea_000(tmppc, get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 2);
		return;
	}
	uae_s8 dst = m68k_dreg(regs, dstreg);
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 14 (3/0) */
/* 4 4,0   */

/* AND.B #<data>.B,Dn */
void REGPARAM2 op_c03c_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 8;  
	uae_s8 src = (uae_u8)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uae_s8 dst = m68k_dreg(regs, dstreg);
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 8 (2/0) */
/* 4 0,0   */

/* AND.W Dn,Dn */
void REGPARAM2 op_c040_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 4;  
	uae_s16 src = m68k_dreg(regs, srcreg);
	uae_s16 dst = m68k_dreg(regs, dstreg);
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 4 (1/0) */
/* 2 0,0   */

/* AND.W (An),Dn */
void REGPARAM2 op_c050_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 8;  
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 8 (2/0) */
/* 2 0,0   */

/* AND.W (An)+,Dn */
void REGPARAM2 op_c058_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 8;  
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) += 2 + 0;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	m68k_areg(regs, srcreg) += 2;
	uae_s16 dst = m68k_dreg(regs, dstreg);
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 8 (2/0) */
/* 2 0,0   */

/* AND.W -(An),Dn */
void REGPARAM2 op_c060_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 10; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - 2;
	do_cycles_ce000_internal(2);
	if (srca & 1) {
		m68k_incpci(4);
		m68k_areg(regs, srcreg) = srca;
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	m68k_areg(regs, srcreg) = srca;
	uae_s16 dst = m68k_dreg(regs, dstreg);
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 10 (2/0) */
/* 2 0,0   */

/* AND.W (d16,An),Dn */
void REGPARAM2 op_c068_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 12 (3/0) */
/* 4 0,0   */

/* AND.W (d8,An,Xn),Dn */
void REGPARAM2 op_c070_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	do_cycles_ce000_internal(2);
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 14 (3/0) */
/* 4 4,0   */

/* AND.W (xxx).W,Dn */
void REGPARAM2 op_c078_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	if (srca & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 12 (3/0) */
/* 4 0,0   */

/* AND.W (xxx).L,Dn */
void REGPARAM2 op_c079_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	srca |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	if (srca & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 16 (4/0) */
/* 6 0,0   */

/* AND.W (d16,PC),Dn */
void REGPARAM2 op_c07a_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_getpci() + 2;
	srca += (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 2);
		return;
	}
	ipl_fetch_now();
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 12 (3/0) */
/* 4 0,0   */

/* AND.W (d8,PC,Xn),Dn */
void REGPARAM2 op_c07b_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	uaecptr tmppc = m68k_getpci() + 2;
	do_cycles_ce000_internal(2);
	srca = get_disp_ea_000(tmppc, get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 2);
		return;
	}
	ipl_fetch_now();
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 14 (3/0) */
/* 4 4,0   */

/* AND.W #<data>.W,Dn */
void REGPARAM2 op_c07c_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 8;  
	uae_s16 src = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 8 (2/0) */
/* 4 0,0   */

/* AND.L Dn,Dn */
void REGPARAM2 op_c080_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 8;  
	uae_s32 src = m68k_dreg(regs, srcreg);
	uae_s32 dst = m68k_dreg(regs, dstreg);
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		dreg_68000_long_replace_low(dstreg, src);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	do_cycles_ce000_internal(4);
	m68k_dreg(regs, dstreg) = (src);
	m68k_incpci(2);
	return;
}
/* 8 (1/0) */
/* 2 0,0   */

/* AND.L (An),Dn */
void REGPARAM2 op_c090_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		dreg_68000_long_replace_low(dstreg, src);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	do_cycles_ce000_internal(2);
	m68k_dreg(regs, dstreg) = (src);
	m68k_incpci(2);
	return;
}
/* 14 (3/0) */
/* 2 0,0   */

/* AND.L (An)+,Dn */
void REGPARAM2 op_c098_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	m68k_areg(regs, srcreg) += 4;
	uae_s32 dst = m68k_dreg(regs, dstreg);
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		dreg_68000_long_replace_low(dstreg, src);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	do_cycles_ce000_internal(2);
	m68k_dreg(regs, dstreg) = (src);
	m68k_incpci(2);
	return;
}
/* 14 (3/0) */
/* 2 0,0   */

/* AND.L -(An),Dn */
void REGPARAM2 op_c0a0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - 4;
	do_cycles_ce000_internal(2);
	if (srca & 1) {
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	m68k_areg(regs, srcreg) = srca;
	uae_s32 dst = m68k_dreg(regs, dstreg);
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		dreg_68000_long_replace_low(dstreg, src);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	do_cycles_ce000_internal(2);
	m68k_dreg(regs, dstreg) = (src);
	m68k_incpci(2);
	return;
}
/* 16 (3/0) */
/* 2 0,0   */

/* AND.L (d16,An),Dn */
void REGPARAM2 op_c0a8_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		dreg_68000_long_replace_low(dstreg, src);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	do_cycles_ce000_internal(2);
	m68k_dreg(regs, dstreg) = (src);
	m68k_incpci(4);
	return;
}
/* 18 (4/0) */
/* 4 0,0   */

/* AND.L (d8,An,Xn),Dn */
void REGPARAM2 op_c0b0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	do_cycles_ce000_internal(2);
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		dreg_68000_long_replace_low(dstreg, src);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	do_cycles_ce000_internal(2);
	m68k_dreg(regs, dstreg) = (src);
	m68k_incpci(4);
	return;
}
/* 20 (4/0) */
/* 4 4,0   */

/* AND.L (xxx).W,Dn */
void REGPARAM2 op_c0b8_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	if (srca & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		dreg_68000_long_replace_low(dstreg, src);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	do_cycles_ce000_internal(2);
	m68k_dreg(regs, dstreg) = (src);
	m68k_incpci(4);
	return;
}
/* 18 (4/0) */
/* 4 0,0   */

/* AND.L (xxx).L,Dn */
void REGPARAM2 op_c0b9_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 22; 
	uaecptr srca;
	srca = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	srca |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	if (srca & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		dreg_68000_long_replace_low(dstreg, src);
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	opcode = regs.ir;
	do_cycles_ce000_internal(2);
	m68k_dreg(regs, dstreg) = (src);
	m68k_incpci(6);
	return;
}
/* 22 (5/0) */
/* 6 0,0   */

/* AND.L (d16,PC),Dn */
void REGPARAM2 op_c0ba_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	srca = m68k_getpci() + 2;
	srca += (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 2);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return;
	}
	ipl_fetch_now();
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 2);
		return;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		dreg_68000_long_replace_low(dstreg, src);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	do_cycles_ce000_internal(2);
	m68k_dreg(regs, dstreg) = (src);
	m68k_incpci(4);
	return;
}
/* 18 (4/0) */
/* 4 0,0   */

/* AND.L (d8,PC,Xn),Dn */
void REGPARAM2 op_c0bb_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	uaecptr tmppc = m68k_getpci() + 2;
	do_cycles_ce000_internal(2);
	srca = get_disp_ea_000(tmppc, get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 2);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return;
	}
	ipl_fetch_now();
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 2);
		return;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		dreg_68000_long_replace_low(dstreg, src);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	do_cycles_ce000_internal(2);
	m68k_dreg(regs, dstreg) = (src);
	m68k_incpci(4);
	return;
}
/* 20 (4/0) */
/* 4 4,0   */

/* AND.L #<data>.L,Dn */
void REGPARAM2 op_c0bc_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 16; 
	uae_s32 src;
	src = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	src |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		dreg_68000_long_replace_low(dstreg, src);
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	opcode = regs.ir;
	do_cycles_ce000_internal(4);
	m68k_dreg(regs, dstreg) = (src);
	m68k_incpci(6);
	return;
}
/* 16 (3/0) */
/* 6 0,0   */

/* MULU.W Dn,Dn */
void REGPARAM2 op_c0c0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 62;
	CurrentInstrCycles = 4;  
	uae_s16 src = m68k_dreg(regs, srcreg);
	uae_s16 dst = m68k_dreg(regs, dstreg);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	ipl_fetch_next();
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();
		SET_ZFLG(1);
		pcoffset -= 2;
		m68k_dreg(regs, dstreg) &= 0xffff0000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	uae_u32 newv = (uae_u32)(uae_u16)dst * (uae_u32)(uae_u16)src;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_NFLG(((uae_s32)(newv)) < 0);
	int cycles = getMulu68kCycles(src);
	do_cycles_ce000_internal(cycles);
	m68k_dreg(regs, dstreg) = (newv);
	m68k_incpci(2);
	return;
}
/* 4+ (1/0) */
/* 2 0,0   */

/* MULU.W (An),Dn */
void REGPARAM2 op_c0d0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 62;
	CurrentInstrCycles = 8;  
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();
		SET_ZFLG(1);
		pcoffset -= 2;
		m68k_dreg(regs, dstreg) &= 0xffff0000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	uae_u32 newv = (uae_u32)(uae_u16)dst * (uae_u32)(uae_u16)src;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_NFLG(((uae_s32)(newv)) < 0);
	int cycles = getMulu68kCycles(src);
	do_cycles_ce000_internal(cycles);
	m68k_dreg(regs, dstreg) = (newv);
	m68k_incpci(2);
	return;
}
/* 8+ (2/0) */
/* 2 0,0   */

/* MULU.W (An)+,Dn */
void REGPARAM2 op_c0d8_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 62;
	CurrentInstrCycles = 8;  
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) += 2 + 0;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	m68k_areg(regs, srcreg) += 2;
	uae_s16 dst = m68k_dreg(regs, dstreg);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();
		SET_ZFLG(1);
		pcoffset -= 2;
		m68k_dreg(regs, dstreg) &= 0xffff0000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	uae_u32 newv = (uae_u32)(uae_u16)dst * (uae_u32)(uae_u16)src;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_NFLG(((uae_s32)(newv)) < 0);
	int cycles = getMulu68kCycles(src);
	do_cycles_ce000_internal(cycles);
	m68k_dreg(regs, dstreg) = (newv);
	m68k_incpci(2);
	return;
}
/* 8+ (2/0) */
/* 2 0,0   */

/* MULU.W -(An),Dn */
void REGPARAM2 op_c0e0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 62;
	CurrentInstrCycles = 10; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - 2;
	do_cycles_ce000_internal(2);
	if (srca & 1) {
		m68k_incpci(4);
		m68k_areg(regs, srcreg) = srca;
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	m68k_areg(regs, srcreg) = srca;
	uae_s16 dst = m68k_dreg(regs, dstreg);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();
		SET_ZFLG(1);
		pcoffset -= 0;
		m68k_dreg(regs, dstreg) &= 0xffff0000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	uae_u32 newv = (uae_u32)(uae_u16)dst * (uae_u32)(uae_u16)src;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_NFLG(((uae_s32)(newv)) < 0);
	int cycles = getMulu68kCycles(src);
	do_cycles_ce000_internal(cycles);
	m68k_dreg(regs, dstreg) = (newv);
	m68k_incpci(2);
	return;
}
/* 10+ (2/0) */
/* 2 0,0   */

/* MULU.W (d16,An),Dn */
void REGPARAM2 op_c0e8_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 62;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();
		SET_ZFLG(1);
		pcoffset -= 4;
		m68k_dreg(regs, dstreg) &= 0xffff0000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	uae_u32 newv = (uae_u32)(uae_u16)dst * (uae_u32)(uae_u16)src;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_NFLG(((uae_s32)(newv)) < 0);
	int cycles = getMulu68kCycles(src);
	do_cycles_ce000_internal(cycles);
	m68k_dreg(regs, dstreg) = (newv);
	m68k_incpci(4);
	return;
}
/* 12+ (3/0) */
/* 4 0,0   */

/* MULU.W (d8,An,Xn),Dn */
void REGPARAM2 op_c0f0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 62;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	do_cycles_ce000_internal(2);
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();
		SET_ZFLG(1);
		pcoffset -= 4;
		m68k_dreg(regs, dstreg) &= 0xffff0000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	uae_u32 newv = (uae_u32)(uae_u16)dst * (uae_u32)(uae_u16)src;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_NFLG(((uae_s32)(newv)) < 0);
	int cycles = getMulu68kCycles(src);
	do_cycles_ce000_internal(cycles);
	m68k_dreg(regs, dstreg) = (newv);
	m68k_incpci(4);
	return;
}
/* 14+ (3/0) */
/* 4 4,0   */

/* MULU.W (xxx).W,Dn */
void REGPARAM2 op_c0f8_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 62;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	if (srca & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();
		SET_ZFLG(1);
		pcoffset -= 2;
		m68k_dreg(regs, dstreg) &= 0xffff0000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	uae_u32 newv = (uae_u32)(uae_u16)dst * (uae_u32)(uae_u16)src;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_NFLG(((uae_s32)(newv)) < 0);
	int cycles = getMulu68kCycles(src);
	do_cycles_ce000_internal(cycles);
	m68k_dreg(regs, dstreg) = (newv);
	m68k_incpci(4);
	return;
}
/* 12+ (3/0) */
/* 4 0,0   */

/* MULU.W (xxx).L,Dn */
void REGPARAM2 op_c0f9_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 62;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	srca |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	if (srca & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();
		SET_ZFLG(1);
		pcoffset -= 2;
		m68k_dreg(regs, dstreg) &= 0xffff0000;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	opcode = regs.ir;
	uae_u32 newv = (uae_u32)(uae_u16)dst * (uae_u32)(uae_u16)src;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_NFLG(((uae_s32)(newv)) < 0);
	int cycles = getMulu68kCycles(src);
	do_cycles_ce000_internal(cycles);
	m68k_dreg(regs, dstreg) = (newv);
	m68k_incpci(6);
	return;
}
/* 16+ (4/0) */
/* 6 0,0   */

/* MULU.W (d16,PC),Dn */
void REGPARAM2 op_c0fa_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 62;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_getpci() + 2;
	srca += (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 2);
		return;
	}
	ipl_fetch_now();
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();
		SET_ZFLG(1);
		pcoffset -= 4;
		m68k_dreg(regs, dstreg) &= 0xffff0000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	uae_u32 newv = (uae_u32)(uae_u16)dst * (uae_u32)(uae_u16)src;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_NFLG(((uae_s32)(newv)) < 0);
	int cycles = getMulu68kCycles(src);
	do_cycles_ce000_internal(cycles);
	m68k_dreg(regs, dstreg) = (newv);
	m68k_incpci(4);
	return;
}
/* 12+ (3/0) */
/* 4 0,0   */

/* MULU.W (d8,PC,Xn),Dn */
void REGPARAM2 op_c0fb_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 62;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	uaecptr tmppc = m68k_getpci() + 2;
	do_cycles_ce000_internal(2);
	srca = get_disp_ea_000(tmppc, get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 2);
		return;
	}
	ipl_fetch_now();
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();
		SET_ZFLG(1);
		pcoffset -= 4;
		m68k_dreg(regs, dstreg) &= 0xffff0000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	uae_u32 newv = (uae_u32)(uae_u16)dst * (uae_u32)(uae_u16)src;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_NFLG(((uae_s32)(newv)) < 0);
	int cycles = getMulu68kCycles(src);
	do_cycles_ce000_internal(cycles);
	m68k_dreg(regs, dstreg) = (newv);
	m68k_incpci(4);
	return;
}
/* 14+ (3/0) */
/* 4 4,0   */

/* MULU.W #<data>.W,Dn */
void REGPARAM2 op_c0fc_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 62;
	CurrentInstrCycles = 8;  
	uae_s16 src = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	ipl_fetch_next();
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();
		SET_ZFLG(1);
		pcoffset -= 2;
		m68k_dreg(regs, dstreg) &= 0xffff0000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	uae_u32 newv = (uae_u32)(uae_u16)dst * (uae_u32)(uae_u16)src;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_NFLG(((uae_s32)(newv)) < 0);
	int cycles = getMulu68kCycles(src);
	do_cycles_ce000_internal(cycles);
	m68k_dreg(regs, dstreg) = (newv);
	m68k_incpci(4);
	return;
}
/* 8+ (2/0) */
/* 4 0,0   */

/* ABCD.B Dn,Dn */
void REGPARAM2 op_c100_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 14;
	CurrentInstrCycles = 6;  
	uae_s8 src = m68k_dreg(regs, srcreg);
	uae_s8 dst = m68k_dreg(regs, dstreg);
	uae_u16 newv_lo = (src & 0xF) + (dst & 0xF) + (GET_XFLG() ? 1 : 0);
	uae_u16 newv_hi = (src & 0xF0) + (dst & 0xF0);
	uae_u16 newv, tmp_newv;
	int cflg;
	newv = tmp_newv = newv_hi + newv_lo;if (newv_lo > 9) { newv += 6; }
	cflg = (newv & 0x3F0) > 0x90;
	if (cflg) newv += 0x60;
	SET_CFLG(cflg);
	COPY_CARRY();
	SET_ZFLG(GET_ZFLG() & (((uae_s8)(newv)) == 0));
	SET_NFLG(((uae_s8)(newv)) < 0);
	SET_VFLG((tmp_newv & 0x80) == 0 && (newv & 0x80) != 0);
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	do_cycles_ce000_internal(2);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
	m68k_incpci(2);
	return;
}
/* 6 (1/0) */
/* 2 0,0   */

/* ABCD.B -(An),-(An) */
void REGPARAM2 op_c108_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 14;
	CurrentInstrCycles = 18; 
	do_cycles_ce000_internal(2);
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	m68k_areg(regs, srcreg) = srca;
	ipl_fetch_next_pre();
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, dstreg) = dsta;
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	m68k_areg(regs, dstreg) = dsta;
	uae_u16 newv_lo = (src & 0xF) + (dst & 0xF) + (GET_XFLG() ? 1 : 0);
	uae_u16 newv_hi = (src & 0xF0) + (dst & 0xF0);
	uae_u16 newv, tmp_newv;
	int cflg;
	newv = tmp_newv = newv_hi + newv_lo;if (newv_lo > 9) { newv += 6; }
	cflg = (newv & 0x3F0) > 0x90;
	if (cflg) newv += 0x60;
	SET_CFLG(cflg);
	COPY_CARRY();
	SET_ZFLG(GET_ZFLG() & (((uae_s8)(newv)) == 0));
	SET_NFLG(((uae_s8)(newv)) < 0);
	SET_VFLG((tmp_newv & 0x80) == 0 && (newv & 0x80) != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_byte(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, newv, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 18 (3/1) */
/* 2 0,0   */

/* AND.B Dn,(An) */
void REGPARAM2 op_c110_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 12; 
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_byte(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 12 (2/1) */
/* 2 0,0   */

/* AND.B Dn,(An)+ */
void REGPARAM2 op_c118_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 12; 
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_byte(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 12 (2/1) */
/* 2 0,0   */

/* AND.B Dn,-(An) */
void REGPARAM2 op_c120_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 14; 
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
	do_cycles_ce000_internal(2);
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, dstreg) = dsta;
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	m68k_areg(regs, dstreg) = dsta;
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_byte(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 14 (2/1) */
/* 2 0,0   */

/* AND.B Dn,(d16,An) */
void REGPARAM2 op_c128_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 16; 
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_byte(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* AND.B Dn,(d8,An,Xn) */
void REGPARAM2 op_c130_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 18; 
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	do_cycles_ce000_internal(2);
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_byte(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 18 (3/1) */
/* 4 4,0   */

/* AND.B Dn,(xxx).W */
void REGPARAM2 op_c138_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	OpcodeFamily = 2;
	CurrentInstrCycles = 16; 
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_byte(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* AND.B Dn,(xxx).L */
void REGPARAM2 op_c139_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	OpcodeFamily = 2;
	CurrentInstrCycles = 20; 
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	dsta |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s8)(src)) == 0);
	SET_NFLG(((uae_s8)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_byte(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, src, 1);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 20 (4/1) */
/* 6 0,0   */

/* EXG.L Dn,Dn */
void REGPARAM2 op_c140_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 35;
	CurrentInstrCycles = 6;  
	uae_s32 src = m68k_dreg(regs, srcreg);
	uae_s32 dst = m68k_dreg(regs, dstreg);
	m68k_dreg(regs, srcreg) = (dst);
	m68k_dreg(regs, dstreg) = (src);
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	do_cycles_ce000_internal(2);
	m68k_incpci(2);
	return;
}
/* 6 (1/0) */
/* 2 0,0   */

/* EXG.L An,An */
void REGPARAM2 op_c148_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 35;
	CurrentInstrCycles = 6;  
	uae_s32 src = m68k_areg(regs, srcreg);
	uae_s32 dst = m68k_areg(regs, dstreg);
	m68k_areg(regs, srcreg) = (dst);
	m68k_areg(regs, dstreg) = (src);
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	do_cycles_ce000_internal(2);
	m68k_incpci(2);
	return;
}
/* 6 (1/0) */
/* 2 0,0   */

/* AND.W Dn,(An) */
void REGPARAM2 op_c150_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 12; 
	uae_s16 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	if (dsta & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dsta, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 dst = x_get_word(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_word(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 12 (2/1) */
/* 2 0,0   */

/* AND.W Dn,(An)+ */
void REGPARAM2 op_c158_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 12; 
	uae_s16 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	if (dsta & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dsta, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 dst = x_get_word(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, dstreg) += 2 + 0;
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	m68k_areg(regs, dstreg) += 2;
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_word(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 12 (2/1) */
/* 2 0,0   */

/* AND.W Dn,-(An) */
void REGPARAM2 op_c160_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 14; 
	uae_s16 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - 2;
	do_cycles_ce000_internal(2);
	if (dsta & 1) {
		m68k_incpci(4);
		m68k_areg(regs, dstreg) = dsta;
		exception3_read_access(opcode, dsta, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 dst = x_get_word(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, dstreg) = dsta;
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	m68k_areg(regs, dstreg) = dsta;
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_word(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 14 (2/1) */
/* 2 0,0   */

/* AND.W Dn,(d16,An) */
void REGPARAM2 op_c168_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 16; 
	uae_s16 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dsta, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 dst = x_get_word(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_word(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* AND.W Dn,(d8,An,Xn) */
void REGPARAM2 op_c170_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 18; 
	uae_s16 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	do_cycles_ce000_internal(2);
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dsta, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 dst = x_get_word(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_word(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 18 (3/1) */
/* 4 4,0   */

/* AND.W Dn,(xxx).W */
void REGPARAM2 op_c178_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	OpcodeFamily = 2;
	CurrentInstrCycles = 16; 
	uae_s16 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, dsta, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 dst = x_get_word(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_word(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* AND.W Dn,(xxx).L */
void REGPARAM2 op_c179_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	OpcodeFamily = 2;
	CurrentInstrCycles = 20; 
	uae_s16 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	dsta |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, dsta, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 dst = x_get_word(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(src)) == 0);
	SET_NFLG(((uae_s16)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_word(dsta, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x1, src, 1);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 20 (4/1) */
/* 6 0,0   */

/* EXG.L Dn,An */
void REGPARAM2 op_c188_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 35;
	CurrentInstrCycles = 6;  
	uae_s32 src = m68k_dreg(regs, srcreg);
	uae_s32 dst = m68k_areg(regs, dstreg);
	m68k_dreg(regs, srcreg) = (dst);
	m68k_areg(regs, dstreg) = (src);
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	do_cycles_ce000_internal(2);
	m68k_incpci(2);
	return;
}
/* 6 (1/0) */
/* 2 0,0   */

/* AND.L Dn,(An) */
void REGPARAM2 op_c190_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 20; 
	uae_s32 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	if (dsta & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dsta, 2, 1);
		return;
	}
	uae_s32 dst = x_get_word(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	dst |= x_get_word(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return;
	}
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	x_put_word(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return;
	}
	x_put_word(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 20 (3/2) */
/* 2 0,0   */

/* AND.L Dn,(An)+ */
void REGPARAM2 op_c198_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 20; 
	uae_s32 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	if (dsta & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dsta, 2, 1);
		return;
	}
	uae_s32 dst = x_get_word(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	dst |= x_get_word(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return;
	}
	m68k_areg(regs, dstreg) += 4;
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	x_put_word(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return;
	}
	x_put_word(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 20 (3/2) */
/* 2 0,0   */

/* AND.L Dn,-(An) */
void REGPARAM2 op_c1a0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 22; 
	uae_s32 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - 4;
	do_cycles_ce000_internal(2);
	if (dsta & 1) {
		m68k_incpci(2);
		m68k_areg(regs, dstreg) = dsta;
		exception3_read_access(opcode, dsta, 2, 1);
		return;
	}
	uae_s32 dst = x_get_word(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, dstreg) = dsta;
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	dst |= x_get_word(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, dstreg) = dsta;
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return;
	}
	m68k_areg(regs, dstreg) = dsta;
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	x_put_word(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return;
	}
	x_put_word(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 22 (3/2) */
/* 2 0,0   */

/* AND.L Dn,(d16,An) */
void REGPARAM2 op_c1a8_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 24; 
	uae_s32 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dsta, 2, 1);
		return;
	}
	uae_s32 dst = x_get_word(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	dst |= x_get_word(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return;
	}
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	x_put_word(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return;
	}
	x_put_word(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 24 (4/2) */
/* 4 0,0   */

/* AND.L Dn,(d8,An,Xn) */
void REGPARAM2 op_c1b0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 2;
	CurrentInstrCycles = 26; 
	uae_s32 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	do_cycles_ce000_internal(2);
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dsta, 2, 1);
		return;
	}
	uae_s32 dst = x_get_word(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	dst |= x_get_word(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return;
	}
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	x_put_word(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return;
	}
	x_put_word(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 26 (4/2) */
/* 4 4,0   */

/* AND.L Dn,(xxx).W */
void REGPARAM2 op_c1b8_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	OpcodeFamily = 2;
	CurrentInstrCycles = 24; 
	uae_s32 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, dsta, 2, 1);
		return;
	}
	uae_s32 dst = x_get_word(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	dst |= x_get_word(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return;
	}
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	x_put_word(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return;
	}
	x_put_word(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 24 (4/2) */
/* 4 0,0   */

/* AND.L Dn,(xxx).L */
void REGPARAM2 op_c1b9_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	OpcodeFamily = 2;
	CurrentInstrCycles = 28; 
	uae_s32 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	dsta |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, dsta, 2, 1);
		return;
	}
	uae_s32 dst = x_get_word(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	dst |= x_get_word(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return;
	}
	src &= dst;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(src)) == 0);
	SET_NFLG(((uae_s32)(src)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		ccr_68000_long_move_ae_LZN(src);
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	x_put_word(dsta + 2, src);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 2, 0x1, src, 1);
		return;
	}
	x_put_word(dsta, src >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 0, 0x1, src >> 16, 1);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 28 (5/2) */
/* 6 0,0   */

/* MULS.W Dn,Dn */
void REGPARAM2 op_c1c0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 63;
	CurrentInstrCycles = 4;  
	uae_s16 src = m68k_dreg(regs, srcreg);
	uae_s16 dst = m68k_dreg(regs, dstreg);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	ipl_fetch_next();
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();
		SET_ZFLG(1);
		pcoffset -= 2;
		m68k_dreg(regs, dstreg) &= 0xffff0000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	uae_u32 newv = (uae_s32)(uae_s16)dst * (uae_s32)(uae_s16)src;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_NFLG(((uae_s32)(newv)) < 0);
	int cycles = getMuls68kCycles(src);
	do_cycles_ce000_internal(cycles);
	m68k_dreg(regs, dstreg) = (newv);
	m68k_incpci(2);
	return;
}
/* 4+ (1/0) */
/* 2 0,0   */

/* MULS.W (An),Dn */
void REGPARAM2 op_c1d0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 63;
	CurrentInstrCycles = 8;  
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();
		SET_ZFLG(1);
		pcoffset -= 2;
		m68k_dreg(regs, dstreg) &= 0xffff0000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	uae_u32 newv = (uae_s32)(uae_s16)dst * (uae_s32)(uae_s16)src;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_NFLG(((uae_s32)(newv)) < 0);
	int cycles = getMuls68kCycles(src);
	do_cycles_ce000_internal(cycles);
	m68k_dreg(regs, dstreg) = (newv);
	m68k_incpci(2);
	return;
}
/* 8+ (2/0) */
/* 2 0,0   */

/* MULS.W (An)+,Dn */
void REGPARAM2 op_c1d8_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 63;
	CurrentInstrCycles = 8;  
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) += 2 + 0;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	m68k_areg(regs, srcreg) += 2;
	uae_s16 dst = m68k_dreg(regs, dstreg);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();
		SET_ZFLG(1);
		pcoffset -= 2;
		m68k_dreg(regs, dstreg) &= 0xffff0000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	uae_u32 newv = (uae_s32)(uae_s16)dst * (uae_s32)(uae_s16)src;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_NFLG(((uae_s32)(newv)) < 0);
	int cycles = getMuls68kCycles(src);
	do_cycles_ce000_internal(cycles);
	m68k_dreg(regs, dstreg) = (newv);
	m68k_incpci(2);
	return;
}
/* 8+ (2/0) */
/* 2 0,0   */

/* MULS.W -(An),Dn */
void REGPARAM2 op_c1e0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 63;
	CurrentInstrCycles = 10; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - 2;
	do_cycles_ce000_internal(2);
	if (srca & 1) {
		m68k_incpci(4);
		m68k_areg(regs, srcreg) = srca;
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	m68k_areg(regs, srcreg) = srca;
	uae_s16 dst = m68k_dreg(regs, dstreg);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();
		SET_ZFLG(1);
		pcoffset -= 0;
		m68k_dreg(regs, dstreg) &= 0xffff0000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	uae_u32 newv = (uae_s32)(uae_s16)dst * (uae_s32)(uae_s16)src;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_NFLG(((uae_s32)(newv)) < 0);
	int cycles = getMuls68kCycles(src);
	do_cycles_ce000_internal(cycles);
	m68k_dreg(regs, dstreg) = (newv);
	m68k_incpci(2);
	return;
}
/* 10+ (2/0) */
/* 2 0,0   */

/* MULS.W (d16,An),Dn */
void REGPARAM2 op_c1e8_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 63;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();
		SET_ZFLG(1);
		pcoffset -= 4;
		m68k_dreg(regs, dstreg) &= 0xffff0000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	uae_u32 newv = (uae_s32)(uae_s16)dst * (uae_s32)(uae_s16)src;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_NFLG(((uae_s32)(newv)) < 0);
	int cycles = getMuls68kCycles(src);
	do_cycles_ce000_internal(cycles);
	m68k_dreg(regs, dstreg) = (newv);
	m68k_incpci(4);
	return;
}
/* 12+ (3/0) */
/* 4 0,0   */

/* MULS.W (d8,An,Xn),Dn */
void REGPARAM2 op_c1f0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 63;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	do_cycles_ce000_internal(2);
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();
		SET_ZFLG(1);
		pcoffset -= 4;
		m68k_dreg(regs, dstreg) &= 0xffff0000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	uae_u32 newv = (uae_s32)(uae_s16)dst * (uae_s32)(uae_s16)src;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_NFLG(((uae_s32)(newv)) < 0);
	int cycles = getMuls68kCycles(src);
	do_cycles_ce000_internal(cycles);
	m68k_dreg(regs, dstreg) = (newv);
	m68k_incpci(4);
	return;
}
/* 14+ (3/0) */
/* 4 4,0   */

/* MULS.W (xxx).W,Dn */
void REGPARAM2 op_c1f8_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 63;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	if (srca & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();
		SET_ZFLG(1);
		pcoffset -= 2;
		m68k_dreg(regs, dstreg) &= 0xffff0000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	uae_u32 newv = (uae_s32)(uae_s16)dst * (uae_s32)(uae_s16)src;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_NFLG(((uae_s32)(newv)) < 0);
	int cycles = getMuls68kCycles(src);
	do_cycles_ce000_internal(cycles);
	m68k_dreg(regs, dstreg) = (newv);
	m68k_incpci(4);
	return;
}
/* 12+ (3/0) */
/* 4 0,0   */

/* MULS.W (xxx).L,Dn */
void REGPARAM2 op_c1f9_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 63;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	srca |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	if (srca & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();
		SET_ZFLG(1);
		pcoffset -= 2;
		m68k_dreg(regs, dstreg) &= 0xffff0000;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	opcode = regs.ir;
	uae_u32 newv = (uae_s32)(uae_s16)dst * (uae_s32)(uae_s16)src;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_NFLG(((uae_s32)(newv)) < 0);
	int cycles = getMuls68kCycles(src);
	do_cycles_ce000_internal(cycles);
	m68k_dreg(regs, dstreg) = (newv);
	m68k_incpci(6);
	return;
}
/* 16+ (4/0) */
/* 6 0,0   */

/* MULS.W (d16,PC),Dn */
void REGPARAM2 op_c1fa_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 63;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_getpci() + 2;
	srca += (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 2);
		return;
	}
	ipl_fetch_now();
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();
		SET_ZFLG(1);
		pcoffset -= 4;
		m68k_dreg(regs, dstreg) &= 0xffff0000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	uae_u32 newv = (uae_s32)(uae_s16)dst * (uae_s32)(uae_s16)src;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_NFLG(((uae_s32)(newv)) < 0);
	int cycles = getMuls68kCycles(src);
	do_cycles_ce000_internal(cycles);
	m68k_dreg(regs, dstreg) = (newv);
	m68k_incpci(4);
	return;
}
/* 12+ (3/0) */
/* 4 0,0   */

/* MULS.W (d8,PC,Xn),Dn */
void REGPARAM2 op_c1fb_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 63;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	uaecptr tmppc = m68k_getpci() + 2;
	do_cycles_ce000_internal(2);
	srca = get_disp_ea_000(tmppc, get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 2);
		return;
	}
	ipl_fetch_now();
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();
		SET_ZFLG(1);
		pcoffset -= 4;
		m68k_dreg(regs, dstreg) &= 0xffff0000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	uae_u32 newv = (uae_s32)(uae_s16)dst * (uae_s32)(uae_s16)src;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_NFLG(((uae_s32)(newv)) < 0);
	int cycles = getMuls68kCycles(src);
	do_cycles_ce000_internal(cycles);
	m68k_dreg(regs, dstreg) = (newv);
	m68k_incpci(4);
	return;
}
/* 14+ (3/0) */
/* 4 4,0   */

/* MULS.W #<data>.W,Dn */
void REGPARAM2 op_c1fc_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 63;
	CurrentInstrCycles = 8;  
	uae_s16 src = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	ipl_fetch_next();
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();
		SET_ZFLG(1);
		pcoffset -= 2;
		m68k_dreg(regs, dstreg) &= 0xffff0000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	uae_u32 newv = (uae_s32)(uae_s16)dst * (uae_s32)(uae_s16)src;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_NFLG(((uae_s32)(newv)) < 0);
	int cycles = getMuls68kCycles(src);
	do_cycles_ce000_internal(cycles);
	m68k_dreg(regs, dstreg) = (newv);
	m68k_incpci(4);
	return;
}
/* 8+ (2/0) */
/* 4 0,0   */

/* ADD.B Dn,Dn */
void REGPARAM2 op_d000_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 4;  
	uae_s8 src = m68k_dreg(regs, srcreg);
	uae_s8 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u8)(~dst)) < ((uae_u8)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 4 (1/0) */
/* 2 0,0   */

/* ADD.B (An),Dn */
void REGPARAM2 op_d010_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 8;  
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	uae_s8 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u8)(~dst)) < ((uae_u8)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 8 (2/0) */
/* 2 0,0   */

/* ADD.B (An)+,Dn */
void REGPARAM2 op_d018_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 8;  
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
	uae_s8 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u8)(~dst)) < ((uae_u8)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 8 (2/0) */
/* 2 0,0   */

/* ADD.B -(An),Dn */
void REGPARAM2 op_d020_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 10; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
	do_cycles_ce000_internal(2);
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	m68k_areg(regs, srcreg) = srca;
	uae_s8 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u8)(~dst)) < ((uae_u8)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 10 (2/0) */
/* 2 0,0   */

/* ADD.B (d16,An),Dn */
void REGPARAM2 op_d028_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	uae_s8 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u8)(~dst)) < ((uae_u8)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 12 (3/0) */
/* 4 0,0   */

/* ADD.B (d8,An,Xn),Dn */
void REGPARAM2 op_d030_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	do_cycles_ce000_internal(2);
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	uae_s8 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u8)(~dst)) < ((uae_u8)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 14 (3/0) */
/* 4 4,0   */

/* ADD.B (xxx).W,Dn */
void REGPARAM2 op_d038_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	uae_s8 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u8)(~dst)) < ((uae_u8)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 12 (3/0) */
/* 4 0,0   */

/* ADD.B (xxx).L,Dn */
void REGPARAM2 op_d039_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	srca |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	uae_s8 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u8)(~dst)) < ((uae_u8)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 16 (4/0) */
/* 6 0,0   */

/* ADD.B (d16,PC),Dn */
void REGPARAM2 op_d03a_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_getpci() + 2;
	srca += (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 2);
		return;
	}
	uae_s8 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u8)(~dst)) < ((uae_u8)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 12 (3/0) */
/* 4 0,0   */

/* ADD.B (d8,PC,Xn),Dn */
void REGPARAM2 op_d03b_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	uaecptr tmppc = m68k_getpci() + 2;
	do_cycles_ce000_internal(2);
	srca = get_disp_ea_000(tmppc, get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	ipl_fetch_now();
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x0, 2);
		return;
	}
	uae_s8 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u8)(~dst)) < ((uae_u8)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 14 (3/0) */
/* 4 4,0   */

/* ADD.B #<data>.B,Dn */
void REGPARAM2 op_d03c_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 8;  
	uae_s8 src = (uae_u8)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uae_s8 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u8)(~dst)) < ((uae_u8)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 8 (2/0) */
/* 4 0,0   */

/* ADD.W Dn,Dn */
void REGPARAM2 op_d040_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 4;  
	uae_s16 src = m68k_dreg(regs, srcreg);
	uae_s16 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 4 (1/0) */
/* 2 0,0   */

/* ADD.W An,Dn */
void REGPARAM2 op_d048_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 4;  
	uae_s16 src = m68k_areg(regs, srcreg);
	uae_s16 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 4 (1/0) */
/* 2 0,0   */

/* ADD.W (An),Dn */
void REGPARAM2 op_d050_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 8;  
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 8 (2/0) */
/* 2 0,0   */

/* ADD.W (An)+,Dn */
void REGPARAM2 op_d058_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 8;  
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) += 2 + 0;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	m68k_areg(regs, srcreg) += 2;
	uae_s16 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 8 (2/0) */
/* 2 0,0   */

/* ADD.W -(An),Dn */
void REGPARAM2 op_d060_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 10; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - 2;
	do_cycles_ce000_internal(2);
	if (srca & 1) {
		m68k_incpci(4);
		m68k_areg(regs, srcreg) = srca;
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	m68k_areg(regs, srcreg) = srca;
	uae_s16 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 10 (2/0) */
/* 2 0,0   */

/* ADD.W (d16,An),Dn */
void REGPARAM2 op_d068_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 12 (3/0) */
/* 4 0,0   */

/* ADD.W (d8,An,Xn),Dn */
void REGPARAM2 op_d070_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	do_cycles_ce000_internal(2);
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 14 (3/0) */
/* 4 4,0   */

/* ADD.W (xxx).W,Dn */
void REGPARAM2 op_d078_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	if (srca & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 12 (3/0) */
/* 4 0,0   */

/* ADD.W (xxx).L,Dn */
void REGPARAM2 op_d079_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	srca |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	if (srca & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 16 (4/0) */
/* 6 0,0   */

/* ADD.W (d16,PC),Dn */
void REGPARAM2 op_d07a_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_getpci() + 2;
	srca += (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 2);
		return;
	}
	ipl_fetch_now();
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 12 (3/0) */
/* 4 0,0   */

/* ADD.W (d8,PC,Xn),Dn */
void REGPARAM2 op_d07b_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	uaecptr tmppc = m68k_getpci() + 2;
	do_cycles_ce000_internal(2);
	srca = get_disp_ea_000(tmppc, get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 2);
		return;
	}
	ipl_fetch_now();
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 14 (3/0) */
/* 4 4,0   */

/* ADD.W #<data>.W,Dn */
void REGPARAM2 op_d07c_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 8;  
	uae_s16 src = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uae_s16 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 8 (2/0) */
/* 4 0,0   */

/* ADD.L Dn,Dn */
void REGPARAM2 op_d080_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 8;  
	uae_s32 src = m68k_dreg(regs, srcreg);
	uae_s32 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u32)(~dst)) < ((uae_u32)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		uae_s16 bnewv = (uae_s16)dst + (uae_s16)src;
		int bflgs = ((uae_s16)(src)) < 0;
		int bflgo = ((uae_s16)(dst)) < 0;
		int bflgn = bnewv < 0;
		ccr_68000_long_move_ae_LZN(bnewv);
		SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
		SET_XFLG(GET_CFLG());
		SET_VFLG((bflgs ^ bflgn) & (bflgo ^ bflgn));
		dreg_68000_long_replace_low(dstreg, bnewv);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	do_cycles_ce000_internal(4);
	m68k_dreg(regs, dstreg) = (newv);
	m68k_incpci(2);
	return;
}
/* 8 (1/0) */
/* 2 0,0   */

/* ADD.L An,Dn */
void REGPARAM2 op_d088_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 8;  
	uae_s32 src = m68k_areg(regs, srcreg);
	uae_s32 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u32)(~dst)) < ((uae_u32)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		uae_s16 bnewv = (uae_s16)dst + (uae_s16)src;
		int bflgs = ((uae_s16)(src)) < 0;
		int bflgo = ((uae_s16)(dst)) < 0;
		int bflgn = bnewv < 0;
		ccr_68000_long_move_ae_LZN(bnewv);
		SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
		SET_XFLG(GET_CFLG());
		SET_VFLG((bflgs ^ bflgn) & (bflgo ^ bflgn));
		dreg_68000_long_replace_low(dstreg, bnewv);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	do_cycles_ce000_internal(4);
	m68k_dreg(regs, dstreg) = (newv);
	m68k_incpci(2);
	return;
}
/* 8 (1/0) */
/* 2 0,0   */

/* ADD.L (An),Dn */
void REGPARAM2 op_d090_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u32)(~dst)) < ((uae_u32)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		dreg_68000_long_replace_low(dstreg, newv);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	do_cycles_ce000_internal(2);
	m68k_dreg(regs, dstreg) = (newv);
	m68k_incpci(2);
	return;
}
/* 14 (3/0) */
/* 2 0,0   */

/* ADD.L (An)+,Dn */
void REGPARAM2 op_d098_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	m68k_areg(regs, srcreg) += 4;
	uae_s32 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u32)(~dst)) < ((uae_u32)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		dreg_68000_long_replace_low(dstreg, newv);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	do_cycles_ce000_internal(2);
	m68k_dreg(regs, dstreg) = (newv);
	m68k_incpci(2);
	return;
}
/* 14 (3/0) */
/* 2 0,0   */

/* ADD.L -(An),Dn */
void REGPARAM2 op_d0a0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - 4;
	do_cycles_ce000_internal(2);
	if (srca & 1) {
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	m68k_areg(regs, srcreg) = srca;
	uae_s32 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u32)(~dst)) < ((uae_u32)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		dreg_68000_long_replace_low(dstreg, newv);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	do_cycles_ce000_internal(2);
	m68k_dreg(regs, dstreg) = (newv);
	m68k_incpci(2);
	return;
}
/* 16 (3/0) */
/* 2 0,0   */

/* ADD.L (d16,An),Dn */
void REGPARAM2 op_d0a8_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u32)(~dst)) < ((uae_u32)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		dreg_68000_long_replace_low(dstreg, newv);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	do_cycles_ce000_internal(2);
	m68k_dreg(regs, dstreg) = (newv);
	m68k_incpci(4);
	return;
}
/* 18 (4/0) */
/* 4 0,0   */

/* ADD.L (d8,An,Xn),Dn */
void REGPARAM2 op_d0b0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	do_cycles_ce000_internal(2);
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u32)(~dst)) < ((uae_u32)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		dreg_68000_long_replace_low(dstreg, newv);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	do_cycles_ce000_internal(2);
	m68k_dreg(regs, dstreg) = (newv);
	m68k_incpci(4);
	return;
}
/* 20 (4/0) */
/* 4 4,0   */

/* ADD.L (xxx).W,Dn */
void REGPARAM2 op_d0b8_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	if (srca & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u32)(~dst)) < ((uae_u32)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		dreg_68000_long_replace_low(dstreg, newv);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	do_cycles_ce000_internal(2);
	m68k_dreg(regs, dstreg) = (newv);
	m68k_incpci(4);
	return;
}
/* 18 (4/0) */
/* 4 0,0   */

/* ADD.L (xxx).L,Dn */
void REGPARAM2 op_d0b9_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 22; 
	uaecptr srca;
	srca = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	srca |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	if (srca & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u32)(~dst)) < ((uae_u32)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		dreg_68000_long_replace_low(dstreg, newv);
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	opcode = regs.ir;
	do_cycles_ce000_internal(2);
	m68k_dreg(regs, dstreg) = (newv);
	m68k_incpci(6);
	return;
}
/* 22 (5/0) */
/* 6 0,0   */

/* ADD.L (d16,PC),Dn */
void REGPARAM2 op_d0ba_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	srca = m68k_getpci() + 2;
	srca += (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 2);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return;
	}
	ipl_fetch_now();
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 2);
		return;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u32)(~dst)) < ((uae_u32)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		dreg_68000_long_replace_low(dstreg, newv);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	do_cycles_ce000_internal(2);
	m68k_dreg(regs, dstreg) = (newv);
	m68k_incpci(4);
	return;
}
/* 18 (4/0) */
/* 4 0,0   */

/* ADD.L (d8,PC,Xn),Dn */
void REGPARAM2 op_d0bb_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	uaecptr tmppc = m68k_getpci() + 2;
	do_cycles_ce000_internal(2);
	srca = get_disp_ea_000(tmppc, get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 2);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return;
	}
	ipl_fetch_now();
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 2);
		return;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u32)(~dst)) < ((uae_u32)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		dreg_68000_long_replace_low(dstreg, newv);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	do_cycles_ce000_internal(2);
	m68k_dreg(regs, dstreg) = (newv);
	m68k_incpci(4);
	return;
}
/* 20 (4/0) */
/* 4 4,0   */

/* ADD.L #<data>.L,Dn */
void REGPARAM2 op_d0bc_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 16; 
	uae_s32 src;
	src = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	ipl_fetch_now();
	src |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	uae_s32 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u32)(~dst)) < ((uae_u32)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		uae_s16 bnewv = (uae_s16)dst + (uae_s16)src;
		int bflgs = ((uae_s16)(src)) < 0;
		int bflgo = ((uae_s16)(dst)) < 0;
		int bflgn = bnewv < 0;
		ccr_68000_long_move_ae_LZN(bnewv);
		SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
		SET_XFLG(GET_CFLG());
		SET_VFLG((bflgs ^ bflgn) & (bflgo ^ bflgn));
		dreg_68000_long_replace_low(dstreg, bnewv);
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	opcode = regs.ir;
	do_cycles_ce000_internal(4);
	m68k_dreg(regs, dstreg) = (newv);
	m68k_incpci(6);
	return;
}
/* 16 (3/0) */
/* 6 0,0   */

/* ADDA.W Dn,An */
void REGPARAM2 op_d0c0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 12;
	CurrentInstrCycles = 8;  
	uae_s16 src = m68k_dreg(regs, srcreg);
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = dst + src;
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		areg_68000_long_replace_low(dstreg, newv);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	do_cycles_ce000_internal(4);
	m68k_areg(regs, dstreg) = (newv);
	m68k_incpci(2);
	return;
}
/* 8 (1/0) */
/* 2 0,0   */

/* ADDA.W An,An */
void REGPARAM2 op_d0c8_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 12;
	CurrentInstrCycles = 8;  
	uae_s16 src = m68k_areg(regs, srcreg);
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = dst + src;
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		areg_68000_long_replace_low(dstreg, newv);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	do_cycles_ce000_internal(4);
	m68k_areg(regs, dstreg) = (newv);
	m68k_incpci(2);
	return;
}
/* 8 (1/0) */
/* 2 0,0   */

/* ADDA.W (An),An */
void REGPARAM2 op_d0d0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 12;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = dst + src;
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		areg_68000_long_replace_low(dstreg, newv);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	do_cycles_ce000_internal(4);
	m68k_areg(regs, dstreg) = (newv);
	m68k_incpci(2);
	return;
}
/* 12 (2/0) */
/* 2 0,0   */

/* ADDA.W (An)+,An */
void REGPARAM2 op_d0d8_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 12;
	CurrentInstrCycles = 12; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) += 2 + 0;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	m68k_areg(regs, srcreg) += 2;
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = dst + src;
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		areg_68000_long_replace_low(dstreg, newv);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	do_cycles_ce000_internal(4);
	m68k_areg(regs, dstreg) = (newv);
	m68k_incpci(2);
	return;
}
/* 12 (2/0) */
/* 2 0,0   */

/* ADDA.W -(An),An */
void REGPARAM2 op_d0e0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 12;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - 2;
	do_cycles_ce000_internal(2);
	if (srca & 1) {
		m68k_incpci(4);
		m68k_areg(regs, srcreg) = srca;
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	m68k_areg(regs, srcreg) = srca;
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = dst + src;
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		areg_68000_long_replace_low(dstreg, newv);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	do_cycles_ce000_internal(4);
	m68k_areg(regs, dstreg) = (newv);
	m68k_incpci(2);
	return;
}
/* 14 (2/0) */
/* 2 0,0   */

/* ADDA.W (d16,An),An */
void REGPARAM2 op_d0e8_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 12;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = dst + src;
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		areg_68000_long_replace_low(dstreg, newv);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	do_cycles_ce000_internal(4);
	m68k_areg(regs, dstreg) = (newv);
	m68k_incpci(4);
	return;
}
/* 16 (3/0) */
/* 4 0,0   */

/* ADDA.W (d8,An,Xn),An */
void REGPARAM2 op_d0f0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 12;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	do_cycles_ce000_internal(2);
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = dst + src;
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		areg_68000_long_replace_low(dstreg, newv);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	do_cycles_ce000_internal(4);
	m68k_areg(regs, dstreg) = (newv);
	m68k_incpci(4);
	return;
}
/* 18 (3/0) */
/* 4 4,0   */

/* ADDA.W (xxx).W,An */
void REGPARAM2 op_d0f8_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 12;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	if (srca & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = dst + src;
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		areg_68000_long_replace_low(dstreg, newv);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	do_cycles_ce000_internal(4);
	m68k_areg(regs, dstreg) = (newv);
	m68k_incpci(4);
	return;
}
/* 16 (3/0) */
/* 4 0,0   */

/* ADDA.W (xxx).L,An */
void REGPARAM2 op_d0f9_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 12;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	srca = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	srca |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	if (srca & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = dst + src;
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		areg_68000_long_replace_low(dstreg, newv);
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	opcode = regs.ir;
	do_cycles_ce000_internal(4);
	m68k_areg(regs, dstreg) = (newv);
	m68k_incpci(6);
	return;
}
/* 20 (4/0) */
/* 6 0,0   */

/* ADDA.W (d16,PC),An */
void REGPARAM2 op_d0fa_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 12;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = m68k_getpci() + 2;
	srca += (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 2);
		return;
	}
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return;
	}
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = dst + src;
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		areg_68000_long_replace_low(dstreg, newv);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	do_cycles_ce000_internal(4);
	m68k_areg(regs, dstreg) = (newv);
	m68k_incpci(4);
	return;
}
/* 16 (3/0) */
/* 4 0,0   */

/* ADDA.W (d8,PC,Xn),An */
void REGPARAM2 op_d0fb_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 12;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	uaecptr tmppc = m68k_getpci() + 2;
	do_cycles_ce000_internal(2);
	srca = get_disp_ea_000(tmppc, get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 1, 2);
		return;
	}
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return;
	}
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = dst + src;
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		areg_68000_long_replace_low(dstreg, newv);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	do_cycles_ce000_internal(4);
	m68k_areg(regs, dstreg) = (newv);
	m68k_incpci(4);
	return;
}
/* 18 (3/0) */
/* 4 4,0   */

/* ADDA.W #<data>.W,An */
void REGPARAM2 op_d0fc_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 12;
	CurrentInstrCycles = 12; 
	uae_s16 src = get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = dst + src;
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		areg_68000_long_replace_low(dstreg, newv);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	do_cycles_ce000_internal(4);
	m68k_areg(regs, dstreg) = (newv);
	m68k_incpci(4);
	return;
}
/* 12 (2/0) */
/* 4 0,0   */

/* ADDX.B Dn,Dn */
void REGPARAM2 op_d100_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 13;
	CurrentInstrCycles = 4;  
	uae_s8 src = m68k_dreg(regs, srcreg);
	uae_s8 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = dst + src + (GET_XFLG() ? 1 : 0);
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(flgs ^ ((flgs ^ flgo) & (flgo ^ flgn)));
	COPY_CARRY();
	SET_ZFLG(GET_ZFLG() & (((uae_s8)(newv)) == 0));
	SET_NFLG(((uae_s8)(newv)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
	m68k_incpci(2);
	return;
}
/* 4 (1/0) */
/* 2 0,0   */

/* ADDX.B -(An),-(An) */
void REGPARAM2 op_d108_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 13;
	CurrentInstrCycles = 18; 
	do_cycles_ce000_internal(2);
	ipl_fetch_now();
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
	uae_s8 src = x_get_byte(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x0, 1);
		return;
	}
	m68k_areg(regs, srcreg) = srca;
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, dstreg) = dsta;
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	m68k_areg(regs, dstreg) = dsta;
	uae_u32 newv = dst + src + (GET_XFLG() ? 1 : 0);
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(flgs ^ ((flgs ^ flgo) & (flgo ^ flgn)));
	COPY_CARRY();
	SET_ZFLG(GET_ZFLG() & (((uae_s8)(newv)) == 0));
	SET_NFLG(((uae_s8)(newv)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_byte(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, newv, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 18 (3/1) */
/* 2 0,0   */

/* ADD.B Dn,(An) */
void REGPARAM2 op_d110_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 12; 
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u8)(~dst)) < ((uae_u8)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_byte(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, newv, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 12 (2/1) */
/* 2 0,0   */

/* ADD.B Dn,(An)+ */
void REGPARAM2 op_d118_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 12; 
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
	uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u8)(~dst)) < ((uae_u8)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_byte(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, newv, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 12 (2/1) */
/* 2 0,0   */

/* ADD.B Dn,-(An) */
void REGPARAM2 op_d120_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 14; 
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
	do_cycles_ce000_internal(2);
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, dstreg) = dsta;
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	m68k_areg(regs, dstreg) = dsta;
	uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u8)(~dst)) < ((uae_u8)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_byte(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, newv, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 14 (2/1) */
/* 2 0,0   */

/* ADD.B Dn,(d16,An) */
void REGPARAM2 op_d128_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 16; 
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u8)(~dst)) < ((uae_u8)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_byte(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, newv, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* ADD.B Dn,(d8,An,Xn) */
void REGPARAM2 op_d130_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 18; 
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	do_cycles_ce000_internal(2);
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u8)(~dst)) < ((uae_u8)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_byte(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, newv, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 18 (3/1) */
/* 4 4,0   */

/* ADD.B Dn,(xxx).W */
void REGPARAM2 op_d138_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	OpcodeFamily = 11;
	CurrentInstrCycles = 16; 
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u8)(~dst)) < ((uae_u8)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_byte(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, newv, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* ADD.B Dn,(xxx).L */
void REGPARAM2 op_d139_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	OpcodeFamily = 11;
	CurrentInstrCycles = 20; 
	uae_s8 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	dsta |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	ipl_fetch_now();
	uae_s8 dst = x_get_byte(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x0, 1);
		return;
	}
	uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
	int flgs = ((uae_s8)(src)) < 0;
	int flgo = ((uae_s8)(dst)) < 0;
	int flgn = ((uae_s8)(newv)) < 0;
	SET_ZFLG(((uae_s8)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u8)(~dst)) < ((uae_u8)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_byte(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x0, newv, 1);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 20 (4/1) */
/* 6 0,0   */

/* ADDX.W Dn,Dn */
void REGPARAM2 op_d140_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 13;
	CurrentInstrCycles = 4;  
	uae_s16 src = m68k_dreg(regs, srcreg);
	uae_s16 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = dst + src + (GET_XFLG() ? 1 : 0);
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(flgs ^ ((flgs ^ flgo) & (flgo ^ flgn)));
	COPY_CARRY();
	SET_ZFLG(GET_ZFLG() & (((uae_s16)(newv)) == 0));
	SET_NFLG(((uae_s16)(newv)) < 0);
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
	regs.ir = regs.irc;
	opcode = regs.ir;
	ipl_fetch_next();
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		if (regs.t1) opcode |= 0x10000;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
	m68k_incpci(2);
	return;
}
/* 4 (1/0) */
/* 2 0,0   */

/* ADDX.W -(An),-(An) */
void REGPARAM2 op_d148_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 13;
	CurrentInstrCycles = 18; 
	do_cycles_ce000_internal(2);
	ipl_fetch_now();
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - 2;
	if (srca & 1) {
		m68k_areg(regs, srcreg) = srca;
		m68k_incpci(4);
		exception3_read_access(opcode, srca, 1, 1);
		return;
	}
	uae_s16 src = x_get_word(srca);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	m68k_areg(regs, srcreg) = srca;
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - 2;
	if (dsta & 1) {
		m68k_areg(regs, dstreg) = dsta;
		m68k_incpci(4);
		exception3_read_access(opcode, dsta, 1, 1);
		return;
	}
	uae_s16 dst = x_get_word(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, dstreg) = dsta;
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	m68k_areg(regs, dstreg) = dsta;
	uae_u32 newv = dst + src + (GET_XFLG() ? 1 : 0);
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(flgs ^ ((flgs ^ flgo) & (flgo ^ flgn)));
	COPY_CARRY();
	SET_ZFLG(GET_ZFLG() & (((uae_s16)(newv)) == 0));
	SET_NFLG(((uae_s16)(newv)) < 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_word(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x1, newv, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 18 (3/1) */
/* 2 0,0   */

/* ADD.W Dn,(An) */
void REGPARAM2 op_d150_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 12; 
	uae_s16 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	if (dsta & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dsta, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 dst = x_get_word(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_word(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x1, newv, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 12 (2/1) */
/* 2 0,0   */

/* ADD.W Dn,(An)+ */
void REGPARAM2 op_d158_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 12; 
	uae_s16 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	if (dsta & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dsta, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 dst = x_get_word(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, dstreg) += 2 + 0;
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	m68k_areg(regs, dstreg) += 2;
	uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_word(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x1, newv, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 12 (2/1) */
/* 2 0,0   */

/* ADD.W Dn,-(An) */
void REGPARAM2 op_d160_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 14; 
	uae_s16 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - 2;
	do_cycles_ce000_internal(2);
	if (dsta & 1) {
		m68k_incpci(4);
		m68k_areg(regs, dstreg) = dsta;
		exception3_read_access(opcode, dsta, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 dst = x_get_word(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, dstreg) = dsta;
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	m68k_areg(regs, dstreg) = dsta;
	uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_word(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x1, newv, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 14 (2/1) */
/* 2 0,0   */

/* ADD.W Dn,(d16,An) */
void REGPARAM2 op_d168_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 16; 
	uae_s16 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dsta, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 dst = x_get_word(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_word(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x1, newv, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* ADD.W Dn,(d8,An,Xn) */
void REGPARAM2 op_d170_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 18; 
	uae_s16 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	do_cycles_ce000_internal(2);
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dsta, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 dst = x_get_word(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_word(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x1, newv, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 18 (3/1) */
/* 4 4,0   */

/* ADD.W Dn,(xxx).W */
void REGPARAM2 op_d178_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	OpcodeFamily = 11;
	CurrentInstrCycles = 16; 
	uae_s16 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, dsta, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 dst = x_get_word(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_word(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x1, newv, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* ADD.W Dn,(xxx).L */
void REGPARAM2 op_d179_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	OpcodeFamily = 11;
	CurrentInstrCycles = 20; 
	uae_s16 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	dsta |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, dsta, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 dst = x_get_word(dsta);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
	int flgs = ((uae_s16)(src)) < 0;
	int flgo = ((uae_s16)(dst)) < 0;
	int flgn = ((uae_s16)(newv)) < 0;
	SET_ZFLG(((uae_s16)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	opcode = regs.ir;
	x_put_word(dsta, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dsta + 0, 0x1, newv, 1);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 20 (4/1) */
/* 6 0,0   */

/* ADDX.L Dn,Dn */
void REGPARAM2 op_d180_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 13;
	CurrentInstrCycles = 8;  
	uae_s32 src = m68k_dreg(regs, srcreg);
	uae_s32 dst = m68k_dreg(regs, dstreg);
	uae_u32 newv = dst + src + (GET_XFLG() ? 1 : 0);
	int oldz = GET_ZFLG();
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(flgs ^ ((flgs ^ flgo) & (flgo ^ flgn)));
	COPY_CARRY();
	SET_ZFLG(GET_ZFLG() & (((uae_s32)(newv)) == 0));
	SET_NFLG(((uae_s32)(newv)) < 0);
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		int bflgs = ((uae_s16)(src)) < 0;
		int bflgo = ((uae_s16)(dst)) < 0;
		int bflgn = ((uae_s16)(newv)) < 0;
		SET_VFLG((bflgs ^ bflgn) & (bflgo ^ bflgn));
		SET_CFLG(bflgs ^ ((bflgs ^ bflgo) & (bflgo ^ bflgn)));
		SET_XFLG(GET_CFLG());
		SET_ZFLG(oldz);
		if (newv & 0xffff) SET_ZFLG(0);
		SET_NFLG(newv & 0x8000); 
		dreg_68000_long_replace_low(dstreg, newv);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	do_cycles_ce000_internal(4);
	m68k_dreg(regs, dstreg) = (newv);
	m68k_incpci(2);
	return;
}
/* 8 (1/0) */
/* 2 0,0   */

/* ADDX.L -(An),-(An) */
void REGPARAM2 op_d188_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 13;
	CurrentInstrCycles = 30; 
	do_cycles_ce000_internal(2);
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - 4;
	if (srca & 1) {
		m68k_incpci(4);
		srca += 2;
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	src |= x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	m68k_areg(regs, srcreg) = srca;
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - 4;
	if (dsta & 1) {
		m68k_incpci(4);
		dsta += 2;
		exception3_read_access(opcode, dsta, 2, 1);
		return;
	}
	uae_s32 dst = x_get_word(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	dst |= x_get_word(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	m68k_areg(regs, dstreg) = dsta;
	uae_u32 newv = dst + src + (GET_XFLG() ? 1 : 0);
	int oldz = GET_ZFLG();
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(flgs ^ ((flgs ^ flgo) & (flgo ^ flgn)));
	COPY_CARRY();
	SET_ZFLG(GET_ZFLG() & (((uae_s32)(newv)) == 0));
	SET_NFLG(((uae_s32)(newv)) < 0);
	x_put_word(dsta + 2, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		int bflgs = ((uae_s16)(src)) < 0;
		int bflgo = ((uae_s16)(dst)) < 0;
		int bflgn = ((uae_s16)(newv)) < 0;
		SET_VFLG((bflgs ^ bflgn) & (bflgo ^ bflgn));
		SET_CFLG(bflgs ^ ((bflgs ^ bflgo) & (bflgo ^ bflgn)));
		COPY_CARRY();
		SET_ZFLG(GET_ZFLG() & (((uae_s16)(newv)) == 0));
		SET_NFLG(((uae_s16)(newv)) < 0);
		exception2_write(opcode, dsta + 2, 0x1, newv, 1);
		return;
	}
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	x_put_word(dsta, newv >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x1, newv >> 16, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 30 (5/2) */
/* 2 0,0   */

/* ADD.L Dn,(An) */
void REGPARAM2 op_d190_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 20; 
	uae_s32 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	if (dsta & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dsta, 2, 1);
		return;
	}
	uae_s32 dst = x_get_word(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	dst |= x_get_word(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return;
	}
	uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u32)(~dst)) < ((uae_u32)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		uae_s16 bnewv = (uae_s16)dst + (uae_s16)src;
		int bflgs = ((uae_s16)(src)) < 0;
		int bflgo = ((uae_s16)(dst)) < 0;
		int bflgn = bnewv < 0;
		ccr_68000_long_move_ae_LZN(bnewv);
		SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
		SET_XFLG(GET_CFLG());
		SET_VFLG((bflgs ^ bflgn) & (bflgo ^ bflgn));
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	x_put_word(dsta + 2, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 2, 0x1, newv, 1);
		return;
	}
	x_put_word(dsta, newv >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x1, newv >> 16, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 20 (3/2) */
/* 2 0,0   */

/* ADD.L Dn,(An)+ */
void REGPARAM2 op_d198_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 20; 
	uae_s32 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg);
	if (dsta & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dsta, 2, 1);
		return;
	}
	uae_s32 dst = x_get_word(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	dst |= x_get_word(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return;
	}
	m68k_areg(regs, dstreg) += 4;
	uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u32)(~dst)) < ((uae_u32)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		uae_s16 bnewv = (uae_s16)dst + (uae_s16)src;
		int bflgs = ((uae_s16)(src)) < 0;
		int bflgo = ((uae_s16)(dst)) < 0;
		int bflgn = bnewv < 0;
		ccr_68000_long_move_ae_LZN(bnewv);
		SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
		SET_XFLG(GET_CFLG());
		SET_VFLG((bflgs ^ bflgn) & (bflgo ^ bflgn));
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	x_put_word(dsta + 2, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 2, 0x1, newv, 1);
		return;
	}
	x_put_word(dsta, newv >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x1, newv >> 16, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 20 (3/2) */
/* 2 0,0   */

/* ADD.L Dn,-(An) */
void REGPARAM2 op_d1a0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 22; 
	uae_s32 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) - 4;
	do_cycles_ce000_internal(2);
	if (dsta & 1) {
		m68k_incpci(2);
		m68k_areg(regs, dstreg) = dsta;
		exception3_read_access(opcode, dsta, 2, 1);
		return;
	}
	uae_s32 dst = x_get_word(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, dstreg) = dsta;
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	dst |= x_get_word(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, dstreg) = dsta;
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return;
	}
	m68k_areg(regs, dstreg) = dsta;
	uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u32)(~dst)) < ((uae_u32)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		uae_s16 bnewv = (uae_s16)dst + (uae_s16)src;
		int bflgs = ((uae_s16)(src)) < 0;
		int bflgo = ((uae_s16)(dst)) < 0;
		int bflgn = bnewv < 0;
		ccr_68000_long_move_ae_LZN(bnewv);
		SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
		SET_XFLG(GET_CFLG());
		SET_VFLG((bflgs ^ bflgn) & (bflgo ^ bflgn));
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	x_put_word(dsta + 2, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 2, 0x1, newv, 1);
		return;
	}
	x_put_word(dsta, newv >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_write(opcode, dsta + 0, 0x1, newv >> 16, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 22 (3/2) */
/* 2 0,0   */

/* ADD.L Dn,(d16,An) */
void REGPARAM2 op_d1a8_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 24; 
	uae_s32 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dsta, 2, 1);
		return;
	}
	uae_s32 dst = x_get_word(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	dst |= x_get_word(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return;
	}
	uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u32)(~dst)) < ((uae_u32)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		uae_s16 bnewv = (uae_s16)dst + (uae_s16)src;
		int bflgs = ((uae_s16)(src)) < 0;
		int bflgo = ((uae_s16)(dst)) < 0;
		int bflgn = bnewv < 0;
		ccr_68000_long_move_ae_LZN(bnewv);
		SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
		SET_XFLG(GET_CFLG());
		SET_VFLG((bflgs ^ bflgn) & (bflgo ^ bflgn));
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	x_put_word(dsta + 2, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 2, 0x1, newv, 1);
		return;
	}
	x_put_word(dsta, newv >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, newv >> 16, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 24 (4/2) */
/* 4 0,0   */

/* ADD.L Dn,(d8,An,Xn) */
void REGPARAM2 op_d1b0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 11;
	CurrentInstrCycles = 26; 
	uae_s32 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	do_cycles_ce000_internal(2);
	dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dsta, 2, 1);
		return;
	}
	uae_s32 dst = x_get_word(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	dst |= x_get_word(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return;
	}
	uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u32)(~dst)) < ((uae_u32)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		uae_s16 bnewv = (uae_s16)dst + (uae_s16)src;
		int bflgs = ((uae_s16)(src)) < 0;
		int bflgo = ((uae_s16)(dst)) < 0;
		int bflgn = bnewv < 0;
		ccr_68000_long_move_ae_LZN(bnewv);
		SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
		SET_XFLG(GET_CFLG());
		SET_VFLG((bflgs ^ bflgn) & (bflgo ^ bflgn));
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	x_put_word(dsta + 2, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 2, 0x1, newv, 1);
		return;
	}
	x_put_word(dsta, newv >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, newv >> 16, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 26 (4/2) */
/* 4 4,0   */

/* ADD.L Dn,(xxx).W */
void REGPARAM2 op_d1b8_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	OpcodeFamily = 11;
	CurrentInstrCycles = 24; 
	uae_s32 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, dsta, 2, 1);
		return;
	}
	uae_s32 dst = x_get_word(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	dst |= x_get_word(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return;
	}
	uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u32)(~dst)) < ((uae_u32)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		uae_s16 bnewv = (uae_s16)dst + (uae_s16)src;
		int bflgs = ((uae_s16)(src)) < 0;
		int bflgo = ((uae_s16)(dst)) < 0;
		int bflgn = bnewv < 0;
		ccr_68000_long_move_ae_LZN(bnewv);
		SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
		SET_XFLG(GET_CFLG());
		SET_VFLG((bflgs ^ bflgn) & (bflgo ^ bflgn));
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	x_put_word(dsta + 2, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 2, 0x1, newv, 1);
		return;
	}
	x_put_word(dsta, newv >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_write(opcode, dsta + 0, 0x1, newv >> 16, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 24 (4/2) */
/* 4 0,0   */

/* ADD.L Dn,(xxx).L */
void REGPARAM2 op_d1b9_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	OpcodeFamily = 11;
	CurrentInstrCycles = 28; 
	uae_s32 src = m68k_dreg(regs, srcreg);
	uaecptr dsta;
	dsta = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	dsta |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	if (dsta & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, dsta, 2, 1);
		return;
	}
	uae_s32 dst = x_get_word(dsta) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 0, 0x1, 1);
		return;
	}
	ipl_fetch_now();
	dst |= x_get_word(dsta + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dsta + 2, 0x1, 1);
		return;
	}
	uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
	int flgs = ((uae_s32)(src)) < 0;
	int flgo = ((uae_s32)(dst)) < 0;
	int flgn = ((uae_s32)(newv)) < 0;
	SET_ZFLG(((uae_s32)(newv)) == 0);
	SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
	SET_CFLG(((uae_u32)(~dst)) < ((uae_u32)(src)));
	COPY_CARRY();
	SET_NFLG(flgn != 0);
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		uae_s16 bnewv = (uae_s16)dst + (uae_s16)src;
		int bflgs = ((uae_s16)(src)) < 0;
		int bflgo = ((uae_s16)(dst)) < 0;
		int bflgn = bnewv < 0;
		ccr_68000_long_move_ae_LZN(bnewv);
		SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
		SET_XFLG(GET_CFLG());
		SET_VFLG((bflgs ^ bflgn) & (bflgo ^ bflgn));
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	x_put_word(dsta + 2, newv);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 2, 0x1, newv, 1);
		return;
	}
	x_put_word(dsta, newv >> 16);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		exception2_write(opcode, dsta + 0, 0x1, newv >> 16, 1);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 28 (5/2) */
/* 6 0,0   */

/* ADDA.L Dn,An */
void REGPARAM2 op_d1c0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 12;
	CurrentInstrCycles = 8;  
	uae_s32 src = m68k_dreg(regs, srcreg);
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = dst + src;
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		areg_68000_long_replace_low(dstreg, newv);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	do_cycles_ce000_internal(4);
	m68k_areg(regs, dstreg) = (newv);
	m68k_incpci(2);
	return;
}
/* 8 (1/0) */
/* 2 0,0   */

/* ADDA.L An,An */
void REGPARAM2 op_d1c8_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 12;
	CurrentInstrCycles = 8;  
	uae_s32 src = m68k_areg(regs, srcreg);
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = dst + src;
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		areg_68000_long_replace_low(dstreg, newv);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	do_cycles_ce000_internal(4);
	m68k_areg(regs, dstreg) = (newv);
	m68k_incpci(2);
	return;
}
/* 8 (1/0) */
/* 2 0,0   */

/* ADDA.L (An),An */
void REGPARAM2 op_d1d0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 12;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = dst + src;
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		areg_68000_long_replace_low(dstreg, newv);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	do_cycles_ce000_internal(2);
	m68k_areg(regs, dstreg) = (newv);
	m68k_incpci(2);
	return;
}
/* 14 (3/0) */
/* 2 0,0   */

/* ADDA.L (An)+,An */
void REGPARAM2 op_d1d8_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 12;
	CurrentInstrCycles = 14; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg);
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	m68k_areg(regs, srcreg) += 4;
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = dst + src;
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		areg_68000_long_replace_low(dstreg, newv);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	do_cycles_ce000_internal(2);
	m68k_areg(regs, dstreg) = (newv);
	m68k_incpci(2);
	return;
}
/* 14 (3/0) */
/* 2 0,0   */

/* ADDA.L -(An),An */
void REGPARAM2 op_d1e0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 12;
	CurrentInstrCycles = 16; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) - 4;
	do_cycles_ce000_internal(2);
	if (srca & 1) {
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) = srca;
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	m68k_areg(regs, srcreg) = srca;
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = dst + src;
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		areg_68000_long_replace_low(dstreg, newv);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	do_cycles_ce000_internal(2);
	m68k_areg(regs, dstreg) = (newv);
	m68k_incpci(2);
	return;
}
/* 16 (3/0) */
/* 2 0,0   */

/* ADDA.L (d16,An),An */
void REGPARAM2 op_d1e8_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 12;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = dst + src;
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		areg_68000_long_replace_low(dstreg, newv);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	do_cycles_ce000_internal(2);
	m68k_areg(regs, dstreg) = (newv);
	m68k_incpci(4);
	return;
}
/* 18 (4/0) */
/* 4 0,0   */

/* ADDA.L (d8,An,Xn),An */
void REGPARAM2 op_d1f0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 12;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	do_cycles_ce000_internal(2);
	srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = dst + src;
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		areg_68000_long_replace_low(dstreg, newv);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	do_cycles_ce000_internal(2);
	m68k_areg(regs, dstreg) = (newv);
	m68k_incpci(4);
	return;
}
/* 20 (4/0) */
/* 4 4,0   */

/* ADDA.L (xxx).W,An */
void REGPARAM2 op_d1f8_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 12;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	if (srca & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = dst + src;
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		areg_68000_long_replace_low(dstreg, newv);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	do_cycles_ce000_internal(2);
	m68k_areg(regs, dstreg) = (newv);
	m68k_incpci(4);
	return;
}
/* 18 (4/0) */
/* 4 0,0   */

/* ADDA.L (xxx).L,An */
void REGPARAM2 op_d1f9_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 12;
	CurrentInstrCycles = 22; 
	uaecptr srca;
	srca = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	srca |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	if (srca & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, srca, 2, 1);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 0, 0x1, 1);
		return;
	}
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, srca + 2, 0x1, 1);
		return;
	}
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = dst + src;
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		areg_68000_long_replace_low(dstreg, newv);
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	opcode = regs.ir;
	do_cycles_ce000_internal(2);
	m68k_areg(regs, dstreg) = (newv);
	m68k_incpci(6);
	return;
}
/* 22 (5/0) */
/* 6 0,0   */

/* ADDA.L (d16,PC),An */
void REGPARAM2 op_d1fa_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 12;
	CurrentInstrCycles = 18; 
	uaecptr srca;
	srca = m68k_getpci() + 2;
	srca += (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 2);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return;
	}
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 2);
		return;
	}
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = dst + src;
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		areg_68000_long_replace_low(dstreg, newv);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	do_cycles_ce000_internal(2);
	m68k_areg(regs, dstreg) = (newv);
	m68k_incpci(4);
	return;
}
/* 18 (4/0) */
/* 4 0,0   */

/* ADDA.L (d8,PC,Xn),An */
void REGPARAM2 op_d1fb_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 12;
	CurrentInstrCycles = 20; 
	uaecptr srca;
	uaecptr tmppc = m68k_getpci() + 2;
	do_cycles_ce000_internal(2);
	srca = get_disp_ea_000(tmppc, get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (srca & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, srca, 2, 2);
		return;
	}
	uae_s32 src = x_get_word(srca) << 16;
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 0, 0x1, 2);
		return;
	}
	src |= x_get_word(srca + 2);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, srca + 2, 0x1, 2);
		return;
	}
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = dst + src;
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		areg_68000_long_replace_low(dstreg, newv);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	do_cycles_ce000_internal(2);
	m68k_areg(regs, dstreg) = (newv);
	m68k_incpci(4);
	return;
}
/* 20 (4/0) */
/* 4 4,0   */

/* ADDA.L #<data>.L,An */
void REGPARAM2 op_d1fc_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 dstreg = (real_opcode >> 9) & 7;
	OpcodeFamily = 12;
	CurrentInstrCycles = 16; 
	uae_s32 src;
	src = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	src |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	uae_s32 dst = m68k_areg(regs, dstreg);
	uae_u32 newv = dst + src;
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		areg_68000_long_replace_low(dstreg, newv);
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	opcode = regs.ir;
	do_cycles_ce000_internal(4);
	m68k_areg(regs, dstreg) = (newv);
	m68k_incpci(6);
	return;
}
/* 16 (3/0) */
/* 6 0,0   */

/* ASRQ.B #<data>,Dn */
void REGPARAM2 op_e000_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 64;
	CurrentInstrCycles = 6;  
	uae_u32 cnt = srcreg;
	uae_s8 data = m68k_dreg(regs, dstreg);
	uae_u32 val = (uae_u8)data;
	CLEAR_CZNV();
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		SET_ZFLG(!(val & 0xff));
		SET_NFLG(val & 0x80);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	uae_u32 sign = (0x80 & val) >> 7;
	int ccnt = cnt & 63;
	cnt &= 63;
	if (cnt >= 8) {
		val = 0xff & (uae_u32)(0 - sign);
		SET_CFLG(sign);
		COPY_CARRY();
	} else {
		val >>= cnt - 1;
		SET_CFLG(val & 1);
		COPY_CARRY();
		val >>= 1;
		val |= (0xff << (8 - cnt)) & (uae_u32)(0 - sign);
		val &= 0xff;
	}
	SET_ZFLG(((uae_s8)(val)) == 0);
	SET_NFLG(((uae_s8)(val)) < 0);
	{
		int cycles = 2;
		cycles += 2 * ccnt;
		do_cycles_ce000_internal(cycles);
	}
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((val) & 0xff);
	m68k_incpci(2);
	return;
}
/* 6+ (1/0) */
/* 2 0,0   */

/* LSRQ.B #<data>,Dn */
void REGPARAM2 op_e008_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 66;
	CurrentInstrCycles = 6;  
	uae_u32 cnt = srcreg;
	uae_s8 data = m68k_dreg(regs, dstreg);
	uae_u32 val = (uae_u8)data;
	CLEAR_CZNV();
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		SET_ZFLG(!(val & 0xff));
		SET_NFLG(val & 0x80);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	int ccnt = cnt & 63;
	cnt &= 63;
	if (cnt >= 8) {
		SET_CFLG((cnt == 8) & (val >> 7));
		COPY_CARRY();
		val = 0;
	} else {
		val >>= cnt - 1;
		SET_CFLG(val & 1);
		COPY_CARRY();
		val >>= 1;
	}
	SET_ZFLG(((uae_s8)(val)) == 0);
	SET_NFLG(((uae_s8)(val)) < 0);
	{
		int cycles = 2;
		cycles += 2 * ccnt;
		do_cycles_ce000_internal(cycles);
	}
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((val) & 0xff);
	m68k_incpci(2);
	return;
}
/* 6+ (1/0) */
/* 2 0,0   */

/* ROXRQ.B #<data>,Dn */
void REGPARAM2 op_e010_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 71;
	CurrentInstrCycles = 6;  
	uae_u32 cnt = srcreg;
	uae_s8 data = m68k_dreg(regs, dstreg);
	uae_u32 val = (uae_u8)data;
	CLEAR_CZNV();
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		SET_ZFLG(!(val & 0xff));
		SET_NFLG(val & 0x80);
		SET_CFLG(GET_XFLG());
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	int ccnt = cnt & 63;
	cnt &= 63;
	{
		cnt--;
		{
			uae_u32 carry;
			uae_u32 hival = (val << 1) | GET_XFLG();
			hival <<= (7 - cnt);
			val >>= cnt;
			carry = val & 1;
			val >>= 1;
			val |= hival;
			SET_XFLG(carry);
			val &= 0xff;
		}
	}
	SET_CFLG(GET_XFLG());
	SET_ZFLG(((uae_s8)(val)) == 0);
	SET_NFLG(((uae_s8)(val)) < 0);
	{
		int cycles = 2;
		cycles += 2 * ccnt;
		do_cycles_ce000_internal(cycles);
	}
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((val) & 0xff);
	m68k_incpci(2);
	return;
}
/* 6+ (1/0) */
/* 2 0,0   */

/* RORQ.B #<data>,Dn */
void REGPARAM2 op_e018_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 69;
	CurrentInstrCycles = 6;  
	uae_u32 cnt = srcreg;
	uae_s8 data = m68k_dreg(regs, dstreg);
	uae_u32 val = (uae_u8)data;
	CLEAR_CZNV();
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		SET_ZFLG(!(val & 0xff));
		SET_NFLG(val & 0x80);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	int ccnt = cnt & 63;
	cnt &= 63;
	{
		uae_u32 hival;
		cnt &= 7;
		hival = val << (8 - cnt);
		val >>= cnt;
		val |= hival;
		val &= 0xff;
		SET_CFLG((val & 0x80) >> 7);
	}
	SET_ZFLG(((uae_s8)(val)) == 0);
	SET_NFLG(((uae_s8)(val)) < 0);
	{
		int cycles = 2;
		cycles += 2 * ccnt;
		do_cycles_ce000_internal(cycles);
	}
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((val) & 0xff);
	m68k_incpci(2);
	return;
}
/* 6+ (1/0) */
/* 2 0,0   */

/* ASR.B Dn,Dn */
void REGPARAM2 op_e020_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 64;
	CurrentInstrCycles = 6;  
	uae_s8 cnt = m68k_dreg(regs, srcreg);
	uae_s8 data = m68k_dreg(regs, dstreg);
	uae_u32 val = (uae_u8)data;
	CLEAR_CZNV();
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		SET_ZFLG(!(val & 0xff));
		SET_NFLG(val & 0x80);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	uae_u32 sign = (0x80 & val) >> 7;
	int ccnt = cnt & 63;
	cnt &= 63;
	if (cnt >= 8) {
		val = 0xff & (uae_u32)(0 - sign);
		SET_CFLG(sign);
		COPY_CARRY();
	} else if (cnt > 0) {
		val >>= cnt - 1;
		SET_CFLG(val & 1);
		COPY_CARRY();
		val >>= 1;
		val |= (0xff << (8 - cnt)) & (uae_u32)(0 - sign);
		val &= 0xff;
	}
	SET_ZFLG(((uae_s8)(val)) == 0);
	SET_NFLG(((uae_s8)(val)) < 0);
	{
		int cycles = 2;
		cycles += 2 * ccnt;
		do_cycles_ce000_internal(cycles);
	}
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((val) & 0xff);
	m68k_incpci(2);
	return;
}
/* 6+ (1/0) */
/* 2 0,0   */

/* LSR.B Dn,Dn */
void REGPARAM2 op_e028_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 66;
	CurrentInstrCycles = 6;  
	uae_s8 cnt = m68k_dreg(regs, srcreg);
	uae_s8 data = m68k_dreg(regs, dstreg);
	uae_u32 val = (uae_u8)data;
	CLEAR_CZNV();
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		SET_ZFLG(!(val & 0xff));
		SET_NFLG(val & 0x80);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	int ccnt = cnt & 63;
	cnt &= 63;
	if (cnt >= 8) {
		SET_CFLG((cnt == 8) & (val >> 7));
		COPY_CARRY();
		val = 0;
	} else if (cnt > 0) {
		val >>= cnt - 1;
		SET_CFLG(val & 1);
		COPY_CARRY();
		val >>= 1;
	}
	SET_ZFLG(((uae_s8)(val)) == 0);
	SET_NFLG(((uae_s8)(val)) < 0);
	{
		int cycles = 2;
		cycles += 2 * ccnt;
		do_cycles_ce000_internal(cycles);
	}
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((val) & 0xff);
	m68k_incpci(2);
	return;
}
/* 6+ (1/0) */
/* 2 0,0   */

/* ROXR.B Dn,Dn */
void REGPARAM2 op_e030_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 71;
	CurrentInstrCycles = 6;  
	uae_s8 cnt = m68k_dreg(regs, srcreg);
	uae_s8 data = m68k_dreg(regs, dstreg);
	uae_u32 val = (uae_u8)data;
	CLEAR_CZNV();
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		SET_ZFLG(!(val & 0xff));
		SET_NFLG(val & 0x80);
		SET_CFLG(GET_XFLG());
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	int ccnt = cnt & 63;
	cnt &= 63;
	if (cnt >= 36) cnt -= 36;
	if (cnt >= 18) cnt -= 18;
	if (cnt >= 9) cnt -= 9;
	if (cnt > 0) {
		cnt--;
		{
			uae_u32 carry;
			uae_u32 hival = (val << 1) | GET_XFLG();
			hival <<= (7 - cnt);
			val >>= cnt;
			carry = val & 1;
			val >>= 1;
			val |= hival;
			SET_XFLG(carry);
			val &= 0xff;
		}
	}
	SET_CFLG(GET_XFLG());
	SET_ZFLG(((uae_s8)(val)) == 0);
	SET_NFLG(((uae_s8)(val)) < 0);
	{
		int cycles = 2;
		cycles += 2 * ccnt;
		do_cycles_ce000_internal(cycles);
	}
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((val) & 0xff);
	m68k_incpci(2);
	return;
}
/* 6+ (1/0) */
/* 2 0,0   */

/* ROR.B Dn,Dn */
void REGPARAM2 op_e038_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 69;
	CurrentInstrCycles = 6;  
	uae_s8 cnt = m68k_dreg(regs, srcreg);
	uae_s8 data = m68k_dreg(regs, dstreg);
	uae_u32 val = (uae_u8)data;
	CLEAR_CZNV();
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		SET_ZFLG(!(val & 0xff));
		SET_NFLG(val & 0x80);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	int ccnt = cnt & 63;
	cnt &= 63;
	if (cnt > 0) {
		uae_u32 hival;
		cnt &= 7;
		hival = val << (8 - cnt);
		val >>= cnt;
		val |= hival;
		val &= 0xff;
		SET_CFLG((val & 0x80) >> 7);
	}
	SET_ZFLG(((uae_s8)(val)) == 0);
	SET_NFLG(((uae_s8)(val)) < 0);
	{
		int cycles = 2;
		cycles += 2 * ccnt;
		do_cycles_ce000_internal(cycles);
	}
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((val) & 0xff);
	m68k_incpci(2);
	return;
}
/* 6+ (1/0) */
/* 2 0,0   */

/* ASRQ.W #<data>,Dn */
void REGPARAM2 op_e040_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 64;
	CurrentInstrCycles = 6;  
	uae_u32 cnt = srcreg;
	uae_s16 data = m68k_dreg(regs, dstreg);
	uae_u32 val = (uae_u16)data;
	CLEAR_CZNV();
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		SET_ZFLG(!(val & 0xffff));
		SET_NFLG(val & 0x8000);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	uae_u32 sign = (0x8000 & val) >> 15;
	int ccnt = cnt & 63;
	cnt &= 63;
	if (cnt >= 16) {
		val = 0xffff & (uae_u32)(0 - sign);
		SET_CFLG(sign);
		COPY_CARRY();
	} else {
		val >>= cnt - 1;
		SET_CFLG(val & 1);
		COPY_CARRY();
		val >>= 1;
		val |= (0xffff << (16 - cnt)) & (uae_u32)(0 - sign);
		val &= 0xffff;
	}
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	{
		int cycles = 2;
		cycles += 2 * ccnt;
		do_cycles_ce000_internal(cycles);
	}
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((val) & 0xffff);
	m68k_incpci(2);
	return;
}
/* 6+ (1/0) */
/* 2 0,0   */

/* LSRQ.W #<data>,Dn */
void REGPARAM2 op_e048_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 66;
	CurrentInstrCycles = 6;  
	uae_u32 cnt = srcreg;
	uae_s16 data = m68k_dreg(regs, dstreg);
	uae_u32 val = (uae_u16)data;
	CLEAR_CZNV();
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		SET_ZFLG(!(val & 0xffff));
		SET_NFLG(val & 0x8000);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	int ccnt = cnt & 63;
	cnt &= 63;
	if (cnt >= 16) {
		SET_CFLG((cnt == 16) & (val >> 15));
		COPY_CARRY();
		val = 0;
	} else {
		val >>= cnt - 1;
		SET_CFLG(val & 1);
		COPY_CARRY();
		val >>= 1;
	}
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	{
		int cycles = 2;
		cycles += 2 * ccnt;
		do_cycles_ce000_internal(cycles);
	}
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((val) & 0xffff);
	m68k_incpci(2);
	return;
}
/* 6+ (1/0) */
/* 2 0,0   */

/* ROXRQ.W #<data>,Dn */
void REGPARAM2 op_e050_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 71;
	CurrentInstrCycles = 6;  
	uae_u32 cnt = srcreg;
	uae_s16 data = m68k_dreg(regs, dstreg);
	uae_u32 val = (uae_u16)data;
	CLEAR_CZNV();
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		SET_ZFLG(!(val & 0xffff));
		SET_NFLG(val & 0x8000);
		SET_CFLG(GET_XFLG());
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	int ccnt = cnt & 63;
	cnt &= 63;
	{
		cnt--;
		{
			uae_u32 carry;
			uae_u32 hival = (val << 1) | GET_XFLG();
			hival <<= (15 - cnt);
			val >>= cnt;
			carry = val & 1;
			val >>= 1;
			val |= hival;
			SET_XFLG(carry);
			val &= 0xffff;
		}
	}
	SET_CFLG(GET_XFLG());
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	{
		int cycles = 2;
		cycles += 2 * ccnt;
		do_cycles_ce000_internal(cycles);
	}
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((val) & 0xffff);
	m68k_incpci(2);
	return;
}
/* 6+ (1/0) */
/* 2 0,0   */

/* RORQ.W #<data>,Dn */
void REGPARAM2 op_e058_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 69;
	CurrentInstrCycles = 6;  
	uae_u32 cnt = srcreg;
	uae_s16 data = m68k_dreg(regs, dstreg);
	uae_u32 val = (uae_u16)data;
	CLEAR_CZNV();
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		SET_ZFLG(!(val & 0xffff));
		SET_NFLG(val & 0x8000);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	int ccnt = cnt & 63;
	cnt &= 63;
	{
		uae_u32 hival;
		cnt &= 15;
		hival = val << (16 - cnt);
		val >>= cnt;
		val |= hival;
		val &= 0xffff;
		SET_CFLG((val & 0x8000) >> 15);
	}
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	{
		int cycles = 2;
		cycles += 2 * ccnt;
		do_cycles_ce000_internal(cycles);
	}
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((val) & 0xffff);
	m68k_incpci(2);
	return;
}
/* 6+ (1/0) */
/* 2 0,0   */

/* ASR.W Dn,Dn */
void REGPARAM2 op_e060_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 64;
	CurrentInstrCycles = 6;  
	uae_s16 cnt = m68k_dreg(regs, srcreg);
	uae_s16 data = m68k_dreg(regs, dstreg);
	uae_u32 val = (uae_u16)data;
	CLEAR_CZNV();
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		SET_ZFLG(!(val & 0xffff));
		SET_NFLG(val & 0x8000);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	uae_u32 sign = (0x8000 & val) >> 15;
	int ccnt = cnt & 63;
	cnt &= 63;
	if (cnt >= 16) {
		val = 0xffff & (uae_u32)(0 - sign);
		SET_CFLG(sign);
		COPY_CARRY();
	} else if (cnt > 0) {
		val >>= cnt - 1;
		SET_CFLG(val & 1);
		COPY_CARRY();
		val >>= 1;
		val |= (0xffff << (16 - cnt)) & (uae_u32)(0 - sign);
		val &= 0xffff;
	}
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	{
		int cycles = 2;
		cycles += 2 * ccnt;
		do_cycles_ce000_internal(cycles);
	}
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((val) & 0xffff);
	m68k_incpci(2);
	return;
}
/* 6+ (1/0) */
/* 2 0,0   */

/* LSR.W Dn,Dn */
void REGPARAM2 op_e068_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 66;
	CurrentInstrCycles = 6;  
	uae_s16 cnt = m68k_dreg(regs, srcreg);
	uae_s16 data = m68k_dreg(regs, dstreg);
	uae_u32 val = (uae_u16)data;
	CLEAR_CZNV();
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		SET_ZFLG(!(val & 0xffff));
		SET_NFLG(val & 0x8000);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	int ccnt = cnt & 63;
	cnt &= 63;
	if (cnt >= 16) {
		SET_CFLG((cnt == 16) & (val >> 15));
		COPY_CARRY();
		val = 0;
	} else if (cnt > 0) {
		val >>= cnt - 1;
		SET_CFLG(val & 1);
		COPY_CARRY();
		val >>= 1;
	}
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	{
		int cycles = 2;
		cycles += 2 * ccnt;
		do_cycles_ce000_internal(cycles);
	}
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((val) & 0xffff);
	m68k_incpci(2);
	return;
}
/* 6+ (1/0) */
/* 2 0,0   */

/* ROXR.W Dn,Dn */
void REGPARAM2 op_e070_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 71;
	CurrentInstrCycles = 6;  
	uae_s16 cnt = m68k_dreg(regs, srcreg);
	uae_s16 data = m68k_dreg(regs, dstreg);
	uae_u32 val = (uae_u16)data;
	CLEAR_CZNV();
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		SET_ZFLG(!(val & 0xffff));
		SET_NFLG(val & 0x8000);
		SET_CFLG(GET_XFLG());
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	int ccnt = cnt & 63;
	cnt &= 63;
	if (cnt >= 34) cnt -= 34;
	if (cnt >= 17) cnt -= 17;
	if (cnt > 0) {
		cnt--;
		{
			uae_u32 carry;
			uae_u32 hival = (val << 1) | GET_XFLG();
			hival <<= (15 - cnt);
			val >>= cnt;
			carry = val & 1;
			val >>= 1;
			val |= hival;
			SET_XFLG(carry);
			val &= 0xffff;
		}
	}
	SET_CFLG(GET_XFLG());
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	{
		int cycles = 2;
		cycles += 2 * ccnt;
		do_cycles_ce000_internal(cycles);
	}
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((val) & 0xffff);
	m68k_incpci(2);
	return;
}
/* 6+ (1/0) */
/* 2 0,0   */

/* ROR.W Dn,Dn */
void REGPARAM2 op_e078_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 69;
	CurrentInstrCycles = 6;  
	uae_s16 cnt = m68k_dreg(regs, srcreg);
	uae_s16 data = m68k_dreg(regs, dstreg);
	uae_u32 val = (uae_u16)data;
	CLEAR_CZNV();
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		SET_ZFLG(!(val & 0xffff));
		SET_NFLG(val & 0x8000);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	int ccnt = cnt & 63;
	cnt &= 63;
	if (cnt > 0) {
		uae_u32 hival;
		cnt &= 15;
		hival = val << (16 - cnt);
		val >>= cnt;
		val |= hival;
		val &= 0xffff;
		SET_CFLG((val & 0x8000) >> 15);
	}
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	{
		int cycles = 2;
		cycles += 2 * ccnt;
		do_cycles_ce000_internal(cycles);
	}
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((val) & 0xffff);
	m68k_incpci(2);
	return;
}
/* 6+ (1/0) */
/* 2 0,0   */

/* ASRQ.L #<data>,Dn */
void REGPARAM2 op_e080_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 64;
	CurrentInstrCycles = 8;  
	uae_u32 cnt = srcreg;
	uae_s32 data = m68k_dreg(regs, dstreg);
	uae_u32 val = data;
	CLEAR_CZNV();
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		SET_NFLG(val & 0x8000);
		SET_ZFLG(!(val & 0xffff));
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	uae_u32 sign = (0x80000000 & val) >> 31;
	int ccnt = cnt & 63;
	cnt &= 63;
	if (cnt >= 32) {
		val = 0xffffffff & (uae_u32)(0 - sign);
		SET_CFLG(sign);
		COPY_CARRY();
	} else {
		val >>= cnt - 1;
		SET_CFLG(val & 1);
		COPY_CARRY();
		val >>= 1;
		val |= (0xffffffff << (32 - cnt)) & (uae_u32)(0 - sign);
		val &= 0xffffffff;
	}
	SET_ZFLG(((uae_s32)(val)) == 0);
	SET_NFLG(((uae_s32)(val)) < 0);
	{
		int cycles = 4;
		cycles += 2 * ccnt;
		do_cycles_ce000_internal(cycles);
	}
	m68k_dreg(regs, dstreg) = (val);
	m68k_incpci(2);
	return;
}
/* 8+ (1/0) */
/* 2 0,0   */

/* LSRQ.L #<data>,Dn */
void REGPARAM2 op_e088_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 66;
	CurrentInstrCycles = 8;  
	uae_u32 cnt = srcreg;
	uae_s32 data = m68k_dreg(regs, dstreg);
	uae_u32 val = data;
	CLEAR_CZNV();
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		SET_NFLG(val & 0x8000);
		SET_ZFLG(!(val & 0xffff));
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	int ccnt = cnt & 63;
	cnt &= 63;
	if (cnt >= 32) {
		SET_CFLG((cnt == 32) & (val >> 31));
		COPY_CARRY();
		val = 0;
	} else {
		val >>= cnt - 1;
		SET_CFLG(val & 1);
		COPY_CARRY();
		val >>= 1;
	}
	SET_ZFLG(((uae_s32)(val)) == 0);
	SET_NFLG(((uae_s32)(val)) < 0);
	{
		int cycles = 4;
		cycles += 2 * ccnt;
		do_cycles_ce000_internal(cycles);
	}
	m68k_dreg(regs, dstreg) = (val);
	m68k_incpci(2);
	return;
}
/* 8+ (1/0) */
/* 2 0,0   */

/* ROXRQ.L #<data>,Dn */
void REGPARAM2 op_e090_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 71;
	CurrentInstrCycles = 8;  
	uae_u32 cnt = srcreg;
	uae_s32 data = m68k_dreg(regs, dstreg);
	uae_u32 val = data;
	CLEAR_CZNV();
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		SET_NFLG(val & 0x8000);
		SET_ZFLG(!(val & 0xffff));
		SET_CFLG(GET_XFLG());
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	int ccnt = cnt & 63;
	cnt &= 63;
	{
		cnt--;
		{
			uae_u32 carry;
			uae_u32 hival = (val << 1) | GET_XFLG();
			hival <<= (31 - cnt);
			val >>= cnt;
			carry = val & 1;
			val >>= 1;
			val |= hival;
			SET_XFLG(carry);
			val &= 0xffffffff;
		}
	}
	SET_CFLG(GET_XFLG());
	SET_ZFLG(((uae_s32)(val)) == 0);
	SET_NFLG(((uae_s32)(val)) < 0);
	{
		int cycles = 4;
		cycles += 2 * ccnt;
		do_cycles_ce000_internal(cycles);
	}
	m68k_dreg(regs, dstreg) = (val);
	m68k_incpci(2);
	return;
}
/* 8+ (1/0) */
/* 2 0,0   */

/* RORQ.L #<data>,Dn */
void REGPARAM2 op_e098_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 69;
	CurrentInstrCycles = 8;  
	uae_u32 cnt = srcreg;
	uae_s32 data = m68k_dreg(regs, dstreg);
	uae_u32 val = data;
	CLEAR_CZNV();
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		SET_NFLG(val & 0x8000);
		SET_ZFLG(!(val & 0xffff));
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	int ccnt = cnt & 63;
	cnt &= 63;
	{
		uae_u32 hival;
		cnt &= 31;
		hival = val << (32 - cnt);
		val >>= cnt;
		val |= hival;
		val &= 0xffffffff;
		SET_CFLG((val & 0x80000000) >> 31);
	}
	SET_ZFLG(((uae_s32)(val)) == 0);
	SET_NFLG(((uae_s32)(val)) < 0);
	{
		int cycles = 4;
		cycles += 2 * ccnt;
		do_cycles_ce000_internal(cycles);
	}
	m68k_dreg(regs, dstreg) = (val);
	m68k_incpci(2);
	return;
}
/* 8+ (1/0) */
/* 2 0,0   */

/* ASR.L Dn,Dn */
void REGPARAM2 op_e0a0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 64;
	CurrentInstrCycles = 8;  
	uae_s32 cnt = m68k_dreg(regs, srcreg);
	uae_s32 data = m68k_dreg(regs, dstreg);
	uae_u32 val = data;
	CLEAR_CZNV();
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		SET_NFLG(val & 0x8000);
		SET_ZFLG(!(val & 0xffff));
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	uae_u32 sign = (0x80000000 & val) >> 31;
	int ccnt = cnt & 63;
	cnt &= 63;
	if (cnt >= 32) {
		val = 0xffffffff & (uae_u32)(0 - sign);
		SET_CFLG(sign);
		COPY_CARRY();
	} else if (cnt > 0) {
		val >>= cnt - 1;
		SET_CFLG(val & 1);
		COPY_CARRY();
		val >>= 1;
		val |= (0xffffffff << (32 - cnt)) & (uae_u32)(0 - sign);
		val &= 0xffffffff;
	}
	SET_ZFLG(((uae_s32)(val)) == 0);
	SET_NFLG(((uae_s32)(val)) < 0);
	{
		int cycles = 4;
		cycles += 2 * ccnt;
		do_cycles_ce000_internal(cycles);
	}
	m68k_dreg(regs, dstreg) = (val);
	m68k_incpci(2);
	return;
}
/* 8+ (1/0) */
/* 2 0,0   */

/* LSR.L Dn,Dn */
void REGPARAM2 op_e0a8_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 66;
	CurrentInstrCycles = 8;  
	uae_s32 cnt = m68k_dreg(regs, srcreg);
	uae_s32 data = m68k_dreg(regs, dstreg);
	uae_u32 val = data;
	CLEAR_CZNV();
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		SET_NFLG(val & 0x8000);
		SET_ZFLG(!(val & 0xffff));
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	int ccnt = cnt & 63;
	cnt &= 63;
	if (cnt >= 32) {
		SET_CFLG((cnt == 32) & (val >> 31));
		COPY_CARRY();
		val = 0;
	} else if (cnt > 0) {
		val >>= cnt - 1;
		SET_CFLG(val & 1);
		COPY_CARRY();
		val >>= 1;
	}
	SET_ZFLG(((uae_s32)(val)) == 0);
	SET_NFLG(((uae_s32)(val)) < 0);
	{
		int cycles = 4;
		cycles += 2 * ccnt;
		do_cycles_ce000_internal(cycles);
	}
	m68k_dreg(regs, dstreg) = (val);
	m68k_incpci(2);
	return;
}
/* 8+ (1/0) */
/* 2 0,0   */

/* ROXR.L Dn,Dn */
void REGPARAM2 op_e0b0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 71;
	CurrentInstrCycles = 8;  
	uae_s32 cnt = m68k_dreg(regs, srcreg);
	uae_s32 data = m68k_dreg(regs, dstreg);
	uae_u32 val = data;
	CLEAR_CZNV();
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		SET_NFLG(val & 0x8000);
		SET_ZFLG(!(val & 0xffff));
		SET_CFLG(GET_XFLG());
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	int ccnt = cnt & 63;
	cnt &= 63;
	if (cnt >= 33) cnt -= 33;
	if (cnt > 0) {
		cnt--;
		{
			uae_u32 carry;
			uae_u32 hival = (val << 1) | GET_XFLG();
			hival <<= (31 - cnt);
			val >>= cnt;
			carry = val & 1;
			val >>= 1;
			val |= hival;
			SET_XFLG(carry);
			val &= 0xffffffff;
		}
	}
	SET_CFLG(GET_XFLG());
	SET_ZFLG(((uae_s32)(val)) == 0);
	SET_NFLG(((uae_s32)(val)) < 0);
	{
		int cycles = 4;
		cycles += 2 * ccnt;
		do_cycles_ce000_internal(cycles);
	}
	m68k_dreg(regs, dstreg) = (val);
	m68k_incpci(2);
	return;
}
/* 8+ (1/0) */
/* 2 0,0   */

/* ROR.L Dn,Dn */
void REGPARAM2 op_e0b8_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 69;
	CurrentInstrCycles = 8;  
	uae_s32 cnt = m68k_dreg(regs, srcreg);
	uae_s32 data = m68k_dreg(regs, dstreg);
	uae_u32 val = data;
	CLEAR_CZNV();
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		SET_NFLG(val & 0x8000);
		SET_ZFLG(!(val & 0xffff));
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	int ccnt = cnt & 63;
	cnt &= 63;
	if (cnt > 0) {
		uae_u32 hival;
		cnt &= 31;
		hival = val << (32 - cnt);
		val >>= cnt;
		val |= hival;
		val &= 0xffffffff;
		SET_CFLG((val & 0x80000000) >> 31);
	}
	SET_ZFLG(((uae_s32)(val)) == 0);
	SET_NFLG(((uae_s32)(val)) < 0);
	{
		int cycles = 4;
		cycles += 2 * ccnt;
		do_cycles_ce000_internal(cycles);
	}
	m68k_dreg(regs, dstreg) = (val);
	m68k_incpci(2);
	return;
}
/* 8+ (1/0) */
/* 2 0,0   */

/* ASRW.W (An) */
void REGPARAM2 op_e0d0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 72;
	CurrentInstrCycles = 12; 
	uaecptr dataa;
	dataa = m68k_areg(regs, srcreg);
	if (dataa & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dataa, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 data = x_get_word(dataa);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dataa + 0, 0x1, 1);
		return;
	}
	uae_u32 val = (uae_u16)data;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();
		SET_CFLG(val & 1);
		SET_ZFLG(!(val >> 1));
		SET_NFLG(val & 0x8000);
		SET_XFLG(GET_CFLG());
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	uae_u32 sign = 0x8000 & val;
	uae_u32 cflg = val & 1;
	val = (val >> 1) | sign;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	SET_CFLG(cflg);
	COPY_CARRY();
	x_put_word(dataa, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dataa + 0, 0x1, val, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 12 (2/1) */
/* 2 0,0   */

/* ASRW.W (An)+ */
void REGPARAM2 op_e0d8_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 72;
	CurrentInstrCycles = 12; 
	uaecptr dataa;
	dataa = m68k_areg(regs, srcreg);
	if (dataa & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dataa, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 data = x_get_word(dataa);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) += 2 + 0;
		exception2_read(opcode, dataa + 0, 0x1, 1);
		return;
	}
	m68k_areg(regs, srcreg) += 2;
	uae_u32 val = (uae_u16)data;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();
		SET_CFLG(val & 1);
		SET_ZFLG(!(val >> 1));
		SET_NFLG(val & 0x8000);
		SET_XFLG(GET_CFLG());
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	uae_u32 sign = 0x8000 & val;
	uae_u32 cflg = val & 1;
	val = (val >> 1) | sign;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	SET_CFLG(cflg);
	COPY_CARRY();
	x_put_word(dataa, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dataa + 0, 0x1, val, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 12 (2/1) */
/* 2 0,0   */

/* ASRW.W -(An) */
void REGPARAM2 op_e0e0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 72;
	CurrentInstrCycles = 14; 
	uaecptr dataa;
	dataa = m68k_areg(regs, srcreg) - 2;
	do_cycles_ce000_internal(2);
	if (dataa & 1) {
		m68k_incpci(4);
		m68k_areg(regs, srcreg) = dataa;
		exception3_read_access(opcode, dataa, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 data = x_get_word(dataa);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, srcreg) = dataa;
		exception2_read(opcode, dataa + 0, 0x1, 1);
		return;
	}
	m68k_areg(regs, srcreg) = dataa;
	uae_u32 val = (uae_u16)data;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();
		SET_CFLG(val & 1);
		SET_ZFLG(!(val >> 1));
		SET_NFLG(val & 0x8000);
		SET_XFLG(GET_CFLG());
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	uae_u32 sign = 0x8000 & val;
	uae_u32 cflg = val & 1;
	val = (val >> 1) | sign;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	SET_CFLG(cflg);
	COPY_CARRY();
	x_put_word(dataa, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dataa + 0, 0x1, val, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 14 (2/1) */
/* 2 0,0   */

/* ASRW.W (d16,An) */
void REGPARAM2 op_e0e8_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 72;
	CurrentInstrCycles = 16; 
	uaecptr dataa;
	dataa = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (dataa & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dataa, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 data = x_get_word(dataa);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dataa + 0, 0x1, 1);
		return;
	}
	uae_u32 val = (uae_u16)data;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();
		SET_CFLG(val & 1);
		SET_ZFLG(!(val >> 1));
		SET_NFLG(val & 0x8000);
		SET_XFLG(GET_CFLG());
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	uae_u32 sign = 0x8000 & val;
	uae_u32 cflg = val & 1;
	val = (val >> 1) | sign;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	SET_CFLG(cflg);
	COPY_CARRY();
	x_put_word(dataa, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dataa + 0, 0x1, val, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* ASRW.W (d8,An,Xn) */
void REGPARAM2 op_e0f0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 72;
	CurrentInstrCycles = 18; 
	uaecptr dataa;
	do_cycles_ce000_internal(2);
	dataa = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (dataa & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dataa, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 data = x_get_word(dataa);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dataa + 0, 0x1, 1);
		return;
	}
	uae_u32 val = (uae_u16)data;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();
		SET_CFLG(val & 1);
		SET_ZFLG(!(val >> 1));
		SET_NFLG(val & 0x8000);
		SET_XFLG(GET_CFLG());
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	uae_u32 sign = 0x8000 & val;
	uae_u32 cflg = val & 1;
	val = (val >> 1) | sign;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	SET_CFLG(cflg);
	COPY_CARRY();
	x_put_word(dataa, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dataa + 0, 0x1, val, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 18 (3/1) */
/* 4 4,0   */

/* ASRW.W (xxx).W */
void REGPARAM2 op_e0f8_14_ff(uae_u32 opcode)
{
	OpcodeFamily = 72;
	CurrentInstrCycles = 16; 
	uaecptr dataa;
	dataa = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	if (dataa & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, dataa, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 data = x_get_word(dataa);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dataa + 0, 0x1, 1);
		return;
	}
	uae_u32 val = (uae_u16)data;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();
		SET_CFLG(val & 1);
		SET_ZFLG(!(val >> 1));
		SET_NFLG(val & 0x8000);
		SET_XFLG(GET_CFLG());
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	uae_u32 sign = 0x8000 & val;
	uae_u32 cflg = val & 1;
	val = (val >> 1) | sign;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	SET_CFLG(cflg);
	COPY_CARRY();
	x_put_word(dataa, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dataa + 0, 0x1, val, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* ASRW.W (xxx).L */
void REGPARAM2 op_e0f9_14_ff(uae_u32 opcode)
{
	OpcodeFamily = 72;
	CurrentInstrCycles = 20; 
	uaecptr dataa;
	dataa = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	dataa |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	if (dataa & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, dataa, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 data = x_get_word(dataa);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dataa + 0, 0x1, 1);
		return;
	}
	uae_u32 val = (uae_u16)data;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();
		SET_CFLG(val & 1);
		SET_ZFLG(!(val >> 1));
		SET_NFLG(val & 0x8000);
		SET_XFLG(GET_CFLG());
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	opcode = regs.ir;
	uae_u32 sign = 0x8000 & val;
	uae_u32 cflg = val & 1;
	val = (val >> 1) | sign;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	SET_CFLG(cflg);
	COPY_CARRY();
	x_put_word(dataa, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dataa + 0, 0x1, val, 1);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 20 (4/1) */
/* 6 0,0   */

/* ASLQ.B #<data>,Dn */
void REGPARAM2 op_e100_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 65;
	CurrentInstrCycles = 6;  
	uae_u32 cnt = srcreg;
	uae_s8 data = m68k_dreg(regs, dstreg);
	uae_u32 val = (uae_u8)data;
	CLEAR_CZNV();
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		SET_ZFLG(!(val & 0xff));
		SET_NFLG(val & 0x80);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	int ccnt = cnt & 63;
	cnt &= 63;
	if (cnt >= 8) {
		SET_VFLG(val != 0);
		SET_CFLG(cnt == 8 ? val & 1 : 0);
		COPY_CARRY();
		val = 0;
	} else {
		uae_u32 mask = (0xff << (7 - cnt)) & 0xff;
		SET_VFLG((val & mask) != mask && (val & mask) != 0);
		val <<= cnt - 1;
		SET_CFLG((val & 0x80) >> 7);
		COPY_CARRY();
		val <<= 1;
		val &= 0xff;
	}
	SET_ZFLG(((uae_s8)(val)) == 0);
	SET_NFLG(((uae_s8)(val)) < 0);
	{
		int cycles = 2;
		cycles += 2 * ccnt;
		do_cycles_ce000_internal(cycles);
	}
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((val) & 0xff);
	m68k_incpci(2);
	return;
}
/* 6+ (1/0) */
/* 2 0,0   */

/* LSLQ.B #<data>,Dn */
void REGPARAM2 op_e108_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 67;
	CurrentInstrCycles = 6;  
	uae_u32 cnt = srcreg;
	uae_s8 data = m68k_dreg(regs, dstreg);
	uae_u32 val = (uae_u8)data;
	CLEAR_CZNV();
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		SET_ZFLG(!(val & 0xff));
		SET_NFLG(val & 0x80);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	int ccnt = cnt & 63;
	cnt &= 63;
	if (cnt >= 8) {
		SET_CFLG(cnt == 8 ? val & 1 : 0);
		COPY_CARRY();
		val = 0;
	} else {
		val <<= (cnt - 1);
		SET_CFLG((val & 0x80) >> 7);
		COPY_CARRY();
		val <<= 1;
		val &= 0xff;
	}
	SET_ZFLG(((uae_s8)(val)) == 0);
	SET_NFLG(((uae_s8)(val)) < 0);
	{
		int cycles = 2;
		cycles += 2 * ccnt;
		do_cycles_ce000_internal(cycles);
	}
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((val) & 0xff);
	m68k_incpci(2);
	return;
}
/* 6+ (1/0) */
/* 2 0,0   */

/* ROXLQ.B #<data>,Dn */
void REGPARAM2 op_e110_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 70;
	CurrentInstrCycles = 6;  
	uae_u32 cnt = srcreg;
	uae_s8 data = m68k_dreg(regs, dstreg);
	uae_u32 val = (uae_u8)data;
	CLEAR_CZNV();
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		SET_ZFLG(!(val & 0xff));
		SET_NFLG(val & 0x80);
		SET_CFLG(GET_XFLG());
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	int ccnt = cnt & 63;
	cnt &= 63;
	{
		cnt--;
		{
			uae_u32 carry;
			uae_u32 loval = val >> (7 - cnt);
			carry = loval & 1;
			val = (((val << 1) | GET_XFLG()) << cnt) | (loval >> 1);
			SET_XFLG(carry);
			val &= 0xff;
		}
	}
	SET_CFLG(GET_XFLG());
	SET_ZFLG(((uae_s8)(val)) == 0);
	SET_NFLG(((uae_s8)(val)) < 0);
	{
		int cycles = 2;
		cycles += 2 * ccnt;
		do_cycles_ce000_internal(cycles);
	}
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((val) & 0xff);
	m68k_incpci(2);
	return;
}
/* 6+ (1/0) */
/* 2 0,0   */

/* ROLQ.B #<data>,Dn */
void REGPARAM2 op_e118_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 68;
	CurrentInstrCycles = 6;  
	uae_u32 cnt = srcreg;
	uae_s8 data = m68k_dreg(regs, dstreg);
	uae_u32 val = (uae_u8)data;
	CLEAR_CZNV();
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		SET_ZFLG(!(val & 0xff));
		SET_NFLG(val & 0x80);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	int ccnt = cnt & 63;
	cnt &= 63;
	{
		uae_u32 loval;
		cnt &= 7;
		loval = val >> (8 - cnt);
		val <<= cnt;
		val |= loval;
		val &= 0xff;
		SET_CFLG(val & 1);
	}
	SET_ZFLG(((uae_s8)(val)) == 0);
	SET_NFLG(((uae_s8)(val)) < 0);
	{
		int cycles = 2;
		cycles += 2 * ccnt;
		do_cycles_ce000_internal(cycles);
	}
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((val) & 0xff);
	m68k_incpci(2);
	return;
}
/* 6+ (1/0) */
/* 2 0,0   */

/* ASL.B Dn,Dn */
void REGPARAM2 op_e120_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 65;
	CurrentInstrCycles = 6;  
	uae_s8 cnt = m68k_dreg(regs, srcreg);
	uae_s8 data = m68k_dreg(regs, dstreg);
	uae_u32 val = (uae_u8)data;
	CLEAR_CZNV();
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		SET_ZFLG(!(val & 0xff));
		SET_NFLG(val & 0x80);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	int ccnt = cnt & 63;
	cnt &= 63;
	if (cnt >= 8) {
		SET_VFLG(val != 0);
		SET_CFLG(cnt == 8 ? val & 1 : 0);
		COPY_CARRY();
		val = 0;
	} else if (cnt > 0) {
		uae_u32 mask = (0xff << (7 - cnt)) & 0xff;
		SET_VFLG((val & mask) != mask && (val & mask) != 0);
		val <<= cnt - 1;
		SET_CFLG((val & 0x80) >> 7);
		COPY_CARRY();
		val <<= 1;
		val &= 0xff;
	}
	SET_ZFLG(((uae_s8)(val)) == 0);
	SET_NFLG(((uae_s8)(val)) < 0);
	{
		int cycles = 2;
		cycles += 2 * ccnt;
		do_cycles_ce000_internal(cycles);
	}
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((val) & 0xff);
	m68k_incpci(2);
	return;
}
/* 6+ (1/0) */
/* 2 0,0   */

/* LSL.B Dn,Dn */
void REGPARAM2 op_e128_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 67;
	CurrentInstrCycles = 6;  
	uae_s8 cnt = m68k_dreg(regs, srcreg);
	uae_s8 data = m68k_dreg(regs, dstreg);
	uae_u32 val = (uae_u8)data;
	CLEAR_CZNV();
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		SET_ZFLG(!(val & 0xff));
		SET_NFLG(val & 0x80);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	int ccnt = cnt & 63;
	cnt &= 63;
	if (cnt >= 8) {
		SET_CFLG(cnt == 8 ? val & 1 : 0);
		COPY_CARRY();
		val = 0;
	} else if (cnt > 0) {
		val <<= (cnt - 1);
		SET_CFLG((val & 0x80) >> 7);
		COPY_CARRY();
		val <<= 1;
		val &= 0xff;
	}
	SET_ZFLG(((uae_s8)(val)) == 0);
	SET_NFLG(((uae_s8)(val)) < 0);
	{
		int cycles = 2;
		cycles += 2 * ccnt;
		do_cycles_ce000_internal(cycles);
	}
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((val) & 0xff);
	m68k_incpci(2);
	return;
}
/* 6+ (1/0) */
/* 2 0,0   */

/* ROXL.B Dn,Dn */
void REGPARAM2 op_e130_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 70;
	CurrentInstrCycles = 6;  
	uae_s8 cnt = m68k_dreg(regs, srcreg);
	uae_s8 data = m68k_dreg(regs, dstreg);
	uae_u32 val = (uae_u8)data;
	CLEAR_CZNV();
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		SET_ZFLG(!(val & 0xff));
		SET_NFLG(val & 0x80);
		SET_CFLG(GET_XFLG());
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	int ccnt = cnt & 63;
	cnt &= 63;
	if (cnt >= 36) cnt -= 36;
	if (cnt >= 18) cnt -= 18;
	if (cnt >= 9) cnt -= 9;
	if (cnt > 0) {
		cnt--;
		{
			uae_u32 carry;
			uae_u32 loval = val >> (7 - cnt);
			carry = loval & 1;
			val = (((val << 1) | GET_XFLG()) << cnt) | (loval >> 1);
			SET_XFLG(carry);
			val &= 0xff;
		}
	}
	SET_CFLG(GET_XFLG());
	SET_ZFLG(((uae_s8)(val)) == 0);
	SET_NFLG(((uae_s8)(val)) < 0);
	{
		int cycles = 2;
		cycles += 2 * ccnt;
		do_cycles_ce000_internal(cycles);
	}
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((val) & 0xff);
	m68k_incpci(2);
	return;
}
/* 6+ (1/0) */
/* 2 0,0   */

/* ROL.B Dn,Dn */
void REGPARAM2 op_e138_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 68;
	CurrentInstrCycles = 6;  
	uae_s8 cnt = m68k_dreg(regs, srcreg);
	uae_s8 data = m68k_dreg(regs, dstreg);
	uae_u32 val = (uae_u8)data;
	CLEAR_CZNV();
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		SET_ZFLG(!(val & 0xff));
		SET_NFLG(val & 0x80);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	int ccnt = cnt & 63;
	cnt &= 63;
	if (cnt > 0) {
		uae_u32 loval;
		cnt &= 7;
		loval = val >> (8 - cnt);
		val <<= cnt;
		val |= loval;
		val &= 0xff;
		SET_CFLG(val & 1);
	}
	SET_ZFLG(((uae_s8)(val)) == 0);
	SET_NFLG(((uae_s8)(val)) < 0);
	{
		int cycles = 2;
		cycles += 2 * ccnt;
		do_cycles_ce000_internal(cycles);
	}
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((val) & 0xff);
	m68k_incpci(2);
	return;
}
/* 6+ (1/0) */
/* 2 0,0   */

/* ASLQ.W #<data>,Dn */
void REGPARAM2 op_e140_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 65;
	CurrentInstrCycles = 6;  
	uae_u32 cnt = srcreg;
	uae_s16 data = m68k_dreg(regs, dstreg);
	uae_u32 val = (uae_u16)data;
	CLEAR_CZNV();
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		SET_ZFLG(!(val & 0xffff));
		SET_NFLG(val & 0x8000);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	int ccnt = cnt & 63;
	cnt &= 63;
	if (cnt >= 16) {
		SET_VFLG(val != 0);
		SET_CFLG(cnt == 16 ? val & 1 : 0);
		COPY_CARRY();
		val = 0;
	} else {
		uae_u32 mask = (0xffff << (15 - cnt)) & 0xffff;
		SET_VFLG((val & mask) != mask && (val & mask) != 0);
		val <<= cnt - 1;
		SET_CFLG((val & 0x8000) >> 15);
		COPY_CARRY();
		val <<= 1;
		val &= 0xffff;
	}
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	{
		int cycles = 2;
		cycles += 2 * ccnt;
		do_cycles_ce000_internal(cycles);
	}
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((val) & 0xffff);
	m68k_incpci(2);
	return;
}
/* 6+ (1/0) */
/* 2 0,0   */

/* LSLQ.W #<data>,Dn */
void REGPARAM2 op_e148_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 67;
	CurrentInstrCycles = 6;  
	uae_u32 cnt = srcreg;
	uae_s16 data = m68k_dreg(regs, dstreg);
	uae_u32 val = (uae_u16)data;
	CLEAR_CZNV();
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		SET_ZFLG(!(val & 0xffff));
		SET_NFLG(val & 0x8000);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	int ccnt = cnt & 63;
	cnt &= 63;
	if (cnt >= 16) {
		SET_CFLG(cnt == 16 ? val & 1 : 0);
		COPY_CARRY();
		val = 0;
	} else {
		val <<= (cnt - 1);
		SET_CFLG((val & 0x8000) >> 15);
		COPY_CARRY();
		val <<= 1;
		val &= 0xffff;
	}
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	{
		int cycles = 2;
		cycles += 2 * ccnt;
		do_cycles_ce000_internal(cycles);
	}
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((val) & 0xffff);
	m68k_incpci(2);
	return;
}
/* 6+ (1/0) */
/* 2 0,0   */

/* ROXLQ.W #<data>,Dn */
void REGPARAM2 op_e150_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 70;
	CurrentInstrCycles = 6;  
	uae_u32 cnt = srcreg;
	uae_s16 data = m68k_dreg(regs, dstreg);
	uae_u32 val = (uae_u16)data;
	CLEAR_CZNV();
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		SET_ZFLG(!(val & 0xffff));
		SET_NFLG(val & 0x8000);
		SET_CFLG(GET_XFLG());
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	int ccnt = cnt & 63;
	cnt &= 63;
	{
		cnt--;
		{
			uae_u32 carry;
			uae_u32 loval = val >> (15 - cnt);
			carry = loval & 1;
			val = (((val << 1) | GET_XFLG()) << cnt) | (loval >> 1);
			SET_XFLG(carry);
			val &= 0xffff;
		}
	}
	SET_CFLG(GET_XFLG());
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	{
		int cycles = 2;
		cycles += 2 * ccnt;
		do_cycles_ce000_internal(cycles);
	}
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((val) & 0xffff);
	m68k_incpci(2);
	return;
}
/* 6+ (1/0) */
/* 2 0,0   */

/* ROLQ.W #<data>,Dn */
void REGPARAM2 op_e158_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 68;
	CurrentInstrCycles = 6;  
	uae_u32 cnt = srcreg;
	uae_s16 data = m68k_dreg(regs, dstreg);
	uae_u32 val = (uae_u16)data;
	CLEAR_CZNV();
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		SET_ZFLG(!(val & 0xffff));
		SET_NFLG(val & 0x8000);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	int ccnt = cnt & 63;
	cnt &= 63;
	{
		uae_u32 loval;
		cnt &= 15;
		loval = val >> (16 - cnt);
		val <<= cnt;
		val |= loval;
		val &= 0xffff;
		SET_CFLG(val & 1);
	}
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	{
		int cycles = 2;
		cycles += 2 * ccnt;
		do_cycles_ce000_internal(cycles);
	}
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((val) & 0xffff);
	m68k_incpci(2);
	return;
}
/* 6+ (1/0) */
/* 2 0,0   */

/* ASL.W Dn,Dn */
void REGPARAM2 op_e160_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 65;
	CurrentInstrCycles = 6;  
	uae_s16 cnt = m68k_dreg(regs, srcreg);
	uae_s16 data = m68k_dreg(regs, dstreg);
	uae_u32 val = (uae_u16)data;
	CLEAR_CZNV();
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		SET_ZFLG(!(val & 0xffff));
		SET_NFLG(val & 0x8000);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	int ccnt = cnt & 63;
	cnt &= 63;
	if (cnt >= 16) {
		SET_VFLG(val != 0);
		SET_CFLG(cnt == 16 ? val & 1 : 0);
		COPY_CARRY();
		val = 0;
	} else if (cnt > 0) {
		uae_u32 mask = (0xffff << (15 - cnt)) & 0xffff;
		SET_VFLG((val & mask) != mask && (val & mask) != 0);
		val <<= cnt - 1;
		SET_CFLG((val & 0x8000) >> 15);
		COPY_CARRY();
		val <<= 1;
		val &= 0xffff;
	}
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	{
		int cycles = 2;
		cycles += 2 * ccnt;
		do_cycles_ce000_internal(cycles);
	}
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((val) & 0xffff);
	m68k_incpci(2);
	return;
}
/* 6+ (1/0) */
/* 2 0,0   */

/* LSL.W Dn,Dn */
void REGPARAM2 op_e168_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 67;
	CurrentInstrCycles = 6;  
	uae_s16 cnt = m68k_dreg(regs, srcreg);
	uae_s16 data = m68k_dreg(regs, dstreg);
	uae_u32 val = (uae_u16)data;
	CLEAR_CZNV();
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		SET_ZFLG(!(val & 0xffff));
		SET_NFLG(val & 0x8000);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	int ccnt = cnt & 63;
	cnt &= 63;
	if (cnt >= 16) {
		SET_CFLG(cnt == 16 ? val & 1 : 0);
		COPY_CARRY();
		val = 0;
	} else if (cnt > 0) {
		val <<= (cnt - 1);
		SET_CFLG((val & 0x8000) >> 15);
		COPY_CARRY();
		val <<= 1;
		val &= 0xffff;
	}
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	{
		int cycles = 2;
		cycles += 2 * ccnt;
		do_cycles_ce000_internal(cycles);
	}
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((val) & 0xffff);
	m68k_incpci(2);
	return;
}
/* 6+ (1/0) */
/* 2 0,0   */

/* ROXL.W Dn,Dn */
void REGPARAM2 op_e170_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 70;
	CurrentInstrCycles = 6;  
	uae_s16 cnt = m68k_dreg(regs, srcreg);
	uae_s16 data = m68k_dreg(regs, dstreg);
	uae_u32 val = (uae_u16)data;
	CLEAR_CZNV();
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		SET_ZFLG(!(val & 0xffff));
		SET_NFLG(val & 0x8000);
		SET_CFLG(GET_XFLG());
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	int ccnt = cnt & 63;
	cnt &= 63;
	if (cnt >= 34) cnt -= 34;
	if (cnt >= 17) cnt -= 17;
	if (cnt > 0) {
		cnt--;
		{
			uae_u32 carry;
			uae_u32 loval = val >> (15 - cnt);
			carry = loval & 1;
			val = (((val << 1) | GET_XFLG()) << cnt) | (loval >> 1);
			SET_XFLG(carry);
			val &= 0xffff;
		}
	}
	SET_CFLG(GET_XFLG());
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	{
		int cycles = 2;
		cycles += 2 * ccnt;
		do_cycles_ce000_internal(cycles);
	}
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((val) & 0xffff);
	m68k_incpci(2);
	return;
}
/* 6+ (1/0) */
/* 2 0,0   */

/* ROL.W Dn,Dn */
void REGPARAM2 op_e178_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 68;
	CurrentInstrCycles = 6;  
	uae_s16 cnt = m68k_dreg(regs, srcreg);
	uae_s16 data = m68k_dreg(regs, dstreg);
	uae_u32 val = (uae_u16)data;
	CLEAR_CZNV();
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		SET_ZFLG(!(val & 0xffff));
		SET_NFLG(val & 0x8000);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	int ccnt = cnt & 63;
	cnt &= 63;
	if (cnt > 0) {
		uae_u32 loval;
		cnt &= 15;
		loval = val >> (16 - cnt);
		val <<= cnt;
		val |= loval;
		val &= 0xffff;
		SET_CFLG(val & 1);
	}
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	{
		int cycles = 2;
		cycles += 2 * ccnt;
		do_cycles_ce000_internal(cycles);
	}
	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((val) & 0xffff);
	m68k_incpci(2);
	return;
}
/* 6+ (1/0) */
/* 2 0,0   */

/* ASLQ.L #<data>,Dn */
void REGPARAM2 op_e180_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 65;
	CurrentInstrCycles = 8;  
	uae_u32 cnt = srcreg;
	uae_s32 data = m68k_dreg(regs, dstreg);
	uae_u32 val = data;
	CLEAR_CZNV();
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		SET_NFLG(val & 0x8000);
		SET_ZFLG(!(val & 0xffff));
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	int ccnt = cnt & 63;
	cnt &= 63;
	if (cnt >= 32) {
		SET_VFLG(val != 0);
		SET_CFLG(cnt == 32 ? val & 1 : 0);
		COPY_CARRY();
		val = 0;
	} else {
		uae_u32 mask = (0xffffffff << (31 - cnt)) & 0xffffffff;
		SET_VFLG((val & mask) != mask && (val & mask) != 0);
		val <<= cnt - 1;
		SET_CFLG((val & 0x80000000) >> 31);
		COPY_CARRY();
		val <<= 1;
		val &= 0xffffffff;
	}
	SET_ZFLG(((uae_s32)(val)) == 0);
	SET_NFLG(((uae_s32)(val)) < 0);
	{
		int cycles = 4;
		cycles += 2 * ccnt;
		do_cycles_ce000_internal(cycles);
	}
	m68k_dreg(regs, dstreg) = (val);
	m68k_incpci(2);
	return;
}
/* 8+ (1/0) */
/* 2 0,0   */

/* LSLQ.L #<data>,Dn */
void REGPARAM2 op_e188_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 67;
	CurrentInstrCycles = 8;  
	uae_u32 cnt = srcreg;
	uae_s32 data = m68k_dreg(regs, dstreg);
	uae_u32 val = data;
	CLEAR_CZNV();
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		SET_NFLG(val & 0x8000);
		SET_ZFLG(!(val & 0xffff));
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	int ccnt = cnt & 63;
	cnt &= 63;
	if (cnt >= 32) {
		SET_CFLG(cnt == 32 ? val & 1 : 0);
		COPY_CARRY();
		val = 0;
	} else {
		val <<= (cnt - 1);
		SET_CFLG((val & 0x80000000) >> 31);
		COPY_CARRY();
		val <<= 1;
		val &= 0xffffffff;
	}
	SET_ZFLG(((uae_s32)(val)) == 0);
	SET_NFLG(((uae_s32)(val)) < 0);
	{
		int cycles = 4;
		cycles += 2 * ccnt;
		do_cycles_ce000_internal(cycles);
	}
	m68k_dreg(regs, dstreg) = (val);
	m68k_incpci(2);
	return;
}
/* 8+ (1/0) */
/* 2 0,0   */

/* ROXLQ.L #<data>,Dn */
void REGPARAM2 op_e190_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 70;
	CurrentInstrCycles = 8;  
	uae_u32 cnt = srcreg;
	uae_s32 data = m68k_dreg(regs, dstreg);
	uae_u32 val = data;
	CLEAR_CZNV();
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		SET_NFLG(val & 0x8000);
		SET_ZFLG(!(val & 0xffff));
		SET_CFLG(GET_XFLG());
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	int ccnt = cnt & 63;
	cnt &= 63;
	{
		cnt--;
		{
			uae_u32 carry;
			uae_u32 loval = val >> (31 - cnt);
			carry = loval & 1;
			val = (((val << 1) | GET_XFLG()) << cnt) | (loval >> 1);
			SET_XFLG(carry);
			val &= 0xffffffff;
		}
	}
	SET_CFLG(GET_XFLG());
	SET_ZFLG(((uae_s32)(val)) == 0);
	SET_NFLG(((uae_s32)(val)) < 0);
	{
		int cycles = 4;
		cycles += 2 * ccnt;
		do_cycles_ce000_internal(cycles);
	}
	m68k_dreg(regs, dstreg) = (val);
	m68k_incpci(2);
	return;
}
/* 8+ (1/0) */
/* 2 0,0   */

/* ROLQ.L #<data>,Dn */
void REGPARAM2 op_e198_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 68;
	CurrentInstrCycles = 8;  
	uae_u32 cnt = srcreg;
	uae_s32 data = m68k_dreg(regs, dstreg);
	uae_u32 val = data;
	CLEAR_CZNV();
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		SET_NFLG(val & 0x8000);
		SET_ZFLG(!(val & 0xffff));
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	int ccnt = cnt & 63;
	cnt &= 63;
	{
		uae_u32 loval;
		cnt &= 31;
		loval = val >> (32 - cnt);
		val <<= cnt;
		val |= loval;
		val &= 0xffffffff;
		SET_CFLG(val & 1);
	}
	SET_ZFLG(((uae_s32)(val)) == 0);
	SET_NFLG(((uae_s32)(val)) < 0);
	{
		int cycles = 4;
		cycles += 2 * ccnt;
		do_cycles_ce000_internal(cycles);
	}
	m68k_dreg(regs, dstreg) = (val);
	m68k_incpci(2);
	return;
}
/* 8+ (1/0) */
/* 2 0,0   */

/* ASL.L Dn,Dn */
void REGPARAM2 op_e1a0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 65;
	CurrentInstrCycles = 8;  
	uae_s32 cnt = m68k_dreg(regs, srcreg);
	uae_s32 data = m68k_dreg(regs, dstreg);
	uae_u32 val = data;
	CLEAR_CZNV();
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		SET_NFLG(val & 0x8000);
		SET_ZFLG(!(val & 0xffff));
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	int ccnt = cnt & 63;
	cnt &= 63;
	if (cnt >= 32) {
		SET_VFLG(val != 0);
		SET_CFLG(cnt == 32 ? val & 1 : 0);
		COPY_CARRY();
		val = 0;
	} else if (cnt > 0) {
		uae_u32 mask = (0xffffffff << (31 - cnt)) & 0xffffffff;
		SET_VFLG((val & mask) != mask && (val & mask) != 0);
		val <<= cnt - 1;
		SET_CFLG((val & 0x80000000) >> 31);
		COPY_CARRY();
		val <<= 1;
		val &= 0xffffffff;
	}
	SET_ZFLG(((uae_s32)(val)) == 0);
	SET_NFLG(((uae_s32)(val)) < 0);
	{
		int cycles = 4;
		cycles += 2 * ccnt;
		do_cycles_ce000_internal(cycles);
	}
	m68k_dreg(regs, dstreg) = (val);
	m68k_incpci(2);
	return;
}
/* 8+ (1/0) */
/* 2 0,0   */

/* LSL.L Dn,Dn */
void REGPARAM2 op_e1a8_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 67;
	CurrentInstrCycles = 8;  
	uae_s32 cnt = m68k_dreg(regs, srcreg);
	uae_s32 data = m68k_dreg(regs, dstreg);
	uae_u32 val = data;
	CLEAR_CZNV();
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		SET_NFLG(val & 0x8000);
		SET_ZFLG(!(val & 0xffff));
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	int ccnt = cnt & 63;
	cnt &= 63;
	if (cnt >= 32) {
		SET_CFLG(cnt == 32 ? val & 1 : 0);
		COPY_CARRY();
		val = 0;
	} else if (cnt > 0) {
		val <<= (cnt - 1);
		SET_CFLG((val & 0x80000000) >> 31);
		COPY_CARRY();
		val <<= 1;
		val &= 0xffffffff;
	}
	SET_ZFLG(((uae_s32)(val)) == 0);
	SET_NFLG(((uae_s32)(val)) < 0);
	{
		int cycles = 4;
		cycles += 2 * ccnt;
		do_cycles_ce000_internal(cycles);
	}
	m68k_dreg(regs, dstreg) = (val);
	m68k_incpci(2);
	return;
}
/* 8+ (1/0) */
/* 2 0,0   */

/* ROXL.L Dn,Dn */
void REGPARAM2 op_e1b0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 70;
	CurrentInstrCycles = 8;  
	uae_s32 cnt = m68k_dreg(regs, srcreg);
	uae_s32 data = m68k_dreg(regs, dstreg);
	uae_u32 val = data;
	CLEAR_CZNV();
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		SET_NFLG(val & 0x8000);
		SET_ZFLG(!(val & 0xffff));
		SET_CFLG(GET_XFLG());
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	int ccnt = cnt & 63;
	cnt &= 63;
	if (cnt >= 33) cnt -= 33;
	if (cnt > 0) {
		cnt--;
		{
			uae_u32 carry;
			uae_u32 loval = val >> (31 - cnt);
			carry = loval & 1;
			val = (((val << 1) | GET_XFLG()) << cnt) | (loval >> 1);
			SET_XFLG(carry);
			val &= 0xffffffff;
		}
	}
	SET_CFLG(GET_XFLG());
	SET_ZFLG(((uae_s32)(val)) == 0);
	SET_NFLG(((uae_s32)(val)) < 0);
	{
		int cycles = 4;
		cycles += 2 * ccnt;
		do_cycles_ce000_internal(cycles);
	}
	m68k_dreg(regs, dstreg) = (val);
	m68k_incpci(2);
	return;
}
/* 8+ (1/0) */
/* 2 0,0   */

/* ROL.L Dn,Dn */
void REGPARAM2 op_e1b8_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = ((real_opcode >> 9) & 7);
	uae_u32 dstreg = real_opcode & 7;
	OpcodeFamily = 68;
	CurrentInstrCycles = 8;  
	uae_s32 cnt = m68k_dreg(regs, srcreg);
	uae_s32 data = m68k_dreg(regs, dstreg);
	uae_u32 val = data;
	CLEAR_CZNV();
	ipl_fetch_next_pre();
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		SET_NFLG(val & 0x8000);
		SET_ZFLG(!(val & 0xffff));
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	int ccnt = cnt & 63;
	cnt &= 63;
	if (cnt > 0) {
		uae_u32 loval;
		cnt &= 31;
		loval = val >> (32 - cnt);
		val <<= cnt;
		val |= loval;
		val &= 0xffffffff;
		SET_CFLG(val & 1);
	}
	SET_ZFLG(((uae_s32)(val)) == 0);
	SET_NFLG(((uae_s32)(val)) < 0);
	{
		int cycles = 4;
		cycles += 2 * ccnt;
		do_cycles_ce000_internal(cycles);
	}
	m68k_dreg(regs, dstreg) = (val);
	m68k_incpci(2);
	return;
}
/* 8+ (1/0) */
/* 2 0,0   */

/* ASLW.W (An) */
void REGPARAM2 op_e1d0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 73;
	CurrentInstrCycles = 12; 
	uaecptr dataa;
	dataa = m68k_areg(regs, srcreg);
	if (dataa & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dataa, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 data = x_get_word(dataa);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dataa + 0, 0x1, 1);
		return;
	}
	uae_u32 val = (uae_u16)data;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();
		SET_CFLG(val & 0x8000);
		SET_ZFLG(!(val & 0x7fff));
		SET_NFLG(val & 0x4000);
		SET_XFLG(GET_CFLG());
		SET_VFLG((val & 0x8000) != ((val << 1) & 0x8000));
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	uae_u32 sign = 0x8000 & val;
	uae_u32 sign2;
	val <<= 1;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	sign2 = 0x8000 & val;
	SET_CFLG(sign != 0);
	COPY_CARRY();
	SET_VFLG(GET_VFLG() | (sign2 != sign));
	x_put_word(dataa, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dataa + 0, 0x1, val, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 12 (2/1) */
/* 2 0,0   */

/* ASLW.W (An)+ */
void REGPARAM2 op_e1d8_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 73;
	CurrentInstrCycles = 12; 
	uaecptr dataa;
	dataa = m68k_areg(regs, srcreg);
	if (dataa & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dataa, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 data = x_get_word(dataa);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) += 2 + 0;
		exception2_read(opcode, dataa + 0, 0x1, 1);
		return;
	}
	m68k_areg(regs, srcreg) += 2;
	uae_u32 val = (uae_u16)data;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();
		SET_CFLG(val & 0x8000);
		SET_ZFLG(!(val & 0x7fff));
		SET_NFLG(val & 0x4000);
		SET_XFLG(GET_CFLG());
		SET_VFLG((val & 0x8000) != ((val << 1) & 0x8000));
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	uae_u32 sign = 0x8000 & val;
	uae_u32 sign2;
	val <<= 1;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	sign2 = 0x8000 & val;
	SET_CFLG(sign != 0);
	COPY_CARRY();
	SET_VFLG(GET_VFLG() | (sign2 != sign));
	x_put_word(dataa, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dataa + 0, 0x1, val, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 12 (2/1) */
/* 2 0,0   */

/* ASLW.W -(An) */
void REGPARAM2 op_e1e0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 73;
	CurrentInstrCycles = 14; 
	uaecptr dataa;
	dataa = m68k_areg(regs, srcreg) - 2;
	do_cycles_ce000_internal(2);
	if (dataa & 1) {
		m68k_incpci(4);
		m68k_areg(regs, srcreg) = dataa;
		exception3_read_access(opcode, dataa, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 data = x_get_word(dataa);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, srcreg) = dataa;
		exception2_read(opcode, dataa + 0, 0x1, 1);
		return;
	}
	m68k_areg(regs, srcreg) = dataa;
	uae_u32 val = (uae_u16)data;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();
		SET_CFLG(val & 0x8000);
		SET_ZFLG(!(val & 0x7fff));
		SET_NFLG(val & 0x4000);
		SET_XFLG(GET_CFLG());
		SET_VFLG((val & 0x8000) != ((val << 1) & 0x8000));
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	uae_u32 sign = 0x8000 & val;
	uae_u32 sign2;
	val <<= 1;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	sign2 = 0x8000 & val;
	SET_CFLG(sign != 0);
	COPY_CARRY();
	SET_VFLG(GET_VFLG() | (sign2 != sign));
	x_put_word(dataa, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dataa + 0, 0x1, val, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 14 (2/1) */
/* 2 0,0   */

/* ASLW.W (d16,An) */
void REGPARAM2 op_e1e8_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 73;
	CurrentInstrCycles = 16; 
	uaecptr dataa;
	dataa = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (dataa & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dataa, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 data = x_get_word(dataa);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dataa + 0, 0x1, 1);
		return;
	}
	uae_u32 val = (uae_u16)data;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();
		SET_CFLG(val & 0x8000);
		SET_ZFLG(!(val & 0x7fff));
		SET_NFLG(val & 0x4000);
		SET_XFLG(GET_CFLG());
		SET_VFLG((val & 0x8000) != ((val << 1) & 0x8000));
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	uae_u32 sign = 0x8000 & val;
	uae_u32 sign2;
	val <<= 1;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	sign2 = 0x8000 & val;
	SET_CFLG(sign != 0);
	COPY_CARRY();
	SET_VFLG(GET_VFLG() | (sign2 != sign));
	x_put_word(dataa, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dataa + 0, 0x1, val, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* ASLW.W (d8,An,Xn) */
void REGPARAM2 op_e1f0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 73;
	CurrentInstrCycles = 18; 
	uaecptr dataa;
	do_cycles_ce000_internal(2);
	dataa = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (dataa & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dataa, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 data = x_get_word(dataa);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dataa + 0, 0x1, 1);
		return;
	}
	uae_u32 val = (uae_u16)data;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();
		SET_CFLG(val & 0x8000);
		SET_ZFLG(!(val & 0x7fff));
		SET_NFLG(val & 0x4000);
		SET_XFLG(GET_CFLG());
		SET_VFLG((val & 0x8000) != ((val << 1) & 0x8000));
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	uae_u32 sign = 0x8000 & val;
	uae_u32 sign2;
	val <<= 1;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	sign2 = 0x8000 & val;
	SET_CFLG(sign != 0);
	COPY_CARRY();
	SET_VFLG(GET_VFLG() | (sign2 != sign));
	x_put_word(dataa, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dataa + 0, 0x1, val, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 18 (3/1) */
/* 4 4,0   */

/* ASLW.W (xxx).W */
void REGPARAM2 op_e1f8_14_ff(uae_u32 opcode)
{
	OpcodeFamily = 73;
	CurrentInstrCycles = 16; 
	uaecptr dataa;
	dataa = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	if (dataa & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, dataa, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 data = x_get_word(dataa);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dataa + 0, 0x1, 1);
		return;
	}
	uae_u32 val = (uae_u16)data;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();
		SET_CFLG(val & 0x8000);
		SET_ZFLG(!(val & 0x7fff));
		SET_NFLG(val & 0x4000);
		SET_XFLG(GET_CFLG());
		SET_VFLG((val & 0x8000) != ((val << 1) & 0x8000));
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	uae_u32 sign = 0x8000 & val;
	uae_u32 sign2;
	val <<= 1;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	sign2 = 0x8000 & val;
	SET_CFLG(sign != 0);
	COPY_CARRY();
	SET_VFLG(GET_VFLG() | (sign2 != sign));
	x_put_word(dataa, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dataa + 0, 0x1, val, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* ASLW.W (xxx).L */
void REGPARAM2 op_e1f9_14_ff(uae_u32 opcode)
{
	OpcodeFamily = 73;
	CurrentInstrCycles = 20; 
	uaecptr dataa;
	dataa = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	dataa |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	if (dataa & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, dataa, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 data = x_get_word(dataa);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dataa + 0, 0x1, 1);
		return;
	}
	uae_u32 val = (uae_u16)data;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();
		SET_CFLG(val & 0x8000);
		SET_ZFLG(!(val & 0x7fff));
		SET_NFLG(val & 0x4000);
		SET_XFLG(GET_CFLG());
		SET_VFLG((val & 0x8000) != ((val << 1) & 0x8000));
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	opcode = regs.ir;
	uae_u32 sign = 0x8000 & val;
	uae_u32 sign2;
	val <<= 1;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	sign2 = 0x8000 & val;
	SET_CFLG(sign != 0);
	COPY_CARRY();
	SET_VFLG(GET_VFLG() | (sign2 != sign));
	x_put_word(dataa, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dataa + 0, 0x1, val, 1);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 20 (4/1) */
/* 6 0,0   */

/* LSRW.W (An) */
void REGPARAM2 op_e2d0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 74;
	CurrentInstrCycles = 12; 
	uaecptr dataa;
	dataa = m68k_areg(regs, srcreg);
	if (dataa & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dataa, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 data = x_get_word(dataa);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dataa + 0, 0x1, 1);
		return;
	}
	uae_u32 val = (uae_u16)data;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();
		SET_CFLG(val & 1);
		SET_ZFLG(!(val & 0xfffe));
		SET_NFLG(0);
		SET_XFLG(GET_CFLG());
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	uae_u32 carry = val & 1;
	val >>= 1;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	SET_CFLG(carry);
	COPY_CARRY();
	x_put_word(dataa, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dataa + 0, 0x1, val, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 12 (2/1) */
/* 2 0,0   */

/* LSRW.W (An)+ */
void REGPARAM2 op_e2d8_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 74;
	CurrentInstrCycles = 12; 
	uaecptr dataa;
	dataa = m68k_areg(regs, srcreg);
	if (dataa & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dataa, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 data = x_get_word(dataa);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) += 2 + 0;
		exception2_read(opcode, dataa + 0, 0x1, 1);
		return;
	}
	m68k_areg(regs, srcreg) += 2;
	uae_u32 val = (uae_u16)data;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();
		SET_CFLG(val & 1);
		SET_ZFLG(!(val & 0xfffe));
		SET_NFLG(0);
		SET_XFLG(GET_CFLG());
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	uae_u32 carry = val & 1;
	val >>= 1;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	SET_CFLG(carry);
	COPY_CARRY();
	x_put_word(dataa, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dataa + 0, 0x1, val, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 12 (2/1) */
/* 2 0,0   */

/* LSRW.W -(An) */
void REGPARAM2 op_e2e0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 74;
	CurrentInstrCycles = 14; 
	uaecptr dataa;
	dataa = m68k_areg(regs, srcreg) - 2;
	do_cycles_ce000_internal(2);
	if (dataa & 1) {
		m68k_incpci(4);
		m68k_areg(regs, srcreg) = dataa;
		exception3_read_access(opcode, dataa, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 data = x_get_word(dataa);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, srcreg) = dataa;
		exception2_read(opcode, dataa + 0, 0x1, 1);
		return;
	}
	m68k_areg(regs, srcreg) = dataa;
	uae_u32 val = (uae_u16)data;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();
		SET_CFLG(val & 1);
		SET_ZFLG(!(val & 0xfffe));
		SET_NFLG(0);
		SET_XFLG(GET_CFLG());
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	uae_u32 carry = val & 1;
	val >>= 1;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	SET_CFLG(carry);
	COPY_CARRY();
	x_put_word(dataa, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dataa + 0, 0x1, val, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 14 (2/1) */
/* 2 0,0   */

/* LSRW.W (d16,An) */
void REGPARAM2 op_e2e8_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 74;
	CurrentInstrCycles = 16; 
	uaecptr dataa;
	dataa = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (dataa & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dataa, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 data = x_get_word(dataa);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dataa + 0, 0x1, 1);
		return;
	}
	uae_u32 val = (uae_u16)data;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();
		SET_CFLG(val & 1);
		SET_ZFLG(!(val & 0xfffe));
		SET_NFLG(0);
		SET_XFLG(GET_CFLG());
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	uae_u32 carry = val & 1;
	val >>= 1;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	SET_CFLG(carry);
	COPY_CARRY();
	x_put_word(dataa, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dataa + 0, 0x1, val, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* LSRW.W (d8,An,Xn) */
void REGPARAM2 op_e2f0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 74;
	CurrentInstrCycles = 18; 
	uaecptr dataa;
	do_cycles_ce000_internal(2);
	dataa = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (dataa & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dataa, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 data = x_get_word(dataa);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dataa + 0, 0x1, 1);
		return;
	}
	uae_u32 val = (uae_u16)data;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();
		SET_CFLG(val & 1);
		SET_ZFLG(!(val & 0xfffe));
		SET_NFLG(0);
		SET_XFLG(GET_CFLG());
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	uae_u32 carry = val & 1;
	val >>= 1;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	SET_CFLG(carry);
	COPY_CARRY();
	x_put_word(dataa, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dataa + 0, 0x1, val, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 18 (3/1) */
/* 4 4,0   */

/* LSRW.W (xxx).W */
void REGPARAM2 op_e2f8_14_ff(uae_u32 opcode)
{
	OpcodeFamily = 74;
	CurrentInstrCycles = 16; 
	uaecptr dataa;
	dataa = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	if (dataa & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, dataa, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 data = x_get_word(dataa);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dataa + 0, 0x1, 1);
		return;
	}
	uae_u32 val = (uae_u16)data;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();
		SET_CFLG(val & 1);
		SET_ZFLG(!(val & 0xfffe));
		SET_NFLG(0);
		SET_XFLG(GET_CFLG());
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	uae_u32 carry = val & 1;
	val >>= 1;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	SET_CFLG(carry);
	COPY_CARRY();
	x_put_word(dataa, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dataa + 0, 0x1, val, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* LSRW.W (xxx).L */
void REGPARAM2 op_e2f9_14_ff(uae_u32 opcode)
{
	OpcodeFamily = 74;
	CurrentInstrCycles = 20; 
	uaecptr dataa;
	dataa = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	dataa |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	if (dataa & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, dataa, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 data = x_get_word(dataa);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dataa + 0, 0x1, 1);
		return;
	}
	uae_u32 val = (uae_u16)data;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();
		SET_CFLG(val & 1);
		SET_ZFLG(!(val & 0xfffe));
		SET_NFLG(0);
		SET_XFLG(GET_CFLG());
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	opcode = regs.ir;
	uae_u32 carry = val & 1;
	val >>= 1;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	SET_CFLG(carry);
	COPY_CARRY();
	x_put_word(dataa, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dataa + 0, 0x1, val, 1);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 20 (4/1) */
/* 6 0,0   */

/* LSLW.W (An) */
void REGPARAM2 op_e3d0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 75;
	CurrentInstrCycles = 12; 
	uaecptr dataa;
	dataa = m68k_areg(regs, srcreg);
	if (dataa & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dataa, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 data = x_get_word(dataa);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dataa + 0, 0x1, 1);
		return;
	}
	uae_u16 val = data;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();
		SET_CFLG(val & 0x8000);
		SET_ZFLG(!(val & 0x7fff));
		SET_NFLG(val & 0x4000);
		SET_XFLG(GET_CFLG());
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	uae_u32 carry = val & 0x8000;
	val <<= 1;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	SET_CFLG(carry >> 15);
	COPY_CARRY();
	x_put_word(dataa, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dataa + 0, 0x1, val, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 12 (2/1) */
/* 2 0,0   */

/* LSLW.W (An)+ */
void REGPARAM2 op_e3d8_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 75;
	CurrentInstrCycles = 12; 
	uaecptr dataa;
	dataa = m68k_areg(regs, srcreg);
	if (dataa & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dataa, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 data = x_get_word(dataa);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) += 2 + 0;
		exception2_read(opcode, dataa + 0, 0x1, 1);
		return;
	}
	m68k_areg(regs, srcreg) += 2;
	uae_u16 val = data;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();
		SET_CFLG(val & 0x8000);
		SET_ZFLG(!(val & 0x7fff));
		SET_NFLG(val & 0x4000);
		SET_XFLG(GET_CFLG());
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	uae_u32 carry = val & 0x8000;
	val <<= 1;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	SET_CFLG(carry >> 15);
	COPY_CARRY();
	x_put_word(dataa, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dataa + 0, 0x1, val, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 12 (2/1) */
/* 2 0,0   */

/* LSLW.W -(An) */
void REGPARAM2 op_e3e0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 75;
	CurrentInstrCycles = 14; 
	uaecptr dataa;
	dataa = m68k_areg(regs, srcreg) - 2;
	do_cycles_ce000_internal(2);
	if (dataa & 1) {
		m68k_incpci(4);
		m68k_areg(regs, srcreg) = dataa;
		exception3_read_access(opcode, dataa, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 data = x_get_word(dataa);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, srcreg) = dataa;
		exception2_read(opcode, dataa + 0, 0x1, 1);
		return;
	}
	m68k_areg(regs, srcreg) = dataa;
	uae_u16 val = data;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();
		SET_CFLG(val & 0x8000);
		SET_ZFLG(!(val & 0x7fff));
		SET_NFLG(val & 0x4000);
		SET_XFLG(GET_CFLG());
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	uae_u32 carry = val & 0x8000;
	val <<= 1;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	SET_CFLG(carry >> 15);
	COPY_CARRY();
	x_put_word(dataa, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dataa + 0, 0x1, val, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 14 (2/1) */
/* 2 0,0   */

/* LSLW.W (d16,An) */
void REGPARAM2 op_e3e8_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 75;
	CurrentInstrCycles = 16; 
	uaecptr dataa;
	dataa = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (dataa & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dataa, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 data = x_get_word(dataa);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dataa + 0, 0x1, 1);
		return;
	}
	uae_u16 val = data;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();
		SET_CFLG(val & 0x8000);
		SET_ZFLG(!(val & 0x7fff));
		SET_NFLG(val & 0x4000);
		SET_XFLG(GET_CFLG());
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	uae_u32 carry = val & 0x8000;
	val <<= 1;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	SET_CFLG(carry >> 15);
	COPY_CARRY();
	x_put_word(dataa, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dataa + 0, 0x1, val, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* LSLW.W (d8,An,Xn) */
void REGPARAM2 op_e3f0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 75;
	CurrentInstrCycles = 18; 
	uaecptr dataa;
	do_cycles_ce000_internal(2);
	dataa = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (dataa & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dataa, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 data = x_get_word(dataa);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dataa + 0, 0x1, 1);
		return;
	}
	uae_u16 val = data;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();
		SET_CFLG(val & 0x8000);
		SET_ZFLG(!(val & 0x7fff));
		SET_NFLG(val & 0x4000);
		SET_XFLG(GET_CFLG());
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	uae_u32 carry = val & 0x8000;
	val <<= 1;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	SET_CFLG(carry >> 15);
	COPY_CARRY();
	x_put_word(dataa, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dataa + 0, 0x1, val, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 18 (3/1) */
/* 4 4,0   */

/* LSLW.W (xxx).W */
void REGPARAM2 op_e3f8_14_ff(uae_u32 opcode)
{
	OpcodeFamily = 75;
	CurrentInstrCycles = 16; 
	uaecptr dataa;
	dataa = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	if (dataa & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, dataa, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 data = x_get_word(dataa);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dataa + 0, 0x1, 1);
		return;
	}
	uae_u16 val = data;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();
		SET_CFLG(val & 0x8000);
		SET_ZFLG(!(val & 0x7fff));
		SET_NFLG(val & 0x4000);
		SET_XFLG(GET_CFLG());
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	uae_u32 carry = val & 0x8000;
	val <<= 1;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	SET_CFLG(carry >> 15);
	COPY_CARRY();
	x_put_word(dataa, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dataa + 0, 0x1, val, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* LSLW.W (xxx).L */
void REGPARAM2 op_e3f9_14_ff(uae_u32 opcode)
{
	OpcodeFamily = 75;
	CurrentInstrCycles = 20; 
	uaecptr dataa;
	dataa = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	dataa |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	if (dataa & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, dataa, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 data = x_get_word(dataa);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dataa + 0, 0x1, 1);
		return;
	}
	uae_u16 val = data;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();
		SET_CFLG(val & 0x8000);
		SET_ZFLG(!(val & 0x7fff));
		SET_NFLG(val & 0x4000);
		SET_XFLG(GET_CFLG());
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	opcode = regs.ir;
	uae_u32 carry = val & 0x8000;
	val <<= 1;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	SET_CFLG(carry >> 15);
	COPY_CARRY();
	x_put_word(dataa, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dataa + 0, 0x1, val, 1);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 20 (4/1) */
/* 6 0,0   */

/* ROXRW.W (An) */
void REGPARAM2 op_e4d0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 79;
	CurrentInstrCycles = 12; 
	uaecptr dataa;
	dataa = m68k_areg(regs, srcreg);
	if (dataa & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dataa, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 data = x_get_word(dataa);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dataa + 0, 0x1, 1);
		return;
	}
	uae_u16 val = data;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();SET_CFLG(val & 1);
		SET_ZFLG(!((val &0x7ffe) | GET_XFLG()))
		;SET_NFLG(GET_XFLG())
		;SET_XFLG(GET_CFLG());
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	uae_u32 carry = val & 1;
	val >>= 1;
	if (GET_XFLG()) val |= 0x8000;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	SET_CFLG(carry);
	COPY_CARRY();
	x_put_word(dataa, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dataa + 0, 0x1, val, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 12 (2/1) */
/* 2 0,0   */

/* ROXRW.W (An)+ */
void REGPARAM2 op_e4d8_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 79;
	CurrentInstrCycles = 12; 
	uaecptr dataa;
	dataa = m68k_areg(regs, srcreg);
	if (dataa & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dataa, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 data = x_get_word(dataa);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) += 2 + 0;
		exception2_read(opcode, dataa + 0, 0x1, 1);
		return;
	}
	m68k_areg(regs, srcreg) += 2;
	uae_u16 val = data;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();SET_CFLG(val & 1);
		SET_ZFLG(!((val &0x7ffe) | GET_XFLG()))
		;SET_NFLG(GET_XFLG())
		;SET_XFLG(GET_CFLG());
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	uae_u32 carry = val & 1;
	val >>= 1;
	if (GET_XFLG()) val |= 0x8000;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	SET_CFLG(carry);
	COPY_CARRY();
	x_put_word(dataa, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dataa + 0, 0x1, val, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 12 (2/1) */
/* 2 0,0   */

/* ROXRW.W -(An) */
void REGPARAM2 op_e4e0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 79;
	CurrentInstrCycles = 14; 
	uaecptr dataa;
	dataa = m68k_areg(regs, srcreg) - 2;
	do_cycles_ce000_internal(2);
	if (dataa & 1) {
		m68k_incpci(4);
		m68k_areg(regs, srcreg) = dataa;
		exception3_read_access(opcode, dataa, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 data = x_get_word(dataa);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, srcreg) = dataa;
		exception2_read(opcode, dataa + 0, 0x1, 1);
		return;
	}
	m68k_areg(regs, srcreg) = dataa;
	uae_u16 val = data;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();SET_CFLG(val & 1);
		SET_ZFLG(!((val &0x7ffe) | GET_XFLG()))
		;SET_NFLG(GET_XFLG())
		;SET_XFLG(GET_CFLG());
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	uae_u32 carry = val & 1;
	val >>= 1;
	if (GET_XFLG()) val |= 0x8000;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	SET_CFLG(carry);
	COPY_CARRY();
	x_put_word(dataa, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dataa + 0, 0x1, val, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 14 (2/1) */
/* 2 0,0   */

/* ROXRW.W (d16,An) */
void REGPARAM2 op_e4e8_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 79;
	CurrentInstrCycles = 16; 
	uaecptr dataa;
	dataa = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (dataa & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dataa, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 data = x_get_word(dataa);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dataa + 0, 0x1, 1);
		return;
	}
	uae_u16 val = data;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();SET_CFLG(val & 1);
		SET_ZFLG(!((val &0x7ffe) | GET_XFLG()))
		;SET_NFLG(GET_XFLG())
		;SET_XFLG(GET_CFLG());
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	uae_u32 carry = val & 1;
	val >>= 1;
	if (GET_XFLG()) val |= 0x8000;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	SET_CFLG(carry);
	COPY_CARRY();
	x_put_word(dataa, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dataa + 0, 0x1, val, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* ROXRW.W (d8,An,Xn) */
void REGPARAM2 op_e4f0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 79;
	CurrentInstrCycles = 18; 
	uaecptr dataa;
	do_cycles_ce000_internal(2);
	dataa = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (dataa & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dataa, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 data = x_get_word(dataa);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dataa + 0, 0x1, 1);
		return;
	}
	uae_u16 val = data;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();SET_CFLG(val & 1);
		SET_ZFLG(!((val &0x7ffe) | GET_XFLG()))
		;SET_NFLG(GET_XFLG())
		;SET_XFLG(GET_CFLG());
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	uae_u32 carry = val & 1;
	val >>= 1;
	if (GET_XFLG()) val |= 0x8000;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	SET_CFLG(carry);
	COPY_CARRY();
	x_put_word(dataa, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dataa + 0, 0x1, val, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 18 (3/1) */
/* 4 4,0   */

/* ROXRW.W (xxx).W */
void REGPARAM2 op_e4f8_14_ff(uae_u32 opcode)
{
	OpcodeFamily = 79;
	CurrentInstrCycles = 16; 
	uaecptr dataa;
	dataa = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	if (dataa & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, dataa, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 data = x_get_word(dataa);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dataa + 0, 0x1, 1);
		return;
	}
	uae_u16 val = data;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();SET_CFLG(val & 1);
		SET_ZFLG(!((val &0x7ffe) | GET_XFLG()))
		;SET_NFLG(GET_XFLG())
		;SET_XFLG(GET_CFLG());
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	uae_u32 carry = val & 1;
	val >>= 1;
	if (GET_XFLG()) val |= 0x8000;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	SET_CFLG(carry);
	COPY_CARRY();
	x_put_word(dataa, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dataa + 0, 0x1, val, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* ROXRW.W (xxx).L */
void REGPARAM2 op_e4f9_14_ff(uae_u32 opcode)
{
	OpcodeFamily = 79;
	CurrentInstrCycles = 20; 
	uaecptr dataa;
	dataa = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	dataa |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	if (dataa & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, dataa, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 data = x_get_word(dataa);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dataa + 0, 0x1, 1);
		return;
	}
	uae_u16 val = data;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();SET_CFLG(val & 1);
		SET_ZFLG(!((val &0x7ffe) | GET_XFLG()))
		;SET_NFLG(GET_XFLG())
		;SET_XFLG(GET_CFLG());
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	opcode = regs.ir;
	uae_u32 carry = val & 1;
	val >>= 1;
	if (GET_XFLG()) val |= 0x8000;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	SET_CFLG(carry);
	COPY_CARRY();
	x_put_word(dataa, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dataa + 0, 0x1, val, 1);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 20 (4/1) */
/* 6 0,0   */

/* ROXLW.W (An) */
void REGPARAM2 op_e5d0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 78;
	CurrentInstrCycles = 12; 
	uaecptr dataa;
	dataa = m68k_areg(regs, srcreg);
	if (dataa & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dataa, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 data = x_get_word(dataa);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dataa + 0, 0x1, 1);
		return;
	}
	uae_u16 val = data;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();
		SET_CFLG(val & 0x8000);
		SET_ZFLG(!((val & 0x7fff) | GET_XFLG()));
		SET_NFLG(val & 0x4000);
		SET_XFLG(GET_CFLG());
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	uae_u32 carry = val & 0x8000;
	val <<= 1;
	if (GET_XFLG()) val |= 1;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	SET_CFLG(carry >> 15);
	COPY_CARRY();
	x_put_word(dataa, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dataa + 0, 0x1, val, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 12 (2/1) */
/* 2 0,0   */

/* ROXLW.W (An)+ */
void REGPARAM2 op_e5d8_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 78;
	CurrentInstrCycles = 12; 
	uaecptr dataa;
	dataa = m68k_areg(regs, srcreg);
	if (dataa & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dataa, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 data = x_get_word(dataa);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) += 2 + 0;
		exception2_read(opcode, dataa + 0, 0x1, 1);
		return;
	}
	m68k_areg(regs, srcreg) += 2;
	uae_u16 val = data;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();
		SET_CFLG(val & 0x8000);
		SET_ZFLG(!((val & 0x7fff) | GET_XFLG()));
		SET_NFLG(val & 0x4000);
		SET_XFLG(GET_CFLG());
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	uae_u32 carry = val & 0x8000;
	val <<= 1;
	if (GET_XFLG()) val |= 1;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	SET_CFLG(carry >> 15);
	COPY_CARRY();
	x_put_word(dataa, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dataa + 0, 0x1, val, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 12 (2/1) */
/* 2 0,0   */

/* ROXLW.W -(An) */
void REGPARAM2 op_e5e0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 78;
	CurrentInstrCycles = 14; 
	uaecptr dataa;
	dataa = m68k_areg(regs, srcreg) - 2;
	do_cycles_ce000_internal(2);
	if (dataa & 1) {
		m68k_incpci(4);
		m68k_areg(regs, srcreg) = dataa;
		exception3_read_access(opcode, dataa, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 data = x_get_word(dataa);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, srcreg) = dataa;
		exception2_read(opcode, dataa + 0, 0x1, 1);
		return;
	}
	m68k_areg(regs, srcreg) = dataa;
	uae_u16 val = data;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();
		SET_CFLG(val & 0x8000);
		SET_ZFLG(!((val & 0x7fff) | GET_XFLG()));
		SET_NFLG(val & 0x4000);
		SET_XFLG(GET_CFLG());
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	uae_u32 carry = val & 0x8000;
	val <<= 1;
	if (GET_XFLG()) val |= 1;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	SET_CFLG(carry >> 15);
	COPY_CARRY();
	x_put_word(dataa, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dataa + 0, 0x1, val, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 14 (2/1) */
/* 2 0,0   */

/* ROXLW.W (d16,An) */
void REGPARAM2 op_e5e8_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 78;
	CurrentInstrCycles = 16; 
	uaecptr dataa;
	dataa = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (dataa & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dataa, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 data = x_get_word(dataa);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dataa + 0, 0x1, 1);
		return;
	}
	uae_u16 val = data;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();
		SET_CFLG(val & 0x8000);
		SET_ZFLG(!((val & 0x7fff) | GET_XFLG()));
		SET_NFLG(val & 0x4000);
		SET_XFLG(GET_CFLG());
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	uae_u32 carry = val & 0x8000;
	val <<= 1;
	if (GET_XFLG()) val |= 1;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	SET_CFLG(carry >> 15);
	COPY_CARRY();
	x_put_word(dataa, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dataa + 0, 0x1, val, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* ROXLW.W (d8,An,Xn) */
void REGPARAM2 op_e5f0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 78;
	CurrentInstrCycles = 18; 
	uaecptr dataa;
	do_cycles_ce000_internal(2);
	dataa = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (dataa & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dataa, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 data = x_get_word(dataa);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dataa + 0, 0x1, 1);
		return;
	}
	uae_u16 val = data;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();
		SET_CFLG(val & 0x8000);
		SET_ZFLG(!((val & 0x7fff) | GET_XFLG()));
		SET_NFLG(val & 0x4000);
		SET_XFLG(GET_CFLG());
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	uae_u32 carry = val & 0x8000;
	val <<= 1;
	if (GET_XFLG()) val |= 1;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	SET_CFLG(carry >> 15);
	COPY_CARRY();
	x_put_word(dataa, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dataa + 0, 0x1, val, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 18 (3/1) */
/* 4 4,0   */

/* ROXLW.W (xxx).W */
void REGPARAM2 op_e5f8_14_ff(uae_u32 opcode)
{
	OpcodeFamily = 78;
	CurrentInstrCycles = 16; 
	uaecptr dataa;
	dataa = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	if (dataa & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, dataa, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 data = x_get_word(dataa);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dataa + 0, 0x1, 1);
		return;
	}
	uae_u16 val = data;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();
		SET_CFLG(val & 0x8000);
		SET_ZFLG(!((val & 0x7fff) | GET_XFLG()));
		SET_NFLG(val & 0x4000);
		SET_XFLG(GET_CFLG());
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	uae_u32 carry = val & 0x8000;
	val <<= 1;
	if (GET_XFLG()) val |= 1;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	SET_CFLG(carry >> 15);
	COPY_CARRY();
	x_put_word(dataa, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dataa + 0, 0x1, val, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* ROXLW.W (xxx).L */
void REGPARAM2 op_e5f9_14_ff(uae_u32 opcode)
{
	OpcodeFamily = 78;
	CurrentInstrCycles = 20; 
	uaecptr dataa;
	dataa = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	dataa |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	if (dataa & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, dataa, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 data = x_get_word(dataa);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dataa + 0, 0x1, 1);
		return;
	}
	uae_u16 val = data;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();
		SET_CFLG(val & 0x8000);
		SET_ZFLG(!((val & 0x7fff) | GET_XFLG()));
		SET_NFLG(val & 0x4000);
		SET_XFLG(GET_CFLG());
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	opcode = regs.ir;
	uae_u32 carry = val & 0x8000;
	val <<= 1;
	if (GET_XFLG()) val |= 1;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	SET_CFLG(carry >> 15);
	COPY_CARRY();
	x_put_word(dataa, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dataa + 0, 0x1, val, 1);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 20 (4/1) */
/* 6 0,0   */

/* RORW.W (An) */
void REGPARAM2 op_e6d0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 77;
	CurrentInstrCycles = 12; 
	uaecptr dataa;
	dataa = m68k_areg(regs, srcreg);
	if (dataa & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dataa, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 data = x_get_word(dataa);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dataa + 0, 0x1, 1);
		return;
	}
	uae_u16 val = data;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();
		SET_CFLG(val & 1);
		SET_ZFLG(!val);
		SET_NFLG(val & 0x0001);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	uae_u32 carry = val & 1;
	val >>= 1;
	if (carry) val |= 0x8000;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	SET_CFLG(carry);
	x_put_word(dataa, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dataa + 0, 0x1, val, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 12 (2/1) */
/* 2 0,0   */

/* RORW.W (An)+ */
void REGPARAM2 op_e6d8_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 77;
	CurrentInstrCycles = 12; 
	uaecptr dataa;
	dataa = m68k_areg(regs, srcreg);
	if (dataa & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dataa, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 data = x_get_word(dataa);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) += 2 + 0;
		exception2_read(opcode, dataa + 0, 0x1, 1);
		return;
	}
	m68k_areg(regs, srcreg) += 2;
	uae_u16 val = data;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();
		SET_CFLG(val & 1);
		SET_ZFLG(!val);
		SET_NFLG(val & 0x0001);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	uae_u32 carry = val & 1;
	val >>= 1;
	if (carry) val |= 0x8000;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	SET_CFLG(carry);
	x_put_word(dataa, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dataa + 0, 0x1, val, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 12 (2/1) */
/* 2 0,0   */

/* RORW.W -(An) */
void REGPARAM2 op_e6e0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 77;
	CurrentInstrCycles = 14; 
	uaecptr dataa;
	dataa = m68k_areg(regs, srcreg) - 2;
	do_cycles_ce000_internal(2);
	if (dataa & 1) {
		m68k_incpci(4);
		m68k_areg(regs, srcreg) = dataa;
		exception3_read_access(opcode, dataa, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 data = x_get_word(dataa);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, srcreg) = dataa;
		exception2_read(opcode, dataa + 0, 0x1, 1);
		return;
	}
	m68k_areg(regs, srcreg) = dataa;
	uae_u16 val = data;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();
		SET_CFLG(val & 1);
		SET_ZFLG(!val);
		SET_NFLG(val & 0x0001);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	uae_u32 carry = val & 1;
	val >>= 1;
	if (carry) val |= 0x8000;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	SET_CFLG(carry);
	x_put_word(dataa, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dataa + 0, 0x1, val, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 14 (2/1) */
/* 2 0,0   */

/* RORW.W (d16,An) */
void REGPARAM2 op_e6e8_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 77;
	CurrentInstrCycles = 16; 
	uaecptr dataa;
	dataa = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (dataa & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dataa, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 data = x_get_word(dataa);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dataa + 0, 0x1, 1);
		return;
	}
	uae_u16 val = data;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();
		SET_CFLG(val & 1);
		SET_ZFLG(!val);
		SET_NFLG(val & 0x0001);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	uae_u32 carry = val & 1;
	val >>= 1;
	if (carry) val |= 0x8000;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	SET_CFLG(carry);
	x_put_word(dataa, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dataa + 0, 0x1, val, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* RORW.W (d8,An,Xn) */
void REGPARAM2 op_e6f0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 77;
	CurrentInstrCycles = 18; 
	uaecptr dataa;
	do_cycles_ce000_internal(2);
	dataa = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (dataa & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dataa, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 data = x_get_word(dataa);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dataa + 0, 0x1, 1);
		return;
	}
	uae_u16 val = data;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();
		SET_CFLG(val & 1);
		SET_ZFLG(!val);
		SET_NFLG(val & 0x0001);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	uae_u32 carry = val & 1;
	val >>= 1;
	if (carry) val |= 0x8000;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	SET_CFLG(carry);
	x_put_word(dataa, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dataa + 0, 0x1, val, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 18 (3/1) */
/* 4 4,0   */

/* RORW.W (xxx).W */
void REGPARAM2 op_e6f8_14_ff(uae_u32 opcode)
{
	OpcodeFamily = 77;
	CurrentInstrCycles = 16; 
	uaecptr dataa;
	dataa = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	if (dataa & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, dataa, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 data = x_get_word(dataa);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dataa + 0, 0x1, 1);
		return;
	}
	uae_u16 val = data;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();
		SET_CFLG(val & 1);
		SET_ZFLG(!val);
		SET_NFLG(val & 0x0001);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	uae_u32 carry = val & 1;
	val >>= 1;
	if (carry) val |= 0x8000;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	SET_CFLG(carry);
	x_put_word(dataa, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dataa + 0, 0x1, val, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* RORW.W (xxx).L */
void REGPARAM2 op_e6f9_14_ff(uae_u32 opcode)
{
	OpcodeFamily = 77;
	CurrentInstrCycles = 20; 
	uaecptr dataa;
	dataa = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	dataa |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	if (dataa & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, dataa, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 data = x_get_word(dataa);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dataa + 0, 0x1, 1);
		return;
	}
	uae_u16 val = data;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();
		SET_CFLG(val & 1);
		SET_ZFLG(!val);
		SET_NFLG(val & 0x0001);
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	opcode = regs.ir;
	uae_u32 carry = val & 1;
	val >>= 1;
	if (carry) val |= 0x8000;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	SET_CFLG(carry);
	x_put_word(dataa, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dataa + 0, 0x1, val, 1);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 20 (4/1) */
/* 6 0,0   */

/* ROLW.W (An) */
void REGPARAM2 op_e7d0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 76;
	CurrentInstrCycles = 12; 
	uaecptr dataa;
	dataa = m68k_areg(regs, srcreg);
	if (dataa & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dataa, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 data = x_get_word(dataa);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dataa + 0, 0x1, 1);
		return;
	}
	uae_u16 val = data;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();SET_CFLG(val & 0x8000);
		SET_ZFLG(!val);
		SET_NFLG(val & 0x4000);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	uae_u32 carry = val & 0x8000;
	val <<= 1;
	if (carry)  val |= 1;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	SET_CFLG(carry >> 15);
	x_put_word(dataa, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dataa + 0, 0x1, val, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 12 (2/1) */
/* 2 0,0   */

/* ROLW.W (An)+ */
void REGPARAM2 op_e7d8_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 76;
	CurrentInstrCycles = 12; 
	uaecptr dataa;
	dataa = m68k_areg(regs, srcreg);
	if (dataa & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dataa, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 data = x_get_word(dataa);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		m68k_areg(regs, srcreg) += 2 + 0;
		exception2_read(opcode, dataa + 0, 0x1, 1);
		return;
	}
	m68k_areg(regs, srcreg) += 2;
	uae_u16 val = data;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();SET_CFLG(val & 0x8000);
		SET_ZFLG(!val);
		SET_NFLG(val & 0x4000);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	uae_u32 carry = val & 0x8000;
	val <<= 1;
	if (carry)  val |= 1;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	SET_CFLG(carry >> 15);
	x_put_word(dataa, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dataa + 0, 0x1, val, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 12 (2/1) */
/* 2 0,0   */

/* ROLW.W -(An) */
void REGPARAM2 op_e7e0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 76;
	CurrentInstrCycles = 14; 
	uaecptr dataa;
	dataa = m68k_areg(regs, srcreg) - 2;
	do_cycles_ce000_internal(2);
	if (dataa & 1) {
		m68k_incpci(4);
		m68k_areg(regs, srcreg) = dataa;
		exception3_read_access(opcode, dataa, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 data = x_get_word(dataa);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		m68k_areg(regs, srcreg) = dataa;
		exception2_read(opcode, dataa + 0, 0x1, 1);
		return;
	}
	m68k_areg(regs, srcreg) = dataa;
	uae_u16 val = data;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();SET_CFLG(val & 0x8000);
		SET_ZFLG(!val);
		SET_NFLG(val & 0x4000);
		exception2_fetch_opcode(opcode, 4, pcoffset);
		return;
	}
	opcode = regs.ir;
	uae_u32 carry = val & 0x8000;
	val <<= 1;
	if (carry)  val |= 1;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	SET_CFLG(carry >> 15);
	x_put_word(dataa, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dataa + 0, 0x1, val, 1);
		return;
	}
	m68k_incpci(2);
	return;
}
/* 14 (2/1) */
/* 2 0,0   */

/* ROLW.W (d16,An) */
void REGPARAM2 op_e7e8_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 76;
	CurrentInstrCycles = 16; 
	uaecptr dataa;
	dataa = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (dataa & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dataa, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 data = x_get_word(dataa);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dataa + 0, 0x1, 1);
		return;
	}
	uae_u16 val = data;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();SET_CFLG(val & 0x8000);
		SET_ZFLG(!val);
		SET_NFLG(val & 0x4000);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	uae_u32 carry = val & 0x8000;
	val <<= 1;
	if (carry)  val |= 1;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	SET_CFLG(carry >> 15);
	x_put_word(dataa, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dataa + 0, 0x1, val, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* ROLW.W (d8,An,Xn) */
void REGPARAM2 op_e7f0_14_ff(uae_u32 opcode)
{
	uae_u32 real_opcode = opcode;
	uae_u32 srcreg = (real_opcode & 7);
	OpcodeFamily = 76;
	CurrentInstrCycles = 18; 
	uaecptr dataa;
	do_cycles_ce000_internal(2);
	dataa = get_disp_ea_000(m68k_areg(regs, srcreg), get_word_ce000_prefetch(4));
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	if (dataa & 1) {
		m68k_incpci(2);
		exception3_read_access(opcode, dataa, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 data = x_get_word(dataa);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(2);
		exception2_read(opcode, dataa + 0, 0x1, 1);
		return;
	}
	uae_u16 val = data;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();SET_CFLG(val & 0x8000);
		SET_ZFLG(!val);
		SET_NFLG(val & 0x4000);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	uae_u32 carry = val & 0x8000;
	val <<= 1;
	if (carry)  val |= 1;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	SET_CFLG(carry >> 15);
	x_put_word(dataa, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dataa + 0, 0x1, val, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 18 (3/1) */
/* 4 4,0   */

/* ROLW.W (xxx).W */
void REGPARAM2 op_e7f8_14_ff(uae_u32 opcode)
{
	OpcodeFamily = 76;
	CurrentInstrCycles = 16; 
	uaecptr dataa;
	dataa = (uae_s32)(uae_s16)get_word_ce000_prefetch(4);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, 0);
		return;
	}
	if (dataa & 1) {
		m68k_incpci(4);
		exception3_read_access(opcode, dataa, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 data = x_get_word(dataa);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(4);
		exception2_read(opcode, dataa + 0, 0x1, 1);
		return;
	}
	uae_u16 val = data;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();SET_CFLG(val & 0x8000);
		SET_ZFLG(!val);
		SET_NFLG(val & 0x4000);
		exception2_fetch_opcode(opcode, 6, pcoffset);
		return;
	}
	opcode = regs.ir;
	uae_u32 carry = val & 0x8000;
	val <<= 1;
	if (carry)  val |= 1;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	SET_CFLG(carry >> 15);
	x_put_word(dataa, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dataa + 0, 0x1, val, 1);
		return;
	}
	m68k_incpci(4);
	return;
}
/* 16 (3/1) */
/* 4 0,0   */

/* ROLW.W (xxx).L */
void REGPARAM2 op_e7f9_14_ff(uae_u32 opcode)
{
	OpcodeFamily = 76;
	CurrentInstrCycles = 20; 
	uaecptr dataa;
	dataa = get_word_ce000_prefetch(4) << 16;
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 4, -2);
		return;
	}
	dataa |= get_word_ce000_prefetch(6);
	if(hardware_bus_error) {
		int pcoffset = 0;
		exception2_fetch(opcode, 6, pcoffset);
		return;
	}
	if (dataa & 1) {
		m68k_incpci(6);
		exception3_read_access(opcode, dataa, 1, 1);
		return;
	}
	ipl_fetch_now();
	uae_s16 data = x_get_word(dataa);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(6);
		exception2_read(opcode, dataa + 0, 0x1, 1);
		return;
	}
	uae_u16 val = data;
	regs.ir = regs.irc;
	opcode |= 0x20000;
	get_word_ce000_prefetch(8);
	if(hardware_bus_error) {
		int pcoffset = 0;
		CLEAR_CZNV();SET_CFLG(val & 0x8000);
		SET_ZFLG(!val);
		SET_NFLG(val & 0x4000);
		exception2_fetch_opcode(opcode, 8, pcoffset);
		return;
	}
	opcode = regs.ir;
	uae_u32 carry = val & 0x8000;
	val <<= 1;
	if (carry)  val |= 1;
	CLEAR_CZNV();
	SET_ZFLG(((uae_s16)(val)) == 0);
	SET_NFLG(((uae_s16)(val)) < 0);
	SET_CFLG(carry >> 15);
	x_put_word(dataa, val);
	if(hardware_bus_error) {
		cpu_bus_rmw=false;
		m68k_incpci(8);
		if (regs.t1) opcode |= 0x10000;
		exception2_write(opcode, dataa + 0, 0x1, val, 1);
		return;
	}
	m68k_incpci(6);
	return;
}
/* 20 (4/1) */
/* 6 0,0   */

