M680x0 Dependent Features
*************************

M680x0 Options
==============

The Motorola 680x0 version of AS has a few machine dependent options:

-march=ARCHITECTURE
     This option specifies a target architecture.  The following architectures are recognized: 68000, 68010, 68020, 68030, 68040, 68060, cpu32, isaa, isaaplus, isab, isac and cfv4e.

-mcpu=CPU
     This option specifies a target cpu.  When used in conjunction with the -march option, the cpu must be within the specified architecture.  Also, the generic features of the architecture are used for instruction generation, rather than those of the specific chip.

-m[no-]68851
-m[no-]68881
-m[no-]div
-m[no-]usp
-m[no-]float
-m[no-]mac
-m[no-]emac

     Enable or disable various architecture specific features.  If a chip or architecture by default supports an option (for instance -march=isaaplus includes the -mdiv option), explicitly disabling the option will override the default.

-l
     You can use the -l option to shorten the size of references to undefined symbols.  If you do not use the -l option, references to undefined symbols are wide enough for a full long (32 bits).  (Since AS cannot know where these symbols end up, AS can only allocate space for the linker to fill in later.  Since AS does not know how far away these symbols are, it allocates as much space as it can.)  If you use this option, the references are only one word wide (16 bits). This may be useful if you want the object file to be as small as possible, and you know that the relevant symbols are always less than 17 bits away.

--register-prefix-optional
     For some configurations, especially those where the compiler normally does not prepend an underscore to the names of user variables, the assembler requires a % before any use of a register name.  This is intended to let the assembler distinguish between C variables and functions named a0 through a7, and so on.  The % is always accepted, but is not required for certain configurations, notably sun3.  The --register-prefix-optional option may be used to permit omitting the % even for configurations for which it is normally required.  If this is done, it will generally be impossible to refer to C variables and functions with the same names as register names.

--bitwise-or
     Normally the character | is treated as a comment character, which means that it can not be used in expressions.  The --bitwise-or option turns | into a normal character.  In this mode, you must either use C style comments, or start comments with a # character at the beginning of a line.

--base-size-default-16  --base-size-default-32
     If you use an addressing mode with a base register without specifying the size, AS will normally use the full 32 bit value. For example, the addressing mode %a0@(%d0) is equivalent to %a0@(%d0:l).  You may use the --base-size-default-16 option to tell AS to default to using the 16 bit value. In this case, %a0@(%d0) is equivalent to %a0@(%d0:w). You may use the --base-size-default-32 option to restore the default behaviour.

--disp-size-default-16  --disp-size-default-32
     If you use an addressing mode with a displacement, and the value of the displacement is not known, AS will normally assume that the value is 32 bits.  For example, if the symbol disp has not been defined, AS will assemble the addressing mode %a0@(disp,%d0) as though disp is a 32 bit value.  You may use the --disp-size-default-16 option to tell AS to instead assume that the displacement is 16 bits.  In this case, AS will assemble %a0@(disp,%d0) as though disp is a 16 bit value.  You may use the --disp-size-default-32 option to restore the default behaviour.

--pcrel
     Always keep branches PC-relative.  In the M680x0 architecture all branches are defined as PC-relative.  However, on some processors they are limited to word displacements maximum.  When AS needs a long branch that is not available, it normally emits an absolute jump instead.  This option disables this substitution.  When this option is given and no long branches are available, only word branches will be emitted.  An error message will be generated if a word branch cannot reach its target.  This option has no effect on 68020 and other processors that have long branches. see Branch Improvement.

-m68000
     AS can assemble code for several different members of the Motorola 680x0 family.  The default depends upon how AS was configured when it was built; normally, the default is to assemble code for the 68020 microprocessor.  The following options may be used to change the default.  These options control which instructions and addressing modes are permitted.  The members of the 680x0 family are very similar.  For detailed information about the differences, see the Motorola manuals.

     -m68000
     -m68ec000
     -m68hc000
     -m68hc001
     -m68008
     -m68302
     -m68306
     -m68307
     -m68322
     -m68356
          Assemble for the 68000. -m68008, -m68302, and so on are synonyms for -m68000, since the chips are the same from the point of view of the assembler.

     -m68010
          Assemble for the 68010.

     -m68020
     -m68ec020
          Assemble for the 68020.  This is normally the default.

     -m68030
     -m68ec030
          Assemble for the 68030.

     -m68040
     -m68ec040
          Assemble for the 68040.

     -m68060
     -m68ec060
          Assemble for the 68060.

     -mcpu32
     -m68330
     -m68331
     -m68332
     -m68333
     -m68334
     -m68336
     -m68340
     -m68341
     -m68349
     -m68360
          Assemble for the CPU32 family of chips.

     -m5200
     -m5202
     -m5204
     -m5206
     -m5206e
     -m521x
     -m5249
     -m528x
     -m5307
     -m5407
     -m547x
     -m548x
     -mcfv4
     -mcfv4e
          Assemble for the ColdFire family of chips.

     -m68881
     -m68882
          Assemble 68881 floating point instructions.  This is the default for the 68020, 68030, and the CPU32.  The 68040 and 68060 always support floating point instructions.

     -mno-68881
          Do not assemble 68881 floating point instructions.  This is the default for 68000 and the 68010.  The 68040 and 68060 always support floating point instructions, even if this option is used.

     -m68851
          Assemble 68851 MMU instructions.  This is the default for the 68020, 68030, and 68060.  The 68040 accepts a somewhat different set of MMU instructions; -m68851 and -m68040 should not be used together.

     -mno-68851
          Do not assemble 68851 MMU instructions.  This is the default for the 68000, 68010, and the CPU32.  The 68040 accepts a somewhat different set of MMU instructions.

Syntax
======

This syntax for the Motorola 680x0 was developed at MIT.

The 680x0 version of AS uses instructions names and syntax compatible with the Sun assembler.  Intervening periods are ignored; for example, movl is equivalent to mov.l.

In the following table APC stands for any of the address registers (%a0 through %a7), the program counter (%pc), the zero-address relative to the program counter (%zpc), a suppressed address register (%za0 through %za7), or it may be omitted entirely.  The use of SIZE means one of w or l, and it may be omitted, along with the leading colon, unless a scale is also specified.  The use of SCALE means one of 1, 2, 4, or 8, and it may always be omitted along with the leading colon.

The following addressing modes are understood:

Immediate
     #NUMBER

Data Register
     %d0 through %d7

Address Register
     %a0 through %a7

     %a7 is also known as %sp, i.e., the Stack Pointer.  %a6 is also known as %fp, the Frame Pointer.

Address Register Indirect
     %a0@ through %a7@

Address Register Postincrement
     %a0@+ through %a7@+

Address Register Predecrement
     %a0@- through %a7@-

Indirect Plus Offset
     APC@(NUMBER)

Index
     APC@(NUMBER,REGISTER:SIZE:SCALE)

     The NUMBER may be omitted.

Postindex
     APC@(NUMBER)@(ONUMBER,REGISTER:SIZE:SCALE)

     The ONUMBER or the REGISTER, but not both, may be omitted.

Preindex
     APC@(NUMBER,REGISTER:SIZE:SCALE)@(ONUMBER)

     The NUMBER may be omitted.  Omitting the REGISTER produces the Postindex addressing mode.

Absolute
     SYMBOL, or DIGITS, optionally followed by :b, :w, or :l.

Motorola Syntax
===============

The standard Motorola syntax for this chip differs from the syntax already discussed (see Syntax).  AS can accept Motorola syntax for operands, even if MIT syntax is used for other operands in the same instruction.  The two kinds of syntax are fully compatible.

In the following table APC stands for any of the address registers (%a0 through %a7), the program counter (%pc), the zero-address relative to the program counter (%zpc), or a suppressed address register (%za0 through %za7).  The use of SIZE means one of w or l, and it may always be omitted along with the leading dot.  The use of SCALE means one of 1, 2, 4, or 8, and it may always be omitted along with the leading asterisk.

The following additional addressing modes are understood:

Address Register Indirect
     (%a0) through (%a7)

     %a7 is also known as %sp, i.e., the Stack Pointer.  %a6 is also known as %fp, the Frame Pointer.

Address Register Postincrement
     (%a0)+ through (%a7)+

Address Register Predecrement
     -(%a0) through -(%a7)

Indirect Plus Offset
     NUMBER(%A0) through NUMBER(%A7), or NUMBER(%PC).

     The NUMBER may also appear within the parentheses, as in (NUMBER,%A0).  When used with the PC, the NUMBER may be omitted (with an address register, omitting the NUMBER produces Address Register Indirect mode).

Index
     NUMBER(APC,REGISTER.SIZE*SCALE)

     The NUMBER may be omitted, or it may appear within the parentheses.  The APC may be omitted.  The REGISTER and the APC may appear in either order.  If both APC and REGISTER are address registers, and the SIZE and SCALE are omitted, then the first register is taken as the base register, and the second as the index register.

Postindex
     ([NUMBER,APC],REGISTER.SIZE*SCALE,ONUMBER)

     The ONUMBER, or the REGISTER, or both, may be omitted. Either the NUMBER or the APC may be omitted, but not both.

Preindex
     ([NUMBER,APC,REGISTER.SIZE*SCALE],ONUMBER)

     The NUMBER, or the APC, or the REGISTER, or any two of them, may be omitted.  The ONUMBER may be omitted.  The REGISTER and the APC may appear in either order.  If both APC and REGISTER are address registers, and the SIZE and SCALE are omitted, then the first register is taken as the base register, and the second as the index register.

Floating Point
==============

Packed decimal (P) format floating literals are not supported. Feel free to add the code!

The floating point formats generated by directives are these.

.float
     Single precision floating point constants.

.double
     Double precision floating point constants.

.extend
.ldouble
     Extended precision (long double) floating point constants.

680x0 Machine Directives
========================

In order to be compatible with the Sun assembler the 680x0 assembler understands the following directives.

.data1
     This directive is identical to a .data 1 directive.

.data2
     This directive is identical to a .data 2 directive.

.even
     This directive is a special case of the .align directive; it aligns the output to an even byte boundary.

.skip
     This directive is identical to a .space directive.

.arch NAME
     Select the target architecture and extension features.  Valid values for NAME are the same as for the -march command-line option.  This directive cannot be specified after any instructions have been assembled.  If it is given multiple times, or in conjunction with the -march option, all uses must be for the same architecture and extension set.

.cpu NAME
     Select the target cpu.  Valid values for NAME are the same as for the -mcpu command-line option.  This directive cannot be specified after any instructions have been assembled.  If it is given multiple times, or in conjunction with the -mopt option, all uses must be for the same cpu.

Opcodes
=======

Branch Improvement
------------------

Certain pseudo opcodes are permitted for branch instructions. They expand to the shortest branch instruction that reach the target.  Generally these mnemonics are made by substituting j for b at the start of a Motorola mnemonic.

The following table summarizes the pseudo-operations.  A * flags cases that are more fully described after the table:

               Displacement
               +------------------------------------------------------------
               |                68020           68000/10, not PC-relative OK
     Pseudo-Op |BYTE    WORD    LONG            ABSOLUTE LONG JUMP    **
               +------------------------------------------------------------
          jbsr |bsrs    bsrw    bsrl            jsr
           jra |bras    braw    bral            jmp
     *     jXX |bXXs    bXXw    bXXl            bNXs;jmp
     *    dbXX | N/A    dbXXw   dbXX;bras;bral  dbXX;bras;jmp
          fjXX | N/A    fbXXw   fbXXl            N/A

     XX: condition
     NX: negative of condition XX

*---see full description below
**---this expansion mode is disallowed by --pcrel

jbsr
jra
     These are the simplest jump pseudo-operations; they always map to one particular machine instruction, depending on the displacement to the branch target.  This instruction will be a byte or word branch is that is sufficient.  Otherwise, a long branch will be emitted if available. If no long branches are available and the --pcrel option is not given, an absolute long jump will be emitted instead.  If no long branches are available, the --pcrel option is given, and a word branch cannot reach the target, an error message is generated.

     In addition to standard branch operands, AS allows these pseudo-operations to have all operands that are allowed for jsr and jmp, substituting these instructions if the operand given is not valid for a branch instruction.

jXX
     Here, jXX stands for an entire family of pseudo-operations, where XX is a conditional branch or condition-code test.  The full list of pseudo-ops in this family is:

           jhi   jls   jcc   jcs   jne   jeq   jvc
           jvs   jpl   jmi   jge   jlt   jgt   jle

     Usually, each of these pseudo-operations expands to a single branch instruction.  However, if a word branch is not sufficient, no long branches are available, and the --pcrel option is not given, AS issues a longer code fragment in terms of NX, the opposite condition to XX.  For example, under these conditions:

              jXX foo

     gives

               bNXs oof
               jmp foo
           oof:

dbXX
     The full family of pseudo-operations covered here is

           dbhi   dbls   dbcc   dbcs   dbne   dbeq   dbvc
           dbvs   dbpl   dbmi   dbge   dblt   dbgt   dble
           dbf    dbra   dbt

     Motorola dbXX instructions allow word displacements only.  When a word displacement is sufficient, each of these pseudo-operations expands to the corresponding Motorola instruction.  When a word displacement is not sufficient and long branches are available, when the source reads dbXX foo, AS emits

               dbXX oo1
               bras oo2
           oo1:bral foo
           oo2:

     If, however, long branches are not available and the --pcrel option is not given, AS emits

               dbXX oo1
               bras oo2
           oo1:jmp foo
           oo2:

fjXX
     This family includes

           fjne   fjeq   fjge   fjlt   fjgt   fjle   fjf
           fjt    fjgl   fjgle  fjnge  fjngl  fjngle fjngt
           fjnle  fjnlt  fjoge  fjogl  fjogt  fjole  fjolt
           fjor   fjseq  fjsf   fjsne  fjst   fjueq  fjuge
           fjugt  fjule  fjult  fjun

     Each of these pseudo-operations always expands to a single Motorola coprocessor branch instruction, word or long.  All Motorola coprocessor branch instructions allow both word and long displacements.

Special Characters
------------------

Line comments are introduced by the | character appearing anywhere on a line, unless the --bitwise-or command-line option has been specified.

An asterisk (*) as the first character on a line marks the start of a line comment as well.

A hash character (#) as the first character on a line also marks the start of a line comment, but in this case it could also be a logical line number directive (see Comments) or a preprocessor control command (see Preprocessing).  If the hash character appears elsewhere on a line it is used to introduce an immediate value.  (This is for compatibility with Sun's assembler).

Multiple statements on the same line can appear if they are separated by the ; character.