D30V Dependent Features
***********************

D30V Options
============

The Mitsubishi D30V version of AS has a few machine dependent options.

-O
     The D30V can often execute two sub-instructions in parallel. When this option is used, AS will attempt to optimize its output by detecting when instructions can be executed in parallel.

-n
     When this option is used, AS will issue a warning every time it adds a nop instruction.

-N
     When this option is used, AS will issue a warning if it needs to insert a nop after a 32-bit multiply before a load or 16-bit multiply instruction.

Syntax
======

The D30V syntax is based on the syntax in Mitsubishi's D30V architecture manual. The differences are detailed below.

Size Modifiers
--------------

The D30V version of AS uses the instruction names in the D30V Architecture Manual.  However, the names in the manual are sometimes ambiguous. There are instruction names that can assemble to a short or long form opcode. How does the assembler pick the correct form?  AS will always pick the smallest form if it can.  When dealing with a symbol that is not defined yet when a line is being assembled, it will always use the long form.  If you need to force the assembler to use either the short or long form of the instruction, you can append either .s (short) or .l (long) to it.  For example, if you are writing an assembly program and you want to do a branch to a symbol that is defined later in your program, you can write bra.s foo. Objdump and GDB will always append .s or .l to instructions which have both short and long forms.

Sub-Instructions
----------------

The D30V assembler takes as input a series of instructions, either one-per-line, or in the special two-per-line format described in the next section.  Some of these instructions will be short-form or sub-instructions.  These sub-instructions can be packed into a single instruction.  The assembler will do this automatically.  It will also detect when it should not pack instructions.  For example, when a label is defined, the next instruction will never be packaged with the previous one.  Whenever a branch and link instruction is called, it will not be packaged with the next instruction so the return address will be valid.  Nops are automatically inserted when necessary.

If you do not want the assembler automatically making these decisions, you can control the packaging and execution type (parallel or sequential) with the special execution symbols described in the next section.

Special Characters
------------------

A semicolon (;) can be used anywhere on a line to start a comment that extends to the end of the line.

If a # appears as the first character of a line, the whole line is treated as a comment, but in this case the line could also be a logical line number directive (see Comments) or a preprocessor control command (see Preprocessing).

Sub-instructions may be executed in order, in reverse-order, or in parallel. Instructions listed in the standard one-per-line format will be executed sequentially unless you use the -O option.

To specify the executing order, use the following symbols:

->
     Sequential with instruction on the left first.

<-
     Sequential with instruction on the right first.

||
     Parallel

The D30V syntax allows either one instruction per line, one instruction per line with the execution symbol, or two instructions per line.  For example

abs r2,r3 -> abs r4,r5
     Execute these sequentially.  The instruction on the right is in the right container and is executed second.

abs r2,r3 <- abs r4,r5
     Execute these reverse-sequentially.  The instruction on the right is in the right container, and is executed first.

abs r2,r3 || abs r4,r5
     Execute these in parallel.

ldw r2,@(r3,r4) ||
mulx r6,r8,r9
     Two-line format. Execute these in parallel.

mulx a0,r8,r9
stw r2,@(r3,r4)
     Two-line format. Execute these sequentially unless -O option is used.  If the -O option is used, the assembler will determine if the instructions could be done in parallel (the above two instructions can be done in parallel), and if so, emit them as parallel instructions. The assembler will put them in the proper containers.  In the above example, the assembler will put the stw instruction in left container and the mulx instruction in the right container.

stw r2,@(r3,r4) ->
mulx a0,r8,r9
     Two-line format.  Execute the stw instruction followed by the mulx instruction sequentially.  The first instruction goes in the left container and the second instruction goes into right container. The assembler will give an error if the machine ordering constraints are violated.

stw r2,@(r3,r4) <-
mulx a0,r8,r9
     Same as previous example, except that the mulx instruction is executed before the stw instruction.

Since $ has no special meaning, you may use it in symbol names.

Guarded Execution
-----------------

AS supports the full range of guarded execution directives for each instruction.  Just append the directive after the instruction proper.  The directives are:

/tx
     Execute the instruction if flag f0 is true.

/fx
     Execute the instruction if flag f0 is false.

/xt
     Execute the instruction if flag f1 is true.

/xf
     Execute the instruction if flag f1 is false.

/tt
     Execute the instruction if both flags f0 and f1 are true.

/tf
     Execute the instruction if flag f0 is true and flag f1 is false.

Register Names
--------------

You can use the predefined symbols r0 through r63 to refer to the D30V registers.  You can also use sp as an alias for r63 and link as an alias for r62.  The accumulators are a0 and a1.

The D30V also has predefined symbols for these control registers and status bits:

psw
     Processor Status Word

bpsw
     Backup Processor Status Word

pc
     Program Counter

bpc
     Backup Program Counter

rpt_c
     Repeat Count

rpt_s
     Repeat Start address

rpt_e
     Repeat End address

mod_s
     Modulo Start address

mod_e
     Modulo End address

iba
     Instruction Break Address

f0
     Flag 0

f1
     Flag 1

f2
     Flag 2

f3
     Flag 3

f4
     Flag 4

f5
     Flag 5

f6
     Flag 6

f7
     Flag 7

s
     Same as flag 4 (saturation flag)

v
     Same as flag 5 (overflow flag)

va
     Same as flag 6 (sticky overflow flag)

c
     Same as flag 7 (carry/borrow flag)

b
     Same as flag 7 (carry/borrow flag)

Addressing Modes
----------------

AS understands the following addressing modes for the D30V. RN in the following refers to any of the numbered registers, but not the control registers.

RN
     Register direct

@RN
     Register indirect

@RN+
     Register indirect with post-increment

@RN-
     Register indirect with post-decrement

@-SP
     Register indirect with pre-decrement

@(DISP, RN)
     Register indirect with displacement

ADDR
     PC relative address (for branch or rep).

#IMM
     Immediate data (the # is optional and ignored)

Floating Point
==============

The D30V has no hardware floating point, but the .float and .double directives generates IEEE floating-point numbers for compatibility with other development tools.

Opcodes
=======

For detailed information on the D30V machine instruction set, see D30V Architecture: A VLIW Microprocessor for Multimedia Applications (Mitsubishi Electric Corp.). AS implements all the standard D30V opcodes.  The only changes are those described in the section on size modifiers