
# error types thrown
from .pyrtlexceptions import PyrtlError
from .pyrtlexceptions import PyrtlInternalError

# core rtl constructs
from .core import LogicNet
from .core import Block
from .core import PostSynthBlock
from .core import working_block
from .core import reset_working_block
from .core import set_working_block
from .core import temp_working_block
from .core import set_debug_mode

# convenience classes for building hardware
from .wire import WireVector
from .wire import Input, Output
from .wire import Const
from .wire import Register

# helper functions
from .helperfuncs import input_list
from .helperfuncs import output_list
from .helperfuncs import register_list
from .helperfuncs import wirevector_list
from .helperfuncs import log2
from .helperfuncs import truncate
from .helperfuncs import match_bitpattern
from .helperfuncs import bitpattern_to_val
from .helperfuncs import chop
from .helperfuncs import val_to_signed_integer
from .helperfuncs import val_to_formatted_str
from .helperfuncs import formatted_str_to_val
from .helperfuncs import infer_val_and_bitwidth
from .helperfuncs import probe
from .helperfuncs import rtl_assert
from .helperfuncs import check_rtl_assertions
from .helperfuncs import find_loop
from .helperfuncs import find_and_print_loop
from .helperfuncs import wire_struct
from .helperfuncs import wire_matrix
from .helperfuncs import one_hot_to_binary
from .helperfuncs import binary_to_one_hot

from .corecircuits import and_all_bits
from .corecircuits import or_all_bits
from .corecircuits import xor_all_bits
from .corecircuits import rtl_any
from .corecircuits import rtl_all
from .corecircuits import mux
from .corecircuits import select
from .corecircuits import concat
from .corecircuits import concat_list
from .corecircuits import parity
from .corecircuits import tree_reduce
from .corecircuits import as_wires
from .corecircuits import match_bitwidth
from .corecircuits import enum_mux
from .corecircuits import bitfield_update
from .corecircuits import bitfield_update_set
from .corecircuits import signed_add
from .corecircuits import signed_sub
from .corecircuits import signed_mult
from .corecircuits import signed_lt
from .corecircuits import signed_le
from .corecircuits import signed_gt
from .corecircuits import signed_ge
from .corecircuits import shift_left_arithmetic
from .corecircuits import shift_right_arithmetic
from .corecircuits import shift_left_logical
from .corecircuits import shift_right_logical

# memory blocks
from .memory import MemBlock
from .memory import RomBlock

# conditional updates
from .conditional import conditional_assignment
from .conditional import otherwise
from .conditional import currently_under_condition

# block simulation support
from .simulation import Simulation
from .simulation import FastSimulation
from .simulation import SimulationTrace
from .simulation import enum_name
from .compilesim import CompiledSimulation

# block visualization output formats
from .visualization import output_to_trivialgraph
from .visualization import graphviz_detailed_namer
from .visualization import output_to_graphviz
from .visualization import output_to_svg
from .visualization import block_to_graphviz_string
from .visualization import block_to_svg
from .visualization import trace_to_html
from .visualization import net_graph

# import from and export to file format routines
from .importexport import input_from_verilog
from .importexport import output_to_verilog
from .importexport import OutputToVerilog
from .importexport import output_verilog_testbench
from .importexport import input_from_blif
from .importexport import output_to_firrtl
from .importexport import input_from_iscas_bench

# different transform passes
from .passes import common_subexp_elimination
from .passes import constant_propagation
from .passes import synthesize
from .passes import nand_synth
from .passes import and_inverter_synth
from .passes import optimize
from .passes import one_bit_selects
from .passes import two_way_concat
from .passes import direct_connect_outputs
from .passes import two_way_fanout

from .transform import net_transform
from .transform import wire_transform
from .transform import copy_block
from .transform import clone_wire
from .transform import replace_wires
from .transform import replace_wire_fast

# analysis and estimation functions
from .analysis import area_estimation
from .analysis import TimingAnalysis
from .analysis import yosys_area_delay
from .analysis import paths
from .analysis import distance
from .analysis import fanout
